Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	cable jz47xx
2	detect
3	instruction CFG_OUT 000100 BYPASS
4	instruction CFG_IN 000101 BYPASS
5	instruction JSTART 001100 BYPASS
6	instruction JPROGRAM 001011 BYPASS
7	pld load /root/FPGA/ADC.bit
8

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