Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	#
2	# $Id$
3
4	register BR 1
5	register BSR 1
6	register DIR 32
7	register EJIMPCODE 32
8	register EJADDRESS 32
9	register EJDATA 32
10	register EJCONTROL 32
11	register EJALL 96
12	register EJFASTDATA 33
13
14	instruction length 5
15
16	instruction BYPASS 11111 BR
17	instruction SAMPLE/PRELOAD 00010 BSR
18	instruction IDCODE 00001 DIR
19	instruction EJTAG_IMPCODE 00011 EJIMPCODE
20	instruction EJTAG_ADDRESS 01000 EJADDRESS
21	instruction EJTAG_DATA 01001 EJDATA
22	instruction EJTAG_CONTROL 01010 EJCONTROL
23	instruction EJTAG_ALL 01011 EJALL
24	instruction EJTAGBOOT 01100 BR
25	instruction NORMALBOOT 01101 BR
26	instruction EJTAG_FASTDATA 01110 EJFASTDATA
27
28	initbus ejtag
29	endian big
30

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