Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	signal TDI 9
2	signal TMS 11
3	signal Gnd_2 12
4	signal TCK 13
5	signal Vcco_1 14
6	signal D4 15
7	signal CF 16
8	signal Reset_OE 19
9	signal D6 31
10	signal CE 21
11	signal Vcco_2 22
12	signal Vcc_1 23
13	signal Gnd_3 24
14	signal D7 25
15	signal CEO 27
16	signal D5 31
17	signal Vcco_3 32
18	signal D3 33
19	signal Gnd_4 34
20	signal D1 35
21	signal TDO 37
22	signal Vpp
23	signal Vcco_4 42
24	signal Vcc_2 41
25	signal D0 2
26	signal Gnd_1 3
27	signal D2 4
28	signal CLK 5
29
30	register BSR 25
31	register BR 1
32	register DIR 32
33
34	instruction length 8
35
36	instruction BYPASS 11111111 BR
37	instruction SAMPLE/PRELOAD 00000001 BSR
38	instruction EXTEST 00000000 BSR
39	instruction IDCODE 11111110 DIR
40
41	bit 24 O 1 D4 23 0 Z
42	bit 23 C 0 *
43	bit 22 O 1 CF 21 0 Z
44	bit 21 C 0 *
45	bit 20 I 1 Reset_OE
46	bit 19 O 1 Reset_OE 18 0 Z
47	bit 18 C 0 *
48	bit 17 O 1 D6 16 0 Z
49	bit 16 C 0 *
50	bit 15 I 1 CE
51	bit 14 O 1 D7 13 0 Z
52	bit 13 C 0 *
53	bit 12 O 1 CEO 11 0 Z
54	bit 11 C 0 *
55	bit 10 O 1 D5 9 0 Z
56	bit 9 C 0 *
57	bit 8 O 1 D3 7 0 Z
58	bit 7 C 0 *
59	bit 6 O 1 D1 5 0 Z
60	bit 5 C 0 *
61	bit 4 O 1 D0 3 0 Z
62	bit 3 C 0 *
63	bit 2 O 1 D2 1 0 Z
64	bit 1 C 0 *
65	bit 0 I 1 CLK
66

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