Hardware Design: SIE
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| 1 | # |
| 2 | # JTAG declarations for XCF04s |
| 3 | # Copyright (C) 2005 |
| 4 | # |
| 5 | # This program is free software; you can redistribute it and/or |
| 6 | # modify it under the terms of the GNU General Public License |
| 7 | # as published by the Free Software Foundation; either version 2 |
| 8 | # of the License, or (at your option) any later version. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| 17 | # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA |
| 18 | # 02111-1307, USA. |
| 19 | # |
| 20 | # Written by Jerome Debard <jdebard@vmetro.no>, 2005. |
| 21 | # |
| 22 | |
| 23 | signal D0 1 |
| 24 | signal NC1 2 |
| 25 | signal CLK 3 |
| 26 | signal TDI 4 |
| 27 | signal TMS 5 |
| 28 | signal TCK 6 |
| 29 | signal CF 7 |
| 30 | signal OE_RESET 8 |
| 31 | signal NC2 9 |
| 32 | signal CE 10 |
| 33 | signal GND 11 |
| 34 | signal NC3 12 |
| 35 | signal CEO 13 |
| 36 | signal NC4 14 |
| 37 | signal NC5 15 |
| 38 | signal NC6 16 |
| 39 | signal TDO 17 |
| 40 | signal VCC 18 |
| 41 | signal VCCO 19 |
| 42 | signal VCCAUX 20 |
| 43 | |
| 44 | |
| 45 | |
| 46 | # mandatory data registers |
| 47 | register BSR 25 |
| 48 | register BR 1 |
| 49 | |
| 50 | # optional data registers |
| 51 | register UCR 32 |
| 52 | |
| 53 | # user-defined registers |
| 54 | |
| 55 | |
| 56 | # instructions |
| 57 | instruction length 8 |
| 58 | |
| 59 | # mandatory instructions |
| 60 | instruction EXTEST 00000000 BSR |
| 61 | instruction SAMPLE/PRELOAD 00000001 BSR |
| 62 | instruction BYPASS 11111111 BR |
| 63 | #instruction INTEST ???????? BSR |
| 64 | instruction IDCODE 11111110 UCR |
| 65 | instruction USERCODE 11111101 UCR |
| 66 | instruction HIGHZ 11111100 BR |
| 67 | instruction CLAMP 11111010 BR |
| 68 | |
| 69 | # user-defined instructions |
| 70 | #instruction ISPEN 11101000 |
| 71 | #instruction ISPENC 11101001 |
| 72 | #instruction FPGM 11101010 |
| 73 | #instruction FADDR 11101011 |
| 74 | #instruction FVFY0 11101111 |
| 75 | #instruction FVFY1 11111000 |
| 76 | #instruction FVFY3 11100010 |
| 77 | #instruction FVFY6 11100110 |
| 78 | #instruction FERASE 11101100 |
| 79 | #instruction SERASE 00001010 |
| 80 | #instruction FDATA0 11101101 |
| 81 | #instruction FDATA3 11110011 |
| 82 | #instruction FBLANK0 11100101 |
| 83 | #instruction FBLANK3 11100001 |
| 84 | #instruction FBLANK6 11100100 |
| 85 | #instruction NORMRST 11110000 |
| 86 | #instruction CONFIG 11101110 |
| 87 | #instruction priv1 11110001 |
| 88 | #instruction ISCTESTSTATUS 11100011 |
| 89 | #instruction priv3 11100111 |
| 90 | #instruction priv4 11110110 |
| 91 | #instruction priv5 11100000 |
| 92 | #instruction priv6 11110111 |
| 93 | #instruction priv7 11110010 |
| 94 | #instruction ISCCLRSTATUS 11110100 |
| 95 | #instruction priv9 11110101 |
| 96 | |
| 97 | |
| 98 | # BSR description |
| 99 | bit 0 I ? CLK |
| 100 | bit 1 X ? . |
| 101 | bit 2 X ? . |
| 102 | bit 3 C ? . |
| 103 | bit 4 O ? D0 3 0 Z |
| 104 | bit 5 X ? . |
| 105 | bit 6 X ? . |
| 106 | bit 7 X ? . |
| 107 | bit 8 X ? . |
| 108 | bit 9 X ? . |
| 109 | bit 10 X ? . |
| 110 | bit 11 C ? . |
| 111 | bit 12 O ? CEO 11 0 Z |
| 112 | bit 13 X ? . |
| 113 | bit 14 X ? . |
| 114 | bit 15 I ? CE |
| 115 | bit 16 X ? . |
| 116 | bit 17 X ? . |
| 117 | bit 18 C ? . |
| 118 | bit 19 O ? OE_RESET 18 0 Z |
| 119 | bit 20 I ? OE_RESET |
| 120 | bit 21 C ? . |
| 121 | bit 22 O ? CF 21 0 Z |
| 122 | bit 23 X ? . |
| 123 | bit 24 X ? . |
| 124 |
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