Date:2013-07-01 20:03:39 (7 years 9 days ago)
Author:Xiangfu
Commit:8dc9141cd305e1468cbb99a8ad1af948ecca590b
Message:add jtag-serial cable, xc3slx16 ucf patches

Files: xc3sprog/patches/0001-add-qi-jtag-serial-cable.patch (1 diff)
xc3sprog/patches/0002-add-xc6slx16-ucf-and-a-Makefile-for-xilinx-tools.patch (1 diff)

Change Details

xc3sprog/patches/0001-add-qi-jtag-serial-cable.patch
1From bbd42d8369343a782317c25c2be933e77956fc26 Mon Sep 17 00:00:00 2001
2From: Xiangfu <xiangfu@openmobilefree.net>
3Date: Mon, 1 Jul 2013 20:19:01 +0800
4Subject: [PATCH 1/2] add qi-jtag-serial cable
5
6---
7 cablelist.txt | 2 ++
8 1 file changed, 2 insertions(+)
9
10diff --git a/cablelist.txt b/cablelist.txt
11index 2d59dda..db37967 100644
12--- a/cablelist.txt
13@@ -6,6 +6,8 @@
14 # Max_Freq == 0 mean use maximum speed of device
15 # Use 1500000 for all cable connected cables and max for all on board cables
16
17+qi ftdi 1500000 0x20b7:0x0713:
18+qijtag ftdi 1500000 0x20b7:0x0713:FTDIJTAG:1:0x00:0x10:0x00:0x00
19 ftdi ftdi 1500000 0x0403:0x6010:
20 minila ftdi 800000 0x0403:0x6010:
21 ft232h ftdi 1500000 0x0403:0x6014:
22--
231.8.1.2
24
xc3sprog/patches/0002-add-xc6slx16-ucf-and-a-Makefile-for-xilinx-tools.patch
1From 1bdad90649f380ba652b6ff522646345c0b575c6 Mon Sep 17 00:00:00 2001
2From: Xiangfu <xiangfu@openmobilefree.net>
3Date: Mon, 1 Jul 2013 20:19:29 +0800
4Subject: [PATCH 2/2] add xc6slx16 ucf and a Makefile for xilinx tools
5
6---
7 bscan_spi/Makefile | 56 ++++++++++++++++++++++++++++++++++++++
8 bscan_spi/bscan_s6_spi_isf_ext.ucf | 4 +++
9 2 files changed, 60 insertions(+)
10 create mode 100644 bscan_spi/Makefile
11 create mode 100644 bscan_spi/bscan_s6_spi_isf_ext.ucf
12
13diff --git a/bscan_spi/Makefile b/bscan_spi/Makefile
14new file mode 100644
15index 0000000..59dad6b
16--- /dev/null
17@@ -0,0 +1,56 @@
18+#
19+# Author: Xiangfu Liu
20+#
21+# This is free and unencumbered software released into the public domain.
22+# For details see the UNLICENSE file at the root of the source tree.
23+#
24+
25+all: bscan_s6_spi_isf_ext.bit
26+
27+# Build for m1
28+#FPGA_TARGET ?= xc6slx45-fgg484-2
29+
30+# Build for mini-slx9 board tqg144/ftg256/csg324
31+#FPGA_TARGET ?= xc6slx9-2-csg324
32+#FPGA_TARGET ?= xc6slx9-2-ftg256
33+FPGA_TARGET ?= xc6slx16-2-ftg256
34+
35+%.bit: %-routed.ncd
36+# -d disables DRC
37+# -b creates rawbits file .rbt
38+# -l creates logic allocation file .ll
39+# -w overwrite existing output file
40+# "-g compress" enables compression
41+ if test -f $<; then bitgen -b -l -w $< $@; fi
42+ mkdir -p bits
43+ cp $@ bits/$(FPGA_TARGET).$@
44+
45+%.ncd: %.xdl
46+ -xdl -xdl2ncd $<
47+
48+%-routed.ncd: %.ncd
49+ par -w $< $@
50+
51+%.ncd: %.ngd
52+ map -w $<
53+
54+%.ngd: %.ucf %.ngc
55+ ngdbuild -uc $< $(@:.ngd=.ngc)
56+
57+%.ngc: %.xst
58+ xst -ifn $<
59+
60+%.xst: %.prj
61+ echo run > $@
62+ echo -ifn $< >> $@
63+ echo -top top >> $@
64+ echo -ifmt MIXED >> $@
65+ echo -opt_mode SPEED >> $@
66+ echo -opt_level 1 >> $@
67+ echo -ofn $(<:.prj=.ngc) >> $@
68+ echo -p $(FPGA_TARGET) >> $@
69+
70+%.prj: %.v
71+ for i in `echo $^`; do \
72+ echo "verilog $(basename $<) $$i" >> $@; \
73+ done
74diff --git a/bscan_spi/bscan_s6_spi_isf_ext.ucf b/bscan_spi/bscan_s6_spi_isf_ext.ucf
75new file mode 100644
76index 0000000..48098cd
77--- /dev/null
78@@ -0,0 +1,4 @@
79+net "MISO" LOC = "P10";
80+net "MOSI" LOC = "T10";
81+net "DRCK1" LOC= "R11";
82+net "CSB" LOC = "T3";
83--
841.8.1.2
85

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