Root/xc3sprog/patches/0002-add-xc6slx16-ucf-and-a-Makefile-for-xilinx-tools.patch

Source at commit 8dc9141cd305e1468cbb99a8ad1af948ecca590b created 6 years 9 months ago.
By Xiangfu, add jtag-serial cable, xc3slx16 ucf patches
1From 1bdad90649f380ba652b6ff522646345c0b575c6 Mon Sep 17 00:00:00 2001
2From: Xiangfu <xiangfu@openmobilefree.net>
3Date: Mon, 1 Jul 2013 20:19:29 +0800
4Subject: [PATCH 2/2] add xc6slx16 ucf and a Makefile for xilinx tools
5
6---
7 bscan_spi/Makefile | 56 ++++++++++++++++++++++++++++++++++++++
8 bscan_spi/bscan_s6_spi_isf_ext.ucf | 4 +++
9 2 files changed, 60 insertions(+)
10 create mode 100644 bscan_spi/Makefile
11 create mode 100644 bscan_spi/bscan_s6_spi_isf_ext.ucf
12
13diff --git a/bscan_spi/Makefile b/bscan_spi/Makefile
14new file mode 100644
15index 0000000..59dad6b
16--- /dev/null
17+++ b/bscan_spi/Makefile
18@@ -0,0 +1,56 @@
19+#
20+# Author: Xiangfu Liu
21+#
22+# This is free and unencumbered software released into the public domain.
23+# For details see the UNLICENSE file at the root of the source tree.
24+#
25+
26+all: bscan_s6_spi_isf_ext.bit
27+
28+# Build for m1
29+#FPGA_TARGET ?= xc6slx45-fgg484-2
30+
31+# Build for mini-slx9 board tqg144/ftg256/csg324
32+#FPGA_TARGET ?= xc6slx9-2-csg324
33+#FPGA_TARGET ?= xc6slx9-2-ftg256
34+FPGA_TARGET ?= xc6slx16-2-ftg256
35+
36+%.bit: %-routed.ncd
37+# -d disables DRC
38+# -b creates rawbits file .rbt
39+# -l creates logic allocation file .ll
40+# -w overwrite existing output file
41+# "-g compress" enables compression
42+ if test -f $<; then bitgen -b -l -w $< $@; fi
43+ mkdir -p bits
44+ cp $@ bits/$(FPGA_TARGET).$@
45+
46+%.ncd: %.xdl
47+ -xdl -xdl2ncd $<
48+
49+%-routed.ncd: %.ncd
50+ par -w $< $@
51+
52+%.ncd: %.ngd
53+ map -w $<
54+
55+%.ngd: %.ucf %.ngc
56+ ngdbuild -uc $< $(@:.ngd=.ngc)
57+
58+%.ngc: %.xst
59+ xst -ifn $<
60+
61+%.xst: %.prj
62+ echo run > $@
63+ echo -ifn $< >> $@
64+ echo -top top >> $@
65+ echo -ifmt MIXED >> $@
66+ echo -opt_mode SPEED >> $@
67+ echo -opt_level 1 >> $@
68+ echo -ofn $(<:.prj=.ngc) >> $@
69+ echo -p $(FPGA_TARGET) >> $@
70+
71+%.prj: %.v
72+ for i in `echo $^`; do \
73+ echo "verilog $(basename $<) $$i" >> $@; \
74+ done
75diff --git a/bscan_spi/bscan_s6_spi_isf_ext.ucf b/bscan_spi/bscan_s6_spi_isf_ext.ucf
76new file mode 100644
77index 0000000..48098cd
78--- /dev/null
79+++ b/bscan_spi/bscan_s6_spi_isf_ext.ucf
80@@ -0,0 +1,4 @@
81+net "MISO" LOC = "P10";
82+net "MOSI" LOC = "T10";
83+net "DRCK1" LOC= "R11";
84+net "CSB" LOC = "T3";
85--
861.8.1.2
87
88

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