Change Details
| target/linux/xburst/files-2.6.31/arch/mips/include/asm/jzsoc.h |
|---|
| 1 | | /* |
| 2 | | * linux/include/asm-mips/jzsoc.h |
| 3 | | * |
| 4 | | * Ingenic's JZXXXX SoC common include. |
| 5 | | * |
| 6 | | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
| 7 | | * |
| 8 | | * Author: <jlwei@ingenic.cn> |
| 9 | | * |
| 10 | | * This program is free software; you can redistribute it and/or modify |
| 11 | | * it under the terms of the GNU General Public License version 2 as |
| 12 | | * published by the Free Software Foundation. |
| 13 | | */ |
| 14 | | |
| 15 | | #ifndef __ASM_JZSOC_H__ |
| 16 | | #define __ASM_JZSOC_H__ |
| 17 | | |
| 18 | | /* |
| 19 | | * SoC include |
| 20 | | */ |
| 21 | | |
| 22 | | #ifdef CONFIG_SOC_JZ4740 |
| 23 | | #include <asm/mach-jz4740/jz4740.h> |
| 24 | | #endif |
| 25 | | |
| 26 | | #endif /* __ASM_JZSOC_H__ */ |
| target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h |
|---|
| 59 | 59 | */ |
| 60 | 60 | #define MSC_WP_PIN GPIO_SD_WP |
| 61 | 61 | #define MSC_HOTPLUG_PIN GPIO_SD_CD_N |
| 62 | | #define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N) |
| 62 | #define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N)) |
| 63 | 63 | |
| 64 | 64 | #define __msc_init_io() \ |
| 65 | 65 | do { \ |
| target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/irq.h |
|---|
| 1 | 1 | #ifndef __JZ4740_IRQ_H__ |
| 2 | 2 | #define __JZ4740_IRQ_H__ |
| 3 | | /* |
| 4 | | * JZ4740 irqs. |
| 5 | | * |
| 6 | | * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de> |
| 7 | | * |
| 8 | | * This program is free software; you can redistribute it and/or modify |
| 9 | | * it under the terms of the GNU General Public License version 2 as |
| 10 | | * published by the Free Software Foundation. |
| 11 | | */ |
| 12 | 3 | |
| 4 | #define MIPS_CPU_IRQ_BASE 0 |
| 13 | 5 | #define JZ_IRQ_BASE 8 |
| 14 | 6 | |
| 15 | 7 | // 1st-level interrupts |
| ... | ... | |
| 39 | 31 | |
| 40 | 32 | /* 2nd-level interrupts */ |
| 41 | 33 | #define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */ |
| 42 | | #define JZ_IRQ_GPIO_0 JZ_IRQ(48) /* 48 to 175 for GPIO pin 0 to 127 */ |
| 43 | 34 | |
| 44 | 35 | #define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x)) |
| 45 | | #define JZ_IRQ_GPIO(x) ((x) + JZ_IRQ(48) |
| 36 | #define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x)) |
| 46 | 37 | |
| 47 | 38 | #define NR_IRQS (JZ_IRQ_GPIO(127) + 1) |
| 48 | 39 | |
Download the corresponding diff file
