Date:2010-07-09 12:03:51 (13 years 5 months ago)
Author:Xiangfu Liu
Commit:5c418bdbf351ed829f18036296c6f23dacb56adc
Message:"[uboot-xburst]-add-n516-sakc-support

only make them compile. not test in device yet.

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
Files: package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/n516/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/n516/config.mk (1 diff)
package/uboot-xburst/files/board/xburst/n516/flash.c (1 diff)
package/uboot-xburst/files/board/xburst/n516/n516.c (1 diff)
package/uboot-xburst/files/board/xburst/n516/u-boot-nand.lds (1 diff)
package/uboot-xburst/files/board/xburst/n516/u-boot.lds (1 diff)
package/uboot-xburst/files/board/xburst/sakc/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/sakc/config.mk (1 diff)
package/uboot-xburst/files/board/xburst/sakc/sakc.c (1 diff)
package/uboot-xburst/files/board/xburst/sakc/u-boot-nand.lds (1 diff)
package/uboot-xburst/files/board/xburst/sakc/u-boot.lds (1 diff)
package/uboot-xburst/files/include/configs/n516.h (1 diff)
package/uboot-xburst/files/include/configs/sakc.h (1 diff)
package/uboot-xburst/patches/009-add-n516.patch (1 diff)
package/uboot-xburst/patches/010-add-sakc.patch (1 diff)

Change Details

package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile
2626LIB = $(obj)lib$(CPU).a
2727
2828START = start.o
29COBJS = cpu.o interrupts.o jz4740.o jz_serial.o
29SOBJS-y =
30COBJS-y = cpu.o interrupts.o jz4740.o jz_serial.o
3031
31COBJS += jz_mmc.o
32COBJS += nanonote_gpm940b0.o
32COBJS-y += jz_mmc.o
33COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
34COBJS-$(CONFIG_SAKC) += nanonote_gpm940b0.o
3335
34SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
35OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
36SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
37OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
3638START := $(addprefix $(obj),$(START))
3739
3840all: $(obj).depend $(START) $(LIB)
package/uboot-xburst/files/board/xburst/n516/Makefile
1#
2# (C) Copyright 2006
3# Ingenic Semiconductor, <jlwei@ingenic.cn>
4#
5# This program is free software; you can redistribute it and/or
6# modify it under the terms of the GNU General Public License as
7# published by the Free Software Foundation; either version 2 of
8# the License, or (at your option) any later version.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
17# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18# MA 02111-1307 USA
19#
20
21include $(TOPDIR)/config.mk
22
23LIB = $(obj)lib$(BOARD).a
24
25COBJS = $(BOARD).o flash.o
26
27OBJS = $(addprefix $(obj),$(COBJS))
28SOBJS =
29
30$(LIB): $(obj).depend $(OBJS) $(SOBJS)
31    $(AR) crv $@ $(OBJS) $(SOBJS)
32
33#########################################################################
34
35# defines $(obj).depend target
36include $(SRCTREE)/rules.mk
37
38sinclude $(obj).depend
39
40#########################################################################
package/uboot-xburst/files/board/xburst/n516/config.mk
1#
2# (C) Copyright 2006
3# Ingenic Semiconductor, <jlwei@ingenic.cn>
4#
5# This program is free software; you can redistribute it and/or
6# modify it under the terms of the GNU General Public License as
7# published by the Free Software Foundation; either version 2 of
8# the License, or (at your option) any later version.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
17# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18# MA 02111-1307 USA
19#
20
21#
22# Hanvon n516 e-book, MIPS32 core
23#
24
25sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
26
27ifndef TEXT_BASE
28# ROM version
29TEXT_BASE = 0x88000000
30
31# RAM version
32#TEXT_BASE = 0x80100000
33endif
package/uboot-xburst/files/board/xburst/n516/flash.c
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22
23flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
24
25/*-----------------------------------------------------------------------
26 * flash_init()
27 *
28 * sets up flash_info and returns size of FLASH (bytes)
29 */
30unsigned long flash_init (void)
31{
32    return (0);
33}
34
35int flash_erase (flash_info_t * info, int s_first, int s_last)
36{
37    printf ("flash_erase not implemented\n");
38    return 0;
39}
40
41void flash_print_info (flash_info_t * info)
42{
43    printf ("flash_print_info not implemented\n");
44}
45
46int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
47{
48    printf ("write_buff not implemented\n");
49    return (-1);
50}
package/uboot-xburst/files/board/xburst/n516/n516.c
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <command.h>
23#include <asm/mipsregs.h>
24#include <asm/jz4740.h>
25#include <asm/addrspace.h>
26#include <asm/cacheops.h>
27
28void _machine_restart(void)
29{
30    __wdt_select_extalclk();
31    __wdt_select_clk_div64();
32    __wdt_set_data(100);
33    __wdt_set_count(0);
34    __tcu_start_wdt_clock();
35    __wdt_start();
36    while(1);
37
38}
39
40static void gpio_init(void)
41{
42
43    REG_GPIO_PXPES(0) = 0xffffffff;
44    REG_GPIO_PXPES(1) = 0xffffffff;
45    REG_GPIO_PXPES(2) = 0xffffffff;
46    REG_GPIO_PXPES(3) = 0xffffffff;
47
48    /*
49     * Initialize NAND Flash Pins
50     */
51    __gpio_as_nand();
52
53    /*
54     * Initialize SDRAM pins
55     */
56    __gpio_as_sdram_32bit();
57
58    /*
59     * Initialize UART0 pins
60     */
61    __gpio_as_uart0();
62
63    /*
64     * Initialize MSC pins
65     */
66    __gpio_as_msc();
67
68    /*
69     * Initialize LCD pins
70     */
71    __gpio_as_lcd_16bit();
72
73    /*
74     * Initialize Other pins
75     */
76    __gpio_as_output(GPIO_SD_VCC_EN_N);
77    __gpio_clear_pin(GPIO_SD_VCC_EN_N);
78
79    __gpio_as_input(GPIO_SD_CD_N);
80    __gpio_disable_pull(GPIO_SD_CD_N);
81
82    __gpio_as_output(GPIO_DISP_OFF_N);
83
84    __gpio_as_output(GPIO_LED_EN);
85    __gpio_set_pin(GPIO_LED_EN);
86
87    __gpio_as_input(127);
88}
89
90static void cpm_init(void)
91{
92    __cpm_stop_ipu();
93    __cpm_stop_cim();
94    __cpm_stop_i2c();
95    __cpm_stop_ssi();
96    __cpm_stop_uart1();
97    __cpm_stop_sadc();
98    __cpm_stop_uhc();
99    __cpm_stop_udc();
100    __cpm_stop_aic1();
101    __cpm_stop_aic2();
102    __cpm_suspend_udcphy();
103    __cpm_suspend_usbphy();
104}
105
106//----------------------------------------------------------------------
107// board early init routine
108
109void board_early_init(void)
110{
111    gpio_init();
112    cpm_init();
113}
114
115//----------------------------------------------------------------------
116// U-Boot common routines
117
118int checkboard (void)
119{
120    DECLARE_GLOBAL_DATA_PTR;
121
122    printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
123           gd->cpu_clk/1000000);
124
125    return 0; /* success */
126}
package/uboot-xburst/files/board/xburst/n516/u-boot-nand.lds
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
22
23OUTPUT_ARCH(mips)
24ENTRY(_start)
25SECTIONS
26{
27    . = 0x00000000;
28
29    . = ALIGN(4);
30    .text :
31    {
32      *(.text)
33    }
34
35    . = ALIGN(4);
36    .rodata : { *(.rodata) }
37
38    . = ALIGN(4);
39    .data : { *(.data) }
40
41    . = ALIGN(4);
42    .sdata : { *(.sdata) }
43
44    _gp = ALIGN(16);
45
46    __got_start = .;
47    .got : { *(.got) }
48    __got_end = .;
49
50    .sdata : { *(.sdata) }
51
52    __u_boot_cmd_start = .;
53    .u_boot_cmd : { *(.u_boot_cmd) }
54    __u_boot_cmd_end = .;
55
56    uboot_end_data = .;
57    num_got_entries = (__got_end - __got_start) >> 2;
58
59    . = ALIGN(4);
60    .sbss : { *(.sbss) }
61    .bss : { *(.bss) }
62    uboot_end = .;
63}
package/uboot-xburst/files/board/xburst/n516/u-boot.lds
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
22
23OUTPUT_ARCH(mips)
24ENTRY(_start)
25SECTIONS
26{
27    . = 0x00000000;
28
29    . = ALIGN(4);
30    .text :
31    {
32      *(.text)
33    }
34
35    . = ALIGN(4);
36    .rodata : { *(.rodata) }
37
38    . = ALIGN(4);
39    .data : { *(.data) }
40
41    . = ALIGN(4);
42    .sdata : { *(.sdata) }
43
44    _gp = ALIGN(16);
45
46    __got_start = .;
47    .got : { *(.got) }
48    __got_end = .;
49
50    .sdata : { *(.sdata) }
51
52    __u_boot_cmd_start = .;
53    .u_boot_cmd : { *(.u_boot_cmd) }
54    __u_boot_cmd_end = .;
55
56    uboot_end_data = .;
57    num_got_entries = (__got_end - __got_start) >> 2;
58
59    . = ALIGN(4);
60    .sbss : { *(.sbss) }
61    .bss : { *(.bss) }
62    uboot_end = .;
63}
package/uboot-xburst/files/board/xburst/sakc/Makefile
1#
2# (C) Copyright 2006
3# Ingenic Semiconductor, <jlwei@ingenic.cn>
4#
5# This program is free software; you can redistribute it and/or
6# modify it under the terms of the GNU General Public License as
7# published by the Free Software Foundation; either version 2 of
8# the License, or (at your option) any later version.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
17# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18# MA 02111-1307 USA
19#
20
21include $(TOPDIR)/config.mk
22
23LIB = lib$(BOARD).a
24
25OBJS = $(BOARD).o
26SOBJS =
27
28$(LIB): .depend $(OBJS) $(SOBJS)
29    $(AR) crv $@ $(OBJS) $(SOBJS)
30
31#########################################################################
32
33# defines $(obj).depend target
34include $(SRCTREE)/rules.mk
35
36sinclude .depend
37
38#########################################################################
package/uboot-xburst/files/board/xburst/sakc/config.mk
1#
2# (C) Copyright 2006 Qi Hardware, Inc.
3# Author: Xiangfu Liu <xiangfu.z@gmail.com>
4#
5# This program is free software; you can redistribute it and/or
6# modify it under the terms of the GNU General Public License as
7# published by the Free Software Foundation; either version 2 of
8# the License, or (at your option) any later version.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
17# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18# MA 02111-1307 USA
19#
20
21#
22# SAKC Board
23#
24
25ifndef TEXT_BASE
26# ROM version
27# TEXT_BASE = 0x88000000
28
29# RAM version
30TEXT_BASE = 0x80100000
31endif
package/uboot-xburst/files/board/xburst/sakc/sakc.c
1/*
2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
8 */
9
10#include <common.h>
11#include <command.h>
12#include <asm/mipsregs.h>
13#include <asm/jz4740.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17static void gpio_init(void)
18{
19    /*
20     * Initialize NAND Flash Pins
21     */
22    __gpio_as_nand();
23
24    /*
25     * Initialize SDRAM pins
26     */
27    __gpio_as_sdram_16bit_4725();
28
29    /*
30     * Initialize UART0 pins
31     */
32    __gpio_as_uart0();
33
34    /*
35     * Initialize LCD pins
36     */
37    __gpio_as_lcd_18bit();
38
39    /*
40     * Initialize MSC pins
41     */
42    __gpio_as_msc();
43
44    /*
45     * Initialize SSI pins
46     */
47    __gpio_as_ssi();
48
49    /*
50     * Initialize I2C pins
51     */
52    __gpio_as_i2c();
53
54    /*
55     * Initialize MSC pins
56     */
57    __gpio_as_msc();
58
59    /*
60     * Initialize Other pins
61     */
62    __gpio_as_input(GPIO_SD_DETECT);
63    __gpio_disable_pull(GPIO_SD_DETECT);
64}
65/* TODO SAKC
66static void cpm_init(void)
67{
68    __cpm_stop_ipu();
69    __cpm_stop_cim();
70    __cpm_stop_i2c();
71    __cpm_stop_ssi();
72    __cpm_stop_uart1();
73    __cpm_stop_sadc();
74    __cpm_stop_uhc();
75    __cpm_stop_aic1();
76    __cpm_stop_aic2();
77}*/
78
79void board_early_init(void)
80{
81    gpio_init();
82    //cpm_init(); //TODO SAKC
83}
84
85/* U-Boot common routines */
86
87int checkboard (void)
88{
89
90    printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
91           gd->cpu_clk/1000000);
92
93    return 0; /* success */
94}
package/uboot-xburst/files/board/xburst/sakc/u-boot-nand.lds
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
22
23OUTPUT_ARCH(mips)
24ENTRY(_start)
25SECTIONS
26{
27    . = 0x00000000;
28
29    . = ALIGN(4);
30    .text :
31    {
32      *(.text)
33    }
34
35    . = ALIGN(4);
36    .rodata : { *(.rodata) }
37
38    . = ALIGN(4);
39    .data : { *(.data) }
40
41    . = ALIGN(4);
42    .sdata : { *(.sdata) }
43
44    _gp = ALIGN(16);
45
46    __got_start = .;
47    .got : { *(.got) }
48    __got_end = .;
49
50    .sdata : { *(.sdata) }
51
52    __u_boot_cmd_start = .;
53    .u_boot_cmd : { *(.u_boot_cmd) }
54    __u_boot_cmd_end = .;
55
56    uboot_end_data = .;
57    num_got_entries = (__got_end - __got_start) >> 2;
58
59    . = ALIGN(4);
60    .sbss : { *(.sbss) }
61    .bss : { *(.bss) }
62    uboot_end = .;
63}
package/uboot-xburst/files/board/xburst/sakc/u-boot.lds
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
22
23OUTPUT_ARCH(mips)
24ENTRY(_start)
25SECTIONS
26{
27    . = 0x00000000;
28
29    . = ALIGN(4);
30    .text :
31    {
32      *(.text)
33    }
34
35    . = ALIGN(4);
36    .rodata : { *(.rodata) }
37
38    . = ALIGN(4);
39    .data : { *(.data) }
40
41    . = ALIGN(4);
42    .sdata : { *(.sdata) }
43
44    _gp = ALIGN(16);
45
46    __got_start = .;
47    .got : { *(.got) }
48    __got_end = .;
49
50    .sdata : { *(.sdata) }
51
52    __u_boot_cmd_start = .;
53    .u_boot_cmd : { *(.u_boot_cmd) }
54    __u_boot_cmd_end = .;
55
56    uboot_end_data = .;
57    num_got_entries = (__got_end - __got_start) >> 2;
58
59    . = ALIGN(4);
60    .sbss : { *(.sbss) }
61    .bss : { *(.bss) }
62    uboot_end = .;
63}
package/uboot-xburst/files/include/configs/n516.h
1/*
2 * (C) Copyright 2006
3 * Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/*
22 * This file contains the configuration parameters for the pavo board.
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28//#define DEBUG
29//#define DEBUG_SHELL
30
31#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32#define CONFIG_JzRISC 1 /* JzRISC core */
33#define CONFIG_JZSOC 1 /* Jz SoC */
34#define CONFIG_JZ4740 1 /* Jz4740 SoC */
35#define CONFIG_PAVO 1 /* PAVO validation board */
36#define CONFIG_NAND_JZ4740
37
38#define CONFIG_BOARD_NAME "n516"
39#define CONFIG_BOARD_HWREV "1.0"
40#define CONFIG_FIRMWARE_EPOCH "0"
41#define CONFIG_UPDATE_TMPBUF 0x80600000
42#define CONFIG_UPDATE_CHUNKSIZE 0x800000
43#define CONFIG_UPDATE_FILENAME "update.oifw"
44#define CONFIG_UPDATE_FILEEXT ".oifw"
45#define CONFIG_UBI_PARTITION "UBI"
46
47#define CONFIG_SKIP_LOWLEVEL_INIT 1
48#undef CONFIG_SKIP_RELOCATE_UBOOT
49
50#if 0
51#define CONFIG_LCD /* LCD support */
52#define CONFIG_JZLCD_METRONOME_800x600
53#define LCD_BPP LCD_COLOR8
54
55#define WFM_DATA_SIZE ( 1 << 14 )
56#define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
57#define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
58#define BMP_LOGO_HEIGHT 0
59#define CONFIG_UBI_WF_VOLUME "waveforms"
60#define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
61#define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
62#endif
63
64#if 0
65#define CONFIG_JZSOC_I2C
66#define CONFIG_HARD_I2C
67#define CONFIG_SYS_I2C_SPEED 100000
68#define CONFIG_SYS_I2C_SLAVE 0
69#define CONFIG_LPC_I2C_ADDR 0x54
70#endif
71
72#define JZ4740_NORBOOT_CFG JZ4740_NORBOOT_16BIT /* NOR Boot config code */
73#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
74
75#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
76#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
77#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL/256) /* incrementer freq */
78
79#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
80
81#define CONFIG_BAUDRATE 57600
82#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
83
84
85#define CONFIG_MMC 1
86#define CONFIG_GENERIC_MMC 1
87#define CONFIG_JZ_MMC 1
88#define CONFIG_FAT 1
89
90#define CONFIG_SYS_HUSH_PARSER
91#define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
92#define CONFIG_CMDLINE_EDITING
93
94/* allow to overwrite serial and ethaddr */
95#define CONFIG_ENV_OVERWRITE
96
97#include <config_cmd_default.h>
98
99#undef CONFIG_CMD_BDI /* bdinfo */
100#undef CONFIG_CMD_FPGA
101#undef CONFIG_CMD_ECHO /* echo arguments */
102#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
103#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
104#undef CONFIG_CMD_IMI /* iminfo */
105#undef CONFIG_CMD_ITEST /* Integer (and string) test */
106#undef CONFIG_CMD_LOADB /* loadb */
107#undef CONFIG_CMD_LOADS /* loads */
108#undef CONFIG_CMD_NFS /* NFS support */
109#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
110#undef CONFIG_CMD_SOURCE /* "source" command support */
111#undef CONFIG_CMD_XIMG /* Load part of Multi Image */
112#undef CONFIG_CMD_NET
113
114//#define CONFIG_CMD_ASKENV
115//#define CONFIG_CMD_DHCP
116//#define CONFIG_CMD_PING
117#define CONFIG_CMD_NAND
118#define CONFIG_CMD_MMC
119#define CONFIG_CMD_FAT
120/*#define CONFIG_CMD_UBI*/
121/*#define CONFIG_CMD_MTDPARTS*/
122//#define CONFIG_CMD_JFFS2
123//#define CONFIG_JFFS2_NAND
124//#define CONFIG_JFFS2_CMDLINE
125#define CONFIG_CMD_UPDATE
126
127#define CONFIG_DOS_PARTITION
128
129/*#define CONFIG_MTD_PARTITIONS*/
130#define CONFIG_RBTREE
131
132/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
133#if 0
134#define CONFIG_ZERO_BOOTDELAY_CHECK
135#define CONFIG_BOOTDELAY 0
136#define CONFIG_BOOTFILE uImage /* file to load */
137#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
138#define CONFIG_BOOTCOMMAND "check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
139#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
140#define CONFIG_IPADDR 192.168.111.1
141#define CONFIG_SERVERIP 192.168.111.2
142#define MTDIDS_DEFAULT "nand0=jz4740-nand"
143#define MTDPARTS_DEFAULT "mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
144#define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
145                "stdout=serial\0stderr=lcd\0"
146#endif
147
148#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
149#define CONFIG_BOOTDELAY 0
150#define CONFIG_BOOTFILE "uImage" /* file to load */
151#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
152#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
153
154
155
156#define CONFIG_SYS_CONSOLE_IS_IN_ENV
157
158/*
159 * Serial download configuration
160 *
161 */
162#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
163#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
164
165/*
166 * Miscellaneous configurable options
167 */
168#define CONFIG_SYS_LONGHELP /* undef to save memory */
169#define CONFIG_SYS_PROMPT "n516 # " /* Monitor Command Prompt */
170#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
172#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
173
174#define CONFIG_SYS_MALLOC_LEN 1024*1024*2
175#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
176
177#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
178
179#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
180
181#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
182
183#define CONFIG_SYS_MEMTEST_START 0x80100000
184#define CONFIG_SYS_MEMTEST_END 0x80800000
185
186/*-----------------------------------------------------------------------
187 * Environment
188 *----------------------------------------------------------------------*/
189#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
190#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
191#else
192#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
193#endif
194
195/*-----------------------------------------------------------------------
196 * NAND FLASH configuration
197 */
198#define CONFIG_SYS_MAX_NAND_DEVICE 1
199#define NAND_MAX_CHIPS 1
200#define CONFIG_SYS_NAND_BASE 0xB8000000
201#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
202
203
204/*
205 * IPL (Initial Program Loader, integrated inside CPU)
206 * Will load first 8k from NAND (SPL) into cache and execute it from there.
207 *
208 * SPL (Secondary Program Loader)
209 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
210 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
211 * controller and the NAND controller so that the special U-Boot image can be
212 * loaded from NAND to SDRAM.
213 *
214 * NUB (NAND U-Boot)
215 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
216 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
217 *
218 */
219#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
220#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
221
222/*
223 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
224 */
225#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
226#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
227
228#define CONFIG_SYS_NAND_PAGE_SIZE 2048
229#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
230#define CONFIG_SYS_NAND_BADBLOCK_PAGE 63 /* NAND bad block was marked at this page in a block, starting from 0 */
231#define CONFIG_SYS_NAND_ECC_POS 6
232#define CONFIG_SYS_NAND_ECCSIZE 512
233#define CONFIG_SYS_NAND_ECCBYTES 9
234
235
236#ifdef CONFIG_ENV_IS_IN_NAND
237//#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
238#define CONFIG_ENV_SIZE (128 * 1024)
239//#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) /* environment starts here */
240#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
241//#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
242#endif
243
244
245/*-----------------------------------------------------------------------
246 * NOR FLASH and environment organization
247 */
248#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
249#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
250
251#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
252
253/* The following #defines are needed to get flash environment right */
254#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
255#define CONFIG_SYS_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
256#define CONFIG_SYS_MONITOR_LEN (256*1024) /* Reserve 256 kB for Monitor */
257
258#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
259
260/* timeout values are in ticks */
261#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
262#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
263
264#ifdef CONFIG_ENV_IS_IN_FLASH
265#define CONFIG_ENV_IS_NOWHERE 1
266#define CONFIG_ENV_ADDR 0xa8040000
267#define CONFIG_ENV_SIZE 0x20000
268#endif
269
270/*-----------------------------------------------------------------------
271 * SDRAM Info.
272 */
273#define CONFIG_NR_DRAM_BANKS 1
274
275// SDRAM paramters
276#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
277#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
278#define SDRAM_ROW 13 /* Row address: 11 to 13 */
279#define SDRAM_COL 9 /* Column address: 8 to 12 */
280#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
281
282// SDRAM Timings, unit: ns
283#define SDRAM_TRAS 45 /* RAS# Active Time */
284#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
285#define SDRAM_TPC 20 /* RAS# Precharge Time */
286#define SDRAM_TRWL 7 /* Write Latency Time */
287#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
288
289/*-----------------------------------------------------------------------
290 * Cache Configuration
291 */
292#define CONFIG_SYS_DCACHE_SIZE 16384
293#define CONFIG_SYS_ICACHE_SIZE 16384
294#define CONFIG_SYS_CACHELINE_SIZE 32
295
296/*-----------------------------------------------------------------------
297 * GPIO definition
298 */
299#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
300#define GPIO_SD_CD_N 103 /* GPD7 */
301#define GPIO_SD_WP 111 /* GPD15 */
302#define GPIO_USB_DETE 115 /* GPD6 */
303//#define GPIO_DC_DETE_N 103 /* GPD7 */
304#define GPIO_CHARG_STAT_N 112 /* GPD15 */
305#define GPIO_DISP_OFF_N 97 /* GPD1 */
306#define GPIO_UDC_HOTPLUG 100 /* GPD4 */
307#define GPIO_LED_EN 124 /* GPD28 */
308
309#define GPIO_RST_L 50 /* GPB18 LCD_SPL */
310#define GPIO_LCDRDY 49 /* GPB17 LCD_CLS */
311#define GPIO_STBY 86 /* GPC22 LCD_PS */
312#define GPIO_ERR 87 /* GPC23 LCD_REV */
313
314#endif /* __CONFIG_H */
package/uboot-xburst/files/include/configs/sakc.h
1/*
2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
8 */
9
10/*
11 * This file contains the configuration parameters for SAKC.
12 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define DEBUG
17#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
18#define CONFIG_JzRISC 1 /* JzRISC core */
19#define CONFIG_JZSOC 1 /* Jz SoC */
20#define CONFIG_JZ4740 1 /* Jz4740 SoC */
21#define CONFIG_SAKC 1 /* SAKC board */
22#define CONFIG_NANONOTE
23#define CONFIG_NAND_JZ4740
24
25#define BOOT_FROM_SDCARD 1
26#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
27
28#define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */
29
30//#define CONFIG_LCD 1 /* LCD support */
31//#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
32//#define CONFIG_SYS_WHITE_ON_BLACK 1
33
34#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
35#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
36#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
37#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
38
39#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
40#define CONFIG_BAUDRATE 57600
41#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
42
43#define CONFIG_MMC 1
44#define CONFIG_FAT 1
45#define CONFIG_DOS_PARTITION 1
46#define CONFIG_SKIP_LOWLEVEL_INIT 1
47#define CONFIG_BOARD_EARLY_INIT_F 1
48#define CONFIG_SYS_NO_FLASH 1
49#define CONFIG_ENV_OVERWRITE 1
50
51#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
52#define CONFIG_BOOTDELAY 3
53#define CONFIG_BOOTFILE "uImage" /* file to load */
54#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
55
56#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
57#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
58
59/*
60 * Command line configuration.
61 */
62#define CONFIG_CMD_BDI /* bdinfo */
63#define CONFIG_CMD_BOOTD /* bootd */
64#define CONFIG_CMD_CONSOLE /* coninfo */
65#define CONFIG_CMD_ECHO /* echo arguments */
66#define CONFIG_CMD_IMI /* iminfo */
67#define CONFIG_CMD_ITEST /* Integer (and string) test */
68
69#define CONFIG_CMD_LOADB /* loadb */
70#define CONFIG_CMD_LOADS /* loads */
71#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
72#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
73#define CONFIG_CMD_RUN /* run command in env variable */
74#define CONFIG_CMD_SAVEENV /* saveenv */
75#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
76#define CONFIG_CMD_SOURCE /* "source" command support */
77#define CONFIG_CMD_XIMG /* Load part of Multi Image */
78
79#define CONFIG_CMD_NAND
80#define CONFIG_CMD_MMC
81#define CONFIG_CMD_FAT
82
83/*
84 * Serial download configuration
85 */
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
88
89/*
90 * Miscellaneous configurable options
91 */
92#define CONFIG_SYS_LONGHELP /* undef to save memory */
93#define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */
94#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
95#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
96/* Print Buffer Size */
97#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
98
99#define CONFIG_SYS_MALLOC_LEN 128 * 1024
100#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
101
102#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
103#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
104#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
105#define CONFIG_SYS_MEMTEST_START 0x80100000
106#define CONFIG_SYS_MEMTEST_END 0x80800000
107
108/*
109 * Environment
110 */
111#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
112
113/*
114 * NAND FLASH configuration
115 */
116/* NAND Boot config code */
117#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
118
119#define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1
120                   * if board nand flash is 2GB, set to 2
121                   * for change the PAGE_SIZE and BLOCK_SIZE
122                   * will delete when there is no 1GB flash
123                   */
124
125#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE)
126/* nand chip block size */
127#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10)
128/* nand bad block was marked at this page in a block, start from 0 */
129#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
130/* ECC offset position in oob area, default value is 6 if it isn't defined */
131#define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE)
132#define CONFIG_SYS_NAND_ECCSIZE 512
133#define CONFIG_SYS_NAND_ECCBYTES 9
134
135#define CONFIG_SYS_MAX_NAND_DEVICE 1
136#define NAND_MAX_CHIPS 1
137#define CONFIG_SYS_NAND_BASE 0xB8000000
138#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
139#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
140
141/*
142 * IPL (Initial Program Loader, integrated inside CPU)
143 * Will load first 8k from NAND (SPL) into cache and execute it from there.
144 *
145 * SPL (Secondary Program Loader)
146 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
147 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
148 * controller and the NAND controller so that the special U-Boot image can be
149 * loaded from NAND to SDRAM.
150 *
151 * NUB (NAND U-Boot)
152 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
153 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
154 *
155 */
156#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
157#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
158/* Start NUB from this addr*/
159
160/*
161 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
162 */
163#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
164#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
165
166#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
167#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
168/* environment starts here */
169#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
170
171/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
172#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
173
174/*
175 * SDRAM Info.
176 */
177#define CONFIG_NR_DRAM_BANKS 1
178
179/* SDRAM paramters */
180#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
181#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
182#define SDRAM_ROW 13 /* Row address: 11 to 13 */
183#define SDRAM_COL 9 /* Column address: 8 to 12 */
184#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
185
186/* SDRAM Timings, unit: ns */
187#define SDRAM_TRAS 45 /* RAS# Active Time */
188#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
189#define SDRAM_TPC 20 /* RAS# Precharge Time */
190#define SDRAM_TRWL 7 /* Write Latency Time */
191#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
192
193/*
194 * Cache Configuration
195 */
196#define CONFIG_SYS_DCACHE_SIZE 16384
197#define CONFIG_SYS_ICACHE_SIZE 16384
198#define CONFIG_SYS_CACHELINE_SIZE 32
199
200/*
201 * GPIO definition
202 */
203#define GPIO_SD_DETECT (2 * 32 + 27)
204#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
205#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
206
207#endif /* __CONFIG_H */
package/uboot-xburst/patches/009-add-n516.patch
1diff --git a/Makefile b/Makefile
2index 4ebdb74..5efac12 100644
3--- a/Makefile
4@@ -2315,6 +2315,18 @@ qi_lb60_config : unconfig
5     @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/nanonote/config.tmp
6     @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
7
8+n516_config : unconfig
9+ @ >include/config.h
10+ @echo "#define CONFIG_N516 1" >>include/config.h
11+ @$(MKCONFIG) -a n516 mips xburst n516 xburst
12+
13+n516_nand_config: unconfig
14+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
15+ @echo "Compile NAND boot image for n516"
16+ @$(MKCONFIG) -a n516 mips xburst n516 xburst
17+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/n516/config.tmp
18+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
19+
20 #========================================================================
21 # Nios
22 #========================================================================
package/uboot-xburst/patches/010-add-sakc.patch
1diff --git a/Makefile b/Makefile
2index d71ea8e..8a36045 100644
3--- a/Makefile
4@@ -2327,6 +2327,13 @@ n516_nand_config: unconfig
5     @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/n516/config.tmp
6     @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
7
8+sakc_config : unconfig
9+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
10+ @echo "Compile NAND boot image for SAKC"
11+ @$(MKCONFIG) -a sakc mips xburst sakc xburst
12+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/sakc/config.tmp
13+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
14+
15 #========================================================================
16 # Nios
17 #========================================================================

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