Date:2010-01-11 02:13:22 (3 years 4 months ago)
Author:Lars C.
Commit:5c8c909c7587ef1ecd1f9cf6f62379d3eb13e99e
Message:jz4740-sound: Replace i2s driver.
Files: target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-i2s.c (1 diff)
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-i2s.h (1 diff)
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-pcm.c (7 diffs)
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-pcm.h (1 diff)

Change Details

target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-i2s.c
11/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
57 * option) any later version.
68 *
7 * Jiejing Zhang(kzjeef(at)gmail.com) 2009: Make jz soc sound card
8 * loaded by soc-core.
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
913 */
1014
11#include <linux/init.h>
15#include <linux/kernel.h>
1216#include <linux/module.h>
13#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
1422#include <linux/delay.h>
23
1524#include <sound/core.h>
1625#include <sound/pcm.h>
1726#include <sound/pcm_params.h>
18#include <sound/initval.h>
1927#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
2030
21#include <asm/mach-jz4740/regs.h>
22#include <asm/mach-jz4740/ops.h>
23
24#include "jz4740-pcm.h"
2531#include "jz4740-i2s.h"
32#include "jz4740-pcm.h"
33
34#define JZ_REG_AIC_CONF 0x00
35#define JZ_REG_AIC_CTRL 0x04
36#define JZ_REG_AIC_I2S_FMT 0x10
37#define JZ_REG_AIC_FIFO_STATUS 0x14
38#define JZ_REG_AIC_I2S_STATUS 0x1c
39#define JZ_REG_AIC_CLK_DIV 0x30
40#define JZ_REG_AIC_FIFO 0x34
41
42#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
43#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
44#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
45#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
46#define JZ_AIC_CONF_I2S BIT(4)
47#define JZ_AIC_CONF_RESET BIT(3)
48#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
49#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
50#define JZ_AIC_CONF_ENABLE BIT(0)
51
52#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
53#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
54
55#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
56#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
57#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
58#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
59#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
60#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
61#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
62#define JZ_AIC_CTRL_FLUSH BIT(8)
63#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
64#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
65#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
66#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
67#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
68#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
69#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
70
71#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
72#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
73
74#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
75#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
76#define JZ_AIC_I2S_FMT_MSB BIT(0)
77
78#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
79
80#define JZ_AIC_CLK_DIV_MASK 0xf
81
82struct jz4740_i2s {
83    struct resource *mem;
84    void __iomem *base;
85    dma_addr_t phys_base;
86
87    struct clk *clk;
88
89    struct jz4740_pcm_config pcm_config;
90};
2691
27static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
92static struct jz4740_dma_config jz4740_i2s_dma_playback_config = {
93    .src_width = JZ4740_DMA_WIDTH_16BIT,
94    .dst_width = JZ4740_DMA_WIDTH_32BIT,
95    .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
96    .request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
97    .flags = JZ4740_DMA_SRC_AUTOINC,
98    .mode = JZ4740_DMA_MODE_SINGLE,
99};
100
101static struct jz4740_dma_config jz4740_i2s_dma_capture_config = {
102    .src_width = JZ4740_DMA_WIDTH_32BIT,
103    .dst_width = JZ4740_DMA_WIDTH_16BIT,
104    .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
105    .request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
106    .flags = JZ4740_DMA_DST_AUTOINC,
107    .mode = JZ4740_DMA_MODE_SINGLE,
108};
109
110
111static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, unsigned int reg)
28112{
29    /*struct snd_soc_pcm_runtime *rtd = substream->private_data;
30      struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;*/
113    return readl(i2s->base + reg);
114}
31115
32    return 0;
116static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, unsigned
117int reg, uint32_t value)
118{
119    writel(value, i2s->base + reg);
33120}
34121
35static int jz4740_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
36        unsigned int fmt)
122static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
37123{
38    /* interface format */
39    switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
40    case SND_SOC_DAIFMT_I2S:
41        /* 1 : ac97 , 0 : i2s */
42        break;
43    case SND_SOC_DAIFMT_LEFT_J:
44        break;
45    default:
46        return -EINVAL;
47    }
124    return dai->private_data;
125}
126
127static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct
128                              snd_soc_dai *dai)
129{
130    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
131    uint32_t conf, ctrl;
132
133    if (dai->active)
134        return 0;
135
136    conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
137    ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
138
139    conf |= JZ_AIC_CONF_ENABLE;
140    ctrl |= JZ_AIC_CTRL_FLUSH;
141
142
143    jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
144    clk_enable(i2s->clk);
145    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
48146
49    switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
50    case SND_SOC_DAIFMT_CBS_CFS:
51            /* 0 : slave */
52        break;
53    case SND_SOC_DAIFMT_CBM_CFS:
54        /* 1 : master */
55        break;
56    default:
57        break;
58    }
59
60147    return 0;
61148}
62149
63/*
64* Set Jz4740 Clock source
65*/
66static int jz4740_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
67        int clk_id, unsigned int freq, int dir)
150static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct
151                              snd_soc_dai *dai)
68152{
69    return 0;
153    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
154    uint32_t conf;
155
156    if (dai->active)
157        return;
158
159    conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
160    conf &= ~JZ_AIC_CONF_ENABLE;
161    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
162
163    clk_disable(i2s->clk);
70164}
71165
72static void jz4740_snd_tx_ctrl(int on)
166
167static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
168                   struct snd_soc_dai *dai)
73169{
74    if (on) {
75                /* enable replay */
76            __i2s_enable_transmit_dma();
77        __i2s_enable_replay();
78        __i2s_enable();
170    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
171    bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
79172
173    uint32_t ctrl;
174    uint32_t mask;
175
176    if (playback) {
177        mask = JZ_AIC_CTRL_ENABLE_PLAYBACK |
178               JZ_AIC_CTRL_ENABLE_TX_DMA;
80179    } else {
81        /* disable replay & capture */
82        __i2s_disable_replay();
83        __i2s_disable_record();
84        __i2s_disable_receive_dma();
85        __i2s_disable_transmit_dma();
86        __i2s_disable();
180        mask = JZ_AIC_CTRL_ENABLE_CAPTURE |
181               JZ_AIC_CTRL_ENABLE_RX_DMA;
87182    }
183
184    ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
185
186    switch (cmd) {
187    case SNDRV_PCM_TRIGGER_START:
188    case SNDRV_PCM_TRIGGER_RESUME:
189    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
190        ctrl |= mask;
191        break;
192    case SNDRV_PCM_TRIGGER_STOP:
193    case SNDRV_PCM_TRIGGER_SUSPEND:
194    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
195        ctrl &= ~mask;
196        break;
197    default:
198        return -EINVAL;
199    }
200
201    jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL,ctrl);
202
203    return 0;
88204}
89205
90static void jz4740_snd_rx_ctrl(int on)
206
207static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai,
208                   unsigned int fmt)
91209{
92    if (on) {
93                /* enable capture */
94        __i2s_enable_receive_dma();
95        __i2s_enable_record();
96        __i2s_enable();
97
98    } else {
99                /* disable replay & capture */
100        __i2s_disable_replay();
101        __i2s_disable_record();
102        __i2s_disable_receive_dma();
103        __i2s_disable_transmit_dma();
104        __i2s_disable();
210    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
211
212    uint32_t format = 0;
213    uint32_t conf;
214
215    conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
216
217    conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
218
219    switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
220    case SND_SOC_DAIFMT_CBS_CFS:
221        conf |= JZ_AIC_CONF_BIT_CLK_MASTER |
222                JZ_AIC_CONF_SYNC_CLK_MASTER;
223        format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
224        break;
225    case SND_SOC_DAIFMT_CBM_CFS:
226        conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
227        break;
228    case SND_SOC_DAIFMT_CBS_CFM:
229        conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
230        break;
231    case SND_SOC_DAIFMT_CBM_CFM:
232        break;
233    default:
234        return -EINVAL;
235    }
236
237    switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
238    case SND_SOC_DAIFMT_MSB:
239        format |= JZ_AIC_I2S_FMT_MSB;
240        break;
241    case SND_SOC_DAIFMT_I2S:
242        break;
243    default:
244        return -EINVAL;
245    }
246
247    switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
248    case SND_SOC_DAIFMT_NB_NF:
249        break;
250    default:
251        return -EINVAL;
105252    }
253
254    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
255    jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
256
257    return 0;
106258}
107259
108260static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
109                struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
261                 struct snd_pcm_hw_params *params,
262                 struct snd_soc_dai *dai)
110263{
111    struct snd_soc_pcm_runtime *rtd = substream->private_data;
112    struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
113    /* int channels = params_channels(params); */
264    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
265    bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
266    int sample_size;
267    enum jz4740_dma_width dma_width;
268    uint32_t ctrl;
114269
115    jz4740_snd_rx_ctrl(0);
116    jz4740_snd_rx_ctrl(0);
270    ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
117271
118272    switch (params_format(params)) {
119273    case SNDRV_PCM_FORMAT_S8:
120        __i2s_set_transmit_trigger(4);
121        __i2s_set_receive_trigger(3);
122        __i2s_set_oss_sample_size(8);
123        __i2s_set_iss_sample_size(8);
274        sample_size = 0;
275        dma_width = JZ4740_DMA_WIDTH_8BIT;
276        break;
277    case SNDRV_PCM_FORMAT_S16:
278        sample_size = 1;
279        dma_width = JZ4740_DMA_WIDTH_16BIT;
124280        break;
125    case SNDRV_PCM_FORMAT_S16_LE:
126        /* playback sample:16 bits, burst:16 bytes */
127        __i2s_set_transmit_trigger(4);
128        /* capture sample:16 bits, burst:16 bytes */
129        __i2s_set_receive_trigger(3);
130        __i2s_set_oss_sample_size(16);
131        __i2s_set_iss_sample_size(16);
281    default:
282        return -EINVAL;
283    }
284
285    if (playback) {
286        ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
287        ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
288    } else {
289        ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
290        ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
291    }
292
293    switch (params_channels(params)) {
294    case 2:
295        break;
296    case 1:
297        if (playback) {
298            ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
299            break;
300        }
301    default:
302        return -EINVAL;
303    }
304
305    jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
306
307    /* This is quite ugly, but apperently it's offical method for passing dma
308     * config to the pcm module */
309    if (playback) {
310        jz4740_i2s_dma_playback_config.src_width = dma_width;
311        i2s->pcm_config.dma_config = &jz4740_i2s_dma_playback_config;
312    } else {
313        jz4740_i2s_dma_capture_config.dst_width = dma_width;
314        i2s->pcm_config.dma_config = &jz4740_i2s_dma_capture_config;
315    }
316    i2s->pcm_config.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
317
318    dai->dma_data = &i2s->pcm_config;
319
320    return 0;
321}
322
323static int jz4740_i2s_set_clkdiv(struct snd_soc_dai *dai,
324                  int div_id, int div)
325{
326    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
327
328    switch (div_id) {
329    case JZ4740_I2S_BIT_CLK:
330        if (div & 1 || div > 16)
331            return -EINVAL;
332        jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div - 1);
132333        break;
334    default:
335        return -EINVAL;
133336    }
134337
135338    return 0;
136339}
137340
138static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
341static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
342                  unsigned int freq, int dir)
139343{
344    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
140345    int ret = 0;
141    switch (cmd) {
142    case SNDRV_PCM_TRIGGER_START:
143    case SNDRV_PCM_TRIGGER_RESUME:
144    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
145        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
146            jz4740_snd_rx_ctrl(1);
147        else
148            jz4740_snd_tx_ctrl(1);
346    struct clk *parent;
347
348    switch (clk_id) {
349    case JZ4740_I2S_CLKSRC_EXT:
350        parent = clk_get(NULL, "ext");
351        clk_set_parent(i2s->clk, parent);
149352        break;
150    case SNDRV_PCM_TRIGGER_STOP:
151    case SNDRV_PCM_TRIGGER_SUSPEND:
152    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
153        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
154            jz4740_snd_rx_ctrl(0);
155        else
156            jz4740_snd_tx_ctrl(0);
353    case JZ4740_I2S_CLKSRC_PLL:
354        parent = clk_get(NULL, "pll half");
355        clk_set_parent(i2s->clk, parent);
356        ret = clk_set_rate(i2s->clk, freq);
157357        break;
158358    default:
159        ret = -EINVAL;
359        return -EINVAL;
160360    }
361    clk_put(parent);
161362
162363    return ret;
163364}
164365
165static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
366static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
166367{
167    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
168    } else {
169    }
368    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
369    uint32_t conf;
170370
171    return;
172}
371    if (!dai->active)
372        return 0;
173373
174static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
175{
176    __i2s_internal_codec();
177    __i2s_as_slave();
178    __i2s_select_i2s();
179    __aic_select_i2s();
180    mdelay(2);
181
182    __i2s_disable();
183    __i2s_reset();
184    mdelay(2);
185
186       __i2s_disable();
187    __i2s_internal_codec();
188    __i2s_as_slave();
189    __i2s_select_i2s();
190    __aic_select_i2s();
191    __i2s_set_oss_sample_size(16);
192    __i2s_set_iss_sample_size(16);
193        __aic_play_lastsample();
194
195    __i2s_disable_record();
196    __i2s_disable_replay();
197    __i2s_disable_loopback();
198    __i2s_set_transmit_trigger(7);
199    __i2s_set_receive_trigger(7);
200
201    jz4740_snd_tx_ctrl(0);
202    jz4740_snd_rx_ctrl(0);
374    conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
375    conf &= ~JZ_AIC_CONF_ENABLE;
376    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
203377
378    clk_disable(i2s->clk);
204379    return 0;
205380}
206381
207#ifdef CONFIG_PM
208static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
382static int jz4740_i2s_resume(struct snd_soc_dai *dai)
209383{
384    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
385    uint32_t conf;
386
210387    if (!dai->active)
211388        return 0;
212389
390    clk_enable(i2s->clk);
391
392    conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
393    conf |= JZ_AIC_CONF_ENABLE;
394    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
395
213396    return 0;
214397}
215398
216static int jz4740_i2s_resume(struct snd_soc_dai *dai)
399
400static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
217401{
218    if (!dai->active)
219        return 0;
402    struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
403    uint32_t conf;
404
405    conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
406           (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
407           JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
408           JZ_AIC_CONF_I2S |
409           JZ_AIC_CONF_INTERNAL_CODEC;
410
411    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
412    jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
220413
221414    return 0;
222415}
223416
224#else
225#define jz4740_i2s_suspend NULL
226#define jz4740_i2s_resume NULL
227#endif
228
229#define JZ4740_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
230        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
231        SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
232        SNDRV_PCM_RATE_48000)
233417
234struct snd_soc_dai_ops snd_jz4740_i2s_dai_ops = {
418static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
235419    .startup = jz4740_i2s_startup,
236420    .shutdown = jz4740_i2s_shutdown,
237421    .trigger = jz4740_i2s_trigger,
238422    .hw_params = jz4740_i2s_hw_params,
239    .set_fmt = jz4740_i2s_set_dai_fmt,
240    .set_sysclk = jz4740_i2s_set_dai_sysclk,
423    .set_fmt = jz4740_i2s_set_fmt,
424    .set_clkdiv = jz4740_i2s_set_clkdiv,
425    .set_sysclk = jz4740_i2s_set_sysclk,
241426};
242427
428#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
429        SNDRV_PCM_FMTBIT_S16_LE)
430
243431struct snd_soc_dai jz4740_i2s_dai = {
244432    .name = "jz4740-i2s",
245    .id = 0,
246433    .probe = jz4740_i2s_probe,
247    .suspend = jz4740_i2s_suspend,
248    .resume = jz4740_i2s_resume,
249434    .playback = {
250435        .channels_min = 1,
251436        .channels_max = 2,
252        .rates = JZ4740_I2S_RATES,
253        .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
437        .rates = SNDRV_PCM_RATE_8000_44100,
438        .formats = JZ4740_I2S_FMTS,
254439    },
255440    .capture = {
256        .channels_min = 1,
441        .channels_min = 2,
257442        .channels_max = 2,
258        .rates = JZ4740_I2S_RATES,
259        .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
443        .rates = SNDRV_PCM_RATE_8000_44100,
444        .formats = JZ4740_I2S_FMTS,
260445    },
261    .ops = &snd_jz4740_i2s_dai_ops,
446    .symmetric_rates = 1,
447    .ops = &jz4740_i2s_dai_ops,
448    .suspend = jz4740_i2s_suspend,
449    .resume = jz4740_i2s_resume,
262450};
263451
264EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
265
266static int __init jz4740_i2s_init(void)
452static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
267453{
268    return snd_soc_register_dai(&jz4740_i2s_dai);
454    struct jz4740_i2s *i2s;
455    int ret;
456
457    i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
458
459    if (!i2s)
460        return -ENOMEM;
461
462    i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463
464    if (!i2s->mem) {
465        ret = -ENOENT;
466        goto err_free;
467    }
468
469    i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
470                pdev->name);
471
472    if (!i2s->mem) {
473        ret = -EBUSY;
474        goto err_free;
475    }
476
477    i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
478
479    if (!i2s->base) {
480        ret = -EBUSY;
481        goto err_release_mem_region;
482    }
483
484    i2s->phys_base = i2s->mem->start;
485
486    jz4740_i2s_dai.private_data = i2s;
487
488    ret = snd_soc_register_dai(&jz4740_i2s_dai);
489
490    i2s->clk = clk_get(&pdev->dev, "i2s");
491
492    if (IS_ERR(i2s->clk)) {
493        ret = PTR_ERR(i2s->clk);
494        goto err_iounmap;
495    }
496
497    platform_set_drvdata(pdev, i2s);
498
499    return 0;
500
501err_iounmap:
502    iounmap(i2s->base);
503err_release_mem_region:
504    release_mem_region(i2s->mem->start, resource_size(i2s->mem));
505err_free:
506    kfree(i2s);
507
508    return ret;
269509}
270510
271static void __exit jz4740_i2s_exit(void)
511static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
272512{
513    struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
514
273515    snd_soc_unregister_dai(&jz4740_i2s_dai);
516
517    clk_put(i2s->clk);
518
519    iounmap(i2s->base);
520    release_mem_region(i2s->mem->start, resource_size(i2s->mem));
521
522    platform_set_drvdata(pdev, NULL);
523    kfree(i2s);
524
525    return 0;
274526}
275527
528static struct platform_driver jz4740_i2s_driver = {
529    .probe = jz4740_i2s_dev_probe,
530    .remove = __devexit_p(jz4740_i2s_dev_remove),
531    .driver = {
532        .name = "jz4740-i2s",
533        .owner = THIS_MODULE,
534    },
535};
536
537static int __init jz4740_i2s_init(void)
538{
539    return platform_driver_register(&jz4740_i2s_driver);
540}
276541module_init(jz4740_i2s_init);
542
543static void __exit jz4740_i2s_exit(void)
544{
545    platform_driver_unregister(&jz4740_i2s_driver);
546}
277547module_exit(jz4740_i2s_exit);
278548
279/* Module information */
280MODULE_AUTHOR("Richard, cjfeng@ingenic.cn, www.ingenic.cn");
281MODULE_DESCRIPTION("jz4740 I2S SoC Interface");
549MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
550MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
282551MODULE_LICENSE("GPL");
552MODULE_ALIAS("platform:jz4740-i2s");
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-i2s.h
77#ifndef _JZ4740_I2S_H
88#define _JZ4740_I2S_H
99
10/* jz4740 DAI ID's */
11#define JZ4740_DAI_I2S 0
10/* I2S clock source */
11#define JZ4740_I2S_CLKSRC_EXT 0
12#define JZ4740_I2S_CLKSRC_PLL 1
1213
13/* I2S clock */
14#define JZ4740_I2S_SYSCLK 0
14#define JZ4740_I2S_BIT_CLK 0
1515
1616extern struct snd_soc_dai jz4740_i2s_dai;
1717
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-pcm.c
2424#include <sound/soc.h>
2525
2626#include <asm/mach-jz4740/dma.h>
27#include <asm/mach-jz4740/regs.h>
2827#include "jz4740-pcm.h"
2928
3029struct jz4740_runtime_data {
...... 
3231    dma_addr_t dma_start;
3332    dma_addr_t dma_pos;
3433    dma_addr_t dma_end;
35    struct jz4740_dma_chan *dma;
36};
3734
38static struct jz4740_dma_config jz4740_pcm_dma_playback_config = {
39    .src_width = JZ4740_DMA_WIDTH_16BIT,
40    .dst_width = JZ4740_DMA_WIDTH_32BIT,
41    .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
42    .request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
43    .flags = JZ4740_DMA_SRC_AUTOINC,
44    .mode = JZ4740_DMA_MODE_SINGLE,
45};
35    struct jz4740_dma_chan *dma;
4636
47static struct jz4740_dma_config jz4740_pcm_dma_capture_config = {
48    .src_width = JZ4740_DMA_WIDTH_32BIT,
49    .dst_width = JZ4740_DMA_WIDTH_16BIT,
50    .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
51    .request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
52    .flags = JZ4740_DMA_DST_AUTOINC,
53    .mode = JZ4740_DMA_MODE_SINGLE,
37    dma_addr_t fifo_addr;
5438};
5539
5640/* identify hardware playback capabilities */
...... 
8569
8670    if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
8771        jz4740_dma_set_src_addr(prtd->dma, prtd->dma_pos);
88        jz4740_dma_set_dst_addr(prtd->dma, CPHYSADDR(AIC_DR));
72        jz4740_dma_set_dst_addr(prtd->dma, prtd->fifo_addr);
8973    } else {
90        jz4740_dma_set_src_addr(prtd->dma, CPHYSADDR(AIC_DR));
74        jz4740_dma_set_src_addr(prtd->dma, prtd->fifo_addr);
9175        jz4740_dma_set_dst_addr(prtd->dma, prtd->dma_pos);
9276    }
9377
...... 
117101{
118102    struct snd_pcm_runtime *runtime = substream->runtime;
119103    struct jz4740_runtime_data *prtd = runtime->private_data;
120    unsigned int size = params_buffer_bytes(params);
121    struct jz4740_dma_config *dma_config;
122    enum jz4740_dma_width width;
123
124    switch (params_format(params)) {
125    case SNDRV_PCM_FORMAT_S8:
126        width = JZ4740_DMA_WIDTH_8BIT;
127        break;
128    case SNDRV_PCM_FORMAT_S16_LE:
129        width = JZ4740_DMA_WIDTH_16BIT;
130        break;
131    default:
132        BUG();
133        break;
134    }
104    struct snd_soc_pcm_runtime *rtd = substream->private_data;
105    struct jz4740_pcm_config *config;
135106
107    config = rtd->dai->cpu_dai->dma_data;
136108    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
137        dma_config = &jz4740_pcm_dma_playback_config;
138        dma_config->src_width = width;
139
140109        prtd->dma = jz4740_dma_request(substream, "PCM Playback");
141110    } else {
142        dma_config = &jz4740_pcm_dma_capture_config;
143        dma_config->dst_width = width;
144
145111        prtd->dma = jz4740_dma_request(substream, "PCM Capture");
146112    }
147113
148114    if (!prtd->dma)
149115        return -EBUSY;
150116
151    jz4740_dma_configure(prtd->dma, dma_config);
152
153    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
154        jz4740_dma_set_dst_addr(prtd->dma, CPHYSADDR(AIC_DR));
155    else
156        jz4740_dma_set_src_addr(prtd->dma, CPHYSADDR(AIC_DR));
117    jz4740_dma_configure(prtd->dma, config->dma_config);
118    prtd->fifo_addr = config->fifo_addr;
157119
158120    jz4740_dma_set_complete_cb(prtd->dma, jz4740_pcm_dma_transfer_done);
159121
160122    snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
161    runtime->dma_bytes = size;
123    runtime->dma_bytes = params_buffer_bytes(params);
162124
163125    prtd->dma_period = params_period_bytes(params);
164126    prtd->dma_start = runtime->dma_addr;
165127    prtd->dma_pos = prtd->dma_start;
166    prtd->dma_end = prtd->dma_start + size;
128    prtd->dma_end = prtd->dma_start + runtime->dma_bytes;
167129
168130    return 0;
169131}
...... 
271233               vma->vm_end - vma->vm_start, vma->vm_page_prot);
272234}
273235
274struct snd_pcm_ops jz4740_pcm_ops = {
236static const struct snd_pcm_ops jz4740_pcm_ops = {
275237    .open = jz4740_pcm_open,
276238    .close = jz4740_pcm_close,
277239    .ioctl = snd_pcm_lib_ioctl,
...... 
303265    return 0;
304266}
305267
306static void jz4740_pcm_free_dma_buffers(struct snd_pcm *pcm)
268static void jz4740_pcm_free(struct snd_pcm *pcm)
307269{
308270    struct snd_pcm_substream *substream;
309271    struct snd_dma_buffer *buf;
...... 
359321    .name = "jz4740-pcm",
360322    .pcm_ops = &jz4740_pcm_ops,
361323    .pcm_new = jz4740_pcm_new,
362    .pcm_free = jz4740_pcm_free_dma_buffers,
324    .pcm_free = jz4740_pcm_free,
363325};
364326EXPORT_SYMBOL_GPL(jz4740_soc_platform);
365327
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-pcm.h
88#ifndef _JZ4740_PCM_H
99#define _JZ4740_PCM_H
1010
11#include <linux/dma-mapping.h>
12#include <asm/mach-jz4740/dma.h>
13
1114/* platform data */
1215extern struct snd_soc_platform jz4740_soc_platform;
1316
17struct jz4740_pcm_config {
18    struct jz4740_dma_config *dma_config;
19    phys_addr_t fifo_addr;
20};
21
1422#endif

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