Date:2012-12-26 11:40:54 (11 years 3 months ago)
Author:juhosg
Commit:7d9a07b8551f0a3ec2e5a24c31ea1a60ecac2cad
Message:mpc83xx: add support for 3.7

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34892 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/mpc83xx/config-3.7 (1 diff)
target/linux/mpc83xx/patches-3.7/100-powerpc_create_fit_uImages.patch (1 diff)
target/linux/mpc83xx/patches-3.7/101-mpc8377_wlan-dts-add-gpio-leds.patch (1 diff)
target/linux/mpc83xx/patches-3.7/110-vitesse_8601.patch (1 diff)
target/linux/mpc83xx/patches-3.7/111-etsec27_war.patch (1 diff)
target/linux/mpc83xx/patches-3.7/120-ucc_tdm.patch (1 diff)
target/linux/mpc83xx/patches-3.7/200-powerpc-add-rbppc-support.patch (1 diff)
target/linux/mpc83xx/patches-3.7/201-powerpc-add-rb_iomap.patch (1 diff)
target/linux/mpc83xx/patches-3.7/202-ata-add-pata_rbppc_cf-driver.patch (1 diff)
target/linux/mpc83xx/patches-3.7/203-mtd-add-rbppc_nand-driver.patch (1 diff)
target/linux/mpc83xx/patches-3.7/300-mpc8377_wlan-dts-add-openwrt-hacks.patch (1 diff)

Change Details

target/linux/mpc83xx/config-3.7
1# CONFIG_40x is not set
2# CONFIG_44x is not set
3CONFIG_6xx=y
4CONFIG_8xxx_WDT=y
5# CONFIG_ADVANCED_OPTIONS is not set
6# CONFIG_ALTIVEC is not set
7# CONFIG_AMIGAONE is not set
8CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
9CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
10CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
11CONFIG_ARCH_HAS_ILOG2_U32=y
12CONFIG_ARCH_HAS_WALK_MEMORY=y
13CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
14CONFIG_ARCH_HIBERNATION_POSSIBLE=y
15CONFIG_ARCH_MAY_HAVE_PC_FDC=y
16# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
17# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
18CONFIG_ARCH_REQUIRE_GPIOLIB=y
19CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
20CONFIG_ARCH_SUPPORTS_MSI=y
21CONFIG_ARCH_SUPPORTS_UPROBES=y
22CONFIG_ARCH_SUSPEND_POSSIBLE=y
23CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
24CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
25# CONFIG_ARPD is not set
26# CONFIG_ASP834x is not set
27CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
28CONFIG_ATA=y
29CONFIG_AUDIT_ARCH=y
30CONFIG_BLK_DEV_SD=y
31# CONFIG_BOOTX_TEXT is not set
32CONFIG_BOUNCE=y
33CONFIG_CC_OPTIMIZE_FOR_SIZE=y
34CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
35CONFIG_CMDLINE_BOOL=y
36CONFIG_COMPAT_BRK=y
37CONFIG_CONFIGFS_FS=m
38CONFIG_CRC16=m
39CONFIG_CRC7=m
40CONFIG_CRC_CCITT=y
41CONFIG_CRC_ITU_T=m
42CONFIG_CRC_T10DIF=m
43CONFIG_CRYPTO_AEAD=y
44CONFIG_CRYPTO_AEAD2=y
45CONFIG_CRYPTO_AES=y
46CONFIG_CRYPTO_ALGAPI=y
47CONFIG_CRYPTO_ALGAPI2=y
48CONFIG_CRYPTO_AUTHENC=y
49CONFIG_CRYPTO_BLKCIPHER=y
50CONFIG_CRYPTO_BLKCIPHER2=y
51CONFIG_CRYPTO_CBC=y
52CONFIG_CRYPTO_CRC32C=y
53CONFIG_CRYPTO_DEFLATE=m
54CONFIG_CRYPTO_DES=m
55CONFIG_CRYPTO_DEV_TALITOS=y
56CONFIG_CRYPTO_GF128MUL=m
57CONFIG_CRYPTO_HASH=y
58CONFIG_CRYPTO_HASH2=y
59CONFIG_CRYPTO_HMAC=m
60CONFIG_CRYPTO_HW=y
61CONFIG_CRYPTO_MANAGER=y
62CONFIG_CRYPTO_MANAGER2=y
63CONFIG_CRYPTO_MD5=m
64CONFIG_CRYPTO_PCOMP2=y
65CONFIG_CRYPTO_RNG2=y
66CONFIG_CRYPTO_SHA1=m
67CONFIG_CRYPTO_WORKQUEUE=y
68CONFIG_DECOMPRESS_LZMA=y
69CONFIG_DEFAULT_CFQ=y
70# CONFIG_DEFAULT_DEADLINE is not set
71CONFIG_DEFAULT_IOSCHED="cfq"
72CONFIG_DEFAULT_UIMAGE=y
73CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
74CONFIG_DMADEVICES=y
75CONFIG_DMA_ENGINE=y
76CONFIG_DTC=y
77# CONFIG_DW_DMAC is not set
78# CONFIG_E200 is not set
79CONFIG_EARLY_PRINTK=y
80# CONFIG_EMBEDDED6xx is not set
81# CONFIG_ENABLE_WARN_DEPRECATED is not set
82# CONFIG_EPAPR_BOOT is not set
83CONFIG_FIRMWARE_IN_KERNEL=y
84CONFIG_FIXED_PHY=y
85CONFIG_FSL_DMA=y
86CONFIG_FSL_EMB_PERFMON=y
87CONFIG_FSL_GTM=y
88CONFIG_FSL_LBC=y
89CONFIG_FSL_PCI=y
90CONFIG_FSL_PQ_MDIO=y
91CONFIG_FSL_SOC=y
92# CONFIG_FSL_ULI1575 is not set
93CONFIG_FS_POSIX_ACL=y
94CONFIG_GENERIC_ACL=y
95CONFIG_GENERIC_ATOMIC64=y
96CONFIG_GENERIC_BUG=y
97CONFIG_GENERIC_CLOCKEVENTS=y
98CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
99CONFIG_GENERIC_CMOS_UPDATE=y
100CONFIG_GENERIC_GPIO=y
101CONFIG_GENERIC_IO=y
102CONFIG_GENERIC_IRQ_SHOW=y
103CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
104CONFIG_GENERIC_ISA_DMA=y
105CONFIG_GENERIC_KERNEL_THREAD=y
106CONFIG_GENERIC_NVRAM=y
107CONFIG_GENERIC_PCI_IOMAP=y
108CONFIG_GENERIC_SMP_IDLE_THREAD=y
109CONFIG_GENERIC_STRNCPY_FROM_USER=y
110CONFIG_GENERIC_STRNLEN_USER=y
111# CONFIG_GENERIC_TBSYNC is not set
112CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
113CONFIG_GEN_RTC=y
114# CONFIG_GEN_RTC_X is not set
115# CONFIG_GE_FPGA is not set
116CONFIG_GIANFAR=y
117CONFIG_GPIOLIB=y
118CONFIG_GPIO_MPC8XXX=y
119CONFIG_GPIO_SYSFS=y
120# CONFIG_HAMRADIO is not set
121CONFIG_HAS_DMA=y
122CONFIG_HAS_IOMEM=y
123CONFIG_HAS_IOPORT=y
124# CONFIG_HAS_RAPIDIO is not set
125CONFIG_HAVE_ARCH_JUMP_LABEL=y
126CONFIG_HAVE_ARCH_KGDB=y
127CONFIG_HAVE_ARCH_TRACEHOOK=y
128CONFIG_HAVE_CLK=y
129CONFIG_HAVE_DEBUG_KMEMLEAK=y
130CONFIG_HAVE_DMA_API_DEBUG=y
131CONFIG_HAVE_DMA_ATTRS=y
132CONFIG_HAVE_DYNAMIC_FTRACE=y
133CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
134CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
135CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
136CONFIG_HAVE_FUNCTION_TRACER=y
137# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
138CONFIG_HAVE_GENERIC_HARDIRQS=y
139CONFIG_HAVE_IDE=y
140CONFIG_HAVE_IOREMAP_PROT=y
141CONFIG_HAVE_IRQ_WORK=y
142CONFIG_HAVE_LATENCYTOP_SUPPORT=y
143CONFIG_HAVE_MEMBLOCK=y
144CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
145CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
146CONFIG_HAVE_OPROFILE=y
147CONFIG_HAVE_PERF_EVENTS=y
148CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
149# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
150CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
151CONFIG_HW_RANDOM=y
152CONFIG_HZ=250
153# CONFIG_HZ_100 is not set
154CONFIG_HZ_250=y
155CONFIG_INET_AH=m
156CONFIG_INET_DIAG=m
157CONFIG_INET_ESP=m
158CONFIG_INET_IPCOMP=m
159CONFIG_INET_LRO=y
160CONFIG_INET_TCP_DIAG=m
161CONFIG_INET_TUNNEL=m
162CONFIG_INET_XFRM_MODE_BEET=m
163CONFIG_INET_XFRM_MODE_TRANSPORT=m
164CONFIG_INET_XFRM_MODE_TUNNEL=m
165CONFIG_INET_XFRM_TUNNEL=m
166CONFIG_INITRAMFS_SOURCE=""
167CONFIG_INPUT=y
168# CONFIG_INPUT_MISC is not set
169# CONFIG_IOMMU_HELPER is not set
170CONFIG_IOSCHED_CFQ=y
171CONFIG_IPIC=y
172CONFIG_IP_PIMSM_V1=y
173CONFIG_IP_PIMSM_V2=y
174CONFIG_IP_ROUTE_CLASSID=y
175CONFIG_IP_SCTP=m
176CONFIG_IRQ_DOMAIN=y
177CONFIG_IRQ_FORCED_THREADING=y
178CONFIG_ISA_DMA_API=y
179# CONFIG_ISDN is not set
180# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
181# CONFIG_JFFS2_LZMA is not set
182# CONFIG_JFFS2_SUMMARY is not set
183CONFIG_JFFS2_ZLIB=y
184CONFIG_KERNEL_START=0xc0000000
185# CONFIG_KMETER1 is not set
186# CONFIG_LBDAF is not set
187# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
188# CONFIG_LEDS_TRIGGER_NETDEV is not set
189# CONFIG_LEDS_TRIGGER_TIMER is not set
190CONFIG_LIBCRC32C=y
191CONFIG_LOG_BUF_SHIFT=15
192CONFIG_LOWMEM_SIZE=0x30000000
193# CONFIG_MATH_EMULATION is not set
194CONFIG_MAX_ACTIVE_REGIONS=32
195CONFIG_MDIO_BITBANG=y
196CONFIG_MDIO_BOARDINFO=y
197CONFIG_MDIO_GPIO=y
198# CONFIG_MMIO_NVRAM is not set
199CONFIG_MODULES_USE_ELF_RELA=y
200# CONFIG_MPC512X_DMA is not set
201CONFIG_MPC830x_RDB=y
202CONFIG_MPC831x_RDB=y
203CONFIG_MPC832x_MDS=y
204CONFIG_MPC832x_RDB=y
205CONFIG_MPC834x_ITX=y
206CONFIG_MPC834x_MDS=y
207CONFIG_MPC836x_MDS=y
208CONFIG_MPC836x_RDK=y
209CONFIG_MPC837x_MDS=y
210CONFIG_MPC837x_RDB=y
211# CONFIG_MPIC is not set
212# CONFIG_MPIC_U3_HT_IRQS is not set
213# CONFIG_MPIC_WEIRD is not set
214CONFIG_MTD_BLOCK2MTD=y
215# CONFIG_MTD_CFI_INTELEXT is not set
216CONFIG_MTD_NAND=y
217CONFIG_MTD_NAND_ECC=y
218CONFIG_MTD_NAND_FSL_ELBC=y
219# CONFIG_MTD_NAND_FSL_IFC is not set
220CONFIG_MTD_NAND_FSL_UPM=y
221CONFIG_MTD_NAND_RB_PPC=y
222CONFIG_MTD_OF_PARTS=y
223CONFIG_MTD_PHYSMAP_OF=y
224# CONFIG_MTD_SM_COMMON is not set
225CONFIG_MTD_UBI=y
226CONFIG_MTD_UBI_BEB_LIMIT=20
227# CONFIG_MTD_UBI_FASTMAP is not set
228# CONFIG_MTD_UBI_GLUEBI is not set
229CONFIG_MTD_UBI_WL_THRESHOLD=4096
230# CONFIG_NEED_DMA_MAP_STATE is not set
231# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
232CONFIG_NEED_PER_CPU_KM=y
233CONFIG_NEED_SG_DMA_LENGTH=y
234# CONFIG_NETWORK_FILESYSTEMS is not set
235CONFIG_NET_CLS_BASIC=m
236CONFIG_NET_CLS_FLOW=m
237CONFIG_NET_CLS_FW=m
238CONFIG_NET_CLS_ROUTE4=m
239CONFIG_NET_CLS_RSVP=m
240CONFIG_NET_CLS_RSVP6=m
241CONFIG_NET_CLS_TCINDEX=m
242CONFIG_NET_CLS_U32=m
243# CONFIG_NET_DMA is not set
244CONFIG_NET_EMATCH=y
245CONFIG_NET_EMATCH_CMP=m
246CONFIG_NET_EMATCH_META=m
247CONFIG_NET_EMATCH_NBYTE=m
248CONFIG_NET_EMATCH_TEXT=m
249CONFIG_NET_EMATCH_U32=m
250CONFIG_NET_IPIP=m
251CONFIG_NET_SCH_CBQ=m
252CONFIG_NET_SCH_DSMARK=m
253CONFIG_NET_SCH_GRED=m
254CONFIG_NET_SCH_HFSC=m
255CONFIG_NET_SCH_HTB=m
256CONFIG_NET_SCH_NETEM=m
257CONFIG_NET_SCH_PRIO=m
258CONFIG_NET_SCH_RED=m
259CONFIG_NET_SCH_SFQ=m
260CONFIG_NET_SCH_TBF=m
261CONFIG_NET_SCH_TEQL=m
262# CONFIG_NONSTATIC_KERNEL is not set
263CONFIG_NR_IRQS=512
264CONFIG_OF=y
265CONFIG_OF_ADDRESS=y
266CONFIG_OF_DEVICE=y
267CONFIG_OF_EARLY_FLATTREE=y
268CONFIG_OF_FLATTREE=y
269CONFIG_OF_GPIO=y
270CONFIG_OF_IRQ=y
271CONFIG_OF_MDIO=y
272CONFIG_OF_MTD=y
273CONFIG_OF_NET=y
274CONFIG_OF_PCI=y
275CONFIG_OF_PCI_IRQ=y
276CONFIG_PAGEFLAGS_EXTENDED=y
277CONFIG_PAGE_OFFSET=0xc0000000
278# CONFIG_PARTITION_ADVANCED is not set
279CONFIG_PATA_RB_PPC=y
280CONFIG_PCI=y
281CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
282CONFIG_PCI_DOMAINS=y
283CONFIG_PCI_MSI=y
284CONFIG_PHYLIB=y
285CONFIG_PHYSICAL_START=0x00000000
286CONFIG_PPC=y
287CONFIG_PPC32=y
288# CONFIG_PPC64 is not set
289# CONFIG_PPC_82xx is not set
290CONFIG_PPC_83xx=y
291# CONFIG_PPC_85xx is not set
292# CONFIG_PPC_86xx is not set
293# CONFIG_PPC_8xx is not set
294# CONFIG_PPC_970_NAP is not set
295CONFIG_PPC_BOOK3S=y
296CONFIG_PPC_BOOK3S_32=y
297# CONFIG_PPC_CELL is not set
298# CONFIG_PPC_CELL_NATIVE is not set
299# CONFIG_PPC_CHRP is not set
300CONFIG_PPC_CLOCK=y
301# CONFIG_PPC_DCR_MMIO is not set
302# CONFIG_PPC_DCR_NATIVE is not set
303CONFIG_PPC_DISABLE_WERROR=y
304# CONFIG_PPC_EARLY_DEBUG is not set
305# CONFIG_PPC_EPAPR_HV_PIC is not set
306CONFIG_PPC_FPU=y
307CONFIG_PPC_HAVE_PMU_SUPPORT=y
308# CONFIG_PPC_I8259 is not set
309# CONFIG_PPC_ICP_HV is not set
310# CONFIG_PPC_ICP_NATIVE is not set
311# CONFIG_PPC_ICS_RTAS is not set
312CONFIG_PPC_INDIRECT_PCI=y
313CONFIG_PPC_LIB_RHEAP=y
314# CONFIG_PPC_MM_SLICES is not set
315# CONFIG_PPC_MPC106 is not set
316# CONFIG_PPC_MPC512x is not set
317# CONFIG_PPC_MPC52xx is not set
318CONFIG_PPC_MPC831x=y
319CONFIG_PPC_MPC832x=y
320CONFIG_PPC_MPC834x=y
321CONFIG_PPC_MPC837x=y
322CONFIG_PPC_MSI_BITMAP=y
323CONFIG_PPC_OF=y
324CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
325# CONFIG_PPC_P7_NAP is not set
326CONFIG_PPC_PCI_CHOICE=y
327# CONFIG_PPC_PMAC is not set
328# CONFIG_PPC_RTAS is not set
329CONFIG_PPC_STD_MMU=y
330CONFIG_PPC_STD_MMU_32=y
331CONFIG_PPC_UDBG_16550=y
332# CONFIG_PPC_WSP is not set
333# CONFIG_PPC_XICS is not set
334# CONFIG_PQ2ADS is not set
335# CONFIG_PREEMPT_RCU is not set
336CONFIG_PROC_DEVICETREE=y
337CONFIG_PROC_PAGE_MONITOR=y
338CONFIG_QE_GPIO=y
339CONFIG_QUICC_ENGINE=y
340CONFIG_RB_IOMAP=y
341CONFIG_RB_PPC=y
342CONFIG_RWSEM_XCHGADD_ALGORITHM=y
343# CONFIG_SBC834x is not set
344CONFIG_SCHED_HRTICK=y
345CONFIG_SCSI=y
346# CONFIG_SCSI_LOWLEVEL is not set
347# CONFIG_SCSI_MULTI_LUN is not set
348# CONFIG_SCSI_PROC_FS is not set
349# CONFIG_SCTP_DBG_MSG is not set
350# CONFIG_SCTP_DBG_OBJCNT is not set
351CONFIG_SCTP_HMAC_MD5=y
352# CONFIG_SCTP_HMAC_NONE is not set
353# CONFIG_SCTP_HMAC_SHA1 is not set
354CONFIG_SERIAL_8250_FSL=y
355CONFIG_SERIAL_8250_PCI=y
356CONFIG_SERIAL_QE=y
357CONFIG_SERIO=y
358CONFIG_SERIO_I8042=y
359CONFIG_SERIO_PCIPS2=y
360CONFIG_SERIO_RAW=y
361CONFIG_SERIO_SERPORT=y
362# CONFIG_SERIO_XILINX_XPS_PS2 is not set
363CONFIG_SIMPLE_GPIO=y
364# CONFIG_SLAB is not set
365CONFIG_SLOB=y
366CONFIG_SOCK_DIAG=y
367CONFIG_SPARSE_IRQ=y
368CONFIG_SPI=y
369CONFIG_SPI_MASTER=y
370# CONFIG_SWAP is not set
371# CONFIG_SWIOTLB is not set
372CONFIG_SYSCTL_EXCEPTION_TRACE=y
373CONFIG_TASK_SIZE=0xc0000000
374# CONFIG_TAU is not set
375CONFIG_TEXTSEARCH_BM=m
376CONFIG_TEXTSEARCH_FSM=m
377CONFIG_TEXTSEARCH_KMP=m
378CONFIG_TICK_CPU_ACCOUNTING=y
379CONFIG_TMPFS_POSIX_ACL=y
380# CONFIG_UBIFS_FS is not set
381CONFIG_UCC=y
382CONFIG_UCC_FAST=y
383CONFIG_UCC_GETH=y
384CONFIG_UCC_SLOW=y
385# CONFIG_UCC_TDM is not set
386# CONFIG_UGETH_TX_ON_DEMAND is not set
387CONFIG_UIDGID_CONVERTED=y
388CONFIG_USB_ARCH_HAS_XHCI=y
389CONFIG_VIA_VELOCITY=y
390CONFIG_VITESSE_PHY=y
391CONFIG_VITESSE_PHY_8601_SKEW=y
392CONFIG_WAN_ROUTER=m
393CONFIG_WORD_SIZE=32
394CONFIG_XFRM_ALGO=m
395CONFIG_XFRM_IPCOMP=m
396CONFIG_YAFFS_9BYTE_TAGS=y
397# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
398CONFIG_YAFFS_AUTO_YAFFS2=y
399# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
400# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
401CONFIG_YAFFS_DISABLE_TAGS_ECC=y
402# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
403# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
404CONFIG_YAFFS_FS=y
405CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
406CONFIG_YAFFS_XATTR=y
407CONFIG_YAFFS_YAFFS1=y
408CONFIG_YAFFS_YAFFS2=y
target/linux/mpc83xx/patches-3.7/100-powerpc_create_fit_uImages.patch
1--- a/arch/powerpc/Makefile
2@@ -155,7 +155,9 @@ all: zImage
3
4 # With make 3.82 we cannot mix normal and wildcard targets
5 BOOT_TARGETS1 := zImage zImage.initrd uImage
6-BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
7+BOOT_TARGETS2 := uImage.fit.% zImage% dtbImage% treeImage.% cuImage.% \
8+ simpleImage.% uImage.%
9+
10
11 PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
12
13@@ -188,6 +190,7 @@ define archhelp
14   @echo '* zImage - Build default images selected by kernel config'
15   @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
16   @echo ' uImage - U-Boot native image format'
17+ @echo ' uImage.fit.<dt> - U-Boot Flattened Image Tree image format'
18   @echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
19   @echo ' versions which do not support device trees'
20   @echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
21--- a/arch/powerpc/boot/.gitignore
22@@ -14,6 +14,7 @@ kernel-vmlinux.strip.c
23 kernel-vmlinux.strip.gz
24 mktree
25 uImage
26+uImage.fit.*
27 cuImage.*
28 dtbImage.*
29 treeImage.*
30--- a/arch/powerpc/boot/Makefile
31@@ -338,6 +338,9 @@ $(obj)/uImage.initrd.%: vmlinux $(obj)/%
32 $(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
33     $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
34
35+$(obj)/uImage.fit.%: vmlinux $(obj)/%.dtb $(wrapperbits)
36+ $(call if_changed,wrap,uboot.fit,,$(obj)/$*.dtb)
37+
38 $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
39     $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
40
41@@ -375,6 +378,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
42
43 # anything not in $(targets)
44 clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
45+ uImage.* \
46     zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
47     zImage.miboot zImage.pmac zImage.pseries \
48     zImage.maple simpleImage.* otheros.bld *.dtb
49--- a/arch/powerpc/boot/wrapper
50@@ -47,6 +47,9 @@ CROSS=
51 # mkimage wrapper script
52 MKIMAGE=$srctree/scripts/mkuboot.sh
53
54+# script to generate an .its file for uImage.fit.* images
55+MKITS=$srctree/scripts/mkits.sh
56+
57 # directory for object and other files used by this script
58 object=arch/powerpc/boot
59 objbin=$object
60@@ -336,6 +339,21 @@ uboot-obs600)
61     if [ -z "$cacheit" ]; then
62     rm -f "$vmz"
63     fi
64+ exit 0
65+ ;;
66+uboot.fit)
67+ rm -f "$ofile"
68+ ${MKITS} -A ppc -C gzip -a $membase -e $membase -v $version \
69+ -d "$srctree/$dtb" -k "$srctree/$vmz" -o "$object/uImage.its"
70+
71+ # mkimage calls dtc for FIT images so use kernel dtc if necessary
72+ export PATH=$PATH:$srctree/scripts/dtc
73+
74+ ${MKIMAGE} -f "$object/uImage.its" "$ofile"
75+ rm "$object/uImage.its"
76+ if [ -z "$cacheit" ]; then
77+ rm -f "$vmz"
78+ fi
79     exit 0
80     ;;
81 esac
target/linux/mpc83xx/patches-3.7/101-mpc8377_wlan-dts-add-gpio-leds.patch
1--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
2@@ -462,4 +462,18 @@
3                   0 0x00800000>;
4         };
5     };
6+
7+ leds {
8+ compatible = "gpio-leds";
9+
10+ diag {
11+ gpios = <&gpio1 9 1>;
12+ default-state = "off";
13+ };
14+
15+ wireless {
16+ gpios = <&gpio1 10 1>;
17+ default-state = "off";
18+ };
19+ };
20 };
target/linux/mpc83xx/patches-3.7/110-vitesse_8601.patch
1--- a/drivers/net/phy/Kconfig
2@@ -69,6 +69,12 @@ config VITESSE_PHY
3         ---help---
4           Currently supports the vsc8244
5
6+config VITESSE_PHY_8601_SKEW
7+ bool "Enable skew timing to vsc8601"
8+ depends on VITESSE_PHY
9+ ---help---
10+ Apply clock timing adjustments for vsc8601
11+
12 config SMSC_PHY
13     tristate "Drivers for SMSC PHYs"
14     ---help---
15--- a/drivers/net/phy/vitesse.c
16@@ -26,6 +26,11 @@
17 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
18 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
19
20+/* EXT_CON1 Register values for VSC8601 */
21+#define MII_VSC8601_EXTCON1_INIT 0x0000
22+#define MII_VSC8601_EXTCON1_SKEW 0x0100
23+#define MII_VSC8601_EXTCON1_ACTIPHY 0x0020
24+
25 /* Vitesse Interrupt Mask Register */
26 #define MII_VSC8244_IMASK 0x19
27 #define MII_VSC8244_IMASK_IEN 0x8000
28@@ -56,6 +61,7 @@
29
30 #define PHY_ID_VSC8244 0x000fc6c0
31 #define PHY_ID_VSC8221 0x000fc550
32+#define PHY_ID_VSC8601 0x00070420
33
34 MODULE_DESCRIPTION("Vitesse PHY driver");
35 MODULE_AUTHOR("Kriston Carson");
36@@ -98,10 +104,34 @@ static int vsc824x_config_init(struct ph
37     return err;
38 }
39
40+static int vsc8601_config_init(struct phy_device *phydev)
41+{
42+ int err;
43+ int extcon;
44+
45+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
46+ MII_VSC8244_AUXCONSTAT_INIT);
47+
48+ if (err < 0)
49+ return err;
50+
51+#ifdef CONFIG_VITESSE_PHY_8601_SKEW
52+ extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
53+ if (err < 0)
54+ return err;
55+
56+ extcon |= MII_VSC8601_EXTCON1_SKEW;
57+
58+ err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
59+#endif
60+
61+ return err;
62+}
63+
64 static int vsc824x_ack_interrupt(struct phy_device *phydev)
65 {
66     int err = 0;
67-
68+
69     /*
70      * Don't bother to ACK the interrupts if interrupts
71      * are disabled. The 824x cannot clear the interrupts
72@@ -177,6 +207,19 @@ static struct phy_driver vsc82xx_driver[
73     .ack_interrupt = &vsc824x_ack_interrupt,
74     .config_intr = &vsc82xx_config_intr,
75     .driver = { .owner = THIS_MODULE,},
76+}, {
77+ /* Vitesse 8601 */
78+ .phy_id = PHY_ID_VSC8601,
79+ .name = "Vitesse VSC8601",
80+ .phy_id_mask = 0x000ffff8,
81+ .features = PHY_GBIT_FEATURES,
82+ .flags = PHY_HAS_INTERRUPT,
83+ .config_init = &vsc8601_config_init,
84+ .config_aneg = &genphy_config_aneg,
85+ .read_status = &genphy_read_status,
86+ .ack_interrupt = &vsc824x_ack_interrupt,
87+ .config_intr = &vsc82xx_config_intr,
88+ .driver = { .owner = THIS_MODULE,},
89 } };
90
91 static int __init vsc82xx_init(void)
target/linux/mpc83xx/patches-3.7/111-etsec27_war.patch
1--- a/drivers/net/ethernet/freescale/gianfar.c
2@@ -1009,7 +1009,16 @@ static int gfar_probe(struct platform_de
3     /* We need to delay at least 3 TX clocks */
4     udelay(2);
5
6- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
7+ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) {
8+ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
9+ } else {
10+ /*
11+ * Do not enable flow control on chips earlier than rev 1.1,
12+ * because of the eTSEC27 erratum
13+ */
14+ tempval = 0;
15+ }
16+
17     gfar_write(&regs->maccfg1, tempval);
18
19     /* Initialize MACCFG2. */
target/linux/mpc83xx/patches-3.7/120-ucc_tdm.patch
1--- /dev/null
2@@ -0,0 +1,221 @@
3+/*
4+ * drivers/misc/ucc_tdm.h
5+ *
6+ * UCC Based Linux TDM Driver
7+ * This driver is designed to support UCC based TDM for PowerPC processors.
8+ * This driver can interface with SLIC device to run VOIP kind of
9+ * applications.
10+ *
11+ * Author: Ashish Kalra & Poonam Aggrwal
12+ *
13+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
14+ *
15+ * This program is free software; you can redistribute it and/or modify it
16+ * under the terms of the GNU General Public License as published by the
17+ * Free Software Foundation; either version 2 of the License, or (at your
18+ * option) any later version.
19+ */
20+
21+#ifndef TDM_H
22+#define TDM_H
23+
24+#define NUM_TS 8
25+#define ACTIVE_CH 8
26+
27+/* SAMPLE_DEPTH is the sample depth is the number of frames before
28+ * an interrupt. Must be a multiple of 4
29+ */
30+#define SAMPLE_DEPTH 80
31+
32+/* define the number of Rx interrupts to go by for initial stuttering */
33+#define STUTTER_INT_CNT 1
34+
35+/* BMRx Field Descriptions to specify tstate and rstate in UCC parameter RAM*/
36+#define EN_BUS_SNOOPING 0x20
37+#define BE_BO 0x10
38+
39+/* UPSMR Register for Transparent UCC controller Bit definitions*/
40+#define NBO 0x00000000 /* Normal Mode 1 bit of data per clock */
41+
42+/* SI Mode register bit definitions */
43+#define NORMAL_OPERATION 0x0000
44+#define AUTO_ECHO 0x0400
45+#define INTERNAL_LB 0x0800
46+#define CONTROL_LB 0x0c00
47+#define SIMODE_CRT (0x8000 >> 9)
48+#define SIMODE_SL (0x8000 >> 10)
49+#define SIMODE_CE (0x8000 >> 11)
50+#define SIMODE_FE (0x8000 >> 12)
51+#define SIMODE_GM (0x8000 >> 13)
52+#define SIMODE_TFSD(val) (val)
53+#define SIMODE_RFSD(val) ((val) << 8)
54+
55+#define SI_TDM_MODE_REGISTER_OFFSET 0
56+
57+#define R_CM 0x02000000
58+#define T_CM 0x02000000
59+
60+#define SET_RX_SI_RAM(n, val) \
61+ out_be16((u16 *)&qe_immr->sir.rx[(n)*2], (u16)(val))
62+
63+#define SET_TX_SI_RAM(n, val) \
64+ out_be16((u16 *)&qe_immr->sir.tx[(n)*2], (u16)(val))
65+
66+/* SI RAM entries */
67+#define SIR_LAST 0x0001
68+#define SIR_CNT(n) ((n) << 2)
69+#define SIR_BYTE 0x0002
70+#define SIR_BIT 0x0000
71+#define SIR_IDLE 0
72+#define SIR_UCC(uccx) (((uccx+9)) << 5)
73+
74+/* BRGC Register Bit definitions */
75+#define BRGC_RESET (0x1<<17)
76+#define BRGC_EN (0x1<<16)
77+#define BRGC_EXTC_QE (0x00<<14)
78+#define BRGC_EXTC_CLK3 (0x01<<14)
79+#define BRGC_EXTC_CLK5 (0x01<<15)
80+#define BRGC_EXTC_CLK9 (0x01<<14)
81+#define BRGC_EXTC_CLK11 (0x01<<14)
82+#define BRGC_EXTC_CLK13 (0x01<<14)
83+#define BRGC_EXTC_CLK15 (0x01<<15)
84+#define BRGC_ATB (0x1<<13)
85+#define BRGC_DIV16 (0x1)
86+
87+/* structure representing UCC transparent parameter RAM */
88+struct ucc_transparent_pram {
89+ __be16 riptr;
90+ __be16 tiptr;
91+ __be16 res0;
92+ __be16 mrblr;
93+ __be32 rstate;
94+ __be32 rbase;
95+ __be16 rbdstat;
96+ __be16 rbdlen;
97+ __be32 rdptr;
98+ __be32 tstate;
99+ __be32 tbase;
100+ __be16 tbdstat;
101+ __be16 tbdlen;
102+ __be32 tdptr;
103+ __be32 rbptr;
104+ __be32 tbptr;
105+ __be32 rcrc;
106+ __be32 res1;
107+ __be32 tcrc;
108+ __be32 res2;
109+ __be32 res3;
110+ __be32 c_mask;
111+ __be32 c_pres;
112+ __be16 disfc;
113+ __be16 crcec;
114+ __be32 res4[4];
115+ __be16 ts_tmp;
116+ __be16 tmp_mb;
117+};
118+
119+#define UCC_TRANSPARENT_PRAM_SIZE 0x100
120+
121+struct tdm_cfg {
122+ u8 com_pin; /* Common receive and transmit pins
123+ * 0 = separate pins
124+ * 1 = common pins
125+ */
126+
127+ u8 fr_sync_level; /* SLx bit Frame Sync Polarity
128+ * 0 = L1R/TSYNC active logic "1"
129+ * 1 = L1R/TSYNC active logic "0"
130+ */
131+
132+ u8 clk_edge; /* CEx bit Tx Rx Clock Edge
133+ * 0 = TX data on rising edge of clock
134+ * RX data on falling edge
135+ * 1 = TX data on falling edge of clock
136+ * RX data on rising edge
137+ */
138+
139+ u8 fr_sync_edge; /* FEx bit Frame sync edge
140+ * Determine when the sync pulses are sampled
141+ * 0 = Falling edge
142+ * 1 = Rising edge
143+ */
144+
145+ u8 rx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
146+ * 00 = no bit delay
147+ * 01 = 1 bit delay
148+ * 10 = 2 bit delay
149+ * 11 = 3 bit delay
150+ */
151+
152+ u8 tx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
153+ * 00 = no bit delay
154+ * 01 = 1 bit delay
155+ * 10 = 2 bit delay
156+ * 11 = 3 bit delay
157+ */
158+
159+ u8 active_num_ts; /* Number of active time slots in TDM
160+ * assume same active Rx/Tx time slots
161+ */
162+};
163+
164+struct ucc_tdm_info {
165+ struct ucc_fast_info uf_info;
166+ u32 ucc_busy;
167+};
168+
169+struct tdm_ctrl {
170+ u32 device_busy;
171+ struct device *device;
172+ struct ucc_fast_private *uf_private;
173+ struct ucc_tdm_info *ut_info;
174+ u32 tdm_port; /* port for this tdm:TDMA,TDMB,TDMC,TDMD */
175+ u32 si; /* serial interface: 0 or 1 */
176+ struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
177+ u16 rx_mask[8]; /* Active Receive channels LSB is ch0 */
178+ u16 tx_mask[8]; /* Active Transmit channels LSB is ch0 */
179+ /* Only channels less than the number of FRAME_SIZE are implemented */
180+ struct tdm_cfg cfg_ctrl; /* Signaling controls configuration */
181+ u8 *tdm_input_data; /* buffer used for Rx by the tdm */
182+ u8 *tdm_output_data; /* buffer used for Tx by the tdm */
183+
184+ dma_addr_t dma_input_addr; /* dma mapped buffer for TDM Rx */
185+ dma_addr_t dma_output_addr; /* dma mapped buffer for TDM Tx */
186+ u16 physical_num_ts; /* physical number of timeslots in the tdm
187+ frame */
188+ u32 phase_rx; /* cycles through 0, 1, 2 */
189+ u32 phase_tx; /* cycles through 0, 1, 2 */
190+ /*
191+ * the following two variables are for dealing with "stutter" problem
192+ * "stutter" period is about 20 frames or so, varies depending active
193+ * channel num depending on the sample depth, the code should let a
194+ * few Rx interrupts go by
195+ */
196+ u32 tdm_icnt;
197+ u32 tdm_flag;
198+ struct ucc_transparent_pram __iomem *ucc_pram;
199+ struct qe_bd __iomem *tx_bd;
200+ struct qe_bd __iomem *rx_bd;
201+ u32 ucc_pram_offset;
202+ u32 tx_bd_offset;
203+ u32 rx_bd_offset;
204+ u32 rx_ucode_buf_offset;
205+ u32 tx_ucode_buf_offset;
206+ bool leg_slic;
207+ wait_queue_head_t wakeup_event;
208+};
209+
210+struct tdm_client {
211+ u32 client_id;
212+ void (*tdm_read)(u32 client_id, short chn_id,
213+ short *pcm_buffer, short len);
214+ void (*tdm_write)(u32 client_id, short chn_id,
215+ short *pcm_buffer, short len);
216+ wait_queue_head_t *wakeup_event;
217+ };
218+
219+#define MAX_PHASE 1
220+#define NR_BUFS 2
221+#define EFF_ACTIVE_CH ACTIVE_CH / 2
222+
223+#endif
224--- /dev/null
225@@ -0,0 +1,1017 @@
226+/*
227+ * drivers/misc/ucc_tdm.c
228+ *
229+ * UCC Based Linux TDM Driver
230+ * This driver is designed to support UCC based TDM for PowerPC processors.
231+ * This driver can interface with SLIC device to run VOIP kind of
232+ * applications.
233+ *
234+ * Author: Ashish Kalra & Poonam Aggrwal
235+ *
236+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
237+ *
238+ * This program is free software; you can redistribute it and/or modify it
239+ * under the terms of the GNU General Public License as published by the
240+ * Free Software Foundation; either version 2 of the License, or (at your
241+ * option) any later version.
242+ */
243+
244+#include <generated/autoconf.h>
245+#include <linux/module.h>
246+#include <linux/sched.h>
247+#include <linux/kernel.h>
248+#include <linux/slab.h>
249+#include <linux/errno.h>
250+#include <linux/types.h>
251+#include <linux/interrupt.h>
252+#include <linux/time.h>
253+#include <linux/skbuff.h>
254+#include <linux/proc_fs.h>
255+#include <linux/delay.h>
256+#include <linux/dma-mapping.h>
257+#include <linux/string.h>
258+#include <linux/irq.h>
259+#include <linux/of_platform.h>
260+#include <linux/io.h>
261+#include <linux/wait.h>
262+#include <linux/timer.h>
263+
264+#include <asm/immap_qe.h>
265+#include <asm/qe.h>
266+#include <asm/ucc.h>
267+#include <asm/ucc_fast.h>
268+#include <asm/ucc_slow.h>
269+
270+#include "ucc_tdm.h"
271+#define DRV_DESC "Freescale QE UCC TDM Driver"
272+#define DRV_NAME "ucc_tdm"
273+
274+
275+/*
276+ * define the following #define if snooping or hardware-based cache coherency
277+ * is disabled on the UCC transparent controller.This flag enables
278+ * software-based cache-coherency support by explicitly flushing data cache
279+ * contents after setting up the TDM output buffer(s) and invalidating the
280+ * data cache contents before the TDM input buffer(s) are read.
281+ */
282+#undef UCC_CACHE_SNOOPING_DISABLED
283+
284+#define MAX_NUM_TDM_DEVICES 8
285+
286+static struct tdm_ctrl *tdm_ctrl[MAX_NUM_TDM_DEVICES];
287+
288+static int num_tdm_devices;
289+static int num_tdm_clients;
290+
291+static struct ucc_tdm_info utdm_primary_info = {
292+ .uf_info = {
293+ .tsa = 1,
294+ .cdp = 1,
295+ .cds = 1,
296+ .ctsp = 1,
297+ .ctss = 1,
298+ .revd = 1,
299+ .urfs = 0x128,
300+ .utfs = 0x128,
301+ .utfet = 0,
302+ .utftt = 0x128,
303+ .ufpt = 256,
304+ .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT,
305+ .tenc = UCC_FAST_TX_ENCODING_NRZ,
306+ .renc = UCC_FAST_RX_ENCODING_NRZ,
307+ .tcrc = UCC_FAST_16_BIT_CRC,
308+ .synl = UCC_FAST_SYNC_LEN_NOT_USED,
309+ },
310+ .ucc_busy = 0,
311+};
312+
313+static struct ucc_tdm_info utdm_info[8];
314+
315+static void dump_siram(struct tdm_ctrl *tdm_c)
316+{
317+#ifdef DEBUG
318+ int i;
319+ u16 phy_num_ts;
320+
321+ phy_num_ts = tdm_c->physical_num_ts;
322+
323+ pr_debug("SI TxRAM dump\n");
324+ /* each slot entry in SI RAM is of 2 bytes */
325+ for (i = 0; i < phy_num_ts * 2; i++)
326+ pr_debug("%x ", in_8(&qe_immr->sir.tx[i]));
327+ pr_debug("\nSI RxRAM dump\n");
328+ for (i = 0; i < phy_num_ts * 2; i++)
329+ pr_debug("%x ", in_8(&qe_immr->sir.rx[i]));
330+ pr_debug("\n");
331+#endif
332+}
333+
334+static void dump_ucc(struct tdm_ctrl *tdm_c)
335+{
336+#ifdef DEBUG
337+ struct ucc_transparent_pram *ucc_pram;
338+
339+ ucc_pram = tdm_c->ucc_pram;
340+
341+ pr_debug("%s Dumping UCC Registers\n", __FUNCTION__);
342+ ucc_fast_dump_regs(tdm_c->uf_private);
343+ pr_debug("%s Dumping UCC Parameter RAM\n", __FUNCTION__);
344+ pr_debug("rbase = 0x%x\n", in_be32(&ucc_pram->rbase));
345+ pr_debug("rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr));
346+ pr_debug("mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr));
347+ pr_debug("rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen));
348+ pr_debug("rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat));
349+ pr_debug("rstate = 0x%x\n", in_be32(&ucc_pram->rstate));
350+ pr_debug("rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr));
351+ pr_debug("tbase = 0x%x\n", in_be32(&ucc_pram->tbase));
352+ pr_debug("tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr));
353+ pr_debug("tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen));
354+ pr_debug("tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat));
355+ pr_debug("tstate = 0x%x\n", in_be32(&ucc_pram->tstate));
356+ pr_debug("tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr));
357+#endif
358+}
359+
360+/*
361+ * For use when a framing bit is not present
362+ * Program current-route SI ram
363+ * Set SIxRAM TDMx
364+ * Entries must be in units of 8.
365+ * SIR_UCC -> Channel Select
366+ * SIR_CNT -> Number of bits or bytes
367+ * SIR_BYTE -> Byte or Bit resolution
368+ * SIR_LAST -> Indicates last entry in SIxRAM
369+ * SIR_IDLE -> The Tx data pin is Tri-stated and the Rx data pin is
370+ * ignored
371+ */
372+static void set_siram(struct tdm_ctrl *tdm_c, enum comm_dir dir)
373+{
374+ const u16 *mask;
375+ u16 temp_mask = 1;
376+ u16 siram_code = 0;
377+ u32 i, j, k;
378+ u32 ucc;
379+ u32 phy_num_ts;
380+
381+ phy_num_ts = tdm_c->physical_num_ts;
382+ ucc = tdm_c->ut_info->uf_info.ucc_num;
383+
384+ if (dir == COMM_DIR_RX)
385+ mask = tdm_c->rx_mask;
386+ else
387+ mask = tdm_c->tx_mask;
388+ k = 0;
389+ j = 0;
390+ for (i = 0; i < phy_num_ts; i++) {
391+ if ((mask[k] & temp_mask) == temp_mask)
392+ siram_code = SIR_UCC(ucc) | SIR_CNT(0) | SIR_BYTE;
393+ else
394+ siram_code = SIR_IDLE | SIR_CNT(0) | SIR_BYTE;
395+ if (dir == COMM_DIR_RX)
396+ out_be16((u16 *)&qe_immr->sir.rx[i * 2], siram_code);
397+ else
398+ out_be16((u16 *)&qe_immr->sir.tx[i * 2], siram_code);
399+ temp_mask = temp_mask << 1;
400+ j++;
401+ if (j >= 16) {
402+ j = 0;
403+ temp_mask = 0x0001;
404+ k++;
405+ }
406+ }
407+ siram_code = siram_code | SIR_LAST;
408+
409+ if (dir == COMM_DIR_RX)
410+ out_be16((u16 *)&qe_immr->sir.rx[(phy_num_ts - 1) * 2],
411+ siram_code);
412+ else
413+ out_be16((u16 *)&qe_immr->sir.tx[(phy_num_ts - 1) * 2],
414+ siram_code);
415+}
416+
417+static void config_si(struct tdm_ctrl *tdm_c)
418+{
419+ u8 rxsyncdelay, txsyncdelay, tdm_port;
420+ u16 sixmr_val = 0;
421+ u32 tdma_mode_off;
422+ u16 *si1_tdm_mode_reg;
423+
424+ tdm_port = tdm_c->tdm_port;
425+
426+ set_siram(tdm_c, COMM_DIR_RX);
427+
428+ set_siram(tdm_c, COMM_DIR_TX);
429+
430+ rxsyncdelay = tdm_c->cfg_ctrl.rx_fr_sync_delay;
431+ txsyncdelay = tdm_c->cfg_ctrl.tx_fr_sync_delay;
432+ if (tdm_c->cfg_ctrl.com_pin)
433+ sixmr_val |= SIMODE_CRT;
434+ if (tdm_c->cfg_ctrl.fr_sync_level == 1)
435+ sixmr_val |= SIMODE_SL;
436+ if (tdm_c->cfg_ctrl.clk_edge == 1)
437+ sixmr_val |= SIMODE_CE;
438+ if (tdm_c->cfg_ctrl.fr_sync_edge == 1)
439+ sixmr_val |= SIMODE_FE;
440+ sixmr_val |= (SIMODE_TFSD(txsyncdelay) | SIMODE_RFSD(rxsyncdelay));
441+
442+ tdma_mode_off = SI_TDM_MODE_REGISTER_OFFSET * tdm_c->tdm_port;
443+
444+ si1_tdm_mode_reg = (u8 *)&qe_immr->si1 + tdma_mode_off;
445+ out_be16(si1_tdm_mode_reg, sixmr_val);
446+
447+ dump_siram(tdm_c);
448+}
449+
450+static int tdm_init(struct tdm_ctrl *tdm_c)
451+{
452+ u32 tdm_port, ucc, act_num_ts;
453+ int ret, i, err;
454+ u32 cecr_subblock;
455+ u32 pram_offset;
456+ u32 rxbdt_offset;
457+ u32 txbdt_offset;
458+ u32 rx_ucode_buf_offset, tx_ucode_buf_offset;
459+ u16 bd_status, bd_len;
460+ enum qe_clock clock;
461+ struct qe_bd __iomem *rx_bd, *tx_bd;
462+
463+ tdm_port = tdm_c->tdm_port;
464+ ucc = tdm_c->ut_info->uf_info.ucc_num;
465+ act_num_ts = tdm_c->cfg_ctrl.active_num_ts;
466+
467+ /*
468+ * TDM Tx and Rx CLKs = 2048 KHz.
469+ */
470+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_clk, "BRG")) {
471+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_clk);
472+ err = qe_setbrg(clock, 2048000, 1);
473+ if (err < 0) {
474+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
475+ tdm_c->ut_info->uf_info.tdm_tx_clk);
476+ return err;
477+ }
478+ }
479+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_clk, "BRG")) {
480+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_clk);
481+ err = qe_setbrg(clock, 2048000, 1);
482+ if (err < 0) {
483+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
484+ tdm_c->ut_info->uf_info.tdm_rx_clk);
485+ return err;
486+ }
487+ }
488+ /*
489+ * TDM FSyncs = 4 KHz.
490+ */
491+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_sync, "BRG")) {
492+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_sync);
493+ err = qe_setbrg(clock, 4000, 1);
494+ if (err < 0) {
495+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
496+ tdm_c->ut_info->uf_info.tdm_tx_sync);
497+ return err;
498+ }
499+ }
500+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_sync, "BRG")) {
501+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_sync);
502+ err = qe_setbrg(clock, 4000, 1);
503+ if (err < 0) {
504+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
505+ tdm_c->ut_info->uf_info.tdm_rx_sync);
506+ return err;
507+ }
508+ }
509+
510+ tdm_c->ut_info->uf_info.uccm_mask = (u32)
511+ ((UCC_TRANS_UCCE_RXB | UCC_TRANS_UCCE_BSY) << 16);
512+
513+ if (ucc_fast_init(&(tdm_c->ut_info->uf_info), &tdm_c->uf_private)) {
514+ printk(KERN_ERR "%s: Failed to init uccf\n", __FUNCTION__);
515+ return -ENOMEM;
516+ }
517+
518+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
519+
520+ /* Write to QE CECR, UCCx channel to Stop Transmission */
521+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
522+ qe_issue_cmd(QE_STOP_TX, cecr_subblock,
523+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
524+
525+ pram_offset = qe_muram_alloc(UCC_TRANSPARENT_PRAM_SIZE,
526+ ALIGNMENT_OF_UCC_SLOW_PRAM);
527+ if (IS_ERR_VALUE(pram_offset)) {
528+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for"
529+ " transparent UCC\n", __FUNCTION__);
530+ ret = -ENOMEM;
531+ goto pram_alloc_error;
532+ }
533+
534+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
535+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
536+ QE_CR_PROTOCOL_UNSPECIFIED, pram_offset);
537+
538+ tdm_c->ucc_pram = qe_muram_addr(pram_offset);
539+ tdm_c->ucc_pram_offset = pram_offset;
540+
541+ /*
542+ * zero-out pram, this will also ensure RSTATE, TSTATE are cleared, also
543+ * DISFC & CRCEC counters will be initialized.
544+ */
545+ memset(tdm_c->ucc_pram, 0, sizeof(struct ucc_transparent_pram));
546+
547+ /* rbase, tbase alignment is 8. */
548+ rxbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
549+ QE_ALIGNMENT_OF_BD);
550+ if (IS_ERR_VALUE(rxbdt_offset)) {
551+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for RxBDs\n",
552+ __FUNCTION__);
553+ ret = -ENOMEM;
554+ goto rxbd_alloc_error;
555+ }
556+ txbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
557+ QE_ALIGNMENT_OF_BD);
558+ if (IS_ERR_VALUE(txbdt_offset)) {
559+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for TxBDs\n",
560+ __FUNCTION__);
561+ ret = -ENOMEM;
562+ goto txbd_alloc_error;
563+ }
564+ tdm_c->tx_bd = qe_muram_addr(txbdt_offset);
565+ tdm_c->rx_bd = qe_muram_addr(rxbdt_offset);
566+
567+ tdm_c->tx_bd_offset = txbdt_offset;
568+ tdm_c->rx_bd_offset = rxbdt_offset;
569+
570+ rx_bd = tdm_c->rx_bd;
571+ tx_bd = tdm_c->tx_bd;
572+
573+ out_be32(&tdm_c->ucc_pram->rbase, (u32) immrbar_virt_to_phys(rx_bd));
574+ out_be32(&tdm_c->ucc_pram->tbase, (u32) immrbar_virt_to_phys(tx_bd));
575+
576+ for (i = 0; i < NR_BUFS - 1; i++) {
577+ bd_status = (u16) ((R_E | R_CM | R_I) >> 16);
578+ bd_len = 0;
579+ out_be16(&rx_bd->length, bd_len);
580+ out_be16(&rx_bd->status, bd_status);
581+ out_be32(&rx_bd->buf,
582+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
583+ rx_bd += 1;
584+
585+ bd_status = (u16) ((T_R | T_CM) >> 16);
586+ bd_len = SAMPLE_DEPTH * act_num_ts;
587+ out_be16(&tx_bd->length, bd_len);
588+ out_be16(&tx_bd->status, bd_status);
589+ out_be32(&tx_bd->buf,
590+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
591+ tx_bd += 1;
592+ }
593+
594+ bd_status = (u16) ((R_E | R_CM | R_I | R_W) >> 16);
595+ bd_len = 0;
596+ out_be16(&rx_bd->length, bd_len);
597+ out_be16(&rx_bd->status, bd_status);
598+ out_be32(&rx_bd->buf,
599+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
600+
601+ bd_status = (u16) ((T_R | T_CM | T_W) >> 16);
602+ bd_len = SAMPLE_DEPTH * act_num_ts;
603+ out_be16(&tx_bd->length, bd_len);
604+ out_be16(&tx_bd->status, bd_status);
605+ out_be32(&tx_bd->buf,
606+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
607+
608+ config_si(tdm_c);
609+
610+ setbits32(&qe_immr->ic.qimr, (0x80000000UL >> ucc));
611+
612+ rx_ucode_buf_offset = qe_muram_alloc(32, 32);
613+ if (IS_ERR_VALUE(rx_ucode_buf_offset)) {
614+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Rx"
615+ " ucode buf\n", __FUNCTION__);
616+ ret = -ENOMEM;
617+ goto rxucode_buf_alloc_error;
618+ }
619+
620+ tx_ucode_buf_offset = qe_muram_alloc(32, 32);
621+ if (IS_ERR_VALUE(tx_ucode_buf_offset)) {
622+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Tx"
623+ " ucode buf\n", __FUNCTION__);
624+ ret = -ENOMEM;
625+ goto txucode_buf_alloc_error;
626+ }
627+ out_be16(&tdm_c->ucc_pram->riptr, (u16) rx_ucode_buf_offset);
628+ out_be16(&tdm_c->ucc_pram->tiptr, (u16) tx_ucode_buf_offset);
629+
630+ tdm_c->rx_ucode_buf_offset = rx_ucode_buf_offset;
631+ tdm_c->tx_ucode_buf_offset = tx_ucode_buf_offset;
632+
633+ /*
634+ * set the receive buffer descriptor maximum size to be
635+ * SAMPLE_DEPTH * number of active RX channels
636+ */
637+ out_be16(&tdm_c->ucc_pram->mrblr, (u16) SAMPLE_DEPTH * act_num_ts);
638+
639+ /*
640+ * enable snooping and BE byte ordering on the UCC pram's
641+ * tstate & rstate registers.
642+ */
643+ out_be32(&tdm_c->ucc_pram->tstate, 0x30000000UL);
644+ out_be32(&tdm_c->ucc_pram->rstate, 0x30000000UL);
645+
646+ /*Put UCC transparent controller into serial interface mode. */
647+ out_be32(&tdm_c->uf_regs->upsmr, 0);
648+
649+ /* Reset TX and RX for UCCx */
650+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
651+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
652+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
653+
654+ return 0;
655+
656+txucode_buf_alloc_error:
657+ qe_muram_free(rx_ucode_buf_offset);
658+rxucode_buf_alloc_error:
659+ qe_muram_free(txbdt_offset);
660+txbd_alloc_error:
661+ qe_muram_free(rxbdt_offset);
662+rxbd_alloc_error:
663+ qe_muram_free(pram_offset);
664+pram_alloc_error:
665+ ucc_fast_free(tdm_c->uf_private);
666+ return ret;
667+}
668+
669+static void tdm_deinit(struct tdm_ctrl *tdm_c)
670+{
671+ qe_muram_free(tdm_c->rx_ucode_buf_offset);
672+ qe_muram_free(tdm_c->tx_ucode_buf_offset);
673+
674+ if (tdm_c->rx_bd_offset) {
675+ qe_muram_free(tdm_c->rx_bd_offset);
676+ tdm_c->rx_bd = NULL;
677+ tdm_c->rx_bd_offset = 0;
678+ }
679+ if (tdm_c->tx_bd_offset) {
680+ qe_muram_free(tdm_c->tx_bd_offset);
681+ tdm_c->tx_bd = NULL;
682+ tdm_c->tx_bd_offset = 0;
683+ }
684+ if (tdm_c->ucc_pram_offset) {
685+ qe_muram_free(tdm_c->ucc_pram_offset);
686+ tdm_c->ucc_pram = NULL;
687+ tdm_c->ucc_pram_offset = 0;
688+ }
689+}
690+
691+
692+static irqreturn_t tdm_isr(int irq, void *dev_id)
693+{
694+ u8 *input_tdm_buffer, *output_tdm_buffer;
695+ u32 txb, rxb;
696+ u32 ucc;
697+ register u32 ucce = 0;
698+ struct tdm_ctrl *tdm_c;
699+ tdm_c = (struct tdm_ctrl *)dev_id;
700+
701+ tdm_c->tdm_icnt++;
702+ ucc = tdm_c->ut_info->uf_info.ucc_num;
703+ input_tdm_buffer = tdm_c->tdm_input_data;
704+ output_tdm_buffer = tdm_c->tdm_output_data;
705+
706+ if (in_be32(tdm_c->uf_private->p_ucce) &
707+ (UCC_TRANS_UCCE_BSY << 16)) {
708+ out_be32(tdm_c->uf_private->p_ucce,
709+ (UCC_TRANS_UCCE_BSY << 16));
710+ pr_info("%s: From tdm isr busy interrupt\n",
711+ __FUNCTION__);
712+ dump_ucc(tdm_c);
713+
714+ return IRQ_HANDLED;
715+ }
716+
717+ if (tdm_c->tdm_flag == 1) {
718+ /* track phases for Rx/Tx */
719+ tdm_c->phase_rx += 1;
720+ if (tdm_c->phase_rx == MAX_PHASE)
721+ tdm_c->phase_rx = 0;
722+
723+ tdm_c->phase_tx += 1;
724+ if (tdm_c->phase_tx == MAX_PHASE)
725+ tdm_c->phase_tx = 0;
726+
727+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
728+ {
729+ u32 temp_rx, temp_tx, phase_tx, phase_rx;
730+ int i;
731+ phase_rx = tdm_c->phase_rx;
732+ phase_tx = tdm_c->phase_tx;
733+ if (phase_rx == 0)
734+ phase_rx = MAX_PHASE;
735+ else
736+ phase_rx -= 1;
737+ if (phase_tx == 0)
738+ phase_tx = MAX_PHASE;
739+ else
740+ phase_tx -= 1;
741+ temp_rx = phase_rx * SAMPLE_DEPTH * ACTIVE_CH;
742+ temp_tx = phase_tx * SAMPLE_DEPTH * ACTIVE_CH;
743+
744+ /*check if loopback received data on TS0 is correct. */
745+ pr_debug("%s: check if loopback received data on TS0"
746+ " is correct\n", __FUNCTION__);
747+ pr_debug("%d,%d ", phase_rx, phase_tx);
748+ for (i = 0; i < 8; i++)
749+ pr_debug("%1d,%1d ",
750+ input_tdm_buffer[temp_rx + i],
751+ output_tdm_buffer[temp_tx + i]);
752+ pr_debug("\n");
753+ }
754+#endif
755+
756+ /* schedule BH */
757+ wake_up_interruptible(&tdm_c->wakeup_event);
758+ } else {
759+ if (tdm_c->tdm_icnt == STUTTER_INT_CNT) {
760+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
761+ in_be32(&tdm_c->ucc_pram->tbase);
762+ rxb = in_be32(&tdm_c->ucc_pram->rbptr) -
763+ in_be32(&tdm_c->ucc_pram->rbase);
764+ tdm_c->phase_tx = txb / sizeof(struct qe_bd);
765+ tdm_c->phase_rx = rxb / sizeof(struct qe_bd);
766+
767+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
768+ tdm_c->phase_tx = tdm_c->phase_rx;
769+#endif
770+
771+ /* signal "stuttering" period is over */
772+ tdm_c->tdm_flag = 1;
773+
774+ pr_debug("%s: stuttering period is over\n",
775+ __FUNCTION__);
776+
777+ if (in_be32(tdm_c->uf_private->p_ucce) &
778+ (UCC_TRANS_UCCE_TXE << 16)) {
779+ u32 cecr_subblock;
780+ out_be32(tdm_c->uf_private->p_ucce,
781+ (UCC_TRANS_UCCE_TXE << 16));
782+ pr_debug("%s: From tdm isr txe interrupt\n",
783+ __FUNCTION__);
784+
785+ cecr_subblock =
786+ ucc_fast_get_qe_cr_subblock(ucc);
787+ qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
788+ (u8) QE_CR_PROTOCOL_UNSPECIFIED,
789+ 0);
790+ }
791+ }
792+ }
793+
794+ ucce = (in_be32(tdm_c->uf_private->p_ucce)
795+ & in_be32(tdm_c->uf_private->p_uccm));
796+
797+ out_be32(tdm_c->uf_private->p_ucce, ucce);
798+
799+ return IRQ_HANDLED;
800+}
801+
802+static int tdm_start(struct tdm_ctrl *tdm_c)
803+{
804+ if (request_irq(tdm_c->ut_info->uf_info.irq, tdm_isr,
805+ 0, "tdm", tdm_c)) {
806+ printk(KERN_ERR "%s: request_irq for tdm_isr failed\n",
807+ __FUNCTION__);
808+ return -ENODEV;
809+ }
810+
811+ ucc_fast_enable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
812+
813+ pr_info("%s 16-bit linear pcm mode active with"
814+ " slots 0 & 2\n", __FUNCTION__);
815+
816+ dump_siram(tdm_c);
817+ dump_ucc(tdm_c);
818+
819+ setbits8(&(qe_immr->si1.siglmr1_h), (0x1 << tdm_c->tdm_port));
820+ pr_info("%s UCC based TDM enabled\n", __FUNCTION__);
821+
822+ return 0;
823+}
824+
825+static void tdm_stop(struct tdm_ctrl *tdm_c)
826+{
827+ u32 port, si;
828+ u32 ucc;
829+ u32 cecr_subblock;
830+
831+ port = tdm_c->tdm_port;
832+ si = tdm_c->si;
833+ ucc = tdm_c->ut_info->uf_info.ucc_num;
834+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
835+
836+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
837+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
838+ qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
839+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
840+
841+ clrbits8(&qe_immr->si1.siglmr1_h, (0x1 << port));
842+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX);
843+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_TX);
844+ free_irq(tdm_c->ut_info->uf_info.irq, tdm_c);
845+}
846+
847+
848+static void config_tdm(struct tdm_ctrl *tdm_c)
849+{
850+ u32 i, j, k;
851+
852+ j = 0;
853+ k = 0;
854+
855+ /* Set Mask Bits */
856+ for (i = 0; i < ACTIVE_CH; i++) {
857+ tdm_c->tx_mask[k] |= (1 << j);
858+ tdm_c->rx_mask[k] |= (1 << j);
859+ j++;
860+ if (j >= 16) {
861+ j = 0;
862+ k++;
863+ }
864+ }
865+ /* physical number of slots in a frame */
866+ tdm_c->physical_num_ts = NUM_TS;
867+
868+ /* common receive and transmit pins */
869+ tdm_c->cfg_ctrl.com_pin = 1;
870+
871+ /* L1R/TSYNC active logic "1" */
872+ tdm_c->cfg_ctrl.fr_sync_level = 0;
873+
874+ /*
875+ * TX data on rising edge of clock
876+ * RX data on falling edge
877+ */
878+ tdm_c->cfg_ctrl.clk_edge = 0;
879+
880+ /* Frame sync sampled on falling edge */
881+ tdm_c->cfg_ctrl.fr_sync_edge = 0;
882+
883+ /* no bit delay */
884+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 0;
885+
886+ /* no bit delay */
887+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 0;
888+
889+#ifndef CONFIG_TDM_HW_LB_TSA_SLIC
890+ if (tdm_c->leg_slic) {
891+ /* Need 1 bit delay for Legrity SLIC */
892+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 1;
893+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 1;
894+ pr_info("%s Delay for Legerity!\n", __FUNCTION__);
895+ }
896+#endif
897+
898+ tdm_c->cfg_ctrl.active_num_ts = ACTIVE_CH;
899+}
900+
901+static void tdm_read(u32 client_id, short chn_id, short *pcm_buffer,
902+ short len)
903+{
904+ int i;
905+ u32 phase_rx;
906+ /* point to where to start for the current phase data processing */
907+ u32 temp_rx;
908+
909+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
910+
911+ u16 *input_tdm_buffer =
912+ (u16 *)tdm_c->tdm_input_data;
913+
914+ phase_rx = tdm_c->phase_rx;
915+ if (phase_rx == 0)
916+ phase_rx = MAX_PHASE;
917+ else
918+ phase_rx -= 1;
919+
920+ temp_rx = phase_rx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
921+
922+#ifdef UCC_CACHE_SNOOPING_DISABLED
923+ flush_dcache_range((size_t) &input_tdm_buffer[temp_rx],
924+ (size_t) &input_tdm_buffer[temp_rx +
925+ SAMPLE_DEPTH * ACTIVE_CH]);
926+#endif
927+ for (i = 0; i < len; i++)
928+ pcm_buffer[i] =
929+ input_tdm_buffer[i * EFF_ACTIVE_CH + temp_rx + chn_id];
930+
931+}
932+
933+static void tdm_write(u32 client_id, short chn_id, short *pcm_buffer,
934+ short len)
935+{
936+ int i;
937+ int phase_tx;
938+ u32 txb;
939+ /* point to where to start for the current phase data processing */
940+ int temp_tx;
941+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
942+
943+ u16 *output_tdm_buffer;
944+ output_tdm_buffer = (u16 *)tdm_c->tdm_output_data;
945+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
946+ in_be32(&tdm_c->ucc_pram->tbase);
947+ phase_tx = txb / sizeof(struct qe_bd);
948+
949+ if (phase_tx == 0)
950+ phase_tx = MAX_PHASE;
951+ else
952+ phase_tx -= 1;
953+
954+ temp_tx = phase_tx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
955+
956+ for (i = 0; i < len; i++)
957+ output_tdm_buffer[i * EFF_ACTIVE_CH + temp_tx + chn_id] =
958+ pcm_buffer[i];
959+
960+#ifdef UCC_CACHE_SNOOPING_DISABLED
961+ flush_dcache_range((size_t) &output_tdm_buffer[temp_tx],
962+ (size_t) &output_tdm_buffer[temp_tx + SAMPLE_DEPTH *
963+ ACTIVE_CH]);
964+#endif
965+}
966+
967+
968+static int tdm_register_client(struct tdm_client *tdm_client)
969+{
970+ u32 i;
971+ if (num_tdm_clients == num_tdm_devices) {
972+ printk(KERN_ERR "all TDM devices busy\n");
973+ return -EBUSY;
974+ }
975+
976+ for (i = 0; i < num_tdm_devices; i++) {
977+ if (!tdm_ctrl[i]->device_busy) {
978+ tdm_ctrl[i]->device_busy = 1;
979+ break;
980+ }
981+ }
982+ num_tdm_clients++;
983+ tdm_client->client_id = i;
984+ tdm_client->tdm_read = tdm_read;
985+ tdm_client->tdm_write = tdm_write;
986+ tdm_client->wakeup_event =
987+ &(tdm_ctrl[i]->wakeup_event);
988+ return 0;
989+}
990+EXPORT_SYMBOL_GPL(tdm_register_client);
991+
992+static int tdm_deregister_client(struct tdm_client *tdm_client)
993+{
994+ num_tdm_clients--;
995+ tdm_ctrl[tdm_client->client_id]->device_busy = 0;
996+ return 0;
997+}
998+EXPORT_SYMBOL_GPL(tdm_deregister_client);
999+
1000+static int ucc_tdm_probe(struct of_device *ofdev,
1001+ const struct of_device_id *match)
1002+{
1003+ struct device_node *np = ofdev->node;
1004+ struct resource res;
1005+ const unsigned int *prop;
1006+ u32 ucc_num, device_num, err, ret = 0;
1007+ struct device_node *np_tmp;
1008+ dma_addr_t physaddr;
1009+ void *tdm_buff;
1010+ struct ucc_tdm_info *ut_info;
1011+
1012+ prop = of_get_property(np, "device-id", NULL);
1013+ if (prop == NULL) {
1014+ printk(KERN_ERR "ucc_tdm: device-id missing\n");
1015+ return -ENODEV;
1016+ }
1017+
1018+ ucc_num = *prop - 1;
1019+ if ((ucc_num < 0) || (ucc_num > 7))
1020+ return -ENODEV;
1021+
1022+ ut_info = &utdm_info[ucc_num];
1023+ if (ut_info->ucc_busy) {
1024+ printk(KERN_ERR "ucc_tdm: UCC in use by another TDM driver"
1025+ "instance\n");
1026+ return -EBUSY;
1027+ }
1028+ if (num_tdm_devices == MAX_NUM_TDM_DEVICES) {
1029+ printk(KERN_ERR "ucc_tdm: All TDM devices already"
1030+ " initialized\n");
1031+ return -ENODEV;
1032+ }
1033+
1034+ ut_info->ucc_busy = 1;
1035+ tdm_ctrl[num_tdm_devices++] =
1036+ kzalloc(sizeof(struct tdm_ctrl), GFP_KERNEL);
1037+ if (!tdm_ctrl[num_tdm_devices - 1]) {
1038+ printk(KERN_ERR "ucc_tdm: no memory to allocate for"
1039+ " tdm control structure\n");
1040+ num_tdm_devices--;
1041+ return -ENOMEM;
1042+ }
1043+ device_num = num_tdm_devices - 1;
1044+
1045+ tdm_ctrl[device_num]->device = &ofdev->dev;
1046+ tdm_ctrl[device_num]->ut_info = ut_info;
1047+
1048+ tdm_ctrl[device_num]->ut_info->uf_info.ucc_num = ucc_num;
1049+
1050+ prop = of_get_property(np, "fsl,tdm-num", NULL);
1051+ if (prop == NULL) {
1052+ ret = -EINVAL;
1053+ goto get_property_error;
1054+ }
1055+
1056+ tdm_ctrl[device_num]->tdm_port = *prop - 1;
1057+
1058+ if (tdm_ctrl[device_num]->tdm_port > 3) {
1059+ ret = -EINVAL;
1060+ goto get_property_error;
1061+ }
1062+
1063+ prop = of_get_property(np, "fsl,si-num", NULL);
1064+ if (prop == NULL) {
1065+ ret = -EINVAL;
1066+ goto get_property_error;
1067+ }
1068+
1069+ tdm_ctrl[device_num]->si = *prop - 1;
1070+
1071+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk =
1072+ of_get_property(np, "fsl,tdm-tx-clk", NULL);
1073+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk == NULL) {
1074+ ret = -EINVAL;
1075+ goto get_property_error;
1076+ }
1077+
1078+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk =
1079+ of_get_property(np, "fsl,tdm-rx-clk", NULL);
1080+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk == NULL) {
1081+ ret = -EINVAL;
1082+ goto get_property_error;
1083+ }
1084+
1085+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync =
1086+ of_get_property(np, "fsl,tdm-tx-sync", NULL);
1087+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync == NULL) {
1088+ ret = -EINVAL;
1089+ goto get_property_error;
1090+ }
1091+
1092+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync =
1093+ of_get_property(np, "fsl,tdm-rx-sync", NULL);
1094+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync == NULL) {
1095+ ret = -EINVAL;
1096+ goto get_property_error;
1097+ }
1098+
1099+ tdm_ctrl[device_num]->ut_info->uf_info.irq =
1100+ irq_of_parse_and_map(np, 0);
1101+ err = of_address_to_resource(np, 0, &res);
1102+ if (err) {
1103+ ret = -EINVAL;
1104+ goto get_property_error;
1105+ }
1106+ tdm_ctrl[device_num]->ut_info->uf_info.regs = res.start;
1107+ tdm_ctrl[device_num]->uf_regs = of_iomap(np, 0);
1108+
1109+ np_tmp = NULL;
1110+ np_tmp = of_find_compatible_node(np_tmp, "slic", "legerity-slic");
1111+ if (np_tmp != NULL) {
1112+ tdm_ctrl[device_num]->leg_slic = 1;
1113+ of_node_put(np_tmp);
1114+ } else
1115+ tdm_ctrl[device_num]->leg_slic = 0;
1116+
1117+ config_tdm(tdm_ctrl[device_num]);
1118+
1119+ tdm_buff = dma_alloc_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1120+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
1121+ &physaddr, GFP_KERNEL);
1122+ if (!tdm_buff) {
1123+ printk(KERN_ERR "ucc-tdm: could not allocate buffer"
1124+ "descriptors\n");
1125+ ret = -ENOMEM;
1126+ goto alloc_error;
1127+ }
1128+
1129+ tdm_ctrl[device_num]->tdm_input_data = tdm_buff;
1130+ tdm_ctrl[device_num]->dma_input_addr = physaddr;
1131+
1132+ tdm_ctrl[device_num]->tdm_output_data = tdm_buff + NR_BUFS *
1133+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
1134+ tdm_ctrl[device_num]->dma_output_addr = physaddr + NR_BUFS *
1135+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
1136+
1137+ init_waitqueue_head(&(tdm_ctrl[device_num]->wakeup_event));
1138+
1139+ ret = tdm_init(tdm_ctrl[device_num]);
1140+ if (ret != 0)
1141+ goto tdm_init_error;
1142+
1143+ ret = tdm_start(tdm_ctrl[device_num]);
1144+ if (ret != 0)
1145+ goto tdm_start_error;
1146+
1147+ dev_set_drvdata(&(ofdev->dev), tdm_ctrl[device_num]);
1148+
1149+ pr_info("%s UCC based tdm module installed\n", __FUNCTION__);
1150+ return 0;
1151+
1152+tdm_start_error:
1153+ tdm_deinit(tdm_ctrl[device_num]);
1154+tdm_init_error:
1155+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1156+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
1157+ tdm_ctrl[device_num]->tdm_input_data,
1158+ tdm_ctrl[device_num]->dma_input_addr);
1159+
1160+alloc_error:
1161+ irq_dispose_mapping(tdm_ctrl[device_num]->ut_info->uf_info.irq);
1162+ iounmap(tdm_ctrl[device_num]->uf_regs);
1163+
1164+get_property_error:
1165+ num_tdm_devices--;
1166+ kfree(tdm_ctrl[device_num]);
1167+ ut_info->ucc_busy = 0;
1168+ return ret;
1169+}
1170+
1171+static int ucc_tdm_remove(struct of_device *ofdev)
1172+{
1173+ struct tdm_ctrl *tdm_c;
1174+ struct ucc_tdm_info *ut_info;
1175+ u32 ucc_num;
1176+
1177+ tdm_c = dev_get_drvdata(&(ofdev->dev));
1178+ dev_set_drvdata(&(ofdev->dev), NULL);
1179+ ucc_num = tdm_c->ut_info->uf_info.ucc_num;
1180+ ut_info = &utdm_info[ucc_num];
1181+ tdm_stop(tdm_c);
1182+ tdm_deinit(tdm_c);
1183+
1184+ ucc_fast_free(tdm_c->uf_private);
1185+
1186+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1187+ tdm_c->cfg_ctrl.active_num_ts,
1188+ tdm_c->tdm_input_data,
1189+ tdm_c->dma_input_addr);
1190+
1191+ irq_dispose_mapping(tdm_c->ut_info->uf_info.irq);
1192+ iounmap(tdm_c->uf_regs);
1193+
1194+ num_tdm_devices--;
1195+ kfree(tdm_c);
1196+
1197+ ut_info->ucc_busy = 0;
1198+
1199+ pr_info("%s UCC based tdm module uninstalled\n", __FUNCTION__);
1200+ return 0;
1201+}
1202+
1203+const struct of_device_id ucc_tdm_match[] = {
1204+ { .type = "tdm", .compatible = "fsl,ucc-tdm", },
1205+ {},
1206+};
1207+
1208+MODULE_DEVICE_TABLE(of, ucc_tdm_match);
1209+
1210+static struct of_platform_driver ucc_tdm_driver = {
1211+ .name = DRV_NAME,
1212+ .match_table = ucc_tdm_match,
1213+ .probe = ucc_tdm_probe,
1214+ .remove = ucc_tdm_remove,
1215+ .driver = {
1216+ .name = DRV_NAME,
1217+ .owner = THIS_MODULE,
1218+ },
1219+};
1220+
1221+static int __init ucc_tdm_init(void)
1222+{
1223+ u32 i;
1224+
1225+ pr_info("ucc_tdm: " DRV_DESC "\n");
1226+ for (i = 0; i < 8; i++)
1227+ memcpy(&(utdm_info[i]), &utdm_primary_info,
1228+ sizeof(utdm_primary_info));
1229+
1230+ return of_register_platform_driver(&ucc_tdm_driver);
1231+}
1232+
1233+static void __exit ucc_tdm_exit(void)
1234+{
1235+ of_unregister_platform_driver(&ucc_tdm_driver);
1236+}
1237+
1238+module_init(ucc_tdm_init);
1239+module_exit(ucc_tdm_exit);
1240+MODULE_AUTHOR("Freescale Semiconductor, Inc");
1241+MODULE_DESCRIPTION(DRV_DESC);
1242+MODULE_LICENSE("GPL");
1243--- a/drivers/misc/Makefile
1244@@ -10,6 +10,7 @@ obj-$(CONFIG_INTEL_MID_PTI) += pti.o
1245 obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
1246 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
1247 obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
1248+obj-$(CONFIG_UCC_TDM) += ucc_tdm.o
1249 obj-$(CONFIG_BMP085) += bmp085.o
1250 obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o
1251 obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o
1252--- a/drivers/misc/Kconfig
1253@@ -202,6 +202,20 @@ config ATMEL_SSC
1254
1255       If unsure, say N.
1256
1257+config UCC_TDM
1258+ tristate "Freescale UCC TDM Driver"
1259+ depends on QUICC_ENGINE && UCC_FAST
1260+ default n
1261+ help
1262+ The TDM driver is for UCC based TDM devices for example, TDM device on
1263+ MPC832x RDB. Select it to run PowerVoIP on MPC832x RDB board.
1264+ The TDM driver can interface with SLIC kind of devices to transmit
1265+ and receive TDM samples. The TDM driver receives Time Division
1266+ multiplexed samples(for different channels) from the SLIC device,
1267+ demutiplexes them and sends them to the upper layers. At the transmit
1268+ end the TDM drivers receives samples for different channels, it
1269+ multiplexes them and sends them to the SLIC device.
1270+
1271 config ENCLOSURE_SERVICES
1272     tristate "Enclosure Services"
1273     default n
1274--- a/arch/powerpc/include/asm/ucc_fast.h
1275@@ -150,6 +150,10 @@ struct ucc_fast_info {
1276     enum ucc_fast_rx_decoding_method renc;
1277     enum ucc_fast_transparent_tcrc tcrc;
1278     enum ucc_fast_sync_len synl;
1279+ char *tdm_rx_clk;
1280+ char *tdm_tx_clk;
1281+ char *tdm_rx_sync;
1282+ char *tdm_tx_sync;
1283 };
1284
1285 struct ucc_fast_private {
1286--- a/arch/powerpc/include/asm/qe.h
1287@@ -670,6 +670,14 @@ struct ucc_slow_pram {
1288 #define UCC_GETH_UCCE_RXF1 0x00000002
1289 #define UCC_GETH_UCCE_RXF0 0x00000001
1290
1291+/* Transparent UCC Event Register (UCCE) */
1292+#define UCC_TRANS_UCCE_GRA 0x0080
1293+#define UCC_TRANS_UCCE_TXE 0x0010
1294+#define UCC_TRANS_UCCE_RXF 0x0008
1295+#define UCC_TRANS_UCCE_BSY 0x0004
1296+#define UCC_TRANS_UCCE_TXB 0x0002
1297+#define UCC_TRANS_UCCE_RXB 0x0001
1298+
1299 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
1300 #define UCC_UART_UPSMR_FLC 0x8000
1301 #define UCC_UART_UPSMR_SL 0x4000
target/linux/mpc83xx/patches-3.7/200-powerpc-add-rbppc-support.patch
1--- a/arch/powerpc/boot/Makefile
2@@ -89,7 +89,8 @@ src-plat-$(CONFIG_44x) += treeboot-ebony
3 src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
4 src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
5 src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
6-src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
7+src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c \
8+ rb600.c rb333.c
9 src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
10 src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
11                     cuboot-c2k.c gamecube-head.S \
12@@ -261,6 +262,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
13 image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
14 image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
15 image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
16+image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
17+ dtbImage.rb333
18
19 # Board ports in arch/powerpc/platform/85xx/Kconfig
20 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
21--- /dev/null
22@@ -0,0 +1,283 @@
23+/*
24+ * RouterBOARD 600 series Device Tree Source
25+ *
26+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
27+ *
28+ * This program is free software; you can redistribute it and/or modify it
29+ * under the terms of the GNU General Public License as published by the
30+ * Free Software Foundation; either version 2 of the License, or (at your
31+ * option) any later version.
32+ */
33+
34+/dts-v1/;
35+
36+/ {
37+ model = "RB600";
38+ compatible = "MPC83xx";
39+ #address-cells = <1>;
40+ #size-cells = <1>;
41+
42+ aliases {
43+ ethernet0 = &enet0;
44+ ethernet1 = &enet1;
45+ pci0 = &pci0;
46+ };
47+
48+ chosen {
49+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
50+ linux,stdout-path = "/soc8343@e0000000/serial@4500";
51+ };
52+
53+ cpus {
54+ #address-cells = <1>;
55+ #size-cells = <0>;
56+
57+ PowerPC,8343E@0 {
58+ device_type = "cpu";
59+ reg = <0x0>;
60+ d-cache-line-size = <0x20>;
61+ i-cache-line-size = <0x20>;
62+ d-cache-size = <0x8000>;
63+ i-cache-size = <0x8000>;
64+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
65+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
66+ };
67+ };
68+
69+ memory {
70+ device_type = "memory";
71+ reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
72+ };
73+
74+ cf@f9200000 {
75+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
76+ interrupt-at-level = <0x0>;
77+ interrupt-parent = <&ipic>;
78+ interrupts = <0x16 0x8>;
79+ lbc_extra_divider = <0x1>;
80+ reg = <0xf9200000 0x200000>;
81+ device_type = "rb,cf";
82+ };
83+
84+ cf@f9000000 {
85+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
86+ interrupt-at-level = <0x0>;
87+ interrupt-parent = <&ipic>;
88+ interrupts = <0x14 0x8>;
89+ lbc_extra_divider = <0x1>;
90+ reg = <0xf9000000 0x200000>;
91+ device_type = "rb,cf";
92+ };
93+
94+ flash {
95+ reg = <0xff800000 0x20000>;
96+ };
97+
98+ nnand {
99+ reg = <0xf0000000 0x1000>;
100+ };
101+
102+ nand {
103+ ale = <&gpio 0x6>;
104+ cle = <&gpio 0x5>;
105+ nce = <&gpio 0x4>;
106+ rdy = <&gpio 0x3>;
107+ reg = <0xf8000000 0x1000>;
108+ device_type = "rb,nand";
109+ };
110+
111+ fancon {
112+ interrupt-parent = <&ipic>;
113+ interrupts = <0x17 0x8>;
114+ sense = <&gpio 0x7>;
115+ fan_on = <&gpio 0x9>;
116+ };
117+
118+ pci0: pci@e0008500 {
119+ device_type = "pci";
120+ compatible = "fsl,mpc8349-pci";
121+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
122+ #address-cells = <3>;
123+ #size-cells = <2>;
124+ #interrupt-cells = <1>;
125+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
126+ bus-range = <0x0 0x0>;
127+ interrupt-map = <
128+ 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
129+ 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
130+ 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
131+ 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
132+ 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
133+ 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
134+ 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
135+ 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
136+ 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
137+ 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
138+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
139+ 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
140+ 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
141+ 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
142+ 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
143+ 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
144+ 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
145+ 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
146+ 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
147+ 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
148+ 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
149+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
150+ interrupt-parent = <&ipic>;
151+ };
152+
153+ soc8343@e0000000 {
154+ #address-cells = <1>;
155+ #size-cells = <1>;
156+ device_type = "soc";
157+ compatible = "simple-bus";
158+ ranges = <0x0 0xe0000000 0x100000>;
159+ reg = <0xe0000000 0x200>;
160+ bus-frequency = <0x1>;
161+
162+ led {
163+ user_led = <0x400 0x8>;
164+ };
165+
166+ beeper {
167+ reg = <0x500 0x100>;
168+ };
169+
170+ gpio: gpio@0 {
171+ reg = <0xc08 0x4>;
172+ device-id = <0x0>;
173+ compatible = "gpio";
174+ device_type = "gpio";
175+ };
176+
177+ dma@82a8 {
178+ #address-cells = <1>;
179+ #size-cells = <1>;
180+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
181+ reg = <0x82a8 4>;
182+ ranges = <0 0x8100 0x1a8>;
183+ interrupt-parent = <&ipic>;
184+ interrupts = <71 8>;
185+ cell-index = <0>;
186+ dma-channel@0 {
187+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
188+ reg = <0 0x80>;
189+ cell-index = <0>;
190+ interrupt-parent = <&ipic>;
191+ interrupts = <71 8>;
192+ };
193+ dma-channel@80 {
194+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
195+ reg = <0x80 0x80>;
196+ cell-index = <1>;
197+ interrupt-parent = <&ipic>;
198+ interrupts = <71 8>;
199+ };
200+ dma-channel@100 {
201+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
202+ reg = <0x100 0x80>;
203+ cell-index = <2>;
204+ interrupt-parent = <&ipic>;
205+ interrupts = <71 8>;
206+ };
207+ dma-channel@180 {
208+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
209+ reg = <0x180 0x28>;
210+ cell-index = <3>;
211+ interrupt-parent = <&ipic>;
212+ interrupts = <71 8>;
213+ };
214+ };
215+
216+ enet0: ethernet@25000 {
217+ #address-cells = <1>;
218+ #size-cells = <1>;
219+ cell-index = <0>;
220+ phy-handle = <&phy0>;
221+ tbi-handle = <&tbi0>;
222+ interrupt-parent = <&ipic>;
223+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
224+ local-mac-address = [00 00 00 00 00 00];
225+ reg = <0x25000 0x1000>;
226+ ranges = <0x0 0x25000 0x1000>;
227+ compatible = "gianfar";
228+ model = "TSEC";
229+ device_type = "network";
230+
231+ mdio@520 {
232+ #address-cells = <1>;
233+ #size-cells = <0>;
234+ compatible = "fsl,gianfar-tbi";
235+ reg = <0x520 0x20>;
236+
237+ tbi0: tbi-phy@11 {
238+ reg = <0x11>;
239+ device_type = "tbi-phy";
240+ };
241+ };
242+ };
243+
244+ enet1: ethernet@24000 {
245+ #address-cells = <1>;
246+ #size-cells = <1>;
247+ cell-index = <1>;
248+ phy-handle = <&phy1>;
249+ tbi-handle = <&tbi1>;
250+ interrupt-parent = <&ipic>;
251+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
252+ local-mac-address = [00 00 00 00 00 00];
253+ reg = <0x24000 0x1000>;
254+ ranges = <0x0 0x24000 0x1000>;
255+ compatible = "gianfar";
256+ model = "TSEC";
257+ device_type = "network";
258+
259+ mdio@520 {
260+ #size-cells = <0x0>;
261+ #address-cells = <0x1>;
262+ reg = <0x520 0x20>;
263+ compatible = "fsl,gianfar-mdio";
264+
265+ phy0: ethernet-phy@0 {
266+ device_type = "ethernet-phy";
267+ reg = <0x0>;
268+ };
269+
270+ phy1: ethernet-phy@1 {
271+ device_type = "ethernet-phy";
272+ reg = <0x1>;
273+ };
274+
275+ tbi1: tbi-phy@11 {
276+ reg = <0x11>;
277+ device_type = "tbi-phy";
278+ };
279+ };
280+ };
281+
282+ ipic: pic@700 {
283+ interrupt-controller;
284+ #address-cells = <0>;
285+ #interrupt-cells = <2>;
286+ reg = <0x700 0x100>;
287+ device_type = "ipic";
288+ };
289+
290+ serial@4500 {
291+ interrupt-parent = <&ipic>;
292+ interrupts = <0x9 0x8>;
293+ clock-frequency = <0xfe4f840>;
294+ reg = <0x4500 0x100>;
295+ compatible = "ns16550";
296+ device_type = "serial";
297+ };
298+
299+ wdt@200 {
300+ reg = <0x200 0x100>;
301+ compatible = "mpc83xx_wdt";
302+ device_type = "watchdog";
303+ };
304+ };
305+};
306--- /dev/null
307@@ -0,0 +1,70 @@
308+/*
309+ * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
310+ *
311+ * Author: Michael Guntsche <mike@it-loops.com>
312+ *
313+ * Copyright (c) 2009 Michael Guntsche
314+ *
315+ * This program is free software; you can redistribute it and/or modify it
316+ * under the terms of the GNU General Public License version 2 as published
317+ * by the Free Software Foundation.
318+ */
319+
320+#include "ops.h"
321+#include "types.h"
322+#include "io.h"
323+#include "stdio.h"
324+#include <libfdt.h>
325+
326+BSS_STACK(4*1024);
327+
328+u64 memsize64;
329+const void *fw_dtb;
330+
331+static void rb600_fixups(void)
332+{
333+ const u32 *reg, *timebase, *clock;
334+ int node, size;
335+
336+ dt_fixup_memory(0, memsize64);
337+
338+ /* Set the MAC addresses. */
339+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
340+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
341+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
342+
343+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
344+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
345+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
346+
347+ /* Find the CPU timebase and clock frequencies. */
348+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
349+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
350+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
351+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
352+
353+}
354+
355+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
356+ unsigned long r6, unsigned long r7)
357+{
358+ const u32 *reg;
359+ int node, size;
360+
361+ fw_dtb = (const void *)r3;
362+
363+ /* Find the memory range. */
364+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
365+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
366+ memsize64 = reg[1];
367+
368+ /* Now we have the memory size; initialize the heap. */
369+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
370+
371+ /* Prepare the device tree and find the console. */
372+ fdt_init(_dtb_start);
373+ serial_console_init();
374+
375+ /* Remaining fixups... */
376+ platform_ops.fixups = rb600_fixups;
377+}
378--- a/arch/powerpc/boot/wrapper
379@@ -217,7 +217,7 @@ ps3)
380     make_space=n
381     pie=
382     ;;
383-ep88xc|ep405|ep8248e)
384+ep88xc|ep405|ep8248e|rb600|rb333)
385     platformo="$object/fixed-head.o $object/$platform.o"
386     binary=y
387     ;;
388--- a/arch/powerpc/platforms/83xx/Kconfig
389@@ -38,6 +38,15 @@ config MPC832x_RDB
390     help
391       This option enables support for the MPC8323 RDB board.
392
393+config RB_PPC
394+ bool "MikroTik RouterBOARD 333/600 series"
395+ select DEFAULT_UIMAGE
396+ select QUICC_ENGINE
397+ select PPC_MPC832x
398+ select PPC_MPC834x
399+ help
400+ This option enables support for MikroTik RouterBOARD 333/600 series boards.
401+
402 config MPC834x_MDS
403     bool "Freescale MPC834x MDS"
404     select DEFAULT_UIMAGE
405--- /dev/null
406@@ -0,0 +1,426 @@
407+
408+/*
409+ * RouterBOARD 333 series Device Tree Source
410+ *
411+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
412+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
413+ *
414+ * This program is free software; you can redistribute it and/or modify it
415+ * under the terms of the GNU General Public License as published by the
416+ * Free Software Foundation; either version 2 of the License, or (at your
417+ * option) any later version.
418+ *
419+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
420+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
421+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
422+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
423+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
424+ *
425+ */
426+
427+
428+/dts-v1/;
429+
430+/ {
431+ model = "RB333";
432+ compatible = "MPC83xx";
433+ #size-cells = <1>;
434+ #address-cells = <1>;
435+
436+ aliases {
437+ ethernet0 = &enet0;
438+ ethernet1 = &enet1;
439+ ethernet2 = &enet2;
440+ pci0 = &pci0;
441+ };
442+
443+ chosen {
444+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
445+ // linux,platform = <0x8062>;
446+ // linux,initrd = <0x488000 0x0>;
447+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
448+ // interrupt-controller = <&ipic>;
449+ };
450+
451+ cpus {
452+ #cpus = <1>;
453+ #size-cells = <0>;
454+ #address-cells = <1>;
455+
456+ PowerPC,8323E@0 {
457+ device_type = "cpu";
458+ reg = <0x0>;
459+ i-cache-size = <0x4000>;
460+ d-cache-size = <0x4000>;
461+ i-cache-line-size = <0x20>;
462+ d-cache-line-size = <0x20>;
463+ // clock-frequency = <0x13de3650>;
464+ // timebase-frequency = <0x1fc9f08>;
465+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
466+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
467+ 32-bit;
468+ };
469+ };
470+
471+ memory {
472+ device_type = "memory";
473+ reg = <0x0 0x4000000>;
474+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
475+ };
476+
477+ flash {
478+ reg = <0xfe000000 0x20000>;
479+ };
480+
481+ nand {
482+ ale = <&gpio2 0x3>;
483+ cle = <&gpio2 0x2>;
484+ nce = <&gpio2 0x1>;
485+ rdy = <&gpio2 0x0>;
486+ reg = <0xf8000000 0x1000>;
487+ device_type = "rb,nand";
488+ };
489+
490+ nnand {
491+ reg = <0xf0000000 0x1000>;
492+ };
493+
494+ voltage {
495+ voltage_gpio = <&gpio3 0x11>;
496+ };
497+
498+ fancon {
499+ interrupt-parent = <&ipic>;
500+ interrupts = <0x14 0x8>;
501+ fan_on = <&gpio0 0x10>;
502+ };
503+
504+ soc8323@e0000000 {
505+ #address-cells = <1>;
506+ #size-cells = <1>;
507+ device_type = "soc";
508+ compatible = "simple-bus";
509+ ranges = <0x0 0xe0000000 0x00100000>;
510+ reg = <0xe0000000 0x00000200>;
511+ bus-frequency = <1>;
512+
513+ wdt@200 {
514+ device_type = "watchdog";
515+ compatible = "mpc83xx_wdt";
516+ reg = <0x200 0x100>;
517+ };
518+
519+ ipic:pic@700 {
520+ interrupt-controller;
521+ #address-cells = <0>;
522+ #interrupt-cells = <2>;
523+ reg = <0x700 0x100>;
524+ device_type = "ipic";
525+ };
526+
527+ par_io@1400 {
528+ num-ports = <4>;
529+ device_type = "par_io";
530+ reg = <0x1400 0x100>;
531+
532+ ucc2pio: ucc_pin@02 {
533+ pio-map = <
534+ /* port pin dir open_drain assignment has_irq */
535+ 3 4 3 0 2 0
536+ 3 5 1 0 2 0
537+ 0 18 1 0 1 0
538+ 0 19 1 0 1 0
539+ 0 20 1 0 1 0
540+ 0 21 1 0 1 0
541+ 0 30 1 0 1 0
542+ 3 6 2 0 1 0
543+ 0 29 2 0 1 0
544+ 0 31 2 0 1 0
545+ 0 22 2 0 1 0
546+ 0 23 2 0 1 0
547+ 0 24 2 0 1 0
548+ 0 25 2 0 1 0
549+ 0 28 2 0 1 0
550+ 0 26 2 0 1 0
551+ 3 31 2 0 1 0>;
552+ };
553+
554+ ucc3pio: ucc_pin@03 {
555+ pio-map = <
556+ /* port pin dir open_drain assignment has_irq */
557+ 1 0 1 0 1 0
558+ 1 1 1 0 1 0
559+ 1 2 1 0 1 0
560+ 1 3 1 0 1 0
561+ 1 12 1 0 1 0
562+ 3 24 2 0 1 0
563+ 1 11 2 0 1 0
564+ 1 13 2 0 1 0
565+ 1 4 2 0 1 0
566+ 1 5 2 0 1 0
567+ 1 6 2 0 1 0
568+ 1 7 2 0 1 0
569+ 1 10 2 0 1 0
570+ 1 8 2 0 1 0
571+ 3 29 2 0 1 0>;
572+ };
573+
574+ ucc4pio: ucc_pin@04 {
575+ pio-map = <
576+ /* port pin dir open_drain assignment has_irq */
577+ 1 18 1 0 1 0
578+ 1 19 1 0 1 0
579+ 1 20 1 0 1 0
580+ 1 21 1 0 1 0
581+ 1 30 1 0 1 0
582+ 3 20 2 0 1 0
583+ 1 30 2 0 1 0
584+ 1 31 2 0 1 0
585+ 1 22 2 0 1 0
586+ 1 23 2 0 1 0
587+ 1 24 2 0 1 0
588+ 1 25 2 0 1 0
589+ 1 28 2 0 1 0
590+ 1 26 2 0 1 0
591+ 3 21 2 0 1 0>;
592+ };
593+ };
594+
595+ serial0: serial@4500 {
596+ cell-index = <0>;
597+ device_type = "serial";
598+ compatible = "fsl,ns16550", "ns16550";
599+ reg = <0x4500 0x100>;
600+ clock-frequency = <0x7f27c20>;
601+ interrupts = <9 0x8>;
602+ interrupt-parent = <&ipic>;
603+ };
604+
605+ dma@82a8 {
606+ #address-cells = <1>;
607+ #size-cells = <1>;
608+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
609+ reg = <0x82a8 4>;
610+ ranges = <0 0x8100 0x1a8>;
611+ interrupt-parent = <&ipic>;
612+ interrupts = <71 8>;
613+ cell-index = <0>;
614+ dma-channel@0 {
615+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
616+ reg = <0 0x80>;
617+ cell-index = <0>;
618+ interrupt-parent = <&ipic>;
619+ interrupts = <71 8>;
620+ };
621+ dma-channel@80 {
622+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
623+ reg = <0x80 0x80>;
624+ cell-index = <1>;
625+ interrupt-parent = <&ipic>;
626+ interrupts = <71 8>;
627+ };
628+ dma-channel@100 {
629+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
630+ reg = <0x100 0x80>;
631+ cell-index = <2>;
632+ interrupt-parent = <&ipic>;
633+ interrupts = <71 8>;
634+ };
635+ dma-channel@180 {
636+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
637+ reg = <0x180 0x28>;
638+ cell-index = <3>;
639+ interrupt-parent = <&ipic>;
640+ interrupts = <71 8>;
641+ };
642+ };
643+
644+ beeper {
645+ gpio = <&gpio3 0x12>;
646+ reg = <0x500 0x100>;
647+ interrupt-parent = <&ipic>;
648+ interrupts = <0x48 0x8>;
649+ };
650+
651+ gpio3: gpio@3 {
652+ reg = <0x144c 0x4>;
653+ device-id = <0x3>;
654+ compatible = "qe_gpio";
655+ device_type = "gpio";
656+ };
657+
658+ gpio2: gpio@2 {
659+ reg = <0x1434 0x4>;
660+ device-id = <0x2>;
661+ compatible = "qe_gpio";
662+ device_type = "gpio";
663+ };
664+
665+ gpio0: gpio@0 {
666+ reg = <0x1404 0x4>;
667+ device-id = <0x0>;
668+ compatible = "qe_gpio";
669+ device_type = "gpio";
670+ };
671+ };
672+
673+ pci0: pci@e0008500 {
674+ device_type = "pci";
675+ // compatible = "83xx";
676+ compatible = "fsl,mpc8349-pci";
677+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
678+ #address-cells = <3>;
679+ #size-cells = <2>;
680+ #interrupt-cells = <1>;
681+ // clock-frequency = <0>;
682+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
683+ bus-range = <0x0 0x0>;
684+ interrupt-map = <
685+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
686+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
687+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
688+
689+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
690+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
691+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
692+
693+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
694+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
695+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
696+
697+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
698+ interrupt-parent = <&ipic>;
699+ // interrupts = <66 0x8>;
700+ };
701+
702+ qe@e0100000 {
703+ reg = <0xe0100000 0x480>;
704+ ranges = <0x0 0xe0100000 0x100000>;
705+ model = "QE";
706+ device_type = "qe";
707+ compatible = "fsl,qe";
708+ #size-cells = <1>;
709+ #address-cells = <1>;
710+ brg-frequency = <0>;
711+ bus-frequency = <0>;
712+ // bus-frequency = <198000000>;
713+ fsl,qe-num-riscs = <1>;
714+ fsl,qe-num-snums = <28>;
715+
716+ qeic: qeic@80 {
717+ interrupt-controller;
718+ compatible = "fsl,qe-ic";
719+ big-endian;
720+ built-in;
721+ reg = <0x80 0x80>;
722+ #interrupt-cells = <1>;
723+ #address-cells = <0>;
724+ device_type = "qeic";
725+ interrupts = <0x20 0x8 0x21 0x8>;
726+ interrupt-parent = <&ipic>;
727+ };
728+
729+ mdio@2120 {
730+ compatible = "ucc_geth_phy";
731+ device_type = "mdio";
732+ reg = <0x3120 0x18>;
733+ #size-cells = <0>;
734+ #address-cells = <1>;
735+
736+ phy3: ethernet-phy@03 {
737+ // interface = <0x3>;
738+ device_type = "ethernet-phy";
739+ reg = <0x3>;
740+ };
741+
742+ phy2: ethernet-phy@02 {
743+ // interface = <0x3>;
744+ device_type = "ethernet-phy";
745+ reg = <0x2>;
746+ };
747+
748+ phy1: ethernet-phy@01 {
749+ // interface = <0x3>;
750+ device_type = "ethernet-phy";
751+ reg = <0x1>;
752+ };
753+ };
754+
755+ enet0: ucc@2200 {
756+ tx-clock = <0x1a>;
757+ rx-clock = <0x1f>;
758+ local-mac-address = [00 00 00 00 00 00];
759+ interrupt-parent = <&qeic>;
760+ interrupts = <0x22>;
761+ reg = <0x2200 0x200>;
762+ device-id = <0x3>;
763+ model = "UCC";
764+ compatible = "ucc_geth";
765+ device_type = "network";
766+ phy-handle = <&phy2>;
767+ pio-handle = <&ucc3pio>;
768+ };
769+
770+ enet1: ucc@3200 {
771+ tx-clock = <0x22>;
772+ rx-clock = <0x20>;
773+ local-mac-address = [00 00 00 00 00 00];
774+ interrupt-parent = <&qeic>;
775+ interrupts = <0x23>;
776+ reg = <0x3200 0x200>;
777+ device-id = <0x4>;
778+ model = "UCC";
779+ compatible = "ucc_geth";
780+ device_type = "network";
781+ phy-handle = <&phy3>;
782+ pio-handle = <&ucc4pio>;
783+ };
784+
785+ enet2: ucc@3000 {
786+ tx-clock = <0x18>;
787+ rx-clock = <0x17>;
788+ local-mac-address = [00 00 00 00 00 00];
789+ interrupt-parent = <&qeic>;
790+ interrupts = <0x21>;
791+ reg = <0x3000 0x200>;
792+ device-id = <0x2>;
793+ model = "UCC";
794+ compatible = "ucc_geth";
795+ device_type = "network";
796+ phy-handle = <&phy1>;
797+ pio-handle = <&ucc2pio>;
798+ };
799+
800+ spi@500 {
801+ mode = "cpu";
802+ interrupt-parent = <&qeic>;
803+ interrupts = <0x1>;
804+ reg = <0x500 0x40>;
805+ compatible = "fsl,spi";
806+ device_type = "spi";
807+ };
808+
809+ spi@4c0 {
810+ mode = "cpu";
811+ interrupt-parent = <&qeic>;
812+ interrupts = <0x2>;
813+ reg = <0x4c0 0x40>;
814+ compatible = "fsl,spi";
815+ device_type = "spi";
816+ };
817+
818+ muram@10000 {
819+ #address-cells = <1>;
820+ #size-cells = <1>;
821+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
822+ ranges = <0x0 0x10000 0x4000>;
823+ device_type = "muram";
824+
825+ data-only@0 {
826+ compatible = "fsl,qe-muram-data",
827+ "fsl,cpm-muram-data";
828+ reg = <0x0 0x4000>;
829+ };
830+ };
831+ };
832+};
833--- /dev/null
834@@ -0,0 +1,86 @@
835+/*
836+ * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
837+ *
838+ * Author: Alexandros C. Couloumbis <alex@ozo.com>
839+ * Author: Michael Guntsche <mike@it-loops.com>
840+ *
841+ * Copyright (c) 2010 Alexandros C. Couloumbis
842+ * Copyright (c) 2009 Michael Guntsche
843+ *
844+ * This program is free software; you can redistribute it and/or modify it
845+ * under the terms of the GNU General Public License version 2 as published
846+ * by the Free Software Foundation.
847+ */
848+
849+#include "ops.h"
850+#include "types.h"
851+#include "io.h"
852+#include "stdio.h"
853+#include <libfdt.h>
854+
855+BSS_STACK(4*1024);
856+
857+u64 memsize64;
858+const void *fw_dtb;
859+
860+static void rb333_fixups(void)
861+{
862+ const u32 *reg, *timebase, *clock;
863+ int node, size;
864+ void *chosen;
865+ const char* bootargs;
866+
867+ dt_fixup_memory(0, memsize64);
868+
869+ /* Find the CPU timebase and clock frequencies. */
870+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
871+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
872+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
873+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
874+
875+ /* Set the MAC addresses. */
876+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@2200");
877+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
878+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
879+
880+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3200");
881+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
882+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
883+
884+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3000");
885+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
886+ dt_fixup_mac_address_by_alias("ethernet2", (const u8 *)reg);
887+
888+ /* Fixup chosen
889+ * The bootloader reads the kernelparm segment and adds the content to
890+ * bootargs. This is needed to specify root and other boot flags.
891+ */
892+ chosen = finddevice("/chosen");
893+ node = fdt_path_offset(fw_dtb, "/chosen");
894+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
895+ setprop_str(chosen, "bootargs", bootargs);
896+}
897+
898+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
899+ unsigned long r6, unsigned long r7)
900+{
901+ const u32 *reg;
902+ int node, size;
903+
904+ fw_dtb = (const void *)r3;
905+
906+ /* Find the memory range. */
907+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
908+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
909+ memsize64 = reg[1];
910+
911+ /* Now we have the memory size; initialize the heap. */
912+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
913+
914+ /* Prepare the device tree and find the console. */
915+ fdt_init(_dtb_start);
916+ serial_console_init();
917+
918+ /* Remaining fixups... */
919+ platform_ops.fixups = rb333_fixups;
920+}
921--- /dev/null
922@@ -0,0 +1,388 @@
923+/*
924+ * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
925+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
926+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
927+ * Copyright (C) Mikrotik 2007
928+ *
929+ * This program is free software; you can redistribute it and/or modify it
930+ * under the terms of the GNU General Public License as published by the
931+ * Free Software Foundation; either version 2 of the License, or (at your
932+ * option) any later version.
933+ */
934+
935+#include <linux/delay.h>
936+#include <linux/root_dev.h>
937+#include <linux/initrd.h>
938+#include <linux/interrupt.h>
939+#include <linux/of_platform.h>
940+#include <linux/of_device.h>
941+#include <linux/of_platform.h>
942+#include <linux/pci.h>
943+#include <asm/time.h>
944+#include <asm/ipic.h>
945+#include <asm/udbg.h>
946+#include <asm/qe.h>
947+#include <asm/qe_ic.h>
948+#include <sysdev/fsl_soc.h>
949+#include <sysdev/fsl_pci.h>
950+#include "mpc83xx.h"
951+
952+#define SYSCTL 0x100
953+#define SICRL 0x014
954+
955+#define GTCFR2 0x04
956+#define GTMDR4 0x22
957+#define GTRFR4 0x26
958+#define GTCNR4 0x2e
959+#define GTVER4 0x36
960+#define GTPSR4 0x3e
961+
962+#define GTCFR_BCM 0x40
963+#define GTCFR_STP4 0x20
964+#define GTCFR_RST4 0x10
965+#define GTCFR_STP3 0x02
966+#define GTCFR_RST3 0x01
967+
968+#define GTMDR_ORI 0x10
969+#define GTMDR_FRR 0x08
970+#define GTMDR_ICLK16 0x04
971+
972+extern int par_io_data_set(u8 port, u8 pin, u8 val);
973+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
974+ int assignment, int has_irq);
975+
976+static unsigned timer_freq;
977+static void *gtm;
978+
979+static int beeper_irq;
980+static unsigned beeper_gpio_pin[2];
981+
982+int rb333model = 0;
983+
984+irqreturn_t rbppc_timer_irq(int irq, void *ptr)
985+{
986+ static int toggle = 0;
987+
988+ par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
989+ toggle = !toggle;
990+
991+ /* ack interrupt */
992+ out_be16(gtm + GTVER4, 3);
993+
994+ return IRQ_HANDLED;
995+}
996+
997+void rbppc_beep(unsigned freq)
998+{
999+ unsigned gtmdr;
1000+
1001+ if (freq > 5000) freq = 5000;
1002+
1003+ if (!gtm)
1004+ return;
1005+ if (!freq) {
1006+ out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
1007+ return;
1008+ }
1009+
1010+ out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
1011+ out_be16(gtm + GTPSR4, 255);
1012+ gtmdr = GTMDR_FRR | GTMDR_ICLK16;
1013+ if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
1014+ out_be16(gtm + GTMDR4, gtmdr);
1015+ out_be16(gtm + GTVER4, 3);
1016+
1017+ out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
1018+ out_be16(gtm + GTCNR4, 0);
1019+}
1020+EXPORT_SYMBOL(rbppc_beep);
1021+
1022+static void __init rbppc_setup_arch(void)
1023+{
1024+ struct device_node *np;
1025+
1026+ np = of_find_node_by_type(NULL, "cpu");
1027+ if (np) {
1028+ const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
1029+ loops_per_jiffy = fp ? *fp / HZ : 0;
1030+
1031+ of_node_put(np);
1032+ }
1033+
1034+ np = of_find_node_by_name(NULL, "serial");
1035+ if (np) {
1036+ timer_freq =
1037+ *(unsigned *) of_get_property(np, "clock-frequency", NULL);
1038+ of_node_put(np);
1039+ }
1040+
1041+#ifdef CONFIG_PCI
1042+ np = of_find_node_by_type(NULL, "pci");
1043+ if (np) {
1044+ mpc83xx_add_bridge(np);
1045+ }
1046+#endif
1047+
1048+if (rb333model) {
1049+
1050+#ifdef CONFIG_QUICC_ENGINE
1051+ qe_reset();
1052+
1053+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
1054+ par_io_init(np);
1055+ of_node_put(np);
1056+
1057+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
1058+ par_io_of_config(np);
1059+ }
1060+#endif
1061+
1062+} /* RB333 */
1063+
1064+}
1065+
1066+void __init rbppc_init_IRQ(void)
1067+{
1068+ struct device_node *np;
1069+
1070+ np = of_find_node_by_type(NULL, "ipic");
1071+ if (np) {
1072+ ipic_init(np, 0);
1073+ ipic_set_default_priority();
1074+ of_node_put(np);
1075+ }
1076+
1077+if (rb333model) {
1078+
1079+#ifdef CONFIG_QUICC_ENGINE
1080+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
1081+ if (!np) {
1082+ np = of_find_node_by_type(NULL, "qeic");
1083+ if (!np)
1084+ return;
1085+ }
1086+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
1087+ of_node_put(np);
1088+#endif /* CONFIG_QUICC_ENGINE */
1089+
1090+} /* RB333 */
1091+
1092+}
1093+
1094+static int __init rbppc_probe(void)
1095+{
1096+ char *model;
1097+
1098+ model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
1099+
1100+ if (!model)
1101+ return 0;
1102+
1103+ if (strcmp(model, "RB333") == 0) {
1104+ rb333model = 1;
1105+ return 1;
1106+ }
1107+
1108+ if (strcmp(model, "RB600") == 0)
1109+ return 1;
1110+
1111+ return 0;
1112+}
1113+
1114+static void __init rbppc_beeper_init(struct device_node *beeper)
1115+{
1116+ struct resource res;
1117+ struct device_node *gpio;
1118+ const unsigned *pin;
1119+ const unsigned *gpio_id;
1120+
1121+ if (of_address_to_resource(beeper, 0, &res)) {
1122+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
1123+ return;
1124+ }
1125+
1126+ pin = of_get_property(beeper, "gpio", NULL);
1127+ if (pin) {
1128+ gpio = of_find_node_by_phandle(pin[0]);
1129+
1130+ if (!gpio) {
1131+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
1132+ return;
1133+ }
1134+
1135+ gpio_id = of_get_property(gpio, "device-id", NULL);
1136+ if (!gpio_id) {
1137+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
1138+ return;
1139+ }
1140+
1141+ beeper_gpio_pin[0] = *gpio_id;
1142+ beeper_gpio_pin[1] = pin[1];
1143+
1144+ par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
1145+ } else {
1146+ void *sysctl;
1147+
1148+ sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
1149+ out_be32(sysctl + SICRL,
1150+ in_be32(sysctl + SICRL) | (1 << (31 - 19)));
1151+ iounmap(sysctl);
1152+ }
1153+
1154+ gtm = ioremap_nocache(res.start, res.end - res.start + 1);
1155+
1156+ beeper_irq = irq_of_parse_and_map(beeper, 0);
1157+ if (beeper_irq != NO_IRQ) {
1158+ int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
1159+ if (e) {
1160+ printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
1161+ }
1162+ }
1163+}
1164+
1165+#define SBIT(x) (0x80000000 >> (x))
1166+#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
1167+
1168+#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
1169+#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
1170+
1171+#define SICRL_RB600(x) ((x) + (0x114 >> 2))
1172+#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
1173+#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
1174+
1175+static void rbppc_restart(char *cmd)
1176+{
1177+ __be32 __iomem *reg;
1178+ unsigned rb_model;
1179+ struct device_node *root;
1180+ unsigned int size;
1181+
1182+ root = of_find_node_by_path("/");
1183+ if (root) {
1184+ const char *prop = (char *) of_get_property(root, "model", &size);
1185+ rb_model = prop[sizeof("RB") - 1] - '0';
1186+ of_node_put(root);
1187+ switch (rb_model) {
1188+ case 3:
1189+ reg = ioremap(get_immrbase(), 0x2000);
1190+ local_irq_disable();
1191+ out_be32(GPIO_DIR_RB333(reg),
1192+ (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
1193+ out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
1194+ break;
1195+ case 6:
1196+ reg = ioremap(get_immrbase(), 0x1000);
1197+ local_irq_disable();
1198+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
1199+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
1200+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
1201+ break;
1202+ default:
1203+ mpc83xx_restart(cmd);
1204+ break;
1205+ }
1206+ }
1207+ else mpc83xx_restart(cmd);
1208+
1209+ for (;;) ;
1210+}
1211+
1212+static void rbppc_halt(void)
1213+{
1214+ while (1);
1215+}
1216+
1217+static struct of_device_id rbppc_ids[] = {
1218+ { .type = "soc", },
1219+ { .compatible = "soc", },
1220+ { .compatible = "simple-bus", },
1221+ { .type = "qe", },
1222+ { .compatible = "fsl,qe", },
1223+ { .compatible = "gianfar", },
1224+ { },
1225+};
1226+
1227+static int __init rbppc_declare_of_platform_devices(void)
1228+{
1229+ struct device_node *np;
1230+ unsigned idx;
1231+
1232+ of_platform_bus_probe(NULL, rbppc_ids, NULL);
1233+
1234+ np = of_find_node_by_type(NULL, "mdio");
1235+ if (np) {
1236+ unsigned len;
1237+ unsigned *res;
1238+ const unsigned *eres;
1239+ struct device_node *ep;
1240+
1241+ ep = of_find_compatible_node(NULL, "network", "ucc_geth");
1242+ if (ep) {
1243+ eres = of_get_property(ep, "reg", &len);
1244+ res = (unsigned *) of_get_property(np, "reg", &len);
1245+ if (res && eres) {
1246+ res[0] = eres[0] + 0x120;
1247+ }
1248+ }
1249+ }
1250+
1251+ np = of_find_node_by_name(NULL, "nand");
1252+ if (np) {
1253+ of_platform_device_create(np, "nand", NULL);
1254+ }
1255+
1256+ idx = 0;
1257+ for_each_node_by_type(np, "rb,cf") {
1258+ char dev_name[12];
1259+ snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
1260+ of_platform_device_create(np, dev_name, NULL);
1261+ ++idx;
1262+ }
1263+
1264+ np = of_find_node_by_name(NULL, "beeper");
1265+ if (np) {
1266+ rbppc_beeper_init(np);
1267+ }
1268+
1269+ return 0;
1270+}
1271+machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
1272+
1273+define_machine(rb600) {
1274+ .name = "MikroTik RouterBOARD 333/600 series",
1275+ .probe = rbppc_probe,
1276+ .setup_arch = rbppc_setup_arch,
1277+ .init_IRQ = rbppc_init_IRQ,
1278+ .get_irq = ipic_get_irq,
1279+ .restart = rbppc_restart,
1280+ .halt = rbppc_halt,
1281+ .time_init = mpc83xx_time_init,
1282+ .calibrate_decr = generic_calibrate_decr,
1283+};
1284+
1285+static void fixup_pcibridge(struct pci_dev *dev)
1286+{
1287+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1288+ /* let the kernel itself set right memory windows */
1289+ pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
1290+ pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
1291+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
1292+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
1293+ pci_write_config_byte(dev, PCI_IO_BASE, 0);
1294+ pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
1295+
1296+ pci_write_config_byte(
1297+ dev, PCI_COMMAND,
1298+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
1299+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1300+ }
1301+}
1302+
1303+
1304+static void fixup_rb604(struct pci_dev *dev)
1305+{
1306+ pci_write_config_byte(dev, 0xC0, 0x01);
1307+}
1308+
1309+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
1310+DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
target/linux/mpc83xx/patches-3.7/201-powerpc-add-rb_iomap.patch
1--- a/arch/powerpc/kernel/Makefile
2@@ -118,9 +118,11 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.
3
4 obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
5
6+ifneq ($(CONFIG_RB_IOMAP),y)
7 ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
8 obj-y += iomap.o
9 endif
10+endif
11
12 obj-$(CONFIG_PPC64) += $(obj64-y)
13 obj-$(CONFIG_PPC32) += $(obj32-y)
14--- a/arch/powerpc/platforms/83xx/Makefile
15@@ -7,6 +7,7 @@ obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mp
16 obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
17 obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
18 obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
19+obj-$(CONFIG_RB_PPC) += rbppc.o
20 obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
21 obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
22 obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
23--- a/arch/powerpc/platforms/Kconfig
24@@ -191,6 +191,10 @@ config PPC_INDIRECT_MMIO
25 config PPC_IO_WORKAROUNDS
26     bool
27
28+config RB_IOMAP
29+ bool
30+ default y if RB_PPC
31+
32 source "drivers/cpufreq/Kconfig"
33
34 menu "CPU Frequency drivers"
35--- a/arch/powerpc/sysdev/Makefile
36@@ -69,3 +69,6 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -
37 obj-$(CONFIG_PPC_XICS) += xics/
38
39 obj-$(CONFIG_GE_FPGA) += ge/
40+
41+obj-$(CONFIG_RB_IOMAP) += rb_iomap.o
42+
43--- /dev/null
44@@ -0,0 +1,204 @@
45+#include <linux/init.h>
46+#include <linux/pci.h>
47+#include <linux/mm.h>
48+#include <asm/io.h>
49+
50+#define LOCALBUS_START 0x40000000
51+#define LOCALBUS_MASK 0x007fffff
52+#define LOCALBUS_REGMASK 0x001fffff
53+
54+static void __iomem *localbus_base;
55+
56+static inline int is_localbus(void __iomem *addr)
57+{
58+ return ((unsigned) addr & ~LOCALBUS_MASK) == LOCALBUS_START;
59+}
60+
61+static inline unsigned localbus_regoff(unsigned reg) {
62+ return (reg << 16) | (((reg ^ 8) & 8) << 17);
63+}
64+
65+static inline void __iomem *localbus_addr(void __iomem *addr)
66+{
67+ return localbus_base
68+ + ((unsigned) addr & LOCALBUS_MASK & ~LOCALBUS_REGMASK)
69+ + localbus_regoff((unsigned) addr & LOCALBUS_REGMASK);
70+}
71+
72+unsigned int ioread8(void __iomem *addr)
73+{
74+ if (is_localbus(addr))
75+ return in_be16(localbus_addr(addr)) >> 8;
76+ return readb(addr);
77+}
78+EXPORT_SYMBOL(ioread8);
79+
80+unsigned int ioread16(void __iomem *addr)
81+{
82+ if (is_localbus(addr))
83+ return le16_to_cpu(in_be16(localbus_addr(addr)));
84+ return readw(addr);
85+}
86+EXPORT_SYMBOL(ioread16);
87+
88+unsigned int ioread16be(void __iomem *addr)
89+{
90+ return in_be16(addr);
91+}
92+EXPORT_SYMBOL(ioread16be);
93+
94+unsigned int ioread32(void __iomem *addr)
95+{
96+ return readl(addr);
97+}
98+EXPORT_SYMBOL(ioread32);
99+
100+unsigned int ioread32be(void __iomem *addr)
101+{
102+ return in_be32(addr);
103+}
104+EXPORT_SYMBOL(ioread32be);
105+
106+void iowrite8(u8 val, void __iomem *addr)
107+{
108+ if (is_localbus(addr))
109+ out_be16(localbus_addr(addr), ((u16) val) << 8);
110+ else
111+ writeb(val, addr);
112+}
113+EXPORT_SYMBOL(iowrite8);
114+
115+void iowrite16(u16 val, void __iomem *addr)
116+{
117+ if (is_localbus(addr))
118+ out_be16(localbus_addr(addr), cpu_to_le16(val));
119+ else
120+ writew(val, addr);
121+}
122+EXPORT_SYMBOL(iowrite16);
123+
124+void iowrite16be(u16 val, void __iomem *addr)
125+{
126+ out_be16(addr, val);
127+}
128+EXPORT_SYMBOL(iowrite16be);
129+
130+void iowrite32(u32 val, void __iomem *addr)
131+{
132+ writel(val, addr);
133+}
134+EXPORT_SYMBOL(iowrite32);
135+
136+void iowrite32be(u32 val, void __iomem *addr)
137+{
138+ out_be32(addr, val);
139+}
140+EXPORT_SYMBOL(iowrite32be);
141+
142+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
143+{
144+ if (is_localbus(addr)) {
145+ unsigned i;
146+ void *laddr = localbus_addr(addr);
147+ u8 *buf = dst;
148+
149+ for (i = 0; i < count; ++i) {
150+ *buf++ = in_be16(laddr) >> 8;
151+ }
152+ } else {
153+ _insb((u8 __iomem *) addr, dst, count);
154+ }
155+}
156+EXPORT_SYMBOL(ioread8_rep);
157+
158+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
159+{
160+ if (is_localbus(addr)) {
161+ unsigned i;
162+ void *laddr = localbus_addr(addr);
163+ u16 *buf = dst;
164+
165+ for (i = 0; i < count; ++i) {
166+ *buf++ = in_be16(laddr);
167+ }
168+ } else {
169+ _insw_ns((u16 __iomem *) addr, dst, count);
170+ }
171+}
172+EXPORT_SYMBOL(ioread16_rep);
173+
174+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
175+{
176+ _insl_ns((u32 __iomem *) addr, dst, count);
177+}
178+EXPORT_SYMBOL(ioread32_rep);
179+
180+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
181+{
182+ if (is_localbus(addr)) {
183+ unsigned i;
184+ void *laddr = localbus_addr(addr);
185+ const u8 *buf = src;
186+
187+ for (i = 0; i < count; ++i) {
188+ out_be16(laddr, ((u16) *buf++) << 8);
189+ }
190+ } else {
191+ _outsb((u8 __iomem *) addr, src, count);
192+ }
193+}
194+EXPORT_SYMBOL(iowrite8_rep);
195+
196+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
197+{
198+ if (is_localbus(addr)) {
199+ unsigned i;
200+ void *laddr = localbus_addr(addr);
201+ const u16 *buf = src;
202+
203+ for (i = 0; i < count; ++i) {
204+ out_be16(laddr, *buf++);
205+ }
206+ } else {
207+ _outsw_ns((u16 __iomem *) addr, src, count);
208+ }
209+}
210+EXPORT_SYMBOL(iowrite16_rep);
211+
212+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
213+{
214+ _outsl_ns((u32 __iomem *) addr, src, count);
215+}
216+EXPORT_SYMBOL(iowrite32_rep);
217+
218+void __iomem *ioport_map(unsigned long port, unsigned int len)
219+{
220+ return (void __iomem *) (port + _IO_BASE);
221+}
222+EXPORT_SYMBOL(ioport_unmap);
223+
224+void ioport_unmap(void __iomem *addr)
225+{
226+ /* Nothing to do */
227+}
228+EXPORT_SYMBOL(ioport_map);
229+
230+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
231+{
232+ /* Nothing to do */
233+}
234+EXPORT_SYMBOL(pci_iounmap);
235+
236+void __iomem *localbus_map(unsigned long addr, unsigned int len)
237+{
238+ if (!localbus_base)
239+ localbus_base = ioremap(addr & ~LOCALBUS_MASK,
240+ LOCALBUS_MASK + 1);
241+ return (void *) (LOCALBUS_START + (addr & LOCALBUS_MASK));
242+}
243+EXPORT_SYMBOL(localbus_map);
244+
245+void localbus_unmap(void __iomem *addr)
246+{
247+}
248+EXPORT_SYMBOL(localbus_unmap);
249--- a/arch/powerpc/platforms/83xx/Kconfig
250@@ -44,6 +44,7 @@ config RB_PPC
251     select QUICC_ENGINE
252     select PPC_MPC832x
253     select PPC_MPC834x
254+ select RB_IOMAP
255     help
256       This option enables support for MikroTik RouterBOARD 333/600 series boards.
257
target/linux/mpc83xx/patches-3.7/202-ata-add-pata_rbppc_cf-driver.patch
1--- a/drivers/ata/Kconfig
2@@ -916,5 +916,12 @@ config PATA_LEGACY
3
4       If unsure, say N.
5
6+config PATA_RB_PPC
7+ tristate "MikroTik RB600 PATA support"
8+ depends on RB_PPC
9+ help
10+ This option enables support for PATA devices on MikroTik RouterBOARD
11+ 600 series boards.
12+
13 endif # ATA_SFF
14 endif # ATA
15--- a/drivers/ata/Makefile
16@@ -91,6 +91,7 @@ obj-$(CONFIG_PATA_PALMLD) += pata_palmld
17 obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
18 obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
19 obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
20+obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
21 obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
22 obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
23
24--- /dev/null
25@@ -0,0 +1,699 @@
26+/*
27+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
28+ * Copyright (C) Mikrotik 2007
29+ *
30+ * This program is free software; you can redistribute it and/or modify it
31+ * under the terms of the GNU General Public License as published by the
32+ * Free Software Foundation; either version 2 of the License, or (at your
33+ * option) any later version.
34+ */
35+
36+#include <linux/kernel.h>
37+#include <linux/module.h>
38+#include <linux/init.h>
39+#include <scsi/scsi_host.h>
40+#include <linux/libata.h>
41+#include <linux/of_platform.h>
42+#include <linux/ata_platform.h>
43+#include <linux/slab.h>
44+
45+#define DEBUG_UPM 0
46+
47+#define DRV_NAME "pata_rbppc_cf"
48+#define DRV_VERSION "0.0.2"
49+
50+#define DEV2SEL_OFFSET 0x00100000
51+
52+#define IMMR_LBCFG_OFFSET 0x00005000
53+#define IMMR_LBCFG_SIZE 0x00001000
54+
55+#define LOCAL_BUS_MCMR 0x00000078
56+#define MxMR_OP_MASK 0x30000000
57+#define MxMR_OP_NORMAL 0x00000000
58+#define MxMR_OP_WRITE 0x10000000
59+#define MxMR_OP_READ 0x20000000
60+#define MxMR_OP_RUN 0x30000000
61+#define MxMR_LUPWAIT_LOW 0x08000000
62+#define MxMR_LUPWAIT_HIGH 0x00000000
63+#define MxMR_LUPWAIT_ENABLE 0x00040000
64+#define MxMR_RLF_MASK 0x0003c000
65+#define MxMR_RLF_SHIFT 14
66+#define MxMR_WLF_MASK 0x00003c00
67+#define MxMR_WLF_SHIFT 10
68+#define MxMR_MAD_MASK 0x0000003f
69+#define LOCAL_BUS_MDR 0x00000088
70+#define LOCAL_BUS_LCRR 0x000000D4
71+#define LCRR_CLKDIV_MASK 0x0000000f
72+
73+#define LOOP_SIZE 4
74+
75+#define UPM_READ_SINGLE_OFFSET 0x00
76+#define UPM_WRITE_SINGLE_OFFSET 0x18
77+#define UPM_DATA_SIZE 0x40
78+
79+#define LBT_CPUIN_MIN 0
80+#define LBT_CPUOUT_MIN 1
81+#define LBT_CPUOUT_MAX 2
82+#define LBT_EXTDEL_MIN 3
83+#define LBT_EXTDEL_MAX 4
84+#define LBT_SIZE 5
85+
86+/* UPM machine configuration bits */
87+#define N_BASE 0x00f00000
88+#define N_CS 0xf0000000
89+#define N_CS_H1 0xc0000000
90+#define N_CS_H2 0x30000000
91+#define N_WE 0x0f000000
92+#define N_WE_H1 0x0c000000
93+#define N_WE_H2 0x03000000
94+#define N_OE 0x00030000
95+#define N_OE_H1 0x00020000
96+#define N_OE_H2 0x00010000
97+#define WAEN 0x00001000
98+#define REDO_2 0x00000100
99+#define REDO_3 0x00000200
100+#define REDO_4 0x00000300
101+#define LOOP 0x00000080
102+#define NA 0x00000008
103+#define UTA 0x00000004
104+#define LAST 0x00000001
105+
106+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
107+#define REDO_MAX_MULT 4
108+
109+#define READ_BASE (N_BASE | N_WE)
110+#define WRITE_BASE (N_BASE | N_OE)
111+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
112+
113+#define EOF_UPM_SETTINGS 0
114+#define ANOTHER_TIMING 1
115+
116+#define OA_CPUIN_MIN 0x01
117+#define OA_CPUOUT_MAX 0x02
118+#define OD_CPUOUT_MIN 0x04
119+#define OA_CPUOUT_DELTA 0x06
120+#define OA_EXTDEL_MAX 0x08
121+#define OD_EXTDEL_MIN 0x10
122+#define OA_EXTDEL_DELTA 0x18
123+#define O_MIN_CYCLE_TIME 0x20
124+#define O_MINUS_PREV 0x40
125+#define O_HALF_CYCLE 0x80
126+
127+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
128+extern void localbus_unmap(void __iomem *addr);
129+
130+struct rbppc_cf_info {
131+ unsigned lbcfg_addr;
132+ unsigned clk_time_ps;
133+ int cur_mode;
134+ u32 lb_timings[LBT_SIZE];
135+};
136+static struct rbppc_cf_info *rbinfo = NULL;
137+
138+struct upm_setting {
139+ unsigned value;
140+ unsigned ns[7];
141+ unsigned clk_minus;
142+ unsigned group_size;
143+ unsigned options;
144+};
145+
146+static const struct upm_setting cfUpmReadSingle[] = {
147+ { READ_BASE | N_OE,
148+ /* t1 - ADDR setup time */
149+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
150+ OA_EXTDEL_MAX) },
151+ { READ_BASE | N_OE_H1,
152+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
153+ { READ_BASE,
154+ /* t2 - OE0 time */
155+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
156+ OA_CPUIN_MIN) },
157+ { READ_BASE | WAEN,
158+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
159+ { READ_BASE | UTA,
160+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
161+ { READ_BASE | N_OE,
162+ /* t9 - ADDR hold time */
163+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
164+ OD_EXTDEL_MIN) },
165+ { READ_BASE | N_OE | N_CS_H2,
166+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
167+ { READ_BASE | N_OE | N_CS,
168+ /* t6Z -IORD data tristate */
169+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
170+ { ANOTHER_TIMING,
171+ /* t2i -IORD recovery time */
172+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
173+ { ANOTHER_TIMING,
174+ /* CS 0 -> 1 MAX */
175+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
176+ OA_EXTDEL_MAX) },
177+ { READ_BASE | N_OE | N_CS | LAST,
178+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
179+ { EOF_UPM_SETTINGS,
180+ /* min total cycle time - includes turnaround and ALE cycle */
181+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
182+};
183+
184+static const struct upm_setting cfUpmWriteSingle[] = {
185+ { WRITE_BASE | N_WE,
186+ /* t1 - ADDR setup time */
187+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
188+ OA_EXTDEL_MAX) },
189+ { WRITE_BASE | N_WE_H1,
190+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
191+ { WRITE_BASE,
192+ /* t2 - WE0 time */
193+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
194+ { WRITE_BASE | WAEN,
195+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
196+ { WRITE_BASE | N_WE,
197+ /* t9 - ADDR hold time */
198+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
199+ OD_EXTDEL_MIN) },
200+ { WRITE_BASE | N_WE | N_CS_H2,
201+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
202+ { WRITE_BASE | N_WE | N_CS,
203+ /* t4 - DATA hold time */
204+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
205+ { ANOTHER_TIMING,
206+ /* t2i -IOWR recovery time */
207+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
208+ { ANOTHER_TIMING,
209+ /* CS 0 -> 1 MAX */
210+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
211+ OA_EXTDEL_MAX) },
212+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
213+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
214+ /* min total cycle time - includes ALE cycle */
215+ { EOF_UPM_SETTINGS,
216+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
217+};
218+
219+static u8 rbppc_cf_check_status(struct ata_port *ap) {
220+ u8 val = ioread8(ap->ioaddr.status_addr);
221+ if (val == 0xF9)
222+ val = 0x7F;
223+ return val;
224+}
225+
226+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
227+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
228+ if (val == 0xF9)
229+ val = 0x7F;
230+ return val;
231+}
232+
233+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
234+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
235+
236+static int ps2clk(int ps, unsigned clk_time_ps) {
237+ int psMaxOver;
238+ if (ps <= 0) return 0;
239+
240+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
241+ psMaxOver = ps * 2 / 100;
242+ if (4 * psMaxOver > clk_time_ps) {
243+ psMaxOver = clk_time_ps / 4;
244+ }
245+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
246+}
247+
248+static int upm_gen_ps_table(const struct upm_setting *upm,
249+ int mode, struct rbppc_cf_info *info,
250+ int *psFinal) {
251+ int uidx;
252+ int lastUpmValIdx = 0;
253+ int group_start_idx = -1;
254+ int group_left_num = -1;
255+ int clk_time_ps = info->clk_time_ps;
256+
257+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
258+ const struct upm_setting *us = upm + uidx;
259+ unsigned opt = us->options;
260+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
261+
262+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
263+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
264+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
265+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
266+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
267+
268+ if (us->value == ANOTHER_TIMING) {
269+ /* use longest timing from alternatives */
270+ if (psFinal[lastUpmValIdx] < ps) {
271+ psFinal[lastUpmValIdx] = ps;
272+ }
273+ ps = 0;
274+ }
275+ else {
276+ if (us->group_size) {
277+ group_start_idx = uidx;
278+ group_left_num = us->group_size;
279+ }
280+ else if (group_left_num > 0) {
281+ /* group time is divided on all group members */
282+ int clk = ps2clk(ps, clk_time_ps);
283+ psFinal[group_start_idx] -= clk * clk_time_ps;
284+ --group_left_num;
285+ }
286+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
287+ int clk = ps2clk(psFinal[lastUpmValIdx],
288+ clk_time_ps);
289+ ps -= clk * clk_time_ps;
290+ }
291+ lastUpmValIdx = uidx;
292+ }
293+ psFinal[uidx] = ps;
294+ }
295+ return uidx;
296+}
297+
298+static int free_half(int ps, int clk, int clk_time_ps) {
299+ if (clk < 2) return 0;
300+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
301+}
302+
303+static void upm_gen_clk_table(const struct upm_setting *upm,
304+ int mode, int clk_time_ps,
305+ int max_uidx, const int *psFinal, int *clkFinal) {
306+ int clk_cycle_time;
307+ int clk_total;
308+ int uidx;
309+
310+ /* convert picoseconds to clocks */
311+ clk_total = 0;
312+ for (uidx = 0; uidx < max_uidx; ++uidx) {
313+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
314+ clkFinal[uidx] = clk;
315+ clk_total += clk;
316+ }
317+
318+ /* check possibility of half cycle usage */
319+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
320+ if ((upm[uidx].options & O_HALF_CYCLE) &&
321+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
322+ clk_time_ps) &&
323+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
324+ clk_time_ps)) {
325+ ++clkFinal[uidx];
326+ --clkFinal[uidx - 1];
327+ --clkFinal[uidx + 1];
328+ }
329+ }
330+
331+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
332+
333+ /* check cycle time, adjust timings if needed */
334+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
335+ upm[max_uidx].clk_minus);
336+ uidx = 0;
337+ while (clk_total < clk_cycle_time) {
338+ /* extend all timings in round-robin to match cycle time */
339+ if (clkFinal[uidx]) {
340+#if DEBUG_UPM
341+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
342+#endif
343+ ++clkFinal[uidx];
344+ ++clk_total;
345+ }
346+ ++uidx;
347+ if (uidx == max_uidx) uidx = 0;
348+ }
349+}
350+
351+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
352+ unsigned *data, int *dataIdx) {
353+ if (*clkLeft == 0) return;
354+
355+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
356+ int times;
357+ int times1;
358+ int times2;
359+
360+ times = *clkLeft / LOOP_SIZE;
361+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
362+ times1 = times / 2;
363+ times2 = times - times1;
364+
365+ val |= LOOP;
366+ data[*dataIdx] = val | REDO_VAL(times1);
367+ ++(*dataIdx);
368+ data[*dataIdx] = val | REDO_VAL(times2);
369+ ++(*dataIdx);
370+
371+ *clkLeft -= times * LOOP_SIZE;
372+ return;
373+ }
374+
375+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
376+ if (*clkLeft < maxClk) maxClk = *clkLeft;
377+
378+ *clkLeft -= maxClk;
379+ val |= REDO_VAL(maxClk);
380+
381+ data[*dataIdx] = val;
382+ ++(*dataIdx);
383+}
384+
385+static int upm_gen_final_data(const struct upm_setting *upm,
386+ int max_uidx, int *clkFinal, unsigned *data) {
387+ int dataIdx;
388+ int uidx;
389+
390+ dataIdx = 0;
391+ for (uidx = 0; uidx < max_uidx; ++uidx) {
392+ int clk = clkFinal[uidx];
393+ while (clk > 0) {
394+ add_data_val(upm[uidx].value, &clk, 0,
395+ data, &dataIdx);
396+ }
397+ }
398+ return dataIdx;
399+}
400+
401+static int conv_upm_table(const struct upm_setting *upm,
402+ int mode, struct rbppc_cf_info *info,
403+ unsigned *data) {
404+#if DEBUG_UPM
405+ int uidx;
406+#endif
407+ int psFinal[32];
408+ int clkFinal[32];
409+ int max_uidx;
410+ int data_len;
411+
412+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
413+
414+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
415+ psFinal, clkFinal);
416+
417+#if DEBUG_UPM
418+ /* dump out debug info */
419+ for (uidx = 0; uidx < max_uidx; ++uidx) {
420+ if (clkFinal[uidx]) {
421+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
422+ uidx, upm[uidx].value,
423+ clkFinal[uidx], psFinal[uidx]);
424+ }
425+ }
426+#endif
427+
428+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
429+
430+#if DEBUG_UPM
431+ for (uidx = 0; uidx < data_len; ++uidx) {
432+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
433+ uidx, data[uidx]);
434+ }
435+#endif
436+ return 0;
437+}
438+
439+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
440+ int i;
441+
442+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
443+ data[i] = EMPTY;
444+ }
445+
446+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
447+ return -1;
448+ }
449+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
450+ return -1;
451+ }
452+ return 0;
453+}
454+
455+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
456+ unsigned i;
457+ unsigned mxmr;
458+
459+ mxmr = in_be32(lbcfg_mxmr);
460+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
461+ mxmr |= (MxMR_OP_WRITE | offset);
462+ out_be32(lbcfg_mxmr, mxmr);
463+ in_be32(lbcfg_mxmr); /* flush MxMR write */
464+
465+ for (i = 0; i < len; ++i) {
466+ int to;
467+ unsigned data = upmData[i + offset];
468+ out_be32(lbcfg_mdr, data);
469+ in_be32(lbcfg_mdr); /* flush MDR write */
470+
471+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
472+
473+ /* wait for dummy write to complete */
474+ for (to = 10000; to >= 0; --to) {
475+ mxmr = in_be32(lbcfg_mxmr);
476+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
477+ break;
478+ }
479+ if (to == 0) {
480+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
481+ }
482+ }
483+ }
484+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
485+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
486+ out_be32(lbcfg_mxmr, mxmr);
487+}
488+
489+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
490+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
491+ void *lbcfgBase;
492+ unsigned upmData[UPM_DATA_SIZE];
493+
494+ if (gen_upm_data(mode, info, upmData)) {
495+ return -1;
496+ }
497+
498+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
499+
500+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
501+ iounmap(lbcfgBase);
502+ return 0;
503+}
504+
505+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
506+{
507+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
508+ int mode = adev->pio_mode - XFER_PIO_0;
509+
510+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
511+ if (mode < 0) mode = 0;
512+ if (mode > 6) mode = 6;
513+
514+ if (info->cur_mode < 0 || info->cur_mode > mode) {
515+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
516+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
517+ info->cur_mode = mode;
518+ }
519+ }
520+}
521+
522+static struct scsi_host_template rbppc_cf_sht = {
523+ ATA_BASE_SHT(DRV_NAME),
524+};
525+
526+static struct ata_port_operations rbppc_cf_port_ops = {
527+ .inherits = &ata_bmdma_port_ops,
528+
529+ .sff_check_status = rbppc_cf_check_status,
530+ .sff_check_altstatus = rbppc_cf_check_altstatus,
531+
532+ .set_piomode = rbppc_cf_set_piomode,
533+
534+ .port_start = rbppc_cf_dummy_ret0,
535+
536+ .sff_irq_clear = rbppc_cf_dummy_noret,
537+};
538+
539+static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
540+ struct device_node *np;
541+ struct resource res;
542+ const u32 *u32ptr;
543+ void *lbcfgBase;
544+ void *lbcfg_lcrr;
545+ unsigned lbc_clk_khz;
546+ unsigned lbc_extra_divider = 1;
547+ unsigned ccb_freq_hz;
548+ unsigned lb_div;
549+
550+ u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
551+ if (u32ptr && *u32ptr) {
552+ lbc_extra_divider = *u32ptr;
553+#if DEBUG_UPM
554+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
555+ lbc_extra_divider);
556+#endif
557+ }
558+
559+ np = of_find_node_by_type(NULL, "serial");
560+ if (!np) {
561+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
562+ return -1;
563+ }
564+ u32ptr = of_get_property(np, "clock-frequency", NULL);
565+ if (u32ptr == 0 || *u32ptr == 0) {
566+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
567+ of_node_put(np);
568+ return -1;
569+ }
570+ ccb_freq_hz = *u32ptr;
571+ of_node_put(np);
572+
573+ np = of_find_node_by_type(NULL, "soc");
574+ if (!np) {
575+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
576+ return -1;
577+ }
578+ if (of_address_to_resource(np, 0, &res)) {
579+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
580+ of_node_put(np);
581+ return -1;
582+ }
583+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
584+ of_node_put(np);
585+
586+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
587+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
588+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
589+ iounmap(lbcfgBase);
590+
591+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
592+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
593+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
594+ lbc_clk_khz, info->clk_time_ps);
595+
596+ u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
597+ if (u32ptr) {
598+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
599+#if DEBUG_UPM
600+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
601+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
602+#endif
603+ }
604+ info->cur_mode = -1;
605+ return 0;
606+}
607+
608+static int rbppc_cf_probe(struct platform_device *pdev)
609+{
610+ struct ata_host *host;
611+ struct ata_port *ap;
612+ struct rbppc_cf_info *info = NULL;
613+ struct resource res;
614+ void *baddr;
615+ const u32 *u32ptr;
616+ int irq_level = 0;
617+ int err = -ENOMEM;
618+
619+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
620+
621+ if (rbinfo == NULL) {
622+ info = kmalloc(sizeof(*info), GFP_KERNEL);
623+ if (info == NULL) {
624+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
625+ goto err_info;
626+ }
627+ memset(info, 0, sizeof(*info));
628+
629+ if (rbppc_cf_init_info(pdev, info)) {
630+ goto err_info;
631+ }
632+ rbinfo = info;
633+ }
634+
635+ u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
636+ if (u32ptr) {
637+ irq_level = *u32ptr;
638+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
639+ }
640+
641+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
642+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
643+ goto err_info;
644+ }
645+
646+ host = ata_host_alloc(&pdev->dev, 1);
647+ if (!host)
648+ goto err_info;
649+
650+ baddr = localbus_map(res.start, res.end - res.start + 1);
651+ host->iomap = baddr;
652+ host->private_data = rbinfo;
653+
654+ ap = host->ports[0];
655+ ap->ops = &rbppc_cf_port_ops;
656+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
657+ ap->mwdma_mask = 0;
658+
659+ ap->ioaddr.cmd_addr = baddr;
660+ ata_sff_std_ports(&ap->ioaddr);
661+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
662+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
663+ ap->ioaddr.bmdma_addr = 0;
664+
665+ err = ata_host_activate(
666+ host,
667+ irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
668+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
669+ &rbppc_cf_sht);
670+ if (!err) return 0;
671+
672+ localbus_unmap(baddr);
673+err_info:
674+ if (info) {
675+ kfree(info);
676+ rbinfo = NULL;
677+ }
678+ return err;
679+}
680+
681+static int rbppc_cf_remove(struct platform_device *pdev)
682+{
683+ struct device *dev = &pdev->dev;
684+ struct ata_host *host = dev_get_drvdata(dev);
685+
686+ if (host == NULL) return -1;
687+
688+ ata_host_detach(host);
689+ return 0;
690+}
691+
692+static struct of_device_id rbppc_cf_ids[] = {
693+ { .name = "cf", },
694+ { },
695+};
696+
697+static struct platform_driver rbppc_cf_driver = {
698+ .probe = rbppc_cf_probe,
699+ .remove = rbppc_cf_remove,
700+ .driver = {
701+ .name = "rbppc-cf",
702+ .owner = THIS_MODULE,
703+ .of_match_table = rbppc_cf_ids,
704+ },
705+};
706+
707+static int __init rbppc_init(void)
708+{
709+ return platform_driver_register(&rbppc_cf_driver);
710+}
711+
712+static void __exit rbppc_exit(void)
713+{
714+ platform_driver_unregister(&rbppc_cf_driver);
715+}
716+
717+MODULE_AUTHOR("Mikrotikls SIA");
718+MODULE_AUTHOR("Noah Fontes");
719+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
720+MODULE_LICENSE("GPL");
721+MODULE_VERSION(DRV_VERSION);
722+
723+module_init(rbppc_init);
724+module_exit(rbppc_exit);
target/linux/mpc83xx/patches-3.7/203-mtd-add-rbppc_nand-driver.patch
1--- a/drivers/mtd/nand/Kconfig
2@@ -454,6 +454,13 @@ config MTD_NAND_PLATFORM
3       devices. You will need to provide platform-specific functions
4       via platform_data.
5
6+config MTD_NAND_RB_PPC
7+ tristate "MikroTik RB333/600 NAND support"
8+ depends on RB_PPC
9+ help
10+ This option enables support for the NAND device on MikroTik
11+ RouterBOARD 333/600 series boards.
12+
13 config MTD_ALAUDA
14     tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
15     depends on USB
16--- a/drivers/mtd/nand/Makefile
17@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
18 obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
19 obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
20 obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
21+obj-$(CONFIG_MTD_NAND_RB_PPC) += rbppc_nand.o
22 obj-$(CONFIG_MTD_ALAUDA) += alauda.o
23 obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
24 obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
25--- /dev/null
26@@ -0,0 +1,250 @@
27+/*
28+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
29+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
30+ * Copyright (C) Mikrotik 2007
31+ *
32+ * This program is free software; you can redistribute it and/or modify it
33+ * under the terms of the GNU General Public License as published by the
34+ * Free Software Foundation; either version 2 of the License, or (at your
35+ * option) any later version.
36+ */
37+
38+#include <linux/init.h>
39+#include <linux/module.h>
40+#include <linux/mtd/nand.h>
41+#include <linux/mtd/mtd.h>
42+#include <linux/mtd/partitions.h>
43+#include <linux/of_platform.h>
44+#include <linux/of_device.h>
45+#include <linux/slab.h>
46+#include <linux/delay.h>
47+#include <asm/io.h>
48+
49+#define DRV_NAME "rbppc_nand"
50+#define DRV_VERSION "0.0.2"
51+
52+static struct mtd_info rmtd;
53+static struct nand_chip rnand;
54+
55+struct rbppc_nand_info {
56+ void *gpi;
57+ void *gpo;
58+ void *localbus;
59+
60+ unsigned gpio_rdy;
61+ unsigned gpio_nce;
62+ unsigned gpio_cle;
63+ unsigned gpio_ale;
64+ unsigned gpio_ctrls;
65+};
66+
67+/* We must use the OOB layout from yaffs 1 if we want this to be recognized
68+ * properly. Borrowed from the OpenWRT patches for the RB532.
69+ *
70+ * See <https://dev.openwrt.org/browser/trunk/target/linux/rb532/
71+ * patches-2.6.28/025-rb532_nand_fixup.patch> for more details.
72+ */
73+static struct nand_ecclayout rbppc_nand_oob_16 = {
74+ .eccbytes = 6,
75+ .eccpos = { 8, 9, 10, 13, 14, 15 },
76+ .oobavail = 9,
77+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
78+};
79+
80+static struct mtd_partition rbppc_nand_partition_info[] = {
81+ {
82+ name: "kernel",
83+ offset: 0,
84+ size: 4 * 1024 * 1024,
85+ },
86+ {
87+ name: "rootfs",
88+ offset: MTDPART_OFS_NXTBLK,
89+ size: MTDPART_SIZ_FULL,
90+ },
91+};
92+
93+static int rbppc_nand_dev_ready(struct mtd_info *mtd) {
94+ struct nand_chip *chip = mtd->priv;
95+ struct rbppc_nand_info *priv = chip->priv;
96+
97+ return in_be32(priv->gpi) & priv->gpio_rdy;
98+}
99+
100+static void rbppc_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
101+ struct nand_chip *chip = mtd->priv;
102+ struct rbppc_nand_info *priv = chip->priv;
103+
104+ if (ctrl & NAND_CTRL_CHANGE) {
105+ unsigned val = in_be32(priv->gpo);
106+ if (!(val & priv->gpio_nce)) {
107+ /* make sure Local Bus has done NAND operations */
108+ readb(priv->localbus);
109+ }
110+
111+ if (ctrl & NAND_CLE) {
112+ val |= priv->gpio_cle;
113+ } else {
114+ val &= ~priv->gpio_cle;
115+ }
116+ if (ctrl & NAND_ALE) {
117+ val |= priv->gpio_ale;
118+ } else {
119+ val &= ~priv->gpio_ale;
120+ }
121+ if (!(ctrl & NAND_NCE)) {
122+ val |= priv->gpio_nce;
123+ } else {
124+ val &= ~priv->gpio_nce;
125+ }
126+ out_be32(priv->gpo, val);
127+
128+ /* make sure GPIO output has changed */
129+ val ^= in_be32(priv->gpo);
130+ if (val & priv->gpio_ctrls) {
131+ printk(KERN_ERR "rbppc_nand_hwcontrol: NAND GPO change failed 0x%08x\n", val);
132+ }
133+ }
134+
135+ if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W);
136+}
137+
138+static void rbppc_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
139+{
140+ struct nand_chip *chip = mtd->priv;
141+ memcpy(buf, chip->IO_ADDR_R, len);
142+}
143+
144+static unsigned init_ok = 0;
145+
146+static int __devinit rbppc_nand_probe(struct platform_device *pdev)
147+{
148+ struct device_node *gpio;
149+ struct device_node *nnand;
150+ struct resource res;
151+ struct rbppc_nand_info *info;
152+ void *baddr;
153+ const unsigned *rdy, *nce, *cle, *ale;
154+
155+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 333/600 series NAND driver, version " DRV_VERSION "\n");
156+
157+ info = kmalloc(sizeof(*info), GFP_KERNEL);
158+
159+ rdy = of_get_property(pdev->dev.of_node, "rdy", NULL);
160+ nce = of_get_property(pdev->dev.of_node, "nce", NULL);
161+ cle = of_get_property(pdev->dev.of_node, "cle", NULL);
162+ ale = of_get_property(pdev->dev.of_node, "ale", NULL);
163+
164+ if (!rdy || !nce || !cle || !ale) {
165+ printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
166+ goto err;
167+ }
168+ if (rdy[0] != nce[0] || rdy[0] != cle[0] || rdy[0] != ale[0]) {
169+ printk(KERN_ERR "rbppc_nand_probe: Different GPIOs are not supported\n");
170+ goto err;
171+ }
172+
173+ gpio = of_find_node_by_phandle(rdy[0]);
174+ if (!gpio) {
175+ printk(KERN_ERR "rbppc_nand_probe: No GPIO<%x> node found\n", *rdy);
176+ goto err;
177+ }
178+ if (of_address_to_resource(gpio, 0, &res)) {
179+ printk(KERN_ERR "rbppc_nand_probe: No reg property in GPIO found\n");
180+ goto err;
181+ }
182+ info->gpo = ioremap_nocache(res.start, res.end - res.start + 1);
183+
184+ if (!of_address_to_resource(gpio, 1, &res)) {
185+ info->gpi = ioremap_nocache(res.start, res.end - res.start + 1);
186+ } else {
187+ info->gpi = info->gpo;
188+ }
189+ of_node_put(gpio);
190+
191+ info->gpio_rdy = 1 << (31 - rdy[1]);
192+ info->gpio_nce = 1 << (31 - nce[1]);
193+ info->gpio_cle = 1 << (31 - cle[1]);
194+ info->gpio_ale = 1 << (31 - ale[1]);
195+ info->gpio_ctrls = info->gpio_nce | info->gpio_cle | info->gpio_ale;
196+
197+ nnand = of_find_node_by_name(NULL, "nnand");
198+ if (!nnand) {
199+ printk("rbppc_nand_probe: No nNAND found\n");
200+ goto err;
201+ }
202+ if (of_address_to_resource(nnand, 0, &res)) {
203+ printk("rbppc_nand_probe: No reg property in nNAND found\n");
204+ goto err;
205+ }
206+ of_node_put(nnand);
207+ info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
208+
209+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
210+ printk("rbppc_nand_probe: No reg property found\n");
211+ goto err;
212+ }
213+ baddr = ioremap_nocache(res.start, res.end - res.start + 1);
214+
215+ memset(&rnand, 0, sizeof(rnand));
216+ rnand.cmd_ctrl = rbppc_nand_cmd_ctrl;
217+ rnand.dev_ready = rbppc_nand_dev_ready;
218+ rnand.read_buf = rbppc_nand_read_buf;
219+ rnand.IO_ADDR_W = baddr;
220+ rnand.IO_ADDR_R = baddr;
221+ rnand.priv = info;
222+
223+ memset(&rmtd, 0, sizeof(rmtd));
224+ rnand.ecc.mode = NAND_ECC_SOFT;
225+ rnand.ecc.layout = &rbppc_nand_oob_16;
226+ rnand.chip_delay = 25;
227+ rmtd.priv = &rnand;
228+ rmtd.owner = THIS_MODULE;
229+
230+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
231+ printk(KERN_ERR "rbppc_nand_probe: RouterBOARD NAND device not found\n");
232+ return -ENXIO;
233+ }
234+
235+ mtd_device_parse_register(&rmtd, NULL, 0, rbppc_nand_partition_info, 2);
236+ init_ok = 1;
237+ return 0;
238+
239+err:
240+ kfree(info);
241+ return -1;
242+}
243+
244+static struct of_device_id rbppc_nand_ids[] = {
245+ { .name = "nand", },
246+ { },
247+};
248+
249+static struct platform_driver rbppc_nand_driver = {
250+ .probe = rbppc_nand_probe,
251+ .driver = {
252+ .name = "rbppc-nand",
253+ .owner = THIS_MODULE,
254+ .of_match_table = rbppc_nand_ids,
255+ },
256+};
257+
258+static int __init rbppc_nand_init(void)
259+{
260+ return platform_driver_register(&rbppc_nand_driver);
261+}
262+
263+static void __exit rbppc_nand_exit(void)
264+{
265+ platform_driver_unregister(&rbppc_nand_driver);
266+}
267+
268+MODULE_AUTHOR("Mikrotikls SIA");
269+MODULE_AUTHOR("Noah Fontes");
270+MODULE_AUTHOR("Michael Guntsche");
271+MODULE_DESCRIPTION("MikroTik RouterBOARD 333/600 series NAND driver");
272+MODULE_LICENSE("GPL");
273+MODULE_VERSION(DRV_VERSION);
274+
275+module_init(rbppc_nand_init);
276+module_exit(rbppc_nand_exit);
target/linux/mpc83xx/patches-3.7/300-mpc8377_wlan-dts-add-openwrt-hacks.patch
1--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
2@@ -81,6 +81,11 @@
3                 reg = <0x3a0000 0x3c60000>;
4                 label = "rootfs";
5             };
6+
7+ partition1@a0000 {
8+ reg = <0xa0000 0x3f60000>;
9+ label = "firmware";
10+ };
11         };
12     };
13
14@@ -476,4 +481,8 @@
15             default-state = "off";
16         };
17     };
18+
19+ chosen {
20+ bootargs = "console=ttyS0,115200 rootfstype=squashfs noinitrd";
21+ };
22 };

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