Date:2010-01-11 03:13:58 (3 years 4 months ago)
Author:Lars C.
Commit:8932999d6e7b0047196662c38afad07848d6035c
Message:jz4740: New timer module
Files: target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/timer.h (1 diff)
target/linux/xburst/files-2.6.31/arch/mips/jz4740/time.c (1 diff)

Change Details

target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/timer.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_TIMER
17#define __ASM_MACH_JZ4740_TIMER
18
19void jz4740_timer_enable_watchdog(void);
20void jz4740_timer_disable_watchdog(void);
21
22#endif
target/linux/xburst/files-2.6.31/arch/mips/jz4740/time.c
11/*
2 * linux/arch/mips/jz4740/time.c
3 *
4 * Setting up the clock on the JZ4740 boards.
5 *
6 * Copyright (C) 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
84 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
129 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
2113 *
2214 */
23#include <linux/types.h>
15
16#include <linux/kernel.h>
2417#include <linux/interrupt.h>
2518#include <linux/time.h>
2619#include <linux/clockchips.h>
20#include <linux/clk.h>
2721
28#include <asm/time.h>
29#include <asm/mach-jz4740/regs.h>
22#include <asm/mach-jz4740/irq.h>
3023#include <asm/mach-jz4740/jz4740.h>
24#include <asm/time.h>
3125
32/* This is for machines which generate the exact clock. */
26#define JZ_REG_TIMER_STOP 0x1C
27#define JZ_REG_TIMER_STOP_SET 0x2C
28#define JZ_REG_TIMER_STOP_CLEAR 0x3C
29#define JZ_REG_TIMER_ENABLE 0x10
30#define JZ_REG_TIMER_ENABLE_SET 0x14
31#define JZ_REG_TIMER_ENABLE_CLEAR 0x18
32#define JZ_REG_TIMER_FLAG 0x20
33#define JZ_REG_TIMER_FLAG_SET 0x24
34#define JZ_REG_TIMER_FLAG_CLEAR 0x28
35#define JZ_REG_TIMER_MASK 0x30
36#define JZ_REG_TIMER_MASK_SET 0x34
37#define JZ_REG_TIMER_MASK_CLEAR 0x38
3338
34#define JZ_TIMER_CHAN 0
35#define JZ_TIMER_IRQ JZ_IRQ_TCU0
39#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
40#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
41#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
42#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
3643
37#define JZ_TIMER_CLOCK (JZ_EXTAL>>4) /* Jz timer clock frequency */
44#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
45#define JZ_TIMER_IRQ_FULL(x) BIT(x)
3846
39static struct clocksource clocksource_jz; /* Jz clock source */
40static struct clock_event_device jz_clockevent_device; /* Jz clock event */
47#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
48#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
49#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
50#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
51#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
52#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
53#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
54#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
55#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
56#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
4157
42void (*jz_timer_callback)(void);
58#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
59#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
60#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
61
62static void __iomem *jz4740_timer_base;
63static uint16_t jz4740_clocksource_counter;
64static uint16_t jz4740_jiffies_per_tick;
65
66void jz4740_timer_enable_watchdog(void)
67{
68    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
69}
4370
44static irqreturn_t jz_timer_interrupt(int irq, void *dev_id)
71void jz4740_timer_disable_watchdog(void)
4572{
46    struct clock_event_device *cd = dev_id;
73    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
74}
4775
48    REG_TCU_TFCR = 1 << JZ_TIMER_CHAN; /* ACK timer */
76static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
77{
78    writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
79}
4980
50    if (jz_timer_callback)
51        jz_timer_callback();
81static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
82{
83    writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
84}
5285
53    cd->event_handler(cd);
86static void jz4740_init_timer(void)
87{
88    uint16_t val = 0;
89    val |= JZ_TIMER_CTRL_PRESCALE_16;
90    val |= JZ_TIMER_CTRL_SRC_EXT;
5491
55    return IRQ_HANDLED;
92    writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
93    writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
94    writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
95    writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
5696}
5797
58static struct irqaction jz_irqaction = {
59    .handler = jz_timer_interrupt,
60    .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
61    .name = "jz-timerirq",
62};
98static void jz4740_timer_enable(unsigned int timer)
99{
100    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
101    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
102}
63103
104static void jz4740_timer_disable(unsigned int timer)
105{
106    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
107    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
108}
64109
65cycle_t jz_get_cycles(void)
110static void jz4740_timer_irq_full_enable(unsigned int timer)
66111{
67    /* convert jiffes to jz timer cycles */
68    return (cycle_t)( jiffies*((JZ_TIMER_CLOCK)/HZ) + REG_TCU_TCNT(JZ_TIMER_CHAN));
112    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
113    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
69114}
70115
71static struct clocksource clocksource_jz = {
72    .name = "jz_clocksource",
73    .rating = 300,
74    .read = jz_get_cycles,
75    .mask = 0xFFFF,
76    .shift = 10,
77    .flags = CLOCK_SOURCE_WATCHDOG,
78};
116static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
117{
118    return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
119    JZ_TIMER_IRQ_FULL(timer));
120}
79121
80static int __init jz_clocksource_init(void)
122static void jz4740_timer_irq_full_disable(unsigned int timer)
81123{
82    clocksource_jz.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, clocksource_jz.shift);
83    clocksource_register(&clocksource_jz);
84    return 0;
124    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
85125}
86126
87static int jz_set_next_event(unsigned long evt,
88                  struct clock_event_device *unused)
127static void jz4740_timer_irq_half_enable(unsigned int timer)
89128{
90    return 0;
129    writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
130    writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
91131}
92132
93static void jz_set_mode(enum clock_event_mode mode,
94            struct clock_event_device *evt)
133static void jz4740_timer_irq_half_disable(unsigned int timer)
95134{
96    switch (mode) {
97    case CLOCK_EVT_MODE_PERIODIC:
98                break;
99        case CLOCK_EVT_MODE_ONESHOT:
100        case CLOCK_EVT_MODE_UNUSED:
101        case CLOCK_EVT_MODE_SHUTDOWN:
102                break;
103        case CLOCK_EVT_MODE_RESUME:
104                break;
105        }
106}
107
108static struct clock_event_device jz_clockevent_device = {
109    .name = "jz-clockenvent",
110    .features = CLOCK_EVT_FEAT_PERIODIC,
111// .features = CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
112
113    /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
114    .mult = 1,
115    .rating = 300,
116    .irq = JZ_TIMER_IRQ,
117    .set_mode = jz_set_mode,
118    .set_next_event = jz_set_next_event,
135    writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
136}
137
138static cycle_t jz4740_clocksource_read(struct clocksource *cs)
139{
140    uint16_t val;
141    val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
142    return val;
143}
144
145static struct clocksource jz4740_clocksource = {
146    .name = "jz4740-timer",
147    .rating = 200,
148    .read = jz4740_clocksource_read,
149    .mask = CLOCKSOURCE_MASK(16),
150    .flags = CLOCK_SOURCE_IS_CONTINUOUS,
119151};
120152
121static void __init jz_clockevent_init(void)
153static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
122154{
123    struct clock_event_device *cd = &jz_clockevent_device;
124    unsigned int cpu = smp_processor_id();
155    struct clock_event_device *cd = devid;
156
157    writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
158
159    if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
160        jz4740_timer_disable(0);
161        cd->event_handler(cd);
162     } else {
163        cd->event_handler(cd);
164    }
165
166    return IRQ_HANDLED;
167}
125168
126    cd->cpumask = cpumask_of(cpu);
127    clockevents_register_device(cd);
169static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
170                       struct clock_event_device *cd)
171{
172    switch(mode) {
173    case CLOCK_EVT_MODE_PERIODIC:
174        writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
175        writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
176    case CLOCK_EVT_MODE_RESUME:
177        jz4740_timer_irq_full_enable(0);
178        jz4740_timer_enable(0);
179        break;
180    case CLOCK_EVT_MODE_ONESHOT:
181    case CLOCK_EVT_MODE_SHUTDOWN:
182        jz4740_timer_disable(0);
183        break;
184    default:
185        break;
186    }
128187}
129188
130static void __init jz_timer_setup(void)
189static int jz4740_clockevent_set_next(unsigned long evt, struct
190clock_event_device *cd)
131191{
132    jz_clocksource_init(); /* init jz clock source */
133    jz_clockevent_init(); /* init jz clock event */
192    writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
193    writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
194    jz4740_timer_enable(0);
134195
135    /*
136     * Make irqs happen for the system timer
137     */
138    jz_irqaction.dev_id = &jz_clockevent_device;
139    setup_irq(JZ_TIMER_IRQ, &jz_irqaction);
196    return 0;
140197}
141198
199static struct clock_event_device jz4740_clockevent = {
200    .name = "jz4740-timer",
201    .features = CLOCK_EVT_FEAT_PERIODIC,
202    .set_next_event = jz4740_clockevent_set_next,
203    .set_mode = jz4740_clockevent_set_mode,
204    .rating = 200,
205    .irq = JZ_IRQ_TCU0,
206};
207
208static struct irqaction jz_irqaction = {
209    .handler = jz4740_clockevent_irq,
210    .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
211    .name = "jz4740-timerirq",
212    .dev_id = &jz4740_clockevent,
213};
214
142215
143216void __init plat_time_init(void)
144217{
145    unsigned int latch;
146    /* Init timer */
147    latch = ( JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
218    int ret;
219    uint32_t clk_rate;
220    struct clk *ext_clk;
221
222    jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
223
224    if (!jz4740_timer_base) {
225        printk(KERN_ERR "Failed to ioremap timer registers");
226        return;
227    }
228
229    /*ext_clk = clk_get(NULL, "ext");
230    clk_rate = clk_get_rate(ext_clk) >> 4;
231    clk_put(ext_clk);*/
232
233
234    clk_rate = JZ_EXTAL >> 4;
235
236    jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
237
238    clockevent_set_clock(&jz4740_clockevent, clk_rate);
239    jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
240    jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
241    jz4740_clockevent.cpumask = cpumask_of(0);
242
243    clockevents_register_device(&jz4740_clockevent);
244
245    clocksource_set_clock(&jz4740_clocksource, clk_rate);
246    ret = clocksource_register(&jz4740_clocksource);
247
248    if (ret)
249        printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
250
251    setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
148252
149    REG_TCU_TCSR(JZ_TIMER_CHAN) = TCU_TCSR_PRESCALE16 | TCU_TCSR_EXT_EN;
150    REG_TCU_TCNT(JZ_TIMER_CHAN) = 0;
151    REG_TCU_TDHR(JZ_TIMER_CHAN) = 0;
152    REG_TCU_TDFR(JZ_TIMER_CHAN) = latch;
253    jz4740_init_timer();
254    writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
255    jz4740_timer_irq_half_disable(0);
256    jz4740_timer_irq_full_enable(0);
257    jz4740_timer_enable(0);
153258
154    REG_TCU_TMSR = (1 << (JZ_TIMER_CHAN + 16)); /* mask half irq */
155    REG_TCU_TMCR = (1 << JZ_TIMER_CHAN); /* unmask full irq */
156    REG_TCU_TSCR = (1 << JZ_TIMER_CHAN); /* enable timer clock */
157    REG_TCU_TESR = (1 << JZ_TIMER_CHAN); /* start counting up */
259    jz4740_timer_irq_half_disable(1);
260    jz4740_timer_irq_full_disable(1);
158261
159    jz_timer_setup();
262    jz4740_timer_enable(1);
160263}

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