Date:2010-08-08 16:16:48 (13 years 7 months ago)
Author:mb
Commit:8b8f4c7a28a7cf8e341dc00367ccd141c5ba9a8e
Message:Add omap24xx.

Boots the kernel with working video and serial console. Userland is untested.


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22530 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/omap24xx/Makefile (1 diff)
target/linux/omap24xx/config-2.6.35 (1 diff)
target/linux/omap24xx/image/Makefile (1 diff)
target/linux/omap24xx/patches-2.6.35/100-optimized-arm-div.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/200-omap-platform.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/300-nokia-board.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/400-bluetooth-hci_h4p.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/500-cbus.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/600-tsc2005.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/700-video-omap.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/800-decompress-unlzo-fixes.patch (1 diff)
target/linux/omap24xx/profiles/100-n810.mk (1 diff)

Change Details

target/linux/omap24xx/Makefile
1#
2# Copyright (C) 2010 OpenWrt.org
3#
4# This is free software, licensed under the GNU General Public License v2.
5# See /LICENSE for more information.
6#
7include $(TOPDIR)/rules.mk
8
9ARCH:=arm
10BOARD:=omap24xx
11BOARDNAME:=TI OMAP-24xx
12FEATURES:=jffs2
13
14LINUX_VERSION:=2.6.35
15
16define Target/Description
17    TI OMAP-24xx
18endef
19
20include $(INCLUDE_DIR)/target.mk
21
22$(eval $(call BuildTarget))
target/linux/omap24xx/config-2.6.35
1# CONFIG_ADIS16209 is not set
2# CONFIG_ADIS16220 is not set
3# CONFIG_ADIS16240 is not set
4# CONFIG_ADIS16260 is not set
5# CONFIG_ADIS16300 is not set
6# CONFIG_ADIS16350 is not set
7# CONFIG_ADIS16400 is not set
8CONFIG_AEABI=y
9CONFIG_ALIGNMENT_TRAP=y
10# CONFIG_APM_EMULATION is not set
11# CONFIG_ARCH_CNS3XXX is not set
12CONFIG_ARCH_HAS_CPUFREQ=y
13CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
14# CONFIG_ARCH_NUC93X is not set
15CONFIG_ARCH_OMAP=y
16# CONFIG_ARCH_OMAP1 is not set
17CONFIG_ARCH_OMAP2=y
18CONFIG_ARCH_OMAP2420=y
19# CONFIG_ARCH_OMAP2430 is not set
20CONFIG_ARCH_OMAP2PLUS=y
21# CONFIG_ARCH_OMAP3 is not set
22# CONFIG_ARCH_OMAP4 is not set
23CONFIG_ARCH_OMAP_OTG=y
24CONFIG_ARCH_REQUIRE_GPIOLIB=y
25# CONFIG_ARCH_S5P6440 is not set
26# CONFIG_ARCH_S5P6442 is not set
27# CONFIG_ARCH_S5PC100 is not set
28# CONFIG_ARCH_S5PV210 is not set
29# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
30# CONFIG_ARCH_SHMOBILE is not set
31# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
32# CONFIG_ARCH_SUPPORTS_MSI is not set
33CONFIG_ARCH_SUSPEND_POSSIBLE=y
34# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
35# CONFIG_ARCH_VEXPRESS is not set
36CONFIG_ARM=y
37CONFIG_ARM_DMA_MEM_BUFFERABLE=y
38CONFIG_ARM_ERRATA_411920=y
39CONFIG_ARM_L1_CACHE_SHIFT=5
40CONFIG_ARM_THUMB=y
41CONFIG_ARM_UNWIND=y
42# CONFIG_ARPD is not set
43CONFIG_ATAGS_PROC=y
44CONFIG_BINFMT_MISC=y
45CONFIG_BITREVERSE=y
46CONFIG_BLK_DEV_LOOP=y
47CONFIG_BLK_DEV_RAM=y
48CONFIG_BLK_DEV_RAM_COUNT=16
49CONFIG_BLK_DEV_RAM_SIZE=4096
50CONFIG_BLK_DEV_SD=y
51# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
52CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
53# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
54CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
55CONFIG_BRANCH_PROFILE_NONE=y
56CONFIG_BRIDGE=m
57CONFIG_BRIDGE_NETFILTER=y
58# CONFIG_BSD_PROCESS_ACCT is not set
59CONFIG_BT=m
60CONFIG_BT_BNEP=m
61# CONFIG_BT_BNEP_MC_FILTER is not set
62# CONFIG_BT_BNEP_PROTO_FILTER is not set
63CONFIG_BT_HCIH4P=m
64CONFIG_BT_HIDP=m
65CONFIG_BT_L2CAP=m
66CONFIG_BT_RFCOMM=m
67CONFIG_BT_SCO=m
68CONFIG_CBUS=y
69CONFIG_CBUS_RETU=y
70# CONFIG_CBUS_RETU_HEADSET is not set
71CONFIG_CBUS_RETU_POWERBUTTON=y
72CONFIG_CBUS_RETU_RTC=y
73CONFIG_CBUS_RETU_USER=y
74CONFIG_CBUS_RETU_WDT=y
75CONFIG_CBUS_TAHVO=y
76CONFIG_CBUS_TAHVO_USER=y
77CONFIG_CC_OPTIMIZE_FOR_SIZE=y
78CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS2,115200 console=tty0"
79CONFIG_CMDLINE_FORCE=y
80CONFIG_COMMON_CLKDEV=y
81CONFIG_COMPAT_BRK=y
82CONFIG_CONSOLE_TRANSLATIONS=y
83CONFIG_CPU_32v6=y
84# CONFIG_CPU_32v6K is not set
85CONFIG_CPU_ABRT_EV6=y
86# CONFIG_CPU_BPREDICT_DISABLE is not set
87CONFIG_CPU_CACHE_V6=y
88CONFIG_CPU_CACHE_VIPT=y
89CONFIG_CPU_COPY_V6=y
90CONFIG_CPU_CP15=y
91CONFIG_CPU_CP15_MMU=y
92CONFIG_CPU_HAS_ASID=y
93CONFIG_CPU_HAS_PMU=y
94# CONFIG_CPU_ICACHE_DISABLE is not set
95CONFIG_CPU_PABRT_V6=y
96CONFIG_CPU_TLB_V6=y
97CONFIG_CPU_V6=y
98CONFIG_CRC16=y
99CONFIG_CRC7=y
100CONFIG_CRC_CCITT=y
101CONFIG_CRC_ITU_T=y
102CONFIG_CRYPTO_AEAD2=y
103CONFIG_CRYPTO_AES=y
104CONFIG_CRYPTO_ANSI_CPRNG=y
105CONFIG_CRYPTO_ARC4=y
106CONFIG_CRYPTO_BLKCIPHER=y
107CONFIG_CRYPTO_BLKCIPHER2=y
108# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set
109CONFIG_CRYPTO_ECB=y
110CONFIG_CRYPTO_HASH=m
111CONFIG_CRYPTO_HASH2=y
112CONFIG_CRYPTO_HW=y
113CONFIG_CRYPTO_MANAGER=y
114CONFIG_CRYPTO_MANAGER2=y
115CONFIG_CRYPTO_RNG=y
116CONFIG_CRYPTO_RNG2=y
117CONFIG_CRYPTO_SHA1=m
118CONFIG_CRYPTO_WORKQUEUE=y
119# CONFIG_CRYPTO_ZLIB is not set
120CONFIG_CUSE=m
121CONFIG_DEBUG_BUGVERBOSE=y
122CONFIG_DEBUG_ERRORS=y
123# CONFIG_DEBUG_FS is not set
124CONFIG_DEBUG_GPIO=y
125CONFIG_DEBUG_INFO=y
126CONFIG_DEBUG_KERNEL=y
127CONFIG_DEBUG_MEMORY_INIT=y
128CONFIG_DEBUG_PREEMPT=y
129CONFIG_DEBUG_USER=y
130CONFIG_DECOMPRESS_BZIP2=y
131CONFIG_DECOMPRESS_GZIP=y
132CONFIG_DECOMPRESS_LZMA=y
133CONFIG_DECOMPRESS_LZO=y
134CONFIG_DEFAULT_CFQ=y
135# CONFIG_DEFAULT_DEADLINE is not set
136CONFIG_DEFAULT_IOSCHED="cfq"
137CONFIG_DEFAULT_TCP_CONG="cubic"
138CONFIG_DETECT_HUNG_TASK=y
139CONFIG_DETECT_SOFTLOCKUP=y
140CONFIG_DEVKMEM=y
141CONFIG_DEVTMPFS=y
142CONFIG_DEVTMPFS_MOUNT=y
143CONFIG_DNOTIFY=y
144CONFIG_DUMMY_CONSOLE=y
145CONFIG_ELF_CORE=y
146# CONFIG_EMBEDDED is not set
147# CONFIG_ENABLE_DEFAULT_TRACERS is not set
148CONFIG_ENABLE_MUST_CHECK=y
149CONFIG_EXT2_FS=y
150CONFIG_EXT2_FS_POSIX_ACL=y
151# CONFIG_EXT2_FS_SECURITY is not set
152CONFIG_EXT2_FS_XATTR=y
153CONFIG_EXT2_FS_XIP=y
154CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
155CONFIG_EXT3_FS=m
156CONFIG_EXT3_FS_POSIX_ACL=y
157# CONFIG_EXT3_FS_SECURITY is not set
158CONFIG_EXT3_FS_XATTR=y
159CONFIG_FAT_FS=y
160CONFIG_FB=y
161CONFIG_FB_CFB_COPYAREA=y
162CONFIG_FB_CFB_FILLRECT=y
163CONFIG_FB_CFB_IMAGEBLIT=y
164CONFIG_FB_OMAP=y
165CONFIG_FB_OMAP_BOOTLOADER_INIT=y
166CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
167CONFIG_FB_OMAP_LCDC_BLIZZARD=y
168CONFIG_FB_OMAP_LCDC_EXTERNAL=y
169# CONFIG_FB_OMAP_LCDC_HWA742 is not set
170CONFIG_FB_OMAP_LCD_MIPID=y
171# CONFIG_FB_OMAP_MANUAL_UPDATE is not set
172# CONFIG_FB_SM7XX is not set
173# CONFIG_FIRMWARE_EDID is not set
174CONFIG_FIRMWARE_IN_KERNEL=y
175CONFIG_FONTS=y
176# CONFIG_FONT_10x18 is not set
177# CONFIG_FONT_6x11 is not set
178# CONFIG_FONT_7x14 is not set
179CONFIG_FONT_8x16=y
180CONFIG_FONT_8x8=y
181# CONFIG_FONT_ACORN_8x8 is not set
182# CONFIG_FONT_MINI_4x6 is not set
183# CONFIG_FONT_PEARL_8x8 is not set
184# CONFIG_FONT_SUN12x22 is not set
185# CONFIG_FONT_SUN8x16 is not set
186# CONFIG_FPE_FASTFPE is not set
187CONFIG_FPE_NWFPE=y
188# CONFIG_FPE_NWFPE_XP is not set
189CONFIG_FRAMEBUFFER_CONSOLE=y
190# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
191# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
192CONFIG_FREEZER=y
193CONFIG_FS_MBCACHE=y
194CONFIG_FS_POSIX_ACL=y
195CONFIG_FS_XIP=y
196CONFIG_FTRACE=y
197CONFIG_FUSE_FS=m
198CONFIG_GENERIC_ACL=y
199CONFIG_GENERIC_ATOMIC64=y
200CONFIG_GENERIC_CLOCKEVENTS=y
201CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
202CONFIG_GENERIC_FIND_LAST_BIT=y
203CONFIG_GENERIC_GPIO=y
204CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
205CONFIG_GPIOLIB=y
206CONFIG_GPIO_SYSFS=y
207# CONFIG_HAMRADIO is not set
208CONFIG_HARDIRQS_SW_RESEND=y
209CONFIG_HAS_DMA=y
210CONFIG_HAS_IOMEM=y
211CONFIG_HAS_IOPORT=y
212CONFIG_HAVE_AOUT=y
213CONFIG_HAVE_ARCH_KGDB=y
214CONFIG_HAVE_CLK=y
215CONFIG_HAVE_FUNCTION_TRACER=y
216CONFIG_HAVE_GENERIC_DMA_COHERENT=y
217CONFIG_HAVE_IDE=y
218CONFIG_HAVE_KERNEL_GZIP=y
219CONFIG_HAVE_KERNEL_LZMA=y
220CONFIG_HAVE_KERNEL_LZO=y
221CONFIG_HAVE_KPROBES=y
222CONFIG_HAVE_KRETPROBES=y
223CONFIG_HAVE_LATENCYTOP_SUPPORT=y
224CONFIG_HAVE_MTD_OTP=y
225CONFIG_HAVE_OPROFILE=y
226CONFIG_HAVE_PERF_EVENTS=y
227CONFIG_HAVE_PROC_CPU=y
228CONFIG_HID=y
229CONFIG_HID_APPLE=m
230CONFIG_HID_SUPPORT=y
231CONFIG_HID_WACOM=m
232# CONFIG_HID_WACOM_POWER_SUPPLY is not set
233CONFIG_HWMON=m
234# CONFIG_HWMON_DEBUG_CHIP is not set
235CONFIG_HW_CONSOLE=y
236CONFIG_HW_RANDOM=y
237CONFIG_HW_RANDOM_OMAP=y
238CONFIG_HZ=128
239CONFIG_I2C=y
240CONFIG_I2C_BOARDINFO=y
241CONFIG_I2C_CHARDEV=y
242CONFIG_I2C_COMPAT=y
243CONFIG_I2C_HELPER_AUTO=y
244CONFIG_I2C_OMAP=y
245CONFIG_IIO=y
246# CONFIG_IIO_RING_BUFFER is not set
247# CONFIG_IIO_TRIGGER is not set
248CONFIG_INET6_XFRM_MODE_BEET=m
249CONFIG_INET6_XFRM_MODE_TRANSPORT=m
250CONFIG_INET6_XFRM_MODE_TUNNEL=m
251CONFIG_INET_DIAG=y
252CONFIG_INET_TCP_DIAG=y
253CONFIG_INET_TUNNEL=m
254CONFIG_INET_XFRM_MODE_BEET=y
255CONFIG_INITRAMFS_SOURCE=""
256# CONFIG_INLINE_READ_UNLOCK is not set
257# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
258# CONFIG_INLINE_SPIN_UNLOCK is not set
259# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
260# CONFIG_INLINE_WRITE_UNLOCK is not set
261# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
262CONFIG_INOTIFY=y
263CONFIG_INOTIFY_USER=y
264CONFIG_INPUT=y
265CONFIG_INPUT_EVDEV=y
266CONFIG_INPUT_KEYBOARD=y
267# CONFIG_INPUT_MISC is not set
268CONFIG_INPUT_MOUSEDEV=y
269# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
270CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
271CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
272CONFIG_INPUT_TOUCHSCREEN=y
273CONFIG_IOSCHED_CFQ=y
274# CONFIG_IOSCHED_DEADLINE is not set
275CONFIG_IPV6=y
276CONFIG_IPV6_MIP6=m
277CONFIG_IPV6_PRIVACY=y
278CONFIG_IPV6_ROUTER_PREF=y
279CONFIG_IPV6_SIT=m
280# CONFIG_IP_ADVANCED_ROUTER is not set
281# CONFIG_IP_MROUTE is not set
282CONFIG_IP_NF_FILTER=y
283CONFIG_IP_NF_IPTABLES=y
284CONFIG_IR_CORE=m
285# CONFIG_ISDN is not set
286CONFIG_JBD=m
287CONFIG_JFFS2_LZO=y
288CONFIG_JFFS2_ZLIB=y
289CONFIG_KALLSYMS=y
290CONFIG_KERNEL_GZIP=y
291# CONFIG_KERNEL_LZMA is not set
292CONFIG_KEXEC=y
293# CONFIG_KEYBOARD_ATKBD is not set
294# CONFIG_KEYBOARD_GPIO is not set
295# CONFIG_KEYBOARD_LKKBD is not set
296CONFIG_KEYBOARD_LM8323=y
297# CONFIG_KEYBOARD_MATRIX is not set
298# CONFIG_KEYBOARD_NEWTON is not set
299# CONFIG_KEYBOARD_OMAP is not set
300# CONFIG_KEYBOARD_STOWAWAY is not set
301# CONFIG_KEYBOARD_SUNKBD is not set
302# CONFIG_KEYBOARD_XTKBD is not set
303# CONFIG_KXSD9 is not set
304# CONFIG_LBDAF is not set
305CONFIG_LEDS=y
306# CONFIG_LEDS_GPIO is not set
307CONFIG_LEDS_TRIGGER_BACKLIGHT=y
308CONFIG_LEDS_TRIGGER_GPIO=y
309# CONFIG_LIS3L02DQ is not set
310CONFIG_LLC=m
311CONFIG_LOCALVERSION_AUTO=y
312CONFIG_LOCK_KERNEL=y
313CONFIG_LOG_BUF_SHIFT=21
314CONFIG_LZO_COMPRESS=y
315CONFIG_LZO_DECOMPRESS=y
316CONFIG_MACH_NOKIA_N800=y
317CONFIG_MACH_NOKIA_N810=y
318CONFIG_MACH_NOKIA_N810_WIMAX=y
319CONFIG_MACH_NOKIA_N8X0=y
320CONFIG_MACH_NOKIA_N8X0_LCD=y
321CONFIG_MACH_NOKIA_N8X0_USB=y
322CONFIG_MACH_OMAP2_TUSB6010=y
323# CONFIG_MACH_OMAP_2430SDP is not set
324# CONFIG_MACH_OMAP_APOLLON is not set
325# CONFIG_MACH_OMAP_GENERIC is not set
326# CONFIG_MACH_OMAP_H4 is not set
327CONFIG_MACVLAN=m
328# CONFIG_MAX1363 is not set
329CONFIG_MEDIA_ATTACH=y
330CONFIG_MEDIA_SUPPORT=m
331CONFIG_MEDIA_TUNER=m
332CONFIG_MEDIA_TUNER_MC44S803=m
333CONFIG_MEDIA_TUNER_MT20XX=m
334CONFIG_MEDIA_TUNER_SIMPLE=m
335CONFIG_MEDIA_TUNER_TDA8290=m
336CONFIG_MEDIA_TUNER_TDA9887=m
337CONFIG_MEDIA_TUNER_TEA5761=m
338CONFIG_MEDIA_TUNER_TEA5767=m
339CONFIG_MEDIA_TUNER_XC2028=m
340CONFIG_MEDIA_TUNER_XC5000=m
341CONFIG_MENELAUS=y
342# CONFIG_MFD_T7L66XB is not set
343# CONFIG_MISC_DEVICES is not set
344CONFIG_MMC=y
345CONFIG_MMC_BLOCK=y
346CONFIG_MMC_OMAP=y
347CONFIG_MMC_SPI=y
348CONFIG_MMC_UNSAFE_RESUME=y
349CONFIG_MODULE_FORCE_LOAD=y
350CONFIG_MODULE_FORCE_UNLOAD=y
351CONFIG_MSDOS_FS=y
352CONFIG_MTD_BLOCK2MTD=y
353# CONFIG_MTD_CFI is not set
354CONFIG_MTD_CMDLINE_PARTS=y
355# CONFIG_MTD_COMPLEX_MAPPINGS is not set
356CONFIG_MTD_ONENAND=y
357# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
358# CONFIG_MTD_ONENAND_GENERIC is not set
359CONFIG_MTD_ONENAND_OMAP2=y
360CONFIG_MTD_ONENAND_OTP=y
361# CONFIG_MTD_ONENAND_SIM is not set
362# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
363CONFIG_NAMESPACES=y
364CONFIG_NEED_DMA_MAP_STATE=y
365CONFIG_NETDEV_10000=y
366CONFIG_NETFILTER_XTABLES=y
367# CONFIG_NET_ETHERNET is not set
368# CONFIG_NET_NS is not set
369# CONFIG_NET_SCHED is not set
370CONFIG_NLS=y
371CONFIG_NO_HZ=y
372CONFIG_OABI_COMPAT=y
373# CONFIG_OMAP2_DSS is not set
374CONFIG_OMAP_32K_TIMER=y
375CONFIG_OMAP_32K_TIMER_HZ=128
376CONFIG_OMAP_BOOT_REASON=y
377CONFIG_OMAP_BOOT_TAG=y
378CONFIG_OMAP_COMPONENT_VERSION=y
379CONFIG_OMAP_DM_TIMER=y
380CONFIG_OMAP_MBOX_FWK=y
381CONFIG_OMAP_MCBSP=y
382# CONFIG_OMAP_MPU_TIMER is not set
383CONFIG_OMAP_MUX=y
384# CONFIG_OMAP_MUX_DEBUG is not set
385CONFIG_OMAP_MUX_WARNINGS=y
386# CONFIG_OMAP_PM_NONE is not set
387CONFIG_OMAP_PM_NOOP=y
388CONFIG_OMAP_RESET_CLOCKS=y
389CONFIG_OMAP_WATCHDOG=y
390CONFIG_PAGEFLAGS_EXTENDED=y
391CONFIG_PAGE_OFFSET=0xC0000000
392# CONFIG_PARTITION_ADVANCED is not set
393# CONFIG_PCI_SYSCALL is not set
394CONFIG_PERF_USE_VMALLOC=y
395# CONFIG_PLAT_SPEAR is not set
396CONFIG_PM=y
397# CONFIG_PM_DEBUG is not set
398CONFIG_PM_OPS=y
399# CONFIG_PM_RUNTIME is not set
400CONFIG_PM_SLEEP=y
401CONFIG_POSIX_MQUEUE=y
402CONFIG_POSIX_MQUEUE_SYSCTL=y
403CONFIG_PPP=m
404CONFIG_PPP_ASYNC=m
405CONFIG_PPP_BSDCOMP=m
406CONFIG_PPP_DEFLATE=m
407CONFIG_PPP_MPPE=m
408# CONFIG_PPP_MULTILINK is not set
409CONFIG_PPP_SYNC_TTY=m
410CONFIG_PREEMPT=y
411# CONFIG_PREEMPT_NONE is not set
412# CONFIG_PREEMPT_TRACER is not set
413CONFIG_PRINTK_TIME=y
414CONFIG_PROC_PAGE_MONITOR=y
415# CONFIG_PROFILE_ALL_BRANCHES is not set
416# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
417CONFIG_RAMZSWAP=m
418CONFIG_RAMZSWAP_STATS=y
419CONFIG_RD_BZIP2=y
420CONFIG_RD_GZIP=y
421CONFIG_RD_LZO=y
422CONFIG_SCHED_DEBUG=y
423CONFIG_SCSI=y
424# CONFIG_SCSI_LOWLEVEL is not set
425CONFIG_SCSI_MOD=y
426CONFIG_SDIO_UART=m
427CONFIG_SENSORS_LM75=m
428CONFIG_SENSORS_TSL2563=m
429# CONFIG_SERIAL_8250_EXTENDED is not set
430CONFIG_SERIAL_8250_NR_UARTS=4
431CONFIG_SERIAL_8250_RUNTIME_UARTS=4
432CONFIG_SERIO=y
433# CONFIG_SERIO_RAW is not set
434CONFIG_SERIO_SERPORT=y
435# CONFIG_SLAB is not set
436CONFIG_SLHC=m
437CONFIG_SLUB=y
438CONFIG_SLUB_DEBUG=y
439# CONFIG_SLUB_DEBUG_ON is not set
440# CONFIG_SLUB_STATS is not set
441CONFIG_SND=m
442CONFIG_SND_ARM=y
443# CONFIG_SND_EMU10K1_SEQ is not set
444CONFIG_SND_JACK=y
445CONFIG_SND_MIXER_OSS=m
446CONFIG_SND_OMAP_SOC=m
447CONFIG_SND_OMAP_SOC_MCBSP=m
448CONFIG_SND_OMAP_SOC_N810=m
449# CONFIG_SND_OPL3_LIB_SEQ is not set
450# CONFIG_SND_OPL4_LIB_SEQ is not set
451CONFIG_SND_PCM=m
452CONFIG_SND_PCM_OSS=m
453# CONFIG_SND_RAWMIDI_SEQ is not set
454# CONFIG_SND_SBAWE_SEQ is not set
455CONFIG_SND_SOC=m
456# CONFIG_SND_SOC_ALL_CODECS is not set
457CONFIG_SND_SOC_I2C_AND_SPI=m
458CONFIG_SND_SOC_TLV320AIC3X=m
459CONFIG_SND_SPI=y
460CONFIG_SND_SUPPORT_OLD_API=y
461CONFIG_SND_TIMER=m
462CONFIG_SOUND=m
463CONFIG_SOUND_OSS_CORE=y
464CONFIG_SOUND_OSS_CORE_PRECLAIM=y
465CONFIG_SPI=y
466# CONFIG_SPI_BITBANG is not set
467# CONFIG_SPI_GPIO is not set
468CONFIG_SPI_MASTER=y
469CONFIG_SPI_OMAP24XX=y
470# CONFIG_SPI_SPIDEV is not set
471CONFIG_STP=m
472# CONFIG_STRIP_ASM_SYMS is not set
473CONFIG_SUSPEND=y
474CONFIG_SUSPEND_FREEZER=y
475CONFIG_SUSPEND_NVS=y
476# CONFIG_SYN_COOKIES is not set
477# CONFIG_SYSCTL_SYSCALL_CHECK is not set
478CONFIG_SYS_SUPPORTS_APM_EMULATION=y
479# CONFIG_TCP_CONG_ADVANCED is not set
480CONFIG_TCP_CONG_CUBIC=y
481# CONFIG_TINY_RCU is not set
482CONFIG_TMPFS_POSIX_ACL=y
483# CONFIG_TOUCHSCREEN_DYNAPRO is not set
484# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
485# CONFIG_TOUCHSCREEN_MCS5000 is not set
486# CONFIG_TOUCHSCREEN_TPS6507X is not set
487CONFIG_TOUCHSCREEN_TSC2005=y
488CONFIG_TREE_RCU=y
489CONFIG_TUN=m
490CONFIG_UID16=y
491# CONFIG_USB_ARCH_HAS_EHCI is not set
492CONFIG_USB_SUPPORT=y
493# CONFIG_USER_NS is not set
494CONFIG_VECTORS_BASE=0xffff0000
495CONFIG_VFAT_FS=y
496CONFIG_VFP=y
497# CONFIG_VGA_CONSOLE is not set
498CONFIG_VIDEO_ALLOW_V4L1=y
499CONFIG_VIDEO_CAPTURE_DRIVERS=y
500CONFIG_VIDEO_DEV=m
501CONFIG_VIDEO_IR=m
502CONFIG_VIDEO_IR_I2C=m
503CONFIG_VIDEO_MEDIA=m
504# CONFIG_VIDEO_OMAP2 is not set
505# CONFIG_VIDEO_OMAP2_VOUT is not set
506CONFIG_VIDEO_TCM825X=m
507CONFIG_VIDEO_V4L1=m
508CONFIG_VIDEO_V4L2=m
509CONFIG_VIDEO_V4L2_COMMON=m
510CONFIG_VLAN_8021Q=m
511CONFIG_VM_EVENT_COUNTERS=y
512CONFIG_VT=y
513CONFIG_VT_CONSOLE=y
514# CONFIG_VT_HW_CONSOLE_BINDING is not set
515CONFIG_WATCHDOG_NOWAYOUT=y
516# CONFIG_ZBOOT_ROM is not set
517CONFIG_ZBOOT_ROM_BSS=0x10200000
518CONFIG_ZBOOT_ROM_TEXT=0x10C08000
519CONFIG_ZONE_DMA_FLAG=0
target/linux/omap24xx/image/Makefile
1#
2# Copyright (C) 2010 OpenWrt.org
3#
4# This is free software, licensed under the GNU General Public License v2.
5# See /LICENSE for more information.
6#
7include $(TOPDIR)/rules.mk
8include $(INCLUDE_DIR)/image.mk
9
10JFFS2_BLOCKSIZE=128k
11JFFS2OPTS += --little-endian --pagesize=0x800 --no-cleanmarkers --pad
12
13
14define Image/BuildKernel
15    $(CP) $(LINUX_DIR)/arch/arm/boot/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
16    chmod 0644 $(BIN_DIR)/$(IMG_PREFIX)-zImage
17endef
18
19define Image/Build/squashfs
20    $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-root.$(1))
21endef
22
23define Image/Build
24    $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-root.$(1)
25    $(call Image/Build/$(1),$(1))
26endef
27
28
29$(eval $(call BuildImage))
target/linux/omap24xx/patches-2.6.35/100-optimized-arm-div.patch
1---
2 arch/arm/boot/compressed/lib1funcs.S | 348 +++++++++++++++++++++++++++++++++++
3 1 file changed, 348 insertions(+)
4
5--- /dev/null
6@@ -0,0 +1,348 @@
7+/*
8+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
9+ *
10+ * Author: Nicolas Pitre <nico@fluxnic.net>
11+ * - contributed to gcc-3.4 on Sep 30, 2003
12+ * - adapted for the Linux kernel on Oct 2, 2003
13+ */
14+
15+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
16+
17+This file is free software; you can redistribute it and/or modify it
18+under the terms of the GNU General Public License as published by the
19+Free Software Foundation; either version 2, or (at your option) any
20+later version.
21+
22+In addition to the permissions in the GNU General Public License, the
23+Free Software Foundation gives you unlimited permission to link the
24+compiled version of this file into combinations with other programs,
25+and to distribute those combinations without any restriction coming
26+from the use of this file. (The General Public License restrictions
27+do apply in other respects; for example, they cover modification of
28+the file, and distribution when not linked into a combine
29+executable.)
30+
31+This file is distributed in the hope that it will be useful, but
32+WITHOUT ANY WARRANTY; without even the implied warranty of
33+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34+General Public License for more details.
35+
36+You should have received a copy of the GNU General Public License
37+along with this program; see the file COPYING. If not, write to
38+the Free Software Foundation, 59 Temple Place - Suite 330,
39+Boston, MA 02111-1307, USA. */
40+
41+
42+#include <linux/linkage.h>
43+#include <asm/assembler.h>
44+
45+
46+.macro ARM_DIV_BODY dividend, divisor, result, curbit
47+
48+#if __LINUX_ARM_ARCH__ >= 5
49+
50+ clz \curbit, \divisor
51+ clz \result, \dividend
52+ sub \result, \curbit, \result
53+ mov \curbit, #1
54+ mov \divisor, \divisor, lsl \result
55+ mov \curbit, \curbit, lsl \result
56+ mov \result, #0
57+
58+#else
59+
60+ @ Initially shift the divisor left 3 bits if possible,
61+ @ set curbit accordingly. This allows for curbit to be located
62+ @ at the left end of each 4 bit nibbles in the division loop
63+ @ to save one loop in most cases.
64+ tst \divisor, #0xe0000000
65+ moveq \divisor, \divisor, lsl #3
66+ moveq \curbit, #8
67+ movne \curbit, #1
68+
69+ @ Unless the divisor is very big, shift it up in multiples of
70+ @ four bits, since this is the amount of unwinding in the main
71+ @ division loop. Continue shifting until the divisor is
72+ @ larger than the dividend.
73+1: cmp \divisor, #0x10000000
74+ cmplo \divisor, \dividend
75+ movlo \divisor, \divisor, lsl #4
76+ movlo \curbit, \curbit, lsl #4
77+ blo 1b
78+
79+ @ For very big divisors, we must shift it a bit at a time, or
80+ @ we will be in danger of overflowing.
81+1: cmp \divisor, #0x80000000
82+ cmplo \divisor, \dividend
83+ movlo \divisor, \divisor, lsl #1
84+ movlo \curbit, \curbit, lsl #1
85+ blo 1b
86+
87+ mov \result, #0
88+
89+#endif
90+
91+ @ Division loop
92+1: cmp \dividend, \divisor
93+ subhs \dividend, \dividend, \divisor
94+ orrhs \result, \result, \curbit
95+ cmp \dividend, \divisor, lsr #1
96+ subhs \dividend, \dividend, \divisor, lsr #1
97+ orrhs \result, \result, \curbit, lsr #1
98+ cmp \dividend, \divisor, lsr #2
99+ subhs \dividend, \dividend, \divisor, lsr #2
100+ orrhs \result, \result, \curbit, lsr #2
101+ cmp \dividend, \divisor, lsr #3
102+ subhs \dividend, \dividend, \divisor, lsr #3
103+ orrhs \result, \result, \curbit, lsr #3
104+ cmp \dividend, #0 @ Early termination?
105+ movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
106+ movne \divisor, \divisor, lsr #4
107+ bne 1b
108+
109+.endm
110+
111+
112+.macro ARM_DIV2_ORDER divisor, order
113+
114+#if __LINUX_ARM_ARCH__ >= 5
115+
116+ clz \order, \divisor
117+ rsb \order, \order, #31
118+
119+#else
120+
121+ cmp \divisor, #(1 << 16)
122+ movhs \divisor, \divisor, lsr #16
123+ movhs \order, #16
124+ movlo \order, #0
125+
126+ cmp \divisor, #(1 << 8)
127+ movhs \divisor, \divisor, lsr #8
128+ addhs \order, \order, #8
129+
130+ cmp \divisor, #(1 << 4)
131+ movhs \divisor, \divisor, lsr #4
132+ addhs \order, \order, #4
133+
134+ cmp \divisor, #(1 << 2)
135+ addhi \order, \order, #3
136+ addls \order, \order, \divisor, lsr #1
137+
138+#endif
139+
140+.endm
141+
142+
143+.macro ARM_MOD_BODY dividend, divisor, order, spare
144+
145+#if __LINUX_ARM_ARCH__ >= 5
146+
147+ clz \order, \divisor
148+ clz \spare, \dividend
149+ sub \order, \order, \spare
150+ mov \divisor, \divisor, lsl \order
151+
152+#else
153+
154+ mov \order, #0
155+
156+ @ Unless the divisor is very big, shift it up in multiples of
157+ @ four bits, since this is the amount of unwinding in the main
158+ @ division loop. Continue shifting until the divisor is
159+ @ larger than the dividend.
160+1: cmp \divisor, #0x10000000
161+ cmplo \divisor, \dividend
162+ movlo \divisor, \divisor, lsl #4
163+ addlo \order, \order, #4
164+ blo 1b
165+
166+ @ For very big divisors, we must shift it a bit at a time, or
167+ @ we will be in danger of overflowing.
168+1: cmp \divisor, #0x80000000
169+ cmplo \divisor, \dividend
170+ movlo \divisor, \divisor, lsl #1
171+ addlo \order, \order, #1
172+ blo 1b
173+
174+#endif
175+
176+ @ Perform all needed substractions to keep only the reminder.
177+ @ Do comparisons in batch of 4 first.
178+ subs \order, \order, #3 @ yes, 3 is intended here
179+ blt 2f
180+
181+1: cmp \dividend, \divisor
182+ subhs \dividend, \dividend, \divisor
183+ cmp \dividend, \divisor, lsr #1
184+ subhs \dividend, \dividend, \divisor, lsr #1
185+ cmp \dividend, \divisor, lsr #2
186+ subhs \dividend, \dividend, \divisor, lsr #2
187+ cmp \dividend, \divisor, lsr #3
188+ subhs \dividend, \dividend, \divisor, lsr #3
189+ cmp \dividend, #1
190+ mov \divisor, \divisor, lsr #4
191+ subges \order, \order, #4
192+ bge 1b
193+
194+ tst \order, #3
195+ teqne \dividend, #0
196+ beq 5f
197+
198+ @ Either 1, 2 or 3 comparison/substractions are left.
199+2: cmn \order, #2
200+ blt 4f
201+ beq 3f
202+ cmp \dividend, \divisor
203+ subhs \dividend, \dividend, \divisor
204+ mov \divisor, \divisor, lsr #1
205+3: cmp \dividend, \divisor
206+ subhs \dividend, \dividend, \divisor
207+ mov \divisor, \divisor, lsr #1
208+4: cmp \dividend, \divisor
209+ subhs \dividend, \dividend, \divisor
210+5:
211+.endm
212+
213+
214+ENTRY(__udivsi3)
215+ENTRY(__aeabi_uidiv)
216+
217+ subs r2, r1, #1
218+ moveq pc, lr
219+ bcc Ldiv0
220+ cmp r0, r1
221+ bls 11f
222+ tst r1, r2
223+ beq 12f
224+
225+ ARM_DIV_BODY r0, r1, r2, r3
226+
227+ mov r0, r2
228+ mov pc, lr
229+
230+11: moveq r0, #1
231+ movne r0, #0
232+ mov pc, lr
233+
234+12: ARM_DIV2_ORDER r1, r2
235+
236+ mov r0, r0, lsr r2
237+ mov pc, lr
238+
239+ENDPROC(__udivsi3)
240+ENDPROC(__aeabi_uidiv)
241+
242+ENTRY(__umodsi3)
243+
244+ subs r2, r1, #1 @ compare divisor with 1
245+ bcc Ldiv0
246+ cmpne r0, r1 @ compare dividend with divisor
247+ moveq r0, #0
248+ tsthi r1, r2 @ see if divisor is power of 2
249+ andeq r0, r0, r2
250+ movls pc, lr
251+
252+ ARM_MOD_BODY r0, r1, r2, r3
253+
254+ mov pc, lr
255+
256+ENDPROC(__umodsi3)
257+
258+ENTRY(__divsi3)
259+ENTRY(__aeabi_idiv)
260+
261+ cmp r1, #0
262+ eor ip, r0, r1 @ save the sign of the result.
263+ beq Ldiv0
264+ rsbmi r1, r1, #0 @ loops below use unsigned.
265+ subs r2, r1, #1 @ division by 1 or -1 ?
266+ beq 10f
267+ movs r3, r0
268+ rsbmi r3, r0, #0 @ positive dividend value
269+ cmp r3, r1
270+ bls 11f
271+ tst r1, r2 @ divisor is power of 2 ?
272+ beq 12f
273+
274+ ARM_DIV_BODY r3, r1, r0, r2
275+
276+ cmp ip, #0
277+ rsbmi r0, r0, #0
278+ mov pc, lr
279+
280+10: teq ip, r0 @ same sign ?
281+ rsbmi r0, r0, #0
282+ mov pc, lr
283+
284+11: movlo r0, #0
285+ moveq r0, ip, asr #31
286+ orreq r0, r0, #1
287+ mov pc, lr
288+
289+12: ARM_DIV2_ORDER r1, r2
290+
291+ cmp ip, #0
292+ mov r0, r3, lsr r2
293+ rsbmi r0, r0, #0
294+ mov pc, lr
295+
296+ENDPROC(__divsi3)
297+ENDPROC(__aeabi_idiv)
298+
299+ENTRY(__modsi3)
300+
301+ cmp r1, #0
302+ beq Ldiv0
303+ rsbmi r1, r1, #0 @ loops below use unsigned.
304+ movs ip, r0 @ preserve sign of dividend
305+ rsbmi r0, r0, #0 @ if negative make positive
306+ subs r2, r1, #1 @ compare divisor with 1
307+ cmpne r0, r1 @ compare dividend with divisor
308+ moveq r0, #0
309+ tsthi r1, r2 @ see if divisor is power of 2
310+ andeq r0, r0, r2
311+ bls 10f
312+
313+ ARM_MOD_BODY r0, r1, r2, r3
314+
315+10: cmp ip, #0
316+ rsbmi r0, r0, #0
317+ mov pc, lr
318+
319+ENDPROC(__modsi3)
320+
321+#ifdef CONFIG_AEABI
322+
323+ENTRY(__aeabi_uidivmod)
324+
325+ stmfd sp!, {r0, r1, ip, lr}
326+ bl __aeabi_uidiv
327+ ldmfd sp!, {r1, r2, ip, lr}
328+ mul r3, r0, r2
329+ sub r1, r1, r3
330+ mov pc, lr
331+
332+ENDPROC(__aeabi_uidivmod)
333+
334+ENTRY(__aeabi_idivmod)
335+
336+ stmfd sp!, {r0, r1, ip, lr}
337+ bl __aeabi_idiv
338+ ldmfd sp!, {r1, r2, ip, lr}
339+ mul r3, r0, r2
340+ sub r1, r1, r3
341+ mov pc, lr
342+
343+ENDPROC(__aeabi_idivmod)
344+
345+#endif
346+
347+Ldiv0:
348+
349+ str lr, [sp, #-8]!
350+ bl __div0
351+ mov r0, #0 @ About as wrong as it could be.
352+ ldr pc, [sp], #8
353+
354+
target/linux/omap24xx/patches-2.6.35/200-omap-platform.patch
1Index: linux-2.6.35/arch/arm/plat-omap/bootreason.c
2===================================================================
3--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4@@ -0,0 +1,79 @@
5+/*
6+ * linux/arch/arm/plat-omap/bootreason.c
7+ *
8+ * OMAP Bootreason passing
9+ *
10+ * Copyright (c) 2004 Nokia
11+ *
12+ * Written by David Weinehall <david.weinehall@nokia.com>
13+ *
14+ * This program is free software; you can redistribute it and/or modify it
15+ * under the terms of the GNU General Public License as published by the
16+ * Free Software Foundation; either version 2 of the License, or (at your
17+ * option) any later version.
18+ *
19+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29+ *
30+ * You should have received a copy of the GNU General Public License along
31+ * with this program; if not, write to the Free Software Foundation, Inc.,
32+ * 675 Mass Ave, Cambridge, MA 02139, USA.
33+ */
34+#include <linux/proc_fs.h>
35+#include <linux/errno.h>
36+#include <plat/board.h>
37+
38+static char boot_reason[16];
39+
40+static int omap_bootreason_read_proc(char *page, char **start, off_t off,
41+ int count, int *eof, void *data)
42+{
43+ int len = 0;
44+
45+ len += sprintf(page + len, "%s\n", boot_reason);
46+
47+ *start = page + off;
48+
49+ if (len > off)
50+ len -= off;
51+ else
52+ len = 0;
53+
54+ return len < count ? len : count;
55+}
56+
57+static int __init bootreason_init(void)
58+{
59+ const struct omap_boot_reason_config *cfg;
60+ int reason_valid = 0;
61+
62+ cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
63+ if (cfg != NULL) {
64+ strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
65+ boot_reason[sizeof(cfg->reason_str)] = 0;
66+ reason_valid = 1;
67+ } else {
68+ /* Read the boot reason from the OMAP registers */
69+ }
70+
71+ if (!reason_valid)
72+ return -ENOENT;
73+
74+ printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
75+
76+ if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
77+ omap_bootreason_read_proc, NULL))
78+ return -ENOMEM;
79+
80+ return 0;
81+}
82+
83+late_initcall(bootreason_init);
84Index: linux-2.6.35/arch/arm/plat-omap/common.c
85===================================================================
86--- linux-2.6.35.orig/arch/arm/plat-omap/common.c 2010-08-08 12:56:15.000000000 +0200
87@@ -47,11 +47,81 @@
88 struct omap_board_config_kernel *omap_board_config;
89 int omap_board_config_size;
90
91+unsigned char omap_bootloader_tag[1024];
92+int omap_bootloader_tag_len;
93+
94+/* used by omap-smp.c and board-4430sdp.c */
95+void __iomem *gic_cpu_base_addr;
96+
97+#ifdef CONFIG_OMAP_BOOT_TAG
98+
99+static int __init parse_tag_omap(const struct tag *tag)
100+{
101+ u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
102+
103+ size <<= 2;
104+ if (size > sizeof(omap_bootloader_tag))
105+ return -1;
106+
107+ memcpy(omap_bootloader_tag, tag->u.omap.data, size);
108+ omap_bootloader_tag_len = size;
109+
110+ return 0;
111+}
112+
113+__tagtable(ATAG_BOARD, parse_tag_omap);
114+
115+#endif
116+
117 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
118 {
119     struct omap_board_config_kernel *kinfo = NULL;
120     int i;
121
122+#ifdef CONFIG_OMAP_BOOT_TAG
123+ struct omap_board_config_entry *info = NULL;
124+
125+ if (omap_bootloader_tag_len > 4)
126+ info = (struct omap_board_config_entry *) omap_bootloader_tag;
127+ while (info != NULL) {
128+ u8 *next;
129+
130+ if (info->tag == tag) {
131+ if (skip == 0)
132+ break;
133+ skip--;
134+ }
135+
136+ if ((info->len & 0x03) != 0) {
137+ /* We bail out to avoid an alignment fault */
138+ printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
139+ info->len, info->tag);
140+ return NULL;
141+ }
142+ next = (u8 *) info + sizeof(*info) + info->len;
143+ if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
144+ info = NULL;
145+ else
146+ info = (struct omap_board_config_entry *) next;
147+ }
148+ if (info != NULL) {
149+ /* Check the length as a lame attempt to check for
150+ * binary inconsistency. */
151+ if (len != NO_LENGTH_CHECK) {
152+ /* Word-align len */
153+ if (len & 0x03)
154+ len = (len + 3) & ~0x03;
155+ if (info->len != len) {
156+ printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
157+ tag, len, info->len);
158+ return NULL;
159+ }
160+ }
161+ if (len_out != NULL)
162+ *len_out = info->len;
163+ return info->data;
164+ }
165+#endif
166     /* Try to find the config from the board-specific structures
167      * in the kernel. */
168     for (i = 0; i < omap_board_config_size; i++) {
169Index: linux-2.6.35/arch/arm/plat-omap/component-version.c
170===================================================================
171--- /dev/null 1970-01-01 00:00:00.000000000 +0000
172@@ -0,0 +1,64 @@
173+/*
174+ * linux/arch/arm/plat-omap/component-version.c
175+ *
176+ * Copyright (C) 2005 Nokia Corporation
177+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
178+ *
179+ * This program is free software; you can redistribute it and/or modify
180+ * it under the terms of the GNU General Public License version 2 as
181+ * published by the Free Software Foundation.
182+ */
183+
184+#include <linux/init.h>
185+#include <linux/module.h>
186+#include <linux/err.h>
187+#include <linux/proc_fs.h>
188+#include <plat/board.h>
189+
190+static int component_version_read_proc(char *page, char **start, off_t off,
191+ int count, int *eof, void *data)
192+{
193+ int len, i;
194+ const struct omap_version_config *ver;
195+ char *p;
196+
197+ i = 0;
198+ p = page;
199+ while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
200+ struct omap_version_config, i)) != NULL) {
201+ p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
202+ i++;
203+ }
204+
205+ len = (p - page) - off;
206+ if (len < 0)
207+ len = 0;
208+
209+ *eof = (len <= count) ? 1 : 0;
210+ *start = page + off;
211+
212+ return len;
213+}
214+
215+static int __init component_version_init(void)
216+{
217+ if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
218+ return -ENODEV;
219+ if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
220+ component_version_read_proc, NULL))
221+ return -ENOMEM;
222+
223+ return 0;
224+}
225+
226+static void __exit component_version_exit(void)
227+{
228+ remove_proc_entry("component_version", NULL);
229+}
230+
231+late_initcall(component_version_init);
232+module_exit(component_version_exit);
233+
234+MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
235+MODULE_DESCRIPTION("Component version driver");
236+MODULE_LICENSE("GPL");
237Index: linux-2.6.35/arch/arm/plat-omap/include/mach/blizzard.h
238===================================================================
239--- /dev/null 1970-01-01 00:00:00.000000000 +0000
240@@ -0,0 +1,12 @@
241+#ifndef _BLIZZARD_H
242+#define _BLIZZARD_H
243+
244+struct blizzard_platform_data {
245+ void (*power_up)(struct device *dev);
246+ void (*power_down)(struct device *dev);
247+ unsigned long (*get_clock_rate)(struct device *dev);
248+
249+ unsigned te_connected : 1;
250+};
251+
252+#endif
253Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-ams-delta.h
254===================================================================
255--- /dev/null 1970-01-01 00:00:00.000000000 +0000
256@@ -0,0 +1,76 @@
257+/*
258+ * arch/arm/plat-omap/include/mach/board-ams-delta.h
259+ *
260+ * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
261+ *
262+ * This program is free software; you can redistribute it and/or modify it
263+ * under the terms of the GNU General Public License as published by the
264+ * Free Software Foundation; either version 2 of the License, or (at your
265+ * option) any later version.
266+ *
267+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
268+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
269+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
270+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
271+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
272+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
273+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
274+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
275+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
276+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277+ *
278+ * You should have received a copy of the GNU General Public License along
279+ * with this program; if not, write to the Free Software Foundation, Inc.,
280+ * 675 Mass Ave, Cambridge, MA 02139, USA.
281+ */
282+#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
283+#define __ASM_ARCH_OMAP_AMS_DELTA_H
284+
285+#if defined (CONFIG_MACH_AMS_DELTA)
286+
287+#define AMS_DELTA_LATCH1_PHYS 0x01000000
288+#define AMS_DELTA_LATCH1_VIRT 0xEA000000
289+#define AMS_DELTA_MODEM_PHYS 0x04000000
290+#define AMS_DELTA_MODEM_VIRT 0xEB000000
291+#define AMS_DELTA_LATCH2_PHYS 0x08000000
292+#define AMS_DELTA_LATCH2_VIRT 0xEC000000
293+
294+#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
295+#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
296+#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
297+#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
298+#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
299+#define AMS_DELTA_LATCH1_LED_VOICE 0x20
300+
301+#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
302+#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
303+#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
304+#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
305+#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
306+#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
307+#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
308+#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
309+#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
310+#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
311+#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
312+#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
313+#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
314+#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
315+
316+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
317+#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
318+#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
319+#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
320+#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
321+#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
322+#define AMS_DELTA_GPIO_PIN_CONFIG 11
323+#define AMS_DELTA_GPIO_PIN_NAND_RB 12
324+
325+#ifndef __ASSEMBLY__
326+void ams_delta_latch1_write(u8 mask, u8 value);
327+void ams_delta_latch2_write(u16 mask, u16 value);
328+#endif
329+
330+#endif /* CONFIG_MACH_AMS_DELTA */
331+
332+#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
333Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board.h
334===================================================================
335--- /dev/null 1970-01-01 00:00:00.000000000 +0000
336@@ -0,0 +1,169 @@
337+/*
338+ * arch/arm/plat-omap/include/mach/board.h
339+ *
340+ * Information structures for board-specific data
341+ *
342+ * Copyright (C) 2004 Nokia Corporation
343+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
344+ */
345+
346+#ifndef _OMAP_BOARD_H
347+#define _OMAP_BOARD_H
348+
349+#include <linux/types.h>
350+
351+#include <plat/gpio-switch.h>
352+
353+/*
354+ * OMAP35x EVM revision
355+ * Run time detection of EVM revision is done by reading Ethernet
356+ * PHY ID -
357+ * GEN_1 = 0x01150000
358+ * GEN_2 = 0x92200000
359+ */
360+enum {
361+ OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
362+ OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
363+};
364+
365+/* Different peripheral ids */
366+#define OMAP_TAG_CLOCK 0x4f01
367+#define OMAP_TAG_LCD 0x4f05
368+#define OMAP_TAG_GPIO_SWITCH 0x4f06
369+#define OMAP_TAG_FBMEM 0x4f08
370+#define OMAP_TAG_STI_CONSOLE 0x4f09
371+#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
372+
373+#define OMAP_TAG_BOOT_REASON 0x4f80
374+#define OMAP_TAG_FLASH_PART 0x4f81
375+#define OMAP_TAG_VERSION_STR 0x4f82
376+
377+struct omap_clock_config {
378+ /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
379+ u8 system_clock_type;
380+};
381+
382+struct omap_serial_console_config {
383+ u8 console_uart;
384+ u32 console_speed;
385+};
386+
387+struct omap_sti_console_config {
388+ unsigned enable:1;
389+ u8 channel;
390+};
391+
392+struct omap_camera_sensor_config {
393+ u16 reset_gpio;
394+ int (*power_on)(void * data);
395+ int (*power_off)(void * data);
396+};
397+
398+struct omap_usb_config {
399+ /* Configure drivers according to the connectors on your board:
400+ * - "A" connector (rectagular)
401+ * ... for host/OHCI use, set "register_host".
402+ * - "B" connector (squarish) or "Mini-B"
403+ * ... for device/gadget use, set "register_dev".
404+ * - "Mini-AB" connector (very similar to Mini-B)
405+ * ... for OTG use as device OR host, initialize "otg"
406+ */
407+ unsigned register_host:1;
408+ unsigned register_dev:1;
409+ u8 otg; /* port number, 1-based: usb1 == 2 */
410+
411+ u8 hmc_mode;
412+
413+ /* implicitly true if otg: host supports remote wakeup? */
414+ u8 rwc;
415+
416+ /* signaling pins used to talk to transceiver on usbN:
417+ * 0 == usbN unused
418+ * 2 == usb0-only, using internal transceiver
419+ * 3 == 3 wire bidirectional
420+ * 4 == 4 wire bidirectional
421+ * 6 == 6 wire unidirectional (or TLL)
422+ */
423+ u8 pins[3];
424+};
425+
426+struct omap_lcd_config {
427+ char panel_name[16];
428+ char ctrl_name[16];
429+ s16 nreset_gpio;
430+ u8 data_lines;
431+};
432+
433+struct device;
434+struct fb_info;
435+struct omap_backlight_config {
436+ int default_intensity;
437+ int (*set_power)(struct device *dev, int state);
438+ int (*check_fb)(struct fb_info *fb);
439+};
440+
441+struct omap_fbmem_config {
442+ u32 start;
443+ u32 size;
444+};
445+
446+struct omap_pwm_led_platform_data {
447+ const char *name;
448+ int intensity_timer;
449+ int blink_timer;
450+ void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
451+};
452+
453+struct omap_uart_config {
454+ /* Bit field of UARTs present; bit 0 --> UART1 */
455+ unsigned int enabled_uarts;
456+};
457+
458+
459+struct omap_flash_part_config {
460+ char part_table[0];
461+};
462+
463+struct omap_boot_reason_config {
464+ char reason_str[12];
465+};
466+
467+struct omap_version_config {
468+ char component[12];
469+ char version[12];
470+};
471+
472+struct omap_board_config_entry {
473+ u16 tag;
474+ u16 len;
475+ u8 data[0];
476+};
477+
478+struct omap_board_config_kernel {
479+ u16 tag;
480+ const void *data;
481+};
482+
483+extern const void *__omap_get_config(u16 tag, size_t len, int nr);
484+
485+#define omap_get_config(tag, type) \
486+ ((const type *) __omap_get_config((tag), sizeof(type), 0))
487+#define omap_get_nr_config(tag, type, nr) \
488+ ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
489+
490+extern const void *omap_get_var_config(u16 tag, size_t *len);
491+
492+extern struct omap_board_config_kernel *omap_board_config;
493+extern int omap_board_config_size;
494+
495+
496+/* for TI reference platforms sharing the same debug card */
497+extern int debug_card_init(u32 addr, unsigned gpio);
498+
499+/* OMAP3EVM revision */
500+#if defined(CONFIG_MACH_OMAP3EVM)
501+u8 get_omap3_evm_rev(void);
502+#else
503+#define get_omap3_evm_rev() (-EINVAL)
504+#endif
505+#endif
506Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-sx1.h
507===================================================================
508--- /dev/null 1970-01-01 00:00:00.000000000 +0000
509@@ -0,0 +1,52 @@
510+/*
511+ * Siemens SX1 board definitions
512+ *
513+ * Copyright: Vovan888 at gmail com
514+ *
515+ * This package is free software; you can redistribute it and/or modify
516+ * it under the terms of the GNU General Public License version 2 as
517+ * published by the Free Software Foundation.
518+ *
519+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
520+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
521+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
522+ */
523+
524+#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
525+#define __ASM_ARCH_SX1_I2C_CHIPS_H
526+
527+#define SOFIA_MAX_LIGHT_VAL 0x2B
528+
529+#define SOFIA_I2C_ADDR 0x32
530+/* Sofia reg 3 bits masks */
531+#define SOFIA_POWER1_REG 0x03
532+
533+#define SOFIA_USB_POWER 0x01
534+#define SOFIA_MMC_POWER 0x04
535+#define SOFIA_BLUETOOTH_POWER 0x08
536+#define SOFIA_MMILIGHT_POWER 0x20
537+
538+#define SOFIA_POWER2_REG 0x04
539+#define SOFIA_BACKLIGHT_REG 0x06
540+#define SOFIA_KEYLIGHT_REG 0x07
541+#define SOFIA_DIMMING_REG 0x09
542+
543+
544+/* Function Prototypes for SX1 devices control on I2C bus */
545+
546+int sx1_setbacklight(u8 backlight);
547+int sx1_getbacklight(u8 *backlight);
548+int sx1_setkeylight(u8 keylight);
549+int sx1_getkeylight(u8 *keylight);
550+
551+int sx1_setmmipower(u8 onoff);
552+int sx1_setusbpower(u8 onoff);
553+int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
554+int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
555+
556+/* MMC prototypes */
557+
558+extern void sx1_mmc_init(void);
559+extern void sx1_mmc_slot_cover_handler(void *arg, int state);
560+
561+#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
562Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-voiceblue.h
563===================================================================
564--- /dev/null 1970-01-01 00:00:00.000000000 +0000
565@@ -0,0 +1,19 @@
566+/*
567+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
568+ *
569+ * Hardware definitions for OMAP5910 based VoiceBlue board.
570+ *
571+ * This program is free software; you can redistribute it and/or modify
572+ * it under the terms of the GNU General Public License version 2 as
573+ * published by the Free Software Foundation.
574+ */
575+
576+#ifndef __ASM_ARCH_VOICEBLUE_H
577+#define __ASM_ARCH_VOICEBLUE_H
578+
579+extern void voiceblue_wdt_enable(void);
580+extern void voiceblue_wdt_disable(void);
581+extern void voiceblue_wdt_ping(void);
582+
583+#endif /* __ASM_ARCH_VOICEBLUE_H */
584+
585Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cbus.h
586===================================================================
587--- /dev/null 1970-01-01 00:00:00.000000000 +0000
588@@ -0,0 +1,31 @@
589+/*
590+ * cbus.h - CBUS platform_data definition
591+ *
592+ * Copyright (C) 2004 - 2009 Nokia Corporation
593+ *
594+ * Written by Felipe Balbi <felipe.balbi@nokia.com>
595+ *
596+ * This file is subject to the terms and conditions of the GNU General
597+ * Public License. See the file "COPYING" in the main directory of this
598+ * archive for more details.
599+ *
600+ * This program is distributed in the hope that it will be useful,
601+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
602+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
603+ * GNU General Public License for more details.
604+ *
605+ * You should have received a copy of the GNU General Public License
606+ * along with this program; if not, write to the Free Software
607+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
608+ */
609+
610+#ifndef __PLAT_CBUS_H
611+#define __PLAT_CBUS_H
612+
613+struct cbus_host_platform_data {
614+ int dat_gpio;
615+ int clk_gpio;
616+ int sel_gpio;
617+};
618+
619+#endif /* __PLAT_CBUS_H */
620Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev.h
621===================================================================
622--- /dev/null 1970-01-01 00:00:00.000000000 +0000
623@@ -0,0 +1,13 @@
624+#ifndef __MACH_CLKDEV_H
625+#define __MACH_CLKDEV_H
626+
627+static inline int __clk_get(struct clk *clk)
628+{
629+ return 1;
630+}
631+
632+static inline void __clk_put(struct clk *clk)
633+{
634+}
635+
636+#endif
637Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev_omap.h
638===================================================================
639--- /dev/null 1970-01-01 00:00:00.000000000 +0000
640@@ -0,0 +1,41 @@
641+/*
642+ * clkdev <-> OMAP integration
643+ *
644+ * Russell King <linux@arm.linux.org.uk>
645+ *
646+ */
647+
648+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
649+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
650+
651+#include <asm/clkdev.h>
652+
653+struct omap_clk {
654+ u16 cpu;
655+ struct clk_lookup lk;
656+};
657+
658+#define CLK(dev, con, ck, cp) \
659+ { \
660+ .cpu = cp, \
661+ .lk = { \
662+ .dev_id = dev, \
663+ .con_id = con, \
664+ .clk = ck, \
665+ }, \
666+ }
667+
668+
669+#define CK_310 (1 << 0)
670+#define CK_7XX (1 << 1)
671+#define CK_1510 (1 << 2)
672+#define CK_16XX (1 << 3)
673+#define CK_243X (1 << 4)
674+#define CK_242X (1 << 5)
675+#define CK_343X (1 << 6)
676+#define CK_3430ES1 (1 << 7)
677+#define CK_3430ES2 (1 << 8)
678+#define CK_443X (1 << 9)
679+
680+#endif
681+
682Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clockdomain.h
683===================================================================
684--- /dev/null 1970-01-01 00:00:00.000000000 +0000
685@@ -0,0 +1,111 @@
686+/*
687+ * arch/arm/plat-omap/include/mach/clockdomain.h
688+ *
689+ * OMAP2/3 clockdomain framework functions
690+ *
691+ * Copyright (C) 2008 Texas Instruments, Inc.
692+ * Copyright (C) 2008 Nokia Corporation
693+ *
694+ * Written by Paul Walmsley
695+ *
696+ * This program is free software; you can redistribute it and/or modify
697+ * it under the terms of the GNU General Public License version 2 as
698+ * published by the Free Software Foundation.
699+ */
700+
701+#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
702+#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
703+
704+#include <plat/powerdomain.h>
705+#include <plat/clock.h>
706+#include <plat/cpu.h>
707+
708+/* Clockdomain capability flags */
709+#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
710+#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
711+#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
712+#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
713+
714+#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
715+#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
716+#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
717+
718+/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
719+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
720+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
721+
722+/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
723+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
724+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
725+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
726+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
727+
728+/*
729+ * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
730+ * and sleepdeps added when a powerdomain should stay active in hwsup mode;
731+ * and conversely, removed when the powerdomain should be allowed to go
732+ * inactive in hwsup mode.
733+ */
734+struct clkdm_pwrdm_autodep {
735+
736+ union {
737+ /* Name of the powerdomain to add a wkdep/sleepdep on */
738+ const char *name;
739+
740+ /* Powerdomain pointer (looked up at clkdm_init() time) */
741+ struct powerdomain *ptr;
742+ } pwrdm;
743+
744+ /* OMAP chip types that this clockdomain dep is valid on */
745+ const struct omap_chip_id omap_chip;
746+
747+};
748+
749+struct clockdomain {
750+
751+ /* Clockdomain name */
752+ const char *name;
753+
754+ union {
755+ /* Powerdomain enclosing this clockdomain */
756+ const char *name;
757+
758+ /* Powerdomain pointer assigned at clkdm_register() */
759+ struct powerdomain *ptr;
760+ } pwrdm;
761+
762+ /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
763+ const u16 clktrctrl_mask;
764+
765+ /* Clockdomain capability flags */
766+ const u8 flags;
767+
768+ /* OMAP chip types that this clockdomain is valid on */
769+ const struct omap_chip_id omap_chip;
770+
771+ /* Usecount tracking */
772+ atomic_t usecount;
773+
774+ struct list_head node;
775+
776+};
777+
778+void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
779+int clkdm_register(struct clockdomain *clkdm);
780+int clkdm_unregister(struct clockdomain *clkdm);
781+struct clockdomain *clkdm_lookup(const char *name);
782+
783+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
784+ void *user);
785+struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
786+
787+void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
788+void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
789+
790+int omap2_clkdm_wakeup(struct clockdomain *clkdm);
791+int omap2_clkdm_sleep(struct clockdomain *clkdm);
792+
793+int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
794+int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
795+
796+#endif
797Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clock.h
798===================================================================
799--- /dev/null 1970-01-01 00:00:00.000000000 +0000
800@@ -0,0 +1,168 @@
801+/*
802+ * arch/arm/plat-omap/include/mach/clock.h
803+ *
804+ * Copyright (C) 2004 - 2005 Nokia corporation
805+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
806+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
807+ *
808+ * This program is free software; you can redistribute it and/or modify
809+ * it under the terms of the GNU General Public License version 2 as
810+ * published by the Free Software Foundation.
811+ */
812+
813+#ifndef __ARCH_ARM_OMAP_CLOCK_H
814+#define __ARCH_ARM_OMAP_CLOCK_H
815+
816+#include <linux/list.h>
817+
818+struct module;
819+struct clk;
820+struct clockdomain;
821+
822+struct clkops {
823+ int (*enable)(struct clk *);
824+ void (*disable)(struct clk *);
825+ void (*find_idlest)(struct clk *, void __iomem **, u8 *);
826+ void (*find_companion)(struct clk *, void __iomem **, u8 *);
827+};
828+
829+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
830+ defined(CONFIG_ARCH_OMAP4)
831+
832+struct clksel_rate {
833+ u32 val;
834+ u8 div;
835+ u8 flags;
836+};
837+
838+struct clksel {
839+ struct clk *parent;
840+ const struct clksel_rate *rates;
841+};
842+
843+struct dpll_data {
844+ void __iomem *mult_div1_reg;
845+ u32 mult_mask;
846+ u32 div1_mask;
847+ struct clk *clk_bypass;
848+ struct clk *clk_ref;
849+ void __iomem *control_reg;
850+ u32 enable_mask;
851+ unsigned int rate_tolerance;
852+ unsigned long last_rounded_rate;
853+ u16 last_rounded_m;
854+ u8 last_rounded_n;
855+ u8 min_divider;
856+ u8 max_divider;
857+ u32 max_tolerance;
858+ u16 max_multiplier;
859+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
860+ u8 modes;
861+ void __iomem *autoidle_reg;
862+ void __iomem *idlest_reg;
863+ u32 autoidle_mask;
864+ u32 freqsel_mask;
865+ u32 idlest_mask;
866+ u8 auto_recal_bit;
867+ u8 recal_en_bit;
868+ u8 recal_st_bit;
869+# endif
870+};
871+
872+#endif
873+
874+struct clk {
875+ struct list_head node;
876+ const struct clkops *ops;
877+ const char *name;
878+ int id;
879+ struct clk *parent;
880+ struct list_head children;
881+ struct list_head sibling; /* node for children */
882+ unsigned long rate;
883+ __u32 flags;
884+ void __iomem *enable_reg;
885+ unsigned long (*recalc)(struct clk *);
886+ int (*set_rate)(struct clk *, unsigned long);
887+ long (*round_rate)(struct clk *, unsigned long);
888+ void (*init)(struct clk *);
889+ __u8 enable_bit;
890+ __s8 usecount;
891+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
892+ defined(CONFIG_ARCH_OMAP4)
893+ u8 fixed_div;
894+ void __iomem *clksel_reg;
895+ u32 clksel_mask;
896+ const struct clksel *clksel;
897+ struct dpll_data *dpll_data;
898+ const char *clkdm_name;
899+ struct clockdomain *clkdm;
900+#else
901+ __u8 rate_offset;
902+ __u8 src_offset;
903+#endif
904+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
905+ struct dentry *dent; /* For visible tree hierarchy */
906+#endif
907+};
908+
909+struct cpufreq_frequency_table;
910+
911+struct clk_functions {
912+ int (*clk_enable)(struct clk *clk);
913+ void (*clk_disable)(struct clk *clk);
914+ long (*clk_round_rate)(struct clk *clk, unsigned long rate);
915+ int (*clk_set_rate)(struct clk *clk, unsigned long rate);
916+ int (*clk_set_parent)(struct clk *clk, struct clk *parent);
917+ void (*clk_allow_idle)(struct clk *clk);
918+ void (*clk_deny_idle)(struct clk *clk);
919+ void (*clk_disable_unused)(struct clk *clk);
920+#ifdef CONFIG_CPU_FREQ
921+ void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
922+#endif
923+};
924+
925+extern unsigned int mpurate;
926+
927+extern int clk_init(struct clk_functions *custom_clocks);
928+extern void clk_preinit(struct clk *clk);
929+extern int clk_register(struct clk *clk);
930+extern void clk_reparent(struct clk *child, struct clk *parent);
931+extern void clk_unregister(struct clk *clk);
932+extern void propagate_rate(struct clk *clk);
933+extern void recalculate_root_clocks(void);
934+extern unsigned long followparent_recalc(struct clk *clk);
935+extern void clk_enable_init_clocks(void);
936+#ifdef CONFIG_CPU_FREQ
937+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
938+#endif
939+
940+extern const struct clkops clkops_null;
941+
942+/* Clock flags */
943+/* bit 0 is free */
944+#define RATE_FIXED (1 << 1) /* Fixed clock rate */
945+/* bits 2-4 are free */
946+#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
947+#define CLOCK_IDLE_CONTROL (1 << 7)
948+#define CLOCK_NO_IDLE_PARENT (1 << 8)
949+#define DELAYED_APP (1 << 9) /* Delay application of clock */
950+#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
951+#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
952+#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
953+#define CLOCK_IN_OMAP4430 (1 << 13)
954+#define ALWAYS_ENABLED (1 << 14)
955+/* bits 13-31 are currently free */
956+
957+/* Clksel_rate flags */
958+#define DEFAULT_RATE (1 << 0)
959+#define RATE_IN_242X (1 << 1)
960+#define RATE_IN_243X (1 << 2)
961+#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
962+#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
963+#define RATE_IN_4430 (1 << 5)
964+
965+#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
966+
967+
968+#endif
969Index: linux-2.6.35/arch/arm/plat-omap/include/mach/common.h
970===================================================================
971--- /dev/null 1970-01-01 00:00:00.000000000 +0000
972@@ -0,0 +1,83 @@
973+/*
974+ * arch/arm/plat-omap/include/mach/common.h
975+ *
976+ * Header for code common to all OMAP machines.
977+ *
978+ * This program is free software; you can redistribute it and/or modify it
979+ * under the terms of the GNU General Public License as published by the
980+ * Free Software Foundation; either version 2 of the License, or (at your
981+ * option) any later version.
982+ *
983+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
984+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
985+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
986+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
987+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
988+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
989+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
990+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
991+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
992+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
993+ *
994+ * You should have received a copy of the GNU General Public License along
995+ * with this program; if not, write to the Free Software Foundation, Inc.,
996+ * 675 Mass Ave, Cambridge, MA 02139, USA.
997+ */
998+
999+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1000+#define __ARCH_ARM_MACH_OMAP_COMMON_H
1001+
1002+#include <plat/i2c.h>
1003+
1004+struct sys_timer;
1005+
1006+/* used by omap-smp.c and board-4430sdp.c */
1007+extern void __iomem *gic_cpu_base_addr;
1008+
1009+extern void omap_map_common_io(void);
1010+extern struct sys_timer omap_timer;
1011+
1012+/* IO bases for various OMAP processors */
1013+struct omap_globals {
1014+ u32 class; /* OMAP class to detect */
1015+ void __iomem *tap; /* Control module ID code */
1016+ void __iomem *sdrc; /* SDRAM Controller */
1017+ void __iomem *sms; /* SDRAM Memory Scheduler */
1018+ void __iomem *ctrl; /* System Control Module */
1019+ void __iomem *prm; /* Power and Reset Management */
1020+ void __iomem *cm; /* Clock Management */
1021+ void __iomem *cm2;
1022+};
1023+
1024+void omap2_set_globals_242x(void);
1025+void omap2_set_globals_243x(void);
1026+void omap2_set_globals_343x(void);
1027+void omap2_set_globals_443x(void);
1028+
1029+/* These get called from omap2_set_globals_xxxx(), do not call these */
1030+void omap2_set_globals_tap(struct omap_globals *);
1031+void omap2_set_globals_sdrc(struct omap_globals *);
1032+void omap2_set_globals_control(struct omap_globals *);
1033+void omap2_set_globals_prcm(struct omap_globals *);
1034+
1035+/**
1036+ * omap_test_timeout - busy-loop, testing a condition
1037+ * @cond: condition to test until it evaluates to true
1038+ * @timeout: maximum number of microseconds in the timeout
1039+ * @index: loop index (integer)
1040+ *
1041+ * Loop waiting for @cond to become true or until at least @timeout
1042+ * microseconds have passed. To use, define some integer @index in the
1043+ * calling code. After running, if @index == @timeout, then the loop has
1044+ * timed out.
1045+ */
1046+#define omap_test_timeout(cond, timeout, index) \
1047+({ \
1048+ for (index = 0; index < timeout; index++) { \
1049+ if (cond) \
1050+ break; \
1051+ udelay(1); \
1052+ } \
1053+})
1054+
1055+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1056Index: linux-2.6.35/arch/arm/plat-omap/include/mach/control.h
1057===================================================================
1058--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1059@@ -0,0 +1,325 @@
1060+/*
1061+ * arch/arm/plat-omap/include/mach/control.h
1062+ *
1063+ * OMAP2/3/4 System Control Module definitions
1064+ *
1065+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
1066+ * Copyright (C) 2007-2008 Nokia Corporation
1067+ *
1068+ * Written by Paul Walmsley
1069+ *
1070+ * This program is free software; you can redistribute it and/or modify
1071+ * it under the terms of the GNU General Public License as published by
1072+ * the Free Software Foundation.
1073+ */
1074+
1075+#ifndef __ASM_ARCH_CONTROL_H
1076+#define __ASM_ARCH_CONTROL_H
1077+
1078+#include <mach/io.h>
1079+
1080+#ifndef __ASSEMBLY__
1081+#define OMAP242X_CTRL_REGADDR(reg) \
1082+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1083+#define OMAP243X_CTRL_REGADDR(reg) \
1084+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1085+#define OMAP343X_CTRL_REGADDR(reg) \
1086+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1087+#else
1088+#define OMAP242X_CTRL_REGADDR(reg) \
1089+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1090+#define OMAP243X_CTRL_REGADDR(reg) \
1091+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1092+#define OMAP343X_CTRL_REGADDR(reg) \
1093+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1094+#endif /* __ASSEMBLY__ */
1095+
1096+/*
1097+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1098+ * OMAP24XX and OMAP34XX.
1099+ */
1100+
1101+/* Control submodule offsets */
1102+
1103+#define OMAP2_CONTROL_INTERFACE 0x000
1104+#define OMAP2_CONTROL_PADCONFS 0x030
1105+#define OMAP2_CONTROL_GENERAL 0x270
1106+#define OMAP343X_CONTROL_MEM_WKUP 0x600
1107+#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1108+#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1109+
1110+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1111+
1112+#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1113+
1114+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1115+#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1116+#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1117+#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1118+#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1119+#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1120+#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1121+#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1122+#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1123+#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1124+#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1125+#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1126+#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1127+
1128+/* 242x-only CONTROL_GENERAL register offsets */
1129+#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1130+#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1131+
1132+/* 243x-only CONTROL_GENERAL register offsets */
1133+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1134+#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1135+#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1136+#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1137+#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1138+#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1139+#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1140+
1141+/* 24xx-only CONTROL_GENERAL register offsets */
1142+#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1143+#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1144+#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1145+#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1146+#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1147+#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1148+#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1149+#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1150+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1151+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1152+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1153+#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1154+#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1155+#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1156+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1157+#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1158+#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1159+#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1160+#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1161+#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1162+#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1163+#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1164+#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1165+#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1166+#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1167+#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1168+#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1169+#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1170+#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1171+#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1172+#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1173+
1174+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1175+
1176+/* 34xx-only CONTROL_GENERAL register offsets */
1177+#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1178+#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1179+#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1180+#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1181+#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1182+#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1183+#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1184+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1185+#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1186+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1187+#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1188+#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1189+#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1190+#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1191+#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1192+#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1193+#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1194+#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1195+#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1196+#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1197+#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1198+#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1199+#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1200+#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1201+#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1202+#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1203+#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1204+#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1205+#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1206+#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1207+#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1208+#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1209+ + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1210+#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1211+#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1212+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1213+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1214+#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1215+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1216+#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1217+#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1218+#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1219+#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1220+#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1221+
1222+
1223+/* 34xx PADCONF register offsets */
1224+#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1225+ (i)*2)
1226+#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1227+#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1228+#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1229+#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1230+#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1231+#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1232+#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1233+#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1234+#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1235+#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1236+#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1237+#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1238+#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1239+#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1240+#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1241+#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1242+#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1243+#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1244+
1245+/* 34xx GENERAL_WKUP regist offsets */
1246+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1247+ 0x008 + (i))
1248+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1249+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1250+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1251+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1252+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1253+
1254+/* 34xx D2D idle-related pins, handled by PM core */
1255+#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1256+#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1257+
1258+/*
1259+ * REVISIT: This list of registers is not comprehensive - there are more
1260+ * that should be added.
1261+ */
1262+
1263+/*
1264+ * Control module register bit defines - these should eventually go into
1265+ * their own regbits file. Some of these will be complicated, depending
1266+ * on the device type (general-purpose, emulator, test, secure, bad, other)
1267+ * and the security mode (secure, non-secure, don't care)
1268+ */
1269+/* CONTROL_DEVCONF0 bits */
1270+#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1271+#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1272+#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1273+#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1274+
1275+/* CONTROL_DEVCONF1 bits */
1276+#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1277+#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1278+#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1279+#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1280+#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1281+
1282+/* CONTROL_STATUS bits */
1283+#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1284+#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1285+#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1286+#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1287+#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1288+#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1289+#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1290+
1291+/* CONTROL_PBIAS_LITE bits */
1292+#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1293+#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1294+#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1295+#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1296+#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1297+#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1298+#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1299+#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1300+#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1301+#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1302+
1303+/* CONTROL_PROG_IO1 bits */
1304+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1305+
1306+/* CONTROL_IVA2_BOOTMOD bits */
1307+#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1308+#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1309+#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1310+
1311+/* CONTROL_PADCONF_X bits */
1312+#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1313+#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1314+
1315+#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1316+#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1317+#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1318+
1319+/*
1320+ * CONTROL OMAP STATUS register to identify OMAP3 features
1321+ */
1322+#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1323+
1324+#define OMAP3_SGX_SHIFT 13
1325+#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1326+#define FEAT_SGX_FULL 0
1327+#define FEAT_SGX_HALF 1
1328+#define FEAT_SGX_NONE 2
1329+
1330+#define OMAP3_IVA_SHIFT 12
1331+#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1332+#define FEAT_IVA 0
1333+#define FEAT_IVA_NONE 1
1334+
1335+#define OMAP3_L2CACHE_SHIFT 10
1336+#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1337+#define FEAT_L2CACHE_NONE 0
1338+#define FEAT_L2CACHE_64KB 1
1339+#define FEAT_L2CACHE_128KB 2
1340+#define FEAT_L2CACHE_256KB 3
1341+
1342+#define OMAP3_ISP_SHIFT 5
1343+#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1344+#define FEAT_ISP 0
1345+#define FEAT_ISP_NONE 1
1346+
1347+#define OMAP3_NEON_SHIFT 4
1348+#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1349+#define FEAT_NEON 0
1350+#define FEAT_NEON_NONE 1
1351+
1352+
1353+#ifndef __ASSEMBLY__
1354+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1355+ defined(CONFIG_ARCH_OMAP4)
1356+extern void __iomem *omap_ctrl_base_get(void);
1357+extern u8 omap_ctrl_readb(u16 offset);
1358+extern u16 omap_ctrl_readw(u16 offset);
1359+extern u32 omap_ctrl_readl(u16 offset);
1360+extern void omap_ctrl_writeb(u8 val, u16 offset);
1361+extern void omap_ctrl_writew(u16 val, u16 offset);
1362+extern void omap_ctrl_writel(u32 val, u16 offset);
1363+
1364+extern void omap3_save_scratchpad_contents(void);
1365+extern void omap3_clear_scratchpad_contents(void);
1366+extern u32 *get_restore_pointer(void);
1367+extern u32 *get_es3_restore_pointer(void);
1368+extern u32 omap3_arm_context[128];
1369+extern void omap3_control_save_context(void);
1370+extern void omap3_control_restore_context(void);
1371+
1372+#else
1373+#define omap_ctrl_base_get() 0
1374+#define omap_ctrl_readb(x) 0
1375+#define omap_ctrl_readw(x) 0
1376+#define omap_ctrl_readl(x) 0
1377+#define omap_ctrl_writeb(x, y) WARN_ON(1)
1378+#define omap_ctrl_writew(x, y) WARN_ON(1)
1379+#define omap_ctrl_writel(x, y) WARN_ON(1)
1380+#endif
1381+#endif /* __ASSEMBLY__ */
1382+
1383+#endif /* __ASM_ARCH_CONTROL_H */
1384+
1385Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cpu.h
1386===================================================================
1387--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1388@@ -0,0 +1,516 @@
1389+/*
1390+ * arch/arm/plat-omap/include/mach/cpu.h
1391+ *
1392+ * OMAP cpu type detection
1393+ *
1394+ * Copyright (C) 2004, 2008 Nokia Corporation
1395+ *
1396+ * Copyright (C) 2009 Texas Instruments.
1397+ *
1398+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
1399+ *
1400+ * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1401+ *
1402+ * This program is free software; you can redistribute it and/or modify
1403+ * it under the terms of the GNU General Public License as published by
1404+ * the Free Software Foundation; either version 2 of the License, or
1405+ * (at your option) any later version.
1406+ *
1407+ * This program is distributed in the hope that it will be useful,
1408+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1409+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1410+ * GNU General Public License for more details.
1411+ *
1412+ * You should have received a copy of the GNU General Public License
1413+ * along with this program; if not, write to the Free Software
1414+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1415+ *
1416+ */
1417+
1418+#ifndef __ASM_ARCH_OMAP_CPU_H
1419+#define __ASM_ARCH_OMAP_CPU_H
1420+
1421+#include <linux/bitops.h>
1422+
1423+/*
1424+ * Omap device type i.e. EMU/HS/TST/GP/BAD
1425+ */
1426+#define OMAP2_DEVICE_TYPE_TEST 0
1427+#define OMAP2_DEVICE_TYPE_EMU 1
1428+#define OMAP2_DEVICE_TYPE_SEC 2
1429+#define OMAP2_DEVICE_TYPE_GP 3
1430+#define OMAP2_DEVICE_TYPE_BAD 4
1431+
1432+int omap_type(void);
1433+
1434+struct omap_chip_id {
1435+ u8 oc;
1436+ u8 type;
1437+};
1438+
1439+#define OMAP_CHIP_INIT(x) { .oc = x }
1440+
1441+/*
1442+ * omap_rev bits:
1443+ * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1444+ * CPU revision (See _REV_ defined in cpu.h) [15:08]
1445+ * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1446+ */
1447+unsigned int omap_rev(void);
1448+
1449+/*
1450+ * Define CPU revision bits
1451+ *
1452+ * Verbose meaning of the revision bits may be different for a silicon
1453+ * family. This difference can be handled separately.
1454+ */
1455+#define OMAP_REVBITS_00 0x00
1456+#define OMAP_REVBITS_10 0x10
1457+#define OMAP_REVBITS_20 0x20
1458+#define OMAP_REVBITS_30 0x30
1459+#define OMAP_REVBITS_40 0x40
1460+
1461+/*
1462+ * Get the CPU revision for OMAP devices
1463+ */
1464+#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1465+
1466+/*
1467+ * Test if multicore OMAP support is needed
1468+ */
1469+#undef MULTI_OMAP1
1470+#undef MULTI_OMAP2
1471+#undef OMAP_NAME
1472+
1473+#ifdef CONFIG_ARCH_OMAP730
1474+# ifdef OMAP_NAME
1475+# undef MULTI_OMAP1
1476+# define MULTI_OMAP1
1477+# else
1478+# define OMAP_NAME omap730
1479+# endif
1480+#endif
1481+#ifdef CONFIG_ARCH_OMAP850
1482+# ifdef OMAP_NAME
1483+# undef MULTI_OMAP1
1484+# define MULTI_OMAP1
1485+# else
1486+# define OMAP_NAME omap850
1487+# endif
1488+#endif
1489+#ifdef CONFIG_ARCH_OMAP15XX
1490+# ifdef OMAP_NAME
1491+# undef MULTI_OMAP1
1492+# define MULTI_OMAP1
1493+# else
1494+# define OMAP_NAME omap1510
1495+# endif
1496+#endif
1497+#ifdef CONFIG_ARCH_OMAP16XX
1498+# ifdef OMAP_NAME
1499+# undef MULTI_OMAP1
1500+# define MULTI_OMAP1
1501+# else
1502+# define OMAP_NAME omap16xx
1503+# endif
1504+#endif
1505+#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1506+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1507+# error "OMAP1 and OMAP2 can't be selected at the same time"
1508+# endif
1509+#endif
1510+#ifdef CONFIG_ARCH_OMAP2420
1511+# ifdef OMAP_NAME
1512+# undef MULTI_OMAP2
1513+# define MULTI_OMAP2
1514+# else
1515+# define OMAP_NAME omap2420
1516+# endif
1517+#endif
1518+#ifdef CONFIG_ARCH_OMAP2430
1519+# ifdef OMAP_NAME
1520+# undef MULTI_OMAP2
1521+# define MULTI_OMAP2
1522+# else
1523+# define OMAP_NAME omap2430
1524+# endif
1525+#endif
1526+#ifdef CONFIG_ARCH_OMAP3430
1527+# ifdef OMAP_NAME
1528+# undef MULTI_OMAP2
1529+# define MULTI_OMAP2
1530+# else
1531+# define OMAP_NAME omap3430
1532+# endif
1533+#endif
1534+
1535+/*
1536+ * Macros to group OMAP into cpu classes.
1537+ * These can be used in most places.
1538+ * cpu_is_omap7xx(): True for OMAP730, OMAP850
1539+ * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1540+ * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1541+ * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1542+ * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1543+ * cpu_is_omap243x(): True for OMAP2430
1544+ * cpu_is_omap343x(): True for OMAP3430
1545+ */
1546+#define GET_OMAP_CLASS (omap_rev() & 0xff)
1547+
1548+#define IS_OMAP_CLASS(class, id) \
1549+static inline int is_omap ##class (void) \
1550+{ \
1551+ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1552+}
1553+
1554+#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1555+
1556+#define IS_OMAP_SUBCLASS(subclass, id) \
1557+static inline int is_omap ##subclass (void) \
1558+{ \
1559+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1560+}
1561+
1562+IS_OMAP_CLASS(7xx, 0x07)
1563+IS_OMAP_CLASS(15xx, 0x15)
1564+IS_OMAP_CLASS(16xx, 0x16)
1565+IS_OMAP_CLASS(24xx, 0x24)
1566+IS_OMAP_CLASS(34xx, 0x34)
1567+IS_OMAP_CLASS(44xx, 0x44)
1568+
1569+IS_OMAP_SUBCLASS(242x, 0x242)
1570+IS_OMAP_SUBCLASS(243x, 0x243)
1571+IS_OMAP_SUBCLASS(343x, 0x343)
1572+IS_OMAP_SUBCLASS(363x, 0x363)
1573+IS_OMAP_SUBCLASS(443x, 0x443)
1574+
1575+#define cpu_is_omap7xx() 0
1576+#define cpu_is_omap15xx() 0
1577+#define cpu_is_omap16xx() 0
1578+#define cpu_is_omap24xx() 0
1579+#define cpu_is_omap242x() 0
1580+#define cpu_is_omap243x() 0
1581+#define cpu_is_omap34xx() 0
1582+#define cpu_is_omap343x() 0
1583+#define cpu_is_omap44xx() 0
1584+#define cpu_is_omap443x() 0
1585+
1586+#if defined(MULTI_OMAP1)
1587+# if defined(CONFIG_ARCH_OMAP730)
1588+# undef cpu_is_omap7xx
1589+# define cpu_is_omap7xx() is_omap7xx()
1590+# endif
1591+# if defined(CONFIG_ARCH_OMAP850)
1592+# undef cpu_is_omap7xx
1593+# define cpu_is_omap7xx() is_omap7xx()
1594+# endif
1595+# if defined(CONFIG_ARCH_OMAP15XX)
1596+# undef cpu_is_omap15xx
1597+# define cpu_is_omap15xx() is_omap15xx()
1598+# endif
1599+# if defined(CONFIG_ARCH_OMAP16XX)
1600+# undef cpu_is_omap16xx
1601+# define cpu_is_omap16xx() is_omap16xx()
1602+# endif
1603+#else
1604+# if defined(CONFIG_ARCH_OMAP730)
1605+# undef cpu_is_omap7xx
1606+# define cpu_is_omap7xx() 1
1607+# endif
1608+# if defined(CONFIG_ARCH_OMAP850)
1609+# undef cpu_is_omap7xx
1610+# define cpu_is_omap7xx() 1
1611+# endif
1612+# if defined(CONFIG_ARCH_OMAP15XX)
1613+# undef cpu_is_omap15xx
1614+# define cpu_is_omap15xx() 1
1615+# endif
1616+# if defined(CONFIG_ARCH_OMAP16XX)
1617+# undef cpu_is_omap16xx
1618+# define cpu_is_omap16xx() 1
1619+# endif
1620+#endif
1621+
1622+#if defined(MULTI_OMAP2)
1623+# if defined(CONFIG_ARCH_OMAP24XX)
1624+# undef cpu_is_omap24xx
1625+# undef cpu_is_omap242x
1626+# undef cpu_is_omap243x
1627+# define cpu_is_omap24xx() is_omap24xx()
1628+# define cpu_is_omap242x() is_omap242x()
1629+# define cpu_is_omap243x() is_omap243x()
1630+# endif
1631+# if defined(CONFIG_ARCH_OMAP34XX)
1632+# undef cpu_is_omap34xx
1633+# undef cpu_is_omap343x
1634+# define cpu_is_omap34xx() is_omap34xx()
1635+# define cpu_is_omap343x() is_omap343x()
1636+# endif
1637+#else
1638+# if defined(CONFIG_ARCH_OMAP24XX)
1639+# undef cpu_is_omap24xx
1640+# define cpu_is_omap24xx() 1
1641+# endif
1642+# if defined(CONFIG_ARCH_OMAP2420)
1643+# undef cpu_is_omap242x
1644+# define cpu_is_omap242x() 1
1645+# endif
1646+# if defined(CONFIG_ARCH_OMAP2430)
1647+# undef cpu_is_omap243x
1648+# define cpu_is_omap243x() 1
1649+# endif
1650+# if defined(CONFIG_ARCH_OMAP34XX)
1651+# undef cpu_is_omap34xx
1652+# define cpu_is_omap34xx() 1
1653+# endif
1654+# if defined(CONFIG_ARCH_OMAP3430)
1655+# undef cpu_is_omap343x
1656+# define cpu_is_omap343x() 1
1657+# endif
1658+#endif
1659+
1660+/*
1661+ * Macros to detect individual cpu types.
1662+ * These are only rarely needed.
1663+ * cpu_is_omap330(): True for OMAP330
1664+ * cpu_is_omap730(): True for OMAP730
1665+ * cpu_is_omap850(): True for OMAP850
1666+ * cpu_is_omap1510(): True for OMAP1510
1667+ * cpu_is_omap1610(): True for OMAP1610
1668+ * cpu_is_omap1611(): True for OMAP1611
1669+ * cpu_is_omap5912(): True for OMAP5912
1670+ * cpu_is_omap1621(): True for OMAP1621
1671+ * cpu_is_omap1710(): True for OMAP1710
1672+ * cpu_is_omap2420(): True for OMAP2420
1673+ * cpu_is_omap2422(): True for OMAP2422
1674+ * cpu_is_omap2423(): True for OMAP2423
1675+ * cpu_is_omap2430(): True for OMAP2430
1676+ * cpu_is_omap3430(): True for OMAP3430
1677+ * cpu_is_omap3505(): True for OMAP3505
1678+ * cpu_is_omap3517(): True for OMAP3517
1679+ */
1680+#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1681+
1682+#define IS_OMAP_TYPE(type, id) \
1683+static inline int is_omap ##type (void) \
1684+{ \
1685+ return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1686+}
1687+
1688+IS_OMAP_TYPE(310, 0x0310)
1689+IS_OMAP_TYPE(730, 0x0730)
1690+IS_OMAP_TYPE(850, 0x0850)
1691+IS_OMAP_TYPE(1510, 0x1510)
1692+IS_OMAP_TYPE(1610, 0x1610)
1693+IS_OMAP_TYPE(1611, 0x1611)
1694+IS_OMAP_TYPE(5912, 0x1611)
1695+IS_OMAP_TYPE(1621, 0x1621)
1696+IS_OMAP_TYPE(1710, 0x1710)
1697+IS_OMAP_TYPE(2420, 0x2420)
1698+IS_OMAP_TYPE(2422, 0x2422)
1699+IS_OMAP_TYPE(2423, 0x2423)
1700+IS_OMAP_TYPE(2430, 0x2430)
1701+IS_OMAP_TYPE(3430, 0x3430)
1702+IS_OMAP_TYPE(3505, 0x3505)
1703+IS_OMAP_TYPE(3517, 0x3517)
1704+
1705+#define cpu_is_omap310() 0
1706+#define cpu_is_omap730() 0
1707+#define cpu_is_omap850() 0
1708+#define cpu_is_omap1510() 0
1709+#define cpu_is_omap1610() 0
1710+#define cpu_is_omap5912() 0
1711+#define cpu_is_omap1611() 0
1712+#define cpu_is_omap1621() 0
1713+#define cpu_is_omap1710() 0
1714+#define cpu_is_omap2420() 0
1715+#define cpu_is_omap2422() 0
1716+#define cpu_is_omap2423() 0
1717+#define cpu_is_omap2430() 0
1718+#define cpu_is_omap3503() 0
1719+#define cpu_is_omap3515() 0
1720+#define cpu_is_omap3525() 0
1721+#define cpu_is_omap3530() 0
1722+#define cpu_is_omap3505() 0
1723+#define cpu_is_omap3517() 0
1724+#define cpu_is_omap3430() 0
1725+#define cpu_is_omap3630() 0
1726+
1727+/*
1728+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1729+ * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1730+ */
1731+
1732+#if defined(CONFIG_ARCH_OMAP730)
1733+# undef cpu_is_omap730
1734+# define cpu_is_omap730() is_omap730()
1735+#endif
1736+
1737+#if defined(CONFIG_ARCH_OMAP850)
1738+# undef cpu_is_omap850
1739+# define cpu_is_omap850() is_omap850()
1740+#endif
1741+
1742+#if defined(CONFIG_ARCH_OMAP15XX)
1743+# undef cpu_is_omap310
1744+# undef cpu_is_omap1510
1745+# define cpu_is_omap310() is_omap310()
1746+# define cpu_is_omap1510() is_omap1510()
1747+#endif
1748+
1749+#if defined(CONFIG_ARCH_OMAP16XX)
1750+# undef cpu_is_omap1610
1751+# undef cpu_is_omap1611
1752+# undef cpu_is_omap5912
1753+# undef cpu_is_omap1621
1754+# undef cpu_is_omap1710
1755+# define cpu_is_omap1610() is_omap1610()
1756+# define cpu_is_omap1611() is_omap1611()
1757+# define cpu_is_omap5912() is_omap5912()
1758+# define cpu_is_omap1621() is_omap1621()
1759+# define cpu_is_omap1710() is_omap1710()
1760+#endif
1761+
1762+#if defined(CONFIG_ARCH_OMAP24XX)
1763+# undef cpu_is_omap2420
1764+# undef cpu_is_omap2422
1765+# undef cpu_is_omap2423
1766+# undef cpu_is_omap2430
1767+# define cpu_is_omap2420() is_omap2420()
1768+# define cpu_is_omap2422() is_omap2422()
1769+# define cpu_is_omap2423() is_omap2423()
1770+# define cpu_is_omap2430() is_omap2430()
1771+#endif
1772+
1773+#if defined(CONFIG_ARCH_OMAP34XX)
1774+# undef cpu_is_omap3430
1775+# undef cpu_is_omap3503
1776+# undef cpu_is_omap3515
1777+# undef cpu_is_omap3525
1778+# undef cpu_is_omap3530
1779+# undef cpu_is_omap3505
1780+# undef cpu_is_omap3517
1781+# define cpu_is_omap3430() is_omap3430()
1782+# define cpu_is_omap3503() (cpu_is_omap3430() && \
1783+ (!omap3_has_iva()) && \
1784+ (!omap3_has_sgx()))
1785+# define cpu_is_omap3515() (cpu_is_omap3430() && \
1786+ (!omap3_has_iva()) && \
1787+ (omap3_has_sgx()))
1788+# define cpu_is_omap3525() (cpu_is_omap3430() && \
1789+ (!omap3_has_sgx()) && \
1790+ (omap3_has_iva()))
1791+# define cpu_is_omap3530() (cpu_is_omap3430())
1792+# define cpu_is_omap3505() is_omap3505()
1793+# define cpu_is_omap3517() is_omap3517()
1794+# undef cpu_is_omap3630
1795+# define cpu_is_omap3630() is_omap363x()
1796+#endif
1797+
1798+# if defined(CONFIG_ARCH_OMAP4)
1799+# undef cpu_is_omap44xx
1800+# undef cpu_is_omap443x
1801+# define cpu_is_omap44xx() is_omap44xx()
1802+# define cpu_is_omap443x() is_omap443x()
1803+# endif
1804+
1805+/* Macros to detect if we have OMAP1 or OMAP2 */
1806+#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1807+ cpu_is_omap16xx())
1808+#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1809+ cpu_is_omap44xx())
1810+
1811+/* Various silicon revisions for omap2 */
1812+#define OMAP242X_CLASS 0x24200024
1813+#define OMAP2420_REV_ES1_0 0x24200024
1814+#define OMAP2420_REV_ES2_0 0x24201024
1815+
1816+#define OMAP243X_CLASS 0x24300024
1817+#define OMAP2430_REV_ES1_0 0x24300024
1818+
1819+#define OMAP343X_CLASS 0x34300034
1820+#define OMAP3430_REV_ES1_0 0x34300034
1821+#define OMAP3430_REV_ES2_0 0x34301034
1822+#define OMAP3430_REV_ES2_1 0x34302034
1823+#define OMAP3430_REV_ES3_0 0x34303034
1824+#define OMAP3430_REV_ES3_1 0x34304034
1825+
1826+#define OMAP3630_REV_ES1_0 0x36300034
1827+
1828+#define OMAP35XX_CLASS 0x35000034
1829+#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1830+#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1831+#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1832+#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1833+#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1834+#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1835+
1836+#define OMAP443X_CLASS 0x44300044
1837+#define OMAP4430_REV_ES1_0 0x44300044
1838+
1839+/*
1840+ * omap_chip bits
1841+ *
1842+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1843+ * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1844+ * something that is only valid on that particular ES revision.
1845+ *
1846+ * These bits may be ORed together to indicate structures that are
1847+ * available on multiple chip types.
1848+ *
1849+ * To test whether a particular structure matches the current OMAP chip type,
1850+ * use omap_chip_is().
1851+ *
1852+ */
1853+#define CHIP_IS_OMAP2420 (1 << 0)
1854+#define CHIP_IS_OMAP2430 (1 << 1)
1855+#define CHIP_IS_OMAP3430 (1 << 2)
1856+#define CHIP_IS_OMAP3430ES1 (1 << 3)
1857+#define CHIP_IS_OMAP3430ES2 (1 << 4)
1858+#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1859+#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1860+#define CHIP_IS_OMAP3630ES1 (1 << 7)
1861+
1862+#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1863+
1864+/*
1865+ * "GE" here represents "greater than or equal to" in terms of ES
1866+ * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1867+ * chips at ES2 and beyond, but not, for example, any OMAP lines after
1868+ * OMAP3.
1869+ */
1870+#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1871+ CHIP_IS_OMAP3430ES3_0 | \
1872+ CHIP_IS_OMAP3430ES3_1 | \
1873+ CHIP_IS_OMAP3630ES1)
1874+#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1875+ CHIP_IS_OMAP3630ES1)
1876+
1877+
1878+int omap_chip_is(struct omap_chip_id oci);
1879+void omap2_check_revision(void);
1880+
1881+/*
1882+ * Runtime detection of OMAP3 features
1883+ */
1884+extern u32 omap3_features;
1885+
1886+#define OMAP3_HAS_L2CACHE BIT(0)
1887+#define OMAP3_HAS_IVA BIT(1)
1888+#define OMAP3_HAS_SGX BIT(2)
1889+#define OMAP3_HAS_NEON BIT(3)
1890+#define OMAP3_HAS_ISP BIT(4)
1891+
1892+#define OMAP3_HAS_FEATURE(feat,flag) \
1893+static inline unsigned int omap3_has_ ##feat(void) \
1894+{ \
1895+ return (omap3_features & OMAP3_HAS_ ##flag); \
1896+} \
1897+
1898+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
1899+OMAP3_HAS_FEATURE(sgx, SGX)
1900+OMAP3_HAS_FEATURE(iva, IVA)
1901+OMAP3_HAS_FEATURE(neon, NEON)
1902+OMAP3_HAS_FEATURE(isp, ISP)
1903+
1904+#endif
1905Index: linux-2.6.35/arch/arm/plat-omap/include/mach/display.h
1906===================================================================
1907--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1908@@ -0,0 +1,575 @@
1909+/*
1910+ * linux/include/asm-arm/arch-omap/display.h
1911+ *
1912+ * Copyright (C) 2008 Nokia Corporation
1913+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1914+ *
1915+ * This program is free software; you can redistribute it and/or modify it
1916+ * under the terms of the GNU General Public License version 2 as published by
1917+ * the Free Software Foundation.
1918+ *
1919+ * This program is distributed in the hope that it will be useful, but WITHOUT
1920+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1921+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1922+ * more details.
1923+ *
1924+ * You should have received a copy of the GNU General Public License along with
1925+ * this program. If not, see <http://www.gnu.org/licenses/>.
1926+ */
1927+
1928+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
1929+#define __ASM_ARCH_OMAP_DISPLAY_H
1930+
1931+#include <linux/list.h>
1932+#include <linux/kobject.h>
1933+#include <linux/device.h>
1934+#include <asm/atomic.h>
1935+
1936+#define DISPC_IRQ_FRAMEDONE (1 << 0)
1937+#define DISPC_IRQ_VSYNC (1 << 1)
1938+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
1939+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
1940+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
1941+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
1942+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
1943+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
1944+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
1945+#define DISPC_IRQ_OCP_ERR (1 << 9)
1946+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
1947+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
1948+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
1949+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
1950+#define DISPC_IRQ_SYNC_LOST (1 << 14)
1951+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
1952+#define DISPC_IRQ_WAKEUP (1 << 16)
1953+
1954+struct omap_dss_device;
1955+struct omap_overlay_manager;
1956+
1957+enum omap_display_type {
1958+ OMAP_DISPLAY_TYPE_NONE = 0,
1959+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
1960+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
1961+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
1962+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
1963+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
1964+};
1965+
1966+enum omap_plane {
1967+ OMAP_DSS_GFX = 0,
1968+ OMAP_DSS_VIDEO1 = 1,
1969+ OMAP_DSS_VIDEO2 = 2
1970+};
1971+
1972+enum omap_channel {
1973+ OMAP_DSS_CHANNEL_LCD = 0,
1974+ OMAP_DSS_CHANNEL_DIGIT = 1,
1975+};
1976+
1977+enum omap_color_mode {
1978+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
1979+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
1980+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
1981+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
1982+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
1983+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
1984+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
1985+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
1986+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
1987+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
1988+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
1989+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
1990+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
1991+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
1992+
1993+ OMAP_DSS_COLOR_GFX_OMAP2 =
1994+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
1995+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
1996+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
1997+ OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
1998+
1999+ OMAP_DSS_COLOR_VID_OMAP2 =
2000+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2001+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2002+ OMAP_DSS_COLOR_UYVY,
2003+
2004+ OMAP_DSS_COLOR_GFX_OMAP3 =
2005+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2006+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2007+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2008+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2009+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2010+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2011+
2012+ OMAP_DSS_COLOR_VID1_OMAP3 =
2013+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2014+ OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2015+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2016+
2017+ OMAP_DSS_COLOR_VID2_OMAP3 =
2018+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2019+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2020+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2021+ OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2022+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2023+};
2024+
2025+enum omap_lcd_display_type {
2026+ OMAP_DSS_LCD_DISPLAY_STN,
2027+ OMAP_DSS_LCD_DISPLAY_TFT,
2028+};
2029+
2030+enum omap_dss_load_mode {
2031+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2032+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
2033+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
2034+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2035+};
2036+
2037+enum omap_dss_trans_key_type {
2038+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2039+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2040+};
2041+
2042+enum omap_rfbi_te_mode {
2043+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
2044+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
2045+};
2046+
2047+enum omap_panel_config {
2048+ OMAP_DSS_LCD_IVS = 1<<0,
2049+ OMAP_DSS_LCD_IHS = 1<<1,
2050+ OMAP_DSS_LCD_IPC = 1<<2,
2051+ OMAP_DSS_LCD_IEO = 1<<3,
2052+ OMAP_DSS_LCD_RF = 1<<4,
2053+ OMAP_DSS_LCD_ONOFF = 1<<5,
2054+
2055+ OMAP_DSS_LCD_TFT = 1<<20,
2056+};
2057+
2058+enum omap_dss_venc_type {
2059+ OMAP_DSS_VENC_TYPE_COMPOSITE,
2060+ OMAP_DSS_VENC_TYPE_SVIDEO,
2061+};
2062+
2063+enum omap_display_caps {
2064+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2065+ OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2066+};
2067+
2068+enum omap_dss_update_mode {
2069+ OMAP_DSS_UPDATE_DISABLED = 0,
2070+ OMAP_DSS_UPDATE_AUTO,
2071+ OMAP_DSS_UPDATE_MANUAL,
2072+};
2073+
2074+enum omap_dss_display_state {
2075+ OMAP_DSS_DISPLAY_DISABLED = 0,
2076+ OMAP_DSS_DISPLAY_ACTIVE,
2077+ OMAP_DSS_DISPLAY_SUSPENDED,
2078+};
2079+
2080+/* XXX perhaps this should be removed */
2081+enum omap_dss_overlay_managers {
2082+ OMAP_DSS_OVL_MGR_LCD,
2083+ OMAP_DSS_OVL_MGR_TV,
2084+};
2085+
2086+enum omap_dss_rotation_type {
2087+ OMAP_DSS_ROT_DMA = 0,
2088+ OMAP_DSS_ROT_VRFB = 1,
2089+};
2090+
2091+/* clockwise rotation angle */
2092+enum omap_dss_rotation_angle {
2093+ OMAP_DSS_ROT_0 = 0,
2094+ OMAP_DSS_ROT_90 = 1,
2095+ OMAP_DSS_ROT_180 = 2,
2096+ OMAP_DSS_ROT_270 = 3,
2097+};
2098+
2099+enum omap_overlay_caps {
2100+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2101+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2102+};
2103+
2104+enum omap_overlay_manager_caps {
2105+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2106+};
2107+
2108+/* RFBI */
2109+
2110+struct rfbi_timings {
2111+ int cs_on_time;
2112+ int cs_off_time;
2113+ int we_on_time;
2114+ int we_off_time;
2115+ int re_on_time;
2116+ int re_off_time;
2117+ int we_cycle_time;
2118+ int re_cycle_time;
2119+ int cs_pulse_width;
2120+ int access_time;
2121+
2122+ int clk_div;
2123+
2124+ u32 tim[5]; /* set by rfbi_convert_timings() */
2125+
2126+ int converted;
2127+};
2128+
2129+void omap_rfbi_write_command(const void *buf, u32 len);
2130+void omap_rfbi_read_data(void *buf, u32 len);
2131+void omap_rfbi_write_data(const void *buf, u32 len);
2132+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2133+ u16 x, u16 y,
2134+ u16 w, u16 h);
2135+int omap_rfbi_enable_te(bool enable, unsigned line);
2136+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2137+ unsigned hs_pulse_time, unsigned vs_pulse_time,
2138+ int hs_pol_inv, int vs_pol_inv, int extif_div);
2139+
2140+/* DSI */
2141+void dsi_bus_lock(void);
2142+void dsi_bus_unlock(void);
2143+int dsi_vc_dcs_write(int channel, u8 *data, int len);
2144+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2145+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2146+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2147+int dsi_vc_send_null(int channel);
2148+int dsi_vc_send_bta_sync(int channel);
2149+
2150+/* Board specific data */
2151+struct omap_dss_board_info {
2152+ int (*get_last_off_on_transaction_id)(struct device *dev);
2153+ int num_devices;
2154+ struct omap_dss_device **devices;
2155+ struct omap_dss_device *default_device;
2156+};
2157+
2158+struct omap_video_timings {
2159+ /* Unit: pixels */
2160+ u16 x_res;
2161+ /* Unit: pixels */
2162+ u16 y_res;
2163+ /* Unit: KHz */
2164+ u32 pixel_clock;
2165+ /* Unit: pixel clocks */
2166+ u16 hsw; /* Horizontal synchronization pulse width */
2167+ /* Unit: pixel clocks */
2168+ u16 hfp; /* Horizontal front porch */
2169+ /* Unit: pixel clocks */
2170+ u16 hbp; /* Horizontal back porch */
2171+ /* Unit: line clocks */
2172+ u16 vsw; /* Vertical synchronization pulse width */
2173+ /* Unit: line clocks */
2174+ u16 vfp; /* Vertical front porch */
2175+ /* Unit: line clocks */
2176+ u16 vbp; /* Vertical back porch */
2177+};
2178+
2179+#ifdef CONFIG_OMAP2_DSS_VENC
2180+/* Hardcoded timings for tv modes. Venc only uses these to
2181+ * identify the mode, and does not actually use the configs
2182+ * itself. However, the configs should be something that
2183+ * a normal monitor can also show */
2184+const extern struct omap_video_timings omap_dss_pal_timings;
2185+const extern struct omap_video_timings omap_dss_ntsc_timings;
2186+#endif
2187+
2188+struct omap_overlay_info {
2189+ bool enabled;
2190+
2191+ u32 paddr;
2192+ void __iomem *vaddr;
2193+ u16 screen_width;
2194+ u16 width;
2195+ u16 height;
2196+ enum omap_color_mode color_mode;
2197+ u8 rotation;
2198+ enum omap_dss_rotation_type rotation_type;
2199+ bool mirror;
2200+
2201+ u16 pos_x;
2202+ u16 pos_y;
2203+ u16 out_width; /* if 0, out_width == width */
2204+ u16 out_height; /* if 0, out_height == height */
2205+ u8 global_alpha;
2206+};
2207+
2208+struct omap_overlay {
2209+ struct kobject kobj;
2210+ struct list_head list;
2211+
2212+ /* static fields */
2213+ const char *name;
2214+ int id;
2215+ enum omap_color_mode supported_modes;
2216+ enum omap_overlay_caps caps;
2217+
2218+ /* dynamic fields */
2219+ struct omap_overlay_manager *manager;
2220+ struct omap_overlay_info info;
2221+
2222+ /* if true, info has been changed, but not applied() yet */
2223+ bool info_dirty;
2224+
2225+ int (*set_manager)(struct omap_overlay *ovl,
2226+ struct omap_overlay_manager *mgr);
2227+ int (*unset_manager)(struct omap_overlay *ovl);
2228+
2229+ int (*set_overlay_info)(struct omap_overlay *ovl,
2230+ struct omap_overlay_info *info);
2231+ void (*get_overlay_info)(struct omap_overlay *ovl,
2232+ struct omap_overlay_info *info);
2233+
2234+ int (*wait_for_go)(struct omap_overlay *ovl);
2235+};
2236+
2237+struct omap_overlay_manager_info {
2238+ u32 default_color;
2239+
2240+ enum omap_dss_trans_key_type trans_key_type;
2241+ u32 trans_key;
2242+ bool trans_enabled;
2243+
2244+ bool alpha_enabled;
2245+};
2246+
2247+struct omap_overlay_manager {
2248+ struct kobject kobj;
2249+ struct list_head list;
2250+
2251+ /* static fields */
2252+ const char *name;
2253+ int id;
2254+ enum omap_overlay_manager_caps caps;
2255+ int num_overlays;
2256+ struct omap_overlay **overlays;
2257+ enum omap_display_type supported_displays;
2258+
2259+ /* dynamic fields */
2260+ struct omap_dss_device *device;
2261+ struct omap_overlay_manager_info info;
2262+
2263+ bool device_changed;
2264+ /* if true, info has been changed but not applied() yet */
2265+ bool info_dirty;
2266+
2267+ int (*set_device)(struct omap_overlay_manager *mgr,
2268+ struct omap_dss_device *dssdev);
2269+ int (*unset_device)(struct omap_overlay_manager *mgr);
2270+
2271+ int (*set_manager_info)(struct omap_overlay_manager *mgr,
2272+ struct omap_overlay_manager_info *info);
2273+ void (*get_manager_info)(struct omap_overlay_manager *mgr,
2274+ struct omap_overlay_manager_info *info);
2275+
2276+ int (*apply)(struct omap_overlay_manager *mgr);
2277+ int (*wait_for_go)(struct omap_overlay_manager *mgr);
2278+};
2279+
2280+struct omap_dss_device {
2281+ struct device dev;
2282+
2283+ enum omap_display_type type;
2284+
2285+ union {
2286+ struct {
2287+ u8 data_lines;
2288+ } dpi;
2289+
2290+ struct {
2291+ u8 channel;
2292+ u8 data_lines;
2293+ } rfbi;
2294+
2295+ struct {
2296+ u8 datapairs;
2297+ } sdi;
2298+
2299+ struct {
2300+ u8 clk_lane;
2301+ u8 clk_pol;
2302+ u8 data1_lane;
2303+ u8 data1_pol;
2304+ u8 data2_lane;
2305+ u8 data2_pol;
2306+
2307+ struct {
2308+ u16 regn;
2309+ u16 regm;
2310+ u16 regm3;
2311+ u16 regm4;
2312+
2313+ u16 lp_clk_div;
2314+
2315+ u16 lck_div;
2316+ u16 pck_div;
2317+ } div;
2318+
2319+ bool ext_te;
2320+ u8 ext_te_gpio;
2321+ } dsi;
2322+
2323+ struct {
2324+ enum omap_dss_venc_type type;
2325+ bool invert_polarity;
2326+ } venc;
2327+ } phy;
2328+
2329+ struct {
2330+ struct omap_video_timings timings;
2331+
2332+ int acbi; /* ac-bias pin transitions per interrupt */
2333+ /* Unit: line clocks */
2334+ int acb; /* ac-bias pin frequency */
2335+
2336+ enum omap_panel_config config;
2337+
2338+ u8 recommended_bpp;
2339+
2340+ struct omap_dss_device *ctrl;
2341+ } panel;
2342+
2343+ struct {
2344+ u8 pixel_size;
2345+ struct rfbi_timings rfbi_timings;
2346+ struct omap_dss_device *panel;
2347+ } ctrl;
2348+
2349+ int reset_gpio;
2350+
2351+ int max_backlight_level;
2352+
2353+ const char *name;
2354+
2355+ /* used to match device to driver */
2356+ const char *driver_name;
2357+
2358+ void *data;
2359+
2360+ struct omap_dss_driver *driver;
2361+
2362+ /* helper variable for driver suspend/resume */
2363+ bool activate_after_resume;
2364+
2365+ enum omap_display_caps caps;
2366+
2367+ struct omap_overlay_manager *manager;
2368+
2369+ enum omap_dss_display_state state;
2370+
2371+ int (*enable)(struct omap_dss_device *dssdev);
2372+ void (*disable)(struct omap_dss_device *dssdev);
2373+
2374+ int (*suspend)(struct omap_dss_device *dssdev);
2375+ int (*resume)(struct omap_dss_device *dssdev);
2376+
2377+ void (*get_resolution)(struct omap_dss_device *dssdev,
2378+ u16 *xres, u16 *yres);
2379+ int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2380+
2381+ int (*check_timings)(struct omap_dss_device *dssdev,
2382+ struct omap_video_timings *timings);
2383+ void (*set_timings)(struct omap_dss_device *dssdev,
2384+ struct omap_video_timings *timings);
2385+ void (*get_timings)(struct omap_dss_device *dssdev,
2386+ struct omap_video_timings *timings);
2387+ int (*update)(struct omap_dss_device *dssdev,
2388+ u16 x, u16 y, u16 w, u16 h);
2389+ int (*sync)(struct omap_dss_device *dssdev);
2390+ int (*wait_vsync)(struct omap_dss_device *dssdev);
2391+
2392+ int (*set_update_mode)(struct omap_dss_device *dssdev,
2393+ enum omap_dss_update_mode);
2394+ enum omap_dss_update_mode (*get_update_mode)
2395+ (struct omap_dss_device *dssdev);
2396+
2397+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2398+ int (*get_te)(struct omap_dss_device *dssdev);
2399+
2400+ u8 (*get_rotate)(struct omap_dss_device *dssdev);
2401+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2402+
2403+ bool (*get_mirror)(struct omap_dss_device *dssdev);
2404+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2405+
2406+ int (*run_test)(struct omap_dss_device *dssdev, int test);
2407+ int (*memory_read)(struct omap_dss_device *dssdev,
2408+ void *buf, size_t size,
2409+ u16 x, u16 y, u16 w, u16 h);
2410+
2411+ int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2412+ u32 (*get_wss)(struct omap_dss_device *dssdev);
2413+
2414+ /* platform specific */
2415+ int (*platform_enable)(struct omap_dss_device *dssdev);
2416+ void (*platform_disable)(struct omap_dss_device *dssdev);
2417+ int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2418+ int (*get_backlight)(struct omap_dss_device *dssdev);
2419+};
2420+
2421+struct omap_dss_driver {
2422+ struct device_driver driver;
2423+
2424+ int (*probe)(struct omap_dss_device *);
2425+ void (*remove)(struct omap_dss_device *);
2426+
2427+ int (*enable)(struct omap_dss_device *display);
2428+ void (*disable)(struct omap_dss_device *display);
2429+ int (*suspend)(struct omap_dss_device *display);
2430+ int (*resume)(struct omap_dss_device *display);
2431+ int (*run_test)(struct omap_dss_device *display, int test);
2432+
2433+ void (*setup_update)(struct omap_dss_device *dssdev,
2434+ u16 x, u16 y, u16 w, u16 h);
2435+
2436+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2437+ int (*wait_for_te)(struct omap_dss_device *dssdev);
2438+
2439+ u8 (*get_rotate)(struct omap_dss_device *dssdev);
2440+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2441+
2442+ bool (*get_mirror)(struct omap_dss_device *dssdev);
2443+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2444+
2445+ int (*memory_read)(struct omap_dss_device *dssdev,
2446+ void *buf, size_t size,
2447+ u16 x, u16 y, u16 w, u16 h);
2448+};
2449+
2450+int omap_dss_register_driver(struct omap_dss_driver *);
2451+void omap_dss_unregister_driver(struct omap_dss_driver *);
2452+
2453+int omap_dss_register_device(struct omap_dss_device *);
2454+void omap_dss_unregister_device(struct omap_dss_device *);
2455+
2456+void omap_dss_get_device(struct omap_dss_device *dssdev);
2457+void omap_dss_put_device(struct omap_dss_device *dssdev);
2458+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2459+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2460+struct omap_dss_device *omap_dss_find_device(void *data,
2461+ int (*match)(struct omap_dss_device *dssdev, void *data));
2462+
2463+int omap_dss_start_device(struct omap_dss_device *dssdev);
2464+void omap_dss_stop_device(struct omap_dss_device *dssdev);
2465+
2466+int omap_dss_get_num_overlay_managers(void);
2467+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2468+
2469+int omap_dss_get_num_overlays(void);
2470+struct omap_overlay *omap_dss_get_overlay(int num);
2471+
2472+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2473+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2474+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2475+
2476+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2477+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2478+ unsigned long timeout);
2479+
2480+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2481+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2482+
2483+#endif
2484Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dma.h
2485===================================================================
2486--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2487@@ -0,0 +1,640 @@
2488+/*
2489+ * arch/arm/plat-omap/include/mach/dma.h
2490+ *
2491+ * Copyright (C) 2003 Nokia Corporation
2492+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2493+ *
2494+ * This program is free software; you can redistribute it and/or modify
2495+ * it under the terms of the GNU General Public License as published by
2496+ * the Free Software Foundation; either version 2 of the License, or
2497+ * (at your option) any later version.
2498+ *
2499+ * This program is distributed in the hope that it will be useful,
2500+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2501+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2502+ * GNU General Public License for more details.
2503+ *
2504+ * You should have received a copy of the GNU General Public License
2505+ * along with this program; if not, write to the Free Software
2506+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2507+ */
2508+#ifndef __ASM_ARCH_DMA_H
2509+#define __ASM_ARCH_DMA_H
2510+
2511+/* Hardware registers for omap1 */
2512+#define OMAP1_DMA_BASE (0xfffed800)
2513+
2514+#define OMAP1_DMA_GCR 0x400
2515+#define OMAP1_DMA_GSCR 0x404
2516+#define OMAP1_DMA_GRST 0x408
2517+#define OMAP1_DMA_HW_ID 0x442
2518+#define OMAP1_DMA_PCH2_ID 0x444
2519+#define OMAP1_DMA_PCH0_ID 0x446
2520+#define OMAP1_DMA_PCH1_ID 0x448
2521+#define OMAP1_DMA_PCHG_ID 0x44a
2522+#define OMAP1_DMA_PCHD_ID 0x44c
2523+#define OMAP1_DMA_CAPS_0_U 0x44e
2524+#define OMAP1_DMA_CAPS_0_L 0x450
2525+#define OMAP1_DMA_CAPS_1_U 0x452
2526+#define OMAP1_DMA_CAPS_1_L 0x454
2527+#define OMAP1_DMA_CAPS_2 0x456
2528+#define OMAP1_DMA_CAPS_3 0x458
2529+#define OMAP1_DMA_CAPS_4 0x45a
2530+#define OMAP1_DMA_PCH2_SR 0x460
2531+#define OMAP1_DMA_PCH0_SR 0x480
2532+#define OMAP1_DMA_PCH1_SR 0x482
2533+#define OMAP1_DMA_PCHD_SR 0x4c0
2534+
2535+/* Hardware registers for omap2 and omap3 */
2536+#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2537+#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2538+#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2539+
2540+#define OMAP_DMA4_REVISION 0x00
2541+#define OMAP_DMA4_GCR 0x78
2542+#define OMAP_DMA4_IRQSTATUS_L0 0x08
2543+#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2544+#define OMAP_DMA4_IRQSTATUS_L2 0x10
2545+#define OMAP_DMA4_IRQSTATUS_L3 0x14
2546+#define OMAP_DMA4_IRQENABLE_L0 0x18
2547+#define OMAP_DMA4_IRQENABLE_L1 0x1c
2548+#define OMAP_DMA4_IRQENABLE_L2 0x20
2549+#define OMAP_DMA4_IRQENABLE_L3 0x24
2550+#define OMAP_DMA4_SYSSTATUS 0x28
2551+#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2552+#define OMAP_DMA4_CAPS_0 0x64
2553+#define OMAP_DMA4_CAPS_2 0x6c
2554+#define OMAP_DMA4_CAPS_3 0x70
2555+#define OMAP_DMA4_CAPS_4 0x74
2556+
2557+#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2558+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2559+
2560+/* Common channel specific registers for omap1 */
2561+#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2562+#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2563+#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2564+#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2565+#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2566+#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2567+#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2568+#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2569+#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2570+#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2571+#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2572+#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2573+#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2574+#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2575+#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2576+
2577+/* Common channel specific registers for omap2 */
2578+#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2579+#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2580+#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2581+#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2582+#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2583+#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2584+#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2585+#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2586+#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2587+#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2588+#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2589+#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2590+#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2591+#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2592+
2593+/* Channel specific registers only on omap1 */
2594+#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2595+#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2596+#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2597+#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2598+#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2599+#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2600+#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2601+#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2602+#define OMAP1_DMA_CCEN(n) 0
2603+#define OMAP1_DMA_CCFN(n) 0
2604+
2605+/* Channel specific registers only on omap2 */
2606+#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2607+#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2608+#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2609+#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2610+#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2611+
2612+/* Additional registers available on OMAP4 */
2613+#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2614+#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2615+#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2616+
2617+/* Dummy defines to keep multi-omap compiles happy */
2618+#define OMAP1_DMA_REVISION 0
2619+#define OMAP1_DMA_IRQSTATUS_L0 0
2620+#define OMAP1_DMA_IRQENABLE_L0 0
2621+#define OMAP1_DMA_OCP_SYSCONFIG 0
2622+#define OMAP_DMA4_HW_ID 0
2623+#define OMAP_DMA4_CAPS_0_L 0
2624+#define OMAP_DMA4_CAPS_0_U 0
2625+#define OMAP_DMA4_CAPS_1_L 0
2626+#define OMAP_DMA4_CAPS_1_U 0
2627+#define OMAP_DMA4_GSCR 0
2628+#define OMAP_DMA4_CPC(n) 0
2629+
2630+#define OMAP_DMA4_LCH_CTRL(n) 0
2631+#define OMAP_DMA4_COLOR_L(n) 0
2632+#define OMAP_DMA4_COLOR_U(n) 0
2633+#define OMAP_DMA4_CCR2(n) 0
2634+#define OMAP1_DMA_CSSA(n) 0
2635+#define OMAP1_DMA_CDSA(n) 0
2636+#define OMAP_DMA4_CSSA_L(n) 0
2637+#define OMAP_DMA4_CSSA_U(n) 0
2638+#define OMAP_DMA4_CDSA_L(n) 0
2639+#define OMAP_DMA4_CDSA_U(n) 0
2640+#define OMAP1_DMA_COLOR(n) 0
2641+
2642+/*----------------------------------------------------------------------------*/
2643+
2644+/* DMA channels for omap1 */
2645+#define OMAP_DMA_NO_DEVICE 0
2646+#define OMAP_DMA_MCSI1_TX 1
2647+#define OMAP_DMA_MCSI1_RX 2
2648+#define OMAP_DMA_I2C_RX 3
2649+#define OMAP_DMA_I2C_TX 4
2650+#define OMAP_DMA_EXT_NDMA_REQ 5
2651+#define OMAP_DMA_EXT_NDMA_REQ2 6
2652+#define OMAP_DMA_UWIRE_TX 7
2653+#define OMAP_DMA_MCBSP1_TX 8
2654+#define OMAP_DMA_MCBSP1_RX 9
2655+#define OMAP_DMA_MCBSP3_TX 10
2656+#define OMAP_DMA_MCBSP3_RX 11
2657+#define OMAP_DMA_UART1_TX 12
2658+#define OMAP_DMA_UART1_RX 13
2659+#define OMAP_DMA_UART2_TX 14
2660+#define OMAP_DMA_UART2_RX 15
2661+#define OMAP_DMA_MCBSP2_TX 16
2662+#define OMAP_DMA_MCBSP2_RX 17
2663+#define OMAP_DMA_UART3_TX 18
2664+#define OMAP_DMA_UART3_RX 19
2665+#define OMAP_DMA_CAMERA_IF_RX 20
2666+#define OMAP_DMA_MMC_TX 21
2667+#define OMAP_DMA_MMC_RX 22
2668+#define OMAP_DMA_NAND 23
2669+#define OMAP_DMA_IRQ_LCD_LINE 24
2670+#define OMAP_DMA_MEMORY_STICK 25
2671+#define OMAP_DMA_USB_W2FC_RX0 26
2672+#define OMAP_DMA_USB_W2FC_RX1 27
2673+#define OMAP_DMA_USB_W2FC_RX2 28
2674+#define OMAP_DMA_USB_W2FC_TX0 29
2675+#define OMAP_DMA_USB_W2FC_TX1 30
2676+#define OMAP_DMA_USB_W2FC_TX2 31
2677+
2678+/* These are only for 1610 */
2679+#define OMAP_DMA_CRYPTO_DES_IN 32
2680+#define OMAP_DMA_SPI_TX 33
2681+#define OMAP_DMA_SPI_RX 34
2682+#define OMAP_DMA_CRYPTO_HASH 35
2683+#define OMAP_DMA_CCP_ATTN 36
2684+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2685+#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2686+#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2687+#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2688+#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2689+#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2690+#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2691+#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2692+#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2693+#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2694+#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2695+#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2696+#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2697+#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2698+#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2699+#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2700+#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2701+#define OMAP_DMA_MMC2_TX 54
2702+#define OMAP_DMA_MMC2_RX 55
2703+#define OMAP_DMA_CRYPTO_DES_OUT 56
2704+
2705+/* DMA channels for 24xx */
2706+#define OMAP24XX_DMA_NO_DEVICE 0
2707+#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2708+#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2709+#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2710+#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2711+#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2712+#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2713+#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2714+#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2715+#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2716+#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2717+#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2718+#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2719+#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2720+#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2721+#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2722+#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2723+#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2724+#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2725+#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2726+#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2727+#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2728+#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2729+#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2730+#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2731+#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2732+#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2733+#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2734+#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2735+#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2736+#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2737+#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2738+#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2739+#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2740+#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2741+#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2742+#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2743+#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2744+#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2745+#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2746+#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2747+#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2748+#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2749+#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2750+#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2751+#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2752+#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2753+#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2754+#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2755+#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2756+#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2757+#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2758+#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2759+#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2760+#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2761+#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2762+#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2763+#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2764+#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2765+#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2766+#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2767+#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2768+#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2769+#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2770+#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2771+#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2772+#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2773+#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2774+#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2775+#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2776+#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2777+#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2778+#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2779+#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2780+#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2781+#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2782+#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2783+#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2784+#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2785+#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2786+#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2787+#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2788+#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2789+#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2790+#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2791+#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2792+#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2793+#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2794+#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2795+#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2796+#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2797+#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2798+#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2799+#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2800+#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2801+#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2802+#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2803+#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2804+#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2805+
2806+/* DMA request lines for 44xx */
2807+#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2808+#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2809+#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2810+#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2811+#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2812+#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2813+#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2814+#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2815+#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2816+#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2817+#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2818+#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2819+#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2820+#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2821+#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2822+#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2823+#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2824+#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2825+#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2826+#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2827+#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2828+#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2829+#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2830+#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2831+#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2832+#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2833+#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2834+#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2835+#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2836+#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2837+#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2838+#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2839+#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2840+#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2841+#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2842+#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2843+#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2844+#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2845+#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2846+#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2847+#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2848+#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2849+#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2850+#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2851+#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2852+#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2853+#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2854+#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2855+#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2856+#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2857+#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2858+#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2859+#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2860+#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2861+#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2862+#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2863+#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2864+#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2865+#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2866+#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2867+#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2868+#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2869+#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2870+#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2871+#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2872+#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2873+#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2874+#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2875+#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2876+#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2877+#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2878+#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2879+#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2880+#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2881+#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2882+#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2883+#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2884+#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2885+#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2886+#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2887+#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2888+
2889+/*----------------------------------------------------------------------------*/
2890+
2891+#define OMAP1_DMA_TOUT_IRQ (1 << 0)
2892+#define OMAP_DMA_DROP_IRQ (1 << 1)
2893+#define OMAP_DMA_HALF_IRQ (1 << 2)
2894+#define OMAP_DMA_FRAME_IRQ (1 << 3)
2895+#define OMAP_DMA_LAST_IRQ (1 << 4)
2896+#define OMAP_DMA_BLOCK_IRQ (1 << 5)
2897+#define OMAP1_DMA_SYNC_IRQ (1 << 6)
2898+#define OMAP2_DMA_PKT_IRQ (1 << 7)
2899+#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
2900+#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
2901+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
2902+#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
2903+
2904+#define OMAP_DMA_CCR_EN (1 << 7)
2905+
2906+#define OMAP_DMA_DATA_TYPE_S8 0x00
2907+#define OMAP_DMA_DATA_TYPE_S16 0x01
2908+#define OMAP_DMA_DATA_TYPE_S32 0x02
2909+
2910+#define OMAP_DMA_SYNC_ELEMENT 0x00
2911+#define OMAP_DMA_SYNC_FRAME 0x01
2912+#define OMAP_DMA_SYNC_BLOCK 0x02
2913+#define OMAP_DMA_SYNC_PACKET 0x03
2914+
2915+#define OMAP_DMA_SRC_SYNC 0x01
2916+#define OMAP_DMA_DST_SYNC 0x00
2917+
2918+#define OMAP_DMA_PORT_EMIFF 0x00
2919+#define OMAP_DMA_PORT_EMIFS 0x01
2920+#define OMAP_DMA_PORT_OCP_T1 0x02
2921+#define OMAP_DMA_PORT_TIPB 0x03
2922+#define OMAP_DMA_PORT_OCP_T2 0x04
2923+#define OMAP_DMA_PORT_MPUI 0x05
2924+
2925+#define OMAP_DMA_AMODE_CONSTANT 0x00
2926+#define OMAP_DMA_AMODE_POST_INC 0x01
2927+#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
2928+#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
2929+
2930+#define DMA_DEFAULT_FIFO_DEPTH 0x10
2931+#define DMA_DEFAULT_ARB_RATE 0x01
2932+/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
2933+#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
2934+#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
2935+#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
2936+#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
2937+#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
2938+#define DMA_THREAD_FIFO_75 (0x01 << 14)
2939+#define DMA_THREAD_FIFO_25 (0x02 << 14)
2940+#define DMA_THREAD_FIFO_50 (0x03 << 14)
2941+
2942+/* DMA4_OCP_SYSCONFIG bits */
2943+#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
2944+#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
2945+#define DMA_SYSCONFIG_EMUFREE (1 << 5)
2946+#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
2947+#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
2948+#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
2949+
2950+#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
2951+#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
2952+
2953+#define DMA_IDLEMODE_SMARTIDLE 0x2
2954+#define DMA_IDLEMODE_NO_IDLE 0x1
2955+#define DMA_IDLEMODE_FORCE_IDLE 0x0
2956+
2957+/* Chaining modes*/
2958+#ifndef CONFIG_ARCH_OMAP1
2959+#define OMAP_DMA_STATIC_CHAIN 0x1
2960+#define OMAP_DMA_DYNAMIC_CHAIN 0x2
2961+#define OMAP_DMA_CHAIN_ACTIVE 0x1
2962+#define OMAP_DMA_CHAIN_INACTIVE 0x0
2963+#endif
2964+
2965+#define DMA_CH_PRIO_HIGH 0x1
2966+#define DMA_CH_PRIO_LOW 0x0 /* Def */
2967+
2968+enum omap_dma_burst_mode {
2969+ OMAP_DMA_DATA_BURST_DIS = 0,
2970+ OMAP_DMA_DATA_BURST_4,
2971+ OMAP_DMA_DATA_BURST_8,
2972+ OMAP_DMA_DATA_BURST_16,
2973+};
2974+
2975+enum end_type {
2976+ OMAP_DMA_LITTLE_ENDIAN = 0,
2977+ OMAP_DMA_BIG_ENDIAN
2978+};
2979+
2980+enum omap_dma_color_mode {
2981+ OMAP_DMA_COLOR_DIS = 0,
2982+ OMAP_DMA_CONSTANT_FILL,
2983+ OMAP_DMA_TRANSPARENT_COPY
2984+};
2985+
2986+enum omap_dma_write_mode {
2987+ OMAP_DMA_WRITE_NON_POSTED = 0,
2988+ OMAP_DMA_WRITE_POSTED,
2989+ OMAP_DMA_WRITE_LAST_NON_POSTED
2990+};
2991+
2992+enum omap_dma_channel_mode {
2993+ OMAP_DMA_LCH_2D = 0,
2994+ OMAP_DMA_LCH_G,
2995+ OMAP_DMA_LCH_P,
2996+ OMAP_DMA_LCH_PD
2997+};
2998+
2999+struct omap_dma_channel_params {
3000+ int data_type; /* data type 8,16,32 */
3001+ int elem_count; /* number of elements in a frame */
3002+ int frame_count; /* number of frames in a element */
3003+
3004+ int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3005+ int src_amode; /* constant, post increment, indexed,
3006+ double indexed */
3007+ unsigned long src_start; /* source address : physical */
3008+ int src_ei; /* source element index */
3009+ int src_fi; /* source frame index */
3010+
3011+ int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3012+ int dst_amode; /* constant, post increment, indexed,
3013+ double indexed */
3014+ unsigned long dst_start; /* source address : physical */
3015+ int dst_ei; /* source element index */
3016+ int dst_fi; /* source frame index */
3017+
3018+ int trigger; /* trigger attached if the channel is
3019+ synchronized */
3020+ int sync_mode; /* sycn on element, frame , block or packet */
3021+ int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3022+
3023+ int ie; /* interrupt enabled */
3024+
3025+ unsigned char read_prio;/* read priority */
3026+ unsigned char write_prio;/* write priority */
3027+
3028+#ifndef CONFIG_ARCH_OMAP1
3029+ enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3030+#endif
3031+};
3032+
3033+
3034+extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3035+extern int omap_request_dma(int dev_id, const char *dev_name,
3036+ void (*callback)(int lch, u16 ch_status, void *data),
3037+ void *data, int *dma_ch);
3038+extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3039+extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3040+extern void omap_free_dma(int ch);
3041+extern void omap_start_dma(int lch);
3042+extern void omap_stop_dma(int lch);
3043+extern void omap_set_dma_transfer_params(int lch, int data_type,
3044+ int elem_count, int frame_count,
3045+ int sync_mode,
3046+ int dma_trigger, int src_or_dst_synch);
3047+extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3048+ u32 color);
3049+extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3050+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3051+
3052+extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3053+ unsigned long src_start,
3054+ int src_ei, int src_fi);
3055+extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3056+extern void omap_set_dma_src_data_pack(int lch, int enable);
3057+extern void omap_set_dma_src_burst_mode(int lch,
3058+ enum omap_dma_burst_mode burst_mode);
3059+
3060+extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3061+ unsigned long dest_start,
3062+ int dst_ei, int dst_fi);
3063+extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3064+extern void omap_set_dma_dest_data_pack(int lch, int enable);
3065+extern void omap_set_dma_dest_burst_mode(int lch,
3066+ enum omap_dma_burst_mode burst_mode);
3067+
3068+extern void omap_set_dma_params(int lch,
3069+ struct omap_dma_channel_params *params);
3070+
3071+extern void omap_dma_link_lch(int lch_head, int lch_queue);
3072+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3073+
3074+extern int omap_set_dma_callback(int lch,
3075+ void (*callback)(int lch, u16 ch_status, void *data),
3076+ void *data);
3077+extern dma_addr_t omap_get_dma_src_pos(int lch);
3078+extern dma_addr_t omap_get_dma_dst_pos(int lch);
3079+extern void omap_clear_dma(int lch);
3080+extern int omap_get_dma_active_status(int lch);
3081+extern int omap_dma_running(void);
3082+extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3083+ int tparams);
3084+extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3085+ unsigned char write_prio);
3086+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3087+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3088+extern int omap_get_dma_index(int lch, int *ei, int *fi);
3089+
3090+void omap_dma_global_context_save(void);
3091+void omap_dma_global_context_restore(void);
3092+
3093+extern void omap_dma_disable_irq(int lch);
3094+
3095+/* Chaining APIs */
3096+#ifndef CONFIG_ARCH_OMAP1
3097+extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3098+ void (*callback) (int lch, u16 ch_status,
3099+ void *data),
3100+ int *chain_id, int no_of_chans,
3101+ int chain_mode,
3102+ struct omap_dma_channel_params params);
3103+extern int omap_free_dma_chain(int chain_id);
3104+extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3105+ int dest_start, int elem_count,
3106+ int frame_count, void *callbk_data);
3107+extern int omap_start_dma_chain_transfers(int chain_id);
3108+extern int omap_stop_dma_chain_transfers(int chain_id);
3109+extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3110+extern int omap_get_dma_chain_dst_pos(int chain_id);
3111+extern int omap_get_dma_chain_src_pos(int chain_id);
3112+
3113+extern int omap_modify_dma_chain_params(int chain_id,
3114+ struct omap_dma_channel_params params);
3115+extern int omap_dma_chain_status(int chain_id);
3116+#endif
3117+
3118+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3119+#include <mach/lcd_dma.h>
3120+#else
3121+static inline int omap_lcd_dma_running(void)
3122+{
3123+ return 0;
3124+}
3125+#endif
3126+
3127+#endif /* __ASM_ARCH_DMA_H */
3128Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dmtimer.h
3129===================================================================
3130--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3131@@ -0,0 +1,84 @@
3132+/*
3133+ * arch/arm/plat-omap/include/mach/dmtimer.h
3134+ *
3135+ * OMAP Dual-Mode Timers
3136+ *
3137+ * Copyright (C) 2005 Nokia Corporation
3138+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3139+ * PWM and clock framwork support by Timo Teras.
3140+ *
3141+ * This program is free software; you can redistribute it and/or modify it
3142+ * under the terms of the GNU General Public License as published by the
3143+ * Free Software Foundation; either version 2 of the License, or (at your
3144+ * option) any later version.
3145+ *
3146+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3147+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3148+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3149+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3150+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3151+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3152+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3153+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3154+ *
3155+ * You should have received a copy of the GNU General Public License along
3156+ * with this program; if not, write to the Free Software Foundation, Inc.,
3157+ * 675 Mass Ave, Cambridge, MA 02139, USA.
3158+ */
3159+
3160+#ifndef __ASM_ARCH_DMTIMER_H
3161+#define __ASM_ARCH_DMTIMER_H
3162+
3163+/* clock sources */
3164+#define OMAP_TIMER_SRC_SYS_CLK 0x00
3165+#define OMAP_TIMER_SRC_32_KHZ 0x01
3166+#define OMAP_TIMER_SRC_EXT_CLK 0x02
3167+
3168+/* timer interrupt enable bits */
3169+#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3170+#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3171+#define OMAP_TIMER_INT_MATCH (1 << 0)
3172+
3173+/* trigger types */
3174+#define OMAP_TIMER_TRIGGER_NONE 0x00
3175+#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3176+#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3177+
3178+struct omap_dm_timer;
3179+struct clk;
3180+
3181+int omap_dm_timer_init(void);
3182+
3183+struct omap_dm_timer *omap_dm_timer_request(void);
3184+struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3185+void omap_dm_timer_free(struct omap_dm_timer *timer);
3186+void omap_dm_timer_enable(struct omap_dm_timer *timer);
3187+void omap_dm_timer_disable(struct omap_dm_timer *timer);
3188+
3189+int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3190+
3191+u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3192+struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3193+
3194+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3195+void omap_dm_timer_start(struct omap_dm_timer *timer);
3196+void omap_dm_timer_stop(struct omap_dm_timer *timer);
3197+
3198+int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3199+void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3200+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3201+void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3202+void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3203+void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3204+
3205+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3206+
3207+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3208+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3209+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3210+void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3211+
3212+int omap_dm_timers_active(void);
3213+
3214+
3215+#endif /* __ASM_ARCH_DMTIMER_H */
3216Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dsp_common.h
3217===================================================================
3218--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3219@@ -0,0 +1,40 @@
3220+/*
3221+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3222+ *
3223+ * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3224+ *
3225+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3226+ *
3227+ * This program is free software; you can redistribute it and/or
3228+ * modify it under the terms of the GNU General Public License
3229+ * version 2 as published by the Free Software Foundation.
3230+ *
3231+ * This program is distributed in the hope that it will be useful, but
3232+ * WITHOUT ANY WARRANTY; without even the implied warranty of
3233+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3234+ * General Public License for more details.
3235+ *
3236+ * You should have received a copy of the GNU General Public License
3237+ * along with this program; if not, write to the Free Software
3238+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3239+ * 02110-1301 USA
3240+ *
3241+ */
3242+
3243+#ifndef ASM_ARCH_DSP_COMMON_H
3244+#define ASM_ARCH_DSP_COMMON_H
3245+
3246+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3247+extern void omap_dsp_request_mpui(void);
3248+extern void omap_dsp_release_mpui(void);
3249+extern int omap_dsp_request_mem(void);
3250+extern int omap_dsp_release_mem(void);
3251+#else
3252+static inline int omap_dsp_request_mem(void)
3253+{
3254+ return 0;
3255+}
3256+#define omap_dsp_release_mem() do {} while (0)
3257+#endif
3258+
3259+#endif /* ASM_ARCH_DSP_COMMON_H */
3260Index: linux-2.6.35/arch/arm/plat-omap/include/mach/fpga.h
3261===================================================================
3262--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3263@@ -0,0 +1,197 @@
3264+/*
3265+ * arch/arm/plat-omap/include/mach/fpga.h
3266+ *
3267+ * Interrupt handler for OMAP-1510 FPGA
3268+ *
3269+ * Copyright (C) 2001 RidgeRun, Inc.
3270+ * Author: Greg Lonnon <glonnon@ridgerun.com>
3271+ *
3272+ * Copyright (C) 2002 MontaVista Software, Inc.
3273+ *
3274+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3275+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3276+ *
3277+ * This program is free software; you can redistribute it and/or modify
3278+ * it under the terms of the GNU General Public License version 2 as
3279+ * published by the Free Software Foundation.
3280+ */
3281+
3282+#ifndef __ASM_ARCH_OMAP_FPGA_H
3283+#define __ASM_ARCH_OMAP_FPGA_H
3284+
3285+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3286+extern void omap1510_fpga_init_irq(void);
3287+#else
3288+#define omap1510_fpga_init_irq() (0)
3289+#endif
3290+
3291+#define fpga_read(reg) __raw_readb(reg)
3292+#define fpga_write(val, reg) __raw_writeb(val, reg)
3293+
3294+/*
3295+ * ---------------------------------------------------------------------------
3296+ * H2/P2 Debug board FPGA
3297+ * ---------------------------------------------------------------------------
3298+ */
3299+/* maps in the FPGA registers and the ETHR registers */
3300+#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3301+#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3302+#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3303+
3304+#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3305+#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3306+#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3307+#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3308+#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3309+#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3310+#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3311+#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3312+
3313+/* NOTE: most boards don't have a static mapping for the FPGA ... */
3314+struct h2p2_dbg_fpga {
3315+ /* offset 0x00 */
3316+ u16 smc91x[8];
3317+ /* offset 0x10 */
3318+ u16 fpga_rev;
3319+ u16 board_rev;
3320+ u16 gpio_outputs;
3321+ u16 leds;
3322+ /* offset 0x18 */
3323+ u16 misc_inputs;
3324+ u16 lan_status;
3325+ u16 lan_reset;
3326+ u16 reserved0;
3327+ /* offset 0x20 */
3328+ u16 ps2_data;
3329+ u16 ps2_ctrl;
3330+ /* plus also 4 rs232 ports ... */
3331+};
3332+
3333+/* LEDs definition on debug board (16 LEDs, all physically green) */
3334+#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3335+#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3336+#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3337+#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3338+/* cpu0 load-meter LEDs */
3339+#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3340+#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3341+#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3342+
3343+#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3344+#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3345+
3346+/*
3347+ * ---------------------------------------------------------------------------
3348+ * OMAP-1510 FPGA
3349+ * ---------------------------------------------------------------------------
3350+ */
3351+#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3352+#define OMAP1510_FPGA_SIZE SZ_4K
3353+#define OMAP1510_FPGA_START 0x08000000 /* PA */
3354+
3355+/* Revision */
3356+#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3357+#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3358+
3359+#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3360+#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3361+#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3362+#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3363+
3364+/* Interrupt status */
3365+#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3366+#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3367+
3368+/* Interrupt mask */
3369+#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3370+#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3371+
3372+/* Reset registers */
3373+#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3374+#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3375+
3376+#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3377+#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3378+#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3379+#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3380+#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3381+#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3382+#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3383+#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3384+#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3385+#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3386+
3387+#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3388+
3389+#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3390+#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3391+#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3392+#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3393+#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3394+#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3395+#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3396+#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3397+#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3398+#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3399+#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3400+
3401+#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3402+
3403+/*
3404+ * Power up Giga UART driver, turn on HID clock.
3405+ * Turn off BT power, since we're not using it and it
3406+ * draws power.
3407+ */
3408+#define OMAP1510_FPGA_RESET_VALUE 0x42
3409+
3410+#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3411+#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3412+#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3413+#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3414+#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3415+#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3416+#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3417+#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3418+
3419+/*
3420+ * Innovator/OMAP1510 FPGA HID register bit definitions
3421+ */
3422+#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3423+#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3424+#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3425+#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3426+#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3427+#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3428+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3429+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3430+
3431+/* The FPGA IRQ is cascaded through GPIO_13 */
3432+#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3433+
3434+/* IRQ Numbers for interrupts muxed through the FPGA */
3435+#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3436+#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3437+#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3438+#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3439+#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3440+#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3441+#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3442+#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3443+#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3444+#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3445+#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3446+#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3447+#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3448+#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3449+#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3450+#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3451+#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3452+#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3453+#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3454+#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3455+#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3456+#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3457+#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3458+#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3459+
3460+#endif
3461Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio.h
3462===================================================================
3463--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3464@@ -0,0 +1,129 @@
3465+/*
3466+ * arch/arm/plat-omap/include/mach/gpio.h
3467+ *
3468+ * OMAP GPIO handling defines and functions
3469+ *
3470+ * Copyright (C) 2003-2005 Nokia Corporation
3471+ *
3472+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3473+ *
3474+ * This program is free software; you can redistribute it and/or modify
3475+ * it under the terms of the GNU General Public License as published by
3476+ * the Free Software Foundation; either version 2 of the License, or
3477+ * (at your option) any later version.
3478+ *
3479+ * This program is distributed in the hope that it will be useful,
3480+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3481+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3482+ * GNU General Public License for more details.
3483+ *
3484+ * You should have received a copy of the GNU General Public License
3485+ * along with this program; if not, write to the Free Software
3486+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3487+ *
3488+ */
3489+
3490+#ifndef __ASM_ARCH_OMAP_GPIO_H
3491+#define __ASM_ARCH_OMAP_GPIO_H
3492+
3493+#include <linux/io.h>
3494+#include <mach/irqs.h>
3495+
3496+#define OMAP1_MPUIO_BASE 0xfffb5000
3497+
3498+#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3499+
3500+#define OMAP_MPUIO_INPUT_LATCH 0x00
3501+#define OMAP_MPUIO_OUTPUT 0x02
3502+#define OMAP_MPUIO_IO_CNTL 0x04
3503+#define OMAP_MPUIO_KBR_LATCH 0x08
3504+#define OMAP_MPUIO_KBC 0x0a
3505+#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3506+#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3507+#define OMAP_MPUIO_KBD_INT 0x10
3508+#define OMAP_MPUIO_GPIO_INT 0x12
3509+#define OMAP_MPUIO_KBD_MASKIT 0x14
3510+#define OMAP_MPUIO_GPIO_MASKIT 0x16
3511+#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3512+#define OMAP_MPUIO_LATCH 0x1a
3513+#else
3514+#define OMAP_MPUIO_INPUT_LATCH 0x00
3515+#define OMAP_MPUIO_OUTPUT 0x04
3516+#define OMAP_MPUIO_IO_CNTL 0x08
3517+#define OMAP_MPUIO_KBR_LATCH 0x10
3518+#define OMAP_MPUIO_KBC 0x14
3519+#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3520+#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3521+#define OMAP_MPUIO_KBD_INT 0x20
3522+#define OMAP_MPUIO_GPIO_INT 0x24
3523+#define OMAP_MPUIO_KBD_MASKIT 0x28
3524+#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3525+#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3526+#define OMAP_MPUIO_LATCH 0x34
3527+#endif
3528+
3529+#define OMAP34XX_NR_GPIOS 6
3530+
3531+#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3532+#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3533+
3534+#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3535+ IH_MPUIO_BASE + ((nr) & 0x0f) : \
3536+ IH_GPIO_BASE + (nr))
3537+
3538+extern int omap_gpio_init(void); /* Call from board init only */
3539+extern void omap2_gpio_prepare_for_retention(void);
3540+extern void omap2_gpio_resume_after_retention(void);
3541+extern void omap_set_gpio_debounce(int gpio, int enable);
3542+extern void omap_set_gpio_debounce_time(int gpio, int enable);
3543+extern void omap_gpio_save_context(void);
3544+extern void omap_gpio_restore_context(void);
3545+/*-------------------------------------------------------------------------*/
3546+
3547+/* Wrappers for "new style" GPIO calls, using the new infrastructure
3548+ * which lets us plug in FPGA, I2C, and other implementations.
3549+ * *
3550+ * The original OMAP-specfic calls should eventually be removed.
3551+ */
3552+
3553+#include <linux/errno.h>
3554+#include <asm-generic/gpio.h>
3555+
3556+static inline int gpio_get_value(unsigned gpio)
3557+{
3558+ return __gpio_get_value(gpio);
3559+}
3560+
3561+static inline void gpio_set_value(unsigned gpio, int value)
3562+{
3563+ __gpio_set_value(gpio, value);
3564+}
3565+
3566+static inline int gpio_cansleep(unsigned gpio)
3567+{
3568+ return __gpio_cansleep(gpio);
3569+}
3570+
3571+static inline int gpio_to_irq(unsigned gpio)
3572+{
3573+ return __gpio_to_irq(gpio);
3574+}
3575+
3576+static inline int irq_to_gpio(unsigned irq)
3577+{
3578+ int tmp;
3579+
3580+ /* omap1 SOC mpuio */
3581+ if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3582+ return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3583+
3584+ /* SOC gpio */
3585+ tmp = irq - IH_GPIO_BASE;
3586+ if (tmp < OMAP_MAX_GPIO_LINES)
3587+ return tmp;
3588+
3589+ /* we don't supply reverse mappings for non-SOC gpios */
3590+ return -EIO;
3591+}
3592+
3593+#endif
3594Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio-switch.h
3595===================================================================
3596--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3597@@ -0,0 +1,54 @@
3598+/*
3599+ * GPIO switch definitions
3600+ *
3601+ * Copyright (C) 2006 Nokia Corporation
3602+ *
3603+ * This program is free software; you can redistribute it and/or modify
3604+ * it under the terms of the GNU General Public License version 2 as
3605+ * published by the Free Software Foundation.
3606+ */
3607+
3608+#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3609+#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3610+
3611+#include <linux/types.h>
3612+
3613+/* Cover:
3614+ * high -> closed
3615+ * low -> open
3616+ * Connection:
3617+ * high -> connected
3618+ * low -> disconnected
3619+ * Activity:
3620+ * high -> active
3621+ * low -> inactive
3622+ *
3623+ */
3624+#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3625+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3626+#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3627+#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3628+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3629+
3630+struct omap_gpio_switch {
3631+ const char *name;
3632+ s16 gpio;
3633+ unsigned flags:4;
3634+ unsigned type:4;
3635+
3636+ /* Time in ms to debounce when transitioning from
3637+ * inactive state to active state. */
3638+ u16 debounce_rising;
3639+ /* Same for transition from active to inactive state. */
3640+ u16 debounce_falling;
3641+
3642+ /* notify board-specific code about state changes */
3643+ void (* notify)(void *data, int state);
3644+ void *notify_data;
3645+};
3646+
3647+/* Call at init time only */
3648+extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3649+ int count);
3650+
3651+#endif
3652Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc.h
3653===================================================================
3654--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3655@@ -0,0 +1,115 @@
3656+/*
3657+ * General-Purpose Memory Controller for OMAP2
3658+ *
3659+ * Copyright (C) 2005-2006 Nokia Corporation
3660+ *
3661+ * This program is free software; you can redistribute it and/or modify
3662+ * it under the terms of the GNU General Public License version 2 as
3663+ * published by the Free Software Foundation.
3664+ */
3665+
3666+#ifndef __OMAP2_GPMC_H
3667+#define __OMAP2_GPMC_H
3668+
3669+/* Maximum Number of Chip Selects */
3670+#define GPMC_CS_NUM 8
3671+
3672+#define GPMC_CS_CONFIG1 0x00
3673+#define GPMC_CS_CONFIG2 0x04
3674+#define GPMC_CS_CONFIG3 0x08
3675+#define GPMC_CS_CONFIG4 0x0c
3676+#define GPMC_CS_CONFIG5 0x10
3677+#define GPMC_CS_CONFIG6 0x14
3678+#define GPMC_CS_CONFIG7 0x18
3679+#define GPMC_CS_NAND_COMMAND 0x1c
3680+#define GPMC_CS_NAND_ADDRESS 0x20
3681+#define GPMC_CS_NAND_DATA 0x24
3682+
3683+#define GPMC_CONFIG 0x50
3684+#define GPMC_STATUS 0x54
3685+
3686+#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3687+#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3688+#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3689+#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3690+#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3691+#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3692+#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3693+#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3694+#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3695+#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3696+#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3697+#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3698+#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3699+#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3700+#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3701+#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3702+#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3703+#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3704+#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3705+#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3706+#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3707+#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3708+#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3709+#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3710+#define GPMC_CONFIG7_CSVALID (1 << 6)
3711+
3712+/*
3713+ * Note that all values in this struct are in nanoseconds, while
3714+ * the register values are in gpmc_fck cycles.
3715+ */
3716+struct gpmc_timings {
3717+ /* Minimum clock period for synchronous mode */
3718+ u16 sync_clk;
3719+
3720+ /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3721+ u16 cs_on; /* Assertion time */
3722+ u16 cs_rd_off; /* Read deassertion time */
3723+ u16 cs_wr_off; /* Write deassertion time */
3724+
3725+ /* ADV signal timings corresponding to GPMC_CONFIG3 */
3726+ u16 adv_on; /* Assertion time */
3727+ u16 adv_rd_off; /* Read deassertion time */
3728+ u16 adv_wr_off; /* Write deassertion time */
3729+
3730+ /* WE signals timings corresponding to GPMC_CONFIG4 */
3731+ u16 we_on; /* WE assertion time */
3732+ u16 we_off; /* WE deassertion time */
3733+
3734+ /* OE signals timings corresponding to GPMC_CONFIG4 */
3735+ u16 oe_on; /* OE assertion time */
3736+ u16 oe_off; /* OE deassertion time */
3737+
3738+ /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3739+ u16 page_burst_access; /* Multiple access word delay */
3740+ u16 access; /* Start-cycle to first data valid delay */
3741+ u16 rd_cycle; /* Total read cycle time */
3742+ u16 wr_cycle; /* Total write cycle time */
3743+
3744+ /* The following are only on OMAP3430 */
3745+ u16 wr_access; /* WRACCESSTIME */
3746+ u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3747+};
3748+
3749+extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3750+extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3751+extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3752+extern unsigned long gpmc_get_fclk_period(void);
3753+
3754+extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3755+extern u32 gpmc_cs_read_reg(int cs, int idx);
3756+extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3757+extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3758+extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3759+extern void gpmc_cs_free(int cs);
3760+extern int gpmc_cs_set_reserved(int cs, int reserved);
3761+extern int gpmc_cs_reserved(int cs);
3762+extern int gpmc_prefetch_enable(int cs, int dma_mode,
3763+ unsigned int u32_count, int is_write);
3764+extern void gpmc_prefetch_reset(void);
3765+extern int gpmc_prefetch_status(void);
3766+extern void omap3_gpmc_save_context(void);
3767+extern void omap3_gpmc_restore_context(void);
3768+extern void __init gpmc_init(void);
3769+
3770+#endif
3771Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3772===================================================================
3773--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3774@@ -0,0 +1,42 @@
3775+/*
3776+ * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3777+ *
3778+ * Copyright (C) 2009 Nokia Corporation
3779+ *
3780+ * This program is free software; you can redistribute it and/or modify
3781+ * it under the terms of the GNU General Public License version 2 as
3782+ * published by the Free Software Foundation.
3783+ */
3784+
3785+#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3786+
3787+#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3788+#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3789+#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3790+#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3791+
3792+struct omap_smc91x_platform_data {
3793+ int cs;
3794+ int gpio_irq;
3795+ int gpio_pwrdwn;
3796+ int gpio_reset;
3797+ int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3798+ u32 flags;
3799+ int (*retime)(void);
3800+};
3801+
3802+#if defined(CONFIG_SMC91X) || \
3803+ defined(CONFIG_SMC91X_MODULE)
3804+
3805+extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3806+
3807+#else
3808+
3809+#define board_smc91x_data NULL
3810+
3811+static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3812+{
3813+}
3814+
3815+#endif
3816+#endif
3817Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hardware.h
3818===================================================================
3819--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3820@@ -0,0 +1,290 @@
3821+/*
3822+ * arch/arm/plat-omap/include/mach/hardware.h
3823+ *
3824+ * Hardware definitions for TI OMAP processors and boards
3825+ *
3826+ * NOTE: Please put device driver specific defines into a separate header
3827+ * file for each driver.
3828+ *
3829+ * Copyright (C) 2001 RidgeRun, Inc.
3830+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3831+ *
3832+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3833+ * and Dirk Behme <dirk.behme@de.bosch.com>
3834+ *
3835+ * This program is free software; you can redistribute it and/or modify it
3836+ * under the terms of the GNU General Public License as published by the
3837+ * Free Software Foundation; either version 2 of the License, or (at your
3838+ * option) any later version.
3839+ *
3840+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3841+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3842+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3843+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3844+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3845+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3846+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3847+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3848+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3849+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3850+ *
3851+ * You should have received a copy of the GNU General Public License along
3852+ * with this program; if not, write to the Free Software Foundation, Inc.,
3853+ * 675 Mass Ave, Cambridge, MA 02139, USA.
3854+ */
3855+
3856+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3857+#define __ASM_ARCH_OMAP_HARDWARE_H
3858+
3859+#include <asm/sizes.h>
3860+#ifndef __ASSEMBLER__
3861+#include <asm/types.h>
3862+#include <plat/cpu.h>
3863+#endif
3864+#include <plat/serial.h>
3865+
3866+/*
3867+ * ---------------------------------------------------------------------------
3868+ * Common definitions for all OMAP processors
3869+ * NOTE: Put all processor or board specific parts to the special header
3870+ * files.
3871+ * ---------------------------------------------------------------------------
3872+ */
3873+
3874+/*
3875+ * ----------------------------------------------------------------------------
3876+ * Timers
3877+ * ----------------------------------------------------------------------------
3878+ */
3879+#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3880+#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3881+#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3882+#define MPU_TIMER_FREE (1 << 6)
3883+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
3884+#define MPU_TIMER_AR (1 << 1)
3885+#define MPU_TIMER_ST (1 << 0)
3886+
3887+/*
3888+ * ----------------------------------------------------------------------------
3889+ * Clocks
3890+ * ----------------------------------------------------------------------------
3891+ */
3892+#define CLKGEN_REG_BASE (0xfffece00)
3893+#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
3894+#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
3895+#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
3896+#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
3897+#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
3898+#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
3899+#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
3900+#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
3901+
3902+#define CK_RATEF 1
3903+#define CK_IDLEF 2
3904+#define CK_ENABLEF 4
3905+#define CK_SELECTF 8
3906+#define SETARM_IDLE_SHIFT
3907+
3908+/* DPLL control registers */
3909+#define DPLL_CTL (0xfffecf00)
3910+
3911+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
3912+#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
3913+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
3914+#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
3915+#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
3916+#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
3917+
3918+/*
3919+ * ---------------------------------------------------------------------------
3920+ * UPLD
3921+ * ---------------------------------------------------------------------------
3922+ */
3923+#define ULPD_REG_BASE (0xfffe0800)
3924+#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
3925+#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
3926+#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
3927+# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
3928+# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
3929+#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
3930+# define SOFT_UDC_REQ (1 << 4)
3931+# define SOFT_USB_CLK_REQ (1 << 3)
3932+# define SOFT_DPLL_REQ (1 << 0)
3933+#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
3934+#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
3935+#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
3936+#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
3937+#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
3938+# define DIS_MMC2_DPLL_REQ (1 << 11)
3939+# define DIS_MMC1_DPLL_REQ (1 << 10)
3940+# define DIS_UART3_DPLL_REQ (1 << 9)
3941+# define DIS_UART2_DPLL_REQ (1 << 8)
3942+# define DIS_UART1_DPLL_REQ (1 << 7)
3943+# define DIS_USB_HOST_DPLL_REQ (1 << 6)
3944+#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
3945+#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
3946+
3947+/*
3948+ * ---------------------------------------------------------------------------
3949+ * Watchdog timer
3950+ * ---------------------------------------------------------------------------
3951+ */
3952+
3953+/* Watchdog timer within the OMAP3.2 gigacell */
3954+#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
3955+#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
3956+#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3957+#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3958+#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
3959+
3960+/*
3961+ * ---------------------------------------------------------------------------
3962+ * Interrupts
3963+ * ---------------------------------------------------------------------------
3964+ */
3965+#ifdef CONFIG_ARCH_OMAP1
3966+
3967+/*
3968+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
3969+ * or something similar.. -- PFM.
3970+ */
3971+
3972+#define OMAP_IH1_BASE 0xfffecb00
3973+#define OMAP_IH2_BASE 0xfffe0000
3974+
3975+#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
3976+#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
3977+#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
3978+#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
3979+#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
3980+#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
3981+#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
3982+
3983+#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
3984+#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
3985+#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
3986+#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
3987+#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
3988+#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
3989+#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
3990+
3991+#define IRQ_ITR_REG_OFFSET 0x00
3992+#define IRQ_MIR_REG_OFFSET 0x04
3993+#define IRQ_SIR_IRQ_REG_OFFSET 0x10
3994+#define IRQ_SIR_FIQ_REG_OFFSET 0x14
3995+#define IRQ_CONTROL_REG_OFFSET 0x18
3996+#define IRQ_ISR_REG_OFFSET 0x9c
3997+#define IRQ_ILR0_REG_OFFSET 0x1c
3998+#define IRQ_GMR_REG_OFFSET 0xa0
3999+
4000+#endif
4001+
4002+/*
4003+ * ----------------------------------------------------------------------------
4004+ * System control registers
4005+ * ----------------------------------------------------------------------------
4006+ */
4007+#define MOD_CONF_CTRL_0 0xfffe1080
4008+#define MOD_CONF_CTRL_1 0xfffe1110
4009+
4010+/*
4011+ * ----------------------------------------------------------------------------
4012+ * Pin multiplexing registers
4013+ * ----------------------------------------------------------------------------
4014+ */
4015+#define FUNC_MUX_CTRL_0 0xfffe1000
4016+#define FUNC_MUX_CTRL_1 0xfffe1004
4017+#define FUNC_MUX_CTRL_2 0xfffe1008
4018+#define COMP_MODE_CTRL_0 0xfffe100c
4019+#define FUNC_MUX_CTRL_3 0xfffe1010
4020+#define FUNC_MUX_CTRL_4 0xfffe1014
4021+#define FUNC_MUX_CTRL_5 0xfffe1018
4022+#define FUNC_MUX_CTRL_6 0xfffe101C
4023+#define FUNC_MUX_CTRL_7 0xfffe1020
4024+#define FUNC_MUX_CTRL_8 0xfffe1024
4025+#define FUNC_MUX_CTRL_9 0xfffe1028
4026+#define FUNC_MUX_CTRL_A 0xfffe102C
4027+#define FUNC_MUX_CTRL_B 0xfffe1030
4028+#define FUNC_MUX_CTRL_C 0xfffe1034
4029+#define FUNC_MUX_CTRL_D 0xfffe1038
4030+#define PULL_DWN_CTRL_0 0xfffe1040
4031+#define PULL_DWN_CTRL_1 0xfffe1044
4032+#define PULL_DWN_CTRL_2 0xfffe1048
4033+#define PULL_DWN_CTRL_3 0xfffe104c
4034+#define PULL_DWN_CTRL_4 0xfffe10ac
4035+
4036+/* OMAP-1610 specific multiplexing registers */
4037+#define FUNC_MUX_CTRL_E 0xfffe1090
4038+#define FUNC_MUX_CTRL_F 0xfffe1094
4039+#define FUNC_MUX_CTRL_10 0xfffe1098
4040+#define FUNC_MUX_CTRL_11 0xfffe109c
4041+#define FUNC_MUX_CTRL_12 0xfffe10a0
4042+#define PU_PD_SEL_0 0xfffe10b4
4043+#define PU_PD_SEL_1 0xfffe10b8
4044+#define PU_PD_SEL_2 0xfffe10bc
4045+#define PU_PD_SEL_3 0xfffe10c0
4046+#define PU_PD_SEL_4 0xfffe10c4
4047+
4048+/* Timer32K for 1610 and 1710*/
4049+#define OMAP_TIMER32K_BASE 0xFFFBC400
4050+
4051+/*
4052+ * ---------------------------------------------------------------------------
4053+ * TIPB bus interface
4054+ * ---------------------------------------------------------------------------
4055+ */
4056+#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4057+#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4058+#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4059+#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4060+
4061+/*
4062+ * ----------------------------------------------------------------------------
4063+ * MPUI interface
4064+ * ----------------------------------------------------------------------------
4065+ */
4066+#define MPUI_BASE (0xfffec900)
4067+#define MPUI_CTRL (MPUI_BASE + 0x0)
4068+#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4069+#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4070+#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4071+#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4072+#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4073+#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4074+#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4075+
4076+/*
4077+ * ----------------------------------------------------------------------------
4078+ * LED Pulse Generator
4079+ * ----------------------------------------------------------------------------
4080+ */
4081+#define OMAP_LPG1_BASE 0xfffbd000
4082+#define OMAP_LPG2_BASE 0xfffbd800
4083+#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4084+#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4085+#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4086+#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4087+
4088+/*
4089+ * ----------------------------------------------------------------------------
4090+ * Pulse-Width Light
4091+ * ----------------------------------------------------------------------------
4092+ */
4093+#define OMAP_PWL_BASE 0xfffb5800
4094+#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4095+#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4096+
4097+/*
4098+ * ---------------------------------------------------------------------------
4099+ * Processor specific defines
4100+ * ---------------------------------------------------------------------------
4101+ */
4102+
4103+#include <plat/omap7xx.h>
4104+#include <plat/omap1510.h>
4105+#include <plat/omap16xx.h>
4106+#include <plat/omap24xx.h>
4107+#include <plat/omap34xx.h>
4108+#include <plat/omap44xx.h>
4109+
4110+#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4111Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hwa742.h
4112===================================================================
4113--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4114@@ -0,0 +1,8 @@
4115+#ifndef _HWA742_H
4116+#define _HWA742_H
4117+
4118+struct hwa742_platform_data {
4119+ unsigned te_connected:1;
4120+};
4121+
4122+#endif
4123Index: linux-2.6.35/arch/arm/plat-omap/include/mach/i2c.h
4124===================================================================
4125--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4126@@ -0,0 +1,39 @@
4127+/*
4128+ * Helper module for board specific I2C bus registration
4129+ *
4130+ * Copyright (C) 2009 Nokia Corporation.
4131+ *
4132+ * This program is free software; you can redistribute it and/or
4133+ * modify it under the terms of the GNU General Public License
4134+ * version 2 as published by the Free Software Foundation.
4135+ *
4136+ * This program is distributed in the hope that it will be useful, but
4137+ * WITHOUT ANY WARRANTY; without even the implied warranty of
4138+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4139+ * General Public License for more details.
4140+ *
4141+ * You should have received a copy of the GNU General Public License
4142+ * along with this program; if not, write to the Free Software
4143+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4144+ * 02110-1301 USA
4145+ *
4146+ */
4147+
4148+#include <linux/i2c.h>
4149+
4150+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4151+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4152+ struct i2c_board_info const *info,
4153+ unsigned len);
4154+#else
4155+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4156+ struct i2c_board_info const *info,
4157+ unsigned len)
4158+{
4159+ return 0;
4160+}
4161+#endif
4162+
4163+int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4164+ struct i2c_board_info const *info,
4165+ unsigned len);
4166Index: linux-2.6.35/arch/arm/plat-omap/include/mach/io.h
4167===================================================================
4168--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4169@@ -0,0 +1,287 @@
4170+/*
4171+ * arch/arm/plat-omap/include/mach/io.h
4172+ *
4173+ * IO definitions for TI OMAP processors and boards
4174+ *
4175+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
4176+ * Copyright (C) 1997-1999 Russell King
4177+ *
4178+ * Copyright (C) 2009 Texas Instruments
4179+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4180+ *
4181+ * This program is free software; you can redistribute it and/or modify it
4182+ * under the terms of the GNU General Public License as published by the
4183+ * Free Software Foundation; either version 2 of the License, or (at your
4184+ * option) any later version.
4185+ *
4186+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4187+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4188+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4189+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4190+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4191+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4192+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4193+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4194+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4195+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4196+ *
4197+ * You should have received a copy of the GNU General Public License along
4198+ * with this program; if not, write to the Free Software Foundation, Inc.,
4199+ * 675 Mass Ave, Cambridge, MA 02139, USA.
4200+ *
4201+ * Modifications:
4202+ * 06-12-1997 RMK Created.
4203+ * 07-04-1999 RMK Major cleanup
4204+ */
4205+
4206+#ifndef __ASM_ARM_ARCH_IO_H
4207+#define __ASM_ARM_ARCH_IO_H
4208+
4209+#include <mach/hardware.h>
4210+
4211+#define IO_SPACE_LIMIT 0xffffffff
4212+
4213+/*
4214+ * We don't actually have real ISA nor PCI buses, but there is so many
4215+ * drivers out there that might just work if we fake them...
4216+ */
4217+#define __io(a) __typesafe_io(a)
4218+#define __mem_pci(a) (a)
4219+
4220+/*
4221+ * ----------------------------------------------------------------------------
4222+ * I/O mapping
4223+ * ----------------------------------------------------------------------------
4224+ */
4225+
4226+#ifdef __ASSEMBLER__
4227+#define IOMEM(x) (x)
4228+#else
4229+#define IOMEM(x) ((void __force __iomem *)(x))
4230+#endif
4231+
4232+#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4233+#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4234+
4235+#define OMAP2_L3_IO_OFFSET 0x90000000
4236+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4237+
4238+
4239+#define OMAP2_L4_IO_OFFSET 0xb2000000
4240+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4241+
4242+#define OMAP4_L3_IO_OFFSET 0xb4000000
4243+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4244+
4245+#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4246+#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4247+
4248+#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4249+#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4250+
4251+#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4252+#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4253+
4254+/*
4255+ * ----------------------------------------------------------------------------
4256+ * Omap1 specific IO mapping
4257+ * ----------------------------------------------------------------------------
4258+ */
4259+
4260+#define OMAP1_IO_PHYS 0xFFFB0000
4261+#define OMAP1_IO_SIZE 0x40000
4262+#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4263+
4264+/*
4265+ * ----------------------------------------------------------------------------
4266+ * Omap2 specific IO mapping
4267+ * ----------------------------------------------------------------------------
4268+ */
4269+
4270+/* We map both L3 and L4 on OMAP2 */
4271+#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4272+#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4273+#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4274+#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4275+#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4276+#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4277+
4278+#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4279+#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4280+#define L4_WK_243X_SIZE SZ_1M
4281+#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4282+#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4283+ /* 0x6e000000 --> 0xfe000000 */
4284+#define OMAP243X_GPMC_SIZE SZ_1M
4285+#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4286+ /* 0x6D000000 --> 0xfd000000 */
4287+#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4288+#define OMAP243X_SDRC_SIZE SZ_1M
4289+#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4290+ /* 0x6c000000 --> 0xfc000000 */
4291+#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4292+#define OMAP243X_SMS_SIZE SZ_1M
4293+
4294+/* DSP */
4295+#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4296+#define DSP_MEM_24XX_VIRT 0xe0000000
4297+#define DSP_MEM_24XX_SIZE 0x28000
4298+#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4299+#define DSP_IPI_24XX_VIRT 0xe1000000
4300+#define DSP_IPI_24XX_SIZE SZ_4K
4301+#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4302+#define DSP_MMU_24XX_VIRT 0xe2000000
4303+#define DSP_MMU_24XX_SIZE SZ_4K
4304+
4305+/*
4306+ * ----------------------------------------------------------------------------
4307+ * Omap3 specific IO mapping
4308+ * ----------------------------------------------------------------------------
4309+ */
4310+
4311+/* We map both L3 and L4 on OMAP3 */
4312+#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4313+#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4314+#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4315+
4316+#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4317+#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4318+#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4319+
4320+/*
4321+ * Need to look at the Size 4M for L4.
4322+ * VPOM3430 was not working for Int controller
4323+ */
4324+
4325+#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4326+#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4327+#define L4_WK_34XX_SIZE SZ_1M
4328+
4329+#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4330+ /* 0x49000000 --> 0xfb000000 */
4331+#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4332+#define L4_PER_34XX_SIZE SZ_1M
4333+
4334+#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4335+ /* 0x54000000 --> 0xfe800000 */
4336+#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4337+#define L4_EMU_34XX_SIZE SZ_8M
4338+
4339+#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4340+ /* 0x6e000000 --> 0xfe000000 */
4341+#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4342+#define OMAP34XX_GPMC_SIZE SZ_1M
4343+
4344+#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4345+ /* 0x6c000000 --> 0xfc000000 */
4346+#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4347+#define OMAP343X_SMS_SIZE SZ_1M
4348+
4349+#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4350+ /* 0x6D000000 --> 0xfd000000 */
4351+#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4352+#define OMAP343X_SDRC_SIZE SZ_1M
4353+
4354+/* DSP */
4355+#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4356+#define DSP_MEM_34XX_VIRT 0xe0000000
4357+#define DSP_MEM_34XX_SIZE 0x28000
4358+#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4359+#define DSP_IPI_34XX_VIRT 0xe1000000
4360+#define DSP_IPI_34XX_SIZE SZ_4K
4361+#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4362+#define DSP_MMU_34XX_VIRT 0xe2000000
4363+#define DSP_MMU_34XX_SIZE SZ_4K
4364+
4365+/*
4366+ * ----------------------------------------------------------------------------
4367+ * Omap4 specific IO mapping
4368+ * ----------------------------------------------------------------------------
4369+ */
4370+
4371+/* We map both L3 and L4 on OMAP4 */
4372+#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4373+#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4374+#define L3_44XX_SIZE SZ_1M
4375+
4376+#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4377+#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4378+#define L4_44XX_SIZE SZ_4M
4379+
4380+
4381+#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4382+#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4383+#define L4_WK_44XX_SIZE SZ_1M
4384+
4385+#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4386+ /* 0x48000000 --> 0xfa000000 */
4387+#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4388+#define L4_PER_44XX_SIZE SZ_4M
4389+
4390+#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4391+ /* 0x49000000 --> 0xfb000000 */
4392+#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4393+#define L4_ABE_44XX_SIZE SZ_1M
4394+
4395+#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4396+ /* 0x54000000 --> 0xfe800000 */
4397+#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4398+#define L4_EMU_44XX_SIZE SZ_8M
4399+
4400+#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4401+ /* 0x50000000 --> 0xf9000000 */
4402+#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4403+#define OMAP44XX_GPMC_SIZE SZ_1M
4404+
4405+
4406+#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4407+ /* 0x4c000000 --> 0xfd100000 */
4408+#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4409+#define OMAP44XX_EMIF1_SIZE SZ_1M
4410+
4411+#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4412+ /* 0x4d000000 --> 0xfd200000 */
4413+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4414+#define OMAP44XX_EMIF2_SIZE SZ_1M
4415+
4416+#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4417+ /* 0x4e000000 --> 0xfd300000 */
4418+#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4419+#define OMAP44XX_DMM_SIZE SZ_1M
4420+/*
4421+ * ----------------------------------------------------------------------------
4422+ * Omap specific register access
4423+ * ----------------------------------------------------------------------------
4424+ */
4425+
4426+#ifndef __ASSEMBLER__
4427+
4428+/*
4429+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4430+ */
4431+
4432+extern u8 omap_readb(u32 pa);
4433+extern u16 omap_readw(u32 pa);
4434+extern u32 omap_readl(u32 pa);
4435+extern void omap_writeb(u8 v, u32 pa);
4436+extern void omap_writew(u16 v, u32 pa);
4437+extern void omap_writel(u32 v, u32 pa);
4438+
4439+struct omap_sdrc_params;
4440+
4441+extern void omap1_map_common_io(void);
4442+extern void omap1_init_common_hw(void);
4443+
4444+extern void omap2_map_common_io(void);
4445+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4446+ struct omap_sdrc_params *sdrc_cs1);
4447+
4448+#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4449+#define __arch_iounmap(v) omap_iounmap(v)
4450+
4451+void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4452+void omap_iounmap(volatile void __iomem *addr);
4453+
4454+#endif
4455+
4456+#endif
4457Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu2.h
4458===================================================================
4459--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4460@@ -0,0 +1,96 @@
4461+/*
4462+ * omap iommu: omap2 architecture specific definitions
4463+ *
4464+ * Copyright (C) 2008-2009 Nokia Corporation
4465+ *
4466+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4467+ *
4468+ * This program is free software; you can redistribute it and/or modify
4469+ * it under the terms of the GNU General Public License version 2 as
4470+ * published by the Free Software Foundation.
4471+ */
4472+
4473+#ifndef __MACH_IOMMU2_H
4474+#define __MACH_IOMMU2_H
4475+
4476+#include <linux/io.h>
4477+
4478+/*
4479+ * MMU Register offsets
4480+ */
4481+#define MMU_REVISION 0x00
4482+#define MMU_SYSCONFIG 0x10
4483+#define MMU_SYSSTATUS 0x14
4484+#define MMU_IRQSTATUS 0x18
4485+#define MMU_IRQENABLE 0x1c
4486+#define MMU_WALKING_ST 0x40
4487+#define MMU_CNTL 0x44
4488+#define MMU_FAULT_AD 0x48
4489+#define MMU_TTB 0x4c
4490+#define MMU_LOCK 0x50
4491+#define MMU_LD_TLB 0x54
4492+#define MMU_CAM 0x58
4493+#define MMU_RAM 0x5c
4494+#define MMU_GFLUSH 0x60
4495+#define MMU_FLUSH_ENTRY 0x64
4496+#define MMU_READ_CAM 0x68
4497+#define MMU_READ_RAM 0x6c
4498+#define MMU_EMU_FAULT_AD 0x70
4499+
4500+#define MMU_REG_SIZE 256
4501+
4502+/*
4503+ * MMU Register bit definitions
4504+ */
4505+#define MMU_LOCK_BASE_SHIFT 10
4506+#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4507+#define MMU_LOCK_BASE(x) \
4508+ ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4509+
4510+#define MMU_LOCK_VICT_SHIFT 4
4511+#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4512+#define MMU_LOCK_VICT(x) \
4513+ ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4514+
4515+#define MMU_CAM_VATAG_SHIFT 12
4516+#define MMU_CAM_VATAG_MASK \
4517+ ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4518+#define MMU_CAM_P (1 << 3)
4519+#define MMU_CAM_V (1 << 2)
4520+#define MMU_CAM_PGSZ_MASK 3
4521+#define MMU_CAM_PGSZ_1M (0 << 0)
4522+#define MMU_CAM_PGSZ_64K (1 << 0)
4523+#define MMU_CAM_PGSZ_4K (2 << 0)
4524+#define MMU_CAM_PGSZ_16M (3 << 0)
4525+
4526+#define MMU_RAM_PADDR_SHIFT 12
4527+#define MMU_RAM_PADDR_MASK \
4528+ ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4529+#define MMU_RAM_ENDIAN_SHIFT 9
4530+#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4531+#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4532+#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4533+#define MMU_RAM_ELSZ_SHIFT 7
4534+#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4535+#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4536+#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4537+#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4538+#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4539+#define MMU_RAM_MIXED_SHIFT 6
4540+#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4541+#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4542+
4543+/*
4544+ * register accessors
4545+ */
4546+static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4547+{
4548+ return __raw_readl(obj->regbase + offs);
4549+}
4550+
4551+static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4552+{
4553+ __raw_writel(val, obj->regbase + offs);
4554+}
4555+
4556+#endif /* __MACH_IOMMU2_H */
4557Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu.h
4558===================================================================
4559--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4560@@ -0,0 +1,168 @@
4561+/*
4562+ * omap iommu: main structures
4563+ *
4564+ * Copyright (C) 2008-2009 Nokia Corporation
4565+ *
4566+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4567+ *
4568+ * This program is free software; you can redistribute it and/or modify
4569+ * it under the terms of the GNU General Public License version 2 as
4570+ * published by the Free Software Foundation.
4571+ */
4572+
4573+#ifndef __MACH_IOMMU_H
4574+#define __MACH_IOMMU_H
4575+
4576+struct iotlb_entry {
4577+ u32 da;
4578+ u32 pa;
4579+ u32 pgsz, prsvd, valid;
4580+ union {
4581+ u16 ap;
4582+ struct {
4583+ u32 endian, elsz, mixed;
4584+ };
4585+ };
4586+};
4587+
4588+struct iommu {
4589+ const char *name;
4590+ struct module *owner;
4591+ struct clk *clk;
4592+ void __iomem *regbase;
4593+ struct device *dev;
4594+
4595+ unsigned int refcount;
4596+ struct mutex iommu_lock; /* global for this whole object */
4597+
4598+ /*
4599+ * We don't change iopgd for a situation like pgd for a task,
4600+ * but share it globally for each iommu.
4601+ */
4602+ u32 *iopgd;
4603+ spinlock_t page_table_lock; /* protect iopgd */
4604+
4605+ int nr_tlb_entries;
4606+
4607+ struct list_head mmap;
4608+ struct mutex mmap_lock; /* protect mmap */
4609+
4610+ int (*isr)(struct iommu *obj);
4611+
4612+ void *ctx; /* iommu context: registres saved area */
4613+};
4614+
4615+struct cr_regs {
4616+ union {
4617+ struct {
4618+ u16 cam_l;
4619+ u16 cam_h;
4620+ };
4621+ u32 cam;
4622+ };
4623+ union {
4624+ struct {
4625+ u16 ram_l;
4626+ u16 ram_h;
4627+ };
4628+ u32 ram;
4629+ };
4630+};
4631+
4632+struct iotlb_lock {
4633+ short base;
4634+ short vict;
4635+};
4636+
4637+/* architecture specific functions */
4638+struct iommu_functions {
4639+ unsigned long version;
4640+
4641+ int (*enable)(struct iommu *obj);
4642+ void (*disable)(struct iommu *obj);
4643+ u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4644+
4645+ void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4646+ void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4647+
4648+ struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4649+ int (*cr_valid)(struct cr_regs *cr);
4650+ u32 (*cr_to_virt)(struct cr_regs *cr);
4651+ void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4652+ ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4653+
4654+ u32 (*get_pte_attr)(struct iotlb_entry *e);
4655+
4656+ void (*save_ctx)(struct iommu *obj);
4657+ void (*restore_ctx)(struct iommu *obj);
4658+ ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4659+};
4660+
4661+struct iommu_platform_data {
4662+ const char *name;
4663+ const char *clk_name;
4664+ const int nr_tlb_entries;
4665+};
4666+
4667+#if defined(CONFIG_ARCH_OMAP1)
4668+#error "iommu for this processor not implemented yet"
4669+#else
4670+#include <plat/iommu2.h>
4671+#endif
4672+
4673+/*
4674+ * utilities for super page(16MB, 1MB, 64KB and 4KB)
4675+ */
4676+
4677+#define iopgsz_max(bytes) \
4678+ (((bytes) >= SZ_16M) ? SZ_16M : \
4679+ ((bytes) >= SZ_1M) ? SZ_1M : \
4680+ ((bytes) >= SZ_64K) ? SZ_64K : \
4681+ ((bytes) >= SZ_4K) ? SZ_4K : 0)
4682+
4683+#define bytes_to_iopgsz(bytes) \
4684+ (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4685+ ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4686+ ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4687+ ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4688+
4689+#define iopgsz_to_bytes(iopgsz) \
4690+ (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4691+ ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4692+ ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4693+ ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4694+
4695+#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4696+
4697+/*
4698+ * global functions
4699+ */
4700+extern u32 iommu_arch_version(void);
4701+
4702+extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4703+extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4704+
4705+extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4706+extern void flush_iotlb_page(struct iommu *obj, u32 da);
4707+extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4708+extern void flush_iotlb_all(struct iommu *obj);
4709+
4710+extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4711+extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4712+
4713+extern struct iommu *iommu_get(const char *name);
4714+extern void iommu_put(struct iommu *obj);
4715+
4716+extern void iommu_save_ctx(struct iommu *obj);
4717+extern void iommu_restore_ctx(struct iommu *obj);
4718+
4719+extern int install_iommu_arch(const struct iommu_functions *ops);
4720+extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4721+
4722+extern int foreach_iommu_device(void *data,
4723+ int (*fn)(struct device *, void *));
4724+
4725+extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4726+extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4727+
4728+#endif /* __MACH_IOMMU_H */
4729Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iovmm.h
4730===================================================================
4731--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4732@@ -0,0 +1,94 @@
4733+/*
4734+ * omap iommu: simple virtual address space management
4735+ *
4736+ * Copyright (C) 2008-2009 Nokia Corporation
4737+ *
4738+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4739+ *
4740+ * This program is free software; you can redistribute it and/or modify
4741+ * it under the terms of the GNU General Public License version 2 as
4742+ * published by the Free Software Foundation.
4743+ */
4744+
4745+#ifndef __IOMMU_MMAP_H
4746+#define __IOMMU_MMAP_H
4747+
4748+struct iovm_struct {
4749+ struct iommu *iommu; /* iommu object which this belongs to */
4750+ u32 da_start; /* area definition */
4751+ u32 da_end;
4752+ u32 flags; /* IOVMF_: see below */
4753+ struct list_head list; /* linked in ascending order */
4754+ const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4755+ void *va; /* mpu side mapped address */
4756+};
4757+
4758+/*
4759+ * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4760+ *
4761+ * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4762+ */
4763+#define IOVMF_SW_SHIFT 16
4764+#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4765+#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4766+#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4767+
4768+/*
4769+ * iovma: h/w flags derived from cam and ram attribute
4770+ */
4771+#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4772+#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4773+
4774+#define IOVMF_PGSZ_MASK (3 << 0)
4775+#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4776+#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4777+#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4778+#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4779+
4780+#define IOVMF_ENDIAN_MASK (1 << 9)
4781+#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4782+#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4783+
4784+#define IOVMF_ELSZ_MASK (3 << 7)
4785+#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4786+#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4787+#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4788+#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4789+
4790+#define IOVMF_MIXED_MASK (1 << 6)
4791+#define IOVMF_MIXED MMU_RAM_MIXED
4792+
4793+/*
4794+ * iovma: s/w flags, used for mapping and umapping internally.
4795+ */
4796+#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4797+#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4798+#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4799+
4800+/* "superpages" is supported just with physically linear pages */
4801+#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4802+#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4803+#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4804+
4805+#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4806+#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4807+#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4808+
4809+
4810+extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4811+extern u32 iommu_vmap(struct iommu *obj, u32 da,
4812+ const struct sg_table *sgt, u32 flags);
4813+extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4814+extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4815+ u32 flags);
4816+extern void iommu_vfree(struct iommu *obj, const u32 da);
4817+extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4818+ u32 flags);
4819+extern void iommu_kunmap(struct iommu *obj, u32 da);
4820+extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4821+ u32 flags);
4822+extern void iommu_kfree(struct iommu *obj, u32 da);
4823+
4824+extern void *da_to_va(struct iommu *obj, u32 da);
4825+
4826+#endif /* __IOMMU_MMAP_H */
4827Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irda.h
4828===================================================================
4829--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4830@@ -0,0 +1,33 @@
4831+/*
4832+ * arch/arm/plat-omap/include/mach/irda.h
4833+ *
4834+ * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4835+ *
4836+ * This program is free software; you can redistribute it and/or modify
4837+ * it under the terms of the GNU General Public License version 2 as
4838+ * published by the Free Software Foundation.
4839+ */
4840+#ifndef ASMARM_ARCH_IRDA_H
4841+#define ASMARM_ARCH_IRDA_H
4842+
4843+/* board specific transceiver capabilities */
4844+
4845+#define IR_SEL 1 /* Selects IrDA */
4846+#define IR_SIRMODE 2
4847+#define IR_FIRMODE 4
4848+#define IR_MIRMODE 8
4849+
4850+struct omap_irda_config {
4851+ int transceiver_cap;
4852+ int (*transceiver_mode)(struct device *dev, int mode);
4853+ int (*select_irda)(struct device *dev, int state);
4854+ int rx_channel;
4855+ int tx_channel;
4856+ unsigned long dest_start;
4857+ unsigned long src_start;
4858+ int tx_trigger;
4859+ int rx_trigger;
4860+ int mode;
4861+};
4862+
4863+#endif
4864Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irqs.h
4865===================================================================
4866--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4867@@ -0,0 +1,506 @@
4868+/*
4869+ * arch/arm/plat-omap/include/mach/irqs.h
4870+ *
4871+ * Copyright (C) Greg Lonnon 2001
4872+ * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4873+ *
4874+ * Copyright (C) 2009 Texas Instruments
4875+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4876+ *
4877+ * This program is free software; you can redistribute it and/or modify
4878+ * it under the terms of the GNU General Public License as published by
4879+ * the Free Software Foundation; either version 2 of the License, or
4880+ * (at your option) any later version.
4881+ *
4882+ * This program is distributed in the hope that it will be useful,
4883+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4884+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4885+ * GNU General Public License for more details.
4886+ *
4887+ * You should have received a copy of the GNU General Public License
4888+ * along with this program; if not, write to the Free Software
4889+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4890+ *
4891+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
4892+ * are different.
4893+ */
4894+
4895+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
4896+#define __ASM_ARCH_OMAP15XX_IRQS_H
4897+
4898+/*
4899+ * IRQ numbers for interrupt handler 1
4900+ *
4901+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4902+ *
4903+ */
4904+#define INT_CAMERA 1
4905+#define INT_FIQ 3
4906+#define INT_RTDX 6
4907+#define INT_DSP_MMU_ABORT 7
4908+#define INT_HOST 8
4909+#define INT_ABORT 9
4910+#define INT_BRIDGE_PRIV 13
4911+#define INT_GPIO_BANK1 14
4912+#define INT_UART3 15
4913+#define INT_TIMER3 16
4914+#define INT_DMA_CH0_6 19
4915+#define INT_DMA_CH1_7 20
4916+#define INT_DMA_CH2_8 21
4917+#define INT_DMA_CH3 22
4918+#define INT_DMA_CH4 23
4919+#define INT_DMA_CH5 24
4920+#define INT_DMA_LCD 25
4921+#define INT_TIMER1 26
4922+#define INT_WD_TIMER 27
4923+#define INT_BRIDGE_PUB 28
4924+#define INT_TIMER2 30
4925+#define INT_LCD_CTRL 31
4926+
4927+/*
4928+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
4929+ */
4930+#define INT_1510_IH2_IRQ 0
4931+#define INT_1510_RES2 2
4932+#define INT_1510_SPI_TX 4
4933+#define INT_1510_SPI_RX 5
4934+#define INT_1510_DSP_MAILBOX1 10
4935+#define INT_1510_DSP_MAILBOX2 11
4936+#define INT_1510_RES12 12
4937+#define INT_1510_LB_MMU 17
4938+#define INT_1510_RES18 18
4939+#define INT_1510_LOCAL_BUS 29
4940+
4941+/*
4942+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
4943+ */
4944+#define INT_1610_IH2_IRQ 0
4945+#define INT_1610_IH2_FIQ 2
4946+#define INT_1610_McBSP2_TX 4
4947+#define INT_1610_McBSP2_RX 5
4948+#define INT_1610_DSP_MAILBOX1 10
4949+#define INT_1610_DSP_MAILBOX2 11
4950+#define INT_1610_LCD_LINE 12
4951+#define INT_1610_GPTIMER1 17
4952+#define INT_1610_GPTIMER2 18
4953+#define INT_1610_SSR_FIFO_0 29
4954+
4955+/*
4956+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
4957+ */
4958+#define INT_7XX_IH2_FIQ 0
4959+#define INT_7XX_IH2_IRQ 1
4960+#define INT_7XX_USB_NON_ISO 2
4961+#define INT_7XX_USB_ISO 3
4962+#define INT_7XX_ICR 4
4963+#define INT_7XX_EAC 5
4964+#define INT_7XX_GPIO_BANK1 6
4965+#define INT_7XX_GPIO_BANK2 7
4966+#define INT_7XX_GPIO_BANK3 8
4967+#define INT_7XX_McBSP2TX 10
4968+#define INT_7XX_McBSP2RX 11
4969+#define INT_7XX_McBSP2RX_OVF 12
4970+#define INT_7XX_LCD_LINE 14
4971+#define INT_7XX_GSM_PROTECT 15
4972+#define INT_7XX_TIMER3 16
4973+#define INT_7XX_GPIO_BANK5 17
4974+#define INT_7XX_GPIO_BANK6 18
4975+#define INT_7XX_SPGIO_WR 29
4976+
4977+/*
4978+ * IRQ numbers for interrupt handler 2
4979+ *
4980+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4981+ */
4982+#define IH2_BASE 32
4983+
4984+#define INT_KEYBOARD (1 + IH2_BASE)
4985+#define INT_uWireTX (2 + IH2_BASE)
4986+#define INT_uWireRX (3 + IH2_BASE)
4987+#define INT_I2C (4 + IH2_BASE)
4988+#define INT_MPUIO (5 + IH2_BASE)
4989+#define INT_USB_HHC_1 (6 + IH2_BASE)
4990+#define INT_McBSP3TX (10 + IH2_BASE)
4991+#define INT_McBSP3RX (11 + IH2_BASE)
4992+#define INT_McBSP1TX (12 + IH2_BASE)
4993+#define INT_McBSP1RX (13 + IH2_BASE)
4994+#define INT_UART1 (14 + IH2_BASE)
4995+#define INT_UART2 (15 + IH2_BASE)
4996+#define INT_BT_MCSI1TX (16 + IH2_BASE)
4997+#define INT_BT_MCSI1RX (17 + IH2_BASE)
4998+#define INT_SOSSI_MATCH (19 + IH2_BASE)
4999+#define INT_USB_W2FC (20 + IH2_BASE)
5000+#define INT_1WIRE (21 + IH2_BASE)
5001+#define INT_OS_TIMER (22 + IH2_BASE)
5002+#define INT_MMC (23 + IH2_BASE)
5003+#define INT_GAUGE_32K (24 + IH2_BASE)
5004+#define INT_RTC_TIMER (25 + IH2_BASE)
5005+#define INT_RTC_ALARM (26 + IH2_BASE)
5006+#define INT_MEM_STICK (27 + IH2_BASE)
5007+
5008+/*
5009+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
5010+ */
5011+#define INT_1510_DSP_MMU (28 + IH2_BASE)
5012+#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5013+
5014+/*
5015+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
5016+ */
5017+#define INT_1610_FAC (0 + IH2_BASE)
5018+#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5019+#define INT_1610_USB_OTG (8 + IH2_BASE)
5020+#define INT_1610_SoSSI (9 + IH2_BASE)
5021+#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5022+#define INT_1610_DSP_MMU (28 + IH2_BASE)
5023+#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5024+#define INT_1610_STI (32 + IH2_BASE)
5025+#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5026+#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5027+#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5028+#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5029+#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5030+#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5031+#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5032+#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5033+#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5034+#define INT_1610_MMC2 (42 + IH2_BASE)
5035+#define INT_1610_CF (43 + IH2_BASE)
5036+#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5037+#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5038+#define INT_1610_SPI (49 + IH2_BASE)
5039+#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5040+#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5041+#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5042+#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5043+#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5044+#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5045+#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5046+#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5047+#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5048+#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5049+#define INT_1610_NAND (63 + IH2_BASE)
5050+#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5051+
5052+/*
5053+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
5054+ */
5055+#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5056+#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5057+#define INT_7XX_CFCD (2 + IH2_BASE)
5058+#define INT_7XX_CFIREQ (3 + IH2_BASE)
5059+#define INT_7XX_I2C (4 + IH2_BASE)
5060+#define INT_7XX_PCC (5 + IH2_BASE)
5061+#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5062+#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5063+#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5064+#define INT_7XX_VLYNQ (9 + IH2_BASE)
5065+#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5066+#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5067+#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5068+#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5069+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5070+#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5071+#define INT_7XX_MCSI (16 + IH2_BASE)
5072+#define INT_7XX_uWireTX (17 + IH2_BASE)
5073+#define INT_7XX_uWireRX (18 + IH2_BASE)
5074+#define INT_7XX_SMC_CD (19 + IH2_BASE)
5075+#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5076+#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5077+#define INT_7XX_TIMER32K (22 + IH2_BASE)
5078+#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5079+#define INT_7XX_UPLD (24 + IH2_BASE)
5080+#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5081+#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5082+#define INT_7XX_USB_GENI (29 + IH2_BASE)
5083+#define INT_7XX_USB_OTG (30 + IH2_BASE)
5084+#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5085+#define INT_7XX_RNG (32 + IH2_BASE)
5086+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5087+#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5088+#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5089+#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5090+#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5091+#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5092+#define INT_7XX_MPUIO (39 + IH2_BASE)
5093+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5094+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5095+#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5096+#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5097+#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5098+#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5099+#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5100+#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5101+#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5102+#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5103+#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5104+#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5105+#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5106+#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5107+#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5108+#define INT_7XX_NAND (63 + IH2_BASE)
5109+
5110+#define INT_24XX_SYS_NIRQ 7
5111+#define INT_24XX_SDMA_IRQ0 12
5112+#define INT_24XX_SDMA_IRQ1 13
5113+#define INT_24XX_SDMA_IRQ2 14
5114+#define INT_24XX_SDMA_IRQ3 15
5115+#define INT_24XX_CAM_IRQ 24
5116+#define INT_24XX_DSS_IRQ 25
5117+#define INT_24XX_MAIL_U0_MPU 26
5118+#define INT_24XX_DSP_UMA 27
5119+#define INT_24XX_DSP_MMU 28
5120+#define INT_24XX_GPIO_BANK1 29
5121+#define INT_24XX_GPIO_BANK2 30
5122+#define INT_24XX_GPIO_BANK3 31
5123+#define INT_24XX_GPIO_BANK4 32
5124+#define INT_24XX_GPIO_BANK5 33
5125+#define INT_24XX_MAIL_U3_MPU 34
5126+#define INT_24XX_GPTIMER1 37
5127+#define INT_24XX_GPTIMER2 38
5128+#define INT_24XX_GPTIMER3 39
5129+#define INT_24XX_GPTIMER4 40
5130+#define INT_24XX_GPTIMER5 41
5131+#define INT_24XX_GPTIMER6 42
5132+#define INT_24XX_GPTIMER7 43
5133+#define INT_24XX_GPTIMER8 44
5134+#define INT_24XX_GPTIMER9 45
5135+#define INT_24XX_GPTIMER10 46
5136+#define INT_24XX_GPTIMER11 47
5137+#define INT_24XX_GPTIMER12 48
5138+#define INT_24XX_SHA1MD5 51
5139+#define INT_24XX_MCBSP4_IRQ_TX 54
5140+#define INT_24XX_MCBSP4_IRQ_RX 55
5141+#define INT_24XX_I2C1_IRQ 56
5142+#define INT_24XX_I2C2_IRQ 57
5143+#define INT_24XX_HDQ_IRQ 58
5144+#define INT_24XX_MCBSP1_IRQ_TX 59
5145+#define INT_24XX_MCBSP1_IRQ_RX 60
5146+#define INT_24XX_MCBSP2_IRQ_TX 62
5147+#define INT_24XX_MCBSP2_IRQ_RX 63
5148+#define INT_24XX_SPI1_IRQ 65
5149+#define INT_24XX_SPI2_IRQ 66
5150+#define INT_24XX_UART1_IRQ 72
5151+#define INT_24XX_UART2_IRQ 73
5152+#define INT_24XX_UART3_IRQ 74
5153+#define INT_24XX_USB_IRQ_GEN 75
5154+#define INT_24XX_USB_IRQ_NISO 76
5155+#define INT_24XX_USB_IRQ_ISO 77
5156+#define INT_24XX_USB_IRQ_HGEN 78
5157+#define INT_24XX_USB_IRQ_HSOF 79
5158+#define INT_24XX_USB_IRQ_OTG 80
5159+#define INT_24XX_MCBSP5_IRQ_TX 81
5160+#define INT_24XX_MCBSP5_IRQ_RX 82
5161+#define INT_24XX_MMC_IRQ 83
5162+#define INT_24XX_MMC2_IRQ 86
5163+#define INT_24XX_MCBSP3_IRQ_TX 89
5164+#define INT_24XX_MCBSP3_IRQ_RX 90
5165+#define INT_24XX_SPI3_IRQ 91
5166+
5167+#define INT_243X_MCBSP2_IRQ 16
5168+#define INT_243X_MCBSP3_IRQ 17
5169+#define INT_243X_MCBSP4_IRQ 18
5170+#define INT_243X_MCBSP5_IRQ 19
5171+#define INT_243X_MCBSP1_IRQ 64
5172+#define INT_243X_HS_USB_MC 92
5173+#define INT_243X_HS_USB_DMA 93
5174+#define INT_243X_CARKIT_IRQ 94
5175+
5176+#define INT_34XX_BENCH_MPU_EMUL 3
5177+#define INT_34XX_ST_MCBSP2_IRQ 4
5178+#define INT_34XX_ST_MCBSP3_IRQ 5
5179+#define INT_34XX_SSM_ABORT_IRQ 6
5180+#define INT_34XX_SYS_NIRQ 7
5181+#define INT_34XX_D2D_FW_IRQ 8
5182+#define INT_34XX_PRCM_MPU_IRQ 11
5183+#define INT_34XX_MCBSP1_IRQ 16
5184+#define INT_34XX_MCBSP2_IRQ 17
5185+#define INT_34XX_MCBSP3_IRQ 22
5186+#define INT_34XX_MCBSP4_IRQ 23
5187+#define INT_34XX_CAM_IRQ 24
5188+#define INT_34XX_MCBSP5_IRQ 27
5189+#define INT_34XX_GPIO_BANK1 29
5190+#define INT_34XX_GPIO_BANK2 30
5191+#define INT_34XX_GPIO_BANK3 31
5192+#define INT_34XX_GPIO_BANK4 32
5193+#define INT_34XX_GPIO_BANK5 33
5194+#define INT_34XX_GPIO_BANK6 34
5195+#define INT_34XX_USIM_IRQ 35
5196+#define INT_34XX_WDT3_IRQ 36
5197+#define INT_34XX_SPI4_IRQ 48
5198+#define INT_34XX_SHA1MD52_IRQ 49
5199+#define INT_34XX_FPKA_READY_IRQ 50
5200+#define INT_34XX_SHA1MD51_IRQ 51
5201+#define INT_34XX_RNG_IRQ 52
5202+#define INT_34XX_I2C3_IRQ 61
5203+#define INT_34XX_FPKA_ERROR_IRQ 64
5204+#define INT_34XX_PBIAS_IRQ 75
5205+#define INT_34XX_OHCI_IRQ 76
5206+#define INT_34XX_EHCI_IRQ 77
5207+#define INT_34XX_TLL_IRQ 78
5208+#define INT_34XX_PARTHASH_IRQ 79
5209+#define INT_34XX_MMC3_IRQ 94
5210+#define INT_34XX_GPT12_IRQ 95
5211+
5212+#define INT_34XX_BENCH_MPU_EMUL 3
5213+
5214+
5215+#define IRQ_GIC_START 32
5216+#define INT_44XX_LOCALTIMER_IRQ 29
5217+#define INT_44XX_LOCALWDT_IRQ 30
5218+
5219+#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5220+#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5221+#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5222+#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5223+#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5224+#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5225+#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5226+#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5227+#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5228+#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5229+#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5230+#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5231+#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5232+#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5233+#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5234+#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5235+#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5236+#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5237+#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5238+#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5239+#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5240+#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5241+#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5242+#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5243+#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5244+#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5245+#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5246+#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5247+#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5248+#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5249+#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5250+#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5251+#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5252+#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5253+#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5254+#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5255+#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5256+#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5257+#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5258+#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5259+#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5260+#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5261+#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5262+#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5263+#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5264+#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5265+#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5266+#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5267+#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5268+#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5269+#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5270+
5271+#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5272+#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5273+#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5274+#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5275+#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5276+#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5277+#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5278+
5279+#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5280+#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5281+#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5282+#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5283+#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5284+#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5285+#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5286+#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5287+#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5288+#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5289+#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5290+#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5291+#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5292+#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5293+#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5294+#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5295+#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5296+#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5297+#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5298+#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5299+#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5300+#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5301+#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5302+
5303+
5304+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5305+ * 16 MPUIO lines */
5306+#define OMAP_MAX_GPIO_LINES 192
5307+#define IH_GPIO_BASE (128 + IH2_BASE)
5308+#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5309+#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5310+
5311+/* External FPGA handles interrupts on Innovator boards */
5312+#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5313+#ifdef CONFIG_MACH_OMAP_INNOVATOR
5314+#define OMAP_FPGA_NR_IRQS 24
5315+#else
5316+#define OMAP_FPGA_NR_IRQS 0
5317+#endif
5318+#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5319+
5320+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5321+#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5322+#ifdef CONFIG_TWL4030_CORE
5323+#define TWL4030_BASE_NR_IRQS 8
5324+#define TWL4030_PWR_NR_IRQS 8
5325+#else
5326+#define TWL4030_BASE_NR_IRQS 0
5327+#define TWL4030_PWR_NR_IRQS 0
5328+#endif
5329+#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5330+#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5331+#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5332+
5333+/* External TWL4030 gpio interrupts are optional */
5334+#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5335+#ifdef CONFIG_GPIO_TWL4030
5336+#define TWL4030_GPIO_NR_IRQS 18
5337+#else
5338+#define TWL4030_GPIO_NR_IRQS 0
5339+#endif
5340+#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5341+
5342+#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5343+#ifdef CONFIG_TWL4030_CORE
5344+#define TWL6030_BASE_NR_IRQS 20
5345+#else
5346+#define TWL6030_BASE_NR_IRQS 0
5347+#endif
5348+#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5349+
5350+/* Total number of interrupts depends on the enabled blocks above */
5351+#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5352+#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5353+#else
5354+#define TWL_IRQ_END TWL6030_IRQ_END
5355+#endif
5356+
5357+#define NR_IRQS TWL_IRQ_END
5358+
5359+#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5360+
5361+#define INTCPS_NR_MIR_REGS 3
5362+#define INTCPS_NR_IRQS 96
5363+
5364+#ifndef __ASSEMBLY__
5365+extern void omap_init_irq(void);
5366+extern int omap_irq_pending(void);
5367+void omap_intc_save_context(void);
5368+void omap_intc_restore_context(void);
5369+#endif
5370+
5371+#include <mach/hardware.h>
5372+
5373+#endif
5374Index: linux-2.6.35/arch/arm/plat-omap/include/mach/keypad.h
5375===================================================================
5376--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5377@@ -0,0 +1,45 @@
5378+/*
5379+ * arch/arm/plat-omap/include/mach/keypad.h
5380+ *
5381+ * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5382+ *
5383+ * This program is free software; you can redistribute it and/or modify
5384+ * it under the terms of the GNU General Public License version 2 as
5385+ * published by the Free Software Foundation.
5386+ */
5387+#ifndef ASMARM_ARCH_KEYPAD_H
5388+#define ASMARM_ARCH_KEYPAD_H
5389+
5390+#warning: Please update the board to use matrix_keypad.h instead
5391+
5392+struct omap_kp_platform_data {
5393+ int rows;
5394+ int cols;
5395+ int *keymap;
5396+ unsigned int keymapsize;
5397+ unsigned int rep:1;
5398+ unsigned long delay;
5399+ unsigned int dbounce:1;
5400+ /* specific to OMAP242x*/
5401+ unsigned int *row_gpios;
5402+ unsigned int *col_gpios;
5403+};
5404+
5405+/* Group (0..3) -- when multiple keys are pressed, only the
5406+ * keys pressed in the same group are considered as pressed. This is
5407+ * in order to workaround certain crappy HW designs that produce ghost
5408+ * keypresses. */
5409+#define GROUP_0 (0 << 16)
5410+#define GROUP_1 (1 << 16)
5411+#define GROUP_2 (2 << 16)
5412+#define GROUP_3 (3 << 16)
5413+#define GROUP_MASK GROUP_3
5414+
5415+#define KEY_PERSISTENT 0x00800000
5416+#define KEYNUM_MASK 0x00EFFFFF
5417+#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5418+#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5419+ KEY_PERSISTENT)
5420+
5421+#endif
5422+
5423Index: linux-2.6.35/arch/arm/plat-omap/include/mach/lcd_mipid.h
5424===================================================================
5425--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5426@@ -0,0 +1,29 @@
5427+#ifndef __LCD_MIPID_H
5428+#define __LCD_MIPID_H
5429+
5430+enum mipid_test_num {
5431+ MIPID_TEST_RGB_LINES,
5432+};
5433+
5434+enum mipid_test_result {
5435+ MIPID_TEST_SUCCESS,
5436+ MIPID_TEST_INVALID,
5437+ MIPID_TEST_FAILED,
5438+};
5439+
5440+#ifdef __KERNEL__
5441+
5442+struct mipid_platform_data {
5443+ int nreset_gpio;
5444+ int data_lines;
5445+
5446+ void (*shutdown)(struct mipid_platform_data *pdata);
5447+ void (*set_bklight_level)(struct mipid_platform_data *pdata,
5448+ int level);
5449+ int (*get_bklight_level)(struct mipid_platform_data *pdata);
5450+ int (*get_bklight_max)(struct mipid_platform_data *pdata);
5451+};
5452+
5453+#endif
5454+
5455+#endif
5456Index: linux-2.6.35/arch/arm/plat-omap/include/mach/led.h
5457===================================================================
5458--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5459@@ -0,0 +1,24 @@
5460+/*
5461+ * arch/arm/plat-omap/include/mach/led.h
5462+ *
5463+ * Copyright (C) 2006 Samsung Electronics
5464+ * Kyungmin Park <kyungmin.park@samsung.com>
5465+ *
5466+ * This program is free software; you can redistribute it and/or modify
5467+ * it under the terms of the GNU General Public License version 2 as
5468+ * published by the Free Software Foundation.
5469+ */
5470+#ifndef ASMARM_ARCH_LED_H
5471+#define ASMARM_ARCH_LED_H
5472+
5473+struct omap_led_config {
5474+ struct led_classdev cdev;
5475+ s16 gpio;
5476+};
5477+
5478+struct omap_led_platform_data {
5479+ s16 nr_leds;
5480+ struct omap_led_config *leds;
5481+};
5482+
5483+#endif
5484Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mailbox.h
5485===================================================================
5486--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5487@@ -0,0 +1,111 @@
5488+/* mailbox.h */
5489+
5490+#ifndef MAILBOX_H
5491+#define MAILBOX_H
5492+
5493+#include <linux/wait.h>
5494+#include <linux/workqueue.h>
5495+#include <linux/blkdev.h>
5496+#include <linux/interrupt.h>
5497+
5498+typedef u32 mbox_msg_t;
5499+struct omap_mbox;
5500+
5501+typedef int __bitwise omap_mbox_irq_t;
5502+#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5503+#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5504+
5505+typedef int __bitwise omap_mbox_type_t;
5506+#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5507+#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5508+
5509+struct omap_mbox_ops {
5510+ omap_mbox_type_t type;
5511+ int (*startup)(struct omap_mbox *mbox);
5512+ void (*shutdown)(struct omap_mbox *mbox);
5513+ /* fifo */
5514+ mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5515+ void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5516+ int (*fifo_empty)(struct omap_mbox *mbox);
5517+ int (*fifo_full)(struct omap_mbox *mbox);
5518+ /* irq */
5519+ void (*enable_irq)(struct omap_mbox *mbox,
5520+ omap_mbox_irq_t irq);
5521+ void (*disable_irq)(struct omap_mbox *mbox,
5522+ omap_mbox_irq_t irq);
5523+ void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5524+ int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5525+ /* ctx */
5526+ void (*save_ctx)(struct omap_mbox *mbox);
5527+ void (*restore_ctx)(struct omap_mbox *mbox);
5528+};
5529+
5530+struct omap_mbox_queue {
5531+ spinlock_t lock;
5532+ struct request_queue *queue;
5533+ struct work_struct work;
5534+ struct tasklet_struct tasklet;
5535+ int (*callback)(void *);
5536+ struct omap_mbox *mbox;
5537+};
5538+
5539+struct omap_mbox {
5540+ char *name;
5541+ unsigned int irq;
5542+
5543+ struct omap_mbox_queue *txq, *rxq;
5544+
5545+ struct omap_mbox_ops *ops;
5546+
5547+ mbox_msg_t seq_snd, seq_rcv;
5548+
5549+ struct device *dev;
5550+
5551+ struct omap_mbox *next;
5552+ void *priv;
5553+
5554+ void (*err_notify)(void);
5555+};
5556+
5557+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5558+void omap_mbox_init_seq(struct omap_mbox *);
5559+
5560+struct omap_mbox *omap_mbox_get(const char *);
5561+void omap_mbox_put(struct omap_mbox *);
5562+
5563+int omap_mbox_register(struct device *parent, struct omap_mbox *);
5564+int omap_mbox_unregister(struct omap_mbox *);
5565+
5566+static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5567+{
5568+ if (!mbox->ops->save_ctx) {
5569+ dev_err(mbox->dev, "%s:\tno save\n", __func__);
5570+ return;
5571+ }
5572+
5573+ mbox->ops->save_ctx(mbox);
5574+}
5575+
5576+static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5577+{
5578+ if (!mbox->ops->restore_ctx) {
5579+ dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5580+ return;
5581+ }
5582+
5583+ mbox->ops->restore_ctx(mbox);
5584+}
5585+
5586+static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5587+ omap_mbox_irq_t irq)
5588+{
5589+ mbox->ops->enable_irq(mbox, irq);
5590+}
5591+
5592+static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5593+ omap_mbox_irq_t irq)
5594+{
5595+ mbox->ops->disable_irq(mbox, irq);
5596+}
5597+
5598+#endif /* MAILBOX_H */
5599Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcbsp.h
5600===================================================================
5601--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5602@@ -0,0 +1,462 @@
5603+/*
5604+ * arch/arm/plat-omap/include/mach/mcbsp.h
5605+ *
5606+ * Defines for Multi-Channel Buffered Serial Port
5607+ *
5608+ * Copyright (C) 2002 RidgeRun, Inc.
5609+ * Author: Steve Johnson
5610+ *
5611+ * This program is free software; you can redistribute it and/or modify
5612+ * it under the terms of the GNU General Public License as published by
5613+ * the Free Software Foundation; either version 2 of the License, or
5614+ * (at your option) any later version.
5615+ *
5616+ * This program is distributed in the hope that it will be useful,
5617+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5618+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5619+ * GNU General Public License for more details.
5620+ *
5621+ * You should have received a copy of the GNU General Public License
5622+ * along with this program; if not, write to the Free Software
5623+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5624+ *
5625+ */
5626+#ifndef __ASM_ARCH_OMAP_MCBSP_H
5627+#define __ASM_ARCH_OMAP_MCBSP_H
5628+
5629+#include <linux/completion.h>
5630+#include <linux/spinlock.h>
5631+
5632+#include <mach/hardware.h>
5633+#include <plat/clock.h>
5634+
5635+#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5636+#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5637+
5638+#define OMAP1510_MCBSP1_BASE 0xe1011800
5639+#define OMAP1510_MCBSP2_BASE 0xfffb1000
5640+#define OMAP1510_MCBSP3_BASE 0xe1017000
5641+
5642+#define OMAP1610_MCBSP1_BASE 0xe1011800
5643+#define OMAP1610_MCBSP2_BASE 0xfffb1000
5644+#define OMAP1610_MCBSP3_BASE 0xe1017000
5645+
5646+#define OMAP24XX_MCBSP1_BASE 0x48074000
5647+#define OMAP24XX_MCBSP2_BASE 0x48076000
5648+#define OMAP2430_MCBSP3_BASE 0x4808c000
5649+#define OMAP2430_MCBSP4_BASE 0x4808e000
5650+#define OMAP2430_MCBSP5_BASE 0x48096000
5651+
5652+#define OMAP34XX_MCBSP1_BASE 0x48074000
5653+#define OMAP34XX_MCBSP2_BASE 0x49022000
5654+#define OMAP34XX_MCBSP3_BASE 0x49024000
5655+#define OMAP34XX_MCBSP4_BASE 0x49026000
5656+#define OMAP34XX_MCBSP5_BASE 0x48096000
5657+
5658+#define OMAP44XX_MCBSP1_BASE 0x49022000
5659+#define OMAP44XX_MCBSP2_BASE 0x49024000
5660+#define OMAP44XX_MCBSP3_BASE 0x49026000
5661+#define OMAP44XX_MCBSP4_BASE 0x48074000
5662+
5663+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5664+
5665+#define OMAP_MCBSP_REG_DRR2 0x00
5666+#define OMAP_MCBSP_REG_DRR1 0x02
5667+#define OMAP_MCBSP_REG_DXR2 0x04
5668+#define OMAP_MCBSP_REG_DXR1 0x06
5669+#define OMAP_MCBSP_REG_SPCR2 0x08
5670+#define OMAP_MCBSP_REG_SPCR1 0x0a
5671+#define OMAP_MCBSP_REG_RCR2 0x0c
5672+#define OMAP_MCBSP_REG_RCR1 0x0e
5673+#define OMAP_MCBSP_REG_XCR2 0x10
5674+#define OMAP_MCBSP_REG_XCR1 0x12
5675+#define OMAP_MCBSP_REG_SRGR2 0x14
5676+#define OMAP_MCBSP_REG_SRGR1 0x16
5677+#define OMAP_MCBSP_REG_MCR2 0x18
5678+#define OMAP_MCBSP_REG_MCR1 0x1a
5679+#define OMAP_MCBSP_REG_RCERA 0x1c
5680+#define OMAP_MCBSP_REG_RCERB 0x1e
5681+#define OMAP_MCBSP_REG_XCERA 0x20
5682+#define OMAP_MCBSP_REG_XCERB 0x22
5683+#define OMAP_MCBSP_REG_PCR0 0x24
5684+#define OMAP_MCBSP_REG_RCERC 0x26
5685+#define OMAP_MCBSP_REG_RCERD 0x28
5686+#define OMAP_MCBSP_REG_XCERC 0x2A
5687+#define OMAP_MCBSP_REG_XCERD 0x2C
5688+#define OMAP_MCBSP_REG_RCERE 0x2E
5689+#define OMAP_MCBSP_REG_RCERF 0x30
5690+#define OMAP_MCBSP_REG_XCERE 0x32
5691+#define OMAP_MCBSP_REG_XCERF 0x34
5692+#define OMAP_MCBSP_REG_RCERG 0x36
5693+#define OMAP_MCBSP_REG_RCERH 0x38
5694+#define OMAP_MCBSP_REG_XCERG 0x3A
5695+#define OMAP_MCBSP_REG_XCERH 0x3C
5696+
5697+/* Dummy defines, these are not available on omap1 */
5698+#define OMAP_MCBSP_REG_XCCR 0x00
5699+#define OMAP_MCBSP_REG_RCCR 0x00
5700+
5701+#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5702+#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5703+
5704+#define AUDIO_MCBSP OMAP_MCBSP1
5705+#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5706+#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5707+
5708+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5709+ defined(CONFIG_ARCH_OMAP4)
5710+
5711+#define OMAP_MCBSP_REG_DRR2 0x00
5712+#define OMAP_MCBSP_REG_DRR1 0x04
5713+#define OMAP_MCBSP_REG_DXR2 0x08
5714+#define OMAP_MCBSP_REG_DXR1 0x0C
5715+#define OMAP_MCBSP_REG_DRR 0x00
5716+#define OMAP_MCBSP_REG_DXR 0x08
5717+#define OMAP_MCBSP_REG_SPCR2 0x10
5718+#define OMAP_MCBSP_REG_SPCR1 0x14
5719+#define OMAP_MCBSP_REG_RCR2 0x18
5720+#define OMAP_MCBSP_REG_RCR1 0x1C
5721+#define OMAP_MCBSP_REG_XCR2 0x20
5722+#define OMAP_MCBSP_REG_XCR1 0x24
5723+#define OMAP_MCBSP_REG_SRGR2 0x28
5724+#define OMAP_MCBSP_REG_SRGR1 0x2C
5725+#define OMAP_MCBSP_REG_MCR2 0x30
5726+#define OMAP_MCBSP_REG_MCR1 0x34
5727+#define OMAP_MCBSP_REG_RCERA 0x38
5728+#define OMAP_MCBSP_REG_RCERB 0x3C
5729+#define OMAP_MCBSP_REG_XCERA 0x40
5730+#define OMAP_MCBSP_REG_XCERB 0x44
5731+#define OMAP_MCBSP_REG_PCR0 0x48
5732+#define OMAP_MCBSP_REG_RCERC 0x4C
5733+#define OMAP_MCBSP_REG_RCERD 0x50
5734+#define OMAP_MCBSP_REG_XCERC 0x54
5735+#define OMAP_MCBSP_REG_XCERD 0x58
5736+#define OMAP_MCBSP_REG_RCERE 0x5C
5737+#define OMAP_MCBSP_REG_RCERF 0x60
5738+#define OMAP_MCBSP_REG_XCERE 0x64
5739+#define OMAP_MCBSP_REG_XCERF 0x68
5740+#define OMAP_MCBSP_REG_RCERG 0x6C
5741+#define OMAP_MCBSP_REG_RCERH 0x70
5742+#define OMAP_MCBSP_REG_XCERG 0x74
5743+#define OMAP_MCBSP_REG_XCERH 0x78
5744+#define OMAP_MCBSP_REG_SYSCON 0x8C
5745+#define OMAP_MCBSP_REG_THRSH2 0x90
5746+#define OMAP_MCBSP_REG_THRSH1 0x94
5747+#define OMAP_MCBSP_REG_IRQST 0xA0
5748+#define OMAP_MCBSP_REG_IRQEN 0xA4
5749+#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5750+#define OMAP_MCBSP_REG_XCCR 0xAC
5751+#define OMAP_MCBSP_REG_RCCR 0xB0
5752+
5753+#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5754+#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5755+
5756+#define AUDIO_MCBSP OMAP_MCBSP2
5757+#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5758+#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5759+
5760+#endif
5761+
5762+/************************** McBSP SPCR1 bit definitions ***********************/
5763+#define RRST 0x0001
5764+#define RRDY 0x0002
5765+#define RFULL 0x0004
5766+#define RSYNC_ERR 0x0008
5767+#define RINTM(value) ((value)<<4) /* bits 4:5 */
5768+#define ABIS 0x0040
5769+#define DXENA 0x0080
5770+#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5771+#define RJUST(value) ((value)<<13) /* bits 13:14 */
5772+#define ALB 0x8000
5773+#define DLB 0x8000
5774+
5775+/************************** McBSP SPCR2 bit definitions ***********************/
5776+#define XRST 0x0001
5777+#define XRDY 0x0002
5778+#define XEMPTY 0x0004
5779+#define XSYNC_ERR 0x0008
5780+#define XINTM(value) ((value)<<4) /* bits 4:5 */
5781+#define GRST 0x0040
5782+#define FRST 0x0080
5783+#define SOFT 0x0100
5784+#define FREE 0x0200
5785+
5786+/************************** McBSP PCR bit definitions *************************/
5787+#define CLKRP 0x0001
5788+#define CLKXP 0x0002
5789+#define FSRP 0x0004
5790+#define FSXP 0x0008
5791+#define DR_STAT 0x0010
5792+#define DX_STAT 0x0020
5793+#define CLKS_STAT 0x0040
5794+#define SCLKME 0x0080
5795+#define CLKRM 0x0100
5796+#define CLKXM 0x0200
5797+#define FSRM 0x0400
5798+#define FSXM 0x0800
5799+#define RIOEN 0x1000
5800+#define XIOEN 0x2000
5801+#define IDLE_EN 0x4000
5802+
5803+/************************** McBSP RCR1 bit definitions ************************/
5804+#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5805+#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5806+
5807+/************************** McBSP XCR1 bit definitions ************************/
5808+#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5809+#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5810+
5811+/*************************** McBSP RCR2 bit definitions ***********************/
5812+#define RDATDLY(value) (value) /* Bits 0:1 */
5813+#define RFIG 0x0004
5814+#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5815+#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5816+#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5817+#define RPHASE 0x8000
5818+
5819+/*************************** McBSP XCR2 bit definitions ***********************/
5820+#define XDATDLY(value) (value) /* Bits 0:1 */
5821+#define XFIG 0x0004
5822+#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5823+#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5824+#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5825+#define XPHASE 0x8000
5826+
5827+/************************* McBSP SRGR1 bit definitions ************************/
5828+#define CLKGDV(value) (value) /* Bits 0:7 */
5829+#define FWID(value) ((value)<<8) /* Bits 8:15 */
5830+
5831+/************************* McBSP SRGR2 bit definitions ************************/
5832+#define FPER(value) (value) /* Bits 0:11 */
5833+#define FSGM 0x1000
5834+#define CLKSM 0x2000
5835+#define CLKSP 0x4000
5836+#define GSYNC 0x8000
5837+
5838+/************************* McBSP MCR1 bit definitions *************************/
5839+#define RMCM 0x0001
5840+#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5841+#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5842+#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5843+
5844+/************************* McBSP MCR2 bit definitions *************************/
5845+#define XMCM(value) (value) /* Bits 0:1 */
5846+#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5847+#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5848+#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5849+
5850+/*********************** McBSP XCCR bit definitions *************************/
5851+#define EXTCLKGATE 0x8000
5852+#define PPCONNECT 0x4000
5853+#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5854+#define XFULL_CYCLE 0x0800
5855+#define DILB 0x0020
5856+#define XDMAEN 0x0008
5857+#define XDISABLE 0x0001
5858+
5859+/********************** McBSP RCCR bit definitions *************************/
5860+#define RFULL_CYCLE 0x0800
5861+#define RDMAEN 0x0008
5862+#define RDISABLE 0x0001
5863+
5864+/********************** McBSP SYSCONFIG bit definitions ********************/
5865+#define CLOCKACTIVITY(value) ((value)<<8)
5866+#define SIDLEMODE(value) ((value)<<3)
5867+#define ENAWAKEUP 0x0004
5868+#define SOFTRST 0x0002
5869+
5870+/********************** McBSP DMA operating modes **************************/
5871+#define MCBSP_DMA_MODE_ELEMENT 0
5872+#define MCBSP_DMA_MODE_THRESHOLD 1
5873+#define MCBSP_DMA_MODE_FRAME 2
5874+
5875+/********************** McBSP WAKEUPEN bit definitions *********************/
5876+#define XEMPTYEOFEN 0x4000
5877+#define XRDYEN 0x0400
5878+#define XEOFEN 0x0200
5879+#define XFSXEN 0x0100
5880+#define XSYNCERREN 0x0080
5881+#define RRDYEN 0x0008
5882+#define REOFEN 0x0004
5883+#define RFSREN 0x0002
5884+#define RSYNCERREN 0x0001
5885+
5886+/* we don't do multichannel for now */
5887+struct omap_mcbsp_reg_cfg {
5888+ u16 spcr2;
5889+ u16 spcr1;
5890+ u16 rcr2;
5891+ u16 rcr1;
5892+ u16 xcr2;
5893+ u16 xcr1;
5894+ u16 srgr2;
5895+ u16 srgr1;
5896+ u16 mcr2;
5897+ u16 mcr1;
5898+ u16 pcr0;
5899+ u16 rcerc;
5900+ u16 rcerd;
5901+ u16 xcerc;
5902+ u16 xcerd;
5903+ u16 rcere;
5904+ u16 rcerf;
5905+ u16 xcere;
5906+ u16 xcerf;
5907+ u16 rcerg;
5908+ u16 rcerh;
5909+ u16 xcerg;
5910+ u16 xcerh;
5911+ u16 xccr;
5912+ u16 rccr;
5913+};
5914+
5915+typedef enum {
5916+ OMAP_MCBSP1 = 0,
5917+ OMAP_MCBSP2,
5918+ OMAP_MCBSP3,
5919+ OMAP_MCBSP4,
5920+ OMAP_MCBSP5
5921+} omap_mcbsp_id;
5922+
5923+typedef int __bitwise omap_mcbsp_io_type_t;
5924+#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
5925+#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
5926+
5927+typedef enum {
5928+ OMAP_MCBSP_WORD_8 = 0,
5929+ OMAP_MCBSP_WORD_12,
5930+ OMAP_MCBSP_WORD_16,
5931+ OMAP_MCBSP_WORD_20,
5932+ OMAP_MCBSP_WORD_24,
5933+ OMAP_MCBSP_WORD_32,
5934+} omap_mcbsp_word_length;
5935+
5936+typedef enum {
5937+ OMAP_MCBSP_CLK_RISING = 0,
5938+ OMAP_MCBSP_CLK_FALLING,
5939+} omap_mcbsp_clk_polarity;
5940+
5941+typedef enum {
5942+ OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
5943+ OMAP_MCBSP_FS_ACTIVE_LOW,
5944+} omap_mcbsp_fs_polarity;
5945+
5946+typedef enum {
5947+ OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
5948+ OMAP_MCBSP_CLK_STP_MODE_DELAY,
5949+} omap_mcbsp_clk_stp_mode;
5950+
5951+
5952+/******* SPI specific mode **********/
5953+typedef enum {
5954+ OMAP_MCBSP_SPI_MASTER = 0,
5955+ OMAP_MCBSP_SPI_SLAVE,
5956+} omap_mcbsp_spi_mode;
5957+
5958+struct omap_mcbsp_spi_cfg {
5959+ omap_mcbsp_spi_mode spi_mode;
5960+ omap_mcbsp_clk_polarity rx_clock_polarity;
5961+ omap_mcbsp_clk_polarity tx_clock_polarity;
5962+ omap_mcbsp_fs_polarity fsx_polarity;
5963+ u8 clk_div;
5964+ omap_mcbsp_clk_stp_mode clk_stp_mode;
5965+ omap_mcbsp_word_length word_length;
5966+};
5967+
5968+/* Platform specific configuration */
5969+struct omap_mcbsp_ops {
5970+ void (*request)(unsigned int);
5971+ void (*free)(unsigned int);
5972+};
5973+
5974+struct omap_mcbsp_platform_data {
5975+ unsigned long phys_base;
5976+ u8 dma_rx_sync, dma_tx_sync;
5977+ u16 rx_irq, tx_irq;
5978+ struct omap_mcbsp_ops *ops;
5979+#ifdef CONFIG_ARCH_OMAP34XX
5980+ u16 buffer_size;
5981+#endif
5982+};
5983+
5984+struct omap_mcbsp {
5985+ struct device *dev;
5986+ unsigned long phys_base;
5987+ void __iomem *io_base;
5988+ u8 id;
5989+ u8 free;
5990+ omap_mcbsp_word_length rx_word_length;
5991+ omap_mcbsp_word_length tx_word_length;
5992+
5993+ omap_mcbsp_io_type_t io_type; /* IRQ or poll */
5994+ /* IRQ based TX/RX */
5995+ int rx_irq;
5996+ int tx_irq;
5997+
5998+ /* DMA stuff */
5999+ u8 dma_rx_sync;
6000+ short dma_rx_lch;
6001+ u8 dma_tx_sync;
6002+ short dma_tx_lch;
6003+
6004+ /* Completion queues */
6005+ struct completion tx_irq_completion;
6006+ struct completion rx_irq_completion;
6007+ struct completion tx_dma_completion;
6008+ struct completion rx_dma_completion;
6009+
6010+ /* Protect the field .free, while checking if the mcbsp is in use */
6011+ spinlock_t lock;
6012+ struct omap_mcbsp_platform_data *pdata;
6013+ struct clk *iclk;
6014+ struct clk *fclk;
6015+#ifdef CONFIG_ARCH_OMAP34XX
6016+ int dma_op_mode;
6017+ u16 max_tx_thres;
6018+ u16 max_rx_thres;
6019+#endif
6020+};
6021+extern struct omap_mcbsp **mcbsp_ptr;
6022+extern int omap_mcbsp_count;
6023+
6024+int omap_mcbsp_init(void);
6025+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6026+ int size);
6027+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6028+#ifdef CONFIG_ARCH_OMAP34XX
6029+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6030+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6031+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6032+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6033+int omap_mcbsp_get_dma_op_mode(unsigned int id);
6034+#else
6035+static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6036+{ }
6037+static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6038+{ }
6039+static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6040+static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6041+static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6042+#endif
6043+int omap_mcbsp_request(unsigned int id);
6044+void omap_mcbsp_free(unsigned int id);
6045+void omap_mcbsp_start(unsigned int id, int tx, int rx);
6046+void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6047+void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6048+u32 omap_mcbsp_recv_word(unsigned int id);
6049+
6050+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6051+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6052+int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6053+int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6054+
6055+
6056+/* SPI specific API */
6057+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6058+
6059+/* Polled read/write functions */
6060+int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6061+int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6062+int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6063+
6064+#endif
6065Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcspi.h
6066===================================================================
6067--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6068@@ -0,0 +1,15 @@
6069+#ifndef _OMAP2_MCSPI_H
6070+#define _OMAP2_MCSPI_H
6071+
6072+struct omap2_mcspi_platform_config {
6073+ unsigned short num_cs;
6074+};
6075+
6076+struct omap2_mcspi_device_config {
6077+ unsigned turbo_mode:1;
6078+
6079+ /* Do we want one channel enabled at the same time? */
6080+ unsigned single_channel:1;
6081+};
6082+
6083+#endif
6084Index: linux-2.6.35/arch/arm/plat-omap/include/mach/memory.h
6085===================================================================
6086--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6087@@ -0,0 +1,103 @@
6088+/*
6089+ * arch/arm/plat-omap/include/mach/memory.h
6090+ *
6091+ * Memory map for OMAP-1510 and 1610
6092+ *
6093+ * Copyright (C) 2000 RidgeRun, Inc.
6094+ * Author: Greg Lonnon <glonnon@ridgerun.com>
6095+ *
6096+ * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6097+ * Copyright (C) 1999 ARM Limited
6098+ *
6099+ * This program is free software; you can redistribute it and/or modify it
6100+ * under the terms of the GNU General Public License as published by the
6101+ * Free Software Foundation; either version 2 of the License, or (at your
6102+ * option) any later version.
6103+ *
6104+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6105+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6106+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6107+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6108+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6109+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6110+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6111+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6112+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6113+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6114+ *
6115+ * You should have received a copy of the GNU General Public License along
6116+ * with this program; if not, write to the Free Software Foundation, Inc.,
6117+ * 675 Mass Ave, Cambridge, MA 02139, USA.
6118+ */
6119+
6120+#ifndef __ASM_ARCH_MEMORY_H
6121+#define __ASM_ARCH_MEMORY_H
6122+
6123+/*
6124+ * Physical DRAM offset.
6125+ */
6126+#if defined(CONFIG_ARCH_OMAP1)
6127+#define PHYS_OFFSET UL(0x10000000)
6128+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6129+ defined(CONFIG_ARCH_OMAP4)
6130+#define PHYS_OFFSET UL(0x80000000)
6131+#endif
6132+
6133+/*
6134+ * Bus address is physical address, except for OMAP-1510 Local Bus.
6135+ * OMAP-1510 bus address is translated into a Local Bus address if the
6136+ * OMAP bus type is lbus. We do the address translation based on the
6137+ * device overriding the defaults used in the dma-mapping API.
6138+ * Note that the is_lbus_device() test is not very efficient on 1510
6139+ * because of the strncmp().
6140+ */
6141+#ifdef CONFIG_ARCH_OMAP15XX
6142+
6143+/*
6144+ * OMAP-1510 Local Bus address offset
6145+ */
6146+#define OMAP1510_LB_OFFSET UL(0x30000000)
6147+
6148+#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6149+#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6150+#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6151+
6152+#define __arch_page_to_dma(dev, page) \
6153+ ({ dma_addr_t __dma = page_to_phys(page); \
6154+ if (is_lbus_device(dev)) \
6155+ __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6156+ __dma; })
6157+
6158+#define __arch_dma_to_page(dev, addr) \
6159+ ({ dma_addr_t __dma = addr; \
6160+ if (is_lbus_device(dev)) \
6161+ __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6162+ phys_to_page(__dma); \
6163+ })
6164+
6165+#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6166+ lbus_to_virt(addr) : \
6167+ __phys_to_virt(addr)); })
6168+
6169+#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6170+ (dma_addr_t) (is_lbus_device(dev) ? \
6171+ virt_to_lbus(__addr) : \
6172+ __virt_to_phys(__addr)); })
6173+
6174+#endif /* CONFIG_ARCH_OMAP15XX */
6175+
6176+/* Override the ARM default */
6177+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6178+
6179+#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6180+#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6181+#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6182+#endif
6183+
6184+#define CONSISTENT_DMA_SIZE \
6185+ (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6186+
6187+#endif
6188+
6189+#endif
6190+
6191Index: linux-2.6.35/arch/arm/plat-omap/include/mach/menelaus.h
6192===================================================================
6193--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6194@@ -0,0 +1,49 @@
6195+/*
6196+ * arch/arm/plat-omap/include/mach/menelaus.h
6197+ *
6198+ * Functions to access Menelaus power management chip
6199+ */
6200+
6201+#ifndef __ASM_ARCH_MENELAUS_H
6202+#define __ASM_ARCH_MENELAUS_H
6203+
6204+struct device;
6205+
6206+struct menelaus_platform_data {
6207+ int (* late_init)(struct device *dev);
6208+};
6209+
6210+extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6211+ void *data);
6212+extern void menelaus_unregister_mmc_callback(void);
6213+extern int menelaus_set_mmc_opendrain(int slot, int enable);
6214+extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6215+
6216+extern int menelaus_set_vmem(unsigned int mV);
6217+extern int menelaus_set_vio(unsigned int mV);
6218+extern int menelaus_set_vmmc(unsigned int mV);
6219+extern int menelaus_set_vaux(unsigned int mV);
6220+extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6221+extern int menelaus_set_slot_sel(int enable);
6222+extern int menelaus_get_slot_pin_states(void);
6223+extern int menelaus_set_vcore_sw(unsigned int mV);
6224+extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6225+
6226+#define EN_VPLL_SLEEP (1 << 7)
6227+#define EN_VMMC_SLEEP (1 << 6)
6228+#define EN_VAUX_SLEEP (1 << 5)
6229+#define EN_VIO_SLEEP (1 << 4)
6230+#define EN_VMEM_SLEEP (1 << 3)
6231+#define EN_DC3_SLEEP (1 << 2)
6232+#define EN_DC2_SLEEP (1 << 1)
6233+#define EN_VC_SLEEP (1 << 0)
6234+
6235+extern int menelaus_set_regulator_sleep(int enable, u32 val);
6236+
6237+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6238+#define omap_has_menelaus() 1
6239+#else
6240+#define omap_has_menelaus() 0
6241+#endif
6242+
6243+#endif
6244Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mmc.h
6245===================================================================
6246--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6247@@ -0,0 +1,157 @@
6248+/*
6249+ * MMC definitions for OMAP2
6250+ *
6251+ * Copyright (C) 2006 Nokia Corporation
6252+ *
6253+ * This program is free software; you can redistribute it and/or modify
6254+ * it under the terms of the GNU General Public License version 2 as
6255+ * published by the Free Software Foundation.
6256+ */
6257+
6258+#ifndef __OMAP2_MMC_H
6259+#define __OMAP2_MMC_H
6260+
6261+#include <linux/types.h>
6262+#include <linux/device.h>
6263+#include <linux/mmc/host.h>
6264+
6265+#include <plat/board.h>
6266+
6267+#define OMAP15XX_NR_MMC 1
6268+#define OMAP16XX_NR_MMC 2
6269+#define OMAP1_MMC_SIZE 0x080
6270+#define OMAP1_MMC1_BASE 0xfffb7800
6271+#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
6272+
6273+#define OMAP24XX_NR_MMC 2
6274+#define OMAP34XX_NR_MMC 3
6275+#define OMAP44XX_NR_MMC 5
6276+#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
6277+#define OMAP3_HSMMC_SIZE 0x200
6278+#define OMAP4_HSMMC_SIZE 0x1000
6279+#define OMAP2_MMC1_BASE 0x4809c000
6280+#define OMAP2_MMC2_BASE 0x480b4000
6281+#define OMAP3_MMC3_BASE 0x480ad000
6282+#define OMAP4_MMC4_BASE 0x480d1000
6283+#define OMAP4_MMC5_BASE 0x480d5000
6284+#define OMAP4_MMC_REG_OFFSET 0x100
6285+#define HSMMC5 (1 << 4)
6286+#define HSMMC4 (1 << 3)
6287+#define HSMMC3 (1 << 2)
6288+#define HSMMC2 (1 << 1)
6289+#define HSMMC1 (1 << 0)
6290+
6291+#define OMAP_MMC_MAX_SLOTS 2
6292+
6293+struct omap_mmc_platform_data {
6294+ /* back-link to device */
6295+ struct device *dev;
6296+
6297+ /* number of slots per controller */
6298+ unsigned nr_slots:2;
6299+
6300+ /* set if your board has components or wiring that limits the
6301+ * maximum frequency on the MMC bus */
6302+ unsigned int max_freq;
6303+
6304+ /* switch the bus to a new slot */
6305+ int (* switch_slot)(struct device *dev, int slot);
6306+ /* initialize board-specific MMC functionality, can be NULL if
6307+ * not supported */
6308+ int (* init)(struct device *dev);
6309+ void (* cleanup)(struct device *dev);
6310+ void (* shutdown)(struct device *dev);
6311+
6312+ /* To handle board related suspend/resume functionality for MMC */
6313+ int (*suspend)(struct device *dev, int slot);
6314+ int (*resume)(struct device *dev, int slot);
6315+
6316+ /* Return context loss count due to PM states changing */
6317+ int (*get_context_loss_count)(struct device *dev);
6318+
6319+ u64 dma_mask;
6320+
6321+ struct omap_mmc_slot_data {
6322+
6323+ /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
6324+ * 8 wire signaling is also optional, and is used with HSMMC
6325+ */
6326+ u8 wires;
6327+
6328+ /*
6329+ * nomux means "standard" muxing is wrong on this board, and
6330+ * that board-specific code handled it before common init logic.
6331+ */
6332+ unsigned nomux:1;
6333+
6334+ /* switch pin can be for card detect (default) or card cover */
6335+ unsigned cover:1;
6336+
6337+ /* use the internal clock */
6338+ unsigned internal_clock:1;
6339+
6340+ /* nonremovable e.g. eMMC */
6341+ unsigned nonremovable:1;
6342+
6343+ /* Try to sleep or power off when possible */
6344+ unsigned power_saving:1;
6345+
6346+ int switch_pin; /* gpio (card detect) */
6347+ int gpio_wp; /* gpio (write protect) */
6348+
6349+ int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
6350+ int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
6351+ int (* get_ro)(struct device *dev, int slot);
6352+ int (*set_sleep)(struct device *dev, int slot, int sleep,
6353+ int vdd, int cardsleep);
6354+
6355+ /* return MMC cover switch state, can be NULL if not supported.
6356+ *
6357+ * possible return values:
6358+ * 0 - closed
6359+ * 1 - open
6360+ */
6361+ int (* get_cover_state)(struct device *dev, int slot);
6362+
6363+ const char *name;
6364+ u32 ocr_mask;
6365+
6366+ /* Card detection IRQs */
6367+ int card_detect_irq;
6368+ int (* card_detect)(int irq);
6369+
6370+ unsigned int ban_openended:1;
6371+
6372+ } slots[OMAP_MMC_MAX_SLOTS];
6373+};
6374+
6375+/* called from board-specific card detection service routine */
6376+extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
6377+
6378+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
6379+ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
6380+void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6381+ int nr_controllers);
6382+void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6383+ int nr_controllers);
6384+int omap_mmc_add(const char *name, int id, unsigned long base,
6385+ unsigned long size, unsigned int irq,
6386+ struct omap_mmc_platform_data *data);
6387+#else
6388+static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6389+ int nr_controllers)
6390+{
6391+}
6392+static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6393+ int nr_controllers)
6394+{
6395+}
6396+static inline int omap_mmc_add(const char *name, int id, unsigned long base,
6397+ unsigned long size, unsigned int irq,
6398+ struct omap_mmc_platform_data *data)
6399+{
6400+ return 0;
6401+}
6402+
6403+#endif
6404+#endif
6405Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mux.h
6406===================================================================
6407--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6408@@ -0,0 +1,662 @@
6409+/*
6410+ * arch/arm/plat-omap/include/mach/mux.h
6411+ *
6412+ * Table of the Omap register configurations for the FUNC_MUX and
6413+ * PULL_DWN combinations.
6414+ *
6415+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
6416+ * Copyright (C) 2003 - 2008 Nokia Corporation
6417+ *
6418+ * Written by Tony Lindgren
6419+ *
6420+ * This program is free software; you can redistribute it and/or modify
6421+ * it under the terms of the GNU General Public License as published by
6422+ * the Free Software Foundation; either version 2 of the License, or
6423+ * (at your option) any later version.
6424+ *
6425+ * This program is distributed in the hope that it will be useful,
6426+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
6427+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6428+ * GNU General Public License for more details.
6429+ *
6430+ * You should have received a copy of the GNU General Public License
6431+ * along with this program; if not, write to the Free Software
6432+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6433+ *
6434+ * NOTE: Please use the following naming style for new pin entries.
6435+ * For example, W8_1610_MMC2_DAT0, where:
6436+ * - W8 = ball
6437+ * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
6438+ * - MMC2_DAT0 = function
6439+ */
6440+
6441+#ifndef __ASM_ARCH_MUX_H
6442+#define __ASM_ARCH_MUX_H
6443+
6444+#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
6445+#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
6446+
6447+#ifdef CONFIG_OMAP_MUX_DEBUG
6448+#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
6449+ .mux_reg = FUNC_MUX_CTRL_##reg, \
6450+ .mask_offset = mode_offset, \
6451+ .mask = mode,
6452+
6453+#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
6454+ .pull_reg = PULL_DWN_CTRL_##reg, \
6455+ .pull_bit = bit, \
6456+ .pull_val = status,
6457+
6458+#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
6459+ .pu_pd_reg = PU_PD_SEL_##reg, \
6460+ .pu_pd_val = status,
6461+
6462+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
6463+ .mux_reg = OMAP7XX_IO_CONF_##reg, \
6464+ .mask_offset = mode_offset, \
6465+ .mask = mode,
6466+
6467+#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
6468+ .pull_reg = OMAP7XX_IO_CONF_##reg, \
6469+ .pull_bit = bit, \
6470+ .pull_val = status,
6471+
6472+#else
6473+
6474+#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
6475+ .mask_offset = mode_offset, \
6476+ .mask = mode,
6477+
6478+#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
6479+ .pull_bit = bit, \
6480+ .pull_val = status,
6481+
6482+#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
6483+ .pu_pd_val = status,
6484+
6485+#define MUX_REG_7XX(reg, mode_offset, mode) \
6486+ .mux_reg = OMAP7XX_IO_CONF_##reg, \
6487+ .mask_offset = mode_offset, \
6488+ .mask = mode,
6489+
6490+#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
6491+ .pull_bit = bit, \
6492+ .pull_val = status,
6493+
6494+#endif /* CONFIG_OMAP_MUX_DEBUG */
6495+
6496+#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
6497+ pull_reg, pull_bit, pull_status, \
6498+ pu_pd_reg, pu_pd_status, debug_status) \
6499+{ \
6500+ .name = desc, \
6501+ .debug = debug_status, \
6502+ MUX_REG(mux_reg, mode_offset, mode) \
6503+ PULL_REG(pull_reg, pull_bit, pull_status) \
6504+ PU_PD_REG(pu_pd_reg, pu_pd_status) \
6505+},
6506+
6507+
6508+/*
6509+ * OMAP730/850 has a slightly different config for the pin mux.
6510+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
6511+ * not the FUNC_MUX_CTRL_x regs from hardware.h
6512+ * - for pull-up/down, only has one enable bit which is is in the same register
6513+ * as mux config
6514+ */
6515+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
6516+ pull_bit, pull_status, debug_status)\
6517+{ \
6518+ .name = desc, \
6519+ .debug = debug_status, \
6520+ MUX_REG_7XX(mux_reg, mode_offset, mode) \
6521+ PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
6522+ PU_PD_REG(NA, 0) \
6523+},
6524+
6525+#define MUX_CFG_24XX(desc, reg_offset, mode, \
6526+ pull_en, pull_mode, dbg) \
6527+{ \
6528+ .name = desc, \
6529+ .debug = dbg, \
6530+ .mux_reg = reg_offset, \
6531+ .mask = mode, \
6532+ .pull_val = pull_en, \
6533+ .pu_pd_val = pull_mode, \
6534+},
6535+
6536+/* 24xx/34xx mux bit defines */
6537+#define OMAP2_PULL_ENA (1 << 3)
6538+#define OMAP2_PULL_UP (1 << 4)
6539+#define OMAP2_ALTELECTRICALSEL (1 << 5)
6540+
6541+struct pin_config {
6542+ char *name;
6543+ const unsigned int mux_reg;
6544+ unsigned char debug;
6545+
6546+#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
6547+ const unsigned char mask_offset;
6548+ const unsigned char mask;
6549+
6550+ const char *pull_name;
6551+ const unsigned int pull_reg;
6552+ const unsigned char pull_val;
6553+ const unsigned char pull_bit;
6554+
6555+ const char *pu_pd_name;
6556+ const unsigned int pu_pd_reg;
6557+ const unsigned char pu_pd_val;
6558+#endif
6559+
6560+#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
6561+ const char *mux_reg_name;
6562+#endif
6563+
6564+};
6565+
6566+enum omap7xx_index {
6567+ /* OMAP 730 keyboard */
6568+ E2_7XX_KBR0,
6569+ J7_7XX_KBR1,
6570+ E1_7XX_KBR2,
6571+ F3_7XX_KBR3,
6572+ D2_7XX_KBR4,
6573+ C2_7XX_KBC0,
6574+ D3_7XX_KBC1,
6575+ E4_7XX_KBC2,
6576+ F4_7XX_KBC3,
6577+ E3_7XX_KBC4,
6578+
6579+ /* USB */
6580+ AA17_7XX_USB_DM,
6581+ W16_7XX_USB_PU_EN,
6582+ W17_7XX_USB_VBUSI,
6583+ W18_7XX_USB_DMCK_OUT,
6584+ W19_7XX_USB_DCRST,
6585+
6586+ /* MMC */
6587+ MMC_7XX_CMD,
6588+ MMC_7XX_CLK,
6589+ MMC_7XX_DAT0,
6590+
6591+ /* I2C */
6592+ I2C_7XX_SCL,
6593+ I2C_7XX_SDA,
6594+};
6595+
6596+enum omap1xxx_index {
6597+ /* UART1 (BT_UART_GATING)*/
6598+ UART1_TX = 0,
6599+ UART1_RTS,
6600+
6601+ /* UART2 (COM_UART_GATING)*/
6602+ UART2_TX,
6603+ UART2_RX,
6604+ UART2_CTS,
6605+ UART2_RTS,
6606+
6607+ /* UART3 (GIGA_UART_GATING) */
6608+ UART3_TX,
6609+ UART3_RX,
6610+ UART3_CTS,
6611+ UART3_RTS,
6612+ UART3_CLKREQ,
6613+ UART3_BCLK, /* 12MHz clock out */
6614+ Y15_1610_UART3_RTS,
6615+
6616+ /* PWT & PWL */
6617+ PWT,
6618+ PWL,
6619+
6620+ /* USB master generic */
6621+ R18_USB_VBUS,
6622+ R18_1510_USB_GPIO0,
6623+ W4_USB_PUEN,
6624+ W4_USB_CLKO,
6625+ W4_USB_HIGHZ,
6626+ W4_GPIO58,
6627+
6628+ /* USB1 master */
6629+ USB1_SUSP,
6630+ USB1_SEO,
6631+ W13_1610_USB1_SE0,
6632+ USB1_TXEN,
6633+ USB1_TXD,
6634+ USB1_VP,
6635+ USB1_VM,
6636+ USB1_RCV,
6637+ USB1_SPEED,
6638+ R13_1610_USB1_SPEED,
6639+ R13_1710_USB1_SE0,
6640+
6641+ /* USB2 master */
6642+ USB2_SUSP,
6643+ USB2_VP,
6644+ USB2_TXEN,
6645+ USB2_VM,
6646+ USB2_RCV,
6647+ USB2_SEO,
6648+ USB2_TXD,
6649+
6650+ /* OMAP-1510 GPIO */
6651+ R18_1510_GPIO0,
6652+ R19_1510_GPIO1,
6653+ M14_1510_GPIO2,
6654+
6655+ /* OMAP1610 GPIO */
6656+ P18_1610_GPIO3,
6657+ Y15_1610_GPIO17,
6658+
6659+ /* OMAP-1710 GPIO */
6660+ R18_1710_GPIO0,
6661+ V2_1710_GPIO10,
6662+ N21_1710_GPIO14,
6663+ W15_1710_GPIO40,
6664+
6665+ /* MPUIO */
6666+ MPUIO2,
6667+ N15_1610_MPUIO2,
6668+ MPUIO4,
6669+ MPUIO5,
6670+ T20_1610_MPUIO5,
6671+ W11_1610_MPUIO6,
6672+ V10_1610_MPUIO7,
6673+ W11_1610_MPUIO9,
6674+ V10_1610_MPUIO10,
6675+ W10_1610_MPUIO11,
6676+ E20_1610_MPUIO13,
6677+ U20_1610_MPUIO14,
6678+ E19_1610_MPUIO15,
6679+
6680+ /* MCBSP2 */
6681+ MCBSP2_CLKR,
6682+ MCBSP2_CLKX,
6683+ MCBSP2_DR,
6684+ MCBSP2_DX,
6685+ MCBSP2_FSR,
6686+ MCBSP2_FSX,
6687+
6688+ /* MCBSP3 */
6689+ MCBSP3_CLKX,
6690+
6691+ /* Misc ballouts */
6692+ BALLOUT_V8_ARMIO3,
6693+ N20_HDQ,
6694+
6695+ /* OMAP-1610 MMC2 */
6696+ W8_1610_MMC2_DAT0,
6697+ V8_1610_MMC2_DAT1,
6698+ W15_1610_MMC2_DAT2,
6699+ R10_1610_MMC2_DAT3,
6700+ Y10_1610_MMC2_CLK,
6701+ Y8_1610_MMC2_CMD,
6702+ V9_1610_MMC2_CMDDIR,
6703+ V5_1610_MMC2_DATDIR0,
6704+ W19_1610_MMC2_DATDIR1,
6705+ R18_1610_MMC2_CLKIN,
6706+
6707+ /* OMAP-1610 External Trace Interface */
6708+ M19_1610_ETM_PSTAT0,
6709+ L15_1610_ETM_PSTAT1,
6710+ L18_1610_ETM_PSTAT2,
6711+ L19_1610_ETM_D0,
6712+ J19_1610_ETM_D6,
6713+ J18_1610_ETM_D7,
6714+
6715+ /* OMAP16XX GPIO */
6716+ P20_1610_GPIO4,
6717+ V9_1610_GPIO7,
6718+ W8_1610_GPIO9,
6719+ N20_1610_GPIO11,
6720+ N19_1610_GPIO13,
6721+ P10_1610_GPIO22,
6722+ V5_1610_GPIO24,
6723+ AA20_1610_GPIO_41,
6724+ W19_1610_GPIO48,
6725+ M7_1610_GPIO62,
6726+ V14_16XX_GPIO37,
6727+ R9_16XX_GPIO18,
6728+ L14_16XX_GPIO49,
6729+
6730+ /* OMAP-1610 uWire */
6731+ V19_1610_UWIRE_SCLK,
6732+ U18_1610_UWIRE_SDI,
6733+ W21_1610_UWIRE_SDO,
6734+ N14_1610_UWIRE_CS0,
6735+ P15_1610_UWIRE_CS3,
6736+ N15_1610_UWIRE_CS1,
6737+
6738+ /* OMAP-1610 SPI */
6739+ U19_1610_SPIF_SCK,
6740+ U18_1610_SPIF_DIN,
6741+ P20_1610_SPIF_DIN,
6742+ W21_1610_SPIF_DOUT,
6743+ R18_1610_SPIF_DOUT,
6744+ N14_1610_SPIF_CS0,
6745+ N15_1610_SPIF_CS1,
6746+ T19_1610_SPIF_CS2,
6747+ P15_1610_SPIF_CS3,
6748+
6749+ /* OMAP-1610 Flash */
6750+ L3_1610_FLASH_CS2B_OE,
6751+ M8_1610_FLASH_CS2B_WE,
6752+
6753+ /* First MMC */
6754+ MMC_CMD,
6755+ MMC_DAT1,
6756+ MMC_DAT2,
6757+ MMC_DAT0,
6758+ MMC_CLK,
6759+ MMC_DAT3,
6760+
6761+ /* OMAP-1710 MMC CMDDIR and DATDIR0 */
6762+ M15_1710_MMC_CLKI,
6763+ P19_1710_MMC_CMDDIR,
6764+ P20_1710_MMC_DATDIR0,
6765+
6766+ /* OMAP-1610 USB0 alternate pin configuration */
6767+ W9_USB0_TXEN,
6768+ AA9_USB0_VP,
6769+ Y5_USB0_RCV,
6770+ R9_USB0_VM,
6771+ V6_USB0_TXD,
6772+ W5_USB0_SE0,
6773+ V9_USB0_SPEED,
6774+ V9_USB0_SUSP,
6775+
6776+ /* USB2 */
6777+ W9_USB2_TXEN,
6778+ AA9_USB2_VP,
6779+ Y5_USB2_RCV,
6780+ R9_USB2_VM,
6781+ V6_USB2_TXD,
6782+ W5_USB2_SE0,
6783+
6784+ /* 16XX UART */
6785+ R13_1610_UART1_TX,
6786+ V14_16XX_UART1_RX,
6787+ R14_1610_UART1_CTS,
6788+ AA15_1610_UART1_RTS,
6789+ R9_16XX_UART2_RX,
6790+ L14_16XX_UART3_RX,
6791+
6792+ /* I2C OMAP-1610 */
6793+ I2C_SCL,
6794+ I2C_SDA,
6795+
6796+ /* Keypad */
6797+ F18_1610_KBC0,
6798+ D20_1610_KBC1,
6799+ D19_1610_KBC2,
6800+ E18_1610_KBC3,
6801+ C21_1610_KBC4,
6802+ G18_1610_KBR0,
6803+ F19_1610_KBR1,
6804+ H14_1610_KBR2,
6805+ E20_1610_KBR3,
6806+ E19_1610_KBR4,
6807+ N19_1610_KBR5,
6808+
6809+ /* Power management */
6810+ T20_1610_LOW_PWR,
6811+
6812+ /* MCLK Settings */
6813+ V5_1710_MCLK_ON,
6814+ V5_1710_MCLK_OFF,
6815+ R10_1610_MCLK_ON,
6816+ R10_1610_MCLK_OFF,
6817+
6818+ /* CompactFlash controller */
6819+ P11_1610_CF_CD2,
6820+ R11_1610_CF_IOIS16,
6821+ V10_1610_CF_IREQ,
6822+ W10_1610_CF_RESET,
6823+ W11_1610_CF_CD1,
6824+
6825+ /* parallel camera */
6826+ J15_1610_CAM_LCLK,
6827+ J18_1610_CAM_D7,
6828+ J19_1610_CAM_D6,
6829+ J14_1610_CAM_D5,
6830+ K18_1610_CAM_D4,
6831+ K19_1610_CAM_D3,
6832+ K15_1610_CAM_D2,
6833+ K14_1610_CAM_D1,
6834+ L19_1610_CAM_D0,
6835+ L18_1610_CAM_VS,
6836+ L15_1610_CAM_HS,
6837+ M19_1610_CAM_RSTZ,
6838+ Y15_1610_CAM_OUTCLK,
6839+
6840+ /* serial camera */
6841+ H19_1610_CAM_EXCLK,
6842+ Y12_1610_CCP_CLKP,
6843+ W13_1610_CCP_CLKM,
6844+ W14_1610_CCP_DATAP,
6845+ Y14_1610_CCP_DATAM,
6846+
6847+};
6848+
6849+enum omap24xx_index {
6850+ /* 24xx I2C */
6851+ M19_24XX_I2C1_SCL,
6852+ L15_24XX_I2C1_SDA,
6853+ J15_24XX_I2C2_SCL,
6854+ H19_24XX_I2C2_SDA,
6855+
6856+ /* 24xx Menelaus interrupt */
6857+ W19_24XX_SYS_NIRQ,
6858+
6859+ /* 24xx clock */
6860+ W14_24XX_SYS_CLKOUT,
6861+
6862+ /* 24xx GPMC chipselects, wait pin monitoring */
6863+ E2_GPMC_NCS2,
6864+ L2_GPMC_NCS7,
6865+ L3_GPMC_WAIT0,
6866+ N7_GPMC_WAIT1,
6867+ M1_GPMC_WAIT2,
6868+ P1_GPMC_WAIT3,
6869+
6870+ /* 242X McBSP */
6871+ Y15_24XX_MCBSP2_CLKX,
6872+ R14_24XX_MCBSP2_FSX,
6873+ W15_24XX_MCBSP2_DR,
6874+ V15_24XX_MCBSP2_DX,
6875+
6876+ /* 24xx GPIO */
6877+ M21_242X_GPIO11,
6878+ P21_242X_GPIO12,
6879+ AA10_242X_GPIO13,
6880+ AA6_242X_GPIO14,
6881+ AA4_242X_GPIO15,
6882+ Y11_242X_GPIO16,
6883+ AA12_242X_GPIO17,
6884+ AA8_242X_GPIO58,
6885+ Y20_24XX_GPIO60,
6886+ W4__24XX_GPIO74,
6887+ N15_24XX_GPIO85,
6888+ M15_24XX_GPIO92,
6889+ P20_24XX_GPIO93,
6890+ P18_24XX_GPIO95,
6891+ M18_24XX_GPIO96,
6892+ L14_24XX_GPIO97,
6893+ J15_24XX_GPIO99,
6894+ V14_24XX_GPIO117,
6895+ P14_24XX_GPIO125,
6896+
6897+ /* 242x DBG GPIO */
6898+ V4_242X_GPIO49,
6899+ W2_242X_GPIO50,
6900+ U4_242X_GPIO51,
6901+ V3_242X_GPIO52,
6902+ V2_242X_GPIO53,
6903+ V6_242X_GPIO53,
6904+ T4_242X_GPIO54,
6905+ Y4_242X_GPIO54,
6906+ T3_242X_GPIO55,
6907+ U2_242X_GPIO56,
6908+
6909+ /* 24xx external DMA requests */
6910+ AA10_242X_DMAREQ0,
6911+ AA6_242X_DMAREQ1,
6912+ E4_242X_DMAREQ2,
6913+ G4_242X_DMAREQ3,
6914+ D3_242X_DMAREQ4,
6915+ E3_242X_DMAREQ5,
6916+
6917+ /* UART3 */
6918+ K15_24XX_UART3_TX,
6919+ K14_24XX_UART3_RX,
6920+
6921+ /* MMC/SDIO */
6922+ G19_24XX_MMC_CLKO,
6923+ H18_24XX_MMC_CMD,
6924+ F20_24XX_MMC_DAT0,
6925+ H14_24XX_MMC_DAT1,
6926+ E19_24XX_MMC_DAT2,
6927+ D19_24XX_MMC_DAT3,
6928+ F19_24XX_MMC_DAT_DIR0,
6929+ E20_24XX_MMC_DAT_DIR1,
6930+ F18_24XX_MMC_DAT_DIR2,
6931+ E18_24XX_MMC_DAT_DIR3,
6932+ G18_24XX_MMC_CMD_DIR,
6933+ H15_24XX_MMC_CLKI,
6934+
6935+ /* Full speed USB */
6936+ J20_24XX_USB0_PUEN,
6937+ J19_24XX_USB0_VP,
6938+ K20_24XX_USB0_VM,
6939+ J18_24XX_USB0_RCV,
6940+ K19_24XX_USB0_TXEN,
6941+ J14_24XX_USB0_SE0,
6942+ K18_24XX_USB0_DAT,
6943+
6944+ N14_24XX_USB1_SE0,
6945+ W12_24XX_USB1_SE0,
6946+ P15_24XX_USB1_DAT,
6947+ R13_24XX_USB1_DAT,
6948+ W20_24XX_USB1_TXEN,
6949+ P13_24XX_USB1_TXEN,
6950+ V19_24XX_USB1_RCV,
6951+ V12_24XX_USB1_RCV,
6952+
6953+ AA10_24XX_USB2_SE0,
6954+ Y11_24XX_USB2_DAT,
6955+ AA12_24XX_USB2_TXEN,
6956+ AA6_24XX_USB2_RCV,
6957+ AA4_24XX_USB2_TLLSE0,
6958+
6959+ /* Keypad GPIO*/
6960+ T19_24XX_KBR0,
6961+ R19_24XX_KBR1,
6962+ V18_24XX_KBR2,
6963+ M21_24XX_KBR3,
6964+ E5__24XX_KBR4,
6965+ M18_24XX_KBR5,
6966+ R20_24XX_KBC0,
6967+ M14_24XX_KBC1,
6968+ H19_24XX_KBC2,
6969+ V17_24XX_KBC3,
6970+ P21_24XX_KBC4,
6971+ L14_24XX_KBC5,
6972+ N19_24XX_KBC6,
6973+
6974+ /* 24xx Menelaus Keypad GPIO */
6975+ B3__24XX_KBR5,
6976+ AA4_24XX_KBC2,
6977+ B13_24XX_KBC6,
6978+
6979+ /* 2430 USB */
6980+ AD9_2430_USB0_PUEN,
6981+ Y11_2430_USB0_VP,
6982+ AD7_2430_USB0_VM,
6983+ AE7_2430_USB0_RCV,
6984+ AD4_2430_USB0_TXEN,
6985+ AF9_2430_USB0_SE0,
6986+ AE6_2430_USB0_DAT,
6987+ AD24_2430_USB1_SE0,
6988+ AB24_2430_USB1_RCV,
6989+ Y25_2430_USB1_TXEN,
6990+ AA26_2430_USB1_DAT,
6991+
6992+ /* 2430 HS-USB */
6993+ AD9_2430_USB0HS_DATA3,
6994+ Y11_2430_USB0HS_DATA4,
6995+ AD7_2430_USB0HS_DATA5,
6996+ AE7_2430_USB0HS_DATA6,
6997+ AD4_2430_USB0HS_DATA2,
6998+ AF9_2430_USB0HS_DATA0,
6999+ AE6_2430_USB0HS_DATA1,
7000+ AE8_2430_USB0HS_CLK,
7001+ AD8_2430_USB0HS_DIR,
7002+ AE5_2430_USB0HS_STP,
7003+ AE9_2430_USB0HS_NXT,
7004+ AC7_2430_USB0HS_DATA7,
7005+
7006+ /* 2430 McBSP */
7007+ AD6_2430_MCBSP_CLKS,
7008+
7009+ AB2_2430_MCBSP1_CLKR,
7010+ AD5_2430_MCBSP1_FSR,
7011+ AA1_2430_MCBSP1_DX,
7012+ AF3_2430_MCBSP1_DR,
7013+ AB3_2430_MCBSP1_FSX,
7014+ Y9_2430_MCBSP1_CLKX,
7015+
7016+ AC10_2430_MCBSP2_FSX,
7017+ AD16_2430_MCBSP2_CLX,
7018+ AE13_2430_MCBSP2_DX,
7019+ AD13_2430_MCBSP2_DR,
7020+ AC10_2430_MCBSP2_FSX_OFF,
7021+ AD16_2430_MCBSP2_CLX_OFF,
7022+ AE13_2430_MCBSP2_DX_OFF,
7023+ AD13_2430_MCBSP2_DR_OFF,
7024+
7025+ AC9_2430_MCBSP3_CLKX,
7026+ AE4_2430_MCBSP3_FSX,
7027+ AE2_2430_MCBSP3_DR,
7028+ AF4_2430_MCBSP3_DX,
7029+
7030+ N3_2430_MCBSP4_CLKX,
7031+ AD23_2430_MCBSP4_DR,
7032+ AB25_2430_MCBSP4_DX,
7033+ AC25_2430_MCBSP4_FSX,
7034+
7035+ AE16_2430_MCBSP5_CLKX,
7036+ AF12_2430_MCBSP5_FSX,
7037+ K7_2430_MCBSP5_DX,
7038+ M1_2430_MCBSP5_DR,
7039+
7040+ /* 2430 McSPI*/
7041+ Y18_2430_MCSPI1_CLK,
7042+ AD15_2430_MCSPI1_SIMO,
7043+ AE17_2430_MCSPI1_SOMI,
7044+ U1_2430_MCSPI1_CS0,
7045+
7046+ /* Touchscreen GPIO */
7047+ AF19_2430_GPIO_85,
7048+
7049+};
7050+
7051+struct omap_mux_cfg {
7052+ struct pin_config *pins;
7053+ unsigned long size;
7054+ int (*cfg_reg)(const struct pin_config *cfg);
7055+};
7056+
7057+#ifdef CONFIG_OMAP_MUX
7058+/* setup pin muxing in Linux */
7059+extern int omap1_mux_init(void);
7060+extern int omap_mux_register(struct omap_mux_cfg *);
7061+extern int omap_cfg_reg(unsigned long reg_cfg);
7062+#else
7063+/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
7064+static inline int omap1_mux_init(void) { return 0; }
7065+static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
7066+#endif
7067+
7068+extern int omap2_mux_init(void);
7069+
7070+#endif
7071Index: linux-2.6.35/arch/arm/plat-omap/include/mach/nand.h
7072===================================================================
7073--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7074@@ -0,0 +1,24 @@
7075+/*
7076+ * arch/arm/plat-omap/include/mach/nand.h
7077+ *
7078+ * Copyright (C) 2006 Micron Technology Inc.
7079+ *
7080+ * This program is free software; you can redistribute it and/or modify
7081+ * it under the terms of the GNU General Public License version 2 as
7082+ * published by the Free Software Foundation.
7083+ */
7084+
7085+#include <linux/mtd/partitions.h>
7086+
7087+struct omap_nand_platform_data {
7088+ unsigned int options;
7089+ int cs;
7090+ int gpio_irq;
7091+ struct mtd_partition *parts;
7092+ int nr_parts;
7093+ int (*nand_setup)(void __iomem *);
7094+ int (*dev_ready)(struct omap_nand_platform_data *);
7095+ int dma_channel;
7096+ void __iomem *gpmc_cs_baseaddr;
7097+ void __iomem *gpmc_baseaddr;
7098+};
7099Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap1510.h
7100===================================================================
7101--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7102@@ -0,0 +1,50 @@
7103+/* arch/arm/plat-omap/include/mach/omap1510.h
7104+ *
7105+ * Hardware definitions for TI OMAP1510 processor.
7106+ *
7107+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7108+ *
7109+ * This program is free software; you can redistribute it and/or modify it
7110+ * under the terms of the GNU General Public License as published by the
7111+ * Free Software Foundation; either version 2 of the License, or (at your
7112+ * option) any later version.
7113+ *
7114+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7115+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7116+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7117+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7118+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7119+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7120+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7121+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7122+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7123+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7124+ *
7125+ * You should have received a copy of the GNU General Public License along
7126+ * with this program; if not, write to the Free Software Foundation, Inc.,
7127+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7128+ */
7129+
7130+#ifndef __ASM_ARCH_OMAP15XX_H
7131+#define __ASM_ARCH_OMAP15XX_H
7132+
7133+/*
7134+ * ----------------------------------------------------------------------------
7135+ * Base addresses
7136+ * ----------------------------------------------------------------------------
7137+ */
7138+
7139+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7140+
7141+#define OMAP1510_DSP_BASE 0xE0000000
7142+#define OMAP1510_DSP_SIZE 0x28000
7143+#define OMAP1510_DSP_START 0xE0000000
7144+
7145+#define OMAP1510_DSPREG_BASE 0xE1000000
7146+#define OMAP1510_DSPREG_SIZE SZ_128K
7147+#define OMAP1510_DSPREG_START 0xE1000000
7148+
7149+#define OMAP1510_DSP_MMU_BASE (0xfffed200)
7150+
7151+#endif /* __ASM_ARCH_OMAP15XX_H */
7152+
7153Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap16xx.h
7154===================================================================
7155--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7156@@ -0,0 +1,202 @@
7157+/* arch/arm/plat-omap/include/mach/omap16xx.h
7158+ *
7159+ * Hardware definitions for TI OMAP1610/5912/1710 processors.
7160+ *
7161+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7162+ *
7163+ * This program is free software; you can redistribute it and/or modify it
7164+ * under the terms of the GNU General Public License as published by the
7165+ * Free Software Foundation; either version 2 of the License, or (at your
7166+ * option) any later version.
7167+ *
7168+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7169+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7170+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7171+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7172+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7173+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7174+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7175+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7176+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7177+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7178+ *
7179+ * You should have received a copy of the GNU General Public License along
7180+ * with this program; if not, write to the Free Software Foundation, Inc.,
7181+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7182+ */
7183+
7184+#ifndef __ASM_ARCH_OMAP16XX_H
7185+#define __ASM_ARCH_OMAP16XX_H
7186+
7187+/*
7188+ * ----------------------------------------------------------------------------
7189+ * Base addresses
7190+ * ----------------------------------------------------------------------------
7191+ */
7192+
7193+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7194+
7195+#define OMAP16XX_DSP_BASE 0xE0000000
7196+#define OMAP16XX_DSP_SIZE 0x28000
7197+#define OMAP16XX_DSP_START 0xE0000000
7198+
7199+#define OMAP16XX_DSPREG_BASE 0xE1000000
7200+#define OMAP16XX_DSPREG_SIZE SZ_128K
7201+#define OMAP16XX_DSPREG_START 0xE1000000
7202+
7203+#define OMAP16XX_SEC_BASE 0xFFFE4000
7204+#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
7205+#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
7206+#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
7207+
7208+/*
7209+ * ---------------------------------------------------------------------------
7210+ * Interrupts
7211+ * ---------------------------------------------------------------------------
7212+ */
7213+#define OMAP_IH2_0_BASE (0xfffe0000)
7214+#define OMAP_IH2_1_BASE (0xfffe0100)
7215+#define OMAP_IH2_2_BASE (0xfffe0200)
7216+#define OMAP_IH2_3_BASE (0xfffe0300)
7217+
7218+#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
7219+#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
7220+#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
7221+#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
7222+#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
7223+#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
7224+#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
7225+
7226+#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
7227+#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
7228+#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
7229+#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
7230+#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
7231+#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
7232+#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
7233+
7234+#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
7235+#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
7236+#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
7237+#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
7238+#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
7239+#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
7240+#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
7241+
7242+#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
7243+#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
7244+#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
7245+#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
7246+#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
7247+#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
7248+#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
7249+
7250+/*
7251+ * ----------------------------------------------------------------------------
7252+ * Clocks
7253+ * ----------------------------------------------------------------------------
7254+ */
7255+#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
7256+
7257+/*
7258+ * ----------------------------------------------------------------------------
7259+ * Pin configuration registers
7260+ * ----------------------------------------------------------------------------
7261+ */
7262+#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
7263+#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
7264+#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
7265+#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
7266+#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
7267+
7268+/*
7269+ * ----------------------------------------------------------------------------
7270+ * System control registers
7271+ * ----------------------------------------------------------------------------
7272+ */
7273+#define OMAP1610_RESET_CONTROL 0xfffe1140
7274+
7275+/*
7276+ * ---------------------------------------------------------------------------
7277+ * TIPB bus interface
7278+ * ---------------------------------------------------------------------------
7279+ */
7280+#define TIPB_SWITCH_BASE (0xfffbc800)
7281+#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
7282+
7283+/* UART3 Registers Mapping through MPU bus */
7284+#define UART3_RHR (OMAP_UART3_BASE + 0)
7285+#define UART3_THR (OMAP_UART3_BASE + 0)
7286+#define UART3_DLL (OMAP_UART3_BASE + 0)
7287+#define UART3_IER (OMAP_UART3_BASE + 4)
7288+#define UART3_DLH (OMAP_UART3_BASE + 4)
7289+#define UART3_IIR (OMAP_UART3_BASE + 8)
7290+#define UART3_FCR (OMAP_UART3_BASE + 8)
7291+#define UART3_EFR (OMAP_UART3_BASE + 8)
7292+#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
7293+#define UART3_MCR (OMAP_UART3_BASE + 0x10)
7294+#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
7295+#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
7296+#define UART3_LSR (OMAP_UART3_BASE + 0x14)
7297+#define UART3_TCR (OMAP_UART3_BASE + 0x18)
7298+#define UART3_MSR (OMAP_UART3_BASE + 0x18)
7299+#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
7300+#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
7301+#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
7302+#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
7303+#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
7304+#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
7305+#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
7306+#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
7307+#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
7308+#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
7309+#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
7310+#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
7311+#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
7312+#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
7313+#define UART3_BLR (OMAP_UART3_BASE + 0x38)
7314+#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
7315+#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
7316+#define UART3_SCR (OMAP_UART3_BASE + 0x40)
7317+#define UART3_SSR (OMAP_UART3_BASE + 0x44)
7318+#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
7319+#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
7320+#define UART3_MVR (OMAP_UART3_BASE + 0x50)
7321+
7322+/*
7323+ * ---------------------------------------------------------------------------
7324+ * Watchdog timer
7325+ * ---------------------------------------------------------------------------
7326+ */
7327+
7328+/* 32-bit Watchdog timer in OMAP 16XX */
7329+#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
7330+#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
7331+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
7332+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
7333+#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
7334+#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
7335+#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
7336+#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
7337+#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
7338+#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
7339+
7340+#define WCLR_PRE_SHIFT 5
7341+#define WCLR_PTV_SHIFT 2
7342+
7343+#define WWPS_W_PEND_WSPR (1 << 4)
7344+#define WWPS_W_PEND_WTGR (1 << 3)
7345+#define WWPS_W_PEND_WLDR (1 << 2)
7346+#define WWPS_W_PEND_WCRR (1 << 1)
7347+#define WWPS_W_PEND_WCLR (1 << 0)
7348+
7349+#define WSPR_ENABLE_0 (0x0000bbbb)
7350+#define WSPR_ENABLE_1 (0x00004444)
7351+#define WSPR_DISABLE_0 (0x0000aaaa)
7352+#define WSPR_DISABLE_1 (0x00005555)
7353+
7354+#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
7355+#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
7356+
7357+#endif /* __ASM_ARCH_OMAP16XX_H */
7358+
7359Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap24xx.h
7360===================================================================
7361--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7362@@ -0,0 +1,89 @@
7363+/*
7364+ * arch/arm/plat-omap/include/mach/omap24xx.h
7365+ *
7366+ * This file contains the processor specific definitions
7367+ * of the TI OMAP24XX.
7368+ *
7369+ * Copyright (C) 2007 Texas Instruments.
7370+ * Copyright (C) 2007 Nokia Corporation.
7371+ *
7372+ * This program is free software; you can redistribute it and/or modify
7373+ * it under the terms of the GNU General Public License as published by
7374+ * the Free Software Foundation; either version 2 of the License, or
7375+ * (at your option) any later version.
7376+ *
7377+ * This program is distributed in the hope that it will be useful,
7378+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7379+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7380+ * GNU General Public License for more details.
7381+ *
7382+ * You should have received a copy of the GNU General Public License
7383+ * along with this program; if not, write to the Free Software
7384+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7385+ *
7386+ */
7387+
7388+#ifndef __ASM_ARCH_OMAP24XX_H
7389+#define __ASM_ARCH_OMAP24XX_H
7390+
7391+/*
7392+ * Please place only base defines here and put the rest in device
7393+ * specific headers. Note also that some of these defines are needed
7394+ * for omap1 to compile without adding ifdefs.
7395+ */
7396+
7397+#define L4_24XX_BASE 0x48000000
7398+#define L4_WK_243X_BASE 0x49000000
7399+#define L3_24XX_BASE 0x68000000
7400+
7401+/* interrupt controller */
7402+#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
7403+#define OMAP24XX_IVA_INTC_BASE 0x40000000
7404+
7405+#define OMAP2420_CTRL_BASE L4_24XX_BASE
7406+#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
7407+#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
7408+#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
7409+#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
7410+#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
7411+#define OMAP2420_SMS_BASE 0x68008000
7412+#define OMAP2420_GPMC_BASE 0x6800a000
7413+
7414+#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
7415+#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
7416+#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
7417+#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
7418+
7419+#define OMAP243X_SMS_BASE 0x6C000000
7420+#define OMAP243X_SDRC_BASE 0x6D000000
7421+#define OMAP243X_GPMC_BASE 0x6E000000
7422+#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
7423+#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
7424+#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
7425+
7426+/* DSP SS */
7427+#define OMAP2420_DSP_BASE 0x58000000
7428+#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
7429+#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
7430+#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
7431+
7432+#define OMAP243X_DSP_BASE 0x5C000000
7433+#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
7434+#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
7435+
7436+/* Mailbox */
7437+#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
7438+
7439+/* Camera */
7440+#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
7441+
7442+/* Security */
7443+#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
7444+#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
7445+#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
7446+#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
7447+#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
7448+#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
7449+
7450+#endif /* __ASM_ARCH_OMAP24XX_H */
7451+
7452Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap34xx.h
7453===================================================================
7454--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7455@@ -0,0 +1,86 @@
7456+/*
7457+ * arch/arm/plat-omap/include/mach/omap34xx.h
7458+ *
7459+ * This file contains the processor specific definitions of the TI OMAP34XX.
7460+ *
7461+ * Copyright (C) 2007 Texas Instruments.
7462+ * Copyright (C) 2007 Nokia Corporation.
7463+ *
7464+ * This program is free software; you can redistribute it and/or modify
7465+ * it under the terms of the GNU General Public License as published by
7466+ * the Free Software Foundation; either version 2 of the License, or
7467+ * (at your option) any later version.
7468+ *
7469+ * This program is distributed in the hope that it will be useful,
7470+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7471+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7472+ * GNU General Public License for more details.
7473+ *
7474+ * You should have received a copy of the GNU General Public License
7475+ * along with this program; if not, write to the Free Software
7476+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7477+ */
7478+
7479+#ifndef __ASM_ARCH_OMAP34XX_H
7480+#define __ASM_ARCH_OMAP34XX_H
7481+
7482+/*
7483+ * Please place only base defines here and put the rest in device
7484+ * specific headers.
7485+ */
7486+
7487+#define L4_34XX_BASE 0x48000000
7488+#define L4_WK_34XX_BASE 0x48300000
7489+#define L4_PER_34XX_BASE 0x49000000
7490+#define L4_EMU_34XX_BASE 0x54000000
7491+#define L3_34XX_BASE 0x68000000
7492+
7493+#define OMAP3430_32KSYNCT_BASE 0x48320000
7494+#define OMAP3430_CM_BASE 0x48004800
7495+#define OMAP3430_PRM_BASE 0x48306800
7496+#define OMAP343X_SMS_BASE 0x6C000000
7497+#define OMAP343X_SDRC_BASE 0x6D000000
7498+#define OMAP34XX_GPMC_BASE 0x6E000000
7499+#define OMAP343X_SCM_BASE 0x48002000
7500+#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
7501+
7502+#define OMAP34XX_IC_BASE 0x48200000
7503+
7504+#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
7505+#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
7506+#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
7507+#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
7508+#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
7509+#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
7510+#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
7511+#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
7512+#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
7513+#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
7514+#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
7515+#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
7516+
7517+#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
7518+#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
7519+#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
7520+#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
7521+#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
7522+#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
7523+#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
7524+#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
7525+#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
7526+#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
7527+#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
7528+#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
7529+
7530+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
7531+#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
7532+#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
7533+#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
7534+#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
7535+#define OMAP34XX_SR1_BASE 0x480C9000
7536+#define OMAP34XX_SR2_BASE 0x480CB000
7537+
7538+#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
7539+
7540+#endif /* __ASM_ARCH_OMAP34XX_H */
7541+
7542Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap44xx.h
7543===================================================================
7544--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7545@@ -0,0 +1,48 @@
7546+/*:
7547+ * Address mappings and base address for OMAP4 interconnects
7548+ * and peripherals.
7549+ *
7550+ * Copyright (C) 2009 Texas Instruments
7551+ *
7552+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7553+ *
7554+ * This program is free software; you can redistribute it and/or modify
7555+ * it under the terms of the GNU General Public License version 2 as
7556+ * published by the Free Software Foundation.
7557+ */
7558+#ifndef __ASM_ARCH_OMAP44XX_H
7559+#define __ASM_ARCH_OMAP44XX_H
7560+
7561+/*
7562+ * Please place only base defines here and put the rest in device
7563+ * specific headers.
7564+ */
7565+#define L4_44XX_BASE 0x4a000000
7566+#define L4_WK_44XX_BASE 0x4a300000
7567+#define L4_PER_44XX_BASE 0x48000000
7568+#define L4_EMU_44XX_BASE 0x54000000
7569+#define L3_44XX_BASE 0x44000000
7570+#define OMAP44XX_EMIF1_BASE 0x4c000000
7571+#define OMAP44XX_EMIF2_BASE 0x4d000000
7572+#define OMAP44XX_DMM_BASE 0x4e000000
7573+#define OMAP4430_32KSYNCT_BASE 0x4a304000
7574+#define OMAP4430_CM1_BASE 0x4a004000
7575+#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
7576+#define OMAP4430_CM2_BASE 0x4a008000
7577+#define OMAP4430_PRM_BASE 0x4a306000
7578+#define OMAP44XX_GPMC_BASE 0x50000000
7579+#define OMAP443X_SCM_BASE 0x4a002000
7580+#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
7581+#define OMAP44XX_IC_BASE 0x48200000
7582+#define OMAP44XX_IVA_INTC_BASE 0x40000000
7583+#define IRQ_SIR_IRQ 0x0040
7584+#define OMAP44XX_GIC_DIST_BASE 0x48241000
7585+#define OMAP44XX_GIC_CPU_BASE 0x48240100
7586+#define OMAP44XX_SCU_BASE 0x48240000
7587+#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
7588+#define OMAP44XX_WKUPGEN_BASE 0x48281000
7589+
7590+#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
7591+
7592+#endif /* __ASM_ARCH_OMAP44XX_H */
7593+
7594Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap730.h
7595===================================================================
7596--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7597@@ -0,0 +1,102 @@
7598+/* arch/arm/plat-omap/include/mach/omap730.h
7599+ *
7600+ * Hardware definitions for TI OMAP730 processor.
7601+ *
7602+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7603+ *
7604+ * This program is free software; you can redistribute it and/or modify it
7605+ * under the terms of the GNU General Public License as published by the
7606+ * Free Software Foundation; either version 2 of the License, or (at your
7607+ * option) any later version.
7608+ *
7609+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7610+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7611+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7612+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7613+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7614+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7615+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7616+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7617+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7618+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7619+ *
7620+ * You should have received a copy of the GNU General Public License along
7621+ * with this program; if not, write to the Free Software Foundation, Inc.,
7622+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7623+ */
7624+
7625+#ifndef __ASM_ARCH_OMAP730_H
7626+#define __ASM_ARCH_OMAP730_H
7627+
7628+/*
7629+ * ----------------------------------------------------------------------------
7630+ * Base addresses
7631+ * ----------------------------------------------------------------------------
7632+ */
7633+
7634+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7635+
7636+#define OMAP730_DSP_BASE 0xE0000000
7637+#define OMAP730_DSP_SIZE 0x50000
7638+#define OMAP730_DSP_START 0xE0000000
7639+
7640+#define OMAP730_DSPREG_BASE 0xE1000000
7641+#define OMAP730_DSPREG_SIZE SZ_128K
7642+#define OMAP730_DSPREG_START 0xE1000000
7643+
7644+/*
7645+ * ----------------------------------------------------------------------------
7646+ * OMAP730 specific configuration registers
7647+ * ----------------------------------------------------------------------------
7648+ */
7649+#define OMAP730_CONFIG_BASE 0xfffe1000
7650+#define OMAP730_IO_CONF_0 0xfffe1070
7651+#define OMAP730_IO_CONF_1 0xfffe1074
7652+#define OMAP730_IO_CONF_2 0xfffe1078
7653+#define OMAP730_IO_CONF_3 0xfffe107c
7654+#define OMAP730_IO_CONF_4 0xfffe1080
7655+#define OMAP730_IO_CONF_5 0xfffe1084
7656+#define OMAP730_IO_CONF_6 0xfffe1088
7657+#define OMAP730_IO_CONF_7 0xfffe108c
7658+#define OMAP730_IO_CONF_8 0xfffe1090
7659+#define OMAP730_IO_CONF_9 0xfffe1094
7660+#define OMAP730_IO_CONF_10 0xfffe1098
7661+#define OMAP730_IO_CONF_11 0xfffe109c
7662+#define OMAP730_IO_CONF_12 0xfffe10a0
7663+#define OMAP730_IO_CONF_13 0xfffe10a4
7664+
7665+#define OMAP730_MODE_1 0xfffe1010
7666+#define OMAP730_MODE_2 0xfffe1014
7667+
7668+/* CSMI specials: in terms of base + offset */
7669+#define OMAP730_MODE2_OFFSET 0x14
7670+
7671+/*
7672+ * ----------------------------------------------------------------------------
7673+ * OMAP730 traffic controller configuration registers
7674+ * ----------------------------------------------------------------------------
7675+ */
7676+#define OMAP730_FLASH_CFG_0 0xfffecc10
7677+#define OMAP730_FLASH_ACFG_0 0xfffecc50
7678+#define OMAP730_FLASH_CFG_1 0xfffecc14
7679+#define OMAP730_FLASH_ACFG_1 0xfffecc54
7680+
7681+/*
7682+ * ----------------------------------------------------------------------------
7683+ * OMAP730 DSP control registers
7684+ * ----------------------------------------------------------------------------
7685+ */
7686+#define OMAP730_ICR_BASE 0xfffbb800
7687+#define OMAP730_DSP_M_CTL 0xfffbb804
7688+#define OMAP730_DSP_MMU_BASE 0xfffed200
7689+
7690+/*
7691+ * ----------------------------------------------------------------------------
7692+ * OMAP730 PCC_UPLD configuration registers
7693+ * ----------------------------------------------------------------------------
7694+ */
7695+#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
7696+#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
7697+
7698+#endif /* __ASM_ARCH_OMAP730_H */
7699+
7700Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap7xx.h
7701===================================================================
7702--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7703@@ -0,0 +1,104 @@
7704+/* arch/arm/plat-omap/include/mach/omap7xx.h
7705+ *
7706+ * Hardware definitions for TI OMAP7XX processor.
7707+ *
7708+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7709+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7710+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
7711+ *
7712+ * This program is free software; you can redistribute it and/or modify it
7713+ * under the terms of the GNU General Public License as published by the
7714+ * Free Software Foundation; either version 2 of the License, or (at your
7715+ * option) any later version.
7716+ *
7717+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7718+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7719+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7720+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7721+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7722+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7723+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7724+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7725+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7726+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7727+ *
7728+ * You should have received a copy of the GNU General Public License along
7729+ * with this program; if not, write to the Free Software Foundation, Inc.,
7730+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7731+ */
7732+
7733+#ifndef __ASM_ARCH_OMAP7XX_H
7734+#define __ASM_ARCH_OMAP7XX_H
7735+
7736+/*
7737+ * ----------------------------------------------------------------------------
7738+ * Base addresses
7739+ * ----------------------------------------------------------------------------
7740+ */
7741+
7742+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7743+
7744+#define OMAP7XX_DSP_BASE 0xE0000000
7745+#define OMAP7XX_DSP_SIZE 0x50000
7746+#define OMAP7XX_DSP_START 0xE0000000
7747+
7748+#define OMAP7XX_DSPREG_BASE 0xE1000000
7749+#define OMAP7XX_DSPREG_SIZE SZ_128K
7750+#define OMAP7XX_DSPREG_START 0xE1000000
7751+
7752+/*
7753+ * ----------------------------------------------------------------------------
7754+ * OMAP7XX specific configuration registers
7755+ * ----------------------------------------------------------------------------
7756+ */
7757+#define OMAP7XX_CONFIG_BASE 0xfffe1000
7758+#define OMAP7XX_IO_CONF_0 0xfffe1070
7759+#define OMAP7XX_IO_CONF_1 0xfffe1074
7760+#define OMAP7XX_IO_CONF_2 0xfffe1078
7761+#define OMAP7XX_IO_CONF_3 0xfffe107c
7762+#define OMAP7XX_IO_CONF_4 0xfffe1080
7763+#define OMAP7XX_IO_CONF_5 0xfffe1084
7764+#define OMAP7XX_IO_CONF_6 0xfffe1088
7765+#define OMAP7XX_IO_CONF_7 0xfffe108c
7766+#define OMAP7XX_IO_CONF_8 0xfffe1090
7767+#define OMAP7XX_IO_CONF_9 0xfffe1094
7768+#define OMAP7XX_IO_CONF_10 0xfffe1098
7769+#define OMAP7XX_IO_CONF_11 0xfffe109c
7770+#define OMAP7XX_IO_CONF_12 0xfffe10a0
7771+#define OMAP7XX_IO_CONF_13 0xfffe10a4
7772+
7773+#define OMAP7XX_MODE_1 0xfffe1010
7774+#define OMAP7XX_MODE_2 0xfffe1014
7775+
7776+/* CSMI specials: in terms of base + offset */
7777+#define OMAP7XX_MODE2_OFFSET 0x14
7778+
7779+/*
7780+ * ----------------------------------------------------------------------------
7781+ * OMAP7XX traffic controller configuration registers
7782+ * ----------------------------------------------------------------------------
7783+ */
7784+#define OMAP7XX_FLASH_CFG_0 0xfffecc10
7785+#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
7786+#define OMAP7XX_FLASH_CFG_1 0xfffecc14
7787+#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
7788+
7789+/*
7790+ * ----------------------------------------------------------------------------
7791+ * OMAP7XX DSP control registers
7792+ * ----------------------------------------------------------------------------
7793+ */
7794+#define OMAP7XX_ICR_BASE 0xfffbb800
7795+#define OMAP7XX_DSP_M_CTL 0xfffbb804
7796+#define OMAP7XX_DSP_MMU_BASE 0xfffed200
7797+
7798+/*
7799+ * ----------------------------------------------------------------------------
7800+ * OMAP7XX PCC_UPLD configuration registers
7801+ * ----------------------------------------------------------------------------
7802+ */
7803+#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
7804+#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
7805+
7806+#endif /* __ASM_ARCH_OMAP7XX_H */
7807+
7808Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap850.h
7809===================================================================
7810--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7811@@ -0,0 +1,102 @@
7812+/* arch/arm/plat-omap/include/mach/omap850.h
7813+ *
7814+ * Hardware definitions for TI OMAP850 processor.
7815+ *
7816+ * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
7817+ *
7818+ * This program is free software; you can redistribute it and/or modify it
7819+ * under the terms of the GNU General Public License as published by the
7820+ * Free Software Foundation; either version 2 of the License, or (at your
7821+ * option) any later version.
7822+ *
7823+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7824+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7825+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7826+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7827+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7828+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7829+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7830+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7831+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7832+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7833+ *
7834+ * You should have received a copy of the GNU General Public License along
7835+ * with this program; if not, write to the Free Software Foundation, Inc.,
7836+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7837+ */
7838+
7839+#ifndef __ASM_ARCH_OMAP850_H
7840+#define __ASM_ARCH_OMAP850_H
7841+
7842+/*
7843+ * ----------------------------------------------------------------------------
7844+ * Base addresses
7845+ * ----------------------------------------------------------------------------
7846+ */
7847+
7848+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7849+
7850+#define OMAP850_DSP_BASE 0xE0000000
7851+#define OMAP850_DSP_SIZE 0x50000
7852+#define OMAP850_DSP_START 0xE0000000
7853+
7854+#define OMAP850_DSPREG_BASE 0xE1000000
7855+#define OMAP850_DSPREG_SIZE SZ_128K
7856+#define OMAP850_DSPREG_START 0xE1000000
7857+
7858+/*
7859+ * ----------------------------------------------------------------------------
7860+ * OMAP850 specific configuration registers
7861+ * ----------------------------------------------------------------------------
7862+ */
7863+#define OMAP850_CONFIG_BASE 0xfffe1000
7864+#define OMAP850_IO_CONF_0 0xfffe1070
7865+#define OMAP850_IO_CONF_1 0xfffe1074
7866+#define OMAP850_IO_CONF_2 0xfffe1078
7867+#define OMAP850_IO_CONF_3 0xfffe107c
7868+#define OMAP850_IO_CONF_4 0xfffe1080
7869+#define OMAP850_IO_CONF_5 0xfffe1084
7870+#define OMAP850_IO_CONF_6 0xfffe1088
7871+#define OMAP850_IO_CONF_7 0xfffe108c
7872+#define OMAP850_IO_CONF_8 0xfffe1090
7873+#define OMAP850_IO_CONF_9 0xfffe1094
7874+#define OMAP850_IO_CONF_10 0xfffe1098
7875+#define OMAP850_IO_CONF_11 0xfffe109c
7876+#define OMAP850_IO_CONF_12 0xfffe10a0
7877+#define OMAP850_IO_CONF_13 0xfffe10a4
7878+
7879+#define OMAP850_MODE_1 0xfffe1010
7880+#define OMAP850_MODE_2 0xfffe1014
7881+
7882+/* CSMI specials: in terms of base + offset */
7883+#define OMAP850_MODE2_OFFSET 0x14
7884+
7885+/*
7886+ * ----------------------------------------------------------------------------
7887+ * OMAP850 traffic controller configuration registers
7888+ * ----------------------------------------------------------------------------
7889+ */
7890+#define OMAP850_FLASH_CFG_0 0xfffecc10
7891+#define OMAP850_FLASH_ACFG_0 0xfffecc50
7892+#define OMAP850_FLASH_CFG_1 0xfffecc14
7893+#define OMAP850_FLASH_ACFG_1 0xfffecc54
7894+
7895+/*
7896+ * ----------------------------------------------------------------------------
7897+ * OMAP850 DSP control registers
7898+ * ----------------------------------------------------------------------------
7899+ */
7900+#define OMAP850_ICR_BASE 0xfffbb800
7901+#define OMAP850_DSP_M_CTL 0xfffbb804
7902+#define OMAP850_DSP_MMU_BASE 0xfffed200
7903+
7904+/*
7905+ * ----------------------------------------------------------------------------
7906+ * OMAP850 PCC_UPLD configuration registers
7907+ * ----------------------------------------------------------------------------
7908+ */
7909+#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
7910+#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
7911+
7912+#endif /* __ASM_ARCH_OMAP850_H */
7913+
7914Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap-alsa.h
7915===================================================================
7916--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7917@@ -0,0 +1,123 @@
7918+/*
7919+ * arch/arm/plat-omap/include/mach/omap-alsa.h
7920+ *
7921+ * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
7922+ *
7923+ * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7924+ *
7925+ * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
7926+ * Written by Daniel Petrini, David Cohen, Anderson Briglia
7927+ * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
7928+ *
7929+ * This program is free software; you can redistribute it and/or modify it
7930+ * under the terms of the GNU General Public License as published by the
7931+ * Free Software Foundation; either version 2 of the License, or (at your
7932+ * option) any later version.
7933+ *
7934+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7935+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7936+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7937+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7938+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7939+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7940+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7941+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7942+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7943+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7944+ *
7945+ * You should have received a copy of the GNU General Public License along
7946+ * with this program; if not, write to the Free Software Foundation, Inc.,
7947+ * 675 Mass Ave, Cambridge, MA 02139, USA.
7948+ *
7949+ * History
7950+ * -------
7951+ *
7952+ * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
7953+ * original version based in sa1100 driver
7954+ * and omap oss driver.
7955+ */
7956+
7957+#ifndef __OMAP_ALSA_H
7958+#define __OMAP_ALSA_H
7959+
7960+#include <plat/dma.h>
7961+#include <sound/core.h>
7962+#include <sound/pcm.h>
7963+#include <plat/mcbsp.h>
7964+#include <linux/platform_device.h>
7965+
7966+#define DMA_BUF_SIZE (1024 * 8)
7967+
7968+/*
7969+ * Buffer management for alsa and dma
7970+ */
7971+struct audio_stream {
7972+ char *id; /* identification string */
7973+ int stream_id; /* numeric identification */
7974+ int dma_dev; /* dma number of that device */
7975+ int *lch; /* Chain of channels this stream is linked to */
7976+ char started; /* to store if the chain was started or not */
7977+ int dma_q_head; /* DMA Channel Q Head */
7978+ int dma_q_tail; /* DMA Channel Q Tail */
7979+ char dma_q_count; /* DMA Channel Q Count */
7980+ int active:1; /* we are using this stream for transfer now */
7981+ int period; /* current transfer period */
7982+ int periods; /* current count of periods registerd in the DMA engine */
7983+ spinlock_t dma_lock; /* for locking in DMA operations */
7984+ struct snd_pcm_substream *stream; /* the pcm stream */
7985+ unsigned linked:1; /* dma channels linked */
7986+ int offset; /* store start position of the last period in the alsa buffer */
7987+ int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
7988+ int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
7989+};
7990+
7991+/*
7992+ * Alsa card structure for aic23
7993+ */
7994+struct snd_card_omap_codec {
7995+ struct snd_card *card;
7996+ struct snd_pcm *pcm;
7997+ long samplerate;
7998+ struct audio_stream s[2]; /* playback & capture */
7999+};
8000+
8001+/* Codec specific information and function pointers.
8002+ * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
8003+ * are responsible for defining the function pointers.
8004+ */
8005+struct omap_alsa_codec_config {
8006+ char *name;
8007+ struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
8008+ struct snd_pcm_hw_constraint_list *hw_constraints_rates;
8009+ struct snd_pcm_hardware *snd_omap_alsa_playback;
8010+ struct snd_pcm_hardware *snd_omap_alsa_capture;
8011+ void (*codec_configure_dev)(void);
8012+ void (*codec_set_samplerate)(long);
8013+ void (*codec_clock_setup)(void);
8014+ int (*codec_clock_on)(void);
8015+ int (*codec_clock_off)(void);
8016+ int (*get_default_samplerate)(void);
8017+};
8018+
8019+/*********** Mixer function prototypes *************************/
8020+int snd_omap_mixer(struct snd_card_omap_codec *);
8021+void snd_omap_init_mixer(void);
8022+
8023+#ifdef CONFIG_PM
8024+void snd_omap_suspend_mixer(void);
8025+void snd_omap_resume_mixer(void);
8026+#endif
8027+
8028+int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
8029+int snd_omap_alsa_remove(struct platform_device *pdev);
8030+#ifdef CONFIG_PM
8031+int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
8032+int snd_omap_alsa_resume(struct platform_device *pdev);
8033+#else
8034+#define snd_omap_alsa_suspend NULL
8035+#define snd_omap_alsa_resume NULL
8036+#endif
8037+
8038+void callback_omap_alsa_sound_dma(void *);
8039+
8040+#endif
8041Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap_device.h
8042===================================================================
8043--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8044@@ -0,0 +1,143 @@
8045+/*
8046+ * omap_device headers
8047+ *
8048+ * Copyright (C) 2009 Nokia Corporation
8049+ * Paul Walmsley
8050+ *
8051+ * Developed in collaboration with (alphabetical order): Benoit
8052+ * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
8053+ * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
8054+ * Woodruff
8055+ *
8056+ * This program is free software; you can redistribute it and/or modify
8057+ * it under the terms of the GNU General Public License version 2 as
8058+ * published by the Free Software Foundation.
8059+ *
8060+ * Eventually this type of functionality should either be
8061+ * a) implemented via arch-specific pointers in platform_device
8062+ * or
8063+ * b) implemented as a proper omap_bus/omap_device in Linux, no more
8064+ * platform_device
8065+ *
8066+ * omap_device differs from omap_hwmod in that it includes external
8067+ * (e.g., board- and system-level) integration details. omap_hwmod
8068+ * stores hardware data that is invariant for a given OMAP chip.
8069+ *
8070+ * To do:
8071+ * - GPIO integration
8072+ * - regulator integration
8073+ *
8074+ */
8075+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8076+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8077+
8078+#include <linux/kernel.h>
8079+#include <linux/platform_device.h>
8080+
8081+#include <plat/omap_hwmod.h>
8082+
8083+/* omap_device._state values */
8084+#define OMAP_DEVICE_STATE_UNKNOWN 0
8085+#define OMAP_DEVICE_STATE_ENABLED 1
8086+#define OMAP_DEVICE_STATE_IDLE 2
8087+#define OMAP_DEVICE_STATE_SHUTDOWN 3
8088+
8089+/**
8090+ * struct omap_device - omap_device wrapper for platform_devices
8091+ * @pdev: platform_device
8092+ * @hwmods: (one .. many per omap_device)
8093+ * @hwmods_cnt: ARRAY_SIZE() of @hwmods
8094+ * @pm_lats: ptr to an omap_device_pm_latency table
8095+ * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
8096+ * @pm_lat_level: array index of the last odpl entry executed - -1 if never
8097+ * @dev_wakeup_lat: dev wakeup latency in nanoseconds
8098+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
8099+ * @_state: one of OMAP_DEVICE_STATE_* (see above)
8100+ * @flags: device flags
8101+ *
8102+ * Integrates omap_hwmod data into Linux platform_device.
8103+ *
8104+ * Field names beginning with underscores are for the internal use of
8105+ * the omap_device code.
8106+ *
8107+ */
8108+struct omap_device {
8109+ struct platform_device pdev;
8110+ struct omap_hwmod **hwmods;
8111+ struct omap_device_pm_latency *pm_lats;
8112+ u32 dev_wakeup_lat;
8113+ u32 _dev_wakeup_lat_limit;
8114+ u8 pm_lats_cnt;
8115+ s8 pm_lat_level;
8116+ u8 hwmods_cnt;
8117+ u8 _state;
8118+};
8119+
8120+/* Device driver interface (call via platform_data fn ptrs) */
8121+
8122+int omap_device_enable(struct platform_device *pdev);
8123+int omap_device_idle(struct platform_device *pdev);
8124+int omap_device_shutdown(struct platform_device *pdev);
8125+
8126+/* Core code interface */
8127+
8128+int omap_device_count_resources(struct omap_device *od);
8129+int omap_device_fill_resources(struct omap_device *od, struct resource *res);
8130+
8131+struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
8132+ struct omap_hwmod *oh, void *pdata,
8133+ int pdata_len,
8134+ struct omap_device_pm_latency *pm_lats,
8135+ int pm_lats_cnt);
8136+
8137+struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
8138+ struct omap_hwmod **oh, int oh_cnt,
8139+ void *pdata, int pdata_len,
8140+ struct omap_device_pm_latency *pm_lats,
8141+ int pm_lats_cnt);
8142+
8143+int omap_device_register(struct omap_device *od);
8144+
8145+/* OMAP PM interface */
8146+int omap_device_align_pm_lat(struct platform_device *pdev,
8147+ u32 new_wakeup_lat_limit);
8148+struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
8149+
8150+/* Other */
8151+
8152+int omap_device_idle_hwmods(struct omap_device *od);
8153+int omap_device_enable_hwmods(struct omap_device *od);
8154+
8155+int omap_device_disable_clocks(struct omap_device *od);
8156+int omap_device_enable_clocks(struct omap_device *od);
8157+
8158+
8159+/*
8160+ * Entries should be kept in latency order ascending
8161+ *
8162+ * deact_lat is the maximum number of microseconds required to complete
8163+ * deactivate_func() at the device's slowest OPP.
8164+ *
8165+ * act_lat is the maximum number of microseconds required to complete
8166+ * activate_func() at the device's slowest OPP.
8167+ *
8168+ * This will result in some suboptimal power management decisions at fast
8169+ * OPPs, but avoids having to recompute all device power management decisions
8170+ * if the system shifts from a fast OPP to a slow OPP (in order to meet
8171+ * latency requirements).
8172+ *
8173+ * XXX should deactivate_func/activate_func() take platform_device pointers
8174+ * rather than omap_device pointers?
8175+ */
8176+struct omap_device_pm_latency {
8177+ u32 deactivate_lat;
8178+ int (*deactivate_func)(struct omap_device *od);
8179+ u32 activate_lat;
8180+ int (*activate_func)(struct omap_device *od);
8181+};
8182+
8183+
8184+/* Get omap_device pointer from platform_device pointer */
8185+#define to_omap_device(x) container_of((x), struct omap_device, pdev)
8186+
8187+#endif
8188Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap_hwmod.h
8189===================================================================
8190--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8191@@ -0,0 +1,467 @@
8192+/*
8193+ * omap_hwmod macros, structures
8194+ *
8195+ * Copyright (C) 2009 Nokia Corporation
8196+ * Paul Walmsley
8197+ *
8198+ * Created in collaboration with (alphabetical order): Benoit Cousson,
8199+ * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
8200+ * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
8201+ *
8202+ * This program is free software; you can redistribute it and/or modify
8203+ * it under the terms of the GNU General Public License version 2 as
8204+ * published by the Free Software Foundation.
8205+ *
8206+ * These headers and macros are used to define OMAP on-chip module
8207+ * data and their integration with other OMAP modules and Linux.
8208+ *
8209+ * References:
8210+ * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
8211+ * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
8212+ * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
8213+ * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
8214+ * - Open Core Protocol Specification 2.2
8215+ *
8216+ * To do:
8217+ * - add interconnect error log structures
8218+ * - add pinmuxing
8219+ * - init_conn_id_bit (CONNID_BIT_VECTOR)
8220+ * - implement default hwmod SMS/SDRC flags?
8221+ *
8222+ */
8223+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8224+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8225+
8226+#include <linux/kernel.h>
8227+#include <linux/ioport.h>
8228+
8229+#include <plat/cpu.h>
8230+
8231+struct omap_device;
8232+
8233+/* OCP SYSCONFIG bit shifts/masks */
8234+#define SYSC_MIDLEMODE_SHIFT 12
8235+#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
8236+#define SYSC_CLOCKACTIVITY_SHIFT 8
8237+#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
8238+#define SYSC_SIDLEMODE_SHIFT 3
8239+#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
8240+#define SYSC_ENAWAKEUP_SHIFT 2
8241+#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
8242+#define SYSC_SOFTRESET_SHIFT 1
8243+#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
8244+#define SYSC_AUTOIDLE_SHIFT 0
8245+#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
8246+
8247+/* OCP SYSSTATUS bit shifts/masks */
8248+#define SYSS_RESETDONE_SHIFT 0
8249+#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
8250+
8251+/* Master standby/slave idle mode flags */
8252+#define HWMOD_IDLEMODE_FORCE (1 << 0)
8253+#define HWMOD_IDLEMODE_NO (1 << 1)
8254+#define HWMOD_IDLEMODE_SMART (1 << 2)
8255+
8256+
8257+/**
8258+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
8259+ * @name: name of the IRQ channel (module local name)
8260+ * @irq_ch: IRQ channel ID
8261+ *
8262+ * @name should be something short, e.g., "tx" or "rx". It is for use
8263+ * by platform_get_resource_byname(). It is defined locally to the
8264+ * hwmod.
8265+ */
8266+struct omap_hwmod_irq_info {
8267+ const char *name;
8268+ u16 irq;
8269+};
8270+
8271+/**
8272+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
8273+ * @name: name of the DMA channel (module local name)
8274+ * @dma_ch: DMA channel ID
8275+ *
8276+ * @name should be something short, e.g., "tx" or "rx". It is for use
8277+ * by platform_get_resource_byname(). It is defined locally to the
8278+ * hwmod.
8279+ */
8280+struct omap_hwmod_dma_info {
8281+ const char *name;
8282+ u16 dma_ch;
8283+};
8284+
8285+/**
8286+ * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
8287+ * @role: "sys", "32k", "tv", etc -- for use in clk_get()
8288+ * @clkdev_dev_id: opt clock: clkdev dev_id string
8289+ * @clkdev_con_id: opt clock: clkdev con_id string
8290+ * @_clk: pointer to the struct clk (filled in at runtime)
8291+ *
8292+ * The module's interface clock and main functional clock should not
8293+ * be added as optional clocks.
8294+ */
8295+struct omap_hwmod_opt_clk {
8296+ const char *role;
8297+ const char *clkdev_dev_id;
8298+ const char *clkdev_con_id;
8299+ struct clk *_clk;
8300+};
8301+
8302+
8303+/* omap_hwmod_omap2_firewall.flags bits */
8304+#define OMAP_FIREWALL_L3 (1 << 0)
8305+#define OMAP_FIREWALL_L4 (1 << 1)
8306+
8307+/**
8308+ * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
8309+ * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
8310+ * @l4_fw_region: L4 firewall region ID
8311+ * @l4_prot_group: L4 protection group ID
8312+ * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
8313+ */
8314+struct omap_hwmod_omap2_firewall {
8315+ u8 l3_perm_bit;
8316+ u8 l4_fw_region;
8317+ u8 l4_prot_group;
8318+ u8 flags;
8319+};
8320+
8321+
8322+/*
8323+ * omap_hwmod_addr_space.flags bits
8324+ *
8325+ * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
8326+ * ADDR_TYPE_RT: Address space contains module register target data.
8327+ */
8328+#define ADDR_MAP_ON_INIT (1 << 0)
8329+#define ADDR_TYPE_RT (1 << 1)
8330+
8331+/**
8332+ * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
8333+ * @pa_start: starting physical address
8334+ * @pa_end: ending physical address
8335+ * @flags: (see omap_hwmod_addr_space.flags macros above)
8336+ *
8337+ * Address space doesn't necessarily follow physical interconnect
8338+ * structure. GPMC is one example.
8339+ */
8340+struct omap_hwmod_addr_space {
8341+ u32 pa_start;
8342+ u32 pa_end;
8343+ u8 flags;
8344+};
8345+
8346+
8347+/*
8348+ * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
8349+ * interface to interact with the hwmod. Used to add sleep dependencies
8350+ * when the module is enabled or disabled.
8351+ */
8352+#define OCP_USER_MPU (1 << 0)
8353+#define OCP_USER_SDMA (1 << 1)
8354+
8355+/* omap_hwmod_ocp_if.flags bits */
8356+#define OCPIF_HAS_IDLEST (1 << 0)
8357+#define OCPIF_SWSUP_IDLE (1 << 1)
8358+#define OCPIF_CAN_BURST (1 << 2)
8359+
8360+/**
8361+ * struct omap_hwmod_ocp_if - OCP interface data
8362+ * @master: struct omap_hwmod that initiates OCP transactions on this link
8363+ * @slave: struct omap_hwmod that responds to OCP transactions on this link
8364+ * @addr: address space associated with this link
8365+ * @clkdev_dev_id: interface clock: clkdev dev_id string
8366+ * @clkdev_con_id: interface clock: clkdev con_id string
8367+ * @_clk: pointer to the interface struct clk (filled in at runtime)
8368+ * @fw: interface firewall data
8369+ * @addr_cnt: ARRAY_SIZE(@addr)
8370+ * @width: OCP data width
8371+ * @thread_cnt: number of threads
8372+ * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
8373+ * @user: initiators using this interface (see OCP_USER_* macros above)
8374+ * @flags: OCP interface flags (see OCPIF_* macros above)
8375+ *
8376+ * It may also be useful to add a tag_cnt field for OCP2.x devices.
8377+ *
8378+ * Parameter names beginning with an underscore are managed internally by
8379+ * the omap_hwmod code and should not be set during initialization.
8380+ */
8381+struct omap_hwmod_ocp_if {
8382+ struct omap_hwmod *master;
8383+ struct omap_hwmod *slave;
8384+ struct omap_hwmod_addr_space *addr;
8385+ const char *clkdev_dev_id;
8386+ const char *clkdev_con_id;
8387+ struct clk *_clk;
8388+ union {
8389+ struct omap_hwmod_omap2_firewall omap2;
8390+ } fw;
8391+ u8 addr_cnt;
8392+ u8 width;
8393+ u8 thread_cnt;
8394+ u8 max_burst_len;
8395+ u8 user;
8396+ u8 flags;
8397+};
8398+
8399+
8400+/* Macros for use in struct omap_hwmod_sysconfig */
8401+
8402+/* Flags for use in omap_hwmod_sysconfig.idlemodes */
8403+#define MASTER_STANDBY_SHIFT 2
8404+#define SLAVE_IDLE_SHIFT 0
8405+#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
8406+#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
8407+#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
8408+#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
8409+#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
8410+#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
8411+
8412+/* omap_hwmod_sysconfig.sysc_flags capability flags */
8413+#define SYSC_HAS_AUTOIDLE (1 << 0)
8414+#define SYSC_HAS_SOFTRESET (1 << 1)
8415+#define SYSC_HAS_ENAWAKEUP (1 << 2)
8416+#define SYSC_HAS_EMUFREE (1 << 3)
8417+#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
8418+#define SYSC_HAS_SIDLEMODE (1 << 5)
8419+#define SYSC_HAS_MIDLEMODE (1 << 6)
8420+#define SYSS_MISSING (1 << 7)
8421+
8422+/* omap_hwmod_sysconfig.clockact flags */
8423+#define CLOCKACT_TEST_BOTH 0x0
8424+#define CLOCKACT_TEST_MAIN 0x1
8425+#define CLOCKACT_TEST_ICLK 0x2
8426+#define CLOCKACT_TEST_NONE 0x3
8427+
8428+/**
8429+ * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
8430+ * @rev_offs: IP block revision register offset (from module base addr)
8431+ * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
8432+ * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
8433+ * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
8434+ * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
8435+ * @clockact: the default value of the module CLOCKACTIVITY bits
8436+ *
8437+ * @clockact describes to the module which clocks are likely to be
8438+ * disabled when the PRCM issues its idle request to the module. Some
8439+ * modules have separate clockdomains for the interface clock and main
8440+ * functional clock, and can check whether they should acknowledge the
8441+ * idle request based on the internal module functionality that has
8442+ * been associated with the clocks marked in @clockact. This field is
8443+ * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
8444+ *
8445+ */
8446+struct omap_hwmod_sysconfig {
8447+ u16 rev_offs;
8448+ u16 sysc_offs;
8449+ u16 syss_offs;
8450+ u8 idlemodes;
8451+ u8 sysc_flags;
8452+ u8 clockact;
8453+};
8454+
8455+/**
8456+ * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
8457+ * @module_offs: PRCM submodule offset from the start of the PRM/CM
8458+ * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
8459+ * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
8460+ * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
8461+ * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
8462+ * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
8463+ *
8464+ * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
8465+ * WKEN, GRPSEL registers. In an ideal world, no extra information
8466+ * would be needed for IDLEST information, but alas, there are some
8467+ * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
8468+ * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
8469+ */
8470+struct omap_hwmod_omap2_prcm {
8471+ s16 module_offs;
8472+ u8 prcm_reg_id;
8473+ u8 module_bit;
8474+ u8 idlest_reg_id;
8475+ u8 idlest_idle_bit;
8476+ u8 idlest_stdby_bit;
8477+};
8478+
8479+
8480+/**
8481+ * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
8482+ * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
8483+ * @device_offs: device register offset from @module_offs
8484+ * @submodule_wkdep_bit: bit shift of the WKDEP range
8485+ */
8486+struct omap_hwmod_omap4_prcm {
8487+ u32 module_offs;
8488+ u16 device_offs;
8489+ u8 submodule_wkdep_bit;
8490+};
8491+
8492+
8493+/*
8494+ * omap_hwmod.flags definitions
8495+ *
8496+ * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
8497+ * of idle, rather than relying on module smart-idle
8498+ * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
8499+ * of standby, rather than relying on module smart-standby
8500+ * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
8501+ * SDRAM controller, etc.
8502+ * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
8503+ * controller, etc.
8504+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
8505+ * when module is enabled, rather than the default, which is to
8506+ * enable autoidle
8507+ * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
8508+ */
8509+#define HWMOD_SWSUP_SIDLE (1 << 0)
8510+#define HWMOD_SWSUP_MSTANDBY (1 << 1)
8511+#define HWMOD_INIT_NO_RESET (1 << 2)
8512+#define HWMOD_INIT_NO_IDLE (1 << 3)
8513+#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
8514+#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
8515+
8516+/*
8517+ * omap_hwmod._int_flags definitions
8518+ * These are for internal use only and are managed by the omap_hwmod code.
8519+ *
8520+ * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
8521+ * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
8522+ * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
8523+ */
8524+#define _HWMOD_NO_MPU_PORT (1 << 0)
8525+#define _HWMOD_WAKEUP_ENABLED (1 << 1)
8526+#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
8527+
8528+/*
8529+ * omap_hwmod._state definitions
8530+ *
8531+ * INITIALIZED: reset (optionally), initialized, enabled, disabled
8532+ * (optionally)
8533+ *
8534+ *
8535+ */
8536+#define _HWMOD_STATE_UNKNOWN 0
8537+#define _HWMOD_STATE_REGISTERED 1
8538+#define _HWMOD_STATE_CLKS_INITED 2
8539+#define _HWMOD_STATE_INITIALIZED 3
8540+#define _HWMOD_STATE_ENABLED 4
8541+#define _HWMOD_STATE_IDLE 5
8542+#define _HWMOD_STATE_DISABLED 6
8543+
8544+/**
8545+ * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
8546+ * @name: name of the hwmod
8547+ * @od: struct omap_device currently associated with this hwmod (internal use)
8548+ * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
8549+ * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
8550+ * @prcm: PRCM data pertaining to this hwmod
8551+ * @clkdev_dev_id: main clock: clkdev dev_id string
8552+ * @clkdev_con_id: main clock: clkdev con_id string
8553+ * @_clk: pointer to the main struct clk (filled in at runtime)
8554+ * @opt_clks: other device clocks that drivers can request (0..*)
8555+ * @masters: ptr to array of OCP ifs that this hwmod can initiate on
8556+ * @slaves: ptr to array of OCP ifs that this hwmod can respond on
8557+ * @sysconfig: device SYSCONFIG/SYSSTATUS register data
8558+ * @dev_attr: arbitrary device attributes that can be passed to the driver
8559+ * @_sysc_cache: internal-use hwmod flags
8560+ * @_rt_va: cached register target start address (internal use)
8561+ * @_mpu_port_index: cached MPU register target slave ID (internal use)
8562+ * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
8563+ * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
8564+ * @mpu_irqs_cnt: number of @mpu_irqs
8565+ * @sdma_chs_cnt: number of @sdma_chs
8566+ * @opt_clks_cnt: number of @opt_clks
8567+ * @master_cnt: number of @master entries
8568+ * @slaves_cnt: number of @slave entries
8569+ * @response_lat: device OCP response latency (in interface clock cycles)
8570+ * @_int_flags: internal-use hwmod flags
8571+ * @_state: internal-use hwmod state
8572+ * @flags: hwmod flags (documented below)
8573+ * @omap_chip: OMAP chips this hwmod is present on
8574+ * @node: list node for hwmod list (internal use)
8575+ *
8576+ * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
8577+ * clock," which for our purposes is defined as "the functional clock needed
8578+ * for register accesses to complete." Modules may not have a main clock if
8579+ * the interface clock also serves as a main clock.
8580+ *
8581+ * Parameter names beginning with an underscore are managed internally by
8582+ * the omap_hwmod code and should not be set during initialization.
8583+ */
8584+struct omap_hwmod {
8585+ const char *name;
8586+ struct omap_device *od;
8587+ struct omap_hwmod_irq_info *mpu_irqs;
8588+ struct omap_hwmod_dma_info *sdma_chs;
8589+ union {
8590+ struct omap_hwmod_omap2_prcm omap2;
8591+ struct omap_hwmod_omap4_prcm omap4;
8592+ } prcm;
8593+ const char *clkdev_dev_id;
8594+ const char *clkdev_con_id;
8595+ struct clk *_clk;
8596+ struct omap_hwmod_opt_clk *opt_clks;
8597+ struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
8598+ struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
8599+ struct omap_hwmod_sysconfig *sysconfig;
8600+ void *dev_attr;
8601+ u32 _sysc_cache;
8602+ void __iomem *_rt_va;
8603+ struct list_head node;
8604+ u16 flags;
8605+ u8 _mpu_port_index;
8606+ u8 msuspendmux_reg_id;
8607+ u8 msuspendmux_shift;
8608+ u8 response_lat;
8609+ u8 mpu_irqs_cnt;
8610+ u8 sdma_chs_cnt;
8611+ u8 opt_clks_cnt;
8612+ u8 masters_cnt;
8613+ u8 slaves_cnt;
8614+ u8 hwmods_cnt;
8615+ u8 _int_flags;
8616+ u8 _state;
8617+ const struct omap_chip_id omap_chip;
8618+};
8619+
8620+int omap_hwmod_init(struct omap_hwmod **ohs);
8621+int omap_hwmod_register(struct omap_hwmod *oh);
8622+int omap_hwmod_unregister(struct omap_hwmod *oh);
8623+struct omap_hwmod *omap_hwmod_lookup(const char *name);
8624+int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
8625+int omap_hwmod_late_init(void);
8626+
8627+int omap_hwmod_enable(struct omap_hwmod *oh);
8628+int omap_hwmod_idle(struct omap_hwmod *oh);
8629+int omap_hwmod_shutdown(struct omap_hwmod *oh);
8630+
8631+int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
8632+int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
8633+
8634+int omap_hwmod_reset(struct omap_hwmod *oh);
8635+void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
8636+
8637+void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
8638+u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
8639+
8640+int omap_hwmod_count_resources(struct omap_hwmod *oh);
8641+int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
8642+
8643+struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
8644+
8645+int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
8646+ struct omap_hwmod *init_oh);
8647+int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
8648+ struct omap_hwmod *init_oh);
8649+
8650+int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
8651+int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
8652+int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
8653+int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
8654+
8655+int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
8656+int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
8657+
8658+#endif
8659Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap-pm.h
8660===================================================================
8661--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8662@@ -0,0 +1,301 @@
8663+/*
8664+ * omap-pm.h - OMAP power management interface
8665+ *
8666+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
8667+ * Copyright (C) 2008-2009 Nokia Corporation
8668+ * Paul Walmsley
8669+ *
8670+ * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
8671+ * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
8672+ * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
8673+ * Richard Woodruff
8674+ */
8675+
8676+#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
8677+#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
8678+
8679+#include <linux/device.h>
8680+#include <linux/cpufreq.h>
8681+
8682+#include "powerdomain.h"
8683+
8684+/**
8685+ * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
8686+ * @rate: target clock rate
8687+ * @opp_id: OPP ID
8688+ * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
8689+ *
8690+ * Operating performance point data. Can vary by OMAP chip and board.
8691+ */
8692+struct omap_opp {
8693+ unsigned long rate;
8694+ u8 opp_id;
8695+ u16 min_vdd;
8696+};
8697+
8698+extern struct omap_opp *mpu_opps;
8699+extern struct omap_opp *dsp_opps;
8700+extern struct omap_opp *l3_opps;
8701+
8702+/*
8703+ * agent_id values for use with omap_pm_set_min_bus_tput():
8704+ *
8705+ * OCP_INITIATOR_AGENT is only valid for devices that can act as
8706+ * initiators -- it represents the device's L3 interconnect
8707+ * connection. OCP_TARGET_AGENT represents the device's L4
8708+ * interconnect connection.
8709+ */
8710+#define OCP_TARGET_AGENT 1
8711+#define OCP_INITIATOR_AGENT 2
8712+
8713+/**
8714+ * omap_pm_if_early_init - OMAP PM init code called before clock fw init
8715+ * @mpu_opp_table: array ptr to struct omap_opp for MPU
8716+ * @dsp_opp_table: array ptr to struct omap_opp for DSP
8717+ * @l3_opp_table : array ptr to struct omap_opp for CORE
8718+ *
8719+ * Initialize anything that must be configured before the clock
8720+ * framework starts. The "_if_" is to avoid name collisions with the
8721+ * PM idle-loop code.
8722+ */
8723+int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
8724+ struct omap_opp *dsp_opp_table,
8725+ struct omap_opp *l3_opp_table);
8726+
8727+/**
8728+ * omap_pm_if_init - OMAP PM init code called after clock fw init
8729+ *
8730+ * The main initialization code. OPP tables are passed in here. The
8731+ * "_if_" is to avoid name collisions with the PM idle-loop code.
8732+ */
8733+int __init omap_pm_if_init(void);
8734+
8735+/**
8736+ * omap_pm_if_exit - OMAP PM exit code
8737+ *
8738+ * Exit code; currently unused. The "_if_" is to avoid name
8739+ * collisions with the PM idle-loop code.
8740+ */
8741+void omap_pm_if_exit(void);
8742+
8743+/*
8744+ * Device-driver-originated constraints (via board-*.c files, platform_data)
8745+ */
8746+
8747+
8748+/**
8749+ * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
8750+ * @dev: struct device * requesting the constraint
8751+ * @t: maximum MPU wakeup latency in microseconds
8752+ *
8753+ * Request that the maximum interrupt latency for the MPU to be no
8754+ * greater than 't' microseconds. "Interrupt latency" in this case is
8755+ * defined as the elapsed time from the occurrence of a hardware or
8756+ * timer interrupt to the time when the device driver's interrupt
8757+ * service routine has been entered by the MPU.
8758+ *
8759+ * It is intended that underlying PM code will use this information to
8760+ * determine what power state to put the MPU powerdomain into, and
8761+ * possibly the CORE powerdomain as well, since interrupt handling
8762+ * code currently runs from SDRAM. Advanced PM or board*.c code may
8763+ * also configure interrupt controller priorities, OCP bus priorities,
8764+ * CPU speed(s), etc.
8765+ *
8766+ * This function will not affect device wakeup latency, e.g., time
8767+ * elapsed from when a device driver enables a hardware device with
8768+ * clk_enable(), to when the device is ready for register access or
8769+ * other use. To control this device wakeup latency, use
8770+ * set_max_dev_wakeup_lat()
8771+ *
8772+ * Multiple calls to set_max_mpu_wakeup_lat() will replace the
8773+ * previous t value. To remove the latency target for the MPU, call
8774+ * with t = -1.
8775+ *
8776+ * No return value.
8777+ */
8778+void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
8779+
8780+
8781+/**
8782+ * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
8783+ * @dev: struct device * requesting the constraint
8784+ * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
8785+ * @r: minimum throughput (in KiB/s)
8786+ *
8787+ * Request that the minimum data throughput on the OCP interconnect
8788+ * attached to device 'dev' interconnect agent 'tbus_id' be no less
8789+ * than 'r' KiB/s.
8790+ *
8791+ * It is expected that the OMAP PM or bus code will use this
8792+ * information to set the interconnect clock to run at the lowest
8793+ * possible speed that satisfies all current system users. The PM or
8794+ * bus code will adjust the estimate based on its model of the bus, so
8795+ * device driver authors should attempt to specify an accurate
8796+ * quantity for their device use case, and let the PM or bus code
8797+ * overestimate the numbers as necessary to handle request/response
8798+ * latency, other competing users on the system, etc. On OMAP2/3, if
8799+ * a driver requests a minimum L4 interconnect speed constraint, the
8800+ * code will also need to add an minimum L3 interconnect speed
8801+ * constraint,
8802+ *
8803+ * Multiple calls to set_min_bus_tput() will replace the previous rate
8804+ * value for this device. To remove the interconnect throughput
8805+ * restriction for this device, call with r = 0.
8806+ *
8807+ * No return value.
8808+ */
8809+void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
8810+
8811+
8812+/**
8813+ * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
8814+ * @dev: struct device *
8815+ * @t: maximum device wakeup latency in microseconds
8816+ *
8817+ * Request that the maximum amount of time necessary for a device to
8818+ * become accessible after its clocks are enabled should be no greater
8819+ * than 't' microseconds. Specifically, this represents the time from
8820+ * when a device driver enables device clocks with clk_enable(), to
8821+ * when the register reads and writes on the device will succeed.
8822+ * This function should be called before clk_disable() is called,
8823+ * since the power state transition decision may be made during
8824+ * clk_disable().
8825+ *
8826+ * It is intended that underlying PM code will use this information to
8827+ * determine what power state to put the powerdomain enclosing this
8828+ * device into.
8829+ *
8830+ * Multiple calls to set_max_dev_wakeup_lat() will replace the
8831+ * previous wakeup latency values for this device. To remove the wakeup
8832+ * latency restriction for this device, call with t = -1.
8833+ *
8834+ * No return value.
8835+ */
8836+void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
8837+
8838+
8839+/**
8840+ * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
8841+ * @dev: struct device *
8842+ * @t: maximum DMA transfer start latency in microseconds
8843+ *
8844+ * Request that the maximum system DMA transfer start latency for this
8845+ * device 'dev' should be no greater than 't' microseconds. "DMA
8846+ * transfer start latency" here is defined as the elapsed time from
8847+ * when a device (e.g., McBSP) requests that a system DMA transfer
8848+ * start or continue, to the time at which data starts to flow into
8849+ * that device from the system DMA controller.
8850+ *
8851+ * It is intended that underlying PM code will use this information to
8852+ * determine what power state to put the CORE powerdomain into.
8853+ *
8854+ * Since system DMA transfers may not involve the MPU, this function
8855+ * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
8856+ * so. Similarly, this function will not affect device wakeup latency
8857+ * -- use set_max_dev_wakeup_lat() to affect that.
8858+ *
8859+ * Multiple calls to set_max_sdma_lat() will replace the previous t
8860+ * value for this device. To remove the maximum DMA latency for this
8861+ * device, call with t = -1.
8862+ *
8863+ * No return value.
8864+ */
8865+void omap_pm_set_max_sdma_lat(struct device *dev, long t);
8866+
8867+
8868+/*
8869+ * DSP Bridge-specific constraints
8870+ */
8871+
8872+/**
8873+ * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
8874+ *
8875+ * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
8876+ * frequency entries. The final item in the array should have .rate =
8877+ * .opp_id = 0.
8878+ */
8879+const struct omap_opp *omap_pm_dsp_get_opp_table(void);
8880+
8881+/**
8882+ * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
8883+ * @opp_id: target DSP OPP ID
8884+ *
8885+ * Set a minimum OPP ID for the DSP. This is intended to be called
8886+ * only from the DSP Bridge MPU-side driver. Unfortunately, the only
8887+ * information that code receives from the DSP/BIOS load estimator is the
8888+ * target OPP ID; hence, this interface. No return value.
8889+ */
8890+void omap_pm_dsp_set_min_opp(u8 opp_id);
8891+
8892+/**
8893+ * omap_pm_dsp_get_opp - report the current DSP OPP ID
8894+ *
8895+ * Report the current OPP for the DSP. Since on OMAP3, the DSP and
8896+ * MPU share a single voltage domain, the OPP ID returned back may
8897+ * represent a higher DSP speed than the OPP requested via
8898+ * omap_pm_dsp_set_min_opp().
8899+ *
8900+ * Returns the current VDD1 OPP ID, or 0 upon error.
8901+ */
8902+u8 omap_pm_dsp_get_opp(void);
8903+
8904+
8905+/*
8906+ * CPUFreq-originated constraint
8907+ *
8908+ * In the future, this should be handled by custom OPP clocktype
8909+ * functions.
8910+ */
8911+
8912+/**
8913+ * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
8914+ *
8915+ * Provide a frequency table usable by CPUFreq for the current chip/board.
8916+ * Returns a pointer to a struct cpufreq_frequency_table array or NULL
8917+ * upon error.
8918+ */
8919+struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
8920+
8921+/**
8922+ * omap_pm_cpu_set_freq - set the current minimum MPU frequency
8923+ * @f: MPU frequency in Hz
8924+ *
8925+ * Set the current minimum CPU frequency. The actual CPU frequency
8926+ * used could end up higher if the DSP requested a higher OPP.
8927+ * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
8928+ * return value.
8929+ */
8930+void omap_pm_cpu_set_freq(unsigned long f);
8931+
8932+/**
8933+ * omap_pm_cpu_get_freq - report the current CPU frequency
8934+ *
8935+ * Returns the current MPU frequency, or 0 upon error.
8936+ */
8937+unsigned long omap_pm_cpu_get_freq(void);
8938+
8939+
8940+/*
8941+ * Device context loss tracking
8942+ */
8943+
8944+/**
8945+ * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
8946+ * @dev: struct device *
8947+ *
8948+ * This function returns the number of times that the device @dev has
8949+ * lost its internal context. This generally occurs on a powerdomain
8950+ * transition to OFF. Drivers use this as an optimization to avoid restoring
8951+ * context if the device hasn't lost it. To use, drivers should initially
8952+ * call this in their context save functions and store the result. Early in
8953+ * the driver's context restore function, the driver should call this function
8954+ * again, and compare the result to the stored counter. If they differ, the
8955+ * driver must restore device context. If the number of context losses
8956+ * exceeds the maximum positive integer, the function will wrap to 0 and
8957+ * continue counting. Returns the number of context losses for this device,
8958+ * or -EINVAL upon error.
8959+ */
8960+int omap_pm_get_dev_context_loss_count(struct device *dev);
8961+
8962+
8963+#endif
8964Index: linux-2.6.35/arch/arm/plat-omap/include/mach/onenand.h
8965===================================================================
8966--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8967@@ -0,0 +1,43 @@
8968+/*
8969+ * arch/arm/plat-omap/include/mach/onenand.h
8970+ *
8971+ * Copyright (C) 2006 Nokia Corporation
8972+ * Author: Juha Yrjola
8973+ *
8974+ * This program is free software; you can redistribute it and/or modify
8975+ * it under the terms of the GNU General Public License version 2 as
8976+ * published by the Free Software Foundation.
8977+ */
8978+
8979+#include <linux/mtd/mtd.h>
8980+#include <linux/mtd/partitions.h>
8981+
8982+#define ONENAND_SYNC_READ (1 << 0)
8983+#define ONENAND_SYNC_READWRITE (1 << 1)
8984+
8985+struct omap_onenand_platform_data {
8986+ int cs;
8987+ int gpio_irq;
8988+ struct mtd_partition *parts;
8989+ int nr_parts;
8990+ int (*onenand_setup)(void __iomem *, int freq);
8991+ int dma_channel;
8992+ u8 flags;
8993+};
8994+
8995+#define ONENAND_MAX_PARTITIONS 8
8996+
8997+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
8998+ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
8999+
9000+extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
9001+
9002+#else
9003+
9004+#define board_onenand_data NULL
9005+
9006+static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
9007+{
9008+}
9009+
9010+#endif
9011Index: linux-2.6.35/arch/arm/plat-omap/include/mach/param.h
9012===================================================================
9013--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9014@@ -0,0 +1,8 @@
9015+/*
9016+ * arch/arm/plat-omap/include/mach/param.h
9017+ *
9018+ */
9019+
9020+#ifdef CONFIG_OMAP_32K_TIMER_HZ
9021+#define HZ CONFIG_OMAP_32K_TIMER_HZ
9022+#endif
9023Index: linux-2.6.35/arch/arm/plat-omap/include/mach/powerdomain.h
9024===================================================================
9025--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9026@@ -0,0 +1,187 @@
9027+/*
9028+ * OMAP2/3 powerdomain control
9029+ *
9030+ * Copyright (C) 2007-8 Texas Instruments, Inc.
9031+ * Copyright (C) 2007-8 Nokia Corporation
9032+ *
9033+ * Written by Paul Walmsley
9034+ *
9035+ * This program is free software; you can redistribute it and/or modify
9036+ * it under the terms of the GNU General Public License version 2 as
9037+ * published by the Free Software Foundation.
9038+ */
9039+
9040+#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
9041+#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
9042+
9043+#include <linux/types.h>
9044+#include <linux/list.h>
9045+
9046+#include <asm/atomic.h>
9047+
9048+#include <plat/cpu.h>
9049+
9050+
9051+/* Powerdomain basic power states */
9052+#define PWRDM_POWER_OFF 0x0
9053+#define PWRDM_POWER_RET 0x1
9054+#define PWRDM_POWER_INACTIVE 0x2
9055+#define PWRDM_POWER_ON 0x3
9056+
9057+#define PWRDM_MAX_PWRSTS 4
9058+
9059+/* Powerdomain allowable state bitfields */
9060+#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
9061+ (1 << PWRDM_POWER_ON))
9062+
9063+#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
9064+ (1 << PWRDM_POWER_RET))
9065+
9066+#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
9067+
9068+
9069+/* Powerdomain flags */
9070+#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
9071+#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
9072+ * in MEM bank 1 position. This is
9073+ * true for OMAP3430
9074+ */
9075+
9076+/*
9077+ * Number of memory banks that are power-controllable. On OMAP3430, the
9078+ * maximum is 4.
9079+ */
9080+#define PWRDM_MAX_MEM_BANKS 4
9081+
9082+/*
9083+ * Maximum number of clockdomains that can be associated with a powerdomain.
9084+ * CORE powerdomain on OMAP3 is the worst case
9085+ */
9086+#define PWRDM_MAX_CLKDMS 4
9087+
9088+/* XXX A completely arbitrary number. What is reasonable here? */
9089+#define PWRDM_TRANSITION_BAILOUT 100000
9090+
9091+struct clockdomain;
9092+struct powerdomain;
9093+
9094+/* Encodes dependencies between powerdomains - statically defined */
9095+struct pwrdm_dep {
9096+
9097+ /* Powerdomain name */
9098+ const char *pwrdm_name;
9099+
9100+ /* Powerdomain pointer - resolved by the powerdomain code */
9101+ struct powerdomain *pwrdm;
9102+
9103+ /* Flags to mark OMAP chip restrictions, etc. */
9104+ const struct omap_chip_id omap_chip;
9105+
9106+};
9107+
9108+struct powerdomain {
9109+
9110+ /* Powerdomain name */
9111+ const char *name;
9112+
9113+ /* the address offset from CM_BASE/PRM_BASE */
9114+ const s16 prcm_offs;
9115+
9116+ /* Used to represent the OMAP chip types containing this pwrdm */
9117+ const struct omap_chip_id omap_chip;
9118+
9119+ /* Powerdomains that can be told to wake this powerdomain up */
9120+ struct pwrdm_dep *wkdep_srcs;
9121+
9122+ /* Powerdomains that can be told to keep this pwrdm from inactivity */
9123+ struct pwrdm_dep *sleepdep_srcs;
9124+
9125+ /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
9126+ const u8 dep_bit;
9127+
9128+ /* Possible powerdomain power states */
9129+ const u8 pwrsts;
9130+
9131+ /* Possible logic power states when pwrdm in RETENTION */
9132+ const u8 pwrsts_logic_ret;
9133+
9134+ /* Powerdomain flags */
9135+ const u8 flags;
9136+
9137+ /* Number of software-controllable memory banks in this powerdomain */
9138+ const u8 banks;
9139+
9140+ /* Possible memory bank pwrstates when pwrdm in RETENTION */
9141+ const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
9142+
9143+ /* Possible memory bank pwrstates when pwrdm is ON */
9144+ const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
9145+
9146+ /* Clockdomains in this powerdomain */
9147+ struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
9148+
9149+ struct list_head node;
9150+
9151+ int state;
9152+ unsigned state_counter[PWRDM_MAX_PWRSTS];
9153+
9154+#ifdef CONFIG_PM_DEBUG
9155+ s64 timer;
9156+ s64 state_timer[PWRDM_MAX_PWRSTS];
9157+#endif
9158+};
9159+
9160+
9161+void pwrdm_init(struct powerdomain **pwrdm_list);
9162+
9163+int pwrdm_register(struct powerdomain *pwrdm);
9164+int pwrdm_unregister(struct powerdomain *pwrdm);
9165+struct powerdomain *pwrdm_lookup(const char *name);
9166+
9167+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
9168+ void *user);
9169+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
9170+ void *user);
9171+
9172+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9173+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9174+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
9175+ int (*fn)(struct powerdomain *pwrdm,
9176+ struct clockdomain *clkdm));
9177+
9178+int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9179+int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9180+int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9181+int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9182+int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9183+int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9184+
9185+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
9186+
9187+int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
9188+int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
9189+int pwrdm_read_pwrst(struct powerdomain *pwrdm);
9190+int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
9191+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
9192+
9193+int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
9194+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9195+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9196+
9197+int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
9198+int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
9199+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9200+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9201+
9202+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
9203+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
9204+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
9205+
9206+int pwrdm_wait_transition(struct powerdomain *pwrdm);
9207+
9208+int pwrdm_state_switch(struct powerdomain *pwrdm);
9209+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
9210+int pwrdm_pre_transition(void);
9211+int pwrdm_post_transition(void);
9212+
9213+#endif
9214Index: linux-2.6.35/arch/arm/plat-omap/include/mach/prcm.h
9215===================================================================
9216--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9217@@ -0,0 +1,39 @@
9218+/*
9219+ * arch/arm/plat-omap/include/mach/prcm.h
9220+ *
9221+ * Access definations for use in OMAP24XX clock and power management
9222+ *
9223+ * Copyright (C) 2005 Texas Instruments, Inc.
9224+ *
9225+ * This program is free software; you can redistribute it and/or modify
9226+ * it under the terms of the GNU General Public License as published by
9227+ * the Free Software Foundation; either version 2 of the License, or
9228+ * (at your option) any later version.
9229+ *
9230+ * This program is distributed in the hope that it will be useful,
9231+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9232+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9233+ * GNU General Public License for more details.
9234+ *
9235+ * You should have received a copy of the GNU General Public License
9236+ * along with this program; if not, write to the Free Software
9237+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9238+ */
9239+
9240+#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
9241+#define __ASM_ARM_ARCH_OMAP_PRCM_H
9242+
9243+u32 omap_prcm_get_reset_sources(void);
9244+void omap_prcm_arch_reset(char mode);
9245+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
9246+
9247+#define START_PADCONF_SAVE 0x2
9248+#define PADCONF_SAVE_DONE 0x1
9249+
9250+void omap3_prcm_save_context(void);
9251+void omap3_prcm_restore_context(void);
9252+
9253+#endif
9254+
9255+
9256+
9257Index: linux-2.6.35/arch/arm/plat-omap/include/mach/sdrc.h
9258===================================================================
9259--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9260@@ -0,0 +1,158 @@
9261+#ifndef ____ASM_ARCH_SDRC_H
9262+#define ____ASM_ARCH_SDRC_H
9263+
9264+/*
9265+ * OMAP2/3 SDRC/SMS register definitions
9266+ *
9267+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
9268+ * Copyright (C) 2007-2008 Nokia Corporation
9269+ *
9270+ * Tony Lindgren
9271+ * Paul Walmsley
9272+ * Richard Woodruff
9273+ *
9274+ * This program is free software; you can redistribute it and/or modify
9275+ * it under the terms of the GNU General Public License version 2 as
9276+ * published by the Free Software Foundation.
9277+ */
9278+
9279+#include <mach/io.h>
9280+
9281+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
9282+
9283+#define SDRC_SYSCONFIG 0x010
9284+#define SDRC_CS_CFG 0x040
9285+#define SDRC_SHARING 0x044
9286+#define SDRC_ERR_TYPE 0x04C
9287+#define SDRC_DLLA_CTRL 0x060
9288+#define SDRC_DLLA_STATUS 0x064
9289+#define SDRC_DLLB_CTRL 0x068
9290+#define SDRC_DLLB_STATUS 0x06C
9291+#define SDRC_POWER 0x070
9292+#define SDRC_MCFG_0 0x080
9293+#define SDRC_MR_0 0x084
9294+#define SDRC_EMR2_0 0x08c
9295+#define SDRC_ACTIM_CTRL_A_0 0x09c
9296+#define SDRC_ACTIM_CTRL_B_0 0x0a0
9297+#define SDRC_RFR_CTRL_0 0x0a4
9298+#define SDRC_MANUAL_0 0x0a8
9299+#define SDRC_MCFG_1 0x0B0
9300+#define SDRC_MR_1 0x0B4
9301+#define SDRC_EMR2_1 0x0BC
9302+#define SDRC_ACTIM_CTRL_A_1 0x0C4
9303+#define SDRC_ACTIM_CTRL_B_1 0x0C8
9304+#define SDRC_RFR_CTRL_1 0x0D4
9305+#define SDRC_MANUAL_1 0x0D8
9306+
9307+#define SDRC_POWER_AUTOCOUNT_SHIFT 8
9308+#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
9309+#define SDRC_POWER_CLKCTRL_SHIFT 4
9310+#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
9311+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
9312+
9313+/*
9314+ * These values represent the number of memory clock cycles between
9315+ * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
9316+ * rows per device, and include a subtraction of a 50 cycle window in the
9317+ * event that the autorefresh command is delayed due to other SDRC activity.
9318+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
9319+ * counter reaches 0.
9320+ *
9321+ * These represent optimal values for common parts, it won't work for all.
9322+ * As long as you scale down, most parameters are still work, they just
9323+ * become sub-optimal. The RFR value goes in the opposite direction. If you
9324+ * don't adjust it down as your clock period increases the refresh interval
9325+ * will not be met. Setting all parameters for complete worst case may work,
9326+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
9327+ * unlocked and their value needs run time calibration. A dynamic call is
9328+ * need for that as no single right value exists acorss production samples.
9329+ *
9330+ * Only the FULL speed values are given. Current code is such that rate
9331+ * changes must be made at DPLLoutx2. The actual value adjustment for low
9332+ * frequency operation will be handled by omap_set_performance()
9333+ *
9334+ * By having the boot loader boot up in the fastest L4 speed available likely
9335+ * will result in something which you can switch between.
9336+ */
9337+#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
9338+#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
9339+#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
9340+#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
9341+#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
9342+
9343+
9344+/*
9345+ * SMS register access
9346+ */
9347+
9348+#define OMAP242X_SMS_REGADDR(reg) \
9349+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
9350+#define OMAP243X_SMS_REGADDR(reg) \
9351+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
9352+#define OMAP343X_SMS_REGADDR(reg) \
9353+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
9354+
9355+/* SMS register offsets - read/write with sms_{read,write}_reg() */
9356+
9357+#define SMS_SYSCONFIG 0x010
9358+#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
9359+#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
9360+#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
9361+/* REVISIT: fill in other SMS registers here */
9362+
9363+
9364+#ifndef __ASSEMBLER__
9365+
9366+/**
9367+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
9368+ * @rate: SDRC clock rate (in Hz)
9369+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
9370+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
9371+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
9372+ * @mr: Value to program to SDRC_MR for this rate
9373+ *
9374+ * This structure holds a pre-computed set of register values for the
9375+ * SDRC for a given SDRC clock rate and SDRAM chip. These are
9376+ * intended to be pre-computed and specified in an array in the board-*.c
9377+ * files. The structure is keyed off the 'rate' field.
9378+ */
9379+struct omap_sdrc_params {
9380+ unsigned long rate;
9381+ u32 actim_ctrla;
9382+ u32 actim_ctrlb;
9383+ u32 rfr_ctrl;
9384+ u32 mr;
9385+};
9386+
9387+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
9388+ struct omap_sdrc_params *sdrc_cs1);
9389+int omap2_sdrc_get_params(unsigned long r,
9390+ struct omap_sdrc_params **sdrc_cs0,
9391+ struct omap_sdrc_params **sdrc_cs1);
9392+void omap2_sms_save_context(void);
9393+void omap2_sms_restore_context(void);
9394+
9395+void omap2_sms_write_rot_control(u32 val, unsigned ctx);
9396+void omap2_sms_write_rot_size(u32 val, unsigned ctx);
9397+void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
9398+
9399+#ifdef CONFIG_ARCH_OMAP2
9400+
9401+struct memory_timings {
9402+ u32 m_type; /* ddr = 1, sdr = 0 */
9403+ u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
9404+ u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
9405+ u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
9406+ u32 base_cs; /* base chip select to use for calculations */
9407+};
9408+
9409+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
9410+
9411+u32 omap2xxx_sdrc_dll_is_unlocked(void);
9412+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
9413+
9414+#endif /* CONFIG_ARCH_OMAP2 */
9415+
9416+#endif /* __ASSEMBLER__ */
9417+
9418+#endif
9419Index: linux-2.6.35/arch/arm/plat-omap/include/mach/serial.h
9420===================================================================
9421--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9422@@ -0,0 +1,65 @@
9423+/*
9424+ * arch/arm/plat-omap/include/mach/serial.h
9425+ *
9426+ * Copyright (C) 2009 Texas Instruments
9427+ * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
9428+ *
9429+ * This program is distributed in the hope that it will be useful,
9430+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9431+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9432+ * GNU General Public License for more details.
9433+ */
9434+
9435+#ifndef __ASM_ARCH_SERIAL_H
9436+#define __ASM_ARCH_SERIAL_H
9437+
9438+#include <linux/init.h>
9439+
9440+#if defined(CONFIG_ARCH_OMAP1)
9441+/* OMAP1 serial ports */
9442+#define OMAP_UART1_BASE 0xfffb0000
9443+#define OMAP_UART2_BASE 0xfffb0800
9444+#define OMAP_UART3_BASE 0xfffb9800
9445+#elif defined(CONFIG_ARCH_OMAP2)
9446+/* OMAP2 serial ports */
9447+#define OMAP_UART1_BASE 0x4806a000
9448+#define OMAP_UART2_BASE 0x4806c000
9449+#define OMAP_UART3_BASE 0x4806e000
9450+#elif defined(CONFIG_ARCH_OMAP3)
9451+/* OMAP3 serial ports */
9452+#define OMAP_UART1_BASE 0x4806a000
9453+#define OMAP_UART2_BASE 0x4806c000
9454+#define OMAP_UART3_BASE 0x49020000
9455+#elif defined(CONFIG_ARCH_OMAP4)
9456+/* OMAP4 serial ports */
9457+#define OMAP_UART1_BASE 0x4806a000
9458+#define OMAP_UART2_BASE 0x4806c000
9459+#define OMAP_UART3_BASE 0x48020000
9460+#define OMAP_UART4_BASE 0x4806e000
9461+#endif
9462+
9463+#define OMAP1510_BASE_BAUD (12000000/16)
9464+#define OMAP16XX_BASE_BAUD (48000000/16)
9465+#define OMAP24XX_BASE_BAUD (48000000/16)
9466+
9467+#define is_omap_port(pt) ({int __ret = 0; \
9468+ if ((pt)->port.mapbase == OMAP_UART1_BASE || \
9469+ (pt)->port.mapbase == OMAP_UART2_BASE || \
9470+ (pt)->port.mapbase == OMAP_UART3_BASE) \
9471+ __ret = 1; \
9472+ __ret; \
9473+ })
9474+
9475+#ifndef __ASSEMBLER__
9476+extern void __init omap_serial_early_init(void);
9477+extern void omap_serial_init(void);
9478+extern void omap_serial_init_port(int port);
9479+extern int omap_uart_can_sleep(void);
9480+extern void omap_uart_check_wakeup(void);
9481+extern void omap_uart_prepare_suspend(void);
9482+extern void omap_uart_prepare_idle(int num);
9483+extern void omap_uart_resume_idle(int num);
9484+extern void omap_uart_enable_irqs(int enable);
9485+#endif
9486+
9487+#endif
9488Index: linux-2.6.35/arch/arm/plat-omap/include/mach/smp.h
9489===================================================================
9490--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9491@@ -0,0 +1,53 @@
9492+/*
9493+ * OMAP4 machine specific smp.h
9494+ *
9495+ * Copyright (C) 2009 Texas Instruments, Inc.
9496+ *
9497+ * Author:
9498+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
9499+ *
9500+ * Interface functions needed for the SMP. This file is based on arm
9501+ * realview smp platform.
9502+ * Copyright (c) 2003 ARM Limited.
9503+ *
9504+ * This program is free software; you can redistribute it and/or modify
9505+ * it under the terms of the GNU General Public License version 2 as
9506+ * published by the Free Software Foundation.
9507+ */
9508+#ifndef OMAP_ARCH_SMP_H
9509+#define OMAP_ARCH_SMP_H
9510+
9511+#include <asm/hardware/gic.h>
9512+
9513+/*
9514+ * set_event() is used to wake up secondary core from wfe using sev. ROM
9515+ * code puts the second core into wfe(standby).
9516+ *
9517+ */
9518+#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
9519+
9520+/* Needed for secondary core boot */
9521+extern void omap_secondary_startup(void);
9522+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
9523+extern void omap_auxcoreboot_addr(u32 cpu_addr);
9524+
9525+/*
9526+ * We use Soft IRQ1 as the IPI
9527+ */
9528+static inline void smp_cross_call(const struct cpumask *mask)
9529+{
9530+ gic_raise_softirq(mask, 1);
9531+}
9532+
9533+/*
9534+ * Read MPIDR: Multiprocessor affinity register
9535+ */
9536+#define hard_smp_processor_id() \
9537+ ({ \
9538+ unsigned int cpunum; \
9539+ __asm__("mrc p15, 0, %0, c0, c0, 5" \
9540+ : "=r" (cpunum)); \
9541+ cpunum &= 0x0F; \
9542+ })
9543+
9544+#endif
9545Index: linux-2.6.35/arch/arm/plat-omap/include/mach/sram.h
9546===================================================================
9547--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9548@@ -0,0 +1,78 @@
9549+/*
9550+ * arch/arm/plat-omap/include/mach/sram.h
9551+ *
9552+ * Interface for functions that need to be run in internal SRAM
9553+ *
9554+ * This program is free software; you can redistribute it and/or modify
9555+ * it under the terms of the GNU General Public License version 2 as
9556+ * published by the Free Software Foundation.
9557+ */
9558+
9559+#ifndef __ARCH_ARM_OMAP_SRAM_H
9560+#define __ARCH_ARM_OMAP_SRAM_H
9561+
9562+extern int __init omap_sram_init(void);
9563+extern void * omap_sram_push(void * start, unsigned long size);
9564+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
9565+
9566+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9567+ u32 base_cs, u32 force_unlock);
9568+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9569+ u32 mem_type);
9570+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
9571+
9572+extern u32 omap3_configure_core_dpll(
9573+ u32 m2, u32 unlock_dll, u32 f, u32 inc,
9574+ u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9575+ u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9576+ u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9577+ u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9578+extern void omap3_sram_restore_context(void);
9579+
9580+/* Do not use these */
9581+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9582+extern unsigned long omap1_sram_reprogram_clock_sz;
9583+
9584+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9585+extern unsigned long omap24xx_sram_reprogram_clock_sz;
9586+
9587+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9588+ u32 base_cs, u32 force_unlock);
9589+extern unsigned long omap242x_sram_ddr_init_sz;
9590+
9591+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9592+ int bypass);
9593+extern unsigned long omap242x_sram_set_prcm_sz;
9594+
9595+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9596+ u32 mem_type);
9597+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
9598+
9599+
9600+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9601+ u32 base_cs, u32 force_unlock);
9602+extern unsigned long omap243x_sram_ddr_init_sz;
9603+
9604+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9605+ int bypass);
9606+extern unsigned long omap243x_sram_set_prcm_sz;
9607+
9608+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9609+ u32 mem_type);
9610+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
9611+
9612+extern u32 omap3_sram_configure_core_dpll(
9613+ u32 m2, u32 unlock_dll, u32 f, u32 inc,
9614+ u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9615+ u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9616+ u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9617+ u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9618+extern unsigned long omap3_sram_configure_core_dpll_sz;
9619+
9620+#ifdef CONFIG_PM
9621+extern void omap_push_sram_idle(void);
9622+#else
9623+static inline void omap_push_sram_idle(void) {}
9624+#endif /* CONFIG_PM */
9625+
9626+#endif
9627Index: linux-2.6.35/arch/arm/plat-omap/include/mach/system.h
9628===================================================================
9629--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9630@@ -0,0 +1,51 @@
9631+/*
9632+ * Copied from arch/arm/mach-sa1100/include/mach/system.h
9633+ * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
9634+ */
9635+#ifndef __ASM_ARCH_SYSTEM_H
9636+#define __ASM_ARCH_SYSTEM_H
9637+#include <linux/clk.h>
9638+
9639+#include <asm/mach-types.h>
9640+#include <mach/hardware.h>
9641+
9642+#include <plat/prcm.h>
9643+
9644+#ifndef CONFIG_MACH_VOICEBLUE
9645+#define voiceblue_reset() do {} while (0)
9646+#else
9647+extern void voiceblue_reset(void);
9648+#endif
9649+
9650+static inline void arch_idle(void)
9651+{
9652+ cpu_do_idle();
9653+}
9654+
9655+static inline void omap1_arch_reset(char mode)
9656+{
9657+ /*
9658+ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
9659+ * "Global Software Reset Affects Traffic Controller Frequency".
9660+ */
9661+ if (cpu_is_omap5912()) {
9662+ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
9663+ DPLL_CTL);
9664+ omap_writew(0x8, ARM_RSTCT1);
9665+ }
9666+
9667+ if (machine_is_voiceblue())
9668+ voiceblue_reset();
9669+ else
9670+ omap_writew(1, ARM_RSTCT1);
9671+}
9672+
9673+static inline void arch_reset(char mode, const char *cmd)
9674+{
9675+ if (!cpu_class_is_omap2())
9676+ omap1_arch_reset(mode);
9677+ else
9678+ omap_prcm_arch_reset(mode);
9679+}
9680+
9681+#endif
9682Index: linux-2.6.35/arch/arm/plat-omap/include/mach/tc.h
9683===================================================================
9684--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9685@@ -0,0 +1,106 @@
9686+/*
9687+ * arch/arm/plat-omap/include/mach/tc.h
9688+ *
9689+ * OMAP Traffic Controller
9690+ *
9691+ * Copyright (C) 2004 Nokia Corporation
9692+ * Author: Imre Deak <imre.deak@nokia.com>
9693+ *
9694+ * This program is free software; you can redistribute it and/or modify it
9695+ * under the terms of the GNU General Public License as published by the
9696+ * Free Software Foundation; either version 2 of the License, or (at your
9697+ * option) any later version.
9698+ *
9699+ * This program is distributed in the hope that it will be useful, but
9700+ * WITHOUT ANY WARRANTY; without even the implied warranty of
9701+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9702+ * General Public License for more details.
9703+ *
9704+ * You should have received a copy of the GNU General Public License along
9705+ * with this program; if not, write to the Free Software Foundation, Inc.,
9706+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
9707+ */
9708+
9709+#ifndef __ASM_ARCH_TC_H
9710+#define __ASM_ARCH_TC_H
9711+
9712+#define TCMIF_BASE 0xfffecc00
9713+#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
9714+#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
9715+#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
9716+#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
9717+#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
9718+#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
9719+#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
9720+#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
9721+#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
9722+#define EMIFF_MRS (TCMIF_BASE + 0x24)
9723+#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
9724+#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
9725+#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
9726+#define TC_ENDIANISM (TCMIF_BASE + 0x34)
9727+#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
9728+#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
9729+#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
9730+#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
9731+#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
9732+#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
9733+#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
9734+
9735+/* external EMIFS chipselect regions */
9736+#define OMAP_CS0_PHYS 0x00000000
9737+#define OMAP_CS0_SIZE SZ_64M
9738+
9739+#define OMAP_CS1_PHYS 0x04000000
9740+#define OMAP_CS1_SIZE SZ_64M
9741+
9742+#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
9743+#define OMAP_CS1A_SIZE SZ_32M
9744+
9745+#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
9746+#define OMAP_CS1B_SIZE SZ_32M
9747+
9748+#define OMAP_CS2_PHYS 0x08000000
9749+#define OMAP_CS2_SIZE SZ_64M
9750+
9751+#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
9752+#define OMAP_CS2A_SIZE SZ_32M
9753+
9754+#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
9755+#define OMAP_CS2B_SIZE SZ_32M
9756+
9757+#define OMAP_CS3_PHYS 0x0c000000
9758+#define OMAP_CS3_SIZE SZ_64M
9759+
9760+#ifndef __ASSEMBLER__
9761+
9762+/* EMIF Slow Interface Configuration Register */
9763+#define OMAP_EMIFS_CONFIG_FR (1 << 4)
9764+#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
9765+#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
9766+#define OMAP_EMIFS_CONFIG_BM (1 << 1)
9767+#define OMAP_EMIFS_CONFIG_WP (1 << 0)
9768+
9769+#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
9770+#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
9771+
9772+/* Almost all documentation for chip and board memory maps assumes
9773+ * BM is clear. Most devel boards have a switch to control booting
9774+ * from NOR flash (using external chipselect 3) rather than mask ROM,
9775+ * which uses BM to interchange the physical CS0 and CS3 addresses.
9776+ */
9777+static inline u32 omap_cs0_phys(void)
9778+{
9779+ return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9780+ ? OMAP_CS3_PHYS : 0;
9781+}
9782+
9783+static inline u32 omap_cs3_phys(void)
9784+{
9785+ return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9786+ ? 0 : OMAP_CS3_PHYS;
9787+}
9788+
9789+#endif /* __ASSEMBLER__ */
9790+
9791+#endif /* __ASM_ARCH_TC_H */
9792Index: linux-2.6.35/arch/arm/plat-omap/include/mach/timer-gp.h
9793===================================================================
9794--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9795@@ -0,0 +1,17 @@
9796+/*
9797+ * OMAP2/3 GPTIMER support.headers
9798+ *
9799+ * Copyright (C) 2009 Nokia Corporation
9800+ *
9801+ * This file is subject to the terms and conditions of the GNU General Public
9802+ * License. See the file "COPYING" in the main directory of this archive
9803+ * for more details.
9804+ */
9805+
9806+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9807+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9808+
9809+int __init omap2_gp_clockevent_set_gptimer(u8 id);
9810+
9811+#endif
9812+
9813Index: linux-2.6.35/arch/arm/plat-omap/include/mach/timex.h
9814===================================================================
9815--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9816@@ -0,0 +1,41 @@
9817+/*
9818+ * arch/arm/plat-omap/include/mach/timex.h
9819+ *
9820+ * Copyright (C) 2000 RidgeRun, Inc.
9821+ * Author: Greg Lonnon <glonnon@ridgerun.com>
9822+ *
9823+ * This program is free software; you can redistribute it and/or modify it
9824+ * under the terms of the GNU General Public License as published by the
9825+ * Free Software Foundation; either version 2 of the License, or (at your
9826+ * option) any later version.
9827+ *
9828+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9829+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9830+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9831+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9832+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9833+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9834+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9835+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9836+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9837+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9838+ *
9839+ * You should have received a copy of the GNU General Public License along
9840+ * with this program; if not, write to the Free Software Foundation, Inc.,
9841+ * 675 Mass Ave, Cambridge, MA 02139, USA.
9842+ */
9843+
9844+#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
9845+#define __ASM_ARCH_OMAP_TIMEX_H
9846+
9847+/*
9848+ * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
9849+ * and that's why the CLOCK_TICK_RATE is not 32768.
9850+ */
9851+#ifdef CONFIG_OMAP_32K_TIMER
9852+#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
9853+#else
9854+#define CLOCK_TICK_RATE (HZ * 100000UL)
9855+#endif
9856+
9857+#endif /* __ASM_ARCH_OMAP_TIMEX_H */
9858Index: linux-2.6.35/arch/arm/plat-omap/include/mach/uncompress.h
9859===================================================================
9860--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9861@@ -0,0 +1,88 @@
9862+/*
9863+ * arch/arm/plat-omap/include/mach/uncompress.h
9864+ *
9865+ * Serial port stubs for kernel decompress status messages
9866+ *
9867+ * Initially based on:
9868+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
9869+ * Copyright (C) 2000 RidgeRun, Inc.
9870+ * Author: Greg Lonnon <glonnon@ridgerun.com>
9871+ *
9872+ * Rewritten by:
9873+ * Author: <source@mvista.com>
9874+ * 2004 (c) MontaVista Software, Inc.
9875+ *
9876+ * This file is licensed under the terms of the GNU General Public License
9877+ * version 2. This program is licensed "as is" without any warranty of any
9878+ * kind, whether express or implied.
9879+ */
9880+
9881+#include <linux/types.h>
9882+#include <linux/serial_reg.h>
9883+#include <plat/serial.h>
9884+
9885+unsigned int system_rev;
9886+
9887+#define UART_OMAP_MDR1 0x08 /* mode definition register */
9888+#define OMAP_ID_730 0x355F
9889+#define OMAP_ID_850 0x362C
9890+#define ID_MASK 0x7fff
9891+#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
9892+#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
9893+
9894+static void putc(int c)
9895+{
9896+ volatile u8 * uart = 0;
9897+ int shift = 2;
9898+
9899+#ifdef CONFIG_MACH_OMAP_PALMTE
9900+ return;
9901+#endif
9902+
9903+#ifdef CONFIG_ARCH_OMAP
9904+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
9905+ uart = (volatile u8 *)(OMAP_UART3_BASE);
9906+#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
9907+ uart = (volatile u8 *)(OMAP_UART2_BASE);
9908+#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
9909+ uart = (volatile u8 *)(OMAP_UART1_BASE);
9910+#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
9911+ return;
9912+#else
9913+ return;
9914+#endif
9915+
9916+#ifdef CONFIG_ARCH_OMAP1
9917+ /* Determine which serial port to use */
9918+ do {
9919+ /* MMU is not on, so cpu_is_omapXXXX() won't work here */
9920+ unsigned int omap_id = omap_get_id();
9921+
9922+ if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
9923+ shift = 0;
9924+
9925+ if (check_port(uart, shift))
9926+ break;
9927+ /* Silent boot if no serial ports are enabled. */
9928+ return;
9929+ } while (0);
9930+#endif /* CONFIG_ARCH_OMAP1 */
9931+#endif
9932+
9933+ /*
9934+ * Now, xmit each character
9935+ */
9936+ while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
9937+ barrier();
9938+ uart[UART_TX << shift] = c;
9939+}
9940+
9941+static inline void flush(void)
9942+{
9943+}
9944+
9945+/*
9946+ * nothing to do
9947+ */
9948+#define arch_decomp_setup()
9949+#define arch_decomp_wdog()
9950Index: linux-2.6.35/arch/arm/plat-omap/include/mach/usb.h
9951===================================================================
9952--- /dev/null 1970-01-01 00:00:00.000000000 +0000
9953@@ -0,0 +1,162 @@
9954+// include/asm-arm/mach-omap/usb.h
9955+
9956+#ifndef __ASM_ARCH_OMAP_USB_H
9957+#define __ASM_ARCH_OMAP_USB_H
9958+
9959+#include <plat/board.h>
9960+
9961+#define OMAP3_HS_USB_PORTS 3
9962+enum ehci_hcd_omap_mode {
9963+ EHCI_HCD_OMAP_MODE_UNKNOWN,
9964+ EHCI_HCD_OMAP_MODE_PHY,
9965+ EHCI_HCD_OMAP_MODE_TLL,
9966+};
9967+
9968+struct ehci_hcd_omap_platform_data {
9969+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
9970+ unsigned phy_reset:1;
9971+
9972+ /* have to be valid if phy_reset is true and portx is in phy mode */
9973+ int reset_gpio_port[OMAP3_HS_USB_PORTS];
9974+};
9975+
9976+/*-------------------------------------------------------------------------*/
9977+
9978+#define OMAP1_OTG_BASE 0xfffb0400
9979+#define OMAP1_UDC_BASE 0xfffb4000
9980+#define OMAP1_OHCI_BASE 0xfffba000
9981+
9982+#define OMAP2_OHCI_BASE 0x4805e000
9983+#define OMAP2_UDC_BASE 0x4805e200
9984+#define OMAP2_OTG_BASE 0x4805e300
9985+
9986+#ifdef CONFIG_ARCH_OMAP1
9987+
9988+#define OTG_BASE OMAP1_OTG_BASE
9989+#define UDC_BASE OMAP1_UDC_BASE
9990+#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
9991+
9992+#else
9993+
9994+#define OTG_BASE OMAP2_OTG_BASE
9995+#define UDC_BASE OMAP2_UDC_BASE
9996+#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
9997+
9998+extern void usb_musb_init(void);
9999+
10000+extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
10001+
10002+#endif
10003+
10004+void omap_usb_init(struct omap_usb_config *pdata);
10005+
10006+/*-------------------------------------------------------------------------*/
10007+
10008+/*
10009+ * OTG and transceiver registers, for OMAPs starting with ARM926
10010+ */
10011+#define OTG_REV (OTG_BASE + 0x00)
10012+#define OTG_SYSCON_1 (OTG_BASE + 0x04)
10013+# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
10014+# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
10015+# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
10016+# define OTG_IDLE_EN (1 << 15)
10017+# define HST_IDLE_EN (1 << 14)
10018+# define DEV_IDLE_EN (1 << 13)
10019+# define OTG_RESET_DONE (1 << 2)
10020+# define OTG_SOFT_RESET (1 << 1)
10021+#define OTG_SYSCON_2 (OTG_BASE + 0x08)
10022+# define OTG_EN (1 << 31)
10023+# define USBX_SYNCHRO (1 << 30)
10024+# define OTG_MST16 (1 << 29)
10025+# define SRP_GPDATA (1 << 28)
10026+# define SRP_GPDVBUS (1 << 27)
10027+# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
10028+# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
10029+# define B_ASE_BRST(w) (((w)>>16)&0x07)
10030+# define SRP_DPW (1 << 14)
10031+# define SRP_DATA (1 << 13)
10032+# define SRP_VBUS (1 << 12)
10033+# define OTG_PADEN (1 << 10)
10034+# define HMC_PADEN (1 << 9)
10035+# define UHOST_EN (1 << 8)
10036+# define HMC_TLLSPEED (1 << 7)
10037+# define HMC_TLLATTACH (1 << 6)
10038+# define OTG_HMC(w) (((w)>>0)&0x3f)
10039+#define OTG_CTRL (OTG_BASE + 0x0c)
10040+# define OTG_USB2_EN (1 << 29)
10041+# define OTG_USB2_DP (1 << 28)
10042+# define OTG_USB2_DM (1 << 27)
10043+# define OTG_USB1_EN (1 << 26)
10044+# define OTG_USB1_DP (1 << 25)
10045+# define OTG_USB1_DM (1 << 24)
10046+# define OTG_USB0_EN (1 << 23)
10047+# define OTG_USB0_DP (1 << 22)
10048+# define OTG_USB0_DM (1 << 21)
10049+# define OTG_ASESSVLD (1 << 20)
10050+# define OTG_BSESSEND (1 << 19)
10051+# define OTG_BSESSVLD (1 << 18)
10052+# define OTG_VBUSVLD (1 << 17)
10053+# define OTG_ID (1 << 16)
10054+# define OTG_DRIVER_SEL (1 << 15)
10055+# define OTG_A_SETB_HNPEN (1 << 12)
10056+# define OTG_A_BUSREQ (1 << 11)
10057+# define OTG_B_HNPEN (1 << 9)
10058+# define OTG_B_BUSREQ (1 << 8)
10059+# define OTG_BUSDROP (1 << 7)
10060+# define OTG_PULLDOWN (1 << 5)
10061+# define OTG_PULLUP (1 << 4)
10062+# define OTG_DRV_VBUS (1 << 3)
10063+# define OTG_PD_VBUS (1 << 2)
10064+# define OTG_PU_VBUS (1 << 1)
10065+# define OTG_PU_ID (1 << 0)
10066+#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
10067+# define DRIVER_SWITCH (1 << 15)
10068+# define A_VBUS_ERR (1 << 13)
10069+# define A_REQ_TMROUT (1 << 12)
10070+# define A_SRP_DETECT (1 << 11)
10071+# define B_HNP_FAIL (1 << 10)
10072+# define B_SRP_TMROUT (1 << 9)
10073+# define B_SRP_DONE (1 << 8)
10074+# define B_SRP_STARTED (1 << 7)
10075+# define OPRT_CHG (1 << 0)
10076+#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
10077+ // same bits as in IRQ_EN
10078+#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
10079+# define OTGVPD (1 << 14)
10080+# define OTGVPU (1 << 13)
10081+# define OTGPUID (1 << 12)
10082+# define USB2VDR (1 << 10)
10083+# define USB2PDEN (1 << 9)
10084+# define USB2PUEN (1 << 8)
10085+# define USB1VDR (1 << 6)
10086+# define USB1PDEN (1 << 5)
10087+# define USB1PUEN (1 << 4)
10088+# define USB0VDR (1 << 2)
10089+# define USB0PDEN (1 << 1)
10090+# define USB0PUEN (1 << 0)
10091+#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
10092+#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
10093+
10094+/*-------------------------------------------------------------------------*/
10095+
10096+/* OMAP1 */
10097+#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
10098+# define CONF_USB2_UNI_R (1 << 8)
10099+# define CONF_USB1_UNI_R (1 << 7)
10100+# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
10101+# define CONF_USB0_ISOLATE_R (1 << 3)
10102+# define CONF_USB_PWRDN_DM_R (1 << 2)
10103+# define CONF_USB_PWRDN_DP_R (1 << 1)
10104+
10105+/* OMAP2 */
10106+# define USB_UNIDIR 0x0
10107+# define USB_UNIDIR_TLL 0x1
10108+# define USB_BIDIR 0x2
10109+# define USB_BIDIR_TLL 0x3
10110+# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
10111+# define USBT2TLL5PI (1 << 17)
10112+# define USB0PUENACTLOI (1 << 16)
10113+# define USBSTANDBYCTRL (1 << 15)
10114+
10115+#endif /* __ASM_ARCH_OMAP_USB_H */
10116Index: linux-2.6.35/arch/arm/plat-omap/include/mach/vram.h
10117===================================================================
10118--- /dev/null 1970-01-01 00:00:00.000000000 +0000
10119@@ -0,0 +1,62 @@
10120+/*
10121+ * VRAM manager for OMAP
10122+ *
10123+ * Copyright (C) 2009 Nokia Corporation
10124+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10125+ *
10126+ * This program is free software; you can redistribute it and/or modify
10127+ * it under the terms of the GNU General Public License version 2 as
10128+ * published by the Free Software Foundation.
10129+ *
10130+ * This program is distributed in the hope that it will be useful, but
10131+ * WITHOUT ANY WARRANTY; without even the implied warranty of
10132+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10133+ * General Public License for more details.
10134+ *
10135+ * You should have received a copy of the GNU General Public License along
10136+ * with this program; if not, write to the Free Software Foundation, Inc.,
10137+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10138+ */
10139+
10140+#ifndef __OMAP_VRAM_H__
10141+#define __OMAP_VRAM_H__
10142+
10143+#include <linux/types.h>
10144+
10145+#define OMAP_VRAM_MEMTYPE_SDRAM 0
10146+#define OMAP_VRAM_MEMTYPE_SRAM 1
10147+#define OMAP_VRAM_MEMTYPE_MAX 1
10148+
10149+extern int omap_vram_add_region(unsigned long paddr, size_t size);
10150+extern int omap_vram_free(unsigned long paddr, size_t size);
10151+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
10152+extern int omap_vram_reserve(unsigned long paddr, size_t size);
10153+extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
10154+ unsigned long *largest_free_block);
10155+
10156+#ifdef CONFIG_OMAP2_VRAM
10157+extern void omap_vram_set_sdram_vram(u32 size, u32 start);
10158+extern void omap_vram_set_sram_vram(u32 size, u32 start);
10159+
10160+extern void omap_vram_reserve_sdram(void);
10161+extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10162+ unsigned long sram_vstart,
10163+ unsigned long sram_size,
10164+ unsigned long pstart_avail,
10165+ unsigned long size_avail);
10166+#else
10167+static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
10168+static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
10169+
10170+static inline void omap_vram_reserve_sdram(void) { }
10171+static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10172+ unsigned long sram_vstart,
10173+ unsigned long sram_size,
10174+ unsigned long pstart_avail,
10175+ unsigned long size_avail)
10176+{
10177+ return 0;
10178+}
10179+#endif
10180+
10181+#endif
10182Index: linux-2.6.35/arch/arm/plat-omap/include/mach/vrfb.h
10183===================================================================
10184--- /dev/null 1970-01-01 00:00:00.000000000 +0000
10185@@ -0,0 +1,50 @@
10186+/*
10187+ * VRFB Rotation Engine
10188+ *
10189+ * Copyright (C) 2009 Nokia Corporation
10190+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10191+ *
10192+ * This program is free software; you can redistribute it and/or modify
10193+ * it under the terms of the GNU General Public License version 2 as
10194+ * published by the Free Software Foundation.
10195+ *
10196+ * This program is distributed in the hope that it will be useful, but
10197+ * WITHOUT ANY WARRANTY; without even the implied warranty of
10198+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10199+ * General Public License for more details.
10200+ *
10201+ * You should have received a copy of the GNU General Public License along
10202+ * with this program; if not, write to the Free Software Foundation, Inc.,
10203+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10204+ */
10205+
10206+#ifndef __OMAP_VRFB_H__
10207+#define __OMAP_VRFB_H__
10208+
10209+#define OMAP_VRFB_LINE_LEN 2048
10210+
10211+struct vrfb {
10212+ u8 context;
10213+ void __iomem *vaddr[4];
10214+ unsigned long paddr[4];
10215+ u16 xres;
10216+ u16 yres;
10217+ u16 xoffset;
10218+ u16 yoffset;
10219+ u8 bytespp;
10220+ bool yuv_mode;
10221+};
10222+
10223+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
10224+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
10225+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
10226+ u8 bytespp);
10227+extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
10228+extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
10229+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
10230+ u16 width, u16 height,
10231+ unsigned bytespp, bool yuv_mode);
10232+extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
10233+extern void omap_vrfb_restore_context(void);
10234+
10235+#endif /* __VRFB_H */
10236Index: linux-2.6.35/arch/arm/plat-omap/include/plat/cbus.h
10237===================================================================
10238--- /dev/null 1970-01-01 00:00:00.000000000 +0000
10239@@ -0,0 +1,31 @@
10240+/*
10241+ * cbus.h - CBUS platform_data definition
10242+ *
10243+ * Copyright (C) 2004 - 2009 Nokia Corporation
10244+ *
10245+ * Written by Felipe Balbi <felipe.balbi@nokia.com>
10246+ *
10247+ * This file is subject to the terms and conditions of the GNU General
10248+ * Public License. See the file "COPYING" in the main directory of this
10249+ * archive for more details.
10250+ *
10251+ * This program is distributed in the hope that it will be useful,
10252+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10253+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10254+ * GNU General Public License for more details.
10255+ *
10256+ * You should have received a copy of the GNU General Public License
10257+ * along with this program; if not, write to the Free Software
10258+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10259+ */
10260+
10261+#ifndef __PLAT_CBUS_H
10262+#define __PLAT_CBUS_H
10263+
10264+struct cbus_host_platform_data {
10265+ int dat_gpio;
10266+ int clk_gpio;
10267+ int sel_gpio;
10268+};
10269+
10270+#endif /* __PLAT_CBUS_H */
10271Index: linux-2.6.35/arch/arm/plat-omap/Kconfig
10272===================================================================
10273--- linux-2.6.35.orig/arch/arm/plat-omap/Kconfig 2010-08-08 12:56:11.000000000 +0200
10274@@ -65,6 +65,30 @@ config OMAP_RESET_CLOCKS
10275       probably do not want this option enabled until your
10276       device drivers work properly.
10277
10278+config OMAP_BOOT_TAG
10279+ bool "OMAP bootloader information passing"
10280+ depends on ARCH_OMAP
10281+ default n
10282+ help
10283+ Say Y, if you have a bootloader which passes information
10284+ about your board and its peripheral configuration.
10285+
10286+config OMAP_BOOT_REASON
10287+ bool "Support for boot reason"
10288+ depends on OMAP_BOOT_TAG
10289+ default n
10290+ help
10291+ Say Y, if you want to have a procfs entry for reading the boot
10292+ reason in user-space.
10293+
10294+config OMAP_COMPONENT_VERSION
10295+ bool "Support for component version display"
10296+ depends on OMAP_BOOT_TAG && PROC_FS
10297+ default n
10298+ help
10299+ Say Y, if you want to have a procfs entry for reading component
10300+ versions (supplied by the bootloader) in user-space.
10301+
10302 config OMAP_MUX
10303     bool "OMAP multiplexing support"
10304     depends on ARCH_OMAP
10305Index: linux-2.6.35/arch/arm/plat-omap/Makefile
10306===================================================================
10307--- linux-2.6.35.orig/arch/arm/plat-omap/Makefile 2010-08-08 12:56:11.000000000 +0200
10308@@ -22,6 +22,8 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-
10309
10310 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
10311 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
10312+obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
10313+obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
10314 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
10315 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
10316 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
10317Index: linux-2.6.35/arch/arm/include/asm/setup.h
10318===================================================================
10319--- linux-2.6.35.orig/arch/arm/include/asm/setup.h 2010-08-08 12:56:16.000000000 +0200
10320@@ -136,6 +136,13 @@ struct tag_acorn {
10321     __u8 adfsdrives;
10322 };
10323
10324+/* TI OMAP specific information */
10325+#define ATAG_BOARD 0x414f4d50
10326+
10327+struct tag_omap {
10328+ u8 data[0];
10329+};
10330+
10331 /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
10332 #define ATAG_MEMCLK 0x41000402
10333
10334@@ -162,6 +169,11 @@ struct tag {
10335         struct tag_acorn acorn;
10336
10337         /*
10338+ * OMAP specific
10339+ */
10340+ struct tag_omap omap;
10341+
10342+ /*
10343          * DC21285 specific
10344          */
10345         struct tag_memclk memclk;
target/linux/omap24xx/patches-2.6.35/300-nokia-board.patch
1Index: linux-2.6.35/arch/arm/mach-omap1/board-nokia770.c
2===================================================================
3--- linux-2.6.35.orig/arch/arm/mach-omap1/board-nokia770.c 2010-08-08 12:56:15.000000000 +0200
4@@ -37,6 +37,7 @@
5 #include <plat/lcd_mipid.h>
6 #include <plat/mmc.h>
7 #include <plat/clock.h>
8+#include <plat/cbus.h>
9
10 #define ADS7846_PENDOWN_GPIO 15
11
12@@ -96,8 +97,23 @@ static struct platform_device nokia770_k
13     .resource = nokia770_kp_resources,
14 };
15
16+static struct cbus_host_platform_data nokia770_cbus_data = {
17+ .clk_gpio = OMAP_MPUIO(11),
18+ .dat_gpio = OMAP_MPUIO(10),
19+ .sel_gpio = OMAP_MPUIO(9),
20+};
21+
22+static struct platform_device nokia770_cbus_device = {
23+ .name = "cbus",
24+ .id = -1,
25+ .dev = {
26+ .platform_data = &nokia770_cbus_data,
27+ },
28+};
29+
30 static struct platform_device *nokia770_devices[] __initdata = {
31     &nokia770_kp_device,
32+ &nokia770_cbus_device,
33 };
34
35 static void mipid_shutdown(struct mipid_platform_data *pdata)
36Index: linux-2.6.35/arch/arm/mach-omap2/board-n8x0.c
37===================================================================
38--- linux-2.6.35.orig/arch/arm/mach-omap2/board-n8x0.c 2010-08-08 12:56:15.000000000 +0200
39@@ -18,8 +18,12 @@
40 #include <linux/io.h>
41 #include <linux/stddef.h>
42 #include <linux/i2c.h>
43+#include <linux/platform_device.h>
44 #include <linux/spi/spi.h>
45+#include <linux/spi/tsc2005.h>
46+#include <linux/input.h>
47 #include <linux/usb/musb.h>
48+#include <linux/i2c/lm8323.h>
49
50 #include <asm/mach/arch.h>
51 #include <asm/mach-types.h>
52@@ -32,6 +36,117 @@
53 #include <plat/onenand.h>
54 #include <plat/mmc.h>
55 #include <plat/serial.h>
56+#include <plat/cbus.h>
57+
58+#define RX51_TSC2005_RESET_GPIO 94
59+#define RX51_TSC2005_IRQ_GPIO 106
60+#define OMAP_TAG_NOKIA_BT 0x4e01
61+
62+static s16 rx44_keymap[LM8323_KEYMAP_SIZE] = {
63+ [0x01] = KEY_Q,
64+ [0x02] = KEY_K,
65+ [0x03] = KEY_O,
66+ [0x04] = KEY_P,
67+ [0x05] = KEY_BACKSPACE,
68+ [0x06] = KEY_A,
69+ [0x07] = KEY_S,
70+ [0x08] = KEY_D,
71+ [0x09] = KEY_F,
72+ [0x0a] = KEY_G,
73+ [0x0b] = KEY_H,
74+ [0x0c] = KEY_J,
75+
76+ [0x11] = KEY_W,
77+ [0x12] = KEY_F4,
78+ [0x13] = KEY_L,
79+ [0x14] = KEY_APOSTROPHE,
80+ [0x16] = KEY_Z,
81+ [0x17] = KEY_X,
82+ [0x18] = KEY_C,
83+ [0x19] = KEY_V,
84+ [0x1a] = KEY_B,
85+ [0x1b] = KEY_N,
86+ [0x1c] = KEY_LEFTSHIFT, /* Actually, this is both shift keys */
87+ [0x1f] = KEY_F7,
88+
89+ [0x21] = KEY_E,
90+ [0x22] = KEY_SEMICOLON,
91+ [0x23] = KEY_MINUS,
92+ [0x24] = KEY_EQUAL,
93+ [0x2b] = KEY_FN,
94+ [0x2c] = KEY_M,
95+ [0x2f] = KEY_F8,
96+
97+ [0x31] = KEY_R,
98+ [0x32] = KEY_RIGHTCTRL,
99+ [0x34] = KEY_SPACE,
100+ [0x35] = KEY_COMMA,
101+ [0x37] = KEY_UP,
102+ [0x3c] = KEY_COMPOSE,
103+ [0x3f] = KEY_F6,
104+
105+ [0x41] = KEY_T,
106+ [0x44] = KEY_DOT,
107+ [0x46] = KEY_RIGHT,
108+ [0x4f] = KEY_F5,
109+ [0x51] = KEY_Y,
110+ [0x53] = KEY_DOWN,
111+ [0x55] = KEY_ENTER,
112+ [0x5f] = KEY_ESC,
113+
114+ [0x61] = KEY_U,
115+ [0x64] = KEY_LEFT,
116+
117+ [0x71] = KEY_I,
118+ [0x75] = KEY_KPENTER,
119+};
120+
121+static struct lm8323_platform_data lm8323_pdata = {
122+ .repeat = 0, /* Repeat is handled in userspace for now. */
123+ .keymap = rx44_keymap,
124+ .size_x = 8,
125+ .size_y = 12,
126+ .debounce_time = 12,
127+ .active_time = 500,
128+
129+ .name = "Internal keyboard",
130+ .pwm_names[0] = "n810::keyboard",
131+ .pwm_names[1] = "n810::cover",
132+ //.pwm1_name = "n810::keyboard",
133+ //.pwm2_name = "n810::cover",
134+};
135+
136+struct omap_bluetooth_config {
137+ u8 chip_type;
138+ u8 bt_wakeup_gpio;
139+ u8 host_wakeup_gpio;
140+ u8 reset_gpio;
141+ u8 bt_uart;
142+ u8 bd_addr[6];
143+ u8 bt_sysclk;
144+};
145+
146+static struct platform_device n8x0_bt_device = {
147+ .name = "hci_h4p",
148+ .id = -1,
149+ .num_resources = 0,
150+};
151+
152+void __init n8x0_bt_init(void)
153+{
154+ const struct omap_bluetooth_config *bt_config;
155+
156+ bt_config = (void *) omap_get_config(OMAP_TAG_NOKIA_BT,
157+ struct omap_bluetooth_config);
158+ n8x0_bt_device.dev.platform_data = (void *) bt_config;
159+ if (platform_device_register(&n8x0_bt_device) < 0)
160+ BUG();
161+}
162+
163+static struct omap2_mcspi_device_config mipid_mcspi_config = {
164+ .turbo_mode = 0,
165+ .single_channel = 1,
166+};
167
168 static int slot1_cover_open;
169 static int slot2_cover_open;
170@@ -139,7 +254,34 @@ static struct omap2_mcspi_device_config
171     .single_channel = 1,
172 };
173
174+#ifdef CONFIG_MACH_NOKIA_N8X0_LCD
175+extern struct mipid_platform_data n8x0_mipid_platform_data;
176+#endif
177+
178+#ifdef CONFIG_TOUCHSCREEN_TSC2005
179+static struct tsc2005_platform_data tsc2005_config;
180+static void rx51_tsc2005_set_reset(bool enable)
181+{
182+ gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
183+}
184+
185+static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
186+ .turbo_mode = 0,
187+ .single_channel = 1,
188+};
189+#endif
190+
191 static struct spi_board_info n800_spi_board_info[] __initdata = {
192+#ifdef CONFIG_MACH_NOKIA_N8X0_LCD
193+ {
194+ .modalias = "lcd_mipid",
195+ .bus_num = 1,
196+ .chip_select = 1,
197+ .max_speed_hz = 4000000,
198+ .controller_data= &mipid_mcspi_config,
199+ .platform_data = &n8x0_mipid_platform_data,
200+ },
201+#endif
202     {
203         .modalias = "p54spi",
204         .bus_num = 2,
205@@ -147,6 +289,68 @@ static struct spi_board_info n800_spi_bo
206         .max_speed_hz = 48000000,
207         .controller_data = &p54spi_mcspi_config,
208     },
209+ {
210+ .modalias = "tsc2005",
211+ .bus_num = 1,
212+ .chip_select = 0,
213+ .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
214+ .max_speed_hz = 6000000,
215+ .controller_data = &tsc2005_mcspi_config,
216+ .platform_data = &tsc2005_config,
217+ },
218+};
219+
220+static void __init tsc2005_set_config(void)
221+{
222+ const struct omap_lcd_config *conf;
223+
224+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
225+ if (conf != NULL) {
226+#ifdef CONFIG_TOUCHSCREEN_TSC2005
227+ if (strcmp(conf->panel_name, "lph8923") == 0) {
228+ tsc2005_config.ts_x_plate_ohm = 180;
229+ tsc2005_config.ts_hw_avg = 0;
230+ tsc2005_config.ts_ignore_last = 0;
231+ tsc2005_config.ts_touch_pressure = 1500;
232+ tsc2005_config.ts_stab_time = 100;
233+ tsc2005_config.ts_pressure_max = 2048;
234+ tsc2005_config.ts_pressure_fudge = 2;
235+ tsc2005_config.ts_x_max = 4096;
236+ tsc2005_config.ts_x_fudge = 4;
237+ tsc2005_config.ts_y_max = 4096;
238+ tsc2005_config.ts_y_fudge = 7;
239+ tsc2005_config.set_reset = rx51_tsc2005_set_reset;
240+ } else if (strcmp(conf->panel_name, "ls041y3") == 0) {
241+ tsc2005_config.ts_x_plate_ohm = 280;
242+ tsc2005_config.ts_hw_avg = 0;
243+ tsc2005_config.ts_ignore_last = 0;
244+ tsc2005_config.ts_touch_pressure = 1500;
245+ tsc2005_config.ts_stab_time = 1000;
246+ tsc2005_config.ts_pressure_max = 2048;
247+ tsc2005_config.ts_pressure_fudge = 2;
248+ tsc2005_config.ts_x_max = 4096;
249+ tsc2005_config.ts_x_fudge = 4;
250+ tsc2005_config.ts_y_max = 4096;
251+ tsc2005_config.ts_y_fudge = 7;
252+ tsc2005_config.set_reset = rx51_tsc2005_set_reset;
253+ } else {
254+ printk(KERN_ERR "Unknown panel type, set default "
255+ "touchscreen configuration\n");
256+ tsc2005_config.ts_x_plate_ohm = 200;
257+ tsc2005_config.ts_stab_time = 100;
258+ }
259+#endif
260+ }
261+}
262+
263+static struct i2c_board_info __initdata_or_module n8x0_i2c_board_info_2[] = {};
264+
265+static struct i2c_board_info __initdata_or_module n810_i2c_board_info_2[] = {
266+ {
267+ I2C_BOARD_INFO("lm8323", 0x45),
268+ .irq = OMAP_GPIO_IRQ(109),
269+ .platform_data = &lm8323_pdata,
270+ },
271 };
272
273 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
274@@ -181,6 +385,20 @@ static struct mtd_partition onenand_part
275     },
276 };
277
278+static struct cbus_host_platform_data n8x0_cbus_data = {
279+ .clk_gpio = 66,
280+ .dat_gpio = 65,
281+ .sel_gpio = 64,
282+};
283+
284+static struct platform_device n8x0_cbus_device = {
285+ .name = "cbus",
286+ .id = -1,
287+ .dev = {
288+ .platform_data = &n8x0_cbus_data,
289+ },
290+};
291+
292 static struct omap_onenand_platform_data board_onenand_data = {
293     .cs = 0,
294     .gpio_irq = 26,
295@@ -649,14 +867,37 @@ static void __init n8x0_init_irq(void)
296     omap_gpio_init();
297 }
298
299+#ifdef CONFIG_MACH_NOKIA_N8X0_LCD
300+extern void n8x0_mipid_init(void);
301+extern void n8x0_blizzard_init(void);
302+#else
303+#define n8x0_mipid_init() 0
304+#define n8x0_blizzard_init() 0
305+#endif
306+
307 static void __init n8x0_init_machine(void)
308 {
309+ platform_device_register(&n8x0_cbus_device);
310+
311+ n8x0_bt_init();
312+
313     /* FIXME: add n810 spi devices */
314+ tsc2005_set_config();
315     spi_register_board_info(n800_spi_board_info,
316                 ARRAY_SIZE(n800_spi_board_info));
317
318     omap_serial_init();
319     n8x0_menelaus_init();
320+
321+ omap_register_i2c_bus(2, 400, n8x0_i2c_board_info_2,
322+ ARRAY_SIZE(n8x0_i2c_board_info_2));
323+
324+ i2c_register_board_info(2, n810_i2c_board_info_2,
325+ ARRAY_SIZE(n810_i2c_board_info_2));
326+
327+ n8x0_mipid_init();
328+ n8x0_blizzard_init();
329+
330     n8x0_onenand_init();
331     n8x0_mmc_init();
332     n8x0_usb_init();
333Index: linux-2.6.35/arch/arm/mach-omap2/board-n8x0-lcd.c
334===================================================================
335--- /dev/null 1970-01-01 00:00:00.000000000 +0000
336@@ -0,0 +1,127 @@
337+/*
338+ * linux/arch/arm/mach-omap2/board-n8x0.c
339+ *
340+ * Copyright (C) 2005-2009 Nokia Corporation
341+ * Author: Juha Yrjola <juha.yrjola@nokia.com>
342+ *
343+ * Modified from mach-omap2/board-generic.c
344+ *
345+ * This program is free software; you can redistribute it and/or modify
346+ * it under the terms of the GNU General Public License version 2 as
347+ * published by the Free Software Foundation.
348+ */
349+
350+#include <linux/clk.h>
351+#include <linux/delay.h>
352+#include <linux/gpio.h>
353+#include <linux/omapfb.h>
354+
355+#include <plat/lcd_mipid.h>
356+#include <plat/blizzard.h>
357+
358+#include <../drivers/cbus/tahvo.h>
359+
360+#define N8X0_BLIZZARD_POWERDOWN_GPIO 15
361+
362+// MIPID LCD Panel
363+
364+static void mipid_shutdown(struct mipid_platform_data *pdata)
365+{
366+ if (pdata->nreset_gpio != -1) {
367+ pr_info("shutdown LCD\n");
368+ gpio_set_value(pdata->nreset_gpio, 0);
369+ msleep(120);
370+ }
371+}
372+
373+struct mipid_platform_data n8x0_mipid_platform_data = {
374+ .shutdown = mipid_shutdown,
375+};
376+
377+void __init n8x0_mipid_init(void)
378+{
379+ const struct omap_lcd_config *conf;
380+
381+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
382+ if (conf != NULL) {
383+ n8x0_mipid_platform_data.nreset_gpio = conf->nreset_gpio;
384+ n8x0_mipid_platform_data.data_lines = conf->data_lines;
385+ printk(KERN_INFO "N8x0 MIPID config loaded");
386+ }
387+ else
388+ printk(KERN_INFO "N8x0 MIPID config not provided");
389+}
390+
391+
392+// Epson Blizzard LCD Controller
393+
394+static struct {
395+ struct clk *sys_ck;
396+} blizzard;
397+
398+static int blizzard_get_clocks(void)
399+{
400+ blizzard.sys_ck = clk_get(0, "osc_ck");
401+ if (IS_ERR(blizzard.sys_ck)) {
402+ printk(KERN_ERR "can't get Blizzard clock\n");
403+ return PTR_ERR(blizzard.sys_ck);
404+ }
405+ return 0;
406+}
407+
408+static unsigned long blizzard_get_clock_rate(struct device *dev)
409+{
410+ return clk_get_rate(blizzard.sys_ck);
411+}
412+
413+static void blizzard_enable_clocks(int enable)
414+{
415+ if (enable)
416+ clk_enable(blizzard.sys_ck);
417+ else
418+ clk_disable(blizzard.sys_ck);
419+}
420+
421+static void blizzard_power_up(struct device *dev)
422+{
423+ /* Vcore to 1.475V */
424+ tahvo_set_clear_reg_bits(0x07, 0, 0xf);
425+ msleep(10);
426+
427+ blizzard_enable_clocks(1);
428+ gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 1);
429+}
430+
431+static void blizzard_power_down(struct device *dev)
432+{
433+ gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 0);
434+ blizzard_enable_clocks(0);
435+
436+ /* Vcore to 1.005V */
437+ tahvo_set_clear_reg_bits(0x07, 0xf, 0);
438+}
439+
440+static struct blizzard_platform_data n8x0_blizzard_data = {
441+ .power_up = blizzard_power_up,
442+ .power_down = blizzard_power_down,
443+ .get_clock_rate = blizzard_get_clock_rate,
444+ .te_connected = 1,
445+};
446+
447+void __init n8x0_blizzard_init(void)
448+{
449+ int r;
450+
451+ r = gpio_request(N8X0_BLIZZARD_POWERDOWN_GPIO, "Blizzard pd");
452+ if (r < 0)
453+ {
454+ printk(KERN_ERR "Can't get N8x0 Blizzard powerdown GPIO %d\n", N8X0_BLIZZARD_POWERDOWN_GPIO);
455+ return;
456+ }
457+ gpio_direction_output(N8X0_BLIZZARD_POWERDOWN_GPIO, 1);
458+
459+ blizzard_get_clocks();
460+ omapfb_set_ctrl_platform_data(&n8x0_blizzard_data);
461+
462+ printk(KERN_INFO "N8x0 Blizzard initialized");
463+}
464Index: linux-2.6.35/arch/arm/mach-omap2/board-n8x0-usb.c
465===================================================================
466--- /dev/null 1970-01-01 00:00:00.000000000 +0000
467@@ -0,0 +1,175 @@
468+/*
469+ * linux/arch/arm/mach-omap2/board-n8x0-usb.c
470+ *
471+ * Copyright (C) 2006 Nokia Corporation
472+ * Author: Juha Yrjola
473+ *
474+ * This program is free software; you can redistribute it and/or modify
475+ * it under the terms of the GNU General Public License version 2 as
476+ * published by the Free Software Foundation.
477+ */
478+
479+#include <linux/types.h>
480+#include <linux/delay.h>
481+#include <linux/platform_device.h>
482+#include <linux/clk.h>
483+#include <linux/err.h>
484+#include <linux/gpio.h>
485+#include <linux/usb/musb.h>
486+
487+#include <plat/gpmc.h>
488+
489+#define TUSB_ASYNC_CS 1
490+#define TUSB_SYNC_CS 4
491+#define GPIO_TUSB_INT 58
492+#define GPIO_TUSB_ENABLE 0
493+
494+static int tusb_set_power(int state);
495+static int tusb_set_clock(struct clk *osc_ck, int state);
496+
497+#if defined(CONFIG_USB_MUSB_OTG)
498+# define BOARD_MODE MUSB_OTG
499+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
500+# define BOARD_MODE MUSB_PERIPHERAL
501+#else /* defined(CONFIG_USB_MUSB_HOST) */
502+# define BOARD_MODE MUSB_HOST
503+#endif
504+
505+static struct musb_hdrc_eps_bits musb_eps[] = {
506+ { "ep1_tx", 5, },
507+ { "ep1_rx", 5, },
508+ { "ep2_tx", 5, },
509+ { "ep2_rx", 5, },
510+ { "ep3_tx", 3, },
511+ { "ep3_rx", 3, },
512+ { "ep4_tx", 3, },
513+ { "ep4_rx", 3, },
514+ { "ep5_tx", 2, },
515+ { "ep5_rx", 2, },
516+ { "ep6_tx", 2, },
517+ { "ep6_rx", 2, },
518+ { "ep7_tx", 2, },
519+ { "ep7_rx", 2, },
520+ { "ep8_tx", 2, },
521+ { "ep8_rx", 2, },
522+ { "ep9_tx", 2, },
523+ { "ep9_rx", 2, },
524+ { "ep10_tx", 2, },
525+ { "ep10_rx", 2, },
526+ { "ep11_tx", 2, },
527+ { "ep11_rx", 2, },
528+ { "ep12_tx", 2, },
529+ { "ep12_rx", 2, },
530+ { "ep13_tx", 2, },
531+ { "ep13_rx", 2, },
532+ { "ep14_tx", 2, },
533+ { "ep14_rx", 2, },
534+ { "ep15_tx", 2, },
535+ { "ep15_rx", 2, },
536+};
537+
538+static struct musb_hdrc_config musb_config = {
539+ .multipoint = 1,
540+ .dyn_fifo = 1,
541+ .soft_con = 1,
542+ .dma = 1,
543+ .num_eps = 16,
544+ .dma_channels = 7,
545+ .ram_bits = 12,
546+ .eps_bits = musb_eps,
547+};
548+
549+static struct musb_hdrc_platform_data tusb_data = {
550+ .mode = BOARD_MODE,
551+ .set_power = tusb_set_power,
552+ .set_clock = tusb_set_clock,
553+ .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
554+ .power = 100, /* Max 100 mA VBUS for host mode */
555+ .clock = "osc_ck",
556+ .config = &musb_config,
557+};
558+
559+/*
560+ * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
561+ * 1.5 V voltage regulators of PM companion chip. Companion chip will then
562+ * provide then PGOOD signal to TUSB6010 which will release it from reset.
563+ */
564+static int tusb_set_power(int state)
565+{
566+ int i, retval = 0;
567+
568+ if (state) {
569+ gpio_set_value(GPIO_TUSB_ENABLE, 1);
570+ msleep(1);
571+
572+ /* Wait until TUSB6010 pulls INT pin down */
573+ i = 100;
574+ while (i && gpio_get_value(GPIO_TUSB_INT)) {
575+ msleep(1);
576+ i--;
577+ }
578+
579+ if (!i) {
580+ printk(KERN_ERR "tusb: powerup failed\n");
581+ retval = -ENODEV;
582+ }
583+ } else {
584+ gpio_set_value(GPIO_TUSB_ENABLE, 0);
585+ msleep(10);
586+ }
587+
588+ return retval;
589+}
590+
591+static int osc_ck_on;
592+
593+static int tusb_set_clock(struct clk *osc_ck, int state)
594+{
595+ if (state) {
596+ if (osc_ck_on > 0)
597+ return -ENODEV;
598+
599+ //omap2_block_sleep();
600+ clk_enable(osc_ck);
601+ osc_ck_on = 1;
602+ } else {
603+ if (osc_ck_on == 0)
604+ return -ENODEV;
605+
606+ clk_disable(osc_ck);
607+ osc_ck_on = 0;
608+ //omap2_allow_sleep();
609+ }
610+
611+ return 0;
612+}
613+
614+void __init n8x0_usb_init(void)
615+{
616+ int ret = 0;
617+ static char announce[] __initdata = KERN_INFO "TUSB 6010\n";
618+
619+ /* PM companion chip power control pin */
620+ ret = gpio_request(GPIO_TUSB_ENABLE, "TUSB6010 enable");
621+ if (ret != 0) {
622+ printk(KERN_ERR "Could not get TUSB power GPIO%i\n",
623+ GPIO_TUSB_ENABLE);
624+ return;
625+ }
626+ gpio_direction_output(GPIO_TUSB_ENABLE, 0);
627+
628+ tusb_set_power(0);
629+
630+ ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
631+ TUSB_ASYNC_CS, TUSB_SYNC_CS,
632+ GPIO_TUSB_INT, 0x3f);
633+ if (ret != 0)
634+ goto err;
635+
636+ printk(announce);
637+
638+ return;
639+
640+err:
641+ gpio_free(GPIO_TUSB_ENABLE);
642+}
643Index: linux-2.6.35/arch/arm/mach-omap2/control.c
644===================================================================
645--- linux-2.6.35.orig/arch/arm/mach-omap2/control.c 2010-08-08 12:56:15.000000000 +0200
646@@ -162,6 +162,7 @@ u16 omap_ctrl_readw(u16 offset)
647     return __raw_readw(OMAP_CTRL_REGADDR(offset));
648 }
649
650+EXPORT_SYMBOL_GPL(omap_ctrl_readl);
651 u32 omap_ctrl_readl(u16 offset)
652 {
653     return __raw_readl(OMAP_CTRL_REGADDR(offset));
654@@ -177,6 +178,7 @@ void omap_ctrl_writew(u16 val, u16 offse
655     __raw_writew(val, OMAP_CTRL_REGADDR(offset));
656 }
657
658+EXPORT_SYMBOL_GPL(omap_ctrl_writel);
659 void omap_ctrl_writel(u32 val, u16 offset)
660 {
661     __raw_writel(val, OMAP_CTRL_REGADDR(offset));
662Index: linux-2.6.35/arch/arm/mach-omap2/Kconfig
663===================================================================
664--- linux-2.6.35.orig/arch/arm/mach-omap2/Kconfig 2010-08-08 12:56:15.000000000 +0200
665@@ -116,6 +116,16 @@ config MACH_NOKIA_N8X0
666     select MACH_NOKIA_N810
667     select MACH_NOKIA_N810_WIMAX
668
669+config MACH_NOKIA_N8X0_LCD
670+ bool
671+ depends on MACH_NOKIA_N8X0 && FB_OMAP_LCDC_BLIZZARD && FB_OMAP_LCD_MIPID
672+ default y
673+
674+config MACH_NOKIA_N8X0_USB
675+ bool
676+ depends on MACH_NOKIA_N8X0 && MACH_OMAP2_TUSB6010
677+ default y
678+
679 config MACH_NOKIA_RX51
680     bool "Nokia RX-51 board"
681     depends on ARCH_OMAP3
682Index: linux-2.6.35/arch/arm/mach-omap2/Makefile
683===================================================================
684--- linux-2.6.35.orig/arch/arm/mach-omap2/Makefile 2010-08-08 12:56:15.000000000 +0200
685@@ -116,6 +116,8 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += boar
686                        hsmmc.o \
687                        board-sdp-flash.o
688 obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
689+obj-$(CONFIG_MACH_NOKIA_N8X0_LCD) += board-n8x0-lcd.o
690+obj-$(CONFIG_MACH_NOKIA_N8X0_USB) += board-n8x0-usb.o
691 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
692                        board-rx51-sdram.o \
693                        board-rx51-peripherals.o \
694Index: linux-2.6.35/arch/arm/mach-omap2/serial.c
695===================================================================
696--- linux-2.6.35.orig/arch/arm/mach-omap2/serial.c 2010-08-08 12:56:15.000000000 +0200
697@@ -495,10 +495,10 @@ static void omap_uart_idle_init(struct o
698         uart->padconf = 0;
699     }
700
701- p->irqflags |= IRQF_SHARED;
702+/* p->irqflags |= IRQF_SHARED;
703     ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
704               "serial idle", (void *)uart);
705- WARN_ON(ret);
706+ WARN_ON(ret); */
707 }
708
709 void omap_uart_enable_irqs(int enable)
710@@ -506,13 +506,13 @@ void omap_uart_enable_irqs(int enable)
711     int ret;
712     struct omap_uart_state *uart;
713
714- list_for_each_entry(uart, &uart_list, node) {
715+/* list_for_each_entry(uart, &uart_list, node) {
716         if (enable)
717             ret = request_irq(uart->p->irq, omap_uart_interrupt,
718                 IRQF_SHARED, "serial idle", (void *)uart);
719         else
720             free_irq(uart->p->irq, (void *)uart);
721- }
722+ } */
723 }
724
725 static ssize_t sleep_timeout_show(struct device *dev,
target/linux/omap24xx/patches-2.6.35/400-bluetooth-hci_h4p.patch
1Index: linux-2.6.35/drivers/bluetooth/hci_h4p/core.c
2===================================================================
3--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4@@ -0,0 +1,1023 @@
5+/*
6+ * This file is part of hci_h4p bluetooth driver
7+ *
8+ * Copyright (C) 2005, 2006 Nokia Corporation.
9+ *
10+ * Contact: Ville Tervo <ville.tervo@nokia.com>
11+ *
12+ * This program is free software; you can redistribute it and/or
13+ * modify it under the terms of the GNU General Public License
14+ * version 2 as published by the Free Software Foundation.
15+ *
16+ * This program is distributed in the hope that it will be useful, but
17+ * WITHOUT ANY WARRANTY; without even the implied warranty of
18+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19+ * General Public License for more details.
20+ *
21+ * You should have received a copy of the GNU General Public License
22+ * along with this program; if not, write to the Free Software
23+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24+ * 02110-1301 USA
25+ *
26+ */
27+
28+#include <linux/module.h>
29+
30+#include <linux/kernel.h>
31+#include <linux/init.h>
32+#include <linux/errno.h>
33+#include <linux/delay.h>
34+#include <linux/spinlock.h>
35+#include <linux/serial_reg.h>
36+#include <linux/skbuff.h>
37+#include <linux/timer.h>
38+#include <linux/device.h>
39+#include <linux/platform_device.h>
40+#include <linux/clk.h>
41+#include <linux/gpio.h>
42+
43+#include <mach/hardware.h>
44+#include <mach/board.h>
45+#include <mach/irqs.h>
46+//#include <mach/pm.h>
47+
48+#include <net/bluetooth/bluetooth.h>
49+#include <net/bluetooth/hci_core.h>
50+#include <net/bluetooth/hci.h>
51+
52+#include "hci_h4p.h"
53+
54+#define PM_TIMEOUT 200
55+
56+struct omap_bluetooth_config {
57+ u8 chip_type;
58+ u8 bt_wakeup_gpio;
59+ u8 host_wakeup_gpio;
60+ u8 reset_gpio;
61+ u8 bt_uart;
62+ u8 bd_addr[6];
63+ u8 bt_sysclk;
64+};
65+
66+/* This should be used in function that cannot release clocks */
67+static void hci_h4p_set_clk(struct hci_h4p_info *info, int *clock, int enable)
68+{
69+ unsigned long flags;
70+
71+ spin_lock_irqsave(&info->clocks_lock, flags);
72+ if (enable && !*clock) {
73+ NBT_DBG_POWER("Enabling %p\n", clock);
74+ clk_enable(info->uart_fclk);
75+#ifdef CONFIG_ARCH_OMAP2
76+ if (cpu_is_omap24xx()) {
77+ clk_enable(info->uart_iclk);
78+ //omap2_block_sleep();
79+ }
80+#endif
81+ }
82+ if (!enable && *clock) {
83+ NBT_DBG_POWER("Disabling %p\n", clock);
84+ clk_disable(info->uart_fclk);
85+#ifdef CONFIG_ARCH_OMAP2
86+ if (cpu_is_omap24xx()) {
87+ clk_disable(info->uart_iclk);
88+ //omap2_allow_sleep();
89+ }
90+#endif
91+ }
92+
93+ *clock = enable;
94+ spin_unlock_irqrestore(&info->clocks_lock, flags);
95+}
96+
97+/* Power management functions */
98+static void hci_h4p_disable_tx(struct hci_h4p_info *info)
99+{
100+ NBT_DBG_POWER("\n");
101+
102+ if (!info->pm_enabled)
103+ return;
104+
105+ mod_timer(&info->tx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
106+}
107+
108+static void hci_h4p_enable_tx(struct hci_h4p_info *info)
109+{
110+ NBT_DBG_POWER("\n");
111+
112+ if (!info->pm_enabled)
113+ return;
114+
115+ del_timer_sync(&info->tx_pm_timer);
116+ if (info->tx_pm_enabled) {
117+ info->tx_pm_enabled = 0;
118+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
119+ gpio_set_value(info->bt_wakeup_gpio, 1);
120+ }
121+}
122+
123+static void hci_h4p_tx_pm_timer(unsigned long data)
124+{
125+ struct hci_h4p_info *info;
126+
127+ NBT_DBG_POWER("\n");
128+
129+ info = (struct hci_h4p_info *)data;
130+
131+ if (hci_h4p_inb(info, UART_LSR) & UART_LSR_TEMT) {
132+ gpio_set_value(info->bt_wakeup_gpio, 0);
133+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
134+ info->tx_pm_enabled = 1;
135+ }
136+ else {
137+ mod_timer(&info->tx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
138+ }
139+}
140+
141+static void hci_h4p_disable_rx(struct hci_h4p_info *info)
142+{
143+ if (!info->pm_enabled)
144+ return;
145+
146+ mod_timer(&info->rx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
147+}
148+
149+static void hci_h4p_enable_rx(struct hci_h4p_info *info)
150+{
151+ unsigned long flags;
152+
153+ if (!info->pm_enabled)
154+ return;
155+
156+ del_timer_sync(&info->rx_pm_timer);
157+ spin_lock_irqsave(&info->lock, flags);
158+ if (info->rx_pm_enabled) {
159+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
160+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_RDI);
161+ __hci_h4p_set_auto_ctsrts(info, 1, UART_EFR_RTS);
162+ info->rx_pm_enabled = 0;
163+ }
164+ spin_unlock_irqrestore(&info->lock, flags);
165+}
166+
167+static void hci_h4p_rx_pm_timer(unsigned long data)
168+{
169+ unsigned long flags;
170+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
171+
172+ spin_lock_irqsave(&info->lock, flags);
173+ if (!(hci_h4p_inb(info, UART_LSR) & UART_LSR_DR)) {
174+ __hci_h4p_set_auto_ctsrts(info, 0, UART_EFR_RTS);
175+ hci_h4p_set_rts(info, 0);
176+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_RDI);
177+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
178+ info->rx_pm_enabled = 1;
179+ }
180+ else {
181+ mod_timer(&info->rx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
182+ }
183+ spin_unlock_irqrestore(&info->lock, flags);
184+}
185+
186+/* Negotiation functions */
187+int hci_h4p_send_alive_packet(struct hci_h4p_info *info)
188+{
189+ NBT_DBG("Sending alive packet\n");
190+
191+ if (!info->alive_cmd_skb)
192+ return -EINVAL;
193+
194+ /* Keep reference to buffer so we can reuse it */
195+ info->alive_cmd_skb = skb_get(info->alive_cmd_skb);
196+
197+ skb_queue_tail(&info->txq, info->alive_cmd_skb);
198+ tasklet_schedule(&info->tx_task);
199+
200+ NBT_DBG("Alive packet sent\n");
201+
202+ return 0;
203+}
204+
205+static void hci_h4p_alive_packet(struct hci_h4p_info *info, struct sk_buff *skb)
206+{
207+ NBT_DBG("Received alive packet\n");
208+ if (skb->data[1] == 0xCC) {
209+ complete(&info->init_completion);
210+ }
211+
212+ kfree_skb(skb);
213+}
214+
215+static int hci_h4p_send_negotiation(struct hci_h4p_info *info, struct sk_buff *skb)
216+{
217+ NBT_DBG("Sending negotiation..\n");
218+
219+ hci_h4p_change_speed(info, INIT_SPEED);
220+
221+ info->init_error = 0;
222+ init_completion(&info->init_completion);
223+ skb_queue_tail(&info->txq, skb);
224+ tasklet_schedule(&info->tx_task);
225+
226+ if (!wait_for_completion_interruptible_timeout(&info->init_completion,
227+ msecs_to_jiffies(1000)))
228+ return -ETIMEDOUT;
229+
230+ NBT_DBG("Negotiation sent\n");
231+ return info->init_error;
232+}
233+
234+static void hci_h4p_negotiation_packet(struct hci_h4p_info *info,
235+ struct sk_buff *skb)
236+{
237+ int err = 0;
238+
239+ if (skb->data[1] == 0x20) {
240+ /* Change to operational settings */
241+ hci_h4p_set_rts(info, 0);
242+
243+ err = hci_h4p_wait_for_cts(info, 0, 100);
244+ if (err < 0)
245+ goto neg_ret;
246+
247+ hci_h4p_change_speed(info, MAX_BAUD_RATE);
248+
249+ err = hci_h4p_wait_for_cts(info, 1, 100);
250+ if (err < 0)
251+ goto neg_ret;
252+
253+ hci_h4p_set_auto_ctsrts(info, 1, UART_EFR_CTS | UART_EFR_RTS);
254+
255+ err = hci_h4p_send_alive_packet(info);
256+ if (err < 0)
257+ goto neg_ret;
258+ } else {
259+ dev_err(info->dev, "Could not negotiate hci_h4p settings\n");
260+ err = -EINVAL;
261+ goto neg_ret;
262+ }
263+
264+ kfree_skb(skb);
265+ return;
266+
267+neg_ret:
268+ info->init_error = err;
269+ complete(&info->init_completion);
270+ kfree_skb(skb);
271+}
272+
273+/* H4 packet handling functions */
274+static int hci_h4p_get_hdr_len(struct hci_h4p_info *info, u8 pkt_type)
275+{
276+ long retval;
277+
278+ switch (pkt_type) {
279+ case H4_EVT_PKT:
280+ retval = HCI_EVENT_HDR_SIZE;
281+ break;
282+ case H4_ACL_PKT:
283+ retval = HCI_ACL_HDR_SIZE;
284+ break;
285+ case H4_SCO_PKT:
286+ retval = HCI_SCO_HDR_SIZE;
287+ break;
288+ case H4_NEG_PKT:
289+ retval = 11;
290+ break;
291+ case H4_ALIVE_PKT:
292+ retval = 3;
293+ break;
294+ default:
295+ dev_err(info->dev, "Unknown H4 packet type 0x%.2x\n", pkt_type);
296+ retval = -1;
297+ break;
298+ }
299+
300+ return retval;
301+}
302+
303+static unsigned int hci_h4p_get_data_len(struct hci_h4p_info *info,
304+ struct sk_buff *skb)
305+{
306+ long retval = -1;
307+ struct hci_event_hdr *evt_hdr;
308+ struct hci_acl_hdr *acl_hdr;
309+ struct hci_sco_hdr *sco_hdr;
310+
311+ switch (bt_cb(skb)->pkt_type) {
312+ case H4_EVT_PKT:
313+ evt_hdr = (struct hci_event_hdr *)skb->data;
314+ retval = evt_hdr->plen;
315+ break;
316+ case H4_ACL_PKT:
317+ acl_hdr = (struct hci_acl_hdr *)skb->data;
318+ retval = le16_to_cpu(acl_hdr->dlen);
319+ break;
320+ case H4_SCO_PKT:
321+ sco_hdr = (struct hci_sco_hdr *)skb->data;
322+ retval = sco_hdr->dlen;
323+ break;
324+ case H4_NEG_PKT:
325+ retval = 0;
326+ break;
327+ case H4_ALIVE_PKT:
328+ retval = 0;
329+ break;
330+ }
331+
332+ return retval;
333+}
334+
335+static inline void hci_h4p_recv_frame(struct hci_h4p_info *info,
336+ struct sk_buff *skb)
337+{
338+
339+ if (unlikely(!test_bit(HCI_RUNNING, &info->hdev->flags))) {
340+ NBT_DBG("fw_event\n");
341+ hci_h4p_parse_fw_event(info, skb);
342+ } else {
343+ hci_recv_frame(skb);
344+ NBT_DBG("Frame sent to upper layer\n");
345+ }
346+}
347+
348+static void hci_h4p_rx_tasklet(unsigned long data)
349+{
350+ u8 byte;
351+ unsigned long flags;
352+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
353+
354+ NBT_DBG("tasklet woke up\n");
355+ NBT_DBG_TRANSFER("rx_tasklet woke up\ndata ");
356+
357+ while (hci_h4p_inb(info, UART_LSR) & UART_LSR_DR) {
358+ byte = hci_h4p_inb(info, UART_RX);
359+ if (info->garbage_bytes) {
360+ info->garbage_bytes--;
361+ continue;
362+ }
363+ if (info->rx_skb == NULL) {
364+ info->rx_skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC | GFP_DMA);
365+ if (!info->rx_skb) {
366+ dev_err(info->dev, "Can't allocate memory for new packet\n");
367+ goto finish_task;
368+ }
369+ info->rx_state = WAIT_FOR_PKT_TYPE;
370+ info->rx_skb->dev = (void *)info->hdev;
371+ }
372+ info->hdev->stat.byte_rx++;
373+ NBT_DBG_TRANSFER_NF("0x%.2x ", byte);
374+ switch (info->rx_state) {
375+ case WAIT_FOR_PKT_TYPE:
376+ bt_cb(info->rx_skb)->pkt_type = byte;
377+ info->rx_count = hci_h4p_get_hdr_len(info, byte);
378+ if (info->rx_count < 0) {
379+ info->hdev->stat.err_rx++;
380+ kfree_skb(info->rx_skb);
381+ info->rx_skb = NULL;
382+ } else {
383+ info->rx_state = WAIT_FOR_HEADER;
384+ }
385+ break;
386+ case WAIT_FOR_HEADER:
387+ info->rx_count--;
388+ *skb_put(info->rx_skb, 1) = byte;
389+ if (info->rx_count == 0) {
390+ info->rx_count = hci_h4p_get_data_len(info, info->rx_skb);
391+ if (info->rx_count > skb_tailroom(info->rx_skb)) {
392+ dev_err(info->dev, "Frame is %ld bytes too long.\n",
393+ info->rx_count - skb_tailroom(info->rx_skb));
394+ kfree_skb(info->rx_skb);
395+ info->rx_skb = NULL;
396+ info->garbage_bytes = info->rx_count - skb_tailroom(info->rx_skb);
397+ break;
398+ }
399+ info->rx_state = WAIT_FOR_DATA;
400+
401+ if (bt_cb(info->rx_skb)->pkt_type == H4_NEG_PKT) {
402+ hci_h4p_negotiation_packet(info, info->rx_skb);
403+ info->rx_skb = NULL;
404+ info->rx_state = WAIT_FOR_PKT_TYPE;
405+ goto finish_task;
406+ }
407+ if (bt_cb(info->rx_skb)->pkt_type == H4_ALIVE_PKT) {
408+ hci_h4p_alive_packet(info, info->rx_skb);
409+ info->rx_skb = NULL;
410+ info->rx_state = WAIT_FOR_PKT_TYPE;
411+ goto finish_task;
412+ }
413+ }
414+ break;
415+ case WAIT_FOR_DATA:
416+ info->rx_count--;
417+ *skb_put(info->rx_skb, 1) = byte;
418+ if (info->rx_count == 0) {
419+ /* H4+ devices should allways send word aligned packets */
420+ if (!(info->rx_skb->len % 2)) {
421+ info->garbage_bytes++;
422+ }
423+ hci_h4p_recv_frame(info, info->rx_skb);
424+ info->rx_skb = NULL;
425+ }
426+ break;
427+ default:
428+ WARN_ON(1);
429+ break;
430+ }
431+ }
432+
433+finish_task:
434+ spin_lock_irqsave(&info->lock, flags);
435+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_RDI);
436+ spin_unlock_irqrestore(&info->lock, flags);
437+
438+ NBT_DBG_TRANSFER_NF("\n");
439+ NBT_DBG("rx_ended\n");
440+}
441+
442+static void hci_h4p_tx_tasklet(unsigned long data)
443+{
444+ unsigned int sent = 0;
445+ unsigned long flags;
446+ struct sk_buff *skb;
447+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
448+
449+ NBT_DBG("tasklet woke up\n");
450+ NBT_DBG_TRANSFER("tx_tasklet woke up\n data ");
451+
452+ skb = skb_dequeue(&info->txq);
453+ if (!skb) {
454+ /* No data in buffer */
455+ NBT_DBG("skb ready\n");
456+ hci_h4p_disable_tx(info);
457+ return;
458+ }
459+
460+ /* Copy data to tx fifo */
461+ while (!(hci_h4p_inb(info, UART_OMAP_SSR) & UART_OMAP_SSR_TXFULL) &&
462+ (sent < skb->len)) {
463+ NBT_DBG_TRANSFER_NF("0x%.2x ", skb->data[sent]);
464+ hci_h4p_outb(info, UART_TX, skb->data[sent]);
465+ sent++;
466+ }
467+
468+ info->hdev->stat.byte_tx += sent;
469+ NBT_DBG_TRANSFER_NF("\n");
470+ if (skb->len == sent) {
471+ kfree_skb(skb);
472+ } else {
473+ skb_pull(skb, sent);
474+ skb_queue_head(&info->txq, skb);
475+ }
476+
477+ spin_lock_irqsave(&info->lock, flags);
478+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_THRI);
479+ spin_unlock_irqrestore(&info->lock, flags);
480+}
481+
482+static irqreturn_t hci_h4p_interrupt(int irq, void *data)
483+{
484+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
485+ u8 iir, msr;
486+ int ret;
487+ unsigned long flags;
488+
489+ ret = IRQ_NONE;
490+
491+ iir = hci_h4p_inb(info, UART_IIR);
492+ if (iir & UART_IIR_NO_INT) {
493+ dev_err(info->dev, "Interrupt but no reason irq 0x%.2x\n", iir);
494+ return IRQ_HANDLED;
495+ }
496+
497+ NBT_DBG("In interrupt handler iir 0x%.2x\n", iir);
498+
499+ iir &= UART_IIR_ID;
500+
501+ if (iir == UART_IIR_MSI) {
502+ msr = hci_h4p_inb(info, UART_MSR);
503+ ret = IRQ_HANDLED;
504+ }
505+ if (iir == UART_IIR_RLSI) {
506+ hci_h4p_inb(info, UART_RX);
507+ hci_h4p_inb(info, UART_LSR);
508+ ret = IRQ_HANDLED;
509+ }
510+
511+ if (iir == UART_IIR_RDI) {
512+ spin_lock_irqsave(&info->lock, flags);
513+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_RDI);
514+ spin_unlock_irqrestore(&info->lock, flags);
515+ tasklet_schedule(&info->rx_task);
516+ ret = IRQ_HANDLED;
517+ }
518+
519+ if (iir == UART_IIR_THRI) {
520+ spin_lock_irqsave(&info->lock, flags);
521+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_THRI);
522+ spin_unlock_irqrestore(&info->lock, flags);
523+ tasklet_schedule(&info->tx_task);
524+ ret = IRQ_HANDLED;
525+ }
526+
527+ return ret;
528+}
529+
530+static irqreturn_t hci_h4p_wakeup_interrupt(int irq, void *dev_inst)
531+{
532+ struct hci_h4p_info *info = dev_inst;
533+ int should_wakeup;
534+ struct hci_dev *hdev;
535+
536+ if (!info->hdev)
537+ return IRQ_HANDLED;
538+
539+ hdev = info->hdev;
540+
541+ if (!test_bit(HCI_RUNNING, &hdev->flags))
542+ return IRQ_HANDLED;
543+
544+ should_wakeup = gpio_get_value(info->host_wakeup_gpio);
545+ NBT_DBG_POWER("gpio interrupt %d\n", should_wakeup);
546+ if (should_wakeup) {
547+ hci_h4p_enable_rx(info);
548+ } else {
549+ hci_h4p_disable_rx(info);
550+ }
551+
552+ return IRQ_HANDLED;
553+}
554+
555+static int hci_h4p_reset(struct hci_h4p_info *info)
556+{
557+ int err;
558+
559+ hci_h4p_init_uart(info);
560+ hci_h4p_set_rts(info, 0);
561+
562+ gpio_set_value(info->reset_gpio, 0);
563+ msleep(100);
564+ gpio_set_value(info->bt_wakeup_gpio, 1);
565+ gpio_set_value(info->reset_gpio, 1);
566+ msleep(100);
567+
568+ err = hci_h4p_wait_for_cts(info, 1, 10);
569+ if (err < 0) {
570+ dev_err(info->dev, "No cts from bt chip\n");
571+ return err;
572+ }
573+
574+ hci_h4p_set_rts(info, 1);
575+
576+ return 0;
577+}
578+
579+/* hci callback functions */
580+static int hci_h4p_hci_flush(struct hci_dev *hdev)
581+{
582+ struct hci_h4p_info *info;
583+ info = hdev->driver_data;
584+
585+ skb_queue_purge(&info->txq);
586+
587+ return 0;
588+}
589+
590+static int hci_h4p_hci_open(struct hci_dev *hdev)
591+{
592+ struct hci_h4p_info *info;
593+ int err;
594+ struct sk_buff *neg_cmd_skb;
595+ struct sk_buff_head fw_queue;
596+
597+ info = hdev->driver_data;
598+
599+ if (test_bit(HCI_RUNNING, &hdev->flags))
600+ return 0;
601+
602+ skb_queue_head_init(&fw_queue);
603+ err = hci_h4p_read_fw(info, &fw_queue);
604+ if (err < 0) {
605+ dev_err(info->dev, "Cannot read firmware\n");
606+ return err;
607+ }
608+ neg_cmd_skb = skb_dequeue(&fw_queue);
609+ if (!neg_cmd_skb) {
610+ err = -EPROTO;
611+ goto err_clean;
612+ }
613+ info->alive_cmd_skb = skb_dequeue(&fw_queue);
614+ if (!info->alive_cmd_skb) {
615+ err = -EPROTO;
616+ goto err_clean;
617+ }
618+
619+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
620+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
621+
622+ tasklet_enable(&info->tx_task);
623+ tasklet_enable(&info->rx_task);
624+ info->rx_state = WAIT_FOR_PKT_TYPE;
625+ info->rx_count = 0;
626+ info->garbage_bytes = 0;
627+ info->rx_skb = NULL;
628+ info->pm_enabled = 0;
629+ init_completion(&info->fw_completion);
630+
631+ err = hci_h4p_reset(info);
632+ if (err < 0)
633+ goto err_clean;
634+
635+ err = hci_h4p_send_negotiation(info, neg_cmd_skb);
636+ neg_cmd_skb = NULL;
637+ if (err < 0)
638+ goto err_clean;
639+
640+ err = hci_h4p_send_fw(info, &fw_queue);
641+ if (err < 0) {
642+ dev_err(info->dev, "Sending firmware failed.\n");
643+ goto err_clean;
644+ }
645+
646+ kfree_skb(info->alive_cmd_skb);
647+ info->alive_cmd_skb = NULL;
648+ info->pm_enabled = 1;
649+ info->tx_pm_enabled = 1;
650+ info->rx_pm_enabled = 0;
651+ set_bit(HCI_RUNNING, &hdev->flags);
652+
653+ NBT_DBG("hci up and running\n");
654+ return 0;
655+
656+err_clean:
657+ hci_h4p_hci_flush(hdev);
658+ tasklet_disable(&info->tx_task);
659+ tasklet_disable(&info->rx_task);
660+ hci_h4p_reset_uart(info);
661+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
662+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
663+ gpio_set_value(info->reset_gpio, 0);
664+ gpio_set_value(info->bt_wakeup_gpio, 0);
665+ skb_queue_purge(&fw_queue);
666+ kfree_skb(neg_cmd_skb);
667+ neg_cmd_skb = NULL;
668+ kfree_skb(info->alive_cmd_skb);
669+ info->alive_cmd_skb = NULL;
670+ kfree_skb(info->rx_skb);
671+
672+ return err;
673+}
674+
675+static int hci_h4p_hci_close(struct hci_dev *hdev)
676+{
677+ struct hci_h4p_info *info = hdev->driver_data;
678+
679+ if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags))
680+ return 0;
681+
682+ hci_h4p_hci_flush(hdev);
683+ del_timer_sync(&info->tx_pm_timer);
684+ del_timer_sync(&info->rx_pm_timer);
685+ tasklet_disable(&info->tx_task);
686+ tasklet_disable(&info->rx_task);
687+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
688+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
689+ hci_h4p_reset_uart(info);
690+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
691+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
692+ gpio_set_value(info->reset_gpio, 0);
693+ gpio_set_value(info->bt_wakeup_gpio, 0);
694+ kfree_skb(info->rx_skb);
695+
696+ return 0;
697+}
698+
699+static void hci_h4p_hci_destruct(struct hci_dev *hdev)
700+{
701+}
702+
703+static int hci_h4p_hci_send_frame(struct sk_buff *skb)
704+{
705+ struct hci_h4p_info *info;
706+ struct hci_dev *hdev = (struct hci_dev *)skb->dev;
707+ int err = 0;
708+
709+ if (!hdev) {
710+ printk(KERN_WARNING "hci_h4p: Frame for unknown device\n");
711+ return -ENODEV;
712+ }
713+
714+ NBT_DBG("dev %p, skb %p\n", hdev, skb);
715+
716+ info = hdev->driver_data;
717+
718+ if (!test_bit(HCI_RUNNING, &hdev->flags)) {
719+ dev_warn(info->dev, "Frame for non-running device\n");
720+ return -EIO;
721+ }
722+
723+ switch (bt_cb(skb)->pkt_type) {
724+ case HCI_COMMAND_PKT:
725+ hdev->stat.cmd_tx++;
726+ break;
727+ case HCI_ACLDATA_PKT:
728+ hdev->stat.acl_tx++;
729+ break;
730+ case HCI_SCODATA_PKT:
731+ hdev->stat.sco_tx++;
732+ break;
733+ }
734+
735+ /* Push frame type to skb */
736+ *skb_push(skb, 1) = (bt_cb(skb)->pkt_type);
737+ /* We should allways send word aligned data to h4+ devices */
738+ if (skb->len % 2) {
739+ err = skb_pad(skb, 1);
740+ }
741+ if (err)
742+ return err;
743+
744+ hci_h4p_enable_tx(info);
745+ skb_queue_tail(&info->txq, skb);
746+ tasklet_schedule(&info->tx_task);
747+
748+ return 0;
749+}
750+
751+static int hci_h4p_hci_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
752+{
753+ return -ENOIOCTLCMD;
754+}
755+
756+static int hci_h4p_register_hdev(struct hci_h4p_info *info)
757+{
758+ struct hci_dev *hdev;
759+
760+ /* Initialize and register HCI device */
761+
762+ hdev = hci_alloc_dev();
763+ if (!hdev) {
764+ dev_err(info->dev, "Can't allocate memory for device\n");
765+ return -ENOMEM;
766+ }
767+ info->hdev = hdev;
768+
769+ hdev->type = HCI_UART;
770+ hdev->driver_data = info;
771+
772+ hdev->open = hci_h4p_hci_open;
773+ hdev->close = hci_h4p_hci_close;
774+ hdev->flush = hci_h4p_hci_flush;
775+ hdev->send = hci_h4p_hci_send_frame;
776+ hdev->destruct = hci_h4p_hci_destruct;
777+ hdev->ioctl = hci_h4p_hci_ioctl;
778+
779+ hdev->owner = THIS_MODULE;
780+
781+ if (hci_register_dev(hdev) < 0) {
782+ dev_err(info->dev, "hci_h4p: Can't register HCI device %s.\n", hdev->name);
783+ return -ENODEV;
784+ }
785+
786+ return 0;
787+}
788+
789+static int hci_h4p_probe(struct platform_device *pdev)
790+{
791+ struct omap_bluetooth_config *bt_config;
792+ struct hci_h4p_info *info;
793+ int irq, err;
794+
795+ dev_info(&pdev->dev, "Registering HCI H4P device\n");
796+ info = kzalloc(sizeof(struct hci_h4p_info), GFP_KERNEL);
797+ if (!info)
798+ return -ENOMEM;
799+
800+ info->dev = &pdev->dev;
801+ info->pm_enabled = 0;
802+ info->tx_pm_enabled = 0;
803+ info->rx_pm_enabled = 0;
804+ info->garbage_bytes = 0;
805+ info->tx_clocks_en = 0;
806+ info->rx_clocks_en = 0;
807+ tasklet_init(&info->tx_task, hci_h4p_tx_tasklet, (unsigned long)info);
808+ tasklet_init(&info->rx_task, hci_h4p_rx_tasklet, (unsigned long)info);
809+ /* hci_h4p_hci_open assumes that tasklet is disabled in startup */
810+ tasklet_disable(&info->tx_task);
811+ tasklet_disable(&info->rx_task);
812+ spin_lock_init(&info->lock);
813+ spin_lock_init(&info->clocks_lock);
814+ skb_queue_head_init(&info->txq);
815+ init_timer(&info->tx_pm_timer);
816+ info->tx_pm_timer.function = hci_h4p_tx_pm_timer;
817+ info->tx_pm_timer.data = (unsigned long)info;
818+ init_timer(&info->rx_pm_timer);
819+ info->rx_pm_timer.function = hci_h4p_rx_pm_timer;
820+ info->rx_pm_timer.data = (unsigned long)info;
821+
822+ if (pdev->dev.platform_data == NULL) {
823+ dev_err(&pdev->dev, "Could not get Bluetooth config data\n");
824+ return -ENODATA;
825+ }
826+
827+ bt_config = pdev->dev.platform_data;
828+ info->chip_type = bt_config->chip_type;
829+ info->bt_wakeup_gpio = bt_config->bt_wakeup_gpio;
830+ info->host_wakeup_gpio = bt_config->host_wakeup_gpio;
831+ info->reset_gpio = bt_config->reset_gpio;
832+ info->bt_sysclk = bt_config->bt_sysclk;
833+
834+ NBT_DBG("RESET gpio: %d\n", info->reset_gpio);
835+ NBT_DBG("BTWU gpio: %d\n", info->bt_wakeup_gpio);
836+ NBT_DBG("HOSTWU gpio: %d\n", info->host_wakeup_gpio);
837+ NBT_DBG("Uart: %d\n", bt_config->bt_uart);
838+ NBT_DBG("sysclk: %d\n", info->bt_sysclk);
839+
840+ err = gpio_request(info->reset_gpio, "BT reset");
841+ if (err < 0) {
842+ dev_err(&pdev->dev, "Cannot get GPIO line %d\n",
843+ info->reset_gpio);
844+ kfree(info);
845+ goto cleanup;
846+ }
847+
848+ err = gpio_request(info->bt_wakeup_gpio, "BT wakeup");
849+ if (err < 0)
850+ {
851+ dev_err(info->dev, "Cannot get GPIO line 0x%d",
852+ info->bt_wakeup_gpio);
853+ gpio_free(info->reset_gpio);
854+ kfree(info);
855+ goto cleanup;
856+ }
857+
858+ err = gpio_request(info->host_wakeup_gpio, "BT host wakeup");
859+ if (err < 0)
860+ {
861+ dev_err(info->dev, "Cannot get GPIO line %d",
862+ info->host_wakeup_gpio);
863+ gpio_free(info->reset_gpio);
864+ gpio_free(info->bt_wakeup_gpio);
865+ kfree(info);
866+ goto cleanup;
867+ }
868+
869+ gpio_direction_output(info->reset_gpio, 0);
870+ gpio_direction_output(info->bt_wakeup_gpio, 0);
871+ gpio_direction_input(info->host_wakeup_gpio);
872+
873+ switch (bt_config->bt_uart) {
874+ case 1:
875+ if (cpu_is_omap16xx()) {
876+ irq = INT_UART1;
877+ info->uart_fclk = clk_get(NULL, "uart1_ck");
878+ } else if (cpu_is_omap24xx()) {
879+ irq = INT_24XX_UART1_IRQ;
880+ info->uart_iclk = clk_get(NULL, "uart1_ick");
881+ info->uart_fclk = clk_get(NULL, "uart1_fck");
882+ }
883+ /* FIXME: Use platform_get_resource for the port */
884+ info->uart_base = ioremap(OMAP_UART1_BASE, 0x16);
885+ if (!info->uart_base)
886+ goto cleanup;
887+ break;
888+ case 2:
889+ if (cpu_is_omap16xx()) {
890+ irq = INT_UART2;
891+ info->uart_fclk = clk_get(NULL, "uart2_ck");
892+ } else {
893+ irq = INT_24XX_UART2_IRQ;
894+ info->uart_iclk = clk_get(NULL, "uart2_ick");
895+ info->uart_fclk = clk_get(NULL, "uart2_fck");
896+ }
897+ /* FIXME: Use platform_get_resource for the port */
898+ info->uart_base = ioremap(OMAP_UART2_BASE, 0x16);
899+ if (!info->uart_base)
900+ goto cleanup;
901+ break;
902+ case 3:
903+ if (cpu_is_omap16xx()) {
904+ irq = INT_UART3;
905+ info->uart_fclk = clk_get(NULL, "uart3_ck");
906+ } else {
907+ irq = INT_24XX_UART3_IRQ;
908+ info->uart_iclk = clk_get(NULL, "uart3_ick");
909+ info->uart_fclk = clk_get(NULL, "uart3_fck");
910+ }
911+ /* FIXME: Use platform_get_resource for the port */
912+ info->uart_base = ioremap(OMAP_UART3_BASE, 0x16);
913+ if (!info->uart_base)
914+ goto cleanup;
915+ break;
916+ default:
917+ dev_err(info->dev, "No uart defined\n");
918+ goto cleanup;
919+ }
920+
921+ info->irq = irq;
922+ err = request_irq(irq, hci_h4p_interrupt, 0, "hci_h4p", (void *)info);
923+ if (err < 0) {
924+ dev_err(info->dev, "hci_h4p: unable to get IRQ %d\n", irq);
925+ goto cleanup;
926+ }
927+
928+ err = request_irq(gpio_to_irq(info->host_wakeup_gpio),
929+ hci_h4p_wakeup_interrupt,
930+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
931+ "hci_h4p_wkup", (void *)info);
932+ if (err < 0) {
933+ dev_err(info->dev, "hci_h4p: unable to get wakeup IRQ %d\n",
934+ gpio_to_irq(info->host_wakeup_gpio));
935+ free_irq(irq, (void *)info);
936+ goto cleanup;
937+ }
938+
939+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
940+ hci_h4p_set_auto_ctsrts(info, 0, UART_EFR_CTS | UART_EFR_RTS);
941+ err = hci_h4p_init_uart(info);
942+ if (err < 0)
943+ goto cleanup_irq;
944+ err = hci_h4p_reset(info);
945+ if (err < 0)
946+ goto cleanup_irq;
947+ err = hci_h4p_wait_for_cts(info, 1, 10);
948+ if (err < 0)
949+ goto cleanup_irq;
950+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
951+
952+ platform_set_drvdata(pdev, info);
953+ err = hci_h4p_sysfs_create_files(info->dev);
954+ if (err < 0)
955+ goto cleanup_irq;
956+
957+ if (hci_h4p_register_hdev(info) < 0) {
958+ dev_err(info->dev, "failed to register hci_h4p hci device\n");
959+ goto cleanup_irq;
960+ }
961+ gpio_set_value(info->reset_gpio, 0);
962+
963+ return 0;
964+
965+cleanup_irq:
966+ free_irq(irq, (void *)info);
967+ free_irq(gpio_to_irq(info->host_wakeup_gpio), (void *)info);
968+cleanup:
969+ gpio_set_value(info->reset_gpio, 0);
970+ gpio_free(info->reset_gpio);
971+ gpio_free(info->bt_wakeup_gpio);
972+ gpio_free(info->host_wakeup_gpio);
973+ kfree(info);
974+
975+ return err;
976+
977+}
978+
979+static int hci_h4p_remove(struct platform_device *dev)
980+{
981+ struct hci_h4p_info *info;
982+
983+ info = platform_get_drvdata(dev);
984+
985+ hci_h4p_hci_close(info->hdev);
986+ free_irq(gpio_to_irq(info->host_wakeup_gpio), (void *) info);
987+ hci_free_dev(info->hdev);
988+ gpio_free(info->reset_gpio);
989+ gpio_free(info->bt_wakeup_gpio);
990+ gpio_free(info->host_wakeup_gpio);
991+ free_irq(info->irq, (void *) info);
992+ kfree(info);
993+
994+ return 0;
995+}
996+
997+static struct platform_driver hci_h4p_driver = {
998+ .probe = hci_h4p_probe,
999+ .remove = hci_h4p_remove,
1000+ .driver = {
1001+ .name = "hci_h4p",
1002+ },
1003+};
1004+
1005+static int __init hci_h4p_init(void)
1006+{
1007+ int err = 0;
1008+
1009+ /* Register the driver with LDM */
1010+ err = platform_driver_register(&hci_h4p_driver);
1011+ if (err < 0)
1012+ printk(KERN_WARNING "failed to register hci_h4p driver\n");
1013+
1014+ return err;
1015+}
1016+
1017+static void __exit hci_h4p_exit(void)
1018+{
1019+ platform_driver_unregister(&hci_h4p_driver);
1020+}
1021+
1022+module_init(hci_h4p_init);
1023+module_exit(hci_h4p_exit);
1024+
1025+MODULE_DESCRIPTION("h4 driver with nokia extensions");
1026+MODULE_LICENSE("GPL");
1027+MODULE_AUTHOR("Ville Tervo");
1028Index: linux-2.6.35/drivers/bluetooth/hci_h4p/fw.c
1029===================================================================
1030--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1031@@ -0,0 +1,155 @@
1032+/*
1033+ * This file is part of hci_h4p bluetooth driver
1034+ *
1035+ * Copyright (C) 2005, 2006 Nokia Corporation.
1036+ *
1037+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1038+ *
1039+ * This program is free software; you can redistribute it and/or
1040+ * modify it under the terms of the GNU General Public License
1041+ * version 2 as published by the Free Software Foundation.
1042+ *
1043+ * This program is distributed in the hope that it will be useful, but
1044+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1045+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1046+ * General Public License for more details.
1047+ *
1048+ * You should have received a copy of the GNU General Public License
1049+ * along with this program; if not, write to the Free Software
1050+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1051+ * 02110-1301 USA
1052+ *
1053+ */
1054+
1055+#include <linux/skbuff.h>
1056+#include <linux/firmware.h>
1057+#include <linux/clk.h>
1058+
1059+#include <net/bluetooth/bluetooth.h>
1060+
1061+#include "hci_h4p.h"
1062+
1063+#define BT_CHIP_TI 2
1064+#define BT_CHIP_CSR 1
1065+
1066+static int fw_pos;
1067+
1068+/* Firmware handling */
1069+static int hci_h4p_open_firmware(struct hci_h4p_info *info,
1070+ const struct firmware **fw_entry)
1071+{
1072+ int err;
1073+
1074+ fw_pos = 0;
1075+ NBT_DBG_FW("Opening %d firmware\n", info->chip_type);
1076+ switch (info->chip_type) {
1077+ case BT_CHIP_TI:
1078+ err = request_firmware(fw_entry, "brf6150fw.bin", info->dev);
1079+ break;
1080+ case BT_CHIP_CSR:
1081+ err = request_firmware(fw_entry, "bc4fw.bin", info->dev);
1082+ break;
1083+ default:
1084+ dev_err(info->dev, "Invalid chip type\n");
1085+ *fw_entry = NULL;
1086+ err = -EINVAL;
1087+ }
1088+
1089+ return err;
1090+}
1091+
1092+static void hci_h4p_close_firmware(const struct firmware *fw_entry)
1093+{
1094+ release_firmware(fw_entry);
1095+}
1096+
1097+/* Read fw. Return length of the command. If no more commands in
1098+ * fw 0 is returned. In error case return value is negative.
1099+ */
1100+static int hci_h4p_read_fw_cmd(struct hci_h4p_info *info, struct sk_buff **skb,
1101+ const struct firmware *fw_entry, int how)
1102+{
1103+ unsigned int cmd_len;
1104+
1105+ if (fw_pos >= fw_entry->size) {
1106+ return 0;
1107+ }
1108+
1109+ cmd_len = fw_entry->data[fw_pos++];
1110+ if (!cmd_len)
1111+ return 0;
1112+
1113+ if (fw_pos + cmd_len > fw_entry->size) {
1114+ dev_err(info->dev, "Corrupted firmware image\n");
1115+ return -EMSGSIZE;
1116+ }
1117+
1118+ *skb = bt_skb_alloc(cmd_len, how);
1119+ if (!*skb) {
1120+ dev_err(info->dev, "Cannot reserve memory for buffer\n");
1121+ return -ENOMEM;
1122+ }
1123+ memcpy(skb_put(*skb, cmd_len), &fw_entry->data[fw_pos], cmd_len);
1124+
1125+ fw_pos += cmd_len;
1126+
1127+ return (*skb)->len;
1128+}
1129+
1130+int hci_h4p_read_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
1131+{
1132+ const struct firmware *fw_entry = NULL;
1133+ struct sk_buff *skb = NULL;
1134+ int err;
1135+
1136+ err = hci_h4p_open_firmware(info, &fw_entry);
1137+ if (err < 0 || !fw_entry)
1138+ goto err_clean;
1139+
1140+ while ((err = hci_h4p_read_fw_cmd(info, &skb, fw_entry, GFP_KERNEL))) {
1141+ if (err < 0 || !skb)
1142+ goto err_clean;
1143+
1144+ skb_queue_tail(fw_queue, skb);
1145+ }
1146+
1147+err_clean:
1148+ hci_h4p_close_firmware(fw_entry);
1149+ return err;
1150+}
1151+
1152+int hci_h4p_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
1153+{
1154+ int err;
1155+
1156+ switch(info->chip_type) {
1157+ case BT_CHIP_CSR:
1158+ err = hci_h4p_bc4_send_fw(info, fw_queue);
1159+ break;
1160+ case BT_CHIP_TI:
1161+ err = hci_h4p_brf6150_send_fw(info, fw_queue);
1162+ break;
1163+ default:
1164+ dev_err(info->dev, "Don't know how to send firmware\n");
1165+ err = -EINVAL;
1166+ }
1167+
1168+ return err;
1169+}
1170+
1171+void hci_h4p_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb)
1172+{
1173+ switch (info->chip_type) {
1174+ case BT_CHIP_CSR:
1175+ hci_h4p_bc4_parse_fw_event(info, skb);
1176+ break;
1177+ case BT_CHIP_TI:
1178+ hci_h4p_brf6150_parse_fw_event(info, skb);
1179+ break;
1180+ default:
1181+ dev_err(info->dev, "Don't know how to parse fw event\n");
1182+ info->fw_error = -EINVAL;
1183+ }
1184+
1185+ return;
1186+}
1187Index: linux-2.6.35/drivers/bluetooth/hci_h4p/fw-csr.c
1188===================================================================
1189--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1190@@ -0,0 +1,149 @@
1191+/*
1192+ * This file is part of hci_h4p bluetooth driver
1193+ *
1194+ * Copyright (C) 2005, 2006 Nokia Corporation.
1195+ *
1196+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1197+ *
1198+ * This program is free software; you can redistribute it and/or
1199+ * modify it under the terms of the GNU General Public License
1200+ * version 2 as published by the Free Software Foundation.
1201+ *
1202+ * This program is distributed in the hope that it will be useful, but
1203+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1204+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1205+ * General Public License for more details.
1206+ *
1207+ * You should have received a copy of the GNU General Public License
1208+ * along with this program; if not, write to the Free Software
1209+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1210+ * 02110-1301 USA
1211+ *
1212+ */
1213+
1214+#include <linux/skbuff.h>
1215+#include <linux/delay.h>
1216+#include <linux/serial_reg.h>
1217+
1218+#include "hci_h4p.h"
1219+
1220+void hci_h4p_bc4_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb)
1221+{
1222+ /* Check if this is fw packet */
1223+ if (skb->data[0] != 0xff) {
1224+ hci_recv_frame(skb);
1225+ return;
1226+ }
1227+
1228+ if (skb->data[11] || skb->data[12]) {
1229+ dev_err(info->dev, "Firmware sending command failed\n");
1230+ info->fw_error = -EPROTO;
1231+ }
1232+
1233+ kfree_skb(skb);
1234+ complete(&info->fw_completion);
1235+}
1236+
1237+int hci_h4p_bc4_send_fw(struct hci_h4p_info *info,
1238+ struct sk_buff_head *fw_queue)
1239+{
1240+ struct sk_buff *skb;
1241+ unsigned int offset;
1242+ int retries, count, i;
1243+
1244+ info->fw_error = 0;
1245+
1246+ NBT_DBG_FW("Sending firmware\n");
1247+ skb = skb_dequeue(fw_queue);
1248+
1249+ if (!skb)
1250+ return -ENOMSG;
1251+
1252+ info->bdaddr[0] = 0x00;
1253+ info->bdaddr[1] = 0x1D;
1254+ info->bdaddr[2] = 0x6E;
1255+ info->bdaddr[3] = 0xD4;
1256+ info->bdaddr[4] = 0xF0;
1257+ info->bdaddr[5] = 0x37;
1258+
1259+ /* Check if this is bd_address packet */
1260+ if (skb->data[15] == 0x01 && skb->data[16] == 0x00) {
1261+ dev_info(info->dev, "bd_address packet found\n");
1262+ offset = 21;
1263+ skb->data[offset + 1] = 0x00;
1264+ skb->data[offset + 5] = 0x00;
1265+ skb->data[offset + 7] = info->bdaddr[0];
1266+ skb->data[offset + 6] = info->bdaddr[1];
1267+ skb->data[offset + 4] = info->bdaddr[2];
1268+ skb->data[offset + 0] = info->bdaddr[3];
1269+ skb->data[offset + 3] = info->bdaddr[4];
1270+ skb->data[offset + 2] = info->bdaddr[5];
1271+ }
1272+
1273+ for (i = 0; i < 6; i++) {
1274+ if (info->bdaddr[i] != 0x00)
1275+ break;
1276+ }
1277+
1278+ /* if (i > 5) {
1279+ dev_info(info->dev, "Valid bluetooth address not found.\n");
1280+ kfree_skb(skb);
1281+ return -ENODEV;
1282+ } */
1283+
1284+ for (count = 1; ; count++) {
1285+ NBT_DBG_FW("Sending firmware command %d\n", count);
1286+ init_completion(&info->fw_completion);
1287+ skb_queue_tail(&info->txq, skb);
1288+ tasklet_schedule(&info->tx_task);
1289+
1290+ skb = skb_dequeue(fw_queue);
1291+ if (!skb)
1292+ break;
1293+
1294+ if (!wait_for_completion_timeout(&info->fw_completion,
1295+ msecs_to_jiffies(1000))) {
1296+ dev_err(info->dev, "No reply to fw command\n");
1297+ return -ETIMEDOUT;
1298+ }
1299+
1300+ if (info->fw_error) {
1301+ dev_err(info->dev, "FW error\n");
1302+ return -EPROTO;
1303+ }
1304+ };
1305+
1306+ /* Wait for chip warm reset */
1307+ retries = 100;
1308+ while ((!skb_queue_empty(&info->txq) ||
1309+ !(hci_h4p_inb(info, UART_LSR) & UART_LSR_TEMT)) &&
1310+ retries--) {
1311+ msleep(10);
1312+ }
1313+ if (!retries) {
1314+ dev_err(info->dev, "Transmitter not empty\n");
1315+ return -ETIMEDOUT;
1316+ }
1317+
1318+ hci_h4p_change_speed(info, BC4_MAX_BAUD_RATE);
1319+
1320+ if (hci_h4p_wait_for_cts(info, 1, 100)) {
1321+ dev_err(info->dev, "cts didn't go down after final speed change\n");
1322+ return -ETIMEDOUT;
1323+ }
1324+
1325+ retries = 100;
1326+ do {
1327+ init_completion(&info->init_completion);
1328+ hci_h4p_send_alive_packet(info);
1329+ retries--;
1330+ } while (!wait_for_completion_timeout(&info->init_completion, 100) &&
1331+ retries > 0);
1332+
1333+ if (!retries) {
1334+ dev_err(info->dev, "No alive reply after speed change\n");
1335+ return -ETIMEDOUT;
1336+ }
1337+
1338+ return 0;
1339+}
1340Index: linux-2.6.35/drivers/bluetooth/hci_h4p/fw-ti.c
1341===================================================================
1342--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1343@@ -0,0 +1,90 @@
1344+/*
1345+ * This file is part of hci_h4p bluetooth driver
1346+ *
1347+ * Copyright (C) 2005, 2006 Nokia Corporation.
1348+ *
1349+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1350+ *
1351+ * This program is free software; you can redistribute it and/or
1352+ * modify it under the terms of the GNU General Public License
1353+ * version 2 as published by the Free Software Foundation.
1354+ *
1355+ * This program is distributed in the hope that it will be useful, but
1356+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1357+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1358+ * General Public License for more details.
1359+ *
1360+ * You should have received a copy of the GNU General Public License
1361+ * along with this program; if not, write to the Free Software
1362+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1363+ * 02110-1301 USA
1364+ *
1365+ */
1366+
1367+#include <linux/skbuff.h>
1368+
1369+#include "hci_h4p.h"
1370+
1371+void hci_h4p_brf6150_parse_fw_event(struct hci_h4p_info *info,
1372+ struct sk_buff *skb)
1373+{
1374+ struct hci_fw_event *ev;
1375+ int err = 0;
1376+
1377+ if (bt_cb(skb)->pkt_type != H4_EVT_PKT) {
1378+ dev_err(info->dev, "Got non event fw packet.\n");
1379+ err = -EPROTO;
1380+ goto ret;
1381+ }
1382+
1383+ ev = (struct hci_fw_event *)skb->data;
1384+ if (ev->hev.evt != HCI_EV_CMD_COMPLETE) {
1385+ dev_err(info->dev, "Got non cmd complete fw event\n");
1386+ err = -EPROTO;
1387+ goto ret;
1388+ }
1389+
1390+ if (ev->status != 0) {
1391+ dev_err(info->dev, "Got error status from fw command\n");
1392+ err = -EPROTO;
1393+ goto ret;
1394+ }
1395+
1396+ret:
1397+ info->fw_error = err;
1398+ complete(&info->fw_completion);
1399+}
1400+
1401+int hci_h4p_brf6150_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
1402+{
1403+ struct sk_buff *skb;
1404+ int err = 0;
1405+
1406+ info->fw_error = 0;
1407+
1408+ while ((skb = skb_dequeue(fw_queue)) != NULL) {
1409+ /* We should allways send word aligned data to h4+ devices */
1410+ if (skb->len % 2) {
1411+ err = skb_pad(skb, 1);
1412+ }
1413+ if (err)
1414+ return err;
1415+
1416+ init_completion(&info->fw_completion);
1417+ skb_queue_tail(&info->txq, skb);
1418+ tasklet_schedule(&info->tx_task);
1419+
1420+ if (!wait_for_completion_timeout(&info->fw_completion, HZ)) {
1421+ dev_err(info->dev, "Timeout while sending brf6150 fw\n");
1422+ return -ETIMEDOUT;
1423+ }
1424+
1425+ if (info->fw_error) {
1426+ dev_err(info->dev, "There was fw_error while sending bfr6150 fw\n");
1427+ return -EPROTO;
1428+ }
1429+ }
1430+ NBT_DBG_FW("Firmware sent\n");
1431+
1432+ return 0;
1433+}
1434Index: linux-2.6.35/drivers/bluetooth/hci_h4p/hci_h4p.h
1435===================================================================
1436--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1437@@ -0,0 +1,183 @@
1438+/*
1439+ * This file is part of hci_h4p bluetooth driver
1440+ *
1441+ * Copyright (C) 2005, 2006 Nokia Corporation.
1442+ *
1443+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1444+ *
1445+ * This program is free software; you can redistribute it and/or
1446+ * modify it under the terms of the GNU General Public License
1447+ * version 2 as published by the Free Software Foundation.
1448+ *
1449+ * This program is distributed in the hope that it will be useful, but
1450+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1451+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1452+ * General Public License for more details.
1453+ *
1454+ * You should have received a copy of the GNU General Public License
1455+ * along with this program; if not, write to the Free Software
1456+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1457+ * 02110-1301 USA
1458+ *
1459+ */
1460+
1461+#include <mach/board.h>
1462+
1463+#include <net/bluetooth/bluetooth.h>
1464+#include <net/bluetooth/hci_core.h>
1465+#include <net/bluetooth/hci.h>
1466+
1467+#ifndef __DRIVERS_BLUETOOTH_HCI_H4P_H
1468+#define __DRIVERS_BLUETOOTH_HCI_H4P_H
1469+
1470+#define UART_SYSC_OMAP_RESET 0x03
1471+#define UART_SYSS_RESETDONE 0x01
1472+#define UART_OMAP_SCR_EMPTY_THR 0x08
1473+#define UART_OMAP_SCR_WAKEUP 0x10
1474+#define UART_OMAP_SSR_WAKEUP 0x02
1475+#define UART_OMAP_SSR_TXFULL 0x01
1476+
1477+#if 0
1478+#define NBT_DBG(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
1479+#else
1480+#define NBT_DBG(...)
1481+#endif
1482+
1483+#if 0
1484+#define NBT_DBG_FW(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
1485+#else
1486+#define NBT_DBG_FW(...)
1487+#endif
1488+
1489+#if 0
1490+#define NBT_DBG_POWER(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
1491+#else
1492+#define NBT_DBG_POWER(...)
1493+#endif
1494+
1495+#if 0
1496+#define NBT_DBG_TRANSFER(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
1497+#else
1498+#define NBT_DBG_TRANSFER(...)
1499+#endif
1500+
1501+#if 0
1502+#define NBT_DBG_TRANSFER_NF(fmt, arg...) printk(fmt "" , ## arg)
1503+#else
1504+#define NBT_DBG_TRANSFER_NF(...)
1505+#endif
1506+
1507+#if 0
1508+#define NBT_DBG_DMA(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
1509+#else
1510+#define NBT_DBG_DMA(...)
1511+#endif
1512+
1513+struct hci_h4p_info {
1514+ struct hci_dev *hdev;
1515+ spinlock_t lock;
1516+
1517+ void __iomem *uart_base;
1518+ unsigned long uart_phys_base;
1519+ int irq;
1520+ struct device *dev;
1521+ u8 bdaddr[6];
1522+ u8 chip_type;
1523+ u8 bt_wakeup_gpio;
1524+ u8 host_wakeup_gpio;
1525+ u8 reset_gpio;
1526+ u8 bt_sysclk;
1527+
1528+
1529+ struct sk_buff_head fw_queue;
1530+ struct sk_buff *alive_cmd_skb;
1531+ struct completion init_completion;
1532+ struct completion fw_completion;
1533+ int fw_error;
1534+ int init_error;
1535+
1536+ struct sk_buff_head txq;
1537+ struct tasklet_struct tx_task;
1538+
1539+ struct sk_buff *rx_skb;
1540+ long rx_count;
1541+ unsigned long rx_state;
1542+ unsigned long garbage_bytes;
1543+ struct tasklet_struct rx_task;
1544+
1545+ int pm_enabled;
1546+ int tx_pm_enabled;
1547+ int rx_pm_enabled;
1548+ struct timer_list tx_pm_timer;
1549+ struct timer_list rx_pm_timer;
1550+
1551+ int tx_clocks_en;
1552+ int rx_clocks_en;
1553+ spinlock_t clocks_lock;
1554+ struct clk *uart_iclk;
1555+ struct clk *uart_fclk;
1556+};
1557+
1558+#define MAX_BAUD_RATE 921600
1559+#define BC4_MAX_BAUD_RATE 3692300
1560+#define UART_CLOCK 48000000
1561+#define BT_INIT_DIVIDER 320
1562+#define BT_BAUDRATE_DIVIDER 384000000
1563+#define BT_SYSCLK_DIV 1000
1564+#define INIT_SPEED 120000
1565+
1566+#define H4_TYPE_SIZE 1
1567+
1568+/* H4+ packet types */
1569+#define H4_CMD_PKT 0x01
1570+#define H4_ACL_PKT 0x02
1571+#define H4_SCO_PKT 0x03
1572+#define H4_EVT_PKT 0x04
1573+#define H4_NEG_PKT 0x06
1574+#define H4_ALIVE_PKT 0x07
1575+
1576+/* TX states */
1577+#define WAIT_FOR_PKT_TYPE 1
1578+#define WAIT_FOR_HEADER 2
1579+#define WAIT_FOR_DATA 3
1580+
1581+struct hci_fw_event {
1582+ struct hci_event_hdr hev;
1583+ struct hci_ev_cmd_complete cmd;
1584+ u8 status;
1585+} __attribute__ ((packed));
1586+
1587+struct hci_bc4_set_bdaddr {
1588+ u8 type;
1589+ struct hci_command_hdr cmd_hdr;
1590+} __attribute__ ((packed));
1591+
1592+int hci_h4p_send_alive_packet(struct hci_h4p_info *info);
1593+
1594+void hci_h4p_bc4_parse_fw_event(struct hci_h4p_info *info,
1595+ struct sk_buff *skb);
1596+int hci_h4p_bc4_send_fw(struct hci_h4p_info *info,
1597+ struct sk_buff_head *fw_queue);
1598+
1599+void hci_h4p_brf6150_parse_fw_event(struct hci_h4p_info *info,
1600+ struct sk_buff *skb);
1601+int hci_h4p_brf6150_send_fw(struct hci_h4p_info *info,
1602+ struct sk_buff_head *fw_queue);
1603+
1604+int hci_h4p_read_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue);
1605+int hci_h4p_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue);
1606+void hci_h4p_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb);
1607+
1608+int hci_h4p_sysfs_create_files(struct device *dev);
1609+
1610+void hci_h4p_outb(struct hci_h4p_info *info, unsigned int offset, u8 val);
1611+u8 hci_h4p_inb(struct hci_h4p_info *info, unsigned int offset);
1612+void hci_h4p_set_rts(struct hci_h4p_info *info, int active);
1613+int hci_h4p_wait_for_cts(struct hci_h4p_info *info, int active, int timeout_ms);
1614+void __hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which);
1615+void hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which);
1616+void hci_h4p_change_speed(struct hci_h4p_info *info, unsigned long speed);
1617+int hci_h4p_reset_uart(struct hci_h4p_info *info);
1618+int hci_h4p_init_uart(struct hci_h4p_info *info);
1619+
1620+#endif /* __DRIVERS_BLUETOOTH_HCI_H4P_H */
1621Index: linux-2.6.35/drivers/bluetooth/hci_h4p/Makefile
1622===================================================================
1623--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1624@@ -0,0 +1,7 @@
1625+#
1626+# Makefile for the Linux Bluetooth HCI device drivers.
1627+#
1628+
1629+obj-$(CONFIG_BT_HCIH4P) += hci_h4p.o
1630+
1631+hci_h4p-objs := core.o fw.o uart.o sysfs.o fw-ti.o fw-csr.o
1632Index: linux-2.6.35/drivers/bluetooth/hci_h4p/sysfs.c
1633===================================================================
1634--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1635@@ -0,0 +1,84 @@
1636+/*
1637+ * This file is part of hci_h4p bluetooth driver
1638+ *
1639+ * Copyright (C) 2005, 2006 Nokia Corporation.
1640+ *
1641+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1642+ *
1643+ * This program is free software; you can redistribute it and/or
1644+ * modify it under the terms of the GNU General Public License
1645+ * version 2 as published by the Free Software Foundation.
1646+ *
1647+ * This program is distributed in the hope that it will be useful, but
1648+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1649+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1650+ * General Public License for more details.
1651+ *
1652+ * You should have received a copy of the GNU General Public License
1653+ * along with this program; if not, write to the Free Software
1654+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1655+ * 02110-1301 USA
1656+ *
1657+ */
1658+
1659+#include <linux/kernel.h>
1660+#include <linux/init.h>
1661+#include <linux/device.h>
1662+#include <linux/platform_device.h>
1663+
1664+#include "hci_h4p.h"
1665+
1666+#ifdef CONFIG_SYSFS
1667+
1668+static ssize_t hci_h4p_store_bdaddr(struct device *dev, struct device_attribute *attr,
1669+ const char *buf, size_t count)
1670+{
1671+ struct hci_h4p_info *info = (struct hci_h4p_info*)dev_get_drvdata(dev);
1672+ unsigned int bdaddr[6];
1673+ int ret, i;
1674+
1675+ dev_info(info->dev, "HCI_H4P_STORE_BDADDR called\n");
1676+
1677+ ret = sscanf(buf, "%2x:%2x:%2x:%2x:%2x:%2x\n",
1678+ &bdaddr[0], &bdaddr[1], &bdaddr[2],
1679+ &bdaddr[3], &bdaddr[4], &bdaddr[5]);
1680+
1681+ if (ret != 6) {
1682+ dev_info(info->dev, "bdaddr isn't found\n");
1683+ return -EINVAL;
1684+ }
1685+
1686+ //for (i = 0; i < 6; i++)
1687+ //info->bdaddr[i] = bdaddr[i] & 0xff;
1688+
1689+ info->bdaddr[0] = 0x00;
1690+ info->bdaddr[1] = 0x1D;
1691+ info->bdaddr[2] = 0x6E;
1692+ info->bdaddr[3] = 0xD4;
1693+ info->bdaddr[4] = 0xF0;
1694+ info->bdaddr[5] = 0x37;
1695+
1696+ return count;
1697+}
1698+
1699+static ssize_t hci_h4p_show_bdaddr(struct device *dev, struct device_attribute *attr,
1700+ char *buf)
1701+{
1702+ struct hci_h4p_info *info = (struct hci_h4p_info*)dev_get_drvdata(dev);
1703+
1704+ return sprintf(buf, "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
1705+ info->bdaddr[0],
1706+ info->bdaddr[1],
1707+ info->bdaddr[2],
1708+ info->bdaddr[3],
1709+ info->bdaddr[4],
1710+ info->bdaddr[5]);
1711+}
1712+
1713+static DEVICE_ATTR(bdaddr, S_IRUGO | S_IWUSR, hci_h4p_show_bdaddr, hci_h4p_store_bdaddr);
1714+int hci_h4p_sysfs_create_files(struct device *dev)
1715+{
1716+ return device_create_file(dev, &dev_attr_bdaddr);
1717+}
1718+
1719+#endif
1720Index: linux-2.6.35/drivers/bluetooth/hci_h4p/uart.c
1721===================================================================
1722--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1723@@ -0,0 +1,169 @@
1724+/*
1725+ * This file is part of hci_h4p bluetooth driver
1726+ *
1727+ * Copyright (C) 2005, 2006 Nokia Corporation.
1728+ *
1729+ * Contact: Ville Tervo <ville.tervo@nokia.com>
1730+ *
1731+ * This program is free software; you can redistribute it and/or
1732+ * modify it under the terms of the GNU General Public License
1733+ * version 2 as published by the Free Software Foundation.
1734+ *
1735+ * This program is distributed in the hope that it will be useful, but
1736+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1737+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1738+ * General Public License for more details.
1739+ *
1740+ * You should have received a copy of the GNU General Public License
1741+ * along with this program; if not, write to the Free Software
1742+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1743+ * 02110-1301 USA
1744+ *
1745+ */
1746+
1747+#include <linux/serial_reg.h>
1748+#include <linux/delay.h>
1749+#include <linux/clk.h>
1750+
1751+#include <asm/io.h>
1752+
1753+#include "hci_h4p.h"
1754+
1755+inline void hci_h4p_outb(struct hci_h4p_info *info, unsigned int offset, u8 val)
1756+{
1757+ offset <<= 2;
1758+ __raw_writeb(val, info->uart_base + offset);
1759+ //outb(val, info->uart_base + (offset << 2));
1760+}
1761+
1762+inline u8 hci_h4p_inb(struct hci_h4p_info *info, unsigned int offset)
1763+{
1764+ offset <<= 2;
1765+ return (u8)__raw_readb(info->uart_base + offset);
1766+ //return (unsigned int)__raw_readb(up->membase + offset);
1767+ //return inb(info->uart_base + (offset << 2));
1768+}
1769+
1770+void hci_h4p_set_rts(struct hci_h4p_info *info, int active)
1771+{
1772+ u8 b;
1773+
1774+ b = hci_h4p_inb(info, UART_MCR);
1775+ if (active)
1776+ b |= UART_MCR_RTS;
1777+ else
1778+ b &= ~UART_MCR_RTS;
1779+ hci_h4p_outb(info, UART_MCR, b);
1780+}
1781+
1782+int hci_h4p_wait_for_cts(struct hci_h4p_info *info, int active,
1783+ int timeout_ms)
1784+{
1785+ int okay;
1786+ unsigned long timeout;
1787+
1788+ okay = 0;
1789+ timeout = jiffies + msecs_to_jiffies(timeout_ms);
1790+ for (;;) {
1791+ int state;
1792+
1793+ state = hci_h4p_inb(info, UART_MSR) & UART_MSR_CTS;
1794+ if (active) {
1795+ if (state)
1796+ return 0;
1797+ } else {
1798+ if (!state)
1799+ return 0;
1800+ }
1801+ if (time_after(jiffies, timeout))
1802+ return -ETIMEDOUT;
1803+ }
1804+}
1805+
1806+void __hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which)
1807+{
1808+ u8 lcr, b;
1809+
1810+ lcr = hci_h4p_inb(info, UART_LCR);
1811+ hci_h4p_outb(info, UART_LCR, 0xbf);
1812+ b = hci_h4p_inb(info, UART_EFR);
1813+ if (on)
1814+ b |= which;
1815+ else
1816+ b &= ~which;
1817+ hci_h4p_outb(info, UART_EFR, b);
1818+ hci_h4p_outb(info, UART_LCR, lcr);
1819+}
1820+
1821+void hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which)
1822+{
1823+ unsigned long flags;
1824+
1825+ spin_lock_irqsave(&info->lock, flags);
1826+ __hci_h4p_set_auto_ctsrts(info, on, which);
1827+ spin_unlock_irqrestore(&info->lock, flags);
1828+}
1829+
1830+void hci_h4p_change_speed(struct hci_h4p_info *info, unsigned long speed)
1831+{
1832+ unsigned int divisor;
1833+ u8 lcr, mdr1;
1834+
1835+ NBT_DBG("Setting speed %lu\n", speed);
1836+
1837+ if (speed >= 460800) {
1838+ divisor = UART_CLOCK / 13 / speed;
1839+ mdr1 = 3;
1840+ } else {
1841+ divisor = UART_CLOCK / 16 / speed;
1842+ mdr1 = 0;
1843+ }
1844+
1845+ hci_h4p_outb(info, UART_OMAP_MDR1, 7); /* Make sure UART mode is disabled */
1846+ lcr = hci_h4p_inb(info, UART_LCR);
1847+ hci_h4p_outb(info, UART_LCR, UART_LCR_DLAB); /* Set DLAB */
1848+ hci_h4p_outb(info, UART_DLL, divisor & 0xff); /* Set speed */
1849+ hci_h4p_outb(info, UART_DLM, divisor >> 8);
1850+ hci_h4p_outb(info, UART_LCR, lcr);
1851+ hci_h4p_outb(info, UART_OMAP_MDR1, mdr1); /* Make sure UART mode is enabled */
1852+}
1853+
1854+int hci_h4p_reset_uart(struct hci_h4p_info *info)
1855+{
1856+ int count = 0;
1857+
1858+ /* Reset the UART */
1859+ hci_h4p_outb(info, UART_OMAP_SYSC, UART_SYSC_OMAP_RESET);
1860+ while (!(hci_h4p_inb(info, UART_OMAP_SYSS) & UART_SYSS_RESETDONE)) {
1861+ if (count++ > 20000) {
1862+ dev_err(info->dev, "hci_h4p: UART reset timeout\n");
1863+ return -ENODEV;
1864+ }
1865+ udelay(1);
1866+ }
1867+
1868+ return 0;
1869+}
1870+
1871+int hci_h4p_init_uart(struct hci_h4p_info *info)
1872+{
1873+ int err;
1874+
1875+ err = hci_h4p_reset_uart(info);
1876+ if (err < 0)
1877+ return err;
1878+
1879+ /* Enable and setup FIFO */
1880+ hci_h4p_outb(info, UART_LCR, UART_LCR_WLEN8);
1881+ hci_h4p_outb(info, UART_OMAP_MDR1, 0x00); /* Make sure UART mode is enabled */
1882+ hci_h4p_outb(info, UART_OMAP_SCR, 0x80);
1883+ hci_h4p_outb(info, UART_EFR, UART_EFR_ECB);
1884+ hci_h4p_outb(info, UART_MCR, UART_MCR_TCRTLR);
1885+ hci_h4p_outb(info, UART_TI752_TLR, 0x1f);
1886+ hci_h4p_outb(info, UART_TI752_TCR, 0xef);
1887+ hci_h4p_outb(info, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
1888+ UART_FCR_CLEAR_XMIT | UART_FCR_R_TRIG_00);
1889+ hci_h4p_outb(info, UART_IER, UART_IER_RDI);
1890+
1891+ return 0;
1892+}
1893Index: linux-2.6.35/drivers/bluetooth/Kconfig
1894===================================================================
1895--- linux-2.6.35.orig/drivers/bluetooth/Kconfig 2010-08-08 12:56:10.000000000 +0200
1896@@ -161,6 +161,16 @@ config BT_HCIBTUART
1897       Say Y here to compile support for HCI UART devices into the
1898       kernel or say M to compile it as module (btuart_cs).
1899
1900+config BT_HCIH4P
1901+ tristate "HCI driver with H4 Nokia extensions"
1902+ depends on BT && ARCH_OMAP
1903+ help
1904+ Bluetooth HCI driver with H4 extensions. This driver provides
1905+ support for H4+ Bluetooth chip with vendor-specific H4 extensions.
1906+
1907+ Say Y here to compile support for h4 extended devices into the kernel
1908+ or say M to compile it as module (hci_h4p).
1909+
1910 config BT_HCIVHCI
1911     tristate "HCI VHCI (Virtual HCI device) driver"
1912     help
1913Index: linux-2.6.35/drivers/bluetooth/Makefile
1914===================================================================
1915--- linux-2.6.35.orig/drivers/bluetooth/Makefile 2010-08-08 12:56:10.000000000 +0200
1916@@ -11,6 +11,7 @@ obj-$(CONFIG_BT_HCIDTL1) += dtl1_cs.o
1917 obj-$(CONFIG_BT_HCIBT3C) += bt3c_cs.o
1918 obj-$(CONFIG_BT_HCIBLUECARD) += bluecard_cs.o
1919 obj-$(CONFIG_BT_HCIBTUART) += btuart_cs.o
1920+obj-$(CONFIG_BT_HCIH4P) += hci_h4p/
1921
1922 obj-$(CONFIG_BT_HCIBTUSB) += btusb.o
1923 obj-$(CONFIG_BT_HCIBTSDIO) += btsdio.o
target/linux/omap24xx/patches-2.6.35/500-cbus.patch
1---
2 arch/arm/Kconfig | 4
3 drivers/Makefile | 2
4 drivers/cbus/Kconfig | 89 ++++
5 drivers/cbus/Makefile | 14
6 drivers/cbus/cbus.c | 309 ++++++++++++++++
7 drivers/cbus/cbus.h | 36 +
8 drivers/cbus/retu-headset.c | 355 ++++++++++++++++++
9 drivers/cbus/retu-pwrbutton.c | 118 ++++++
10 drivers/cbus/retu-rtc.c | 477 +++++++++++++++++++++++++
11 drivers/cbus/retu-user.c | 425 ++++++++++++++++++++++
12 drivers/cbus/retu-wdt.c | 388 ++++++++++++++++++++
13 drivers/cbus/retu.c | 468 ++++++++++++++++++++++++
14 drivers/cbus/retu.h | 77 ++++
15 drivers/cbus/tahvo-usb.c | 777 +++++++++++++++++++++++++++++++++++++++++
16 drivers/cbus/tahvo-user.c | 407 +++++++++++++++++++++
17 drivers/cbus/tahvo.c | 443 +++++++++++++++++++++++
18 drivers/cbus/tahvo.h | 61 +++
19 drivers/cbus/user_retu_tahvo.h | 75 +++
20 18 files changed, 4524 insertions(+), 1 deletion(-)
21
22--- /dev/null
23@@ -0,0 +1,309 @@
24+/*
25+ * drivers/cbus/cbus.c
26+ *
27+ * Support functions for CBUS serial protocol
28+ *
29+ * Copyright (C) 2004, 2005 Nokia Corporation
30+ *
31+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
32+ * David Weinehall <david.weinehall@nokia.com>, and
33+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
34+ *
35+ * This file is subject to the terms and conditions of the GNU General
36+ * Public License. See the file "COPYING" in the main directory of this
37+ * archive for more details.
38+ *
39+ * This program is distributed in the hope that it will be useful,
40+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42+ * GNU General Public License for more details.
43+ *
44+ * You should have received a copy of the GNU General Public License
45+ * along with this program; if not, write to the Free Software
46+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
47+ */
48+
49+#include <linux/device.h>
50+#include <linux/init.h>
51+#include <linux/kernel.h>
52+#include <linux/delay.h>
53+#include <linux/spinlock.h>
54+#include <linux/gpio.h>
55+#include <linux/platform_device.h>
56+#include <linux/slab.h>
57+
58+#include <asm/io.h>
59+#include <asm/mach-types.h>
60+
61+#include <plat/board.h>
62+#include <plat/cbus.h>
63+
64+#include "cbus.h"
65+
66+struct cbus_host *cbus_host = NULL;
67+EXPORT_SYMBOL(cbus_host);
68+
69+#ifdef CONFIG_ARCH_OMAP1
70+/* We use our own MPUIO functions to get closer to 1MHz bus speed */
71+
72+static inline void cbus_set_gpio_direction(u32 base, int mpuio, int is_input)
73+{
74+ u16 w;
75+
76+ mpuio &= 0x0f;
77+ w = __raw_readw(base + OMAP_MPUIO_IO_CNTL);
78+ if (is_input)
79+ w |= 1 << mpuio;
80+ else
81+ w &= ~(1 << mpuio);
82+ __raw_writew(w, base + OMAP_MPUIO_IO_CNTL);
83+
84+}
85+
86+static inline void cbus_set_gpio_dataout(u32 base, int mpuio, int enable)
87+{
88+ u16 w;
89+
90+ mpuio &= 0x0f;
91+ w = __raw_readw(base + OMAP_MPUIO_OUTPUT);
92+ if (enable)
93+ w |= 1 << mpuio;
94+ else
95+ w &= ~(1 << mpuio);
96+ __raw_writew(w, base + OMAP_MPUIO_OUTPUT);
97+}
98+
99+static inline int cbus_get_gpio_datain(u32 base, int mpuio)
100+{
101+ mpuio &= 0x0f;
102+
103+ return (__raw_readw(base + OMAP_MPUIO_INPUT_LATCH) & (1 << mpuio)) != 0;
104+}
105+
106+static void cbus_send_bit(struct cbus_host *host, u32 base, int bit,
107+ int set_to_input)
108+{
109+ cbus_set_gpio_dataout(base, host->dat_gpio, bit ? 1 : 0);
110+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
111+
112+ /* The data bit is read on the rising edge of CLK */
113+ if (set_to_input)
114+ cbus_set_gpio_direction(base, host->dat_gpio, 1);
115+
116+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
117+}
118+
119+static u8 cbus_receive_bit(struct cbus_host *host, u32 base)
120+{
121+ u8 ret;
122+
123+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
124+ ret = cbus_get_gpio_datain(base, host->dat_gpio);
125+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
126+
127+ return ret;
128+}
129+
130+#define cbus_output(base, gpio, val) cbus_set_gpio_direction(base, gpio, 0)
131+
132+#else
133+
134+#define cbus_output(base, gpio, val) gpio_direction_output(gpio, val)
135+#define cbus_set_gpio_dataout(base, gpio, enable) gpio_set_value(gpio, enable)
136+#define cbus_get_gpio_datain(base, int, gpio) gpio_get_value(gpio)
137+
138+static void _cbus_send_bit(struct cbus_host *host, int bit, int set_to_input)
139+{
140+ gpio_set_value(host->dat_gpio, bit ? 1 : 0);
141+ gpio_set_value(host->clk_gpio, 1);
142+
143+ /* The data bit is read on the rising edge of CLK */
144+ if (set_to_input)
145+ gpio_direction_input(host->dat_gpio);
146+
147+ gpio_set_value(host->clk_gpio, 0);
148+}
149+
150+static u8 _cbus_receive_bit(struct cbus_host *host)
151+{
152+ u8 ret;
153+
154+ gpio_set_value(host->clk_gpio, 1);
155+ ret = gpio_get_value(host->dat_gpio);
156+ gpio_set_value(host->clk_gpio, 0);
157+
158+ return ret;
159+}
160+
161+#define cbus_send_bit(host, base, bit, set_to_input) _cbus_send_bit(host, bit, set_to_input)
162+#define cbus_receive_bit(host, base) _cbus_receive_bit(host)
163+
164+#endif
165+
166+static int cbus_transfer(struct cbus_host *host, int dev, int reg, int data)
167+{
168+ int i;
169+ int is_read = 0;
170+ unsigned long flags;
171+ u32 base;
172+
173+#ifdef CONFIG_ARCH_OMAP1
174+ base = OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE);
175+#else
176+ base = 0;
177+#endif
178+
179+ if (data < 0)
180+ is_read = 1;
181+
182+ /* We don't want interrupts disturbing our transfer */
183+ spin_lock_irqsave(&host->lock, flags);
184+
185+ /* Reset state and start of transfer, SEL stays down during transfer */
186+ cbus_set_gpio_dataout(base, host->sel_gpio, 0);
187+
188+ /* Set the DAT pin to output */
189+ cbus_output(base, host->dat_gpio, 1);
190+
191+ /* Send the device address */
192+ for (i = 3; i > 0; i--)
193+ cbus_send_bit(host, base, dev & (1 << (i - 1)), 0);
194+
195+ /* Send the rw flag */
196+ cbus_send_bit(host, base, is_read, 0);
197+
198+ /* Send the register address */
199+ for (i = 5; i > 0; i--) {
200+ int set_to_input = 0;
201+
202+ if (is_read && i == 1)
203+ set_to_input = 1;
204+
205+ cbus_send_bit(host, base, reg & (1 << (i - 1)), set_to_input);
206+ }
207+
208+ if (!is_read) {
209+ for (i = 16; i > 0; i--)
210+ cbus_send_bit(host, base, data & (1 << (i - 1)), 0);
211+ } else {
212+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
213+ data = 0;
214+
215+ for (i = 16; i > 0; i--) {
216+ u8 bit = cbus_receive_bit(host, base);
217+
218+ if (bit)
219+ data |= 1 << (i - 1);
220+ }
221+ }
222+
223+ /* Indicate end of transfer, SEL goes up until next transfer */
224+ cbus_set_gpio_dataout(base, host->sel_gpio, 1);
225+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
226+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
227+
228+ spin_unlock_irqrestore(&host->lock, flags);
229+
230+ return is_read ? data : 0;
231+}
232+
233+/*
234+ * Read a given register from the device
235+ */
236+int cbus_read_reg(struct cbus_host *host, int dev, int reg)
237+{
238+ return cbus_host ? cbus_transfer(host, dev, reg, -1) : -ENODEV;
239+}
240+EXPORT_SYMBOL(cbus_read_reg);
241+
242+/*
243+ * Write to a given register of the device
244+ */
245+int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val)
246+{
247+ return cbus_host ? cbus_transfer(host, dev, reg, (int)val) : -ENODEV;
248+}
249+EXPORT_SYMBOL(cbus_write_reg);
250+
251+static int __init cbus_bus_probe(struct platform_device *pdev)
252+{
253+ struct cbus_host *chost;
254+ struct cbus_host_platform_data *pdata = pdev->dev.platform_data;
255+ int ret;
256+
257+ chost = kzalloc(sizeof (*chost), GFP_KERNEL);
258+ if (chost == NULL)
259+ return -ENOMEM;
260+
261+ spin_lock_init(&chost->lock);
262+
263+ chost->clk_gpio = pdata->clk_gpio;
264+ chost->dat_gpio = pdata->dat_gpio;
265+ chost->sel_gpio = pdata->sel_gpio;
266+
267+ if ((ret = gpio_request(chost->clk_gpio, "CBUS clk")) < 0)
268+ goto exit1;
269+
270+ if ((ret = gpio_request(chost->dat_gpio, "CBUS data")) < 0)
271+ goto exit2;
272+
273+ if ((ret = gpio_request(chost->sel_gpio, "CBUS sel")) < 0)
274+ goto exit3;
275+
276+ gpio_direction_output(chost->clk_gpio, 0);
277+ gpio_direction_input(chost->dat_gpio);
278+ gpio_direction_output(chost->sel_gpio, 1);
279+
280+ gpio_set_value(chost->clk_gpio, 1);
281+ gpio_set_value(chost->clk_gpio, 0);
282+
283+ platform_set_drvdata(pdev, chost);
284+
285+ cbus_host = chost;
286+
287+ return 0;
288+exit3:
289+ gpio_free(chost->dat_gpio);
290+exit2:
291+ gpio_free(chost->clk_gpio);
292+exit1:
293+ kfree(chost);
294+
295+ return ret;
296+}
297+
298+static void __exit cbus_bus_remove(struct platform_device *pdev)
299+{
300+ struct cbus_host *chost = platform_get_drvdata(pdev);
301+
302+ gpio_free(chost->dat_gpio);
303+ gpio_free(chost->clk_gpio);
304+ kfree(chost);
305+}
306+
307+static struct platform_driver cbus_driver = {
308+ .remove = __exit_p(cbus_bus_remove),
309+ .driver = {
310+ .name = "cbus",
311+ },
312+};
313+
314+static int __init cbus_bus_init(void)
315+{
316+ return platform_driver_probe(&cbus_driver, cbus_bus_probe);
317+}
318+
319+subsys_initcall(cbus_bus_init);
320+
321+static void __exit cbus_bus_exit(void)
322+{
323+ platform_driver_unregister(&cbus_driver);
324+}
325+module_exit(cbus_bus_exit);
326+
327+MODULE_DESCRIPTION("CBUS serial protocol");
328+MODULE_LICENSE("GPL");
329+MODULE_AUTHOR("Juha Yrjölä");
330+MODULE_AUTHOR("David Weinehall");
331+MODULE_AUTHOR("Mikko Ylinen");
332+
333--- /dev/null
334@@ -0,0 +1,36 @@
335+/*
336+ * drivers/cbus/cbus.h
337+ *
338+ * Copyright (C) 2004, 2005 Nokia Corporation
339+ *
340+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
341+ * David Weinehall <david.weinehall@nokia.com>
342+ *
343+ * This file is subject to the terms and conditions of the GNU General
344+ * Public License. See the file "COPYING" in the main directory of this
345+ * archive for more details.
346+ *
347+ * This program is distributed in the hope that it will be useful,
348+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
349+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
350+ * GNU General Public License for more details.
351+ *
352+ * You should have received a copy of the GNU General Public License
353+ * along with this program; if not, write to the Free Software
354+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
355+ */
356+
357+#ifndef __DRIVERS_CBUS_CBUS_H
358+#define __DRIVERS_CBUS_CBUS_H
359+
360+struct cbus_host {
361+ int clk_gpio, dat_gpio, sel_gpio;
362+ spinlock_t lock;
363+};
364+
365+extern struct cbus_host *cbus_host;
366+
367+extern int cbus_read_reg(struct cbus_host *host, int dev, int reg);
368+extern int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val);
369+
370+#endif /* __DRIVERS_CBUS_CBUS_H */
371--- /dev/null
372@@ -0,0 +1,89 @@
373+#
374+# CBUS device configuration
375+#
376+
377+menu "CBUS support"
378+
379+config CBUS
380+ depends on ARCH_OMAP
381+ bool "CBUS support on OMAP"
382+ ---help---
383+ CBUS is a proprietary serial protocol by Nokia. It is mainly
384+ used for accessing Energy Management auxiliary chips.
385+
386+ If you want CBUS support, you should say Y here.
387+
388+config CBUS_TAHVO
389+ depends on CBUS
390+ bool "Support for Tahvo"
391+ ---help---
392+ Tahvo is a mixed signal ASIC with some system features
393+
394+ If you want Tahvo support, you should say Y here.
395+
396+config CBUS_TAHVO_USER
397+ depends on CBUS_TAHVO
398+ bool "Support for Tahvo user space functions"
399+ ---help---
400+ If you want support for Tahvo's user space read/write etc. functions,
401+ you should say Y here.
402+
403+config CBUS_TAHVO_USB
404+ depends on CBUS_TAHVO && USB
405+ tristate "Support for Tahvo USB transceiver"
406+ ---help---
407+ If you want Tahvo support for USB transceiver, say Y or M here.
408+
409+config CBUS_TAHVO_USB_HOST_BY_DEFAULT
410+ depends on CBUS_TAHVO_USB && USB_OTG
411+ boolean "Device in USB host mode by default"
412+ ---help---
413+ Say Y here, if you want the device to enter USB host mode
414+ by default on bootup.
415+
416+config CBUS_RETU
417+ depends on CBUS
418+ bool "Support for Retu"
419+ ---help---
420+ Retu is a mixed signal ASIC with some system features
421+
422+ If you want Retu support, you should say Y here.
423+
424+config CBUS_RETU_USER
425+ depends on CBUS_RETU
426+ bool "Support for Retu user space functions"
427+ ---help---
428+ If you want support for Retu's user space read/write etc. functions,
429+ you should say Y here.
430+
431+config CBUS_RETU_POWERBUTTON
432+ depends on CBUS_RETU
433+ bool "Support for Retu power button"
434+ ---help---
435+ The power button on Nokia 770 is connected to the Retu ASIC.
436+
437+ If you want support for the Retu power button, you should say Y here.
438+
439+config CBUS_RETU_RTC
440+ depends on CBUS_RETU && SYSFS
441+ tristate "Support for Retu pseudo-RTC"
442+ ---help---
443+ Say Y here if you want support for the device that alleges to be an
444+ RTC in Retu. This will expose a sysfs interface for it.
445+
446+config CBUS_RETU_WDT
447+ depends on CBUS_RETU && SYSFS && WATCHDOG
448+ tristate "Support for Retu watchdog timer"
449+ ---help---
450+ Say Y here if you want support for the watchdog in Retu. This will
451+ expose a sysfs interface to grok it.
452+
453+config CBUS_RETU_HEADSET
454+ depends on CBUS_RETU && SYSFS
455+ tristate "Support for headset detection with Retu/Vilma"
456+ ---help---
457+ Say Y here if you want support detecting a headset that's connected
458+ to Retu/Vilma. Detection state and events are exposed through
459+ sysfs.
460+
461+endmenu
462--- /dev/null
463@@ -0,0 +1,14 @@
464+#
465+# Makefile for CBUS.
466+#
467+
468+obj-$(CONFIG_CBUS) += cbus.o
469+obj-$(CONFIG_CBUS_TAHVO) += tahvo.o
470+obj-$(CONFIG_CBUS_RETU) += retu.o
471+obj-$(CONFIG_CBUS_TAHVO_USB) += tahvo-usb.o
472+obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o
473+obj-$(CONFIG_CBUS_RETU_RTC) += retu-rtc.o
474+obj-$(CONFIG_CBUS_RETU_WDT) += retu-wdt.o
475+obj-$(CONFIG_CBUS_TAHVO_USER) += tahvo-user.o
476+obj-$(CONFIG_CBUS_RETU_USER) += retu-user.o
477+obj-$(CONFIG_CBUS_RETU_HEADSET) += retu-headset.o
478--- /dev/null
479@@ -0,0 +1,468 @@
480+/**
481+ * drivers/cbus/retu.c
482+ *
483+ * Support functions for Retu ASIC
484+ *
485+ * Copyright (C) 2004, 2005 Nokia Corporation
486+ *
487+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
488+ * David Weinehall <david.weinehall@nokia.com>, and
489+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
490+ *
491+ * This file is subject to the terms and conditions of the GNU General
492+ * Public License. See the file "COPYING" in the main directory of this
493+ * archive for more details.
494+ *
495+ * This program is distributed in the hope that it will be useful,
496+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
497+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
498+ * GNU General Public License for more details.
499+ *
500+ * You should have received a copy of the GNU General Public License
501+ * along with this program; if not, write to the Free Software
502+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
503+ */
504+
505+#include <linux/module.h>
506+#include <linux/init.h>
507+
508+#include <linux/kernel.h>
509+#include <linux/errno.h>
510+#include <linux/device.h>
511+#include <linux/miscdevice.h>
512+#include <linux/poll.h>
513+#include <linux/fs.h>
514+#include <linux/irq.h>
515+#include <linux/interrupt.h>
516+#include <linux/platform_device.h>
517+#include <linux/gpio.h>
518+
519+#include <asm/uaccess.h>
520+#include <asm/mach-types.h>
521+
522+#include <plat/mux.h>
523+#include <plat/board.h>
524+
525+#include "cbus.h"
526+#include "retu.h"
527+
528+#define RETU_ID 0x01
529+#define PFX "retu: "
530+
531+static int retu_initialized;
532+static int retu_irq_pin;
533+static int retu_is_vilma;
534+
535+static struct tasklet_struct retu_tasklet;
536+spinlock_t retu_lock = SPIN_LOCK_UNLOCKED;
537+
538+static struct completion device_release;
539+
540+struct retu_irq_handler_desc {
541+ int (*func)(unsigned long);
542+ unsigned long arg;
543+ char name[8];
544+};
545+
546+static struct retu_irq_handler_desc retu_irq_handlers[MAX_RETU_IRQ_HANDLERS];
547+
548+/**
549+ * retu_read_reg - Read a value from a register in Retu
550+ * @reg: the register to read from
551+ *
552+ * This function returns the contents of the specified register
553+ */
554+int retu_read_reg(int reg)
555+{
556+ BUG_ON(!retu_initialized);
557+ return cbus_read_reg(cbus_host, RETU_ID, reg);
558+}
559+
560+/**
561+ * retu_write_reg - Write a value to a register in Retu
562+ * @reg: the register to write to
563+ * @reg: the value to write to the register
564+ *
565+ * This function writes a value to the specified register
566+ */
567+void retu_write_reg(int reg, u16 val)
568+{
569+ BUG_ON(!retu_initialized);
570+ cbus_write_reg(cbus_host, RETU_ID, reg, val);
571+}
572+
573+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear)
574+{
575+ unsigned long flags;
576+ u16 w;
577+
578+ spin_lock_irqsave(&retu_lock, flags);
579+ w = retu_read_reg(reg);
580+ w &= ~clear;
581+ w |= set;
582+ retu_write_reg(reg, w);
583+ spin_unlock_irqrestore(&retu_lock, flags);
584+}
585+
586+#define ADC_MAX_CHAN_NUMBER 13
587+
588+int retu_read_adc(int channel)
589+{
590+ unsigned long flags;
591+ int res;
592+
593+ if (channel < 0 || channel > ADC_MAX_CHAN_NUMBER)
594+ return -EINVAL;
595+
596+ spin_lock_irqsave(&retu_lock, flags);
597+
598+ if ((channel == 8) && retu_is_vilma) {
599+ int scr = retu_read_reg(RETU_REG_ADCSCR);
600+ int ch = (retu_read_reg(RETU_REG_ADCR) >> 10) & 0xf;
601+ if (((scr & 0xff) != 0) && (ch != 8))
602+ retu_write_reg (RETU_REG_ADCSCR, (scr & ~0xff));
603+ }
604+
605+ /* Select the channel and read result */
606+ retu_write_reg(RETU_REG_ADCR, channel << 10);
607+ res = retu_read_reg(RETU_REG_ADCR) & 0x3ff;
608+
609+ if (retu_is_vilma)
610+ retu_write_reg(RETU_REG_ADCR, (1 << 13));
611+
612+ /* Unlock retu */
613+ spin_unlock_irqrestore(&retu_lock, flags);
614+
615+ return res;
616+}
617+
618+
619+static u16 retu_disable_bogus_irqs(u16 mask)
620+{
621+ int i;
622+
623+ for (i = 0; i < MAX_RETU_IRQ_HANDLERS; i++) {
624+ if (mask & (1 << i))
625+ continue;
626+ if (retu_irq_handlers[i].func != NULL)
627+ continue;
628+ /* an IRQ was enabled but we don't have a handler for it */
629+ printk(KERN_INFO PFX "disabling bogus IRQ %d\n", i);
630+ mask |= (1 << i);
631+ }
632+ return mask;
633+}
634+
635+/*
636+ * Disable given RETU interrupt
637+ */
638+void retu_disable_irq(int id)
639+{
640+ unsigned long flags;
641+ u16 mask;
642+
643+ spin_lock_irqsave(&retu_lock, flags);
644+ mask = retu_read_reg(RETU_REG_IMR);
645+ mask |= 1 << id;
646+ mask = retu_disable_bogus_irqs(mask);
647+ retu_write_reg(RETU_REG_IMR, mask);
648+ spin_unlock_irqrestore(&retu_lock, flags);
649+}
650+
651+/*
652+ * Enable given RETU interrupt
653+ */
654+void retu_enable_irq(int id)
655+{
656+ unsigned long flags;
657+ u16 mask;
658+
659+ if (id == 3) {
660+ printk("Enabling Retu IRQ %d\n", id);
661+ dump_stack();
662+ }
663+ spin_lock_irqsave(&retu_lock, flags);
664+ mask = retu_read_reg(RETU_REG_IMR);
665+ mask &= ~(1 << id);
666+ mask = retu_disable_bogus_irqs(mask);
667+ retu_write_reg(RETU_REG_IMR, mask);
668+ spin_unlock_irqrestore(&retu_lock, flags);
669+}
670+
671+/*
672+ * Acknowledge given RETU interrupt
673+ */
674+void retu_ack_irq(int id)
675+{
676+ retu_write_reg(RETU_REG_IDR, 1 << id);
677+}
678+
679+/*
680+ * RETU interrupt handler. Only schedules the tasklet.
681+ */
682+static irqreturn_t retu_irq_handler(int irq, void *dev_id)
683+{
684+ tasklet_schedule(&retu_tasklet);
685+ return IRQ_HANDLED;
686+}
687+
688+/*
689+ * Tasklet handler
690+ */
691+static void retu_tasklet_handler(unsigned long data)
692+{
693+ struct retu_irq_handler_desc *hnd;
694+ u16 id;
695+ u16 im;
696+ int i;
697+
698+ for (;;) {
699+ id = retu_read_reg(RETU_REG_IDR);
700+ im = ~retu_read_reg(RETU_REG_IMR);
701+ id &= im;
702+
703+ if (!id)
704+ break;
705+
706+ for (i = 0; id != 0; i++, id >>= 1) {
707+ if (!(id & 1))
708+ continue;
709+ hnd = &retu_irq_handlers[i];
710+ if (hnd->func == NULL) {
711+ /* Spurious retu interrupt - disable and ack it */
712+ printk(KERN_INFO "Spurious Retu interrupt "
713+ "(id %d)\n", i);
714+ retu_disable_irq(i);
715+ retu_ack_irq(i);
716+ continue;
717+ }
718+ hnd->func(hnd->arg);
719+ /*
720+ * Don't acknowledge the interrupt here
721+ * It must be done explicitly
722+ */
723+ }
724+ }
725+}
726+
727+/*
728+ * Register the handler for a given RETU interrupt source.
729+ */
730+int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name)
731+{
732+ struct retu_irq_handler_desc *hnd;
733+
734+ if (irq_handler == NULL || id >= MAX_RETU_IRQ_HANDLERS ||
735+ name == NULL) {
736+ printk(KERN_ERR PFX "Invalid arguments to %s\n",
737+ __FUNCTION__);
738+ return -EINVAL;
739+ }
740+ hnd = &retu_irq_handlers[id];
741+ if (hnd->func != NULL) {
742+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
743+ return -EBUSY;
744+ }
745+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
746+ id, name);
747+ hnd->func = irq_handler;
748+ hnd->arg = arg;
749+ strlcpy(hnd->name, name, sizeof(hnd->name));
750+
751+ retu_ack_irq(id);
752+ retu_enable_irq(id);
753+
754+ return 0;
755+}
756+
757+/*
758+ * Unregister the handler for a given RETU interrupt source.
759+ */
760+void retu_free_irq(int id)
761+{
762+ struct retu_irq_handler_desc *hnd;
763+
764+ if (id >= MAX_RETU_IRQ_HANDLERS) {
765+ printk(KERN_ERR PFX "Invalid argument to %s\n",
766+ __FUNCTION__);
767+ return;
768+ }
769+ hnd = &retu_irq_handlers[id];
770+ if (hnd->func == NULL) {
771+ printk(KERN_ERR PFX "IRQ %d already freed\n", id);
772+ return;
773+ }
774+
775+ retu_disable_irq(id);
776+ hnd->func = NULL;
777+}
778+
779+/**
780+ * retu_power_off - Shut down power to system
781+ *
782+ * This function puts the system in power off state
783+ */
784+static void retu_power_off(void)
785+{
786+ /* Ignore power button state */
787+ retu_write_reg(RETU_REG_CC1, retu_read_reg(RETU_REG_CC1) | 2);
788+ /* Expire watchdog immediately */
789+ retu_write_reg(RETU_REG_WATCHDOG, 0);
790+ /* Wait for poweroff*/
791+ for (;;);
792+}
793+
794+/**
795+ * retu_probe - Probe for Retu ASIC
796+ * @dev: the Retu device
797+ *
798+ * Probe for the Retu ASIC and allocate memory
799+ * for its device-struct if found
800+ */
801+static int __devinit retu_probe(struct device *dev)
802+{
803+ int rev, ret;
804+
805+ /* Prepare tasklet */
806+ tasklet_init(&retu_tasklet, retu_tasklet_handler, 0);
807+
808+ /* REVISIT: Pass these from board-*.c files in platform_data */
809+ if (machine_is_nokia770()) {
810+ retu_irq_pin = 62;
811+ } else if (machine_is_nokia_n800() || machine_is_nokia_n810() ||
812+ machine_is_nokia_n810_wimax()) {
813+ retu_irq_pin = 108;
814+ } else {
815+ printk(KERN_ERR "cbus: Unsupported board for tahvo\n");
816+ return -ENODEV;
817+ }
818+
819+ if ((ret = gpio_request(retu_irq_pin, "RETU irq")) < 0) {
820+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
821+ return ret;
822+ }
823+
824+ /* Set the pin as input */
825+ gpio_direction_input(retu_irq_pin);
826+
827+ /* Rising edge triggers the IRQ */
828+ set_irq_type(gpio_to_irq(retu_irq_pin), IRQ_TYPE_EDGE_RISING);
829+
830+ retu_initialized = 1;
831+
832+ rev = retu_read_reg(RETU_REG_ASICR) & 0xff;
833+ if (rev & (1 << 7))
834+ retu_is_vilma = 1;
835+
836+ printk(KERN_INFO "%s v%d.%d found\n", retu_is_vilma ? "Vilma" : "Retu",
837+ (rev >> 4) & 0x07, rev & 0x0f);
838+
839+ /* Mask all RETU interrupts */
840+ retu_write_reg(RETU_REG_IMR, 0xffff);
841+
842+ ret = request_irq(gpio_to_irq(retu_irq_pin), retu_irq_handler, 0,
843+ "retu", 0);
844+ if (ret < 0) {
845+ printk(KERN_ERR PFX "Unable to register IRQ handler\n");
846+ gpio_free(retu_irq_pin);
847+ return ret;
848+ }
849+ set_irq_wake(gpio_to_irq(retu_irq_pin), 1);
850+
851+ /* Register power off function */
852+ pm_power_off = retu_power_off;
853+
854+#ifdef CONFIG_CBUS_RETU_USER
855+ /* Initialize user-space interface */
856+ if (retu_user_init() < 0) {
857+ printk(KERN_ERR "Unable to initialize driver\n");
858+ free_irq(gpio_to_irq(retu_irq_pin), 0);
859+ gpio_free(retu_irq_pin);
860+ return ret;
861+ }
862+#endif
863+
864+ return 0;
865+}
866+
867+static int retu_remove(struct device *dev)
868+{
869+#ifdef CONFIG_CBUS_RETU_USER
870+ retu_user_cleanup();
871+#endif
872+ /* Mask all RETU interrupts */
873+ retu_write_reg(RETU_REG_IMR, 0xffff);
874+ free_irq(gpio_to_irq(retu_irq_pin), 0);
875+ gpio_free(retu_irq_pin);
876+ tasklet_kill(&retu_tasklet);
877+
878+ return 0;
879+}
880+
881+static void retu_device_release(struct device *dev)
882+{
883+ complete(&device_release);
884+}
885+
886+static struct device_driver retu_driver = {
887+ .name = "retu",
888+ .bus = &platform_bus_type,
889+ .probe = retu_probe,
890+ .remove = retu_remove,
891+};
892+
893+static struct platform_device retu_device = {
894+ .name = "retu",
895+ .id = -1,
896+ .dev = {
897+ .release = retu_device_release,
898+ }
899+};
900+
901+/**
902+ * retu_init - initialise Retu driver
903+ *
904+ * Initialise the Retu driver and return 0 if everything worked ok
905+ */
906+static int __init retu_init(void)
907+{
908+ int ret = 0;
909+
910+ printk(KERN_INFO "Retu/Vilma driver initialising\n");
911+
912+ init_completion(&device_release);
913+
914+ if ((ret = driver_register(&retu_driver)) < 0)
915+ return ret;
916+
917+ if ((ret = platform_device_register(&retu_device)) < 0) {
918+ driver_unregister(&retu_driver);
919+ return ret;
920+ }
921+ return 0;
922+}
923+
924+/*
925+ * Cleanup
926+ */
927+static void __exit retu_exit(void)
928+{
929+ platform_device_unregister(&retu_device);
930+ driver_unregister(&retu_driver);
931+ wait_for_completion(&device_release);
932+}
933+
934+EXPORT_SYMBOL(retu_request_irq);
935+EXPORT_SYMBOL(retu_free_irq);
936+EXPORT_SYMBOL(retu_enable_irq);
937+EXPORT_SYMBOL(retu_disable_irq);
938+EXPORT_SYMBOL(retu_ack_irq);
939+EXPORT_SYMBOL(retu_read_reg);
940+EXPORT_SYMBOL(retu_write_reg);
941+
942+subsys_initcall(retu_init);
943+module_exit(retu_exit);
944+
945+MODULE_DESCRIPTION("Retu ASIC control");
946+MODULE_LICENSE("GPL");
947+MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen");
948--- /dev/null
949@@ -0,0 +1,77 @@
950+/**
951+ * drivers/cbus/retu.h
952+ *
953+ * Copyright (C) 2004, 2005 Nokia Corporation
954+ *
955+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
956+ * David Weinehall <david.weinehall@nokia.com>
957+ *
958+ * This file is subject to the terms and conditions of the GNU General
959+ * Public License. See the file "COPYING" in the main directory of this
960+ * archive for more details.
961+ *
962+ * This program is distributed in the hope that it will be useful,
963+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
964+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
965+ * GNU General Public License for more details.
966+
967+ * You should have received a copy of the GNU General Public License
968+ * along with this program; if not, write to the Free Software
969+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
970+ */
971+
972+#ifndef __DRIVERS_CBUS_RETU_H
973+#define __DRIVERS_CBUS_RETU_H
974+
975+#include <linux/types.h>
976+
977+/* Registers */
978+#define RETU_REG_ASICR 0x00 /* ASIC ID & revision */
979+#define RETU_REG_IDR 0x01 /* Interrupt ID */
980+#define RETU_REG_IMR 0x02 /* Interrupt mask */
981+#define RETU_REG_RTCDSR 0x03 /* RTC seconds register */
982+#define RETU_REG_RTCHMR 0x04 /* RTC hours and minutes register */
983+#define RETU_REG_RTCHMAR 0x05 /* RTC hours and minutes alarm and time set register */
984+#define RETU_REG_RTCCALR 0x06 /* RTC calibration register */
985+#define RETU_REG_ADCR 0x08 /* ADC result */
986+#define RETU_REG_ADCSCR 0x09 /* ADC sample ctrl */
987+#define RETU_REG_CC1 0x0d /* Common control register 1 */
988+#define RETU_REG_CC2 0x0e /* Common control register 2 */
989+#define RETU_REG_CTRL_CLR 0x0f /* Regulator clear register */
990+#define RETU_REG_CTRL_SET 0x10 /* Regulator set register */
991+#define RETU_REG_STATUS 0x16 /* Status register */
992+#define RETU_REG_WATCHDOG 0x17 /* Watchdog register */
993+#define RETU_REG_AUDTXR 0x18 /* Audio Codec Tx register */
994+#define RETU_REG_MAX 0x1f
995+
996+/* Interrupt sources */
997+#define RETU_INT_PWR 0
998+#define RETU_INT_CHAR 1
999+#define RETU_INT_RTCS 2
1000+#define RETU_INT_RTCM 3
1001+#define RETU_INT_RTCD 4
1002+#define RETU_INT_RTCA 5
1003+#define RETU_INT_HOOK 6
1004+#define RETU_INT_HEAD 7
1005+#define RETU_INT_ADCS 8
1006+
1007+#define MAX_RETU_IRQ_HANDLERS 16
1008+
1009+int retu_read_reg(int reg);
1010+void retu_write_reg(int reg, u16 val);
1011+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear);
1012+int retu_read_adc(int channel);
1013+int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name);
1014+void retu_free_irq(int id);
1015+void retu_enable_irq(int id);
1016+void retu_disable_irq(int id);
1017+void retu_ack_irq(int id);
1018+
1019+#ifdef CONFIG_CBUS_RETU_USER
1020+int retu_user_init(void);
1021+void retu_user_cleanup(void);
1022+#endif
1023+
1024+extern spinlock_t retu_lock;
1025+
1026+#endif /* __DRIVERS_CBUS_RETU_H */
1027--- /dev/null
1028@@ -0,0 +1,355 @@
1029+/**
1030+ * Retu/Vilma headset detection
1031+ *
1032+ * Copyright (C) 2006 Nokia Corporation
1033+ *
1034+ * Written by Juha Yrjölä
1035+ *
1036+ * This file is subject to the terms and conditions of the GNU General
1037+ * Public License. See the file "COPYING" in the main directory of this
1038+ * archive for more details.
1039+ *
1040+ * This program is distributed in the hope that it will be useful,
1041+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1042+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1043+ * GNU General Public License for more details.
1044+ *
1045+ * You should have received a copy of the GNU General Public License
1046+ * along with this program; if not, write to the Free Software
1047+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1048+ */
1049+
1050+#include <linux/module.h>
1051+#include <linux/init.h>
1052+#include <linux/kernel.h>
1053+#include <linux/delay.h>
1054+#include <linux/input.h>
1055+#include <linux/platform_device.h>
1056+
1057+#include "retu.h"
1058+
1059+#define RETU_ADC_CHANNEL_HOOKDET 0x05
1060+
1061+#define RETU_HEADSET_KEY KEY_PHONE
1062+
1063+struct retu_headset {
1064+ spinlock_t lock;
1065+ struct mutex mutex;
1066+ struct platform_device *pdev;
1067+ struct input_dev *idev;
1068+ unsigned bias_enabled;
1069+ unsigned detection_enabled;
1070+ unsigned pressed;
1071+ struct timer_list enable_timer;
1072+ struct timer_list detect_timer;
1073+};
1074+
1075+static void retu_headset_set_bias(int enable)
1076+{
1077+ if (enable) {
1078+ retu_set_clear_reg_bits(RETU_REG_AUDTXR,
1079+ (1 << 0) | (1 << 1), 0);
1080+ msleep(2);
1081+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 1 << 3, 0);
1082+ } else {
1083+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 0,
1084+ (1 << 0) | (1 << 1) | (1 << 3));
1085+ }
1086+}
1087+
1088+static void retu_headset_enable(struct retu_headset *hs)
1089+{
1090+ mutex_lock(&hs->mutex);
1091+ if (!hs->bias_enabled) {
1092+ hs->bias_enabled = 1;
1093+ retu_headset_set_bias(1);
1094+ }
1095+ mutex_unlock(&hs->mutex);
1096+}
1097+
1098+static void retu_headset_disable(struct retu_headset *hs)
1099+{
1100+ mutex_lock(&hs->mutex);
1101+ if (hs->bias_enabled) {
1102+ hs->bias_enabled = 0;
1103+ retu_headset_set_bias(0);
1104+ }
1105+ mutex_unlock(&hs->mutex);
1106+}
1107+
1108+static void retu_headset_det_enable(struct retu_headset *hs)
1109+{
1110+ mutex_lock(&hs->mutex);
1111+ if (!hs->detection_enabled) {
1112+ hs->detection_enabled = 1;
1113+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0);
1114+ retu_enable_irq(RETU_INT_HOOK);
1115+ }
1116+ mutex_unlock(&hs->mutex);
1117+}
1118+
1119+static void retu_headset_det_disable(struct retu_headset *hs)
1120+{
1121+ unsigned long flags;
1122+
1123+ mutex_lock(&hs->mutex);
1124+ if (hs->detection_enabled) {
1125+ hs->detection_enabled = 0;
1126+ retu_disable_irq(RETU_INT_HOOK);
1127+ del_timer_sync(&hs->enable_timer);
1128+ del_timer_sync(&hs->detect_timer);
1129+ spin_lock_irqsave(&hs->lock, flags);
1130+ if (hs->pressed)
1131+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
1132+ spin_unlock_irqrestore(&hs->lock, flags);
1133+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8));
1134+ }
1135+ mutex_unlock(&hs->mutex);
1136+}
1137+
1138+static ssize_t retu_headset_hookdet_show(struct device *dev,
1139+ struct device_attribute *attr,
1140+ char *buf)
1141+{
1142+ int val;
1143+
1144+ val = retu_read_adc(RETU_ADC_CHANNEL_HOOKDET);
1145+ return sprintf(buf, "%d\n", val);
1146+}
1147+
1148+static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL);
1149+
1150+static ssize_t retu_headset_enable_show(struct device *dev,
1151+ struct device_attribute *attr,
1152+ char *buf)
1153+{
1154+ struct retu_headset *hs = dev_get_drvdata(dev);
1155+
1156+ return sprintf(buf, "%u\n", hs->bias_enabled);
1157+}
1158+
1159+static ssize_t retu_headset_enable_store(struct device *dev,
1160+ struct device_attribute *attr,
1161+ const char *buf, size_t count)
1162+{
1163+ struct retu_headset *hs = dev_get_drvdata(dev);
1164+ int enable;
1165+
1166+ if (sscanf(buf, "%u", &enable) != 1)
1167+ return -EINVAL;
1168+ if (enable)
1169+ retu_headset_enable(hs);
1170+ else
1171+ retu_headset_disable(hs);
1172+ return count;
1173+}
1174+
1175+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR | S_IWGRP,
1176+ retu_headset_enable_show, retu_headset_enable_store);
1177+
1178+static ssize_t retu_headset_enable_det_show(struct device *dev,
1179+ struct device_attribute *attr,
1180+ char *buf)
1181+{
1182+ struct retu_headset *hs = dev_get_drvdata(dev);
1183+
1184+ return sprintf(buf, "%u\n", hs->detection_enabled);
1185+}
1186+
1187+static ssize_t retu_headset_enable_det_store(struct device *dev,
1188+ struct device_attribute *attr,
1189+ const char *buf, size_t count)
1190+{
1191+ struct retu_headset *hs = dev_get_drvdata(dev);
1192+ int enable;
1193+
1194+ if (sscanf(buf, "%u", &enable) != 1)
1195+ return -EINVAL;
1196+ if (enable)
1197+ retu_headset_det_enable(hs);
1198+ else
1199+ retu_headset_det_disable(hs);
1200+ return count;
1201+}
1202+
1203+static DEVICE_ATTR(enable_det, S_IRUGO | S_IWUSR | S_IWGRP,
1204+ retu_headset_enable_det_show,
1205+ retu_headset_enable_det_store);
1206+
1207+static void retu_headset_hook_interrupt(unsigned long arg)
1208+{
1209+ struct retu_headset *hs = (struct retu_headset *) arg;
1210+ unsigned long flags;
1211+
1212+ retu_ack_irq(RETU_INT_HOOK);
1213+ spin_lock_irqsave(&hs->lock, flags);
1214+ if (!hs->pressed) {
1215+ /* Headset button was just pressed down. */
1216+ hs->pressed = 1;
1217+ input_report_key(hs->idev, RETU_HEADSET_KEY, 1);
1218+ }
1219+ spin_unlock_irqrestore(&hs->lock, flags);
1220+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8));
1221+ mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50));
1222+}
1223+
1224+static void retu_headset_enable_timer(unsigned long arg)
1225+{
1226+ struct retu_headset *hs = (struct retu_headset *) arg;
1227+
1228+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0);
1229+ mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350));
1230+}
1231+
1232+static void retu_headset_detect_timer(unsigned long arg)
1233+{
1234+ struct retu_headset *hs = (struct retu_headset *) arg;
1235+ unsigned long flags;
1236+
1237+ spin_lock_irqsave(&hs->lock, flags);
1238+ if (hs->pressed) {
1239+ hs->pressed = 0;
1240+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
1241+ }
1242+ spin_unlock_irqrestore(&hs->lock, flags);
1243+}
1244+
1245+static int __init retu_headset_probe(struct platform_device *pdev)
1246+{
1247+ struct retu_headset *hs;
1248+ int r;
1249+
1250+ hs = kzalloc(sizeof(*hs), GFP_KERNEL);
1251+ if (hs == NULL)
1252+ return -ENOMEM;
1253+
1254+ hs->pdev = pdev;
1255+
1256+ hs->idev = input_allocate_device();
1257+ if (hs->idev == NULL) {
1258+ r = -ENOMEM;
1259+ goto err1;
1260+ }
1261+ hs->idev->name = "retu-headset";
1262+ hs->idev->dev.parent = &pdev->dev;
1263+ set_bit(EV_KEY, hs->idev->evbit);
1264+ set_bit(RETU_HEADSET_KEY, hs->idev->keybit);
1265+ r = input_register_device(hs->idev);
1266+ if (r < 0)
1267+ goto err2;
1268+
1269+ r = device_create_file(&pdev->dev, &dev_attr_hookdet);
1270+ if (r < 0)
1271+ goto err3;
1272+ r = device_create_file(&pdev->dev, &dev_attr_enable);
1273+ if (r < 0)
1274+ goto err4;
1275+ r = device_create_file(&pdev->dev, &dev_attr_enable_det);
1276+ if (r < 0)
1277+ goto err5;
1278+ platform_set_drvdata(pdev, hs);
1279+
1280+ spin_lock_init(&hs->lock);
1281+ mutex_init(&hs->mutex);
1282+ setup_timer(&hs->enable_timer, retu_headset_enable_timer,
1283+ (unsigned long) hs);
1284+ setup_timer(&hs->detect_timer, retu_headset_detect_timer,
1285+ (unsigned long) hs);
1286+
1287+ r = retu_request_irq(RETU_INT_HOOK, retu_headset_hook_interrupt,
1288+ (unsigned long) hs, "hookdet");
1289+ if (r != 0) {
1290+ dev_err(&pdev->dev, "hookdet IRQ not available\n");
1291+ goto err6;
1292+ }
1293+ retu_disable_irq(RETU_INT_HOOK);
1294+ return 0;
1295+err6:
1296+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
1297+err5:
1298+ device_remove_file(&pdev->dev, &dev_attr_enable);
1299+err4:
1300+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
1301+err3:
1302+ input_unregister_device(hs->idev);
1303+err2:
1304+ input_free_device(hs->idev);
1305+err1:
1306+ kfree(hs);
1307+ return r;
1308+}
1309+
1310+static int retu_headset_remove(struct platform_device *pdev)
1311+{
1312+ struct retu_headset *hs = platform_get_drvdata(pdev);
1313+
1314+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
1315+ device_remove_file(&pdev->dev, &dev_attr_enable);
1316+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
1317+ retu_headset_disable(hs);
1318+ retu_headset_det_disable(hs);
1319+ retu_free_irq(RETU_INT_HOOK);
1320+ input_unregister_device(hs->idev);
1321+ input_free_device(hs->idev);
1322+ return 0;
1323+}
1324+
1325+static int retu_headset_suspend(struct platform_device *pdev,
1326+ pm_message_t mesg)
1327+{
1328+ struct retu_headset *hs = platform_get_drvdata(pdev);
1329+
1330+ mutex_lock(&hs->mutex);
1331+ if (hs->bias_enabled)
1332+ retu_headset_set_bias(0);
1333+ mutex_unlock(&hs->mutex);
1334+
1335+ return 0;
1336+}
1337+
1338+static int retu_headset_resume(struct platform_device *pdev)
1339+{
1340+ struct retu_headset *hs = platform_get_drvdata(pdev);
1341+
1342+ mutex_lock(&hs->mutex);
1343+ if (hs->bias_enabled)
1344+ retu_headset_set_bias(1);
1345+ mutex_unlock(&hs->mutex);
1346+
1347+ return 0;
1348+}
1349+
1350+static struct platform_driver retu_headset_driver = {
1351+ .probe = retu_headset_probe,
1352+ .remove = retu_headset_remove,
1353+ .suspend = retu_headset_suspend,
1354+ .resume = retu_headset_resume,
1355+ .driver = {
1356+ .name = "retu-headset",
1357+ },
1358+};
1359+
1360+static int __init retu_headset_init(void)
1361+{
1362+ int r;
1363+
1364+ printk(KERN_INFO "Retu/Vilma headset driver initializing\n");
1365+
1366+ r = platform_driver_register(&retu_headset_driver);
1367+ if (r < 0)
1368+ return r;
1369+
1370+ return 0;
1371+}
1372+
1373+static void __exit retu_headset_exit(void)
1374+{
1375+ platform_driver_unregister(&retu_headset_driver);
1376+}
1377+
1378+module_init(retu_headset_init);
1379+module_exit(retu_headset_exit);
1380+
1381+MODULE_DESCRIPTION("Retu/Vilma headset detection");
1382+MODULE_LICENSE("GPL");
1383+MODULE_AUTHOR("Juha Yrjölä");
1384--- /dev/null
1385@@ -0,0 +1,118 @@
1386+/**
1387+ * drivers/cbus/retu-pwrbutton.c
1388+ *
1389+ * Driver for sending retu power button event to input-layer
1390+ *
1391+ * Copyright (C) 2004 Nokia Corporation
1392+ *
1393+ * Written by Ari Saastamoinen <ari.saastamoinen@elektrobit.com>
1394+ *
1395+ * Contact Juha Yrjölä <juha.yrjola@nokia.com>
1396+ *
1397+ * This file is subject to the terms and conditions of the GNU General
1398+ * Public License. See the file "COPYING" in the main directory of this
1399+ * archive for more details.
1400+ *
1401+ * This program is distributed in the hope that it will be useful,
1402+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1403+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1404+ * GNU General Public License for more details.
1405+ *
1406+ * You should have received a copy of the GNU General Public License
1407+ * along with this program; if not, write to the Free Software
1408+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1409+ */
1410+
1411+#include <linux/module.h>
1412+#include <linux/init.h>
1413+#include <linux/kernel.h>
1414+#include <linux/errno.h>
1415+#include <linux/input.h>
1416+#include <linux/timer.h>
1417+#include <linux/jiffies.h>
1418+#include <linux/bitops.h>
1419+
1420+#include "retu.h"
1421+
1422+#define RETU_STATUS_PWRONX (1 << 5)
1423+
1424+#define PWRBTN_DELAY 20
1425+#define PWRBTN_UP 0
1426+#define PWRBTN_PRESSED 1
1427+
1428+static int pwrbtn_state;
1429+static struct input_dev *pwrbtn_dev;
1430+static struct timer_list pwrbtn_timer;
1431+
1432+static void retubutton_timer_func(unsigned long arg)
1433+{
1434+ int state;
1435+
1436+ if (retu_read_reg(RETU_REG_STATUS) & RETU_STATUS_PWRONX)
1437+ state = PWRBTN_UP;
1438+ else
1439+ state = PWRBTN_PRESSED;
1440+
1441+ if (pwrbtn_state != state) {
1442+ input_report_key(pwrbtn_dev, KEY_POWER, state);
1443+ pwrbtn_state = state;
1444+ }
1445+}
1446+
1447+/**
1448+ * Interrupt function is called whenever power button key is pressed
1449+ * or released.
1450+ */
1451+static void retubutton_irq(unsigned long arg)
1452+{
1453+ retu_ack_irq(RETU_INT_PWR);
1454+ mod_timer(&pwrbtn_timer, jiffies + msecs_to_jiffies(PWRBTN_DELAY));
1455+}
1456+
1457+/**
1458+ * Init function.
1459+ * Allocates interrupt for power button and registers itself to input layer.
1460+ */
1461+static int __init retubutton_init(void)
1462+{
1463+ int irq;
1464+
1465+ printk(KERN_INFO "Retu power button driver initialized\n");
1466+ irq = RETU_INT_PWR;
1467+
1468+ init_timer(&pwrbtn_timer);
1469+ pwrbtn_timer.function = retubutton_timer_func;
1470+
1471+ if (retu_request_irq(irq, &retubutton_irq, 0, "PwrOnX") < 0) {
1472+ printk(KERN_ERR "%s@%s: Cannot allocate irq\n",
1473+ __FUNCTION__, __FILE__);
1474+ return -EBUSY;
1475+ }
1476+
1477+ pwrbtn_dev = input_allocate_device();
1478+ if (!pwrbtn_dev)
1479+ return -ENOMEM;
1480+
1481+ pwrbtn_dev->evbit[0] = BIT_MASK(EV_KEY);
1482+ pwrbtn_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
1483+ pwrbtn_dev->name = "retu-pwrbutton";
1484+
1485+ return input_register_device(pwrbtn_dev);
1486+}
1487+
1488+/**
1489+ * Cleanup function which is called when driver is unloaded
1490+ */
1491+static void __exit retubutton_exit(void)
1492+{
1493+ retu_free_irq(RETU_INT_PWR);
1494+ del_timer_sync(&pwrbtn_timer);
1495+ input_unregister_device(pwrbtn_dev);
1496+}
1497+
1498+module_init(retubutton_init);
1499+module_exit(retubutton_exit);
1500+
1501+MODULE_DESCRIPTION("Retu Power Button");
1502+MODULE_LICENSE("GPL");
1503+MODULE_AUTHOR("Ari Saastamoinen");
1504--- /dev/null
1505@@ -0,0 +1,477 @@
1506+/**
1507+ * drivers/cbus/retu-rtc.c
1508+ *
1509+ * Support for Retu RTC
1510+ *
1511+ * Copyright (C) 2004, 2005 Nokia Corporation
1512+ *
1513+ * Written by Paul Mundt <paul.mundt@nokia.com> and
1514+ * Igor Stoppa <igor.stoppa@nokia.com>
1515+ *
1516+ * The Retu RTC is essentially a partial read-only RTC that gives us Retu's
1517+ * idea of what time actually is. It's left as a userspace excercise to map
1518+ * this back to time in the real world and ensure that calibration settings
1519+ * are sane to compensate for any horrible drift (on account of not being able
1520+ * to set the clock to anything).
1521+ *
1522+ * Days are semi-writeable. Namely, Retu will only track 255 days for us
1523+ * consecutively, after which the counter is explicitly stuck at 255 until
1524+ * someone comes along and clears it with a write. In the event that no one
1525+ * comes along and clears it, we no longer have any idea what day it is.
1526+ *
1527+ * This file is subject to the terms and conditions of the GNU General
1528+ * Public License. See the file "COPYING" in the main directory of this
1529+ * archive for more details.
1530+ *
1531+ * This program is distributed in the hope that it will be useful,
1532+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1533+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1534+ * GNU General Public License for more details.
1535+ *
1536+ * You should have received a copy of the GNU General Public License
1537+ * along with this program; if not, write to the Free Software
1538+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1539+ */
1540+
1541+#include <linux/device.h>
1542+#include <linux/init.h>
1543+#include <linux/kernel.h>
1544+#include <linux/module.h>
1545+#include <linux/completion.h>
1546+#include <linux/platform_device.h>
1547+#include <linux/mutex.h>
1548+#include <linux/workqueue.h>
1549+
1550+#include "cbus.h"
1551+#include "retu.h"
1552+
1553+static struct mutex retu_rtc_mutex;
1554+static u16 retu_rtc_alarm_expired;
1555+static u16 retu_rtc_reset_occurred;
1556+
1557+static DECLARE_COMPLETION(retu_rtc_exited);
1558+static DECLARE_COMPLETION(retu_rtc_sync);
1559+
1560+static void retu_rtc_barrier(void);
1561+
1562+static void retu_rtc_device_release(struct device *dev)
1563+{
1564+ complete(&retu_rtc_exited);
1565+}
1566+
1567+static ssize_t retu_rtc_time_show(struct device *dev, struct device_attribute *attr,
1568+ char *buf)
1569+{
1570+ u16 dsr, hmr, dsr2;
1571+
1572+ mutex_lock(&retu_rtc_mutex);
1573+
1574+ do {
1575+ u16 dummy;
1576+
1577+ /*
1578+ * Not being in_interrupt() for a retu rtc IRQ, we need to
1579+ * read twice for consistency..
1580+ */
1581+ dummy = retu_read_reg(RETU_REG_RTCDSR);
1582+ dsr = retu_read_reg(RETU_REG_RTCDSR);
1583+
1584+ dummy = retu_read_reg(RETU_REG_RTCHMR);
1585+ hmr = retu_read_reg(RETU_REG_RTCHMR);
1586+
1587+ dummy = retu_read_reg(RETU_REG_RTCDSR);
1588+ dsr2 = retu_read_reg(RETU_REG_RTCDSR);
1589+ } while ((dsr != dsr2));
1590+
1591+ mutex_unlock(&retu_rtc_mutex);
1592+
1593+ /*
1594+ * Format a 32-bit date-string for userspace
1595+ *
1596+ * days | hours | minutes | seconds
1597+ *
1598+ * 8 bits for each.
1599+ *
1600+ * This mostly sucks because days and seconds are tracked in RTCDSR
1601+ * while hours and minutes are tracked in RTCHMR. And yes, there
1602+ * really are no words that can describe an 8 bit day register (or
1603+ * rather, none that will be reprinted here).
1604+ */
1605+ return sprintf(buf, "0x%08x\n", (((dsr >> 8) & 0xff) << 24) |
1606+ (((hmr >> 8) & 0x1f) << 16) |
1607+ ((hmr & 0x3f) << 8) | (dsr & 0x3f));
1608+}
1609+
1610+static ssize_t retu_rtc_time_store(struct device *dev, struct device_attribute *attr,
1611+ const char *buf, size_t count)
1612+{
1613+ mutex_lock(&retu_rtc_mutex);
1614+ /*
1615+ * Writing anything to the day counter forces it to 0
1616+ * The seconds counter would be cleared by resetting the minutes counter,
1617+ * however this won't happen, since we are using the hh:mm counters as
1618+ * a set of free running counters and the day counter as a multiple
1619+ * overflow holder.
1620+ */
1621+
1622+ /* Reset day counter, but keep Temperature Shutdown state */
1623+ retu_write_reg(RETU_REG_RTCDSR,
1624+ retu_read_reg(RETU_REG_RTCDSR) & (1 << 6));
1625+
1626+ mutex_unlock(&retu_rtc_mutex);
1627+
1628+ return count;
1629+}
1630+
1631+static DEVICE_ATTR(time, S_IRUGO | S_IWUSR, retu_rtc_time_show,
1632+ retu_rtc_time_store);
1633+
1634+
1635+static ssize_t retu_rtc_reset_show(struct device *dev, struct device_attribute *attr, char *buf)
1636+{
1637+ /*
1638+ * Returns the status of the rtc
1639+ *
1640+ * 0: no reset has occurred or the status has been cleared
1641+ * 1: a reset has occurred
1642+ *
1643+ * RTC needs to be reset only when both main battery
1644+ * _AND_ backup battery are discharged
1645+ */
1646+ return sprintf(buf, "%u\n", retu_rtc_reset_occurred);
1647+}
1648+
1649+static void retu_rtc_do_reset(void)
1650+{
1651+ u16 ccr1;
1652+
1653+ ccr1 = retu_read_reg(RETU_REG_CC1);
1654+ /* RTC in reset */
1655+ retu_write_reg(RETU_REG_CC1, ccr1 | 0x0001);
1656+ /* RTC in normal operating mode */
1657+ retu_write_reg(RETU_REG_CC1, ccr1 & ~0x0001);
1658+
1659+ retu_rtc_barrier();
1660+ /* Disable alarm and RTC WD */
1661+ retu_write_reg(RETU_REG_RTCHMAR, 0x7f3f);
1662+ /* Set Calibration register to default value */
1663+ retu_write_reg(RETU_REG_RTCCALR, 0x00c0);
1664+
1665+ retu_rtc_alarm_expired = 0;
1666+ retu_rtc_reset_occurred = 1;
1667+}
1668+
1669+static ssize_t retu_rtc_reset_store(struct device *dev, struct device_attribute *attr,
1670+ const char *buf, size_t count)
1671+{
1672+ unsigned choice;
1673+
1674+ if(sscanf(buf, "%u", &choice) != 1)
1675+ return count;
1676+ mutex_lock(&retu_rtc_mutex);
1677+ if (choice == 0)
1678+ retu_rtc_reset_occurred = 0;
1679+ else if (choice == 1)
1680+ retu_rtc_do_reset();
1681+ mutex_unlock(&retu_rtc_mutex);
1682+ return count;
1683+}
1684+
1685+static DEVICE_ATTR(reset, S_IRUGO | S_IWUSR, retu_rtc_reset_show,
1686+ retu_rtc_reset_store);
1687+
1688+static ssize_t retu_rtc_alarm_show(struct device *dev, struct device_attribute *attr,
1689+ char *buf)
1690+{
1691+ u16 chmar;
1692+ ssize_t retval;
1693+
1694+ mutex_lock(&retu_rtc_mutex);
1695+ /*
1696+ * Format a 16-bit date-string for userspace
1697+ *
1698+ * hours | minutes
1699+ * 8 bits for each.
1700+ */
1701+ chmar = retu_read_reg(RETU_REG_RTCHMAR);
1702+ /* No shifting needed, only masking unrelated bits */
1703+ retval = sprintf(buf, "0x%04x\n", chmar & 0x1f3f);
1704+ mutex_unlock(&retu_rtc_mutex);
1705+
1706+ return retval;
1707+}
1708+
1709+static ssize_t retu_rtc_alarm_store(struct device *dev, struct device_attribute *attr,
1710+ const char *buf, size_t count)
1711+{
1712+ u16 chmar;
1713+ unsigned alrm;
1714+ unsigned hours;
1715+ unsigned minutes;
1716+
1717+ mutex_lock(&retu_rtc_mutex);
1718+
1719+ if(sscanf(buf, "%x", &alrm) != 1)
1720+ return count;
1721+ hours = (alrm >> 8) & 0x001f;
1722+ minutes = (alrm >> 0) & 0x003f;
1723+ if ((hours < 24 && minutes < 60) || (hours == 24 && minutes == 60)) {
1724+ /*
1725+ * OK, the time format for the alarm is valid (including the
1726+ * disabling values)
1727+ */
1728+ /* Keeps the RTC watchdog status */
1729+ chmar = retu_read_reg(RETU_REG_RTCHMAR) & 0x6000;
1730+ chmar |= alrm & 0x1f3f; /* Stores the requested alarm */
1731+ retu_rtc_barrier();
1732+ retu_write_reg(RETU_REG_RTCHMAR, chmar);
1733+ /* If the alarm is being disabled */
1734+ if (hours == 24 && minutes == 60) {
1735+ /* disable the interrupt */
1736+ retu_disable_irq(RETU_INT_RTCA);
1737+ retu_rtc_alarm_expired = 0;
1738+ } else
1739+ /* enable the interrupt */
1740+ retu_enable_irq(RETU_INT_RTCA);
1741+ }
1742+ mutex_unlock(&retu_rtc_mutex);
1743+
1744+ return count;
1745+}
1746+
1747+static DEVICE_ATTR(alarm, S_IRUGO | S_IWUSR, retu_rtc_alarm_show,
1748+ retu_rtc_alarm_store);
1749+
1750+static ssize_t retu_rtc_alarm_expired_show(struct device *dev, struct device_attribute *attr,
1751+ char *buf)
1752+{
1753+ ssize_t retval;
1754+
1755+ retval = sprintf(buf, "%u\n", retu_rtc_alarm_expired);
1756+
1757+ return retval;
1758+}
1759+
1760+static ssize_t retu_rtc_alarm_expired_store(struct device *dev, struct device_attribute *attr,
1761+ const char *buf, size_t count)
1762+{
1763+ retu_rtc_alarm_expired = 0;
1764+
1765+ return count;
1766+}
1767+
1768+static DEVICE_ATTR(alarm_expired, S_IRUGO | S_IWUSR, retu_rtc_alarm_expired_show,
1769+ retu_rtc_alarm_expired_store);
1770+
1771+
1772+static ssize_t retu_rtc_cal_show(struct device *dev, struct device_attribute *attr,
1773+ char *buf)
1774+{
1775+ u16 rtccalr1;
1776+
1777+ mutex_lock(&retu_rtc_mutex);
1778+ rtccalr1 = retu_read_reg(RETU_REG_RTCCALR);
1779+ mutex_unlock(&retu_rtc_mutex);
1780+
1781+ /*
1782+ * Shows the status of the Calibration Register.
1783+ *
1784+ * Default, after power loss: 0x0000
1785+ * Default, for R&D: 0x00C0
1786+ * Default, for factory: 0x00??
1787+ *
1788+ */
1789+ return sprintf(buf, "0x%04x\n", rtccalr1 & 0x00ff);
1790+}
1791+
1792+static ssize_t retu_rtc_cal_store(struct device *dev, struct device_attribute *attr,
1793+ const char *buf, size_t count)
1794+{
1795+ unsigned calibration_value;
1796+
1797+ if (sscanf(buf, "%x", &calibration_value) != 1)
1798+ return count;
1799+
1800+ mutex_lock(&retu_rtc_mutex);
1801+ retu_rtc_barrier();
1802+ retu_write_reg(RETU_REG_RTCCALR, calibration_value & 0x00ff);
1803+ mutex_unlock(&retu_rtc_mutex);
1804+
1805+ return count;
1806+}
1807+
1808+static DEVICE_ATTR(cal, S_IRUGO | S_IWUSR, retu_rtc_cal_show,
1809+ retu_rtc_cal_store);
1810+
1811+static struct platform_device retu_rtc_device;
1812+
1813+static void retu_rtca_disable(void)
1814+{
1815+ retu_disable_irq(RETU_INT_RTCA);
1816+ retu_rtc_alarm_expired = 1;
1817+ retu_rtc_barrier();
1818+ retu_write_reg(RETU_REG_RTCHMAR, (24 << 8) | 60);
1819+}
1820+
1821+static void retu_rtca_expired(struct work_struct *unused)
1822+{
1823+ retu_rtca_disable();
1824+ sysfs_notify(&retu_rtc_device.dev.kobj, NULL, "alarm_expired");
1825+}
1826+
1827+DECLARE_WORK(retu_rtca_work, retu_rtca_expired);
1828+
1829+/*
1830+ * RTCHMR RTCHMAR RTCCAL must be accessed within 0.9 s since the seconds
1831+ * interrupt has been signaled in the IDR register
1832+ */
1833+static void retu_rtcs_interrupt(unsigned long unused)
1834+{
1835+ retu_ack_irq(RETU_INT_RTCS);
1836+ complete_all(&retu_rtc_sync);
1837+}
1838+
1839+static void retu_rtca_interrupt(unsigned long unused)
1840+{
1841+ retu_ack_irq(RETU_INT_RTCA);
1842+ schedule_work(&retu_rtca_work);
1843+}
1844+
1845+static int retu_rtc_init_irq(void)
1846+{
1847+ int ret;
1848+
1849+ ret = retu_request_irq(RETU_INT_RTCS, retu_rtcs_interrupt, 0, "RTCS");
1850+ if (ret != 0)
1851+ return ret;
1852+ /*
1853+ * We will take care of enabling and disabling the interrupt
1854+ * elsewhere, so leave it off by default..
1855+ */
1856+ retu_disable_irq(RETU_INT_RTCS);
1857+
1858+ ret = retu_request_irq(RETU_INT_RTCA, retu_rtca_interrupt, 0, "RTCA");
1859+ if (ret != 0) {
1860+ retu_free_irq(RETU_INT_RTCS);
1861+ return ret;
1862+ }
1863+ retu_disable_irq(RETU_INT_RTCA);
1864+
1865+ return 0;
1866+}
1867+
1868+
1869+static int __devinit retu_rtc_probe(struct device *dev)
1870+{
1871+ int r;
1872+
1873+ retu_rtc_alarm_expired = retu_read_reg(RETU_REG_IDR) &
1874+ (0x1 << RETU_INT_RTCA);
1875+
1876+ if ((r = retu_rtc_init_irq()) != 0)
1877+ return r;
1878+
1879+ mutex_init(&retu_rtc_mutex);
1880+
1881+ /* If the calibration register is zero, we've probably lost
1882+ * power */
1883+ if (retu_read_reg(RETU_REG_RTCCALR) & 0x00ff)
1884+ retu_rtc_reset_occurred = 0;
1885+ else
1886+ retu_rtc_do_reset();
1887+
1888+ if ((r = device_create_file(dev, &dev_attr_time)) != 0)
1889+ return r;
1890+ else if ((r = device_create_file(dev, &dev_attr_reset)) != 0)
1891+ goto err_unregister_time;
1892+ else if ((r = device_create_file(dev, &dev_attr_alarm)) != 0)
1893+ goto err_unregister_reset;
1894+ else if ((r = device_create_file(dev, &dev_attr_alarm_expired)) != 0)
1895+ goto err_unregister_alarm;
1896+ else if ((r = device_create_file(dev, &dev_attr_cal)) != 0)
1897+ goto err_unregister_alarm_expired;
1898+ else
1899+ return r;
1900+
1901+err_unregister_alarm_expired:
1902+ device_remove_file(dev, &dev_attr_alarm_expired);
1903+err_unregister_alarm:
1904+ device_remove_file(dev, &dev_attr_alarm);
1905+err_unregister_reset:
1906+ device_remove_file(dev, &dev_attr_reset);
1907+err_unregister_time:
1908+ device_remove_file(dev, &dev_attr_time);
1909+ return r;
1910+}
1911+
1912+static int __devexit retu_rtc_remove(struct device *dev)
1913+{
1914+ retu_disable_irq(RETU_INT_RTCS);
1915+ retu_free_irq(RETU_INT_RTCS);
1916+ retu_free_irq(RETU_INT_RTCA);
1917+ device_remove_file(dev, &dev_attr_cal);
1918+ device_remove_file(dev, &dev_attr_alarm_expired);
1919+ device_remove_file(dev, &dev_attr_alarm);
1920+ device_remove_file(dev, &dev_attr_reset);
1921+ device_remove_file(dev, &dev_attr_time);
1922+ return 0;
1923+}
1924+
1925+static struct device_driver retu_rtc_driver = {
1926+ .name = "retu-rtc",
1927+ .bus = &platform_bus_type,
1928+ .probe = retu_rtc_probe,
1929+ .remove = __devexit_p(retu_rtc_remove),
1930+};
1931+
1932+static struct platform_device retu_rtc_device = {
1933+ .name = "retu-rtc",
1934+ .id = -1,
1935+ .dev = {
1936+ .release = retu_rtc_device_release,
1937+ },
1938+};
1939+
1940+/* This function provides syncronization with the RTCS interrupt handler */
1941+static void retu_rtc_barrier(void)
1942+{
1943+ INIT_COMPLETION(retu_rtc_sync);
1944+ retu_ack_irq(RETU_INT_RTCS);
1945+ retu_enable_irq(RETU_INT_RTCS);
1946+ wait_for_completion(&retu_rtc_sync);
1947+ retu_disable_irq(RETU_INT_RTCS);
1948+}
1949+
1950+static int __init retu_rtc_init(void)
1951+{
1952+ int ret;
1953+
1954+ init_completion(&retu_rtc_exited);
1955+
1956+ if ((ret = driver_register(&retu_rtc_driver)) != 0)
1957+ return ret;
1958+
1959+ if ((ret = platform_device_register(&retu_rtc_device)) != 0)
1960+ goto err_unregister_driver;
1961+
1962+ return 0;
1963+
1964+err_unregister_driver:
1965+ driver_unregister(&retu_rtc_driver);
1966+ return ret;
1967+}
1968+
1969+static void __exit retu_rtc_exit(void)
1970+{
1971+ platform_device_unregister(&retu_rtc_device);
1972+ driver_unregister(&retu_rtc_driver);
1973+
1974+ wait_for_completion(&retu_rtc_exited);
1975+}
1976+
1977+module_init(retu_rtc_init);
1978+module_exit(retu_rtc_exit);
1979+
1980+MODULE_DESCRIPTION("Retu RTC");
1981+MODULE_LICENSE("GPL");
1982+MODULE_AUTHOR("Paul Mundt and Igor Stoppa");
1983--- /dev/null
1984@@ -0,0 +1,425 @@
1985+/**
1986+ * drivers/cbus/retu-user.c
1987+ *
1988+ * Retu user space interface functions
1989+ *
1990+ * Copyright (C) 2004, 2005 Nokia Corporation
1991+ *
1992+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
1993+ *
1994+ * This file is subject to the terms and conditions of the GNU General
1995+ * Public License. See the file "COPYING" in the main directory of this
1996+ * archive for more details.
1997+ *
1998+ * This program is distributed in the hope that it will be useful,
1999+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2000+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2001+ * GNU General Public License for more details.
2002+ *
2003+ * You should have received a copy of the GNU General Public License
2004+ * along with this program; if not, write to the Free Software
2005+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2006+ */
2007+
2008+#include <linux/types.h>
2009+#include <linux/kernel.h>
2010+#include <linux/interrupt.h>
2011+#include <linux/module.h>
2012+#include <linux/init.h>
2013+#include <linux/fs.h>
2014+#include <linux/miscdevice.h>
2015+#include <linux/poll.h>
2016+#include <linux/list.h>
2017+#include <linux/spinlock.h>
2018+#include <linux/sched.h>
2019+#include <linux/mutex.h>
2020+#include <linux/slab.h>
2021+
2022+#include <asm/uaccess.h>
2023+
2024+#include "retu.h"
2025+
2026+#include "user_retu_tahvo.h"
2027+
2028+/* Maximum size of IRQ node buffer/pool */
2029+#define RETU_MAX_IRQ_BUF_LEN 16
2030+
2031+#define PFX "retu-user: "
2032+
2033+/* Bitmap for marking the interrupt sources as having the handlers */
2034+static u32 retu_irq_bits;
2035+
2036+/* For allowing only one user process to subscribe to the retu interrupts */
2037+static struct file *retu_irq_subscr = NULL;
2038+
2039+/* For poll and IRQ passing */
2040+struct retu_irq {
2041+ u32 id;
2042+ struct list_head node;
2043+};
2044+
2045+static spinlock_t retu_irqs_lock;
2046+static struct retu_irq *retu_irq_block;
2047+static LIST_HEAD(retu_irqs);
2048+static LIST_HEAD(retu_irqs_reserve);
2049+
2050+/* Wait queue - used when user wants to read the device */
2051+DECLARE_WAIT_QUEUE_HEAD(retu_user_waitqueue);
2052+
2053+/* Semaphore to protect irq subscription sequence */
2054+static struct mutex retu_mutex;
2055+
2056+/* This array specifies RETU register types (read/write/toggle) */
2057+static const u8 retu_access_bits[] = {
2058+ 1,
2059+ 4,
2060+ 3,
2061+ 3,
2062+ 1,
2063+ 3,
2064+ 3,
2065+ 0,
2066+ 3,
2067+ 3,
2068+ 3,
2069+ 3,
2070+ 3,
2071+ 3,
2072+ 3,
2073+ 4,
2074+ 4,
2075+ 3,
2076+ 0,
2077+ 0,
2078+ 0,
2079+ 0,
2080+ 1,
2081+ 3,
2082+ 3,
2083+ 3,
2084+ 3,
2085+ 3,
2086+ 3,
2087+ 3,
2088+ 3,
2089+ 3
2090+};
2091+
2092+/*
2093+ * The handler for all RETU interrupts.
2094+ *
2095+ * arg is the interrupt source in RETU.
2096+ */
2097+static void retu_user_irq_handler(unsigned long arg)
2098+{
2099+ struct retu_irq *irq;
2100+
2101+ retu_ack_irq(arg);
2102+
2103+ spin_lock(&retu_irqs_lock);
2104+ if (list_empty(&retu_irqs_reserve)) {
2105+ spin_unlock(&retu_irqs_lock);
2106+ return;
2107+ }
2108+ irq = list_entry((&retu_irqs_reserve)->next, struct retu_irq, node);
2109+ irq->id = arg;
2110+ list_move_tail(&irq->node, &retu_irqs);
2111+ spin_unlock(&retu_irqs_lock);
2112+
2113+ /* wake up waiting thread */
2114+ wake_up(&retu_user_waitqueue);
2115+}
2116+
2117+/*
2118+ * This routine sets up the interrupt handler and marks an interrupt source
2119+ * in RETU as a candidate for signal delivery to the user process.
2120+ */
2121+static int retu_user_subscribe_to_irq(int id, struct file *filp)
2122+{
2123+ int ret;
2124+
2125+ mutex_lock(&retu_mutex);
2126+ if ((retu_irq_subscr != NULL) && (retu_irq_subscr != filp)) {
2127+ mutex_unlock(&retu_mutex);
2128+ return -EBUSY;
2129+ }
2130+ /* Store the file pointer of the first user process registering IRQs */
2131+ retu_irq_subscr = filp;
2132+ mutex_unlock(&retu_mutex);
2133+
2134+ if (retu_irq_bits & (1 << id))
2135+ return 0;
2136+
2137+ ret = retu_request_irq(id, retu_user_irq_handler, id, "");
2138+ if (ret < 0)
2139+ return ret;
2140+
2141+ /* Mark that this interrupt has a handler */
2142+ retu_irq_bits |= 1 << id;
2143+
2144+ return 0;
2145+}
2146+
2147+/*
2148+ * Unregisters all RETU interrupt handlers.
2149+ */
2150+static void retu_unreg_irq_handlers(void)
2151+{
2152+ int id;
2153+
2154+ if (!retu_irq_bits)
2155+ return;
2156+
2157+ for (id = 0; id < MAX_RETU_IRQ_HANDLERS; id++)
2158+ if (retu_irq_bits & (1 << id))
2159+ retu_free_irq(id);
2160+
2161+ retu_irq_bits = 0;
2162+}
2163+
2164+/*
2165+ * Write to RETU register.
2166+ * Returns 0 upon success, a negative error value otherwise.
2167+ */
2168+static int retu_user_write_with_mask(u32 field, u16 value)
2169+{
2170+ u32 mask;
2171+ u32 reg;
2172+ u_short tmp;
2173+ unsigned long flags;
2174+
2175+ mask = MASK(field);
2176+ reg = REG(field);
2177+
2178+ /* Detect bad mask and reg */
2179+ if (mask == 0 || reg > RETU_REG_MAX ||
2180+ retu_access_bits[reg] == READ_ONLY) {
2181+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
2182+ reg, mask);
2183+ return -EINVAL;
2184+ }
2185+
2186+ /* Justify value according to mask */
2187+ while (!(mask & 1)) {
2188+ value = value << 1;
2189+ mask = mask >> 1;
2190+ }
2191+
2192+ spin_lock_irqsave(&retu_lock, flags);
2193+ if (retu_access_bits[reg] == TOGGLE) {
2194+ /* No need to detect previous content of register */
2195+ tmp = 0;
2196+ } else {
2197+ /* Read current value of register */
2198+ tmp = retu_read_reg(reg);
2199+ }
2200+
2201+ /* Generate new value */
2202+ tmp = (tmp & ~MASK(field)) | (value & MASK(field));
2203+ /* Write data to RETU */
2204+ retu_write_reg(reg, tmp);
2205+ spin_unlock_irqrestore(&retu_lock, flags);
2206+
2207+ return 0;
2208+}
2209+
2210+/*
2211+ * Read RETU register.
2212+ */
2213+static u32 retu_user_read_with_mask(u32 field)
2214+{
2215+ u_short value;
2216+ u32 mask, reg;
2217+
2218+ mask = MASK(field);
2219+ reg = REG(field);
2220+
2221+ /* Detect bad mask and reg */
2222+ if (mask == 0 || reg > RETU_REG_MAX) {
2223+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
2224+ reg, mask);
2225+ return -EINVAL;
2226+ }
2227+
2228+ /* Read the register */
2229+ value = retu_read_reg(reg) & mask;
2230+
2231+ /* Right justify value */
2232+ while (!(mask & 1)) {
2233+ value = value >> 1;
2234+ mask = mask >> 1;
2235+ }
2236+
2237+ return value;
2238+}
2239+
2240+/*
2241+ * Close device
2242+ */
2243+static int retu_close(struct inode *inode, struct file *filp)
2244+{
2245+ /* Unregister all interrupts that have been registered */
2246+ if (retu_irq_subscr == filp) {
2247+ retu_unreg_irq_handlers();
2248+ retu_irq_subscr = NULL;
2249+ }
2250+
2251+ return 0;
2252+}
2253+
2254+/*
2255+ * Device control (ioctl)
2256+ */
2257+static int retu_ioctl(struct inode *inode, struct file *filp,
2258+ unsigned int cmd, unsigned long arg)
2259+{
2260+ struct retu_tahvo_write_parms par;
2261+ int ret;
2262+
2263+ switch (cmd) {
2264+ case URT_IOCT_IRQ_SUBSCR:
2265+ return retu_user_subscribe_to_irq(arg, filp);
2266+ case RETU_IOCH_READ:
2267+ return retu_user_read_with_mask(arg);
2268+ case RETU_IOCX_WRITE:
2269+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
2270+ if (ret)
2271+ printk(KERN_ERR "copy_from_user failed: %d\n", ret);
2272+ par.result = retu_user_write_with_mask(par.field, par.value);
2273+ ret = copy_to_user((void __user *) arg, &par, sizeof(par));
2274+ if (ret)
2275+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
2276+ break;
2277+ case RETU_IOCH_ADC_READ:
2278+ return retu_read_adc(arg);
2279+ default:
2280+ return -ENOIOCTLCMD;
2281+ }
2282+ return 0;
2283+}
2284+
2285+/*
2286+ * Read from device
2287+ */
2288+static ssize_t retu_read(struct file *filp, char *buf, size_t count,
2289+ loff_t * offp)
2290+{
2291+ struct retu_irq *irq;
2292+
2293+ u32 nr, i;
2294+
2295+ /* read not permitted if neither filp nor anyone has registered IRQs */
2296+ if (retu_irq_subscr != filp)
2297+ return -EPERM;
2298+
2299+ if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0))
2300+ return -EINVAL;
2301+
2302+ nr = count / sizeof(u32);
2303+
2304+ for (i = 0; i < nr; i++) {
2305+ unsigned long flags;
2306+ u32 irq_id;
2307+ int ret;
2308+
2309+ ret = wait_event_interruptible(retu_user_waitqueue,
2310+ !list_empty(&retu_irqs));
2311+ if (ret < 0)
2312+ return ret;
2313+
2314+ spin_lock_irqsave(&retu_irqs_lock, flags);
2315+ irq = list_entry((&retu_irqs)->next, struct retu_irq, node);
2316+ irq_id = irq->id;
2317+ list_move(&irq->node, &retu_irqs_reserve);
2318+ spin_unlock_irqrestore(&retu_irqs_lock, flags);
2319+
2320+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
2321+ sizeof(irq_id));
2322+ if (ret)
2323+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
2324+ }
2325+
2326+ return count;
2327+}
2328+
2329+/*
2330+ * Poll method
2331+ */
2332+static unsigned retu_poll(struct file *filp, struct poll_table_struct *pt)
2333+{
2334+ if (!list_empty(&retu_irqs))
2335+ return POLLIN;
2336+
2337+ poll_wait(filp, &retu_user_waitqueue, pt);
2338+
2339+ if (!list_empty(&retu_irqs))
2340+ return POLLIN;
2341+ else
2342+ return 0;
2343+}
2344+
2345+static struct file_operations retu_user_fileops = {
2346+ .owner = THIS_MODULE,
2347+ .ioctl = retu_ioctl,
2348+ .read = retu_read,
2349+ .release = retu_close,
2350+ .poll = retu_poll
2351+};
2352+
2353+static struct miscdevice retu_device = {
2354+ .minor = MISC_DYNAMIC_MINOR,
2355+ .name = "retu",
2356+ .fops = &retu_user_fileops
2357+};
2358+
2359+/*
2360+ * Initialization
2361+ *
2362+ * @return 0 if successful, error value otherwise.
2363+ */
2364+int retu_user_init(void)
2365+{
2366+ struct retu_irq *irq;
2367+ int res, i;
2368+
2369+ irq = kmalloc(sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN, GFP_KERNEL);
2370+ if (irq == NULL) {
2371+ printk(KERN_ERR PFX "kmalloc failed\n");
2372+ return -ENOMEM;
2373+ }
2374+ memset(irq, 0, sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN);
2375+ for (i = 0; i < RETU_MAX_IRQ_BUF_LEN; i++)
2376+ list_add(&irq[i].node, &retu_irqs_reserve);
2377+
2378+ retu_irq_block = irq;
2379+
2380+ spin_lock_init(&retu_irqs_lock);
2381+ mutex_init(&retu_mutex);
2382+
2383+ /* Request a misc device */
2384+ res = misc_register(&retu_device);
2385+ if (res < 0) {
2386+ printk(KERN_ERR PFX "unable to register misc device for %s\n",
2387+ retu_device.name);
2388+ kfree(irq);
2389+ return res;
2390+ }
2391+
2392+ return 0;
2393+}
2394+
2395+/*
2396+ * Cleanup.
2397+ */
2398+void retu_user_cleanup(void)
2399+{
2400+ /* Unregister our misc device */
2401+ misc_deregister(&retu_device);
2402+ /* Unregister and disable all RETU interrupts used by this module */
2403+ retu_unreg_irq_handlers();
2404+ kfree(retu_irq_block);
2405+}
2406+
2407+MODULE_DESCRIPTION("Retu ASIC user space functions");
2408+MODULE_LICENSE("GPL");
2409+MODULE_AUTHOR("Mikko Ylinen");
2410--- /dev/null
2411@@ -0,0 +1,388 @@
2412+/**
2413+ * drivers/cbus/retu-wdt.c
2414+ *
2415+ * Driver for Retu watchdog
2416+ *
2417+ * Copyright (C) 2004, 2005 Nokia Corporation
2418+ *
2419+ * Written by Amit Kucheria <amit.kucheria@nokia.com>
2420+ *
2421+ * This file is subject to the terms and conditions of the GNU General
2422+ * Public License. See the file "COPYING" in the main directory of this
2423+ * archive for more details.
2424+ *
2425+ * This program is distributed in the hope that it will be useful,
2426+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2427+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2428+ * GNU General Public License for more details.
2429+ *
2430+ * You should have received a copy of the GNU General Public License
2431+ * along with this program; if not, write to the Free Software
2432+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2433+ */
2434+
2435+#include <linux/kernel.h>
2436+#include <linux/module.h>
2437+#include <linux/device.h>
2438+#include <linux/init.h>
2439+#include <linux/fs.h>
2440+#include <linux/io.h>
2441+#include <linux/platform_device.h>
2442+#include <linux/slab.h>
2443+
2444+#include <linux/completion.h>
2445+#include <linux/errno.h>
2446+#include <linux/moduleparam.h>
2447+#include <linux/platform_device.h>
2448+#include <linux/miscdevice.h>
2449+#include <linux/watchdog.h>
2450+
2451+#include <asm/uaccess.h>
2452+
2453+#include <plat/prcm.h>
2454+
2455+#include "cbus.h"
2456+#include "retu.h"
2457+
2458+/* Watchdog timeout in seconds */
2459+#define RETU_WDT_MIN_TIMER 0
2460+#define RETU_WDT_DEFAULT_TIMER 32
2461+#define RETU_WDT_MAX_TIMER 63
2462+
2463+static struct completion retu_wdt_completion;
2464+static DEFINE_MUTEX(retu_wdt_mutex);
2465+
2466+/* Current period of watchdog */
2467+static unsigned int period_val = RETU_WDT_DEFAULT_TIMER;
2468+static int counter_param = RETU_WDT_MAX_TIMER;
2469+
2470+struct retu_wdt_dev {
2471+ struct device *dev;
2472+ int users;
2473+ struct miscdevice retu_wdt_miscdev;
2474+ struct timer_list ping_timer;
2475+};
2476+
2477+static struct retu_wdt_dev *retu_wdt;
2478+
2479+static void retu_wdt_set_ping_timer(unsigned long enable);
2480+
2481+static int _retu_modify_counter(unsigned int new)
2482+{
2483+ retu_write_reg(RETU_REG_WATCHDOG, (u16)new);
2484+
2485+ return 0;
2486+}
2487+
2488+static int retu_modify_counter(unsigned int new)
2489+{
2490+ if (new < RETU_WDT_MIN_TIMER || new > RETU_WDT_MAX_TIMER)
2491+ return -EINVAL;
2492+
2493+ mutex_lock(&retu_wdt_mutex);
2494+ period_val = new;
2495+ _retu_modify_counter(period_val);
2496+ mutex_unlock(&retu_wdt_mutex);
2497+
2498+ return 0;
2499+}
2500+
2501+static ssize_t retu_wdt_period_show(struct device *dev,
2502+ struct device_attribute *attr, char *buf)
2503+{
2504+ /* Show current max counter */
2505+ return sprintf(buf, "%u\n", (u16)period_val);
2506+}
2507+
2508+/*
2509+ * Note: This inteface is non-standard and likely to disappear!
2510+ * Use /dev/watchdog instead, that's the standard.
2511+ */
2512+static ssize_t retu_wdt_period_store(struct device *dev,
2513+ struct device_attribute *attr,
2514+ const char *buf, size_t count)
2515+{
2516+ unsigned int new_period;
2517+ int ret;
2518+
2519+#ifdef CONFIG_WATCHDOG_NOWAYOUT
2520+ retu_wdt_set_ping_timer(0);
2521+#endif
2522+
2523+ if (sscanf(buf, "%u", &new_period) != 1) {
2524+ printk(KERN_ALERT "retu_wdt_period_store: Invalid input\n");
2525+ return -EINVAL;
2526+ }
2527+
2528+ ret = retu_modify_counter(new_period);
2529+ if (ret < 0)
2530+ return ret;
2531+
2532+ return strnlen(buf, count);
2533+}
2534+
2535+static ssize_t retu_wdt_counter_show(struct device *dev,
2536+ struct device_attribute *attr, char *buf)
2537+{
2538+ u16 counter;
2539+
2540+ /* Show current value in watchdog counter */
2541+ counter = retu_read_reg(RETU_REG_WATCHDOG);
2542+
2543+ /* Only the 5 LSB are important */
2544+ return snprintf(buf, PAGE_SIZE, "%u\n", (counter & 0x3F));
2545+}
2546+
2547+static DEVICE_ATTR(period, S_IRUGO | S_IWUSR, retu_wdt_period_show, \
2548+ retu_wdt_period_store);
2549+static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL);
2550+
2551+/*----------------------------------------------------------------------------*/
2552+
2553+/*
2554+ * Since retu watchdog cannot be disabled in hardware, we must kick it
2555+ * with a timer until userspace watchdog software takes over. Do this
2556+ * unless /dev/watchdog is open or CONFIG_WATCHDOG_NOWAYOUT is set.
2557+ */
2558+static void retu_wdt_set_ping_timer(unsigned long enable)
2559+{
2560+ _retu_modify_counter(RETU_WDT_MAX_TIMER);
2561+ if (enable)
2562+ mod_timer(&retu_wdt->ping_timer,
2563+ jiffies + RETU_WDT_DEFAULT_TIMER * HZ);
2564+ else
2565+ del_timer_sync(&retu_wdt->ping_timer);
2566+}
2567+
2568+static int retu_wdt_open(struct inode *inode, struct file *file)
2569+{
2570+ if (test_and_set_bit(1, (unsigned long *)&(retu_wdt->users)))
2571+ return -EBUSY;
2572+
2573+ file->private_data = (void *)retu_wdt;
2574+ retu_wdt_set_ping_timer(0);
2575+
2576+ return nonseekable_open(inode, file);
2577+}
2578+
2579+static int retu_wdt_release(struct inode *inode, struct file *file)
2580+{
2581+ struct retu_wdt_dev *wdev = file->private_data;
2582+
2583+#ifndef CONFIG_WATCHDOG_NOWAYOUT
2584+ retu_wdt_set_ping_timer(1);
2585+#endif
2586+ wdev->users = 0;
2587+
2588+ return 0;
2589+}
2590+
2591+static ssize_t retu_wdt_write(struct file *file, const char __user *data,
2592+ size_t len, loff_t *ppos)
2593+{
2594+ if (len)
2595+ retu_modify_counter(RETU_WDT_MAX_TIMER);
2596+
2597+ return len;
2598+}
2599+
2600+static int retu_wdt_ioctl(struct inode *inode, struct file *file,
2601+ unsigned int cmd, unsigned long arg)
2602+{
2603+ int new_margin;
2604+
2605+ static struct watchdog_info ident = {
2606+ .identity = "Retu Watchdog",
2607+ .options = WDIOF_SETTIMEOUT,
2608+ .firmware_version = 0,
2609+ };
2610+
2611+ switch (cmd) {
2612+ default:
2613+ return -ENOTTY;
2614+ case WDIOC_GETSUPPORT:
2615+ return copy_to_user((struct watchdog_info __user *)arg, &ident,
2616+ sizeof(ident));
2617+ case WDIOC_GETSTATUS:
2618+ return put_user(0, (int __user *)arg);
2619+ case WDIOC_GETBOOTSTATUS:
2620+ if (cpu_is_omap16xx())
2621+ return put_user(omap_readw(ARM_SYSST),
2622+ (int __user *)arg);
2623+ if (cpu_is_omap24xx())
2624+ return put_user(omap_prcm_get_reset_sources(),
2625+ (int __user *)arg);
2626+ case WDIOC_KEEPALIVE:
2627+ retu_modify_counter(RETU_WDT_MAX_TIMER);
2628+ break;
2629+ case WDIOC_SETTIMEOUT:
2630+ if (get_user(new_margin, (int __user *)arg))
2631+ return -EFAULT;
2632+ retu_modify_counter(new_margin);
2633+ /* Fall through */
2634+ case WDIOC_GETTIMEOUT:
2635+ return put_user(period_val, (int __user *)arg);
2636+ }
2637+
2638+ return 0;
2639+}
2640+
2641+/* Start kicking retu watchdog until user space starts doing the kicking */
2642+static int __init retu_wdt_ping(void)
2643+{
2644+
2645+#ifdef CONFIG_WATCHDOG_NOWAYOUT
2646+ retu_modify_counter(RETU_WDT_MAX_TIMER);
2647+#else
2648+ retu_wdt_set_ping_timer(1);
2649+#endif
2650+
2651+ return 0;
2652+}
2653+late_initcall(retu_wdt_ping);
2654+
2655+static const struct file_operations retu_wdt_fops = {
2656+ .owner = THIS_MODULE,
2657+ .write = retu_wdt_write,
2658+ .ioctl = retu_wdt_ioctl,
2659+ .open = retu_wdt_open,
2660+ .release = retu_wdt_release,
2661+};
2662+
2663+/*----------------------------------------------------------------------------*/
2664+
2665+static int __devinit retu_wdt_probe(struct device *dev)
2666+{
2667+ struct retu_wdt_dev *wdev;
2668+ int ret;
2669+
2670+ wdev = kzalloc(sizeof(struct retu_wdt_dev), GFP_KERNEL);
2671+ if (!wdev)
2672+ return -ENOMEM;
2673+
2674+ wdev->users = 0;
2675+
2676+ ret = device_create_file(dev, &dev_attr_period);
2677+ if (ret) {
2678+ printk(KERN_ERR "retu_wdt_probe: Error creating "
2679+ "sys device file: period\n");
2680+ goto free1;
2681+ }
2682+
2683+ ret = device_create_file(dev, &dev_attr_counter);
2684+ if (ret) {
2685+ printk(KERN_ERR "retu_wdt_probe: Error creating "
2686+ "sys device file: counter\n");
2687+ goto free2;
2688+ }
2689+
2690+ dev_set_drvdata(dev, wdev);
2691+ retu_wdt = wdev;
2692+ wdev->retu_wdt_miscdev.parent = dev;
2693+ wdev->retu_wdt_miscdev.minor = WATCHDOG_MINOR;
2694+ wdev->retu_wdt_miscdev.name = "watchdog";
2695+ wdev->retu_wdt_miscdev.fops = &retu_wdt_fops;
2696+
2697+ ret = misc_register(&(wdev->retu_wdt_miscdev));
2698+ if (ret)
2699+ goto free3;
2700+
2701+ setup_timer(&wdev->ping_timer, retu_wdt_set_ping_timer, 1);
2702+
2703+ /* Kick the watchdog for kernel booting to finish */
2704+ retu_modify_counter(RETU_WDT_MAX_TIMER);
2705+
2706+ return 0;
2707+
2708+free3:
2709+ device_remove_file(dev, &dev_attr_counter);
2710+
2711+free2:
2712+ device_remove_file(dev, &dev_attr_period);
2713+free1:
2714+ kfree(wdev);
2715+
2716+ return ret;
2717+}
2718+
2719+static int __devexit retu_wdt_remove(struct device *dev)
2720+{
2721+ struct retu_wdt_dev *wdev;
2722+
2723+ wdev = dev_get_drvdata(dev);
2724+ misc_deregister(&(wdev->retu_wdt_miscdev));
2725+ device_remove_file(dev, &dev_attr_period);
2726+ device_remove_file(dev, &dev_attr_counter);
2727+ kfree(wdev);
2728+
2729+ return 0;
2730+}
2731+
2732+static void retu_wdt_device_release(struct device *dev)
2733+{
2734+ complete(&retu_wdt_completion);
2735+}
2736+
2737+static struct platform_device retu_wdt_device = {
2738+ .name = "retu-watchdog",
2739+ .id = -1,
2740+ .dev = {
2741+ .release = retu_wdt_device_release,
2742+ },
2743+};
2744+
2745+static struct device_driver retu_wdt_driver = {
2746+ .name = "retu-watchdog",
2747+ .bus = &platform_bus_type,
2748+ .probe = retu_wdt_probe,
2749+ .remove = __devexit_p(retu_wdt_remove),
2750+};
2751+
2752+static int __init retu_wdt_init(void)
2753+{
2754+ int ret;
2755+
2756+ init_completion(&retu_wdt_completion);
2757+
2758+ ret = driver_register(&retu_wdt_driver);
2759+ if (ret)
2760+ return ret;
2761+
2762+ ret = platform_device_register(&retu_wdt_device);
2763+ if (ret)
2764+ goto exit1;
2765+
2766+ /* passed as module parameter? */
2767+ ret = retu_modify_counter(counter_param);
2768+ if (ret == -EINVAL) {
2769+ ret = retu_modify_counter(RETU_WDT_DEFAULT_TIMER);
2770+ printk(KERN_INFO
2771+ "retu_wdt_init: Intializing to default value\n");
2772+ }
2773+
2774+ printk(KERN_INFO "Retu watchdog driver initialized\n");
2775+ return ret;
2776+
2777+exit1:
2778+ driver_unregister(&retu_wdt_driver);
2779+ wait_for_completion(&retu_wdt_completion);
2780+
2781+ return ret;
2782+}
2783+
2784+static void __exit retu_wdt_exit(void)
2785+{
2786+ platform_device_unregister(&retu_wdt_device);
2787+ driver_unregister(&retu_wdt_driver);
2788+
2789+ wait_for_completion(&retu_wdt_completion);
2790+}
2791+
2792+module_init(retu_wdt_init);
2793+module_exit(retu_wdt_exit);
2794+module_param(counter_param, int, 0);
2795+
2796+MODULE_DESCRIPTION("Retu WatchDog");
2797+MODULE_AUTHOR("Amit Kucheria");
2798+MODULE_LICENSE("GPL");
2799+
2800--- /dev/null
2801@@ -0,0 +1,443 @@
2802+/**
2803+ * drivers/cbus/tahvo.c
2804+ *
2805+ * Support functions for Tahvo ASIC
2806+ *
2807+ * Copyright (C) 2004, 2005 Nokia Corporation
2808+ *
2809+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
2810+ * David Weinehall <david.weinehall@nokia.com>, and
2811+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
2812+ *
2813+ * This file is subject to the terms and conditions of the GNU General
2814+ * Public License. See the file "COPYING" in the main directory of this
2815+ * archive for more details.
2816+ *
2817+ * This program is distributed in the hope that it will be useful,
2818+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2819+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2820+ * GNU General Public License for more details.
2821+ *
2822+ * You should have received a copy of the GNU General Public License
2823+ * along with this program; if not, write to the Free Software
2824+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2825+ */
2826+
2827+#include <linux/module.h>
2828+#include <linux/init.h>
2829+
2830+#include <linux/kernel.h>
2831+#include <linux/errno.h>
2832+#include <linux/device.h>
2833+#include <linux/miscdevice.h>
2834+#include <linux/poll.h>
2835+#include <linux/fs.h>
2836+#include <linux/irq.h>
2837+#include <linux/interrupt.h>
2838+#include <linux/platform_device.h>
2839+#include <linux/gpio.h>
2840+
2841+#include <asm/uaccess.h>
2842+#include <asm/mach-types.h>
2843+
2844+#include <plat/mux.h>
2845+#include <plat/board.h>
2846+
2847+#include "cbus.h"
2848+#include "tahvo.h"
2849+
2850+#define TAHVO_ID 0x02
2851+#define PFX "tahvo: "
2852+
2853+static int tahvo_initialized;
2854+static int tahvo_irq_pin;
2855+static int tahvo_is_betty;
2856+
2857+static struct tasklet_struct tahvo_tasklet;
2858+spinlock_t tahvo_lock = SPIN_LOCK_UNLOCKED;
2859+
2860+static struct completion device_release;
2861+
2862+struct tahvo_irq_handler_desc {
2863+ int (*func)(unsigned long);
2864+ unsigned long arg;
2865+ char name[8];
2866+};
2867+
2868+static struct tahvo_irq_handler_desc tahvo_irq_handlers[MAX_TAHVO_IRQ_HANDLERS];
2869+
2870+/**
2871+ * tahvo_read_reg - Read a value from a register in Tahvo
2872+ * @reg: the register to read from
2873+ *
2874+ * This function returns the contents of the specified register
2875+ */
2876+int tahvo_read_reg(int reg)
2877+{
2878+ BUG_ON(!tahvo_initialized);
2879+ return cbus_read_reg(cbus_host, TAHVO_ID, reg);
2880+}
2881+
2882+/**
2883+ * tahvo_write_reg - Write a value to a register in Tahvo
2884+ * @reg: the register to write to
2885+ * @reg: the value to write to the register
2886+ *
2887+ * This function writes a value to the specified register
2888+ */
2889+void tahvo_write_reg(int reg, u16 val)
2890+{
2891+ BUG_ON(!tahvo_initialized);
2892+ cbus_write_reg(cbus_host, TAHVO_ID, reg, val);
2893+}
2894+
2895+/**
2896+ * tahvo_set_clear_reg_bits - set and clear register bits atomically
2897+ * @reg: the register to write to
2898+ * @bits: the bits to set
2899+ *
2900+ * This function sets and clears the specified Tahvo register bits atomically
2901+ */
2902+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear)
2903+{
2904+ unsigned long flags;
2905+ u16 w;
2906+
2907+ spin_lock_irqsave(&tahvo_lock, flags);
2908+ w = tahvo_read_reg(reg);
2909+ w &= ~clear;
2910+ w |= set;
2911+ tahvo_write_reg(reg, w);
2912+ spin_unlock_irqrestore(&tahvo_lock, flags);
2913+}
2914+
2915+/*
2916+ * Disable given TAHVO interrupt
2917+ */
2918+void tahvo_disable_irq(int id)
2919+{
2920+ unsigned long flags;
2921+ u16 mask;
2922+
2923+ spin_lock_irqsave(&tahvo_lock, flags);
2924+ mask = tahvo_read_reg(TAHVO_REG_IMR);
2925+ mask |= 1 << id;
2926+ tahvo_write_reg(TAHVO_REG_IMR, mask);
2927+ spin_unlock_irqrestore(&tahvo_lock, flags);
2928+}
2929+
2930+/*
2931+ * Enable given TAHVO interrupt
2932+ */
2933+void tahvo_enable_irq(int id)
2934+{
2935+ unsigned long flags;
2936+ u16 mask;
2937+
2938+ spin_lock_irqsave(&tahvo_lock, flags);
2939+ mask = tahvo_read_reg(TAHVO_REG_IMR);
2940+ mask &= ~(1 << id);
2941+ tahvo_write_reg(TAHVO_REG_IMR, mask);
2942+ spin_unlock_irqrestore(&tahvo_lock, flags);
2943+}
2944+
2945+/*
2946+ * Acknowledge given TAHVO interrupt
2947+ */
2948+void tahvo_ack_irq(int id)
2949+{
2950+ tahvo_write_reg(TAHVO_REG_IDR, 1 << id);
2951+}
2952+
2953+static int tahvo_7bit_backlight;
2954+
2955+int tahvo_get_backlight_level(void)
2956+{
2957+ int mask;
2958+
2959+ if (tahvo_7bit_backlight)
2960+ mask = 0x7f;
2961+ else
2962+ mask = 0x0f;
2963+ return tahvo_read_reg(TAHVO_REG_LEDPWMR) & mask;
2964+}
2965+
2966+int tahvo_get_max_backlight_level(void)
2967+{
2968+ if (tahvo_7bit_backlight)
2969+ return 0x7f;
2970+ else
2971+ return 0x0f;
2972+}
2973+
2974+void tahvo_set_backlight_level(int level)
2975+{
2976+ int max_level;
2977+
2978+ max_level = tahvo_get_max_backlight_level();
2979+ if (level > max_level)
2980+ level = max_level;
2981+ tahvo_write_reg(TAHVO_REG_LEDPWMR, level);
2982+}
2983+
2984+/*
2985+ * TAHVO interrupt handler. Only schedules the tasklet.
2986+ */
2987+static irqreturn_t tahvo_irq_handler(int irq, void *dev_id)
2988+{
2989+ tasklet_schedule(&tahvo_tasklet);
2990+ return IRQ_HANDLED;
2991+}
2992+
2993+/*
2994+ * Tasklet handler
2995+ */
2996+static void tahvo_tasklet_handler(unsigned long data)
2997+{
2998+ struct tahvo_irq_handler_desc *hnd;
2999+ u16 id;
3000+ u16 im;
3001+ int i;
3002+
3003+ for (;;) {
3004+ id = tahvo_read_reg(TAHVO_REG_IDR);
3005+ im = ~tahvo_read_reg(TAHVO_REG_IMR);
3006+ id &= im;
3007+
3008+ if (!id)
3009+ break;
3010+
3011+ for (i = 0; id != 0; i++, id >>= 1) {
3012+ if (!(id & 1))
3013+ continue;
3014+ hnd = &tahvo_irq_handlers[i];
3015+ if (hnd->func == NULL) {
3016+ /* Spurious tahvo interrupt - just ack it */
3017+ printk(KERN_INFO "Spurious Tahvo interrupt "
3018+ "(id %d)\n", i);
3019+ tahvo_disable_irq(i);
3020+ tahvo_ack_irq(i);
3021+ continue;
3022+ }
3023+ hnd->func(hnd->arg);
3024+ /*
3025+ * Don't acknowledge the interrupt here
3026+ * It must be done explicitly
3027+ */
3028+ }
3029+ }
3030+}
3031+
3032+/*
3033+ * Register the handler for a given TAHVO interrupt source.
3034+ */
3035+int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name)
3036+{
3037+ struct tahvo_irq_handler_desc *hnd;
3038+
3039+ if (irq_handler == NULL || id >= MAX_TAHVO_IRQ_HANDLERS ||
3040+ name == NULL) {
3041+ printk(KERN_ERR PFX "Invalid arguments to %s\n",
3042+ __FUNCTION__);
3043+ return -EINVAL;
3044+ }
3045+ hnd = &tahvo_irq_handlers[id];
3046+ if (hnd->func != NULL) {
3047+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
3048+ return -EBUSY;
3049+ }
3050+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
3051+ id, name);
3052+ hnd->func = irq_handler;
3053+ hnd->arg = arg;
3054+ strlcpy(hnd->name, name, sizeof(hnd->name));
3055+
3056+ tahvo_ack_irq(id);
3057+ tahvo_enable_irq(id);
3058+
3059+ return 0;
3060+}
3061+
3062+/*
3063+ * Unregister the handler for a given TAHVO interrupt source.
3064+ */
3065+void tahvo_free_irq(int id)
3066+{
3067+ struct tahvo_irq_handler_desc *hnd;
3068+
3069+ if (id >= MAX_TAHVO_IRQ_HANDLERS) {
3070+ printk(KERN_ERR PFX "Invalid argument to %s\n",
3071+ __FUNCTION__);
3072+ return;
3073+ }
3074+ hnd = &tahvo_irq_handlers[id];
3075+ if (hnd->func == NULL) {
3076+ printk(KERN_ERR PFX "IRQ %d already freed\n", id);
3077+ return;
3078+ }
3079+
3080+ tahvo_disable_irq(id);
3081+ hnd->func = NULL;
3082+}
3083+
3084+/**
3085+ * tahvo_probe - Probe for Tahvo ASIC
3086+ * @dev: the Tahvo device
3087+ *
3088+ * Probe for the Tahvo ASIC and allocate memory
3089+ * for its device-struct if found
3090+ */
3091+static int __devinit tahvo_probe(struct device *dev)
3092+{
3093+ int rev, id, ret;
3094+
3095+ /* Prepare tasklet */
3096+ tasklet_init(&tahvo_tasklet, tahvo_tasklet_handler, 0);
3097+
3098+ tahvo_initialized = 1;
3099+
3100+ rev = tahvo_read_reg(TAHVO_REG_ASICR);
3101+
3102+ id = (rev >> 8) & 0xff;
3103+ if (id == 0x03) {
3104+ if ((rev & 0xff) >= 0x50)
3105+ tahvo_7bit_backlight = 1;
3106+ } else if (id == 0x0b) {
3107+ tahvo_is_betty = 1;
3108+ tahvo_7bit_backlight = 1;
3109+ } else {
3110+ printk(KERN_ERR "Tahvo/Betty chip not found");
3111+ return -ENODEV;
3112+ }
3113+
3114+ printk(KERN_INFO "%s v%d.%d found\n", tahvo_is_betty ? "Betty" : "Tahvo",
3115+ (rev >> 4) & 0x0f, rev & 0x0f);
3116+
3117+ /* REVISIT: Pass these from board-*.c files in platform_data */
3118+ if (machine_is_nokia770()) {
3119+ tahvo_irq_pin = 40;
3120+ } else if (machine_is_nokia_n800() || machine_is_nokia_n810() ||
3121+ machine_is_nokia_n810_wimax()) {
3122+ tahvo_irq_pin = 111;
3123+ } else {
3124+ printk(KERN_ERR "cbus: Unsupported board for tahvo\n");
3125+ return -ENODEV;
3126+ }
3127+
3128+ if ((ret = gpio_request(tahvo_irq_pin, "TAHVO irq")) < 0) {
3129+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
3130+ return ret;
3131+ }
3132+
3133+ /* Set the pin as input */
3134+ gpio_direction_input(tahvo_irq_pin);
3135+
3136+ /* Rising edge triggers the IRQ */
3137+ set_irq_type(gpio_to_irq(tahvo_irq_pin), IRQ_TYPE_EDGE_RISING);
3138+
3139+ /* Mask all TAHVO interrupts */
3140+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
3141+
3142+ ret = request_irq(gpio_to_irq(tahvo_irq_pin), tahvo_irq_handler, 0,
3143+ "tahvo", 0);
3144+ if (ret < 0) {
3145+ printk(KERN_ERR PFX "Unable to register IRQ handler\n");
3146+ gpio_free(tahvo_irq_pin);
3147+ return ret;
3148+ }
3149+#ifdef CONFIG_CBUS_TAHVO_USER
3150+ /* Initialize user-space interface */
3151+ if (tahvo_user_init() < 0) {
3152+ printk(KERN_ERR "Unable to initialize driver\n");
3153+ free_irq(gpio_to_irq(tahvo_irq_pin), 0);
3154+ gpio_free(tahvo_irq_pin);
3155+ return ret;
3156+ }
3157+#endif
3158+ return 0;
3159+}
3160+
3161+static int tahvo_remove(struct device *dev)
3162+{
3163+#ifdef CONFIG_CBUS_TAHVO_USER
3164+ tahvo_user_cleanup();
3165+#endif
3166+ /* Mask all TAHVO interrupts */
3167+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
3168+ free_irq(gpio_to_irq(tahvo_irq_pin), 0);
3169+ gpio_free(tahvo_irq_pin);
3170+ tasklet_kill(&tahvo_tasklet);
3171+
3172+ return 0;
3173+}
3174+
3175+static void tahvo_device_release(struct device *dev)
3176+{
3177+ complete(&device_release);
3178+}
3179+
3180+static struct device_driver tahvo_driver = {
3181+ .name = "tahvo",
3182+ .bus = &platform_bus_type,
3183+ .probe = tahvo_probe,
3184+ .remove = tahvo_remove,
3185+};
3186+
3187+static struct platform_device tahvo_device = {
3188+ .name = "tahvo",
3189+ .id = -1,
3190+ .dev = {
3191+ .release = tahvo_device_release,
3192+ }
3193+};
3194+
3195+/**
3196+ * tahvo_init - initialise Tahvo driver
3197+ *
3198+ * Initialise the Tahvo driver and return 0 if everything worked ok
3199+ */
3200+static int __init tahvo_init(void)
3201+{
3202+ int ret = 0;
3203+
3204+ printk(KERN_INFO "Tahvo/Betty driver initialising\n");
3205+
3206+ init_completion(&device_release);
3207+
3208+ if ((ret = driver_register(&tahvo_driver)) < 0)
3209+ return ret;
3210+
3211+ if ((ret = platform_device_register(&tahvo_device)) < 0) {
3212+ driver_unregister(&tahvo_driver);
3213+ return ret;
3214+ }
3215+ return 0;
3216+}
3217+
3218+/*
3219+ * Cleanup
3220+ */
3221+static void __exit tahvo_exit(void)
3222+{
3223+ platform_device_unregister(&tahvo_device);
3224+ driver_unregister(&tahvo_driver);
3225+ wait_for_completion(&device_release);
3226+}
3227+
3228+EXPORT_SYMBOL(tahvo_request_irq);
3229+EXPORT_SYMBOL(tahvo_free_irq);
3230+EXPORT_SYMBOL(tahvo_enable_irq);
3231+EXPORT_SYMBOL(tahvo_disable_irq);
3232+EXPORT_SYMBOL(tahvo_ack_irq);
3233+EXPORT_SYMBOL(tahvo_read_reg);
3234+EXPORT_SYMBOL(tahvo_write_reg);
3235+EXPORT_SYMBOL(tahvo_get_backlight_level);
3236+EXPORT_SYMBOL(tahvo_get_max_backlight_level);
3237+EXPORT_SYMBOL(tahvo_set_backlight_level);
3238+
3239+subsys_initcall(tahvo_init);
3240+module_exit(tahvo_exit);
3241+
3242+MODULE_DESCRIPTION("Tahvo ASIC control");
3243+MODULE_LICENSE("GPL");
3244+MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen");
3245--- /dev/null
3246@@ -0,0 +1,61 @@
3247+/*
3248+ * drivers/cbus/tahvo.h
3249+ *
3250+ * Copyright (C) 2004, 2005 Nokia Corporation
3251+ *
3252+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
3253+ * David Weinehall <david.weinehall@nokia.com>
3254+ *
3255+ * This file is subject to the terms and conditions of the GNU General
3256+ * Public License. See the file "COPYING" in the main directory of this
3257+ * archive for more details.
3258+ *
3259+ * This program is distributed in the hope that it will be useful,
3260+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3261+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3262+ * GNU General Public License for more details.
3263+
3264+ * You should have received a copy of the GNU General Public License
3265+ * along with this program; if not, write to the Free Software
3266+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3267+ */
3268+
3269+#ifndef __DRIVERS_CBUS_TAHVO_H
3270+#define __DRIVERS_CBUS_TAHVO_H
3271+
3272+#include <linux/types.h>
3273+
3274+/* Registers */
3275+#define TAHVO_REG_ASICR 0x00 /* ASIC ID & revision */
3276+#define TAHVO_REG_IDR 0x01 /* Interrupt ID */
3277+#define TAHVO_REG_IDSR 0x02 /* Interrupt status */
3278+#define TAHVO_REG_IMR 0x03 /* Interrupt mask */
3279+#define TAHVO_REG_LEDPWMR 0x05 /* LED PWM */
3280+#define TAHVO_REG_USBR 0x06 /* USB control */
3281+#define TAHVO_REG_MAX 0x0d
3282+
3283+/* Interrupt sources */
3284+#define TAHVO_INT_VBUSON 0
3285+
3286+#define MAX_TAHVO_IRQ_HANDLERS 8
3287+
3288+int tahvo_read_reg(int reg);
3289+void tahvo_write_reg(int reg, u16 val);
3290+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear);
3291+int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name);
3292+void tahvo_free_irq(int id);
3293+void tahvo_enable_irq(int id);
3294+void tahvo_disable_irq(int id);
3295+void tahvo_ack_irq(int id);
3296+int tahvo_get_backlight_level(void);
3297+int tahvo_get_max_backlight_level(void);
3298+void tahvo_set_backlight_level(int level);
3299+
3300+#ifdef CONFIG_CBUS_TAHVO_USER
3301+int tahvo_user_init(void);
3302+void tahvo_user_cleanup(void);
3303+#endif
3304+
3305+extern spinlock_t tahvo_lock;
3306+
3307+#endif /* __DRIVERS_CBUS_TAHVO_H */
3308--- /dev/null
3309@@ -0,0 +1,777 @@
3310+/**
3311+ * drivers/cbus/tahvo-usb.c
3312+ *
3313+ * Tahvo USB transeiver
3314+ *
3315+ * Copyright (C) 2005-2006 Nokia Corporation
3316+ *
3317+ * Parts copied from drivers/i2c/chips/isp1301_omap.c
3318+ * Copyright (C) 2004 Texas Instruments
3319+ * Copyright (C) 2004 David Brownell
3320+ *
3321+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
3322+ * Tony Lindgren <tony@atomide.com>, and
3323+ * Timo Teräs <timo.teras@nokia.com>
3324+ *
3325+ * This file is subject to the terms and conditions of the GNU General
3326+ * Public License. See the file "COPYING" in the main directory of this
3327+ * archive for more details.
3328+ *
3329+ * This program is distributed in the hope that it will be useful,
3330+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3331+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3332+ * GNU General Public License for more details.
3333+ *
3334+ * You should have received a copy of the GNU General Public License
3335+ * along with this program; if not, write to the Free Software
3336+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3337+ */
3338+
3339+#include <linux/kernel.h>
3340+#include <linux/module.h>
3341+#include <linux/init.h>
3342+#include <linux/slab.h>
3343+#include <linux/io.h>
3344+#include <linux/interrupt.h>
3345+#include <linux/platform_device.h>
3346+#include <linux/usb/ch9.h>
3347+#include <linux/usb/gadget.h>
3348+#include <linux/usb.h>
3349+#include <linux/usb/otg.h>
3350+#include <linux/i2c.h>
3351+#include <linux/workqueue.h>
3352+#include <linux/kobject.h>
3353+#include <linux/clk.h>
3354+#include <linux/mutex.h>
3355+
3356+#include <asm/irq.h>
3357+#include <plat/usb.h>
3358+
3359+#include "cbus.h"
3360+#include "tahvo.h"
3361+
3362+#define DRIVER_NAME "tahvo-usb"
3363+
3364+#define USBR_SLAVE_CONTROL (1 << 8)
3365+#define USBR_VPPVIO_SW (1 << 7)
3366+#define USBR_SPEED (1 << 6)
3367+#define USBR_REGOUT (1 << 5)
3368+#define USBR_MASTER_SW2 (1 << 4)
3369+#define USBR_MASTER_SW1 (1 << 3)
3370+#define USBR_SLAVE_SW (1 << 2)
3371+#define USBR_NSUSPEND (1 << 1)
3372+#define USBR_SEMODE (1 << 0)
3373+
3374+/* bits in OTG_CTRL */
3375+
3376+/* Bits that are controlled by OMAP OTG and are read-only */
3377+#define OTG_CTRL_OMAP_MASK (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\
3378+ OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
3379+/* Bits that are controlled by transceiver */
3380+#define OTG_CTRL_XCVR_MASK (OTG_ASESSVLD|OTG_BSESSEND|\
3381+ OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
3382+/* Bits that are controlled by system */
3383+#define OTG_CTRL_SYS_MASK (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|\
3384+ OTG_B_HNPEN|OTG_BUSDROP)
3385+
3386+#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG)
3387+#error tahvo-otg.c does not work with OCHI yet!
3388+#endif
3389+
3390+#define TAHVO_MODE_HOST 0
3391+#define TAHVO_MODE_PERIPHERAL 1
3392+
3393+#ifdef CONFIG_USB_OTG
3394+#define TAHVO_MODE(tu) (tu)->tahvo_mode
3395+#elif defined(CONFIG_USB_GADGET_OMAP)
3396+#define TAHVO_MODE(tu) TAHVO_MODE_PERIPHERAL
3397+#else
3398+#define TAHVO_MODE(tu) TAHVO_MODE_HOST
3399+#endif
3400+
3401+struct tahvo_usb {
3402+ struct platform_device *pt_dev;
3403+ struct otg_transceiver otg;
3404+ int vbus_state;
3405+ struct work_struct irq_work;
3406+ struct mutex serialize;
3407+#ifdef CONFIG_USB_OTG
3408+ int tahvo_mode;
3409+#endif
3410+};
3411+static struct platform_device tahvo_usb_device;
3412+
3413+/*
3414+ * ---------------------------------------------------------------------------
3415+ * OTG related functions
3416+ *
3417+ * These shoud be separated into omap-otg.c driver module, as they are used
3418+ * by various transceivers. These functions are needed in the UDC-only case
3419+ * as well. These functions are copied from GPL isp1301_omap.c
3420+ * ---------------------------------------------------------------------------
3421+ */
3422+static struct platform_device *tahvo_otg_dev;
3423+
3424+static irqreturn_t omap_otg_irq(int irq, void *arg)
3425+{
3426+ struct platform_device *otg_dev = arg;
3427+ struct tahvo_usb *tu = platform_get_drvdata(otg_dev);
3428+ u16 otg_irq;
3429+
3430+ otg_irq = omap_readw(OTG_IRQ_SRC);
3431+ if (otg_irq & OPRT_CHG) {
3432+ omap_writew(OPRT_CHG, OTG_IRQ_SRC);
3433+ } else if (otg_irq & B_SRP_TMROUT) {
3434+ omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
3435+ } else if (otg_irq & B_HNP_FAIL) {
3436+ omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
3437+ } else if (otg_irq & A_SRP_DETECT) {
3438+ omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
3439+ } else if (otg_irq & A_REQ_TMROUT) {
3440+ omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
3441+ } else if (otg_irq & A_VBUS_ERR) {
3442+ omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
3443+ } else if (otg_irq & DRIVER_SWITCH) {
3444+ if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
3445+ tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
3446+ /* role is host */
3447+ usb_bus_start_enum(tu->otg.host,
3448+ tu->otg.host->otg_port);
3449+ }
3450+ omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
3451+ } else
3452+ return IRQ_NONE;
3453+
3454+ return IRQ_HANDLED;
3455+
3456+}
3457+
3458+static int omap_otg_init(void)
3459+{
3460+ u32 l;
3461+
3462+#ifdef CONFIG_USB_OTG
3463+ if (!tahvo_otg_dev) {
3464+ printk("tahvo-usb: no tahvo_otg_dev\n");
3465+ return -ENODEV;
3466+ }
3467+#endif
3468+
3469+ l = omap_readl(OTG_SYSCON_1);
3470+ l &= ~OTG_IDLE_EN;
3471+ omap_writel(l, OTG_SYSCON_1);
3472+ udelay(100);
3473+
3474+ /* some of these values are board-specific... */
3475+ l = omap_readl(OTG_SYSCON_2);
3476+ l |= OTG_EN
3477+ /* for B-device: */
3478+ | SRP_GPDATA /* 9msec Bdev D+ pulse */
3479+ | SRP_GPDVBUS /* discharge after VBUS pulse */
3480+ // | (3 << 24) /* 2msec VBUS pulse */
3481+ /* for A-device: */
3482+ | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
3483+ | SRP_DPW /* detect 167+ns SRP pulses */
3484+ | SRP_DATA | SRP_VBUS; /* accept both kinds of SRP pulse */
3485+ omap_writel(l, OTG_SYSCON_2);
3486+
3487+ omap_writew(DRIVER_SWITCH | OPRT_CHG
3488+ | B_SRP_TMROUT | B_HNP_FAIL
3489+ | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT,
3490+ OTG_IRQ_EN);
3491+ l = omap_readl(OTG_SYSCON_2);
3492+ l |= OTG_EN;
3493+ omap_writel(l, OTG_SYSCON_2);
3494+
3495+ return 0;
3496+}
3497+
3498+static int omap_otg_probe(struct device *dev)
3499+{
3500+ int ret;
3501+
3502+ tahvo_otg_dev = to_platform_device(dev);
3503+ ret = omap_otg_init();
3504+ if (ret != 0) {
3505+ printk(KERN_ERR "tahvo-usb: omap_otg_init failed\n");
3506+ return ret;
3507+ }
3508+
3509+ return request_irq(tahvo_otg_dev->resource[1].start,
3510+ omap_otg_irq, IRQF_DISABLED, DRIVER_NAME,
3511+ &tahvo_usb_device);
3512+}
3513+
3514+static int omap_otg_remove(struct device *dev)
3515+{
3516+ free_irq(tahvo_otg_dev->resource[1].start, &tahvo_usb_device);
3517+ tahvo_otg_dev = NULL;
3518+
3519+ return 0;
3520+}
3521+
3522+struct device_driver omap_otg_driver = {
3523+ .name = "omap_otg",
3524+ .bus = &platform_bus_type,
3525+ .probe = omap_otg_probe,
3526+ .remove = omap_otg_remove,
3527+};
3528+
3529+/*
3530+ * ---------------------------------------------------------------------------
3531+ * Tahvo related functions
3532+ * These are Nokia proprietary code, except for the OTG register settings,
3533+ * which are copied from isp1301.c
3534+ * ---------------------------------------------------------------------------
3535+ */
3536+static ssize_t vbus_state_show(struct device *device,
3537+ struct device_attribute *attr, char *buf)
3538+{
3539+ struct tahvo_usb *tu = dev_get_drvdata(device);
3540+ return sprintf(buf, "%d\n", tu->vbus_state);
3541+}
3542+static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL);
3543+
3544+int vbus_active = 0;
3545+
3546+#if 0
3547+
3548+static int host_suspend(struct tahvo_usb *tu)
3549+{
3550+ struct device *dev;
3551+
3552+ if (!tu->otg.host)
3553+ return -ENODEV;
3554+
3555+ /* Currently ASSUMES only the OTG port matters;
3556+ * other ports could be active...
3557+ */
3558+ dev = tu->otg.host->controller;
3559+ return dev->driver->suspend(dev, PMSG_SUSPEND);
3560+}
3561+
3562+static int host_resume(struct tahvo_usb *tu)
3563+{
3564+ struct device *dev;
3565+
3566+ if (!tu->otg.host)
3567+ return -ENODEV;
3568+
3569+ dev = tu->otg.host->controller;
3570+ return dev->driver->resume(dev);
3571+}
3572+
3573+#else
3574+
3575+static int host_suspend(struct tahvo_usb *tu)
3576+{
3577+ return 0;
3578+}
3579+
3580+static int host_resume(struct tahvo_usb *tu)
3581+{
3582+ return 0;
3583+}
3584+
3585+#endif
3586+
3587+static void check_vbus_state(struct tahvo_usb *tu)
3588+{
3589+ int reg, prev_state;
3590+
3591+ reg = tahvo_read_reg(TAHVO_REG_IDSR);
3592+ if (reg & 0x01) {
3593+ u32 l;
3594+
3595+ vbus_active = 1;
3596+ switch (tu->otg.state) {
3597+ case OTG_STATE_B_IDLE:
3598+ /* Enable the gadget driver */
3599+ if (tu->otg.gadget)
3600+ usb_gadget_vbus_connect(tu->otg.gadget);
3601+ /* Set B-session valid and not B-sessio ended to indicate
3602+ * Vbus to be ok. */
3603+ l = omap_readl(OTG_CTRL);
3604+ l &= ~OTG_BSESSEND;
3605+ l |= OTG_BSESSVLD;
3606+ omap_writel(l, OTG_CTRL);
3607+
3608+ tu->otg.state = OTG_STATE_B_PERIPHERAL;
3609+ break;
3610+ case OTG_STATE_A_IDLE:
3611+ /* Session is now valid assuming the USB hub is driving Vbus */
3612+ tu->otg.state = OTG_STATE_A_HOST;
3613+ host_resume(tu);
3614+ break;
3615+ default:
3616+ break;
3617+ }
3618+ printk("USB cable connected\n");
3619+ } else {
3620+ switch (tu->otg.state) {
3621+ case OTG_STATE_B_PERIPHERAL:
3622+ if (tu->otg.gadget)
3623+ usb_gadget_vbus_disconnect(tu->otg.gadget);
3624+ tu->otg.state = OTG_STATE_B_IDLE;
3625+ break;
3626+ case OTG_STATE_A_HOST:
3627+ tu->otg.state = OTG_STATE_A_IDLE;
3628+ break;
3629+ default:
3630+ break;
3631+ }
3632+ printk("USB cable disconnected\n");
3633+ vbus_active = 0;
3634+ }
3635+
3636+ prev_state = tu->vbus_state;
3637+ tu->vbus_state = reg & 0x01;
3638+ if (prev_state != tu->vbus_state)
3639+ sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state");
3640+}
3641+
3642+static void tahvo_usb_become_host(struct tahvo_usb *tu)
3643+{
3644+ u32 l;
3645+
3646+ /* Clear system and transceiver controlled bits
3647+ * also mark the A-session is always valid */
3648+ omap_otg_init();
3649+
3650+ l = omap_readl(OTG_CTRL);
3651+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK);
3652+ l |= OTG_ASESSVLD;
3653+ omap_writel(l, OTG_CTRL);
3654+
3655+ /* Power up the transceiver in USB host mode */
3656+ tahvo_write_reg(TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND |
3657+ USBR_MASTER_SW2 | USBR_MASTER_SW1);
3658+ tu->otg.state = OTG_STATE_A_IDLE;
3659+
3660+ check_vbus_state(tu);
3661+}
3662+
3663+static void tahvo_usb_stop_host(struct tahvo_usb *tu)
3664+{
3665+ host_suspend(tu);
3666+ tu->otg.state = OTG_STATE_A_IDLE;
3667+}
3668+
3669+static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
3670+{
3671+ u32 l;
3672+
3673+ /* Clear system and transceiver controlled bits
3674+ * and enable ID to mark peripheral mode and
3675+ * BSESSEND to mark no Vbus */
3676+ omap_otg_init();
3677+ l = omap_readl(OTG_CTRL);
3678+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
3679+ l |= OTG_ID | OTG_BSESSEND;
3680+ omap_writel(l, OTG_CTRL);
3681+
3682+ /* Power up transceiver and set it in USB perhiperal mode */
3683+ tahvo_write_reg(TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW);
3684+ tu->otg.state = OTG_STATE_B_IDLE;
3685+
3686+ check_vbus_state(tu);
3687+}
3688+
3689+static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu)
3690+{
3691+ u32 l;
3692+
3693+ l = omap_readl(OTG_CTRL);
3694+ l &= ~OTG_BSESSVLD;
3695+ l |= OTG_BSESSEND;
3696+ omap_writel(l, OTG_CTRL);
3697+
3698+ if (tu->otg.gadget)
3699+ usb_gadget_vbus_disconnect(tu->otg.gadget);
3700+ tu->otg.state = OTG_STATE_B_IDLE;
3701+
3702+}
3703+
3704+static void tahvo_usb_power_off(struct tahvo_usb *tu)
3705+{
3706+ u32 l;
3707+ int id;
3708+
3709+ /* Disable gadget controller if any */
3710+ if (tu->otg.gadget)
3711+ usb_gadget_vbus_disconnect(tu->otg.gadget);
3712+
3713+ host_suspend(tu);
3714+
3715+ /* Disable OTG and interrupts */
3716+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
3717+ id = OTG_ID;
3718+ else
3719+ id = 0;
3720+ l = omap_readl(OTG_CTRL);
3721+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
3722+ l |= id | OTG_BSESSEND;
3723+ omap_writel(l, OTG_CTRL);
3724+ omap_writew(0, OTG_IRQ_EN);
3725+
3726+ l = omap_readl(OTG_SYSCON_2);
3727+ l &= ~OTG_EN;
3728+ omap_writel(l, OTG_SYSCON_2);
3729+
3730+ l = omap_readl(OTG_SYSCON_1);
3731+ l |= OTG_IDLE_EN;
3732+ omap_writel(l, OTG_SYSCON_1);
3733+
3734+ /* Power off transceiver */
3735+ tahvo_write_reg(TAHVO_REG_USBR, 0);
3736+ tu->otg.state = OTG_STATE_UNDEFINED;
3737+}
3738+
3739+
3740+static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA)
3741+{
3742+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
3743+
3744+ dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA);
3745+
3746+ if (dev->state == OTG_STATE_B_PERIPHERAL) {
3747+ /* REVISIT: Can Tahvo charge battery from VBUS? */
3748+ }
3749+ return 0;
3750+}
3751+
3752+static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend)
3753+{
3754+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
3755+ u16 w;
3756+
3757+ dev_dbg(&tu->pt_dev->dev, "set_suspend\n");
3758+
3759+ w = tahvo_read_reg(TAHVO_REG_USBR);
3760+ if (suspend)
3761+ w &= ~USBR_NSUSPEND;
3762+ else
3763+ w |= USBR_NSUSPEND;
3764+ tahvo_write_reg(TAHVO_REG_USBR, w);
3765+
3766+ return 0;
3767+}
3768+
3769+static int tahvo_usb_start_srp(struct otg_transceiver *dev)
3770+{
3771+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
3772+ u32 otg_ctrl;
3773+
3774+ dev_dbg(&tu->pt_dev->dev, "start_srp\n");
3775+
3776+ if (!dev || tu->otg.state != OTG_STATE_B_IDLE)
3777+ return -ENODEV;
3778+
3779+ otg_ctrl = omap_readl(OTG_CTRL);
3780+ if (!(otg_ctrl & OTG_BSESSEND))
3781+ return -EINVAL;
3782+
3783+ otg_ctrl |= OTG_B_BUSREQ;
3784+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK;
3785+ omap_writel(otg_ctrl, OTG_CTRL);
3786+ tu->otg.state = OTG_STATE_B_SRP_INIT;
3787+
3788+ return 0;
3789+}
3790+
3791+static int tahvo_usb_start_hnp(struct otg_transceiver *otg)
3792+{
3793+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
3794+
3795+ dev_dbg(&tu->pt_dev->dev, "start_hnp\n");
3796+#ifdef CONFIG_USB_OTG
3797+ /* REVISIT: Add this for OTG */
3798+#endif
3799+ return -EINVAL;
3800+}
3801+
3802+static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host)
3803+{
3804+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
3805+ u32 l;
3806+
3807+ dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host);
3808+
3809+ if (otg == NULL)
3810+ return -ENODEV;
3811+
3812+#if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP)
3813+
3814+ mutex_lock(&tu->serialize);
3815+
3816+ if (host == NULL) {
3817+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST)
3818+ tahvo_usb_power_off(tu);
3819+ tu->otg.host = NULL;
3820+ mutex_unlock(&tu->serialize);
3821+ return 0;
3822+ }
3823+
3824+ l = omap_readl(OTG_SYSCON_1);
3825+ l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN);
3826+ omap_writel(l, OTG_SYSCON_1);
3827+
3828+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) {
3829+ tu->otg.host = NULL;
3830+ tahvo_usb_become_host(tu);
3831+ } else
3832+ host_suspend(tu);
3833+
3834+ tu->otg.host = host;
3835+
3836+ mutex_unlock(&tu->serialize);
3837+#else
3838+ /* No host mode configured, so do not allow host controlled to be set */
3839+ return -EINVAL;
3840+#endif
3841+
3842+ return 0;
3843+}
3844+
3845+static int tahvo_usb_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
3846+{
3847+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
3848+
3849+ dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget);
3850+
3851+ if (!otg)
3852+ return -ENODEV;
3853+
3854+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_GADGET_OMAP)
3855+
3856+ mutex_lock(&tu->serialize);
3857+
3858+ if (!gadget) {
3859+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
3860+ tahvo_usb_power_off(tu);
3861+ tu->otg.gadget = NULL;
3862+ mutex_unlock(&tu->serialize);
3863+ return 0;
3864+ }
3865+
3866+ tu->otg.gadget = gadget;
3867+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
3868+ tahvo_usb_become_peripheral(tu);
3869+
3870+ mutex_unlock(&tu->serialize);
3871+#else
3872+ /* No gadget mode configured, so do not allow host controlled to be set */
3873+ return -EINVAL;
3874+#endif
3875+
3876+ return 0;
3877+}
3878+
3879+static void tahvo_usb_irq_work(struct work_struct *work)
3880+{
3881+ struct tahvo_usb *tu = container_of(work, struct tahvo_usb, irq_work);
3882+
3883+ mutex_lock(&tu->serialize);
3884+ check_vbus_state(tu);
3885+ mutex_unlock(&tu->serialize);
3886+}
3887+
3888+static void tahvo_usb_vbus_interrupt(unsigned long arg)
3889+{
3890+ struct tahvo_usb *tu = (struct tahvo_usb *) arg;
3891+
3892+ tahvo_ack_irq(TAHVO_INT_VBUSON);
3893+ /* Seems we need this to acknowledge the interrupt */
3894+ tahvo_read_reg(TAHVO_REG_IDSR);
3895+ schedule_work(&tu->irq_work);
3896+}
3897+
3898+#ifdef CONFIG_USB_OTG
3899+static ssize_t otg_mode_show(struct device *device,
3900+ struct device_attribute *attr, char *buf)
3901+{
3902+ struct tahvo_usb *tu = dev_get_drvdata(device);
3903+ switch (tu->tahvo_mode) {
3904+ case TAHVO_MODE_HOST:
3905+ return sprintf(buf, "host\n");
3906+ case TAHVO_MODE_PERIPHERAL:
3907+ return sprintf(buf, "peripheral\n");
3908+ }
3909+ return sprintf(buf, "unknown\n");
3910+}
3911+
3912+static ssize_t otg_mode_store(struct device *device,
3913+ struct device_attribute *attr,
3914+ const char *buf, size_t count)
3915+{
3916+ struct tahvo_usb *tu = dev_get_drvdata(device);
3917+ int r;
3918+
3919+ r = strlen(buf);
3920+ mutex_lock(&tu->serialize);
3921+ if (strncmp(buf, "host", 4) == 0) {
3922+ if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL)
3923+ tahvo_usb_stop_peripheral(tu);
3924+ tu->tahvo_mode = TAHVO_MODE_HOST;
3925+ if (tu->otg.host) {
3926+ printk(KERN_INFO "Selected HOST mode: host controller present.\n");
3927+ tahvo_usb_become_host(tu);
3928+ } else {
3929+ printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n");
3930+ tahvo_usb_power_off(tu);
3931+ }
3932+ } else if (strncmp(buf, "peripheral", 10) == 0) {
3933+ if (tu->tahvo_mode == TAHVO_MODE_HOST)
3934+ tahvo_usb_stop_host(tu);
3935+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
3936+ if (tu->otg.gadget) {
3937+ printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n");
3938+ tahvo_usb_become_peripheral(tu);
3939+ } else {
3940+ printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n");
3941+ tahvo_usb_power_off(tu);
3942+ }
3943+ } else
3944+ r = -EINVAL;
3945+
3946+ mutex_unlock(&tu->serialize);
3947+ return r;
3948+}
3949+
3950+static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
3951+#endif
3952+
3953+static int tahvo_usb_probe(struct device *dev)
3954+{
3955+ struct tahvo_usb *tu;
3956+ int ret;
3957+
3958+ dev_dbg(dev, "probe\n");
3959+
3960+ /* Create driver data */
3961+ tu = kmalloc(sizeof(*tu), GFP_KERNEL);
3962+ if (!tu)
3963+ return -ENOMEM;
3964+ memset(tu, 0, sizeof(*tu));
3965+ tu->pt_dev = container_of(dev, struct platform_device, dev);
3966+#ifdef CONFIG_USB_OTG
3967+ /* Default mode */
3968+#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT
3969+ tu->tahvo_mode = TAHVO_MODE_HOST;
3970+#else
3971+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
3972+#endif
3973+#endif
3974+
3975+ INIT_WORK(&tu->irq_work, tahvo_usb_irq_work);
3976+ mutex_init(&tu->serialize);
3977+
3978+ /* Set initial state, so that we generate kevents only on
3979+ * state changes */
3980+ tu->vbus_state = tahvo_read_reg(TAHVO_REG_IDSR) & 0x01;
3981+
3982+ /* We cannot enable interrupt until omap_udc is initialized */
3983+ ret = tahvo_request_irq(TAHVO_INT_VBUSON, tahvo_usb_vbus_interrupt,
3984+ (unsigned long) tu, "vbus_interrupt");
3985+ if (ret != 0) {
3986+ kfree(tu);
3987+ printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n");
3988+ return ret;
3989+ }
3990+
3991+ /* Attributes */
3992+ ret = device_create_file(dev, &dev_attr_vbus_state);
3993+#ifdef CONFIG_USB_OTG
3994+ ret |= device_create_file(dev, &dev_attr_otg_mode);
3995+#endif
3996+ if (ret)
3997+ printk(KERN_ERR "attribute creation failed: %d\n", ret);
3998+
3999+ /* Create OTG interface */
4000+ tahvo_usb_power_off(tu);
4001+ tu->otg.state = OTG_STATE_UNDEFINED;
4002+ tu->otg.label = DRIVER_NAME;
4003+ tu->otg.set_host = tahvo_usb_set_host;
4004+ tu->otg.set_peripheral = tahvo_usb_set_peripheral;
4005+ tu->otg.set_power = tahvo_usb_set_power;
4006+ tu->otg.set_suspend = tahvo_usb_set_suspend;
4007+ tu->otg.start_srp = tahvo_usb_start_srp;
4008+ tu->otg.start_hnp = tahvo_usb_start_hnp;
4009+
4010+ ret = otg_set_transceiver(&tu->otg);
4011+ if (ret < 0) {
4012+ printk(KERN_ERR "Cannot register USB transceiver\n");
4013+ kfree(tu);
4014+ tahvo_free_irq(TAHVO_INT_VBUSON);
4015+ return ret;
4016+ }
4017+
4018+ dev_set_drvdata(dev, tu);
4019+
4020+ /* Act upon current vbus state once at startup. A vbus state irq may or
4021+ * may not be generated in addition to this. */
4022+ schedule_work(&tu->irq_work);
4023+ return 0;
4024+}
4025+
4026+static int tahvo_usb_remove(struct device *dev)
4027+{
4028+ dev_dbg(dev, "remove\n");
4029+
4030+ tahvo_free_irq(TAHVO_INT_VBUSON);
4031+ flush_scheduled_work();
4032+ otg_set_transceiver(0);
4033+ device_remove_file(dev, &dev_attr_vbus_state);
4034+#ifdef CONFIG_USB_OTG
4035+ device_remove_file(dev, &dev_attr_otg_mode);
4036+#endif
4037+ return 0;
4038+}
4039+
4040+static struct device_driver tahvo_usb_driver = {
4041+ .name = "tahvo-usb",
4042+ .bus = &platform_bus_type,
4043+ .probe = tahvo_usb_probe,
4044+ .remove = tahvo_usb_remove,
4045+};
4046+
4047+static struct platform_device tahvo_usb_device = {
4048+ .name = "tahvo-usb",
4049+ .id = -1,
4050+};
4051+
4052+static int __init tahvo_usb_init(void)
4053+{
4054+ int ret = 0;
4055+
4056+ printk(KERN_INFO "Tahvo USB transceiver driver initializing\n");
4057+ ret = driver_register(&tahvo_usb_driver);
4058+ if (ret)
4059+ return ret;
4060+ ret = platform_device_register(&tahvo_usb_device);
4061+ if (ret < 0) {
4062+ driver_unregister(&tahvo_usb_driver);
4063+ return ret;
4064+ }
4065+ ret = driver_register(&omap_otg_driver);
4066+ if (ret) {
4067+ platform_device_unregister(&tahvo_usb_device);
4068+ driver_unregister(&tahvo_usb_driver);
4069+ return ret;
4070+ }
4071+ return 0;
4072+}
4073+
4074+subsys_initcall(tahvo_usb_init);
4075+
4076+static void __exit tahvo_usb_exit(void)
4077+{
4078+ driver_unregister(&omap_otg_driver);
4079+ platform_device_unregister(&tahvo_usb_device);
4080+ driver_unregister(&tahvo_usb_driver);
4081+}
4082+module_exit(tahvo_usb_exit);
4083+
4084+MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver");
4085+MODULE_LICENSE("GPL");
4086+MODULE_AUTHOR("Juha Yrjölä, Tony Lindgren, and Timo Teräs");
4087--- /dev/null
4088@@ -0,0 +1,407 @@
4089+/**
4090+ * drivers/cbus/tahvo-user.c
4091+ *
4092+ * Tahvo user space interface functions
4093+ *
4094+ * Copyright (C) 2004, 2005 Nokia Corporation
4095+ *
4096+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
4097+ *
4098+ * This file is subject to the terms and conditions of the GNU General
4099+ * Public License. See the file "COPYING" in the main directory of this
4100+ * archive for more details.
4101+ *
4102+ * This program is distributed in the hope that it will be useful,
4103+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4104+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4105+ * GNU General Public License for more details.
4106+ *
4107+ * You should have received a copy of the GNU General Public License
4108+ * along with this program; if not, write to the Free Software
4109+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4110+ */
4111+
4112+#include <linux/types.h>
4113+#include <linux/kernel.h>
4114+#include <linux/interrupt.h>
4115+#include <linux/module.h>
4116+#include <linux/init.h>
4117+#include <linux/fs.h>
4118+#include <linux/miscdevice.h>
4119+#include <linux/poll.h>
4120+#include <linux/list.h>
4121+#include <linux/spinlock.h>
4122+#include <linux/sched.h>
4123+#include <linux/mutex.h>
4124+#include <linux/slab.h>
4125+
4126+#include <asm/uaccess.h>
4127+
4128+#include "tahvo.h"
4129+
4130+#include "user_retu_tahvo.h"
4131+
4132+/* Maximum size of IRQ node buffer/pool */
4133+#define TAHVO_MAX_IRQ_BUF_LEN 16
4134+
4135+#define PFX "tahvo-user: "
4136+
4137+/* Bitmap for marking the interrupt sources as having the handlers */
4138+static u32 tahvo_irq_bits;
4139+
4140+/* For allowing only one user process to subscribe to the tahvo interrupts */
4141+static struct file *tahvo_irq_subscr = NULL;
4142+
4143+/* For poll and IRQ passing */
4144+struct tahvo_irq {
4145+ u32 id;
4146+ struct list_head node;
4147+};
4148+
4149+static spinlock_t tahvo_irqs_lock;
4150+static struct tahvo_irq *tahvo_irq_block;
4151+static LIST_HEAD(tahvo_irqs);
4152+static LIST_HEAD(tahvo_irqs_reserve);
4153+
4154+/* Wait queue - used when user wants to read the device */
4155+DECLARE_WAIT_QUEUE_HEAD(tahvo_user_waitqueue);
4156+
4157+/* Semaphore to protect irq subscription sequence */
4158+static struct mutex tahvo_mutex;
4159+
4160+/* This array specifies TAHVO register types (read/write/toggle) */
4161+static const u8 tahvo_access_bits[] = {
4162+ 1,
4163+ 4,
4164+ 1,
4165+ 3,
4166+ 3,
4167+ 3,
4168+ 3,
4169+ 3,
4170+ 3,
4171+ 3,
4172+ 3,
4173+ 3,
4174+ 3,
4175+ 1
4176+};
4177+
4178+/*
4179+ * The handler for all TAHVO interrupts.
4180+ *
4181+ * arg is the interrupt source in TAHVO.
4182+ */
4183+static void tahvo_user_irq_handler(unsigned long arg)
4184+{
4185+ struct tahvo_irq *irq;
4186+
4187+ /* user has to re-enable the interrupt once ready
4188+ * for receiving them again */
4189+ tahvo_disable_irq(arg);
4190+ tahvo_ack_irq(arg);
4191+
4192+ spin_lock(&tahvo_irqs_lock);
4193+ if (list_empty(&tahvo_irqs_reserve)) {
4194+ spin_unlock(&tahvo_irqs_lock);
4195+ return;
4196+ }
4197+ irq = list_entry((&tahvo_irqs_reserve)->next, struct tahvo_irq, node);
4198+ irq->id = arg;
4199+ list_move_tail(&irq->node, &tahvo_irqs);
4200+ spin_unlock(&tahvo_irqs_lock);
4201+
4202+ /* wake up waiting thread */
4203+ wake_up(&tahvo_user_waitqueue);
4204+}
4205+
4206+/*
4207+ * This routine sets up the interrupt handler and marks an interrupt source
4208+ * in TAHVO as a candidate for signal delivery to the user process.
4209+ */
4210+static int tahvo_user_subscribe_to_irq(int id, struct file *filp)
4211+{
4212+ int ret;
4213+
4214+ mutex_lock(&tahvo_mutex);
4215+ if ((tahvo_irq_subscr != NULL) && (tahvo_irq_subscr != filp)) {
4216+ mutex_unlock(&tahvo_mutex);
4217+ return -EBUSY;
4218+ }
4219+ /* Store the file pointer of the first user process registering IRQs */
4220+ tahvo_irq_subscr = filp;
4221+ mutex_unlock(&tahvo_mutex);
4222+
4223+ if (tahvo_irq_bits & (1 << id))
4224+ return 0;
4225+
4226+ ret = tahvo_request_irq(id, tahvo_user_irq_handler, id, "");
4227+ if (ret < 0)
4228+ return ret;
4229+
4230+ /* Mark that this interrupt has a handler */
4231+ tahvo_irq_bits |= 1 << id;
4232+
4233+ return 0;
4234+}
4235+
4236+/*
4237+ * Unregister all TAHVO interrupt handlers
4238+ */
4239+static void tahvo_unreg_irq_handlers(void)
4240+{
4241+ int id;
4242+
4243+ if (!tahvo_irq_bits)
4244+ return;
4245+
4246+ for (id = 0; id < MAX_TAHVO_IRQ_HANDLERS; id++)
4247+ if (tahvo_irq_bits & (1 << id))
4248+ tahvo_free_irq(id);
4249+
4250+ tahvo_irq_bits = 0;
4251+}
4252+
4253+/*
4254+ * Write to TAHVO register.
4255+ * Returns 0 upon success, a negative error value otherwise.
4256+ */
4257+static int tahvo_user_write_with_mask(u32 field, u16 value)
4258+{
4259+ u32 mask;
4260+ u32 reg;
4261+ u_short tmp;
4262+ unsigned long flags;
4263+
4264+ mask = MASK(field);
4265+ reg = REG(field);
4266+
4267+ /* Detect bad mask and reg */
4268+ if (mask == 0 || reg > TAHVO_REG_MAX ||
4269+ tahvo_access_bits[reg] == READ_ONLY) {
4270+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
4271+ reg, mask);
4272+ return -EINVAL;
4273+ }
4274+
4275+ /* Justify value according to mask */
4276+ while (!(mask & 1)) {
4277+ value = value << 1;
4278+ mask = mask >> 1;
4279+ }
4280+
4281+ spin_lock_irqsave(&tahvo_lock, flags);
4282+ if (tahvo_access_bits[reg] == TOGGLE) {
4283+ /* No need to detect previous content of register */
4284+ tmp = 0;
4285+ } else {
4286+ /* Read current value of register */
4287+ tmp = tahvo_read_reg(reg);
4288+ }
4289+ /* Generate a new value */
4290+ tmp = (tmp & ~MASK(field)) | (value & MASK(field));
4291+ /* Write data to TAHVO */
4292+ tahvo_write_reg(reg, tmp);
4293+ spin_unlock_irqrestore(&tahvo_lock, flags);
4294+
4295+ return 0;
4296+}
4297+
4298+/*
4299+ * Read TAHVO register.
4300+ */
4301+static u32 tahvo_user_read_with_mask(u32 field)
4302+{
4303+ u_short value;
4304+ u32 mask, reg;
4305+
4306+ mask = MASK(field);
4307+ reg = REG(field);
4308+
4309+ /* Detect bad mask and reg */
4310+ if (mask == 0 || reg > TAHVO_REG_MAX) {
4311+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
4312+ reg, mask);
4313+ return -EINVAL;
4314+ }
4315+
4316+ /* Read the register */
4317+ value = tahvo_read_reg(reg) & mask;
4318+
4319+ /* Right justify value */
4320+ while (!(mask & 1)) {
4321+ value = value >> 1;
4322+ mask = mask >> 1;
4323+ }
4324+
4325+ return value;
4326+}
4327+
4328+/*
4329+ * Close device
4330+ */
4331+static int tahvo_close(struct inode *inode, struct file *filp)
4332+{
4333+ /* Unregister all interrupts that have been registered */
4334+ if (tahvo_irq_subscr == filp) {
4335+ tahvo_unreg_irq_handlers();
4336+ tahvo_irq_subscr = NULL;
4337+ }
4338+
4339+ return 0;
4340+}
4341+
4342+/*
4343+ * Device control (ioctl)
4344+ */
4345+static int tahvo_ioctl(struct inode *inode, struct file *filp,
4346+ unsigned int cmd, unsigned long arg)
4347+{
4348+ struct retu_tahvo_write_parms par;
4349+ int ret;
4350+
4351+ switch (cmd) {
4352+ case URT_IOCT_IRQ_SUBSCR:
4353+ return tahvo_user_subscribe_to_irq(arg, filp);
4354+ case TAHVO_IOCH_READ:
4355+ return tahvo_user_read_with_mask(arg);
4356+ case TAHVO_IOCX_WRITE:
4357+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
4358+ if (ret)
4359+ printk(KERN_ERR "copy_from_user failed: %d\n", ret);
4360+ par.result = tahvo_user_write_with_mask(par.field, par.value);
4361+ ret = copy_to_user((void __user *) arg, &par, sizeof(par));
4362+ if (ret)
4363+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
4364+ break;
4365+ default:
4366+ return -ENOIOCTLCMD;
4367+ }
4368+ return 0;
4369+}
4370+
4371+/*
4372+ * Read from device
4373+ */
4374+static ssize_t tahvo_read(struct file *filp, char *buf, size_t count,
4375+ loff_t * offp)
4376+{
4377+ struct tahvo_irq *irq;
4378+
4379+ u32 nr, i;
4380+
4381+ /* read not permitted if neither filp nor anyone has registered IRQs */
4382+ if (tahvo_irq_subscr != filp)
4383+ return -EPERM;
4384+
4385+ if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0))
4386+ return -EINVAL;
4387+
4388+ nr = count / sizeof(u32);
4389+
4390+ for (i = 0; i < nr; i++) {
4391+ unsigned long flags;
4392+ u32 irq_id;
4393+ int ret;
4394+
4395+ ret = wait_event_interruptible(tahvo_user_waitqueue,
4396+ !list_empty(&tahvo_irqs));
4397+ if (ret < 0)
4398+ return ret;
4399+
4400+ spin_lock_irqsave(&tahvo_irqs_lock, flags);
4401+ irq = list_entry((&tahvo_irqs)->next, struct tahvo_irq, node);
4402+ irq_id = irq->id;
4403+ list_move(&irq->node, &tahvo_irqs_reserve);
4404+ spin_unlock_irqrestore(&tahvo_irqs_lock, flags);
4405+
4406+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
4407+ sizeof(irq_id));
4408+ if (ret)
4409+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
4410+ }
4411+
4412+ return count;
4413+}
4414+
4415+/*
4416+ * Poll method
4417+ */
4418+static unsigned tahvo_poll(struct file *filp, struct poll_table_struct *pt)
4419+{
4420+ if (!list_empty(&tahvo_irqs))
4421+ return POLLIN;
4422+
4423+ poll_wait(filp, &tahvo_user_waitqueue, pt);
4424+
4425+ if (!list_empty(&tahvo_irqs))
4426+ return POLLIN;
4427+ else
4428+ return 0;
4429+}
4430+
4431+static struct file_operations tahvo_user_fileops = {
4432+ .owner = THIS_MODULE,
4433+ .ioctl = tahvo_ioctl,
4434+ .read = tahvo_read,
4435+ .release = tahvo_close,
4436+ .poll = tahvo_poll
4437+};
4438+
4439+static struct miscdevice tahvo_device = {
4440+ .minor = MISC_DYNAMIC_MINOR,
4441+ .name = "tahvo",
4442+ .fops = &tahvo_user_fileops
4443+};
4444+
4445+/*
4446+ * Initialization
4447+ *
4448+ * @return 0 if successful, error value otherwise.
4449+ */
4450+int tahvo_user_init(void)
4451+{
4452+ struct tahvo_irq *irq;
4453+ int res, i;
4454+
4455+ irq = kmalloc(sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN, GFP_KERNEL);
4456+ if (irq == NULL) {
4457+ printk(KERN_ERR PFX "kmalloc failed\n");
4458+ return -ENOMEM;
4459+ }
4460+ memset(irq, 0, sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN);
4461+ for (i = 0; i < TAHVO_MAX_IRQ_BUF_LEN; i++)
4462+ list_add(&irq[i].node, &tahvo_irqs_reserve);
4463+
4464+ tahvo_irq_block = irq;
4465+
4466+ spin_lock_init(&tahvo_irqs_lock);
4467+ mutex_init(&tahvo_mutex);
4468+
4469+ /* Request a misc device */
4470+ res = misc_register(&tahvo_device);
4471+ if (res < 0) {
4472+ printk(KERN_ERR PFX "unable to register misc device for %s\n",
4473+ tahvo_device.name);
4474+ kfree(irq);
4475+ return res;
4476+ }
4477+
4478+ return 0;
4479+}
4480+
4481+/*
4482+ * Cleanup.
4483+ */
4484+void tahvo_user_cleanup(void)
4485+{
4486+ /* Unregister our misc device */
4487+ misc_deregister(&tahvo_device);
4488+ /* Unregister and disable all TAHVO interrupts */
4489+ tahvo_unreg_irq_handlers();
4490+ kfree(tahvo_irq_block);
4491+}
4492+
4493+MODULE_DESCRIPTION("Tahvo ASIC user space functions");
4494+MODULE_LICENSE("GPL");
4495+MODULE_AUTHOR("Mikko Ylinen");
4496--- /dev/null
4497@@ -0,0 +1,75 @@
4498+/**
4499+ * drivers/cbus/user_retu_tahvo.h
4500+ *
4501+ * Copyright (C) 2004, 2005 Nokia Corporation
4502+ *
4503+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
4504+ *
4505+ * Definitions and types used by both retu-user and tahvo-user.
4506+ *
4507+ * This file is subject to the terms and conditions of the GNU General
4508+ * Public License. See the file "COPYING" in the main directory of this
4509+ * archive for more details.
4510+ *
4511+ * This program is distributed in the hope that it will be useful,
4512+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4513+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4514+ * GNU General Public License for more details.
4515+
4516+ * You should have received a copy of the GNU General Public License
4517+ * along with this program; if not, write to the Free Software
4518+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4519+ */
4520+
4521+#ifndef _USER_RETU_TAHVO_H
4522+#define _USER_RETU_TAHVO_H
4523+
4524+/* Chip IDs */
4525+#define CHIP_RETU 1
4526+#define CHIP_TAHVO 2
4527+
4528+/* Register access type bits */
4529+#define READ_ONLY 1
4530+#define WRITE_ONLY 2
4531+#define READ_WRITE 3
4532+#define TOGGLE 4
4533+
4534+#define MASK(field) ((u16)(field & 0xFFFF))
4535+#define REG(field) ((u16)((field >> 16) & 0x3F))
4536+
4537+/*** IOCTL definitions. These should be kept in sync with user space **********/
4538+
4539+#define URT_IOC_MAGIC '`'
4540+
4541+/*
4542+ * IOCTL function naming conventions:
4543+ * ==================================
4544+ * 0 -- No argument and return value
4545+ * S -- Set through a pointer
4546+ * T -- Tell directly with the argument value
4547+ * G -- Reply by setting through a pointer
4548+ * Q -- response is on the return value
4549+ * X -- S and G atomically
4550+ * H -- T and Q atomically
4551+ */
4552+
4553+/* General */
4554+#define URT_IOCT_IRQ_SUBSCR _IO(URT_IOC_MAGIC, 0)
4555+
4556+/* RETU */
4557+#define RETU_IOCH_READ _IO(URT_IOC_MAGIC, 1)
4558+#define RETU_IOCX_WRITE _IO(URT_IOC_MAGIC, 2)
4559+#define RETU_IOCH_ADC_READ _IO(URT_IOC_MAGIC, 3)
4560+
4561+/* TAHVO */
4562+#define TAHVO_IOCH_READ _IO(URT_IOC_MAGIC, 4)
4563+#define TAHVO_IOCX_WRITE _IO(URT_IOC_MAGIC, 5)
4564+
4565+/* This structure is used for writing RETU/TAHVO registers */
4566+struct retu_tahvo_write_parms {
4567+ u32 field;
4568+ u16 value;
4569+ u8 result;
4570+};
4571+
4572+#endif
4573--- linux-2.6.35.orig/drivers/Makefile
4574@@ -74,7 +74,7 @@ obj-$(CONFIG_GAMEPORT) += input/gamepor
4575 obj-$(CONFIG_INPUT) += input/
4576 obj-$(CONFIG_I2O) += message/
4577 obj-$(CONFIG_RTC_LIB) += rtc/
4578-obj-y += i2c/ media/
4579+obj-y += i2c/ media/ cbus/
4580 obj-$(CONFIG_PPS) += pps/
4581 obj-$(CONFIG_W1) += w1/
4582 obj-$(CONFIG_POWER_SUPPLY) += power/
4583--- linux-2.6.35.orig/arch/arm/Kconfig
4584@@ -1669,6 +1669,10 @@ source "net/Kconfig"
4585
4586 source "drivers/Kconfig"
4587
4588+if ARCH_OMAP
4589+source "drivers/cbus/Kconfig"
4590+endif
4591+
4592 source "fs/Kconfig"
4593
4594 source "arch/arm/Kconfig.debug"
target/linux/omap24xx/patches-2.6.35/600-tsc2005.patch
1---
2 drivers/input/touchscreen/Kconfig | 11
3 drivers/input/touchscreen/Makefile | 1
4 drivers/input/touchscreen/tsc2005.c | 958 ++++++++++++++++++++++++++++++++++++
5 include/linux/spi/tsc2005.h | 30 +
6 4 files changed, 1000 insertions(+)
7
8--- linux-2.6.35.orig/drivers/input/touchscreen/Kconfig
9@@ -561,6 +561,17 @@ config TOUCHSCREEN_TOUCHIT213
10       To compile this driver as a module, choose M here: the
11       module will be called touchit213.
12
13+config TOUCHSCREEN_TSC2005
14+ tristate "TSC2005 based touchscreens"
15+ depends on SPI_MASTER
16+ help
17+ Say Y here if you have a TSC2005 based touchscreen.
18+
19+ If unsure, say N.
20+
21+ To compile this driver as a module, choose M here: the
22+ module will be called tsc2005.
23+
24 config TOUCHSCREEN_TSC2007
25     tristate "TSC2007 based touchscreens"
26     depends on I2C
27--- linux-2.6.35.orig/drivers/input/touchscreen/Makefile
28@@ -34,6 +34,7 @@ obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c
29 obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o
30 obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o
31 obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o
32+obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o
33 obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o
34 obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o
35 obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001) += wacom_w8001.o
36--- /dev/null
37@@ -0,0 +1,958 @@
38+/*
39+ * TSC2005 touchscreen driver
40+ *
41+ * Copyright (C) 2006-2008 Nokia Corporation
42+ *
43+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
44+ * based on TSC2301 driver by Klaus K. Pedersen <klaus.k.pedersen@nokia.com>
45+ *
46+ * This program is free software; you can redistribute it and/or modify
47+ * it under the terms of the GNU General Public License as published by
48+ * the Free Software Foundation; either version 2 of the License, or
49+ * (at your option) any later version.
50+ *
51+ * This program is distributed in the hope that it will be useful,
52+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
53+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
54+ * GNU General Public License for more details.
55+ *
56+ * You should have received a copy of the GNU General Public License
57+ * along with this program; if not, write to the Free Software
58+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
59+ *
60+ */
61+
62+#include <linux/kernel.h>
63+#include <linux/module.h>
64+#include <linux/input.h>
65+#include <linux/interrupt.h>
66+#include <linux/delay.h>
67+#include <linux/spi/spi.h>
68+
69+#include <linux/spi/tsc2005.h>
70+
71+/**
72+ * The touchscreen interface operates as follows:
73+ *
74+ * Initialize:
75+ * Request access to GPIO103 (DAV)
76+ * tsc2005_ts_irq_handler will trigger when DAV line goes down
77+ *
78+ * 1) Pen is pressed against touchscreeen
79+ * 2) TSC2005 performs AD conversion
80+ * 3) After the conversion is done TSC2005 drives DAV line down
81+ * 4) GPIO IRQ is received and tsc2005_ts_irq_handler is called
82+ * 5) tsc2005_ts_irq_handler queues up an spi transfer to fetch
83+ * the x, y, z1, z2 values
84+ * 6) tsc2005_ts_rx() reports coordinates to input layer and
85+ * sets up tsc2005_ts_timer() to be called after TSC2005_TS_SCAN_TIME
86+ * 7) When the penup_timer expires, there have not been DAV interrupts
87+ * during the last 20ms which means the pen has been lifted.
88+ */
89+
90+#define TSC2005_VDD_LOWER_27
91+
92+#ifdef TSC2005_VDD_LOWER_27
93+#define TSC2005_HZ (10000000)
94+#else
95+#define TSC2005_HZ (25000000)
96+#endif
97+
98+#define TSC2005_CMD (0x80)
99+#define TSC2005_REG (0x00)
100+
101+#define TSC2005_CMD_STOP (1)
102+#define TSC2005_CMD_10BIT (0 << 2)
103+#define TSC2005_CMD_12BIT (1 << 2)
104+
105+#define TSC2005_CMD_SCAN_XYZZ (0 << 3)
106+#define TSC2005_CMD_SCAN_XY (1 << 3)
107+#define TSC2005_CMD_SCAN_X (2 << 3)
108+#define TSC2005_CMD_SCAN_Y (3 << 3)
109+#define TSC2005_CMD_SCAN_ZZ (4 << 3)
110+#define TSC2005_CMD_AUX_SINGLE (5 << 3)
111+#define TSC2005_CMD_TEMP1 (6 << 3)
112+#define TSC2005_CMD_TEMP2 (7 << 3)
113+#define TSC2005_CMD_AUX_CONT (8 << 3)
114+#define TSC2005_CMD_TEST_X_CONN (9 << 3)
115+#define TSC2005_CMD_TEST_Y_CONN (10 << 3)
116+#define TSC2005_CMD_TEST_SHORT (11 << 3)
117+/* command 12 reserved, according to 2008-03 erratum */
118+#define TSC2005_CMD_DRIVE_XX (13 << 3)
119+#define TSC2005_CMD_DRIVE_YY (14 << 3)
120+#define TSC2005_CMD_DRIVE_YX (15 << 3)
121+
122+#define TSC2005_REG_X (0 << 3)
123+#define TSC2005_REG_Y (1 << 3)
124+#define TSC2005_REG_Z1 (2 << 3)
125+#define TSC2005_REG_Z2 (3 << 3)
126+#define TSC2005_REG_AUX (4 << 3)
127+#define TSC2005_REG_TEMP1 (5 << 3)
128+#define TSC2005_REG_TEMP2 (6 << 3)
129+#define TSC2005_REG_STATUS (7 << 3)
130+#define TSC2005_REG_AUX_HIGH (8 << 3)
131+#define TSC2005_REG_AUX_LOW (9 << 3)
132+#define TSC2005_REG_TEMP_HIGH (10 << 3)
133+#define TSC2005_REG_TEMP_LOW (11 << 3)
134+#define TSC2005_REG_CFR0 (12 << 3)
135+#define TSC2005_REG_CFR1 (13 << 3)
136+#define TSC2005_REG_CFR2 (14 << 3)
137+#define TSC2005_REG_FUNCTION (15 << 3)
138+
139+#define TSC2005_REG_PND0 (1 << 1)
140+#define TSC2005_REG_READ (0x01)
141+#define TSC2005_REG_WRITE (0x00)
142+
143+
144+#define TSC2005_CFR0_LONGSAMPLING (1)
145+#define TSC2005_CFR0_DETECTINWAIT (1 << 1)
146+#define TSC2005_CFR0_SENSETIME_32US (0)
147+#define TSC2005_CFR0_SENSETIME_96US (1 << 2)
148+#define TSC2005_CFR0_SENSETIME_544US (1 << 3)
149+#define TSC2005_CFR0_SENSETIME_2080US (1 << 4)
150+#define TSC2005_CFR0_SENSETIME_2656US (0x001C)
151+#define TSC2005_CFR0_PRECHARGE_20US (0x0000)
152+#define TSC2005_CFR0_PRECHARGE_84US (0x0020)
153+#define TSC2005_CFR0_PRECHARGE_276US (0x0040)
154+#define TSC2005_CFR0_PRECHARGE_1044US (0x0080)
155+#define TSC2005_CFR0_PRECHARGE_1364US (0x00E0)
156+#define TSC2005_CFR0_STABTIME_0US (0x0000)
157+#define TSC2005_CFR0_STABTIME_100US (0x0100)
158+#define TSC2005_CFR0_STABTIME_500US (0x0200)
159+#define TSC2005_CFR0_STABTIME_1MS (0x0300)
160+#define TSC2005_CFR0_STABTIME_5MS (0x0400)
161+#define TSC2005_CFR0_STABTIME_100MS (0x0700)
162+#define TSC2005_CFR0_CLOCK_4MHZ (0x0000)
163+#define TSC2005_CFR0_CLOCK_2MHZ (0x0800)
164+#define TSC2005_CFR0_CLOCK_1MHZ (0x1000)
165+#define TSC2005_CFR0_RESOLUTION12 (0x2000)
166+#define TSC2005_CFR0_STATUS (0x4000)
167+#define TSC2005_CFR0_PENMODE (0x8000)
168+
169+#define TSC2005_CFR0_INITVALUE (TSC2005_CFR0_STABTIME_1MS | \
170+ TSC2005_CFR0_CLOCK_1MHZ | \
171+ TSC2005_CFR0_RESOLUTION12 | \
172+ TSC2005_CFR0_PRECHARGE_276US | \
173+ TSC2005_CFR0_PENMODE)
174+
175+/* Bits common to both read and write of config register 0 */
176+#define TSC2005_CFR0_RW_MASK 0x3fff
177+
178+#define TSC2005_CFR1_BATCHDELAY_0MS (0x0000)
179+#define TSC2005_CFR1_BATCHDELAY_1MS (0x0001)
180+#define TSC2005_CFR1_BATCHDELAY_2MS (0x0002)
181+#define TSC2005_CFR1_BATCHDELAY_4MS (0x0003)
182+#define TSC2005_CFR1_BATCHDELAY_10MS (0x0004)
183+#define TSC2005_CFR1_BATCHDELAY_20MS (0x0005)
184+#define TSC2005_CFR1_BATCHDELAY_40MS (0x0006)
185+#define TSC2005_CFR1_BATCHDELAY_100MS (0x0007)
186+
187+#define TSC2005_CFR1_INITVALUE (TSC2005_CFR1_BATCHDELAY_4MS)
188+
189+#define TSC2005_CFR2_MAVE_TEMP (0x0001)
190+#define TSC2005_CFR2_MAVE_AUX (0x0002)
191+#define TSC2005_CFR2_MAVE_Z (0x0004)
192+#define TSC2005_CFR2_MAVE_Y (0x0008)
193+#define TSC2005_CFR2_MAVE_X (0x0010)
194+#define TSC2005_CFR2_AVG_1 (0x0000)
195+#define TSC2005_CFR2_AVG_3 (0x0400)
196+#define TSC2005_CFR2_AVG_7 (0x0800)
197+#define TSC2005_CFR2_MEDIUM_1 (0x0000)
198+#define TSC2005_CFR2_MEDIUM_3 (0x1000)
199+#define TSC2005_CFR2_MEDIUM_7 (0x2000)
200+#define TSC2005_CFR2_MEDIUM_15 (0x3000)
201+
202+#define TSC2005_CFR2_IRQ_MASK (0xC000)
203+#define TSC2005_CFR2_IRQ_DAV (0x4000)
204+#define TSC2005_CFR2_IRQ_PEN (0x8000)
205+#define TSC2005_CFR2_IRQ_PENDAV (0x0000)
206+
207+#define TSC2005_CFR2_INITVALUE (TSC2005_CFR2_IRQ_PENDAV | \
208+ TSC2005_CFR2_MAVE_X | \
209+ TSC2005_CFR2_MAVE_Y | \
210+ TSC2005_CFR2_MAVE_Z | \
211+ TSC2005_CFR2_MEDIUM_15 | \
212+ TSC2005_CFR2_AVG_7)
213+
214+#define MAX_12BIT ((1 << 12) - 1)
215+#define TS_SAMPLES 4
216+#define TSC2005_TS_PENUP_TIME 40
217+
218+static const u32 tsc2005_read_reg[] = {
219+ (TSC2005_REG | TSC2005_REG_X | TSC2005_REG_READ) << 16,
220+ (TSC2005_REG | TSC2005_REG_Y | TSC2005_REG_READ) << 16,
221+ (TSC2005_REG | TSC2005_REG_Z1 | TSC2005_REG_READ) << 16,
222+ (TSC2005_REG | TSC2005_REG_Z2 | TSC2005_REG_READ) << 16,
223+};
224+#define NUM_READ_REGS (sizeof(tsc2005_read_reg)/sizeof(tsc2005_read_reg[0]))
225+
226+struct tsc2005 {
227+ struct spi_device *spi;
228+
229+ struct input_dev *idev;
230+ char phys[32];
231+ struct timer_list penup_timer;
232+
233+ /* ESD recovery via a hardware reset if the tsc2005
234+ * doesn't respond after a configurable period (in ms) of
235+ * IRQ/SPI inactivity. If esd_timeout is 0, timer and work
236+ * fields are used.
237+ */
238+ u32 esd_timeout;
239+ struct timer_list esd_timer;
240+ struct work_struct esd_work;
241+
242+ spinlock_t lock;
243+ struct mutex mutex;
244+
245+ struct spi_message read_msg;
246+ struct spi_transfer read_xfer[NUM_READ_REGS];
247+ u32 data[NUM_READ_REGS];
248+
249+ /* previously reported x,y,p (if pen_down) */
250+ int out_x;
251+ int out_y;
252+ int out_p;
253+ /* fudge parameters - changes must exceed one of these. */
254+ int fudge_x;
255+ int fudge_y;
256+ int fudge_p;
257+ /* raw copy of previous x,y,z */
258+ int in_x;
259+ int in_y;
260+ int in_z1;
261+ int in_z2;
262+ /* average accumulators for each component */
263+ int sample_cnt;
264+ int avg_x;
265+ int avg_y;
266+ int avg_z1;
267+ int avg_z2;
268+ /* configuration */
269+ int x_plate_ohm;
270+ int hw_avg_max;
271+ int stab_time;
272+ int p_max;
273+ int touch_pressure;
274+ /* status */
275+ u8 sample_sent;
276+ u8 pen_down;
277+ u8 disabled;
278+ u8 disable_depth;
279+ u8 spi_pending;
280+
281+ void (*set_reset)(bool enable);
282+};
283+
284+static void tsc2005_cmd(struct tsc2005 *ts, u8 cmd)
285+{
286+ u8 data = TSC2005_CMD | TSC2005_CMD_12BIT | cmd;
287+ struct spi_message msg;
288+ struct spi_transfer xfer = { 0 };
289+
290+ xfer.tx_buf = &data;
291+ xfer.rx_buf = NULL;
292+ xfer.len = 1;
293+ xfer.bits_per_word = 8;
294+
295+ spi_message_init(&msg);
296+ spi_message_add_tail(&xfer, &msg);
297+ spi_sync(ts->spi, &msg);
298+}
299+
300+static void tsc2005_write(struct tsc2005 *ts, u8 reg, u16 value)
301+{
302+ u32 tx;
303+ struct spi_message msg;
304+ struct spi_transfer xfer = { 0 };
305+
306+ tx = (TSC2005_REG | reg | TSC2005_REG_PND0 |
307+ TSC2005_REG_WRITE) << 16;
308+ tx |= value;
309+
310+ xfer.tx_buf = &tx;
311+ xfer.rx_buf = NULL;
312+ xfer.len = 4;
313+ xfer.bits_per_word = 24;
314+
315+ spi_message_init(&msg);
316+ spi_message_add_tail(&xfer, &msg);
317+ spi_sync(ts->spi, &msg);
318+}
319+
320+static void tsc2005_read(struct tsc2005 *ts, u8 reg, u16 *value)
321+{
322+ u32 tx;
323+ u32 rx = 0;
324+ struct spi_message msg;
325+ struct spi_transfer xfer = { 0 };
326+
327+ tx = (TSC2005_REG | reg | TSC2005_REG_READ) << 16;
328+
329+ xfer.tx_buf = &tx;
330+ xfer.rx_buf = &rx;
331+ xfer.len = 4;
332+ xfer.bits_per_word = 24;
333+
334+ spi_message_init(&msg);
335+ spi_message_add_tail(&xfer, &msg);
336+ spi_sync(ts->spi, &msg);
337+ *value = rx;
338+}
339+
340+static void tsc2005_ts_update_pen_state(struct tsc2005 *ts,
341+ int x, int y, int pressure)
342+{
343+ if (pressure) {
344+ input_report_abs(ts->idev, ABS_X, x);
345+ input_report_abs(ts->idev, ABS_Y, y);
346+ input_report_abs(ts->idev, ABS_PRESSURE, pressure);
347+ if (!ts->pen_down) {
348+ input_report_key(ts->idev, BTN_TOUCH, 1);
349+ ts->pen_down = 1;
350+ }
351+ } else {
352+ input_report_abs(ts->idev, ABS_PRESSURE, 0);
353+ if (ts->pen_down) {
354+ input_report_key(ts->idev, BTN_TOUCH, 0);
355+ ts->pen_down = 0;
356+ }
357+ }
358+
359+ input_sync(ts->idev);
360+}
361+
362+/*
363+ * This function is called by the SPI framework after the coordinates
364+ * have been read from TSC2005
365+ */
366+static void tsc2005_ts_rx(void *arg)
367+{
368+ struct tsc2005 *ts = arg;
369+ unsigned long flags;
370+ int inside_rect, pressure_limit;
371+ int x, y, z1, z2, pressure;
372+
373+ spin_lock_irqsave(&ts->lock, flags);
374+
375+ if (ts->disable_depth) {
376+ ts->spi_pending = 0;
377+ goto out;
378+ }
379+
380+ x = ts->data[0];
381+ y = ts->data[1];
382+ z1 = ts->data[2];
383+ z2 = ts->data[3];
384+
385+ /* validate pressure and position */
386+ if (x > MAX_12BIT || y > MAX_12BIT)
387+ goto out;
388+
389+ /* skip coords if the pressure-components are out of range */
390+ if (z1 < 100 || z2 > MAX_12BIT || z1 >= z2)
391+ goto out;
392+
393+ /* skip point if this is a pen down with the exact same values as
394+ * the value before pen-up - that implies SPI fed us stale data
395+ */
396+ if (!ts->pen_down &&
397+ ts->in_x == x &&
398+ ts->in_y == y &&
399+ ts->in_z1 == z1 &&
400+ ts->in_z2 == z2)
401+ goto out;
402+
403+ /* At this point we are happy we have a valid and useful reading.
404+ * Remember it for later comparisons. We may now begin downsampling
405+ */
406+ ts->in_x = x;
407+ ts->in_y = y;
408+ ts->in_z1 = z1;
409+ ts->in_z2 = z2;
410+
411+ /* don't run average on the "pen down" event */
412+ if (ts->sample_sent) {
413+ ts->avg_x += x;
414+ ts->avg_y += y;
415+ ts->avg_z1 += z1;
416+ ts->avg_z2 += z2;
417+
418+ if (++ts->sample_cnt < TS_SAMPLES)
419+ goto out;
420+
421+ x = ts->avg_x / TS_SAMPLES;
422+ y = ts->avg_y / TS_SAMPLES;
423+ z1 = ts->avg_z1 / TS_SAMPLES;
424+ z2 = ts->avg_z2 / TS_SAMPLES;
425+ }
426+
427+ ts->sample_cnt = 0;
428+ ts->avg_x = 0;
429+ ts->avg_y = 0;
430+ ts->avg_z1 = 0;
431+ ts->avg_z2 = 0;
432+
433+ pressure = x * (z2 - z1) / z1;
434+ pressure = pressure * ts->x_plate_ohm / 4096;
435+
436+ pressure_limit = ts->sample_sent ? ts->p_max : ts->touch_pressure;
437+ if (pressure > pressure_limit)
438+ goto out;
439+
440+ /* Discard the event if it still is within the previous rect -
441+ * unless the pressure is clearly harder, but then use previous
442+ * x,y position. If any coordinate deviates enough, fudging
443+ * of all three will still take place in the input layer.
444+ */
445+ inside_rect = (ts->sample_sent &&
446+ x > (int)ts->out_x - ts->fudge_x &&
447+ x < (int)ts->out_x + ts->fudge_x &&
448+ y > (int)ts->out_y - ts->fudge_y &&
449+ y < (int)ts->out_y + ts->fudge_y);
450+ if (inside_rect)
451+ x = ts->out_x, y = ts->out_y;
452+
453+ if (!inside_rect || pressure < (ts->out_p - ts->fudge_p)) {
454+ tsc2005_ts_update_pen_state(ts, x, y, pressure);
455+ ts->sample_sent = 1;
456+ ts->out_x = x;
457+ ts->out_y = y;
458+ ts->out_p = pressure;
459+ }
460+out:
461+ if (ts->spi_pending > 1) {
462+ /* One or more interrupts (sometimes several dozens)
463+ * occured while waiting for the SPI read - get
464+ * another read going.
465+ */
466+ ts->spi_pending = 1;
467+ if (spi_async(ts->spi, &ts->read_msg)) {
468+ dev_err(&ts->spi->dev, "ts: spi_async() failed");
469+ ts->spi_pending = 0;
470+ }
471+ } else
472+ ts->spi_pending = 0;
473+
474+ /* kick pen up timer - to make sure it expires again(!) */
475+ if (ts->sample_sent) {
476+ mod_timer(&ts->penup_timer,
477+ jiffies + msecs_to_jiffies(TSC2005_TS_PENUP_TIME));
478+ /* Also kick the watchdog, as we still think we're alive */
479+ if (ts->esd_timeout && ts->disable_depth == 0) {
480+ unsigned long wdj = msecs_to_jiffies(ts->esd_timeout);
481+ mod_timer(&ts->esd_timer, round_jiffies(jiffies+wdj));
482+ }
483+ }
484+ spin_unlock_irqrestore(&ts->lock, flags);
485+}
486+
487+/* This penup timer is very forgiving of delayed SPI reads. The
488+ * (ESD) watchdog will rescue us if spi_pending remains set, unless
489+ * we are enterring the disabled state. In that case we must just
490+ * handle the pen up, and let disabling complete.
491+ */
492+static void tsc2005_ts_penup_timer_handler(unsigned long data)
493+{
494+ struct tsc2005 *ts = (struct tsc2005 *)data;
495+ if ((!ts->spi_pending || ts->disable_depth) &&
496+ ts->sample_sent) {
497+ tsc2005_ts_update_pen_state(ts, 0, 0, 0);
498+ ts->sample_sent = 0;
499+ }
500+}
501+
502+/*
503+ * This interrupt is called when pen is down and coordinates are
504+ * available. That is indicated by a either:
505+ * a) a rising edge on PINTDAV or (PENDAV mode)
506+ * b) a falling edge on DAV line (DAV mode)
507+ * depending on the setting of the IRQ bits in the CFR2 setting above.
508+ */
509+static irqreturn_t tsc2005_ts_irq_handler(int irq, void *dev_id)
510+{
511+ struct tsc2005 *ts = dev_id;
512+ if (ts->disable_depth)
513+ goto out;
514+
515+ if (!ts->spi_pending) {
516+ if (spi_async(ts->spi, &ts->read_msg)) {
517+ dev_err(&ts->spi->dev, "ts: spi_async() failed");
518+ goto out;
519+ }
520+ }
521+ /* By shifting in 1s we can never wrap */
522+ ts->spi_pending = (ts->spi_pending<<1)+1;
523+
524+ /* Kick pen up timer only if it's not been started yet. Strictly,
525+ * it isn't even necessary to start it at all here, but doing so
526+ * keeps an equivalence between pen state and timer state.
527+ * The SPI read loop will keep pushing it into the future.
528+ * If it times out with an SPI pending, it's ignored anyway.
529+ */
530+ if (!timer_pending(&ts->penup_timer)) {
531+ unsigned long pu = msecs_to_jiffies(TSC2005_TS_PENUP_TIME);
532+ ts->penup_timer.expires = jiffies + pu;
533+ add_timer(&ts->penup_timer);
534+ }
535+out:
536+ return IRQ_HANDLED;
537+}
538+
539+static void tsc2005_ts_setup_spi_xfer(struct tsc2005 *ts)
540+{
541+ struct spi_message *m = &ts->read_msg;
542+ struct spi_transfer *x = &ts->read_xfer[0];
543+ int i;
544+
545+ spi_message_init(m);
546+
547+ for (i = 0; i < NUM_READ_REGS; i++, x++) {
548+ x->tx_buf = &tsc2005_read_reg[i];
549+ x->rx_buf = &ts->data[i];
550+ x->len = 4;
551+ x->bits_per_word = 24;
552+ x->cs_change = i < (NUM_READ_REGS - 1);
553+ spi_message_add_tail(x, m);
554+ }
555+
556+ m->complete = tsc2005_ts_rx;
557+ m->context = ts;
558+}
559+
560+static ssize_t tsc2005_ts_pen_down_show(struct device *dev,
561+ struct device_attribute *attr,
562+ char *buf)
563+{
564+ struct tsc2005 *ts = dev_get_drvdata(dev);
565+
566+ return sprintf(buf, "%u\n", ts->pen_down);
567+}
568+
569+static DEVICE_ATTR(pen_down, S_IRUGO, tsc2005_ts_pen_down_show, NULL);
570+
571+static int tsc2005_configure(struct tsc2005 *ts, int flags)
572+{
573+ tsc2005_write(ts, TSC2005_REG_CFR0, TSC2005_CFR0_INITVALUE);
574+ tsc2005_write(ts, TSC2005_REG_CFR1, TSC2005_CFR1_INITVALUE);
575+ tsc2005_write(ts, TSC2005_REG_CFR2, TSC2005_CFR2_INITVALUE);
576+ tsc2005_cmd(ts, flags);
577+
578+ return 0;
579+}
580+
581+static void tsc2005_start_scan(struct tsc2005 *ts)
582+{
583+ tsc2005_configure(ts, TSC2005_CMD_SCAN_XYZZ);
584+}
585+
586+static void tsc2005_stop_scan(struct tsc2005 *ts)
587+{
588+ tsc2005_cmd(ts, TSC2005_CMD_STOP);
589+}
590+
591+/* Must be called with mutex held */
592+static void tsc2005_disable(struct tsc2005 *ts)
593+{
594+ if (ts->disable_depth++ != 0)
595+ return;
596+
597+ disable_irq(ts->spi->irq);
598+ if (ts->esd_timeout)
599+ del_timer(&ts->esd_timer);
600+
601+ /* wait until penup timer expire normally */
602+ do {
603+ msleep(4);
604+ } while (ts->sample_sent);
605+
606+ tsc2005_stop_scan(ts);
607+}
608+
609+static void tsc2005_enable(struct tsc2005 *ts)
610+{
611+ if (ts->disable_depth != 1)
612+ goto out;
613+
614+ if (ts->esd_timeout) {
615+ unsigned long wdj = msecs_to_jiffies(ts->esd_timeout);
616+ ts->esd_timer.expires = round_jiffies(jiffies+wdj);
617+ add_timer(&ts->esd_timer);
618+ }
619+ tsc2005_start_scan(ts);
620+ enable_irq(ts->spi->irq);
621+out:
622+ --ts->disable_depth;
623+}
624+
625+static ssize_t tsc2005_disable_show(struct device *dev,
626+ struct device_attribute *attr, char *buf)
627+{
628+ struct tsc2005 *ts = dev_get_drvdata(dev);
629+
630+ return sprintf(buf, "%u\n", ts->disabled);
631+}
632+
633+static ssize_t tsc2005_disable_store(struct device *dev,
634+ struct device_attribute *attr,
635+ const char *buf, size_t count)
636+{
637+ struct tsc2005 *ts = dev_get_drvdata(dev);
638+ unsigned long res;
639+ int i;
640+
641+ if (strict_strtoul(buf, 10, &res) < 0)
642+ return -EINVAL;
643+ i = res ? 1 : 0;
644+
645+ mutex_lock(&ts->mutex);
646+ if (i == ts->disabled)
647+ goto out;
648+ ts->disabled = i;
649+
650+ if (i)
651+ tsc2005_disable(ts);
652+ else
653+ tsc2005_enable(ts);
654+out:
655+ mutex_unlock(&ts->mutex);
656+ return count;
657+}
658+
659+static DEVICE_ATTR(disable_ts, 0664, tsc2005_disable_show,
660+ tsc2005_disable_store);
661+
662+static ssize_t tsc2005_ctrl_selftest_show(struct device *dev,
663+ struct device_attribute *attr,
664+ char *buf)
665+{
666+ u16 temp_high_orig, temp_high_test, temp_high;
667+ unsigned int result = 1;
668+ struct tsc2005 *ts = dev_get_drvdata(dev);
669+
670+ if (!ts->set_reset) {
671+ dev_warn(&ts->spi->dev,
672+ "unable to selftest: reset not configured\n");
673+ result = 0;
674+ goto out;
675+ }
676+
677+ mutex_lock(&ts->mutex);
678+ tsc2005_disable(ts);
679+
680+ /* Test ctrl communications via temp high / low registers */
681+ tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high_orig);
682+
683+ temp_high_test = (temp_high_orig - 1) & 0x0FFF;
684+
685+ tsc2005_write(ts, TSC2005_REG_TEMP_HIGH, temp_high_test);
686+
687+ tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high);
688+
689+ if (temp_high != temp_high_test) {
690+ result = 0;
691+ dev_warn(dev, "selftest failed: %d != %d\n",
692+ temp_high, temp_high_test);
693+ }
694+
695+ /* HW Reset */
696+ ts->set_reset(0);
697+ msleep(1); /* only 10us required */
698+ ts->set_reset(1);
699+
700+ tsc2005_enable(ts);
701+
702+ /* Test that reset really happened */
703+ tsc2005_read(ts, TSC2005_REG_TEMP_HIGH, &temp_high);
704+
705+ if (temp_high != temp_high_orig) {
706+ result = 0;
707+ dev_warn(dev, "selftest failed after reset: "
708+ "%d != %d\n",
709+ temp_high, temp_high_orig);
710+ }
711+
712+ mutex_unlock(&ts->mutex);
713+
714+out:
715+ return sprintf(buf, "%u\n", result);
716+}
717+
718+static DEVICE_ATTR(ts_ctrl_selftest, S_IRUGO, tsc2005_ctrl_selftest_show, NULL);
719+
720+static void tsc2005_esd_timer_handler(unsigned long data)
721+{
722+ struct tsc2005 *ts = (struct tsc2005 *)data;
723+ if (!ts->disable_depth)
724+ schedule_work(&ts->esd_work);
725+}
726+
727+static void tsc2005_rst_handler(struct work_struct *work)
728+{
729+ u16 reg_val;
730+ struct tsc2005 *ts = container_of(work, struct tsc2005, esd_work);
731+ unsigned long wdj;
732+
733+ mutex_lock(&ts->mutex);
734+
735+ /* If we are disabled, or the a touch has been detected,
736+ * then ignore this timeout. The enable will restart the
737+ * watchdog, as it restarts scanning
738+ */
739+ if (ts->disable_depth)
740+ goto out;
741+
742+ /* If we cannot read our known value from configuration register 0
743+ * then reset the controller as if from power-up and start
744+ * scanning again. Always re-arm the watchdog.
745+ */
746+ tsc2005_read(ts, TSC2005_REG_CFR0, &reg_val);
747+ if ((reg_val ^ TSC2005_CFR0_INITVALUE) & TSC2005_CFR0_RW_MASK) {
748+ dev_info(&ts->spi->dev, "TSC not responding, resetting.\n");
749+ /* If this timer kicked in, the penup timer, if ever active
750+ * at all, must have expired ages ago, so no need to del it.
751+ */
752+ ts->set_reset(0);
753+ if (ts->sample_sent) {
754+ tsc2005_ts_update_pen_state(ts, 0, 0, 0);
755+ ts->sample_sent = 0;
756+ }
757+ ts->spi_pending = 0;
758+ msleep(1); /* only 10us required */
759+ ts->set_reset(1);
760+ tsc2005_start_scan(ts);
761+ }
762+ wdj = msecs_to_jiffies(ts->esd_timeout);
763+ mod_timer(&ts->esd_timer, round_jiffies(jiffies+wdj));
764+
765+out:
766+ mutex_unlock(&ts->mutex);
767+}
768+
769+static int __devinit tsc2005_ts_init(struct tsc2005 *ts,
770+ struct tsc2005_platform_data *pdata)
771+{
772+ struct input_dev *idev;
773+ int r;
774+ int x_max, y_max;
775+
776+ init_timer(&ts->penup_timer);
777+ setup_timer(&ts->penup_timer, tsc2005_ts_penup_timer_handler,
778+ (unsigned long)ts);
779+
780+ spin_lock_init(&ts->lock);
781+ mutex_init(&ts->mutex);
782+
783+ ts->x_plate_ohm = pdata->ts_x_plate_ohm ? : 280;
784+ ts->hw_avg_max = pdata->ts_hw_avg;
785+ ts->stab_time = pdata->ts_stab_time;
786+ x_max = pdata->ts_x_max ? : 4096;
787+ ts->fudge_x = pdata->ts_x_fudge ? : 4;
788+ y_max = pdata->ts_y_max ? : 4096;
789+ ts->fudge_y = pdata->ts_y_fudge ? : 8;
790+ ts->p_max = pdata->ts_pressure_max ? : MAX_12BIT;
791+ ts->touch_pressure = pdata->ts_touch_pressure ? : ts->p_max;
792+ ts->fudge_p = pdata->ts_pressure_fudge ? : 2;
793+
794+ ts->set_reset = pdata->set_reset;
795+
796+ idev = input_allocate_device();
797+ if (idev == NULL) {
798+ r = -ENOMEM;
799+ goto err1;
800+ }
801+
802+ idev->name = "TSC2005 touchscreen";
803+ snprintf(ts->phys, sizeof(ts->phys), "%s/input-ts",
804+ dev_name(&ts->spi->dev));
805+ idev->phys = ts->phys;
806+
807+ idev->evbit[0] = BIT(EV_ABS) | BIT(EV_KEY);
808+ idev->absbit[0] = BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE);
809+ idev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
810+ ts->idev = idev;
811+
812+ tsc2005_ts_setup_spi_xfer(ts);
813+
814+ input_set_abs_params(idev, ABS_X, 0, x_max, ts->fudge_x, 0);
815+ input_set_abs_params(idev, ABS_Y, 0, y_max, ts->fudge_y, 0);
816+ input_set_abs_params(idev, ABS_PRESSURE, 0, ts->p_max, ts->fudge_p, 0);
817+
818+ tsc2005_start_scan(ts);
819+
820+ r = request_irq(ts->spi->irq, tsc2005_ts_irq_handler,
821+ (((TSC2005_CFR2_INITVALUE & TSC2005_CFR2_IRQ_MASK) ==
822+ TSC2005_CFR2_IRQ_PENDAV)
823+ ? IRQF_TRIGGER_RISING
824+ : IRQF_TRIGGER_FALLING) |
825+ IRQF_DISABLED, "tsc2005", ts);
826+ if (r < 0) {
827+ dev_err(&ts->spi->dev, "unable to get DAV IRQ");
828+ goto err2;
829+ }
830+
831+ set_irq_wake(ts->spi->irq, 1);
832+
833+ r = input_register_device(idev);
834+ if (r < 0) {
835+ dev_err(&ts->spi->dev, "can't register touchscreen device\n");
836+ goto err3;
837+ }
838+
839+ /* We can tolerate these failing */
840+ r = device_create_file(&ts->spi->dev, &dev_attr_ts_ctrl_selftest);
841+ if (r < 0)
842+ dev_warn(&ts->spi->dev, "can't create sysfs file for %s: %d\n",
843+ dev_attr_ts_ctrl_selftest.attr.name, r);
844+
845+ r = device_create_file(&ts->spi->dev, &dev_attr_pen_down);
846+ if (r < 0)
847+ dev_warn(&ts->spi->dev, "can't create sysfs file for %s: %d\n",
848+ dev_attr_pen_down.attr.name, r);
849+
850+ r = device_create_file(&ts->spi->dev, &dev_attr_disable_ts);
851+ if (r < 0)
852+ dev_warn(&ts->spi->dev, "can't create sysfs file for %s: %d\n",
853+ dev_attr_disable_ts.attr.name, r);
854+
855+ /* Finally, configure and start the optional EDD watchdog. */
856+ ts->esd_timeout = pdata->esd_timeout;
857+ if (ts->esd_timeout && ts->set_reset) {
858+ unsigned long wdj;
859+ setup_timer(&ts->esd_timer, tsc2005_esd_timer_handler,
860+ (unsigned long)ts);
861+ INIT_WORK(&ts->esd_work, tsc2005_rst_handler);
862+ wdj = msecs_to_jiffies(ts->esd_timeout);
863+ ts->esd_timer.expires = round_jiffies(jiffies+wdj);
864+ add_timer(&ts->esd_timer);
865+ }
866+
867+ return 0;
868+err3:
869+ free_irq(ts->spi->irq, ts);
870+err2:
871+ tsc2005_stop_scan(ts);
872+ input_free_device(idev);
873+err1:
874+ return r;
875+}
876+
877+static int __devinit tsc2005_probe(struct spi_device *spi)
878+{
879+ struct tsc2005 *ts;
880+ struct tsc2005_platform_data *pdata = spi->dev.platform_data;
881+ int r;
882+
883+ if (spi->irq < 0) {
884+ dev_dbg(&spi->dev, "no irq?\n");
885+ return -ENODEV;
886+ }
887+ if (!pdata) {
888+ dev_dbg(&spi->dev, "no platform data?\n");
889+ return -ENODEV;
890+ }
891+
892+ ts = kzalloc(sizeof(*ts), GFP_KERNEL);
893+ if (ts == NULL)
894+ return -ENOMEM;
895+
896+ dev_set_drvdata(&spi->dev, ts);
897+ ts->spi = spi;
898+ spi->dev.power.power_state = PMSG_ON;
899+
900+ spi->mode = SPI_MODE_0;
901+ spi->bits_per_word = 8;
902+ /* The max speed might've been defined by the board-specific
903+ * struct */
904+ if (!spi->max_speed_hz)
905+ spi->max_speed_hz = TSC2005_HZ;
906+
907+ spi_setup(spi);
908+
909+ r = tsc2005_ts_init(ts, pdata);
910+ if (r)
911+ goto err1;
912+
913+ return 0;
914+
915+err1:
916+ kfree(ts);
917+ return r;
918+}
919+
920+static int __devexit tsc2005_remove(struct spi_device *spi)
921+{
922+ struct tsc2005 *ts = dev_get_drvdata(&spi->dev);
923+
924+ mutex_lock(&ts->mutex);
925+ tsc2005_disable(ts);
926+ mutex_unlock(&ts->mutex);
927+
928+ device_remove_file(&ts->spi->dev, &dev_attr_disable_ts);
929+ device_remove_file(&ts->spi->dev, &dev_attr_pen_down);
930+ device_remove_file(&ts->spi->dev, &dev_attr_ts_ctrl_selftest);
931+
932+ free_irq(ts->spi->irq, ts);
933+ input_unregister_device(ts->idev);
934+
935+ if (ts->esd_timeout)
936+ del_timer(&ts->esd_timer);
937+ kfree(ts);
938+
939+ return 0;
940+}
941+
942+#ifdef CONFIG_PM
943+static int tsc2005_suspend(struct spi_device *spi, pm_message_t mesg)
944+{
945+ struct tsc2005 *ts = dev_get_drvdata(&spi->dev);
946+
947+ mutex_lock(&ts->mutex);
948+ tsc2005_disable(ts);
949+ mutex_unlock(&ts->mutex);
950+
951+ return 0;
952+}
953+
954+static int tsc2005_resume(struct spi_device *spi)
955+{
956+ struct tsc2005 *ts = dev_get_drvdata(&spi->dev);
957+
958+ mutex_lock(&ts->mutex);
959+ tsc2005_enable(ts);
960+ mutex_unlock(&ts->mutex);
961+
962+ return 0;
963+}
964+#endif
965+
966+static struct spi_driver tsc2005_driver = {
967+ .driver = {
968+ .name = "tsc2005",
969+ .owner = THIS_MODULE,
970+ },
971+#ifdef CONFIG_PM
972+ .suspend = tsc2005_suspend,
973+ .resume = tsc2005_resume,
974+#endif
975+ .probe = tsc2005_probe,
976+ .remove = __devexit_p(tsc2005_remove),
977+};
978+
979+static int __init tsc2005_init(void)
980+{
981+ printk(KERN_INFO "TSC2005 driver initializing\n");
982+
983+ return spi_register_driver(&tsc2005_driver);
984+}
985+module_init(tsc2005_init);
986+
987+static void __exit tsc2005_exit(void)
988+{
989+ spi_unregister_driver(&tsc2005_driver);
990+}
991+module_exit(tsc2005_exit);
992+
993+MODULE_AUTHOR("Lauri Leukkunen <lauri.leukkunen@nokia.com>");
994+MODULE_LICENSE("GPL");
995+MODULE_ALIAS("platform:tsc2005");
996--- /dev/null
997@@ -0,0 +1,30 @@
998+#ifndef _LINUX_SPI_TSC2005_H
999+#define _LINUX_SPI_TSC2005_H
1000+
1001+#include <linux/types.h>
1002+
1003+struct tsc2005_platform_data {
1004+ u16 ts_x_plate_ohm;
1005+ u32 ts_stab_time; /* voltage settling time */
1006+ u8 ts_hw_avg; /* HW assiseted averaging. Can be
1007+ 0, 4, 8, 16 samples per reading */
1008+ u32 ts_touch_pressure; /* Pressure limit until we report a
1009+ touch event. After that we switch
1010+ to ts_max_pressure. */
1011+ u32 ts_pressure_max;/* Samples with bigger pressure value will
1012+ be ignored, since the corresponding X, Y
1013+ values are unreliable */
1014+ u32 ts_pressure_fudge;
1015+ u32 ts_x_max;
1016+ u32 ts_x_fudge;
1017+ u32 ts_y_max;
1018+ u32 ts_y_fudge;
1019+
1020+ u32 esd_timeout; /* msec of inactivity before we check */
1021+
1022+ unsigned ts_ignore_last:1;
1023+
1024+ void (*set_reset)(bool enable);
1025+};
1026+
1027+#endif
target/linux/omap24xx/patches-2.6.35/700-video-omap.patch
1Index: linux-2.6.35/drivers/video/omap/dispc.c
2===================================================================
3--- linux-2.6.35.orig/drivers/video/omap/dispc.c 2010-08-08 12:56:09.000000000 +0200
4@@ -190,6 +190,11 @@ static struct {
5     struct omapfb_color_key color_key;
6 } dispc;
7
8+struct platform_device omapdss_device = {
9+ .name = "omapdss",
10+ .id = -1,
11+};
12+
13 static void enable_lcd_clocks(int enable);
14
15 static void inline dispc_write_reg(int idx, u32 val)
16@@ -916,20 +921,20 @@ static irqreturn_t omap_dispc_irq_handle
17
18 static int get_dss_clocks(void)
19 {
20- dispc.dss_ick = clk_get(&dispc.fbdev->dssdev->dev, "ick");
21+ dispc.dss_ick = clk_get(&omapdss_device.dev, "ick");
22     if (IS_ERR(dispc.dss_ick)) {
23         dev_err(dispc.fbdev->dev, "can't get ick\n");
24         return PTR_ERR(dispc.dss_ick);
25     }
26
27- dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "dss1_fck");
28+ dispc.dss1_fck = clk_get(&omapdss_device.dev, "dss1_fck");
29     if (IS_ERR(dispc.dss1_fck)) {
30         dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
31         clk_put(dispc.dss_ick);
32         return PTR_ERR(dispc.dss1_fck);
33     }
34
35- dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "tv_fck");
36+ dispc.dss_54m_fck = clk_get(&omapdss_device.dev, "tv_fck");
37     if (IS_ERR(dispc.dss_54m_fck)) {
38         dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
39         clk_put(dispc.dss_ick);
40@@ -1381,6 +1386,12 @@ static int omap_dispc_init(struct omapfb
41     int skip_init = 0;
42     int i;
43
44+ r = platform_device_register(&omapdss_device);
45+ if (r) {
46+ dev_err(fbdev->dev, "can't register omapdss device\n");
47+ return r;
48+ }
49+
50     memset(&dispc, 0, sizeof(dispc));
51
52     dispc.base = ioremap(DISPC_BASE, SZ_1K);
53@@ -1524,6 +1535,7 @@ static void omap_dispc_cleanup(void)
54     free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
55     put_dss_clocks();
56     iounmap(dispc.base);
57+ platform_device_unregister(&omapdss_device);
58 }
59
60 const struct lcd_ctrl omap2_int_ctrl = {
61Index: linux-2.6.35/drivers/video/omap/lcd_htcherald.c
62===================================================================
63--- linux-2.6.35.orig/drivers/video/omap/lcd_htcherald.c 2010-08-08 12:56:09.000000000 +0200
64@@ -115,12 +115,12 @@ struct platform_driver htcherald_panel_d
65     },
66 };
67
68-static int __init htcherald_panel_drv_init(void)
69+static int htcherald_panel_drv_init(void)
70 {
71     return platform_driver_register(&htcherald_panel_driver);
72 }
73
74-static void __exit htcherald_panel_drv_cleanup(void)
75+static void htcherald_panel_drv_cleanup(void)
76 {
77     platform_driver_unregister(&htcherald_panel_driver);
78 }
79Index: linux-2.6.35/drivers/video/omap/lcd_mipid.c
80===================================================================
81--- linux-2.6.35.orig/drivers/video/omap/lcd_mipid.c 2010-08-08 12:56:09.000000000 +0200
82@@ -551,9 +551,9 @@ static int mipid_detect(struct mipid_dev
83         md->esd_check = ls041y3_esd_check;
84         break;
85     default:
86- md->panel.name = "unknown";
87- dev_err(&md->spi->dev, "invalid display ID\n");
88- return -ENODEV;
89+ dev_err(&md->spi->dev, "FIXME: LCD panel detection failed! ID: %02x%02x%02x\n", display_id[0], display_id[1], display_id[2]);
90+ md->panel.name = "ls041y3";
91+ md->esd_check = ls041y3_esd_check;
92     }
93
94     md->revision = display_id[1];
95Index: linux-2.6.35/drivers/video/omap/omapfb.h
96===================================================================
97--- linux-2.6.35.orig/drivers/video/omap/omapfb.h 2010-08-08 12:56:09.000000000 +0200
98@@ -203,8 +203,6 @@ struct omapfb_device {
99
100     struct omapfb_mem_desc mem_desc;
101     struct fb_info *fb_info[OMAPFB_PLANE_NUM];
102-
103- struct platform_device *dssdev; /* dummy dev for clocks */
104 };
105
106 #ifdef CONFIG_ARCH_OMAP1
107@@ -226,4 +224,6 @@ extern int omapfb_update_window_async(s
108                        void (*callback)(void *),
109                        void *callback_data);
110
111+extern struct platform_device omapdss_device;
112+
113 #endif /* __OMAPFB_H */
114Index: linux-2.6.35/drivers/video/omap/omapfb_main.c
115===================================================================
116--- linux-2.6.35.orig/drivers/video/omap/omapfb_main.c 2010-08-08 12:56:09.000000000 +0200
117@@ -84,19 +84,6 @@ static struct caps_table_struct color_ca
118     { 1 << OMAPFB_COLOR_YUY422, "YUY422", },
119 };
120
121-static void omapdss_release(struct device *dev)
122-{
123-}
124-
125-/* dummy device for clocks */
126-static struct platform_device omapdss_device = {
127- .name = "omapdss",
128- .id = -1,
129- .dev = {
130- .release = omapdss_release,
131- },
132-};
133-
134 /*
135  * ---------------------------------------------------------------------------
136  * LCD panel
137@@ -1715,7 +1702,6 @@ static int omapfb_do_probe(struct platfo
138
139     fbdev->dev = &pdev->dev;
140     fbdev->panel = panel;
141- fbdev->dssdev = &omapdss_device;
142     platform_set_drvdata(pdev, fbdev);
143
144     mutex_init(&fbdev->rqueue_mutex);
145@@ -1830,16 +1816,8 @@ cleanup:
146
147 static int omapfb_probe(struct platform_device *pdev)
148 {
149- int r;
150-
151     BUG_ON(fbdev_pdev != NULL);
152
153- r = platform_device_register(&omapdss_device);
154- if (r) {
155- dev_err(&pdev->dev, "can't register omapdss device\n");
156- return r;
157- }
158-
159     /* Delay actual initialization until the LCD is registered */
160     fbdev_pdev = pdev;
161     if (fbdev_panel != NULL)
162@@ -1867,9 +1845,6 @@ static int omapfb_remove(struct platform
163     fbdev->state = OMAPFB_DISABLED;
164     omapfb_free_resources(fbdev, saved_state);
165
166- platform_device_unregister(&omapdss_device);
167- fbdev->dssdev = NULL;
168-
169     return 0;
170 }
171
172---
173 drivers/video/omap/rfbi.c | 4 ++--
174 1 file changed, 2 insertions(+), 2 deletions(-)
175
176--- linux-2.6.35.orig/drivers/video/omap/rfbi.c
177@@ -84,13 +84,13 @@ static inline u32 rfbi_read_reg(int idx)
178
179 static int rfbi_get_clocks(void)
180 {
181- rfbi.dss_ick = clk_get(&rfbi.fbdev->dssdev->dev, "ick");
182+ rfbi.dss_ick = clk_get(&omapdss_device.dev, "ick");
183     if (IS_ERR(rfbi.dss_ick)) {
184         dev_err(rfbi.fbdev->dev, "can't get ick\n");
185         return PTR_ERR(rfbi.dss_ick);
186     }
187
188- rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "dss1_fck");
189+ rfbi.dss1_fck = clk_get(&omapdss_device.dev, "dss1_fck");
190     if (IS_ERR(rfbi.dss1_fck)) {
191         dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
192         clk_put(rfbi.dss_ick);
target/linux/omap24xx/patches-2.6.35/800-decompress-unlzo-fixes.patch
1---
2 lib/decompress_unlzo.c | 4 ++++
3 1 file changed, 4 insertions(+)
4
5--- linux-2.6.35.orig/lib/decompress_unlzo.c
6@@ -50,6 +50,10 @@ static const unsigned char lzop_magic[]
7 #define LZO_BLOCK_SIZE (256*1024l)
8 #define HEADER_HAS_FILTER 0x00000800L
9
10+#ifndef INIT
11+#define INIT /* nothing */
12+#endif
13+
14 STATIC inline int INIT parse_header(u8 *input, u8 *skip)
15 {
16     int l;
target/linux/omap24xx/profiles/100-n810.mk
1#
2# Copyright (C) 2010 OpenWrt.org
3#
4# This is free software, licensed under the GNU General Public License v2.
5# See /LICENSE for more information.
6#
7
8define Profile/n810
9  NAME:=Nokia n810
10  PACKAGES:=
11endef
12
13define Profile/n810/Description
14    Package set compatible with Nokia n810 hardware
15endef
16$(eval $(call Profile,n810))
17

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