Date:2010-08-08 16:16:48 (4 years 21 days ago)
Author:mb
Commit:8b8f4c7a28a7cf8e341dc00367ccd141c5ba9a8e
Message:Add omap24xx.

Boots the kernel with working video and serial console. Userland is untested.


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22530 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/omap24xx/Makefile (1 diff)
target/linux/omap24xx/config-2.6.35 (1 diff)
target/linux/omap24xx/image/Makefile (1 diff)
target/linux/omap24xx/patches-2.6.35/100-optimized-arm-div.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/200-omap-platform.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/300-nokia-board.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/400-bluetooth-hci_h4p.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/500-cbus.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/600-tsc2005.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/700-video-omap.patch (1 diff)
target/linux/omap24xx/patches-2.6.35/800-decompress-unlzo-fixes.patch (1 diff)
target/linux/omap24xx/profiles/100-n810.mk (1 diff)

Change Details

target/linux/omap24xx/Makefile
1#
2# Copyright (C) 2010 OpenWrt.org
3#
4# This is free software, licensed under the GNU General Public License v2.
5# See /LICENSE for more information.
6#
7include $(TOPDIR)/rules.mk
8
9ARCH:=arm
10BOARD:=omap24xx
11BOARDNAME:=TI OMAP-24xx
12FEATURES:=jffs2
13
14LINUX_VERSION:=2.6.35
15
16define Target/Description
17    TI OMAP-24xx
18endef
19
20include $(INCLUDE_DIR)/target.mk
21
22$(eval $(call BuildTarget))
target/linux/omap24xx/config-2.6.35
1# CONFIG_ADIS16209 is not set
2# CONFIG_ADIS16220 is not set
3# CONFIG_ADIS16240 is not set
4# CONFIG_ADIS16260 is not set
5# CONFIG_ADIS16300 is not set
6# CONFIG_ADIS16350 is not set
7# CONFIG_ADIS16400 is not set
8CONFIG_AEABI=y
9CONFIG_ALIGNMENT_TRAP=y
10# CONFIG_APM_EMULATION is not set
11# CONFIG_ARCH_CNS3XXX is not set
12CONFIG_ARCH_HAS_CPUFREQ=y
13CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
14# CONFIG_ARCH_NUC93X is not set
15CONFIG_ARCH_OMAP=y
16# CONFIG_ARCH_OMAP1 is not set
17CONFIG_ARCH_OMAP2=y
18CONFIG_ARCH_OMAP2420=y
19# CONFIG_ARCH_OMAP2430 is not set
20CONFIG_ARCH_OMAP2PLUS=y
21# CONFIG_ARCH_OMAP3 is not set
22# CONFIG_ARCH_OMAP4 is not set
23CONFIG_ARCH_OMAP_OTG=y
24CONFIG_ARCH_REQUIRE_GPIOLIB=y
25# CONFIG_ARCH_S5P6440 is not set
26# CONFIG_ARCH_S5P6442 is not set
27# CONFIG_ARCH_S5PC100 is not set
28# CONFIG_ARCH_S5PV210 is not set
29# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
30# CONFIG_ARCH_SHMOBILE is not set
31# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
32# CONFIG_ARCH_SUPPORTS_MSI is not set
33CONFIG_ARCH_SUSPEND_POSSIBLE=y
34# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
35# CONFIG_ARCH_VEXPRESS is not set
36CONFIG_ARM=y
37CONFIG_ARM_DMA_MEM_BUFFERABLE=y
38CONFIG_ARM_ERRATA_411920=y
39CONFIG_ARM_L1_CACHE_SHIFT=5
40CONFIG_ARM_THUMB=y
41CONFIG_ARM_UNWIND=y
42# CONFIG_ARPD is not set
43CONFIG_ATAGS_PROC=y
44CONFIG_BINFMT_MISC=y
45CONFIG_BITREVERSE=y
46CONFIG_BLK_DEV_LOOP=y
47CONFIG_BLK_DEV_RAM=y
48CONFIG_BLK_DEV_RAM_COUNT=16
49CONFIG_BLK_DEV_RAM_SIZE=4096
50CONFIG_BLK_DEV_SD=y
51# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
52CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
53# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
54CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
55CONFIG_BRANCH_PROFILE_NONE=y
56CONFIG_BRIDGE=m
57CONFIG_BRIDGE_NETFILTER=y
58# CONFIG_BSD_PROCESS_ACCT is not set
59CONFIG_BT=m
60CONFIG_BT_BNEP=m
61# CONFIG_BT_BNEP_MC_FILTER is not set
62# CONFIG_BT_BNEP_PROTO_FILTER is not set
63CONFIG_BT_HCIH4P=m
64CONFIG_BT_HIDP=m
65CONFIG_BT_L2CAP=m
66CONFIG_BT_RFCOMM=m
67CONFIG_BT_SCO=m
68CONFIG_CBUS=y
69CONFIG_CBUS_RETU=y
70# CONFIG_CBUS_RETU_HEADSET is not set
71CONFIG_CBUS_RETU_POWERBUTTON=y
72CONFIG_CBUS_RETU_RTC=y
73CONFIG_CBUS_RETU_USER=y
74CONFIG_CBUS_RETU_WDT=y
75CONFIG_CBUS_TAHVO=y
76CONFIG_CBUS_TAHVO_USER=y
77CONFIG_CC_OPTIMIZE_FOR_SIZE=y
78CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS2,115200 console=tty0"
79CONFIG_CMDLINE_FORCE=y
80CONFIG_COMMON_CLKDEV=y
81CONFIG_COMPAT_BRK=y
82CONFIG_CONSOLE_TRANSLATIONS=y
83CONFIG_CPU_32v6=y
84# CONFIG_CPU_32v6K is not set
85CONFIG_CPU_ABRT_EV6=y
86# CONFIG_CPU_BPREDICT_DISABLE is not set
87CONFIG_CPU_CACHE_V6=y
88CONFIG_CPU_CACHE_VIPT=y
89CONFIG_CPU_COPY_V6=y
90CONFIG_CPU_CP15=y
91CONFIG_CPU_CP15_MMU=y
92CONFIG_CPU_HAS_ASID=y
93CONFIG_CPU_HAS_PMU=y
94# CONFIG_CPU_ICACHE_DISABLE is not set
95CONFIG_CPU_PABRT_V6=y
96CONFIG_CPU_TLB_V6=y
97CONFIG_CPU_V6=y
98CONFIG_CRC16=y
99CONFIG_CRC7=y
100CONFIG_CRC_CCITT=y
101CONFIG_CRC_ITU_T=y
102CONFIG_CRYPTO_AEAD2=y
103CONFIG_CRYPTO_AES=y
104CONFIG_CRYPTO_ANSI_CPRNG=y
105CONFIG_CRYPTO_ARC4=y
106CONFIG_CRYPTO_BLKCIPHER=y
107CONFIG_CRYPTO_BLKCIPHER2=y
108# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set
109CONFIG_CRYPTO_ECB=y
110CONFIG_CRYPTO_HASH=m
111CONFIG_CRYPTO_HASH2=y
112CONFIG_CRYPTO_HW=y
113CONFIG_CRYPTO_MANAGER=y
114CONFIG_CRYPTO_MANAGER2=y
115CONFIG_CRYPTO_RNG=y
116CONFIG_CRYPTO_RNG2=y
117CONFIG_CRYPTO_SHA1=m
118CONFIG_CRYPTO_WORKQUEUE=y
119# CONFIG_CRYPTO_ZLIB is not set
120CONFIG_CUSE=m
121CONFIG_DEBUG_BUGVERBOSE=y
122CONFIG_DEBUG_ERRORS=y
123# CONFIG_DEBUG_FS is not set
124CONFIG_DEBUG_GPIO=y
125CONFIG_DEBUG_INFO=y
126CONFIG_DEBUG_KERNEL=y
127CONFIG_DEBUG_MEMORY_INIT=y
128CONFIG_DEBUG_PREEMPT=y
129CONFIG_DEBUG_USER=y
130CONFIG_DECOMPRESS_BZIP2=y
131CONFIG_DECOMPRESS_GZIP=y
132CONFIG_DECOMPRESS_LZMA=y
133CONFIG_DECOMPRESS_LZO=y
134CONFIG_DEFAULT_CFQ=y
135# CONFIG_DEFAULT_DEADLINE is not set
136CONFIG_DEFAULT_IOSCHED="cfq"
137CONFIG_DEFAULT_TCP_CONG="cubic"
138CONFIG_DETECT_HUNG_TASK=y
139CONFIG_DETECT_SOFTLOCKUP=y
140CONFIG_DEVKMEM=y
141CONFIG_DEVTMPFS=y
142CONFIG_DEVTMPFS_MOUNT=y
143CONFIG_DNOTIFY=y
144CONFIG_DUMMY_CONSOLE=y
145CONFIG_ELF_CORE=y
146# CONFIG_EMBEDDED is not set
147# CONFIG_ENABLE_DEFAULT_TRACERS is not set
148CONFIG_ENABLE_MUST_CHECK=y
149CONFIG_EXT2_FS=y
150CONFIG_EXT2_FS_POSIX_ACL=y
151# CONFIG_EXT2_FS_SECURITY is not set
152CONFIG_EXT2_FS_XATTR=y
153CONFIG_EXT2_FS_XIP=y
154CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
155CONFIG_EXT3_FS=m
156CONFIG_EXT3_FS_POSIX_ACL=y
157# CONFIG_EXT3_FS_SECURITY is not set
158CONFIG_EXT3_FS_XATTR=y
159CONFIG_FAT_FS=y
160CONFIG_FB=y
161CONFIG_FB_CFB_COPYAREA=y
162CONFIG_FB_CFB_FILLRECT=y
163CONFIG_FB_CFB_IMAGEBLIT=y
164CONFIG_FB_OMAP=y
165CONFIG_FB_OMAP_BOOTLOADER_INIT=y
166CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
167CONFIG_FB_OMAP_LCDC_BLIZZARD=y
168CONFIG_FB_OMAP_LCDC_EXTERNAL=y
169# CONFIG_FB_OMAP_LCDC_HWA742 is not set
170CONFIG_FB_OMAP_LCD_MIPID=y
171# CONFIG_FB_OMAP_MANUAL_UPDATE is not set
172# CONFIG_FB_SM7XX is not set
173# CONFIG_FIRMWARE_EDID is not set
174CONFIG_FIRMWARE_IN_KERNEL=y
175CONFIG_FONTS=y
176# CONFIG_FONT_10x18 is not set
177# CONFIG_FONT_6x11 is not set
178# CONFIG_FONT_7x14 is not set
179CONFIG_FONT_8x16=y
180CONFIG_FONT_8x8=y
181# CONFIG_FONT_ACORN_8x8 is not set
182# CONFIG_FONT_MINI_4x6 is not set
183# CONFIG_FONT_PEARL_8x8 is not set
184# CONFIG_FONT_SUN12x22 is not set
185# CONFIG_FONT_SUN8x16 is not set
186# CONFIG_FPE_FASTFPE is not set
187CONFIG_FPE_NWFPE=y
188# CONFIG_FPE_NWFPE_XP is not set
189CONFIG_FRAMEBUFFER_CONSOLE=y
190# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
191# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
192CONFIG_FREEZER=y
193CONFIG_FS_MBCACHE=y
194CONFIG_FS_POSIX_ACL=y
195CONFIG_FS_XIP=y
196CONFIG_FTRACE=y
197CONFIG_FUSE_FS=m
198CONFIG_GENERIC_ACL=y
199CONFIG_GENERIC_ATOMIC64=y
200CONFIG_GENERIC_CLOCKEVENTS=y
201CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
202CONFIG_GENERIC_FIND_LAST_BIT=y
203CONFIG_GENERIC_GPIO=y
204CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
205CONFIG_GPIOLIB=y
206CONFIG_GPIO_SYSFS=y
207# CONFIG_HAMRADIO is not set
208CONFIG_HARDIRQS_SW_RESEND=y
209CONFIG_HAS_DMA=y
210CONFIG_HAS_IOMEM=y
211CONFIG_HAS_IOPORT=y
212CONFIG_HAVE_AOUT=y
213CONFIG_HAVE_ARCH_KGDB=y
214CONFIG_HAVE_CLK=y
215CONFIG_HAVE_FUNCTION_TRACER=y
216CONFIG_HAVE_GENERIC_DMA_COHERENT=y
217CONFIG_HAVE_IDE=y
218CONFIG_HAVE_KERNEL_GZIP=y
219CONFIG_HAVE_KERNEL_LZMA=y
220CONFIG_HAVE_KERNEL_LZO=y
221CONFIG_HAVE_KPROBES=y
222CONFIG_HAVE_KRETPROBES=y
223CONFIG_HAVE_LATENCYTOP_SUPPORT=y
224CONFIG_HAVE_MTD_OTP=y
225CONFIG_HAVE_OPROFILE=y
226CONFIG_HAVE_PERF_EVENTS=y
227CONFIG_HAVE_PROC_CPU=y
228CONFIG_HID=y
229CONFIG_HID_APPLE=m
230CONFIG_HID_SUPPORT=y
231CONFIG_HID_WACOM=m
232# CONFIG_HID_WACOM_POWER_SUPPLY is not set
233CONFIG_HWMON=m
234# CONFIG_HWMON_DEBUG_CHIP is not set
235CONFIG_HW_CONSOLE=y
236CONFIG_HW_RANDOM=y
237CONFIG_HW_RANDOM_OMAP=y
238CONFIG_HZ=128
239CONFIG_I2C=y
240CONFIG_I2C_BOARDINFO=y
241CONFIG_I2C_CHARDEV=y
242CONFIG_I2C_COMPAT=y
243CONFIG_I2C_HELPER_AUTO=y
244CONFIG_I2C_OMAP=y
245CONFIG_IIO=y
246# CONFIG_IIO_RING_BUFFER is not set
247# CONFIG_IIO_TRIGGER is not set
248CONFIG_INET6_XFRM_MODE_BEET=m
249CONFIG_INET6_XFRM_MODE_TRANSPORT=m
250CONFIG_INET6_XFRM_MODE_TUNNEL=m
251CONFIG_INET_DIAG=y
252CONFIG_INET_TCP_DIAG=y
253CONFIG_INET_TUNNEL=m
254CONFIG_INET_XFRM_MODE_BEET=y
255CONFIG_INITRAMFS_SOURCE=""
256# CONFIG_INLINE_READ_UNLOCK is not set
257# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
258# CONFIG_INLINE_SPIN_UNLOCK is not set
259# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
260# CONFIG_INLINE_WRITE_UNLOCK is not set
261# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
262CONFIG_INOTIFY=y
263CONFIG_INOTIFY_USER=y
264CONFIG_INPUT=y
265CONFIG_INPUT_EVDEV=y
266CONFIG_INPUT_KEYBOARD=y
267# CONFIG_INPUT_MISC is not set
268CONFIG_INPUT_MOUSEDEV=y
269# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
270CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
271CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
272CONFIG_INPUT_TOUCHSCREEN=y
273CONFIG_IOSCHED_CFQ=y
274# CONFIG_IOSCHED_DEADLINE is not set
275CONFIG_IPV6=y
276CONFIG_IPV6_MIP6=m
277CONFIG_IPV6_PRIVACY=y
278CONFIG_IPV6_ROUTER_PREF=y
279CONFIG_IPV6_SIT=m
280# CONFIG_IP_ADVANCED_ROUTER is not set
281# CONFIG_IP_MROUTE is not set
282CONFIG_IP_NF_FILTER=y
283CONFIG_IP_NF_IPTABLES=y
284CONFIG_IR_CORE=m
285# CONFIG_ISDN is not set
286CONFIG_JBD=m
287CONFIG_JFFS2_LZO=y
288CONFIG_JFFS2_ZLIB=y
289CONFIG_KALLSYMS=y
290CONFIG_KERNEL_GZIP=y
291# CONFIG_KERNEL_LZMA is not set
292CONFIG_KEXEC=y
293# CONFIG_KEYBOARD_ATKBD is not set
294# CONFIG_KEYBOARD_GPIO is not set
295# CONFIG_KEYBOARD_LKKBD is not set
296CONFIG_KEYBOARD_LM8323=y
297# CONFIG_KEYBOARD_MATRIX is not set
298# CONFIG_KEYBOARD_NEWTON is not set
299# CONFIG_KEYBOARD_OMAP is not set
300# CONFIG_KEYBOARD_STOWAWAY is not set
301# CONFIG_KEYBOARD_SUNKBD is not set
302# CONFIG_KEYBOARD_XTKBD is not set
303# CONFIG_KXSD9 is not set
304# CONFIG_LBDAF is not set
305CONFIG_LEDS=y
306# CONFIG_LEDS_GPIO is not set
307CONFIG_LEDS_TRIGGER_BACKLIGHT=y
308CONFIG_LEDS_TRIGGER_GPIO=y
309# CONFIG_LIS3L02DQ is not set
310CONFIG_LLC=m
311CONFIG_LOCALVERSION_AUTO=y
312CONFIG_LOCK_KERNEL=y
313CONFIG_LOG_BUF_SHIFT=21
314CONFIG_LZO_COMPRESS=y
315CONFIG_LZO_DECOMPRESS=y
316CONFIG_MACH_NOKIA_N800=y
317CONFIG_MACH_NOKIA_N810=y
318CONFIG_MACH_NOKIA_N810_WIMAX=y
319CONFIG_MACH_NOKIA_N8X0=y
320CONFIG_MACH_NOKIA_N8X0_LCD=y
321CONFIG_MACH_NOKIA_N8X0_USB=y
322CONFIG_MACH_OMAP2_TUSB6010=y
323# CONFIG_MACH_OMAP_2430SDP is not set
324# CONFIG_MACH_OMAP_APOLLON is not set
325# CONFIG_MACH_OMAP_GENERIC is not set
326# CONFIG_MACH_OMAP_H4 is not set
327CONFIG_MACVLAN=m
328# CONFIG_MAX1363 is not set
329CONFIG_MEDIA_ATTACH=y
330CONFIG_MEDIA_SUPPORT=m
331CONFIG_MEDIA_TUNER=m
332CONFIG_MEDIA_TUNER_MC44S803=m
333CONFIG_MEDIA_TUNER_MT20XX=m
334CONFIG_MEDIA_TUNER_SIMPLE=m
335CONFIG_MEDIA_TUNER_TDA8290=m
336CONFIG_MEDIA_TUNER_TDA9887=m
337CONFIG_MEDIA_TUNER_TEA5761=m
338CONFIG_MEDIA_TUNER_TEA5767=m
339CONFIG_MEDIA_TUNER_XC2028=m
340CONFIG_MEDIA_TUNER_XC5000=m
341CONFIG_MENELAUS=y
342# CONFIG_MFD_T7L66XB is not set
343# CONFIG_MISC_DEVICES is not set
344CONFIG_MMC=y
345CONFIG_MMC_BLOCK=y
346CONFIG_MMC_OMAP=y
347CONFIG_MMC_SPI=y
348CONFIG_MMC_UNSAFE_RESUME=y
349CONFIG_MODULE_FORCE_LOAD=y
350CONFIG_MODULE_FORCE_UNLOAD=y
351CONFIG_MSDOS_FS=y
352CONFIG_MTD_BLOCK2MTD=y
353# CONFIG_MTD_CFI is not set
354CONFIG_MTD_CMDLINE_PARTS=y
355# CONFIG_MTD_COMPLEX_MAPPINGS is not set
356CONFIG_MTD_ONENAND=y
357# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
358# CONFIG_MTD_ONENAND_GENERIC is not set
359CONFIG_MTD_ONENAND_OMAP2=y
360CONFIG_MTD_ONENAND_OTP=y
361# CONFIG_MTD_ONENAND_SIM is not set
362# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
363CONFIG_NAMESPACES=y
364CONFIG_NEED_DMA_MAP_STATE=y
365CONFIG_NETDEV_10000=y
366CONFIG_NETFILTER_XTABLES=y
367# CONFIG_NET_ETHERNET is not set
368# CONFIG_NET_NS is not set
369# CONFIG_NET_SCHED is not set
370CONFIG_NLS=y
371CONFIG_NO_HZ=y
372CONFIG_OABI_COMPAT=y
373# CONFIG_OMAP2_DSS is not set
374CONFIG_OMAP_32K_TIMER=y
375CONFIG_OMAP_32K_TIMER_HZ=128
376CONFIG_OMAP_BOOT_REASON=y
377CONFIG_OMAP_BOOT_TAG=y
378CONFIG_OMAP_COMPONENT_VERSION=y
379CONFIG_OMAP_DM_TIMER=y
380CONFIG_OMAP_MBOX_FWK=y
381CONFIG_OMAP_MCBSP=y
382# CONFIG_OMAP_MPU_TIMER is not set
383CONFIG_OMAP_MUX=y
384# CONFIG_OMAP_MUX_DEBUG is not set
385CONFIG_OMAP_MUX_WARNINGS=y
386# CONFIG_OMAP_PM_NONE is not set
387CONFIG_OMAP_PM_NOOP=y
388CONFIG_OMAP_RESET_CLOCKS=y
389CONFIG_OMAP_WATCHDOG=y
390CONFIG_PAGEFLAGS_EXTENDED=y
391CONFIG_PAGE_OFFSET=0xC0000000
392# CONFIG_PARTITION_ADVANCED is not set
393# CONFIG_PCI_SYSCALL is not set
394CONFIG_PERF_USE_VMALLOC=y
395# CONFIG_PLAT_SPEAR is not set
396CONFIG_PM=y
397# CONFIG_PM_DEBUG is not set
398CONFIG_PM_OPS=y
399# CONFIG_PM_RUNTIME is not set
400CONFIG_PM_SLEEP=y
401CONFIG_POSIX_MQUEUE=y
402CONFIG_POSIX_MQUEUE_SYSCTL=y
403CONFIG_PPP=m
404CONFIG_PPP_ASYNC=m
405CONFIG_PPP_BSDCOMP=m
406CONFIG_PPP_DEFLATE=m
407CONFIG_PPP_MPPE=m
408# CONFIG_PPP_MULTILINK is not set
409CONFIG_PPP_SYNC_TTY=m
410CONFIG_PREEMPT=y
411# CONFIG_PREEMPT_NONE is not set
412# CONFIG_PREEMPT_TRACER is not set
413CONFIG_PRINTK_TIME=y
414CONFIG_PROC_PAGE_MONITOR=y
415# CONFIG_PROFILE_ALL_BRANCHES is not set
416# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
417CONFIG_RAMZSWAP=m
418CONFIG_RAMZSWAP_STATS=y
419CONFIG_RD_BZIP2=y
420CONFIG_RD_GZIP=y
421CONFIG_RD_LZO=y
422CONFIG_SCHED_DEBUG=y
423CONFIG_SCSI=y
424# CONFIG_SCSI_LOWLEVEL is not set
425CONFIG_SCSI_MOD=y
426CONFIG_SDIO_UART=m
427CONFIG_SENSORS_LM75=m
428CONFIG_SENSORS_TSL2563=m
429# CONFIG_SERIAL_8250_EXTENDED is not set
430CONFIG_SERIAL_8250_NR_UARTS=4
431CONFIG_SERIAL_8250_RUNTIME_UARTS=4
432CONFIG_SERIO=y
433# CONFIG_SERIO_RAW is not set
434CONFIG_SERIO_SERPORT=y
435# CONFIG_SLAB is not set
436CONFIG_SLHC=m
437CONFIG_SLUB=y
438CONFIG_SLUB_DEBUG=y
439# CONFIG_SLUB_DEBUG_ON is not set
440# CONFIG_SLUB_STATS is not set
441CONFIG_SND=m
442CONFIG_SND_ARM=y
443# CONFIG_SND_EMU10K1_SEQ is not set
444CONFIG_SND_JACK=y
445CONFIG_SND_MIXER_OSS=m
446CONFIG_SND_OMAP_SOC=m
447CONFIG_SND_OMAP_SOC_MCBSP=m
448CONFIG_SND_OMAP_SOC_N810=m
449# CONFIG_SND_OPL3_LIB_SEQ is not set
450# CONFIG_SND_OPL4_LIB_SEQ is not set
451CONFIG_SND_PCM=m
452CONFIG_SND_PCM_OSS=m
453# CONFIG_SND_RAWMIDI_SEQ is not set
454# CONFIG_SND_SBAWE_SEQ is not set
455CONFIG_SND_SOC=m
456# CONFIG_SND_SOC_ALL_CODECS is not set
457CONFIG_SND_SOC_I2C_AND_SPI=m
458CONFIG_SND_SOC_TLV320AIC3X=m
459CONFIG_SND_SPI=y
460CONFIG_SND_SUPPORT_OLD_API=y
461CONFIG_SND_TIMER=m
462CONFIG_SOUND=m
463CONFIG_SOUND_OSS_CORE=y
464CONFIG_SOUND_OSS_CORE_PRECLAIM=y
465CONFIG_SPI=y
466# CONFIG_SPI_BITBANG is not set
467# CONFIG_SPI_GPIO is not set
468CONFIG_SPI_MASTER=y
469CONFIG_SPI_OMAP24XX=y
470# CONFIG_SPI_SPIDEV is not set
471CONFIG_STP=m
472# CONFIG_STRIP_ASM_SYMS is not set
473CONFIG_SUSPEND=y
474CONFIG_SUSPEND_FREEZER=y
475CONFIG_SUSPEND_NVS=y
476# CONFIG_SYN_COOKIES is not set
477# CONFIG_SYSCTL_SYSCALL_CHECK is not set
478CONFIG_SYS_SUPPORTS_APM_EMULATION=y
479# CONFIG_TCP_CONG_ADVANCED is not set
480CONFIG_TCP_CONG_CUBIC=y
481# CONFIG_TINY_RCU is not set
482CONFIG_TMPFS_POSIX_ACL=y
483# CONFIG_TOUCHSCREEN_DYNAPRO is not set
484# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
485# CONFIG_TOUCHSCREEN_MCS5000 is not set
486# CONFIG_TOUCHSCREEN_TPS6507X is not set
487CONFIG_TOUCHSCREEN_TSC2005=y
488CONFIG_TREE_RCU=y
489CONFIG_TUN=m
490CONFIG_UID16=y
491# CONFIG_USB_ARCH_HAS_EHCI is not set
492CONFIG_USB_SUPPORT=y
493# CONFIG_USER_NS is not set
494CONFIG_VECTORS_BASE=0xffff0000
495CONFIG_VFAT_FS=y
496CONFIG_VFP=y
497# CONFIG_VGA_CONSOLE is not set
498CONFIG_VIDEO_ALLOW_V4L1=y
499CONFIG_VIDEO_CAPTURE_DRIVERS=y
500CONFIG_VIDEO_DEV=m
501CONFIG_VIDEO_IR=m
502CONFIG_VIDEO_IR_I2C=m
503CONFIG_VIDEO_MEDIA=m
504# CONFIG_VIDEO_OMAP2 is not set
505# CONFIG_VIDEO_OMAP2_VOUT is not set
506CONFIG_VIDEO_TCM825X=m
507CONFIG_VIDEO_V4L1=m
508CONFIG_VIDEO_V4L2=m
509CONFIG_VIDEO_V4L2_COMMON=m
510CONFIG_VLAN_8021Q=m
511CONFIG_VM_EVENT_COUNTERS=y
512CONFIG_VT=y
513CONFIG_VT_CONSOLE=y
514# CONFIG_VT_HW_CONSOLE_BINDING is not set
515CONFIG_WATCHDOG_NOWAYOUT=y
516# CONFIG_ZBOOT_ROM is not set
517CONFIG_ZBOOT_ROM_BSS=0x10200000
518CONFIG_ZBOOT_ROM_TEXT=0x10C08000
519CONFIG_ZONE_DMA_FLAG=0
target/linux/omap24xx/image/Makefile
1#
2# Copyright (C) 2010 OpenWrt.org
3#
4# This is free software, licensed under the GNU General Public License v2.
5# See /LICENSE for more information.
6#
7include $(TOPDIR)/rules.mk
8include $(INCLUDE_DIR)/image.mk
9
10JFFS2_BLOCKSIZE=128k
11JFFS2OPTS += --little-endian --pagesize=0x800 --no-cleanmarkers --pad
12
13
14define Image/BuildKernel
15    $(CP) $(LINUX_DIR)/arch/arm/boot/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
16    chmod 0644 $(BIN_DIR)/$(IMG_PREFIX)-zImage
17endef
18
19define Image/Build/squashfs
20    $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-root.$(1))
21endef
22
23define Image/Build
24    $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-root.$(1)
25    $(call Image/Build/$(1),$(1))
26endef
27
28
29$(eval $(call BuildImage))
target/linux/omap24xx/patches-2.6.35/100-optimized-arm-div.patch
1---
2 arch/arm/boot/compressed/lib1funcs.S | 348 +++++++++++++++++++++++++++++++++++
3 1 file changed, 348 insertions(+)
4
5--- /dev/null
6@@ -0,0 +1,348 @@
7+/*
8+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
9+ *
10+ * Author: Nicolas Pitre <nico@fluxnic.net>
11+ * - contributed to gcc-3.4 on Sep 30, 2003
12+ * - adapted for the Linux kernel on Oct 2, 2003
13+ */
14+
15+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
16+
17+This file is free software; you can redistribute it and/or modify it
18+under the terms of the GNU General Public License as published by the
19+Free Software Foundation; either version 2, or (at your option) any
20+later version.
21+
22+In addition to the permissions in the GNU General Public License, the
23+Free Software Foundation gives you unlimited permission to link the
24+compiled version of this file into combinations with other programs,
25+and to distribute those combinations without any restriction coming
26+from the use of this file. (The General Public License restrictions
27+do apply in other respects; for example, they cover modification of
28+the file, and distribution when not linked into a combine
29+executable.)
30+
31+This file is distributed in the hope that it will be useful, but
32+WITHOUT ANY WARRANTY; without even the implied warranty of
33+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34+General Public License for more details.
35+
36+You should have received a copy of the GNU General Public License
37+along with this program; see the file COPYING. If not, write to
38+the Free Software Foundation, 59 Temple Place - Suite 330,
39+Boston, MA 02111-1307, USA. */
40+
41+
42+#include <linux/linkage.h>
43+#include <asm/assembler.h>
44+
45+
46+.macro ARM_DIV_BODY dividend, divisor, result, curbit
47+
48+#if __LINUX_ARM_ARCH__ >= 5
49+
50+ clz \curbit, \divisor
51+ clz \result, \dividend
52+ sub \result, \curbit, \result
53+ mov \curbit, #1
54+ mov \divisor, \divisor, lsl \result
55+ mov \curbit, \curbit, lsl \result
56+ mov \result, #0
57+
58+#else
59+
60+ @ Initially shift the divisor left 3 bits if possible,
61+ @ set curbit accordingly. This allows for curbit to be located
62+ @ at the left end of each 4 bit nibbles in the division loop
63+ @ to save one loop in most cases.
64+ tst \divisor, #0xe0000000
65+ moveq \divisor, \divisor, lsl #3
66+ moveq \curbit, #8
67+ movne \curbit, #1
68+
69+ @ Unless the divisor is very big, shift it up in multiples of
70+ @ four bits, since this is the amount of unwinding in the main
71+ @ division loop. Continue shifting until the divisor is
72+ @ larger than the dividend.
73+1: cmp \divisor, #0x10000000
74+ cmplo \divisor, \dividend
75+ movlo \divisor, \divisor, lsl #4
76+ movlo \curbit, \curbit, lsl #4
77+ blo 1b
78+
79+ @ For very big divisors, we must shift it a bit at a time, or
80+ @ we will be in danger of overflowing.
81+1: cmp \divisor, #0x80000000
82+ cmplo \divisor, \dividend
83+ movlo \divisor, \divisor, lsl #1
84+ movlo \curbit, \curbit, lsl #1
85+ blo 1b
86+
87+ mov \result, #0
88+
89+#endif
90+
91+ @ Division loop
92+1: cmp \dividend, \divisor
93+ subhs \dividend, \dividend, \divisor
94+ orrhs \result, \result, \curbit
95+ cmp \dividend, \divisor, lsr #1
96+ subhs \dividend, \dividend, \divisor, lsr #1
97+ orrhs \result, \result, \curbit, lsr #1
98+ cmp \dividend, \divisor, lsr #2
99+ subhs \dividend, \dividend, \divisor, lsr #2
100+ orrhs \result, \result, \curbit, lsr #2
101+ cmp \dividend, \divisor, lsr #3
102+ subhs \dividend, \dividend, \divisor, lsr #3
103+ orrhs \result, \result, \curbit, lsr #3
104+ cmp \dividend, #0 @ Early termination?
105+ movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
106+ movne \divisor, \divisor, lsr #4
107+ bne 1b
108+
109+.endm
110+
111+
112+.macro ARM_DIV2_ORDER divisor, order
113+
114+#if __LINUX_ARM_ARCH__ >= 5
115+
116+ clz \order, \divisor
117+ rsb \order, \order, #31
118+
119+#else
120+
121+ cmp \divisor, #(1 << 16)
122+ movhs \divisor, \divisor, lsr #16
123+ movhs \order, #16
124+ movlo \order, #0
125+
126+ cmp \divisor, #(1 << 8)
127+ movhs \divisor, \divisor, lsr #8
128+ addhs \order, \order, #8
129+
130+ cmp \divisor, #(1 << 4)
131+ movhs \divisor, \divisor, lsr #4
132+ addhs \order, \order, #4
133+
134+ cmp \divisor, #(1 << 2)
135+ addhi \order, \order, #3
136+ addls \order, \order, \divisor, lsr #1
137+
138+#endif
139+
140+.endm
141+
142+
143+.macro ARM_MOD_BODY dividend, divisor, order, spare
144+
145+#if __LINUX_ARM_ARCH__ >= 5
146+
147+ clz \order, \divisor
148+ clz \spare, \dividend
149+ sub \order, \order, \spare
150+ mov \divisor, \divisor, lsl \order
151+
152+#else
153+
154+ mov \order, #0
155+
156+ @ Unless the divisor is very big, shift it up in multiples of
157+ @ four bits, since this is the amount of unwinding in the main
158+ @ division loop. Continue shifting until the divisor is
159+ @ larger than the dividend.
160+1: cmp \divisor, #0x10000000
161+ cmplo \divisor, \dividend
162+ movlo \divisor, \divisor, lsl #4
163+ addlo \order, \order, #4
164+ blo 1b
165+
166+ @ For very big divisors, we must shift it a bit at a time, or
167+ @ we will be in danger of overflowing.
168+1: cmp \divisor, #0x80000000
169+ cmplo \divisor, \dividend
170+ movlo \divisor, \divisor, lsl #1
171+ addlo \order, \order, #1
172+ blo 1b
173+
174+#endif
175+
176+ @ Perform all needed substractions to keep only the reminder.
177+ @ Do comparisons in batch of 4 first.
178+ subs \order, \order, #3 @ yes, 3 is intended here
179+ blt 2f
180+
181+1: cmp \dividend, \divisor
182+ subhs \dividend, \dividend, \divisor
183+ cmp \dividend, \divisor, lsr #1
184+ subhs \dividend, \dividend, \divisor, lsr #1
185+ cmp \dividend, \divisor, lsr #2
186+ subhs \dividend, \dividend, \divisor, lsr #2
187+ cmp \dividend, \divisor, lsr #3
188+ subhs \dividend, \dividend, \divisor, lsr #3
189+ cmp \dividend, #1
190+ mov \divisor, \divisor, lsr #4
191+ subges \order, \order, #4
192+ bge 1b
193+
194+ tst \order, #3
195+ teqne \dividend, #0
196+ beq 5f
197+
198+ @ Either 1, 2 or 3 comparison/substractions are left.
199+2: cmn \order, #2
200+ blt 4f
201+ beq 3f
202+ cmp \dividend, \divisor
203+ subhs \dividend, \dividend, \divisor
204+ mov \divisor, \divisor, lsr #1
205+3: cmp \dividend, \divisor
206+ subhs \dividend, \dividend, \divisor
207+ mov \divisor, \divisor, lsr #1
208+4: cmp \dividend, \divisor
209+ subhs \dividend, \dividend, \divisor
210+5:
211+.endm
212+
213+
214+ENTRY(__udivsi3)
215+ENTRY(__aeabi_uidiv)
216+
217+ subs r2, r1, #1
218+ moveq pc, lr
219+ bcc Ldiv0
220+ cmp r0, r1
221+ bls 11f
222+ tst r1, r2
223+ beq 12f
224+
225+ ARM_DIV_BODY r0, r1, r2, r3
226+
227+ mov r0, r2
228+ mov pc, lr
229+
230+11: moveq r0, #1
231+ movne r0, #0
232+ mov pc, lr
233+
234+12: ARM_DIV2_ORDER r1, r2
235+
236+ mov r0, r0, lsr r2
237+ mov pc, lr
238+
239+ENDPROC(__udivsi3)
240+ENDPROC(__aeabi_uidiv)
241+
242+ENTRY(__umodsi3)
243+
244+ subs r2, r1, #1 @ compare divisor with 1
245+ bcc Ldiv0
246+ cmpne r0, r1 @ compare dividend with divisor
247+ moveq r0, #0
248+ tsthi r1, r2 @ see if divisor is power of 2
249+ andeq r0, r0, r2
250+ movls pc, lr
251+
252+ ARM_MOD_BODY r0, r1, r2, r3
253+
254+ mov pc, lr
255+
256+ENDPROC(__umodsi3)
257+
258+ENTRY(__divsi3)
259+ENTRY(__aeabi_idiv)
260+
261+ cmp r1, #0
262+ eor ip, r0, r1 @ save the sign of the result.
263+ beq Ldiv0
264+ rsbmi r1, r1, #0 @ loops below use unsigned.
265+ subs r2, r1, #1 @ division by 1 or -1 ?
266+ beq 10f
267+ movs r3, r0
268+ rsbmi r3, r0, #0 @ positive dividend value
269+ cmp r3, r1
270+ bls 11f
271+ tst r1, r2 @ divisor is power of 2 ?
272+ beq 12f
273+
274+ ARM_DIV_BODY r3, r1, r0, r2
275+
276+ cmp ip, #0
277+ rsbmi r0, r0, #0
278+ mov pc, lr
279+
280+10: teq ip, r0 @ same sign ?
281+ rsbmi r0, r0, #0
282+ mov pc, lr
283+
284+11: movlo r0, #0
285+ moveq r0, ip, asr #31
286+ orreq r0, r0, #1
287+ mov pc, lr
288+
289+12: ARM_DIV2_ORDER r1, r2
290+
291+ cmp ip, #0
292+ mov r0, r3, lsr r2
293+ rsbmi r0, r0, #0
294+ mov pc, lr
295+
296+ENDPROC(__divsi3)
297+ENDPROC(__aeabi_idiv)
298+
299+ENTRY(__modsi3)
300+
301+ cmp r1, #0
302+ beq Ldiv0
303+ rsbmi r1, r1, #0 @ loops below use unsigned.
304+ movs ip, r0 @ preserve sign of dividend
305+ rsbmi r0, r0, #0 @ if negative make positive
306+ subs r2, r1, #1 @ compare divisor with 1
307+ cmpne r0, r1 @ compare dividend with divisor
308+ moveq r0, #0
309+ tsthi r1, r2 @ see if divisor is power of 2
310+ andeq r0, r0, r2
311+ bls 10f
312+
313+ ARM_MOD_BODY r0, r1, r2, r3
314+
315+10: cmp ip, #0
316+ rsbmi r0, r0, #0
317+ mov pc, lr
318+
319+ENDPROC(__modsi3)
320+
321+#ifdef CONFIG_AEABI
322+
323+ENTRY(__aeabi_uidivmod)
324+
325+ stmfd sp!, {r0, r1, ip, lr}
326+ bl __aeabi_uidiv
327+ ldmfd sp!, {r1, r2, ip, lr}
328+ mul r3, r0, r2
329+ sub r1, r1, r3
330+ mov pc, lr
331+
332+ENDPROC(__aeabi_uidivmod)
333+
334+ENTRY(__aeabi_idivmod)
335+
336+ stmfd sp!, {r0, r1, ip, lr}
337+ bl __aeabi_idiv
338+ ldmfd sp!, {r1, r2, ip, lr}
339+ mul r3, r0, r2
340+ sub r1, r1, r3
341+ mov pc, lr
342+
343+ENDPROC(__aeabi_idivmod)
344+
345+#endif
346+
347+Ldiv0:
348+
349+ str lr, [sp, #-8]!
350+ bl __div0
351+ mov r0, #0 @ About as wrong as it could be.
352+ ldr pc, [sp], #8
353+
354+
target/linux/omap24xx/patches-2.6.35/200-omap-platform.patch
1Index: linux-2.6.35/arch/arm/plat-omap/bootreason.c
2===================================================================
3--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4@@ -0,0 +1,79 @@
5+/*
6+ * linux/arch/arm/plat-omap/bootreason.c
7+ *
8+ * OMAP Bootreason passing
9+ *
10+ * Copyright (c) 2004 Nokia
11+ *
12+ * Written by David Weinehall <david.weinehall@nokia.com>
13+ *
14+ * This program is free software; you can redistribute it and/or modify it
15+ * under the terms of the GNU General Public License as published by the
16+ * Free Software Foundation; either version 2 of the License, or (at your
17+ * option) any later version.
18+ *
19+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29+ *
30+ * You should have received a copy of the GNU General Public License along
31+ * with this program; if not, write to the Free Software Foundation, Inc.,
32+ * 675 Mass Ave, Cambridge, MA 02139, USA.
33+ */
34+#include <linux/proc_fs.h>
35+#include <linux/errno.h>
36+#include <plat/board.h>
37+
38+static char boot_reason[16];
39+
40+static int omap_bootreason_read_proc(char *page, char **start, off_t off,
41+ int count, int *eof, void *data)
42+{
43+ int len = 0;
44+
45+ len += sprintf(page + len, "%s\n", boot_reason);
46+
47+ *start = page + off;
48+
49+ if (len > off)
50+ len -= off;
51+ else
52+ len = 0;
53+
54+ return len < count ? len : count;
55+}
56+
57+static int __init bootreason_init(void)
58+{
59+ const struct omap_boot_reason_config *cfg;
60+ int reason_valid = 0;
61+
62+ cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
63+ if (cfg != NULL) {
64+ strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
65+ boot_reason[sizeof(cfg->reason_str)] = 0;
66+ reason_valid = 1;
67+ } else {
68+ /* Read the boot reason from the OMAP registers */
69+ }
70+
71+ if (!reason_valid)
72+ return -ENOENT;
73+
74+ printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
75+
76+ if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
77+ omap_bootreason_read_proc, NULL))
78+ return -ENOMEM;
79+
80+ return 0;
81+}
82+
83+late_initcall(bootreason_init);
84Index: linux-2.6.35/arch/arm/plat-omap/common.c
85===================================================================
86--- linux-2.6.35.orig/arch/arm/plat-omap/common.c 2010-08-08 12:56:15.000000000 +0200
87@@ -47,11 +47,81 @@
88 struct omap_board_config_kernel *omap_board_config;
89 int omap_board_config_size;
90
91+unsigned char omap_bootloader_tag[1024];
92+int omap_bootloader_tag_len;
93+
94+/* used by omap-smp.c and board-4430sdp.c */
95+void __iomem *gic_cpu_base_addr;
96+
97+#ifdef CONFIG_OMAP_BOOT_TAG
98+
99+static int __init parse_tag_omap(const struct tag *tag)
100+{
101+ u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
102+
103+ size <<= 2;
104+ if (size > sizeof(omap_bootloader_tag))
105+ return -1;
106+
107+ memcpy(omap_bootloader_tag, tag->u.omap.data, size);
108+ omap_bootloader_tag_len = size;
109+
110+ return 0;
111+}
112+
113+__tagtable(ATAG_BOARD, parse_tag_omap);
114+
115+#endif
116+
117 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
118 {
119     struct omap_board_config_kernel *kinfo = NULL;
120     int i;
121
122+#ifdef CONFIG_OMAP_BOOT_TAG
123+ struct omap_board_config_entry *info = NULL;
124+
125+ if (omap_bootloader_tag_len > 4)
126+ info = (struct omap_board_config_entry *) omap_bootloader_tag;
127+ while (info != NULL) {
128+ u8 *next;
129+
130+ if (info->tag == tag) {
131+ if (skip == 0)
132+ break;
133+ skip--;
134+ }
135+
136+ if ((info->len & 0x03) != 0) {
137+ /* We bail out to avoid an alignment fault */
138+ printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
139+ info->len, info->tag);
140+ return NULL;
141+ }
142+ next = (u8 *) info + sizeof(*info) + info->len;
143+ if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
144+ info = NULL;
145+ else
146+ info = (struct omap_board_config_entry *) next;
147+ }
148+ if (info != NULL) {
149+ /* Check the length as a lame attempt to check for
150+ * binary inconsistency. */
151+ if (len != NO_LENGTH_CHECK) {
152+ /* Word-align len */
153+ if (len & 0x03)
154+ len = (len + 3) & ~0x03;
155+ if (info->len != len) {
156+ printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
157+ tag, len, info->len);
158+ return NULL;
159+ }
160+ }
161+ if (len_out != NULL)
162+ *len_out = info->len;
163+ return info->data;
164+ }
165+#endif
166     /* Try to find the config from the board-specific structures
167      * in the kernel. */
168     for (i = 0; i < omap_board_config_size; i++) {
169Index: linux-2.6.35/arch/arm/plat-omap/component-version.c
170===================================================================
171--- /dev/null 1970-01-01 00:00:00.000000000 +0000
172@@ -0,0 +1,64 @@
173+/*
174+ * linux/arch/arm/plat-omap/component-version.c
175+ *
176+ * Copyright (C) 2005 Nokia Corporation
177+ * Written by Juha Yrjl <juha.yrjola@nokia.com>
178+ *
179+ * This program is free software; you can redistribute it and/or modify
180+ * it under the terms of the GNU General Public License version 2 as
181+ * published by the Free Software Foundation.
182+ */
183+
184+#include <linux/init.h>
185+#include <linux/module.h>
186+#include <linux/err.h>
187+#include <linux/proc_fs.h>
188+#include <plat/board.h>
189+
190+static int component_version_read_proc(char *page, char **start, off_t off,
191+ int count, int *eof, void *data)
192+{
193+ int len, i;
194+ const struct omap_version_config *ver;
195+ char *p;
196+
197+ i = 0;
198+ p = page;
199+ while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
200+ struct omap_version_config, i)) != NULL) {
201+ p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
202+ i++;
203+ }
204+
205+ len = (p - page) - off;
206+ if (len < 0)
207+ len = 0;
208+
209+ *eof = (len <= count) ? 1 : 0;
210+ *start = page + off;
211+
212+ return len;
213+}
214+
215+static int __init component_version_init(void)
216+{
217+ if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
218+ return -ENODEV;
219+ if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
220+ component_version_read_proc, NULL))
221+ return -ENOMEM;
222+
223+ return 0;
224+}
225+
226+static void __exit component_version_exit(void)
227+{
228+ remove_proc_entry("component_version", NULL);
229+}
230+
231+late_initcall(component_version_init);
232+module_exit(component_version_exit);
233+
234+MODULE_AUTHOR("Juha Yrjl <juha.yrjola@nokia.com>");
235+MODULE_DESCRIPTION("Component version driver");
236+MODULE_LICENSE("GPL");
237Index: linux-2.6.35/arch/arm/plat-omap/include/mach/blizzard.h
238===================================================================
239--- /dev/null 1970-01-01 00:00:00.000000000 +0000
240@@ -0,0 +1,12 @@
241+#ifndef _BLIZZARD_H
242+#define _BLIZZARD_H
243+
244+struct blizzard_platform_data {
245+ void (*power_up)(struct device *dev);
246+ void (*power_down)(struct device *dev);
247+ unsigned long (*get_clock_rate)(struct device *dev);
248+
249+ unsigned te_connected : 1;
250+};
251+
252+#endif
253Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-ams-delta.h
254===================================================================
255--- /dev/null 1970-01-01 00:00:00.000000000 +0000
256@@ -0,0 +1,76 @@
257+/*
258+ * arch/arm/plat-omap/include/mach/board-ams-delta.h
259+ *
260+ * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
261+ *
262+ * This program is free software; you can redistribute it and/or modify it
263+ * under the terms of the GNU General Public License as published by the
264+ * Free Software Foundation; either version 2 of the License, or (at your
265+ * option) any later version.
266+ *
267+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
268+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
269+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
270+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
271+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
272+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
273+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
274+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
275+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
276+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277+ *
278+ * You should have received a copy of the GNU General Public License along
279+ * with this program; if not, write to the Free Software Foundation, Inc.,
280+ * 675 Mass Ave, Cambridge, MA 02139, USA.
281+ */
282+#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
283+#define __ASM_ARCH_OMAP_AMS_DELTA_H
284+
285+#if defined (CONFIG_MACH_AMS_DELTA)
286+
287+#define AMS_DELTA_LATCH1_PHYS 0x01000000
288+#define AMS_DELTA_LATCH1_VIRT 0xEA000000
289+#define AMS_DELTA_MODEM_PHYS 0x04000000
290+#define AMS_DELTA_MODEM_VIRT 0xEB000000
291+#define AMS_DELTA_LATCH2_PHYS 0x08000000
292+#define AMS_DELTA_LATCH2_VIRT 0xEC000000
293+
294+#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
295+#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
296+#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
297+#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
298+#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
299+#define AMS_DELTA_LATCH1_LED_VOICE 0x20
300+
301+#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
302+#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
303+#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
304+#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
305+#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
306+#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
307+#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
308+#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
309+#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
310+#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
311+#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
312+#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
313+#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
314+#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
315+
316+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
317+#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
318+#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
319+#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
320+#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
321+#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
322+#define AMS_DELTA_GPIO_PIN_CONFIG 11
323+#define AMS_DELTA_GPIO_PIN_NAND_RB 12
324+
325+#ifndef __ASSEMBLY__
326+void ams_delta_latch1_write(u8 mask, u8 value);
327+void ams_delta_latch2_write(u16 mask, u16 value);
328+#endif
329+
330+#endif /* CONFIG_MACH_AMS_DELTA */
331+
332+#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
333Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board.h
334===================================================================
335--- /dev/null 1970-01-01 00:00:00.000000000 +0000
336@@ -0,0 +1,169 @@
337+/*
338+ * arch/arm/plat-omap/include/mach/board.h
339+ *
340+ * Information structures for board-specific data
341+ *
342+ * Copyright (C) 2004 Nokia Corporation
343+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
344+ */
345+
346+#ifndef _OMAP_BOARD_H
347+#define _OMAP_BOARD_H
348+
349+#include <linux/types.h>
350+
351+#include <plat/gpio-switch.h>
352+
353+/*
354+ * OMAP35x EVM revision
355+ * Run time detection of EVM revision is done by reading Ethernet
356+ * PHY ID -
357+ * GEN_1 = 0x01150000
358+ * GEN_2 = 0x92200000
359+ */
360+enum {
361+ OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
362+ OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
363+};
364+
365+/* Different peripheral ids */
366+#define OMAP_TAG_CLOCK 0x4f01
367+#define OMAP_TAG_LCD 0x4f05
368+#define OMAP_TAG_GPIO_SWITCH 0x4f06
369+#define OMAP_TAG_FBMEM 0x4f08
370+#define OMAP_TAG_STI_CONSOLE 0x4f09
371+#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
372+
373+#define OMAP_TAG_BOOT_REASON 0x4f80
374+#define OMAP_TAG_FLASH_PART 0x4f81
375+#define OMAP_TAG_VERSION_STR 0x4f82
376+
377+struct omap_clock_config {
378+ /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
379+ u8 system_clock_type;
380+};
381+
382+struct omap_serial_console_config {
383+ u8 console_uart;
384+ u32 console_speed;
385+};
386+
387+struct omap_sti_console_config {
388+ unsigned enable:1;
389+ u8 channel;
390+};
391+
392+struct omap_camera_sensor_config {
393+ u16 reset_gpio;
394+ int (*power_on)(void * data);
395+ int (*power_off)(void * data);
396+};
397+
398+struct omap_usb_config {
399+ /* Configure drivers according to the connectors on your board:
400+ * - "A" connector (rectagular)
401+ * ... for host/OHCI use, set "register_host".
402+ * - "B" connector (squarish) or "Mini-B"
403+ * ... for device/gadget use, set "register_dev".
404+ * - "Mini-AB" connector (very similar to Mini-B)
405+ * ... for OTG use as device OR host, initialize "otg"
406+ */
407+ unsigned register_host:1;
408+ unsigned register_dev:1;
409+ u8 otg; /* port number, 1-based: usb1 == 2 */
410+
411+ u8 hmc_mode;
412+
413+ /* implicitly true if otg: host supports remote wakeup? */
414+ u8 rwc;
415+
416+ /* signaling pins used to talk to transceiver on usbN:
417+ * 0 == usbN unused
418+ * 2 == usb0-only, using internal transceiver
419+ * 3 == 3 wire bidirectional
420+ * 4 == 4 wire bidirectional
421+ * 6 == 6 wire unidirectional (or TLL)
422+ */
423+ u8 pins[3];
424+};
425+
426+struct omap_lcd_config {
427+ char panel_name[16];
428+ char ctrl_name[16];
429+ s16 nreset_gpio;
430+ u8 data_lines;
431+};
432+
433+struct device;
434+struct fb_info;
435+struct omap_backlight_config {
436+ int default_intensity;
437+ int (*set_power)(struct device *dev, int state);
438+ int (*check_fb)(struct fb_info *fb);
439+};
440+
441+struct omap_fbmem_config {
442+ u32 start;
443+ u32 size;
444+};
445+
446+struct omap_pwm_led_platform_data {
447+ const char *name;
448+ int intensity_timer;
449+ int blink_timer;
450+ void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
451+};
452+
453+struct omap_uart_config {
454+ /* Bit field of UARTs present; bit 0 --> UART1 */
455+ unsigned int enabled_uarts;
456+};
457+
458+
459+struct omap_flash_part_config {
460+ char part_table[0];
461+};
462+
463+struct omap_boot_reason_config {
464+ char reason_str[12];
465+};
466+
467+struct omap_version_config {
468+ char component[12];
469+ char version[12];
470+};
471+
472+struct omap_board_config_entry {
473+ u16 tag;
474+ u16 len;
475+ u8 data[0];
476+};
477+
478+struct omap_board_config_kernel {
479+ u16 tag;
480+ const void *data;
481+};
482+
483+extern const void *__omap_get_config(u16 tag, size_t len, int nr);
484+
485+#define omap_get_config(tag, type) \
486+ ((const type *) __omap_get_config((tag), sizeof(type), 0))
487+#define omap_get_nr_config(tag, type, nr) \
488+ ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
489+
490+extern const void *omap_get_var_config(u16 tag, size_t *len);
491+
492+extern struct omap_board_config_kernel *omap_board_config;
493+extern int omap_board_config_size;
494+
495+
496+/* for TI reference platforms sharing the same debug card */
497+extern int debug_card_init(u32 addr, unsigned gpio);
498+
499+/* OMAP3EVM revision */
500+#if defined(CONFIG_MACH_OMAP3EVM)
501+u8 get_omap3_evm_rev(void);
502+#else
503+#define get_omap3_evm_rev() (-EINVAL)
504+#endif
505+#endif
506Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-sx1.h
507===================================================================
508--- /dev/null 1970-01-01 00:00:00.000000000 +0000
509@@ -0,0 +1,52 @@
510+/*
511+ * Siemens SX1 board definitions
512+ *
513+ * Copyright: Vovan888 at gmail com
514+ *
515+ * This package is free software; you can redistribute it and/or modify
516+ * it under the terms of the GNU General Public License version 2 as
517+ * published by the Free Software Foundation.
518+ *
519+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
520+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
521+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
522+ */
523+
524+#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
525+#define __ASM_ARCH_SX1_I2C_CHIPS_H
526+
527+#define SOFIA_MAX_LIGHT_VAL 0x2B
528+
529+#define SOFIA_I2C_ADDR 0x32
530+/* Sofia reg 3 bits masks */
531+#define SOFIA_POWER1_REG 0x03
532+
533+#define SOFIA_USB_POWER 0x01
534+#define SOFIA_MMC_POWER 0x04
535+#define SOFIA_BLUETOOTH_POWER 0x08
536+#define SOFIA_MMILIGHT_POWER 0x20
537+
538+#define SOFIA_POWER2_REG 0x04
539+#define SOFIA_BACKLIGHT_REG 0x06
540+#define SOFIA_KEYLIGHT_REG 0x07
541+#define SOFIA_DIMMING_REG 0x09
542+
543+
544+/* Function Prototypes for SX1 devices control on I2C bus */
545+
546+int sx1_setbacklight(u8 backlight);
547+int sx1_getbacklight(u8 *backlight);
548+int sx1_setkeylight(u8 keylight);
549+int sx1_getkeylight(u8 *keylight);
550+
551+int sx1_setmmipower(u8 onoff);
552+int sx1_setusbpower(u8 onoff);
553+int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
554+int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
555+
556+/* MMC prototypes */
557+
558+extern void sx1_mmc_init(void);
559+extern void sx1_mmc_slot_cover_handler(void *arg, int state);
560+
561+#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
562Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-voiceblue.h
563===================================================================
564--- /dev/null 1970-01-01 00:00:00.000000000 +0000
565@@ -0,0 +1,19 @@
566+/*
567+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
568+ *
569+ * Hardware definitions for OMAP5910 based VoiceBlue board.
570+ *
571+ * This program is free software; you can redistribute it and/or modify
572+ * it under the terms of the GNU General Public License version 2 as
573+ * published by the Free Software Foundation.
574+ */
575+
576+#ifndef __ASM_ARCH_VOICEBLUE_H
577+#define __ASM_ARCH_VOICEBLUE_H
578+
579+extern void voiceblue_wdt_enable(void);
580+extern void voiceblue_wdt_disable(void);
581+extern void voiceblue_wdt_ping(void);
582+
583+#endif /* __ASM_ARCH_VOICEBLUE_H */
584+
585Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cbus.h
586===================================================================
587--- /dev/null 1970-01-01 00:00:00.000000000 +0000
588@@ -0,0 +1,31 @@
589+/*
590+ * cbus.h - CBUS platform_data definition
591+ *
592+ * Copyright (C) 2004 - 2009 Nokia Corporation
593+ *
594+ * Written by Felipe Balbi <felipe.balbi@nokia.com>
595+ *
596+ * This file is subject to the terms and conditions of the GNU General
597+ * Public License. See the file "COPYING" in the main directory of this
598+ * archive for more details.
599+ *
600+ * This program is distributed in the hope that it will be useful,
601+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
602+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
603+ * GNU General Public License for more details.
604+ *
605+ * You should have received a copy of the GNU General Public License
606+ * along with this program; if not, write to the Free Software
607+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
608+ */
609+
610+#ifndef __PLAT_CBUS_H
611+#define __PLAT_CBUS_H
612+
613+struct cbus_host_platform_data {
614+ int dat_gpio;
615+ int clk_gpio;
616+ int sel_gpio;
617+};
618+
619+#endif /* __PLAT_CBUS_H */
620Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev.h
621===================================================================
622--- /dev/null 1970-01-01 00:00:00.000000000 +0000
623@@ -0,0 +1,13 @@
624+#ifndef __MACH_CLKDEV_H
625+#define __MACH_CLKDEV_H
626+
627+static inline int __clk_get(struct clk *clk)
628+{
629+ return 1;
630+}
631+
632+static inline void __clk_put(struct clk *clk)
633+{
634+}
635+
636+#endif
637Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev_omap.h
638===================================================================
639--- /dev/null 1970-01-01 00:00:00.000000000 +0000
640@@ -0,0 +1,41 @@
641+/*
642+ * clkdev <-> OMAP integration
643+ *
644+ * Russell King <linux@arm.linux.org.uk>
645+ *
646+ */
647+
648+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
649+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
650+
651+#include <asm/clkdev.h>
652+
653+struct omap_clk {
654+ u16 cpu;
655+ struct clk_lookup lk;
656+};
657+
658+#define CLK(dev, con, ck, cp) \
659+ { \
660+ .cpu = cp, \
661+ .lk = { \
662+ .dev_id = dev, \
663+ .con_id = con, \
664+ .clk = ck, \
665+ }, \
666+ }
667+
668+
669+#define CK_310 (1 << 0)
670+#define CK_7XX (1 << 1)
671+#define CK_1510 (1 << 2)
672+#define CK_16XX (1 << 3)
673+#define CK_243X (1 << 4)
674+#define CK_242X (1 << 5)
675+#define CK_343X (1 << 6)
676+#define CK_3430ES1 (1 << 7)
677+#define CK_3430ES2 (1 << 8)
678+#define CK_443X (1 << 9)
679+
680+#endif
681+
682Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clockdomain.h
683===================================================================
684--- /dev/null 1970-01-01 00:00:00.000000000 +0000
685@@ -0,0 +1,111 @@
686+/*
687+ * arch/arm/plat-omap/include/mach/clockdomain.h
688+ *
689+ * OMAP2/3 clockdomain framework functions
690+ *
691+ * Copyright (C) 2008 Texas Instruments, Inc.
692+ * Copyright (C) 2008 Nokia Corporation
693+ *
694+ * Written by Paul Walmsley
695+ *
696+ * This program is free software; you can redistribute it and/or modify
697+ * it under the terms of the GNU General Public License version 2 as
698+ * published by the Free Software Foundation.
699+ */
700+
701+#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
702+#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
703+
704+#include <plat/powerdomain.h>
705+#include <plat/clock.h>
706+#include <plat/cpu.h>
707+
708+/* Clockdomain capability flags */
709+#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
710+#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
711+#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
712+#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
713+
714+#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
715+#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
716+#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
717+
718+/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
719+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
720+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
721+
722+/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
723+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
724+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
725+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
726+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
727+
728+/*
729+ * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
730+ * and sleepdeps added when a powerdomain should stay active in hwsup mode;
731+ * and conversely, removed when the powerdomain should be allowed to go
732+ * inactive in hwsup mode.
733+ */
734+struct clkdm_pwrdm_autodep {
735+
736+ union {
737+ /* Name of the powerdomain to add a wkdep/sleepdep on */
738+ const char *name;
739+
740+ /* Powerdomain pointer (looked up at clkdm_init() time) */
741+ struct powerdomain *ptr;
742+ } pwrdm;
743+
744+ /* OMAP chip types that this clockdomain dep is valid on */
745+ const struct omap_chip_id omap_chip;
746+
747+};
748+
749+struct clockdomain {
750+
751+ /* Clockdomain name */
752+ const char *name;
753+
754+ union {
755+ /* Powerdomain enclosing this clockdomain */
756+ const char *name;
757+
758+ /* Powerdomain pointer assigned at clkdm_register() */
759+ struct powerdomain *ptr;
760+ } pwrdm;
761+
762+ /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
763+ const u16 clktrctrl_mask;
764+
765+ /* Clockdomain capability flags */
766+ const u8 flags;
767+
768+ /* OMAP chip types that this clockdomain is valid on */
769+ const struct omap_chip_id omap_chip;
770+
771+ /* Usecount tracking */
772+ atomic_t usecount;
773+
774+ struct list_head node;
775+
776+};
777+
778+void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
779+int clkdm_register(struct clockdomain *clkdm);
780+int clkdm_unregister(struct clockdomain *clkdm);
781+struct clockdomain *clkdm_lookup(const char *name);
782+
783+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
784+ void *user);
785+struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
786+
787+void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
788+void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
789+
790+int omap2_clkdm_wakeup(struct clockdomain *clkdm);
791+int omap2_clkdm_sleep(struct clockdomain *clkdm);
792+
793+int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
794+int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
795+
796+#endif
797Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clock.h
798===================================================================
799--- /dev/null 1970-01-01 00:00:00.000000000 +0000
800@@ -0,0 +1,168 @@
801+/*
802+ * arch/arm/plat-omap/include/mach/clock.h
803+ *
804+ * Copyright (C) 2004 - 2005 Nokia corporation
805+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
806+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
807+ *
808+ * This program is free software; you can redistribute it and/or modify
809+ * it under the terms of the GNU General Public License version 2 as
810+ * published by the Free Software Foundation.
811+ */
812+
813+#ifndef __ARCH_ARM_OMAP_CLOCK_H
814+#define __ARCH_ARM_OMAP_CLOCK_H
815+
816+#include <linux/list.h>
817+
818+struct module;
819+struct clk;
820+struct clockdomain;
821+
822+struct clkops {
823+ int (*enable)(struct clk *);
824+ void (*disable)(struct clk *);
825+ void (*find_idlest)(struct clk *, void __iomem **, u8 *);
826+ void (*find_companion)(struct clk *, void __iomem **, u8 *);
827+};
828+
829+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
830+ defined(CONFIG_ARCH_OMAP4)
831+
832+struct clksel_rate {
833+ u32 val;
834+ u8 div;
835+ u8 flags;
836+};
837+
838+struct clksel {
839+ struct clk *parent;
840+ const struct clksel_rate *rates;
841+};
842+
843+struct dpll_data {
844+ void __iomem *mult_div1_reg;
845+ u32 mult_mask;
846+ u32 div1_mask;
847+ struct clk *clk_bypass;
848+ struct clk *clk_ref;
849+ void __iomem *control_reg;
850+ u32 enable_mask;
851+ unsigned int rate_tolerance;
852+ unsigned long last_rounded_rate;
853+ u16 last_rounded_m;
854+ u8 last_rounded_n;
855+ u8 min_divider;
856+ u8 max_divider;
857+ u32 max_tolerance;
858+ u16 max_multiplier;
859+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
860+ u8 modes;
861+ void __iomem *autoidle_reg;
862+ void __iomem *idlest_reg;
863+ u32 autoidle_mask;
864+ u32 freqsel_mask;
865+ u32 idlest_mask;
866+ u8 auto_recal_bit;
867+ u8 recal_en_bit;
868+ u8 recal_st_bit;
869+# endif
870+};
871+
872+#endif
873+
874+struct clk {
875+ struct list_head node;
876+ const struct clkops *ops;
877+ const char *name;
878+ int id;
879+ struct clk *parent;
880+ struct list_head children;
881+ struct list_head sibling; /* node for children */
882+ unsigned long rate;
883+ __u32 flags;
884+ void __iomem *enable_reg;
885+ unsigned long (*recalc)(struct clk *);
886+ int (*set_rate)(struct clk *, unsigned long);
887+ long (*round_rate)(struct clk *, unsigned long);
888+ void (*init)(struct clk *);
889+ __u8 enable_bit;
890+ __s8 usecount;
891+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
892+ defined(CONFIG_ARCH_OMAP4)
893+ u8 fixed_div;
894+ void __iomem *clksel_reg;
895+ u32 clksel_mask;
896+ const struct clksel *clksel;
897+ struct dpll_data *dpll_data;
898+ const char *clkdm_name;
899+ struct clockdomain *clkdm;
900+#else
901+ __u8 rate_offset;
902+ __u8 src_offset;
903+#endif
904+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
905+ struct dentry *dent; /* For visible tree hierarchy */
906+#endif
907+};
908+
909+struct cpufreq_frequency_table;
910+
911+struct clk_functions {
912+ int (*clk_enable)(struct clk *clk);
913+ void (*clk_disable)(struct clk *clk);
914+ long (*clk_round_rate)(struct clk *clk, unsigned long rate);
915+ int (*clk_set_rate)(struct clk *clk, unsigned long rate);
916+ int (*clk_set_parent)(struct clk *clk, struct clk *parent);
917+ void (*clk_allow_idle)(struct clk *clk);
918+ void (*clk_deny_idle)(struct clk *clk);
919+ void (*clk_disable_unused)(struct clk *clk);
920+#ifdef CONFIG_CPU_FREQ
921+ void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
922+#endif
923+};
924+
925+extern unsigned int mpurate;
926+
927+extern int clk_init(struct clk_functions *custom_clocks);
928+extern void clk_preinit(struct clk *clk);
929+extern int clk_register(struct clk *clk);
930+extern void clk_reparent(struct clk *child, struct clk *parent);
931+extern void clk_unregister(struct clk *clk);
932+extern void propagate_rate(struct clk *clk);
933+extern void recalculate_root_clocks(void);
934+extern unsigned long followparent_recalc(struct clk *clk);
935+extern void clk_enable_init_clocks(void);
936+#ifdef CONFIG_CPU_FREQ
937+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
938+#endif
939+
940+extern const struct clkops clkops_null;
941+
942+/* Clock flags */
943+/* bit 0 is free */
944+#define RATE_FIXED (1 << 1) /* Fixed clock rate */
945+/* bits 2-4 are free */
946+#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
947+#define CLOCK_IDLE_CONTROL (1 << 7)
948+#define CLOCK_NO_IDLE_PARENT (1 << 8)
949+#define DELAYED_APP (1 << 9) /* Delay application of clock */
950+#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
951+#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
952+#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
953+#define CLOCK_IN_OMAP4430 (1 << 13)
954+#define ALWAYS_ENABLED (1 << 14)
955+/* bits 13-31 are currently free */
956+
957+/* Clksel_rate flags */
958+#define DEFAULT_RATE (1 << 0)
959+#define RATE_IN_242X (1 << 1)
960+#define RATE_IN_243X (1 << 2)
961+#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
962+#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
963+#define RATE_IN_4430 (1 << 5)
964+
965+#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
966+
967+
968+#endif
969Index: linux-2.6.35/arch/arm/plat-omap/include/mach/common.h
970===================================================================
971--- /dev/null 1970-01-01 00:00:00.000000000 +0000
972@@ -0,0 +1,83 @@
973+/*
974+ * arch/arm/plat-omap/include/mach/common.h
975+ *
976+ * Header for code common to all OMAP machines.
977+ *
978+ * This program is free software; you can redistribute it and/or modify it
979+ * under the terms of the GNU General Public License as published by the
980+ * Free Software Foundation; either version 2 of the License, or (at your
981+ * option) any later version.
982+ *
983+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
984+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
985+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
986+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
987+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
988+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
989+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
990+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
991+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
992+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
993+ *
994+ * You should have received a copy of the GNU General Public License along
995+ * with this program; if not, write to the Free Software Foundation, Inc.,
996+ * 675 Mass Ave, Cambridge, MA 02139, USA.
997+ */
998+
999+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1000+#define __ARCH_ARM_MACH_OMAP_COMMON_H
1001+
1002+#include <plat/i2c.h>
1003+
1004+struct sys_timer;
1005+
1006+/* used by omap-smp.c and board-4430sdp.c */
1007+extern void __iomem *gic_cpu_base_addr;
1008+
1009+extern void omap_map_common_io(void);
1010+extern struct sys_timer omap_timer;
1011+
1012+/* IO bases for various OMAP processors */
1013+struct omap_globals {
1014+ u32 class; /* OMAP class to detect */
1015+ void __iomem *tap; /* Control module ID code */
1016+ void __iomem *sdrc; /* SDRAM Controller */
1017+ void __iomem *sms; /* SDRAM Memory Scheduler */
1018+ void __iomem *ctrl; /* System Control Module */
1019+ void __iomem *prm; /* Power and Reset Management */
1020+ void __iomem *cm; /* Clock Management */
1021+ void __iomem *cm2;
1022+};
1023+
1024+void omap2_set_globals_242x(void);
1025+void omap2_set_globals_243x(void);
1026+void omap2_set_globals_343x(void);
1027+void omap2_set_globals_443x(void);
1028+
1029+/* These get called from omap2_set_globals_xxxx(), do not call these */
1030+void omap2_set_globals_tap(struct omap_globals *);
1031+void omap2_set_globals_sdrc(struct omap_globals *);
1032+void omap2_set_globals_control(struct omap_globals *);
1033+void omap2_set_globals_prcm(struct omap_globals *);
1034+
1035+/**
1036+ * omap_test_timeout - busy-loop, testing a condition
1037+ * @cond: condition to test until it evaluates to true
1038+ * @timeout: maximum number of microseconds in the timeout
1039+ * @index: loop index (integer)
1040+ *
1041+ * Loop waiting for @cond to become true or until at least @timeout
1042+ * microseconds have passed. To use, define some integer @index in the
1043+ * calling code. After running, if @index == @timeout, then the loop has
1044+ * timed out.
1045+ */
1046+#define omap_test_timeout(cond, timeout, index) \
1047+({ \
1048+ for (index = 0; index < timeout; index++) { \
1049+ if (cond) \
1050+ break; \
1051+ udelay(1); \
1052+ } \
1053+})
1054+
1055+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1056Index: linux-2.6.35/arch/arm/plat-omap/include/mach/control.h
1057===================================================================
1058--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1059@@ -0,0 +1,325 @@
1060+/*
1061+ * arch/arm/plat-omap/include/mach/control.h
1062+ *
1063+ * OMAP2/3/4 System Control Module definitions
1064+ *
1065+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
1066+ * Copyright (C) 2007-2008 Nokia Corporation
1067+ *
1068+ * Written by Paul Walmsley
1069+ *
1070+ * This program is free software; you can redistribute it and/or modify
1071+ * it under the terms of the GNU General Public License as published by
1072+ * the Free Software Foundation.
1073+ */
1074+
1075+#ifndef __ASM_ARCH_CONTROL_H
1076+#define __ASM_ARCH_CONTROL_H
1077+
1078+#include <mach/io.h>
1079+
1080+#ifndef __ASSEMBLY__
1081+#define OMAP242X_CTRL_REGADDR(reg) \
1082+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1083+#define OMAP243X_CTRL_REGADDR(reg) \
1084+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1085+#define OMAP343X_CTRL_REGADDR(reg) \
1086+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1087+#else
1088+#define OMAP242X_CTRL_REGADDR(reg) \
1089+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1090+#define OMAP243X_CTRL_REGADDR(reg) \
1091+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1092+#define OMAP343X_CTRL_REGADDR(reg) \
1093+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1094+#endif /* __ASSEMBLY__ */
1095+
1096+/*
1097+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1098+ * OMAP24XX and OMAP34XX.
1099+ */
1100+
1101+/* Control submodule offsets */
1102+
1103+#define OMAP2_CONTROL_INTERFACE 0x000
1104+#define OMAP2_CONTROL_PADCONFS 0x030
1105+#define OMAP2_CONTROL_GENERAL 0x270
1106+#define OMAP343X_CONTROL_MEM_WKUP 0x600
1107+#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1108+#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1109+
1110+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1111+
1112+#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1113+
1114+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1115+#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1116+#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1117+#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1118+#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1119+#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1120+#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1121+#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1122+#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1123+#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1124+#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1125+#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1126+#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1127+
1128+/* 242x-only CONTROL_GENERAL register offsets */
1129+#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1130+#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1131+
1132+/* 243x-only CONTROL_GENERAL register offsets */
1133+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1134+#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1135+#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1136+#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1137+#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1138+#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1139+#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1140+
1141+/* 24xx-only CONTROL_GENERAL register offsets */
1142+#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1143+#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1144+#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1145+#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1146+#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1147+#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1148+#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1149+#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1150+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1151+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1152+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1153+#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1154+#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1155+#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1156+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1157+#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1158+#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1159+#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1160+#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1161+#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1162+#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1163+#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1164+#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1165+#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1166+#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1167+#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1168+#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1169+#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1170+#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1171+#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1172+#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1173+
1174+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1175+
1176+/* 34xx-only CONTROL_GENERAL register offsets */
1177+#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1178+#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1179+#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1180+#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1181+#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1182+#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1183+#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1184+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1185+#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1186+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1187+#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1188+#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1189+#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1190+#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1191+#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1192+#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1193+#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1194+#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1195+#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1196+#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1197+#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1198+#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1199+#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1200+#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1201+#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1202+#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1203+#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1204+#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1205+#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1206+#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1207+#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1208+#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1209+ + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1210+#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1211+#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1212+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1213+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1214+#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1215+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1216+#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1217+#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1218+#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1219+#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1220+#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1221+
1222+
1223+/* 34xx PADCONF register offsets */
1224+#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1225+ (i)*2)
1226+#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1227+#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1228+#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1229+#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1230+#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1231+#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1232+#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1233+#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1234+#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1235+#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1236+#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1237+#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1238+#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1239+#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1240+#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1241+#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1242+#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1243+#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1244+
1245+/* 34xx GENERAL_WKUP regist offsets */
1246+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1247+ 0x008 + (i))
1248+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1249+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1250+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1251+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1252+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1253+
1254+/* 34xx D2D idle-related pins, handled by PM core */
1255+#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1256+#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1257+
1258+/*
1259+ * REVISIT: This list of registers is not comprehensive - there are more
1260+ * that should be added.
1261+ */
1262+
1263+/*
1264+ * Control module register bit defines - these should eventually go into
1265+ * their own regbits file. Some of these will be complicated, depending
1266+ * on the device type (general-purpose, emulator, test, secure, bad, other)
1267+ * and the security mode (secure, non-secure, don't care)
1268+ */
1269+/* CONTROL_DEVCONF0 bits */
1270+#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1271+#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1272+#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1273+#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1274+
1275+/* CONTROL_DEVCONF1 bits */
1276+#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1277+#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1278+#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1279+#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1280+#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1281+
1282+/* CONTROL_STATUS bits */
1283+#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1284+#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1285+#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1286+#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1287+#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1288+#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1289+#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1290+
1291+/* CONTROL_PBIAS_LITE bits */
1292+#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1293+#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1294+#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1295+#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1296+#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1297+#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1298+#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1299+#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1300+#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1301+#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1302+
1303+/* CONTROL_PROG_IO1 bits */
1304+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1305+
1306+/* CONTROL_IVA2_BOOTMOD bits */
1307+#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1308+#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1309+#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1310+
1311+/* CONTROL_PADCONF_X bits */
1312+#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1313+#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1314+
1315+#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1316+#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1317+#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1318+
1319+/*
1320+ * CONTROL OMAP STATUS register to identify OMAP3 features
1321+ */
1322+#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1323+
1324+#define OMAP3_SGX_SHIFT 13
1325+#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1326+#define FEAT_SGX_FULL 0
1327+#define FEAT_SGX_HALF 1
1328+#define FEAT_SGX_NONE 2
1329+
1330+#define OMAP3_IVA_SHIFT 12
1331+#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1332+#define FEAT_IVA 0
1333+#define FEAT_IVA_NONE 1
1334+
1335+#define OMAP3_L2CACHE_SHIFT 10
1336+#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1337+#define FEAT_L2CACHE_NONE 0
1338+#define FEAT_L2CACHE_64KB 1
1339+#define FEAT_L2CACHE_128KB 2
1340+#define FEAT_L2CACHE_256KB 3
1341+
1342+#define OMAP3_ISP_SHIFT 5
1343+#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1344+#define FEAT_ISP 0
1345+#define FEAT_ISP_NONE 1
1346+
1347+#define OMAP3_NEON_SHIFT 4
1348+#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1349+#define FEAT_NEON 0
1350+#define FEAT_NEON_NONE 1
1351+
1352+
1353+#ifndef __ASSEMBLY__
1354+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1355+ defined(CONFIG_ARCH_OMAP4)
1356+extern void __iomem *omap_ctrl_base_get(void);
1357+extern u8 omap_ctrl_readb(u16 offset);
1358+extern u16 omap_ctrl_readw(u16 offset);
1359+extern u32 omap_ctrl_readl(u16 offset);
1360+extern void omap_ctrl_writeb(u8 val, u16 offset);
1361+extern void omap_ctrl_writew(u16 val, u16 offset);
1362+extern void omap_ctrl_writel(u32 val, u16 offset);
1363+
1364+extern void omap3_save_scratchpad_contents(void);
1365+extern void omap3_clear_scratchpad_contents(void);
1366+extern u32 *get_restore_pointer(void);
1367+extern u32 *get_es3_restore_pointer(void);
1368+extern u32 omap3_arm_context[128];
1369+extern void omap3_control_save_context(void);
1370+extern void omap3_control_restore_context(void);
1371+
1372+#else
1373+#define omap_ctrl_base_get() 0
1374+#define omap_ctrl_readb(x) 0
1375+#define omap_ctrl_readw(x) 0
1376+#define omap_ctrl_readl(x) 0
1377+#define omap_ctrl_writeb(x, y) WARN_ON(1)
1378+#define omap_ctrl_writew(x, y) WARN_ON(1)
1379+#define omap_ctrl_writel(x, y) WARN_ON(1)
1380+#endif
1381+#endif /* __ASSEMBLY__ */
1382+
1383+#endif /* __ASM_ARCH_CONTROL_H */
1384+
1385Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cpu.h
1386===================================================================
1387--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1388@@ -0,0 +1,516 @@
1389+/*
1390+ * arch/arm/plat-omap/include/mach/cpu.h
1391+ *
1392+ * OMAP cpu type detection
1393+ *
1394+ * Copyright (C) 2004, 2008 Nokia Corporation
1395+ *
1396+ * Copyright (C) 2009 Texas Instruments.
1397+ *
1398+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
1399+ *
1400+ * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1401+ *
1402+ * This program is free software; you can redistribute it and/or modify
1403+ * it under the terms of the GNU General Public License as published by
1404+ * the Free Software Foundation; either version 2 of the License, or
1405+ * (at your option) any later version.
1406+ *
1407+ * This program is distributed in the hope that it will be useful,
1408+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1409+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1410+ * GNU General Public License for more details.
1411+ *
1412+ * You should have received a copy of the GNU General Public License
1413+ * along with this program; if not, write to the Free Software
1414+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1415+ *
1416+ */
1417+
1418+#ifndef __ASM_ARCH_OMAP_CPU_H
1419+#define __ASM_ARCH_OMAP_CPU_H
1420+
1421+#include <linux/bitops.h>
1422+
1423+/*
1424+ * Omap device type i.e. EMU/HS/TST/GP/BAD
1425+ */
1426+#define OMAP2_DEVICE_TYPE_TEST 0
1427+#define OMAP2_DEVICE_TYPE_EMU 1
1428+#define OMAP2_DEVICE_TYPE_SEC 2
1429+#define OMAP2_DEVICE_TYPE_GP 3
1430+#define OMAP2_DEVICE_TYPE_BAD 4
1431+
1432+int omap_type(void);
1433+
1434+struct omap_chip_id {
1435+ u8 oc;
1436+ u8 type;
1437+};
1438+
1439+#define OMAP_CHIP_INIT(x) { .oc = x }
1440+
1441+/*
1442+ * omap_rev bits:
1443+ * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1444+ * CPU revision (See _REV_ defined in cpu.h) [15:08]
1445+ * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1446+ */
1447+unsigned int omap_rev(void);
1448+
1449+/*
1450+ * Define CPU revision bits
1451+ *
1452+ * Verbose meaning of the revision bits may be different for a silicon
1453+ * family. This difference can be handled separately.
1454+ */
1455+#define OMAP_REVBITS_00 0x00
1456+#define OMAP_REVBITS_10 0x10
1457+#define OMAP_REVBITS_20 0x20
1458+#define OMAP_REVBITS_30 0x30
1459+#define OMAP_REVBITS_40 0x40
1460+
1461+/*
1462+ * Get the CPU revision for OMAP devices
1463+ */
1464+#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1465+
1466+/*
1467+ * Test if multicore OMAP support is needed
1468+ */
1469+#undef MULTI_OMAP1
1470+#undef MULTI_OMAP2
1471+#undef OMAP_NAME
1472+
1473+#ifdef CONFIG_ARCH_OMAP730
1474+# ifdef OMAP_NAME
1475+# undef MULTI_OMAP1
1476+# define MULTI_OMAP1
1477+# else
1478+# define OMAP_NAME omap730
1479+# endif
1480+#endif
1481+#ifdef CONFIG_ARCH_OMAP850
1482+# ifdef OMAP_NAME
1483+# undef MULTI_OMAP1
1484+# define MULTI_OMAP1
1485+# else
1486+# define OMAP_NAME omap850
1487+# endif
1488+#endif
1489+#ifdef CONFIG_ARCH_OMAP15XX
1490+# ifdef OMAP_NAME
1491+# undef MULTI_OMAP1
1492+# define MULTI_OMAP1
1493+# else
1494+# define OMAP_NAME omap1510
1495+# endif
1496+#endif
1497+#ifdef CONFIG_ARCH_OMAP16XX
1498+# ifdef OMAP_NAME
1499+# undef MULTI_OMAP1
1500+# define MULTI_OMAP1
1501+# else
1502+# define OMAP_NAME omap16xx
1503+# endif
1504+#endif
1505+#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1506+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1507+# error "OMAP1 and OMAP2 can't be selected at the same time"
1508+# endif
1509+#endif
1510+#ifdef CONFIG_ARCH_OMAP2420
1511+# ifdef OMAP_NAME
1512+# undef MULTI_OMAP2
1513+# define MULTI_OMAP2
1514+# else
1515+# define OMAP_NAME omap2420
1516+# endif
1517+#endif
1518+#ifdef CONFIG_ARCH_OMAP2430
1519+# ifdef OMAP_NAME
1520+# undef MULTI_OMAP2
1521+# define MULTI_OMAP2
1522+# else
1523+# define OMAP_NAME omap2430
1524+# endif
1525+#endif
1526+#ifdef CONFIG_ARCH_OMAP3430
1527+# ifdef OMAP_NAME
1528+# undef MULTI_OMAP2
1529+# define MULTI_OMAP2
1530+# else
1531+# define OMAP_NAME omap3430
1532+# endif
1533+#endif
1534+
1535+/*
1536+ * Macros to group OMAP into cpu classes.
1537+ * These can be used in most places.
1538+ * cpu_is_omap7xx(): True for OMAP730, OMAP850
1539+ * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1540+ * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1541+ * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1542+ * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1543+ * cpu_is_omap243x(): True for OMAP2430
1544+ * cpu_is_omap343x(): True for OMAP3430
1545+ */
1546+#define GET_OMAP_CLASS (omap_rev() & 0xff)
1547+
1548+#define IS_OMAP_CLASS(class, id) \
1549+static inline int is_omap ##class (void) \
1550+{ \
1551+ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1552+}
1553+
1554+#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1555+
1556+#define IS_OMAP_SUBCLASS(subclass, id) \
1557+static inline int is_omap ##subclass (void) \
1558+{ \
1559+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1560+}
1561+
1562+IS_OMAP_CLASS(7xx, 0x07)
1563+IS_OMAP_CLASS(15xx, 0x15)
1564+IS_OMAP_CLASS(16xx, 0x16)
1565+IS_OMAP_CLASS(24xx, 0x24)
1566+IS_OMAP_CLASS(34xx, 0x34)
1567+IS_OMAP_CLASS(44xx, 0x44)
1568+
1569+IS_OMAP_SUBCLASS(242x, 0x242)
1570+IS_OMAP_SUBCLASS(243x, 0x243)
1571+IS_OMAP_SUBCLASS(343x, 0x343)
1572+IS_OMAP_SUBCLASS(363x, 0x363)
1573+IS_OMAP_SUBCLASS(443x, 0x443)
1574+
1575+#define cpu_is_omap7xx() 0
1576+#define cpu_is_omap15xx() 0
1577+#define cpu_is_omap16xx() 0
1578+#define cpu_is_omap24xx() 0
1579+#define cpu_is_omap242x() 0
1580+#define cpu_is_omap243x() 0
1581+#define cpu_is_omap34xx() 0
1582+#define cpu_is_omap343x() 0
1583+#define cpu_is_omap44xx() 0
1584+#define cpu_is_omap443x() 0
1585+
1586+#if defined(MULTI_OMAP1)
1587+# if defined(CONFIG_ARCH_OMAP730)
1588+# undef cpu_is_omap7xx
1589+# define cpu_is_omap7xx() is_omap7xx()
1590+# endif
1591+# if defined(CONFIG_ARCH_OMAP850)
1592+# undef cpu_is_omap7xx
1593+# define cpu_is_omap7xx() is_omap7xx()
1594+# endif
1595+# if defined(CONFIG_ARCH_OMAP15XX)
1596+# undef cpu_is_omap15xx
1597+# define cpu_is_omap15xx() is_omap15xx()
1598+# endif
1599+# if defined(CONFIG_ARCH_OMAP16XX)
1600+# undef cpu_is_omap16xx
1601+# define cpu_is_omap16xx() is_omap16xx()
1602+# endif
1603+#else
1604+# if defined(CONFIG_ARCH_OMAP730)
1605+# undef cpu_is_omap7xx
1606+# define cpu_is_omap7xx() 1
1607+# endif
1608+# if defined(CONFIG_ARCH_OMAP850)
1609+# undef cpu_is_omap7xx
1610+# define cpu_is_omap7xx() 1
1611+# endif
1612+# if defined(CONFIG_ARCH_OMAP15XX)
1613+# undef cpu_is_omap15xx
1614+# define cpu_is_omap15xx() 1
1615+# endif
1616+# if defined(CONFIG_ARCH_OMAP16XX)
1617+# undef cpu_is_omap16xx
1618+# define cpu_is_omap16xx() 1
1619+# endif
1620+#endif
1621+
1622+#if defined(MULTI_OMAP2)
1623+# if defined(CONFIG_ARCH_OMAP24XX)
1624+# undef cpu_is_omap24xx
1625+# undef cpu_is_omap242x
1626+# undef cpu_is_omap243x
1627+# define cpu_is_omap24xx() is_omap24xx()
1628+# define cpu_is_omap242x() is_omap242x()
1629+# define cpu_is_omap243x() is_omap243x()
1630+# endif
1631+# if defined(CONFIG_ARCH_OMAP34XX)
1632+# undef cpu_is_omap34xx
1633+# undef cpu_is_omap343x
1634+# define cpu_is_omap34xx() is_omap34xx()
1635+# define cpu_is_omap343x() is_omap343x()
1636+# endif
1637+#else
1638+# if defined(CONFIG_ARCH_OMAP24XX)
1639+# undef cpu_is_omap24xx
1640+# define cpu_is_omap24xx() 1
1641+# endif
1642+# if defined(CONFIG_ARCH_OMAP2420)
1643+# undef cpu_is_omap242x
1644+# define cpu_is_omap242x() 1
1645+# endif
1646+# if defined(CONFIG_ARCH_OMAP2430)
1647+# undef cpu_is_omap243x
1648+# define cpu_is_omap243x() 1
1649+# endif
1650+# if defined(CONFIG_ARCH_OMAP34XX)
1651+# undef cpu_is_omap34xx
1652+# define cpu_is_omap34xx() 1
1653+# endif
1654+# if defined(CONFIG_ARCH_OMAP3430)
1655+# undef cpu_is_omap343x
1656+# define cpu_is_omap343x() 1
1657+# endif
1658+#endif
1659+
1660+/*
1661+ * Macros to detect individual cpu types.
1662+ * These are only rarely needed.
1663+ * cpu_is_omap330(): True for OMAP330
1664+ * cpu_is_omap730(): True for OMAP730
1665+ * cpu_is_omap850(): True for OMAP850
1666+ * cpu_is_omap1510(): True for OMAP1510
1667+ * cpu_is_omap1610(): True for OMAP1610
1668+ * cpu_is_omap1611(): True for OMAP1611
1669+ * cpu_is_omap5912(): True for OMAP5912
1670+ * cpu_is_omap1621(): True for OMAP1621
1671+ * cpu_is_omap1710(): True for OMAP1710
1672+ * cpu_is_omap2420(): True for OMAP2420
1673+ * cpu_is_omap2422(): True for OMAP2422
1674+ * cpu_is_omap2423(): True for OMAP2423
1675+ * cpu_is_omap2430(): True for OMAP2430
1676+ * cpu_is_omap3430(): True for OMAP3430
1677+ * cpu_is_omap3505(): True for OMAP3505
1678+ * cpu_is_omap3517(): True for OMAP3517
1679+ */
1680+#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1681+
1682+#define IS_OMAP_TYPE(type, id) \
1683+static inline int is_omap ##type (void) \
1684+{ \
1685+ return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1686+}
1687+
1688+IS_OMAP_TYPE(310, 0x0310)
1689+IS_OMAP_TYPE(730, 0x0730)
1690+IS_OMAP_TYPE(850, 0x0850)
1691+IS_OMAP_TYPE(1510, 0x1510)
1692+IS_OMAP_TYPE(1610, 0x1610)
1693+IS_OMAP_TYPE(1611, 0x1611)
1694+IS_OMAP_TYPE(5912, 0x1611)
1695+IS_OMAP_TYPE(1621, 0x1621)
1696+IS_OMAP_TYPE(1710, 0x1710)
1697+IS_OMAP_TYPE(2420, 0x2420)
1698+IS_OMAP_TYPE(2422, 0x2422)
1699+IS_OMAP_TYPE(2423, 0x2423)
1700+IS_OMAP_TYPE(2430, 0x2430)
1701+IS_OMAP_TYPE(3430, 0x3430)
1702+IS_OMAP_TYPE(3505, 0x3505)
1703+IS_OMAP_TYPE(3517, 0x3517)
1704+
1705+#define cpu_is_omap310() 0
1706+#define cpu_is_omap730() 0
1707+#define cpu_is_omap850() 0
1708+#define cpu_is_omap1510() 0
1709+#define cpu_is_omap1610() 0
1710+#define cpu_is_omap5912() 0
1711+#define cpu_is_omap1611() 0
1712+#define cpu_is_omap1621() 0
1713+#define cpu_is_omap1710() 0
1714+#define cpu_is_omap2420() 0
1715+#define cpu_is_omap2422() 0
1716+#define cpu_is_omap2423() 0
1717+#define cpu_is_omap2430() 0
1718+#define cpu_is_omap3503() 0
1719+#define cpu_is_omap3515() 0
1720+#define cpu_is_omap3525() 0
1721+#define cpu_is_omap3530() 0
1722+#define cpu_is_omap3505() 0
1723+#define cpu_is_omap3517() 0
1724+#define cpu_is_omap3430() 0
1725+#define cpu_is_omap3630() 0
1726+
1727+/*
1728+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1729+ * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1730+ */
1731+
1732+#if defined(CONFIG_ARCH_OMAP730)
1733+# undef cpu_is_omap730
1734+# define cpu_is_omap730() is_omap730()
1735+#endif
1736+
1737+#if defined(CONFIG_ARCH_OMAP850)
1738+# undef cpu_is_omap850
1739+# define cpu_is_omap850() is_omap850()
1740+#endif
1741+
1742+#if defined(CONFIG_ARCH_OMAP15XX)
1743+# undef cpu_is_omap310
1744+# undef cpu_is_omap1510
1745+# define cpu_is_omap310() is_omap310()
1746+# define cpu_is_omap1510() is_omap1510()
1747+#endif
1748+
1749+#if defined(CONFIG_ARCH_OMAP16XX)
1750+# undef cpu_is_omap1610
1751+# undef cpu_is_omap1611
1752+# undef cpu_is_omap5912
1753+# undef cpu_is_omap1621
1754+# undef cpu_is_omap1710
1755+# define cpu_is_omap1610() is_omap1610()
1756+# define cpu_is_omap1611() is_omap1611()
1757+# define cpu_is_omap5912() is_omap5912()
1758+# define cpu_is_omap1621() is_omap1621()
1759+# define cpu_is_omap1710() is_omap1710()
1760+#endif
1761+
1762+#if defined(CONFIG_ARCH_OMAP24XX)
1763+# undef cpu_is_omap2420
1764+# undef cpu_is_omap2422
1765+# undef cpu_is_omap2423
1766+# undef cpu_is_omap2430
1767+# define cpu_is_omap2420() is_omap2420()
1768+# define cpu_is_omap2422() is_omap2422()
1769+# define cpu_is_omap2423() is_omap2423()
1770+# define cpu_is_omap2430() is_omap2430()
1771+#endif
1772+
1773+#if defined(CONFIG_ARCH_OMAP34XX)
1774+# undef cpu_is_omap3430
1775+# undef cpu_is_omap3503
1776+# undef cpu_is_omap3515
1777+# undef cpu_is_omap3525
1778+# undef cpu_is_omap3530
1779+# undef cpu_is_omap3505
1780+# undef cpu_is_omap3517
1781+# define cpu_is_omap3430() is_omap3430()
1782+# define cpu_is_omap3503() (cpu_is_omap3430() && \
1783+ (!omap3_has_iva()) && \
1784+ (!omap3_has_sgx()))
1785+# define cpu_is_omap3515() (cpu_is_omap3430() && \
1786+ (!omap3_has_iva()) && \
1787+ (omap3_has_sgx()))
1788+# define cpu_is_omap3525() (cpu_is_omap3430() && \
1789+ (!omap3_has_sgx()) && \
1790+ (omap3_has_iva()))
1791+# define cpu_is_omap3530() (cpu_is_omap3430())
1792+# define cpu_is_omap3505() is_omap3505()
1793+# define cpu_is_omap3517() is_omap3517()
1794+# undef cpu_is_omap3630
1795+# define cpu_is_omap3630() is_omap363x()
1796+#endif
1797+
1798+# if defined(CONFIG_ARCH_OMAP4)
1799+# undef cpu_is_omap44xx
1800+# undef cpu_is_omap443x
1801+# define cpu_is_omap44xx() is_omap44xx()
1802+# define cpu_is_omap443x() is_omap443x()
1803+# endif
1804+
1805+/* Macros to detect if we have OMAP1 or OMAP2 */
1806+#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1807+ cpu_is_omap16xx())
1808+#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1809+ cpu_is_omap44xx())
1810+
1811+/* Various silicon revisions for omap2 */
1812+#define OMAP242X_CLASS 0x24200024
1813+#define OMAP2420_REV_ES1_0 0x24200024
1814+#define OMAP2420_REV_ES2_0 0x24201024
1815+
1816+#define OMAP243X_CLASS 0x24300024
1817+#define OMAP2430_REV_ES1_0 0x24300024
1818+
1819+#define OMAP343X_CLASS 0x34300034
1820+#define OMAP3430_REV_ES1_0 0x34300034
1821+#define OMAP3430_REV_ES2_0 0x34301034
1822+#define OMAP3430_REV_ES2_1 0x34302034
1823+#define OMAP3430_REV_ES3_0 0x34303034
1824+#define OMAP3430_REV_ES3_1 0x34304034
1825+
1826+#define OMAP3630_REV_ES1_0 0x36300034
1827+
1828+#define OMAP35XX_CLASS 0x35000034
1829+#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1830+#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1831+#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1832+#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1833+#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1834+#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1835+
1836+#define OMAP443X_CLASS 0x44300044
1837+#define OMAP4430_REV_ES1_0 0x44300044
1838+
1839+/*
1840+ * omap_chip bits
1841+ *
1842+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1843+ * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1844+ * something that is only valid on that particular ES revision.
1845+ *
1846+ * These bits may be ORed together to indicate structures that are
1847+ * available on multiple chip types.
1848+ *
1849+ * To test whether a particular structure matches the current OMAP chip type,
1850+ * use omap_chip_is().
1851+ *
1852+ */
1853+#define CHIP_IS_OMAP2420 (1 << 0)
1854+#define CHIP_IS_OMAP2430 (1 << 1)
1855+#define CHIP_IS_OMAP3430 (1 << 2)
1856+#define CHIP_IS_OMAP3430ES1 (1 << 3)
1857+#define CHIP_IS_OMAP3430ES2 (1 << 4)
1858+#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1859+#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1860+#define CHIP_IS_OMAP3630ES1 (1 << 7)
1861+
1862+#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1863+
1864+/*
1865+ * "GE" here represents "greater than or equal to" in terms of ES
1866+ * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1867+ * chips at ES2 and beyond, but not, for example, any OMAP lines after
1868+ * OMAP3.
1869+ */
1870+#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1871+ CHIP_IS_OMAP3430ES3_0 | \
1872+ CHIP_IS_OMAP3430ES3_1 | \
1873+ CHIP_IS_OMAP3630ES1)
1874+#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1875+ CHIP_IS_OMAP3630ES1)
1876+
1877+
1878+int omap_chip_is(struct omap_chip_id oci);
1879+void omap2_check_revision(void);
1880+
1881+/*
1882+ * Runtime detection of OMAP3 features
1883+ */
1884+extern u32 omap3_features;
1885+
1886+#define OMAP3_HAS_L2CACHE BIT(0)
1887+#define OMAP3_HAS_IVA BIT(1)
1888+#define OMAP3_HAS_SGX BIT(2)
1889+#define OMAP3_HAS_NEON BIT(3)
1890+#define OMAP3_HAS_ISP BIT(4)
1891+
1892+#define OMAP3_HAS_FEATURE(feat,flag) \
1893+static inline unsigned int omap3_has_ ##feat(void) \
1894+{ \
1895+ return (omap3_features & OMAP3_HAS_ ##flag); \
1896+} \
1897+
1898+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
1899+OMAP3_HAS_FEATURE(sgx, SGX)
1900+OMAP3_HAS_FEATURE(iva, IVA)
1901+OMAP3_HAS_FEATURE(neon, NEON)
1902+OMAP3_HAS_FEATURE(isp, ISP)
1903+
1904+#endif
1905Index: linux-2.6.35/arch/arm/plat-omap/include/mach/display.h
1906===================================================================
1907--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1908@@ -0,0 +1,575 @@
1909+/*
1910+ * linux/include/asm-arm/arch-omap/display.h
1911+ *
1912+ * Copyright (C) 2008 Nokia Corporation
1913+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1914+ *
1915+ * This program is free software; you can redistribute it and/or modify it
1916+ * under the terms of the GNU General Public License version 2 as published by
1917+ * the Free Software Foundation.
1918+ *
1919+ * This program is distributed in the hope that it will be useful, but WITHOUT
1920+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1921+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1922+ * more details.
1923+ *
1924+ * You should have received a copy of the GNU General Public License along with
1925+ * this program. If not, see <http://www.gnu.org/licenses/>.
1926+ */
1927+
1928+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
1929+#define __ASM_ARCH_OMAP_DISPLAY_H
1930+
1931+#include <linux/list.h>
1932+#include <linux/kobject.h>
1933+#include <linux/device.h>
1934+#include <asm/atomic.h>
1935+
1936+#define DISPC_IRQ_FRAMEDONE (1 << 0)
1937+#define DISPC_IRQ_VSYNC (1 << 1)
1938+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
1939+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
1940+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
1941+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
1942+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
1943+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
1944+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
1945+#define DISPC_IRQ_OCP_ERR (1 << 9)
1946+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
1947+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
1948+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
1949+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
1950+#define DISPC_IRQ_SYNC_LOST (1 << 14)
1951+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
1952+#define DISPC_IRQ_WAKEUP (1 << 16)
1953+
1954+struct omap_dss_device;
1955+struct omap_overlay_manager;
1956+
1957+enum omap_display_type {
1958+ OMAP_DISPLAY_TYPE_NONE = 0,
1959+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
1960+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
1961+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
1962+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
1963+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
1964+};
1965+
1966+enum omap_plane {
1967+ OMAP_DSS_GFX = 0,
1968+ OMAP_DSS_VIDEO1 = 1,
1969+ OMAP_DSS_VIDEO2 = 2
1970+};
1971+
1972+enum omap_channel {
1973+ OMAP_DSS_CHANNEL_LCD = 0,
1974+ OMAP_DSS_CHANNEL_DIGIT = 1,
1975+};
1976+
1977+enum omap_color_mode {
1978+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
1979+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
1980+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
1981+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
1982+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
1983+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
1984+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
1985+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
1986+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
1987+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
1988+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
1989+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
1990+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
1991+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
1992+
1993+ OMAP_DSS_COLOR_GFX_OMAP2 =
1994+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
1995+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
1996+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
1997+ OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
1998+
1999+ OMAP_DSS_COLOR_VID_OMAP2 =
2000+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2001+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2002+ OMAP_DSS_COLOR_UYVY,
2003+
2004+ OMAP_DSS_COLOR_GFX_OMAP3 =
2005+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2006+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2007+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2008+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2009+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2010+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2011+
2012+ OMAP_DSS_COLOR_VID1_OMAP3 =
2013+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2014+ OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2015+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2016+
2017+ OMAP_DSS_COLOR_VID2_OMAP3 =
2018+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2019+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2020+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2021+ OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2022+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2023+};
2024+
2025+enum omap_lcd_display_type {
2026+ OMAP_DSS_LCD_DISPLAY_STN,
2027+ OMAP_DSS_LCD_DISPLAY_TFT,
2028+};
2029+
2030+enum omap_dss_load_mode {
2031+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2032+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
2033+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
2034+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2035+};
2036+
2037+enum omap_dss_trans_key_type {
2038+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2039+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2040+};
2041+
2042+enum omap_rfbi_te_mode {
2043+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
2044+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
2045+};
2046+
2047+enum omap_panel_config {
2048+ OMAP_DSS_LCD_IVS = 1<<0,
2049+ OMAP_DSS_LCD_IHS = 1<<1,
2050+ OMAP_DSS_LCD_IPC = 1<<2,
2051+ OMAP_DSS_LCD_IEO = 1<<3,
2052+ OMAP_DSS_LCD_RF = 1<<4,
2053+ OMAP_DSS_LCD_ONOFF = 1<<5,
2054+
2055+ OMAP_DSS_LCD_TFT = 1<<20,
2056+};
2057+
2058+enum omap_dss_venc_type {
2059+ OMAP_DSS_VENC_TYPE_COMPOSITE,
2060+ OMAP_DSS_VENC_TYPE_SVIDEO,
2061+};
2062+
2063+enum omap_display_caps {
2064+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2065+ OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2066+};
2067+
2068+enum omap_dss_update_mode {
2069+ OMAP_DSS_UPDATE_DISABLED = 0,
2070+ OMAP_DSS_UPDATE_AUTO,
2071+ OMAP_DSS_UPDATE_MANUAL,
2072+};
2073+
2074+enum omap_dss_display_state {
2075+ OMAP_DSS_DISPLAY_DISABLED = 0,
2076+ OMAP_DSS_DISPLAY_ACTIVE,
2077+ OMAP_DSS_DISPLAY_SUSPENDED,
2078+};
2079+
2080+/* XXX perhaps this should be removed */
2081+enum omap_dss_overlay_managers {
2082+ OMAP_DSS_OVL_MGR_LCD,
2083+ OMAP_DSS_OVL_MGR_TV,
2084+};
2085+
2086+enum omap_dss_rotation_type {
2087+ OMAP_DSS_ROT_DMA = 0,
2088+ OMAP_DSS_ROT_VRFB = 1,
2089+};
2090+
2091+/* clockwise rotation angle */
2092+enum omap_dss_rotation_angle {
2093+ OMAP_DSS_ROT_0 = 0,
2094+ OMAP_DSS_ROT_90 = 1,
2095+ OMAP_DSS_ROT_180 = 2,
2096+ OMAP_DSS_ROT_270 = 3,
2097+};
2098+
2099+enum omap_overlay_caps {
2100+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2101+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2102+};
2103+
2104+enum omap_overlay_manager_caps {
2105+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2106+};
2107+
2108+/* RFBI */
2109+
2110+struct rfbi_timings {
2111+ int cs_on_time;
2112+ int cs_off_time;
2113+ int we_on_time;
2114+ int we_off_time;
2115+ int re_on_time;
2116+ int re_off_time;
2117+ int we_cycle_time;
2118+ int re_cycle_time;
2119+ int cs_pulse_width;
2120+ int access_time;
2121+
2122+ int clk_div;
2123+
2124+ u32 tim[5]; /* set by rfbi_convert_timings() */
2125+
2126+ int converted;
2127+};
2128+
2129+void omap_rfbi_write_command(const void *buf, u32 len);
2130+void omap_rfbi_read_data(void *buf, u32 len);
2131+void omap_rfbi_write_data(const void *buf, u32 len);
2132+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2133+ u16 x, u16 y,
2134+ u16 w, u16 h);
2135+int omap_rfbi_enable_te(bool enable, unsigned line);
2136+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2137+ unsigned hs_pulse_time, unsigned vs_pulse_time,
2138+ int hs_pol_inv, int vs_pol_inv, int extif_div);
2139+
2140+/* DSI */
2141+void dsi_bus_lock(void);
2142+void dsi_bus_unlock(void);
2143+int dsi_vc_dcs_write(int channel, u8 *data, int len);
2144+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2145+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2146+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2147+int dsi_vc_send_null(int channel);
2148+int dsi_vc_send_bta_sync(int channel);
2149+
2150+/* Board specific data */
2151+struct omap_dss_board_info {
2152+ int (*get_last_off_on_transaction_id)(struct device *dev);
2153+ int num_devices;
2154+ struct omap_dss_device **devices;
2155+ struct omap_dss_device *default_device;
2156+};
2157+
2158+struct omap_video_timings {
2159+ /* Unit: pixels */
2160+ u16 x_res;
2161+ /* Unit: pixels */
2162+ u16 y_res;
2163+ /* Unit: KHz */
2164+ u32 pixel_clock;
2165+ /* Unit: pixel clocks */
2166+ u16 hsw; /* Horizontal synchronization pulse width */
2167+ /* Unit: pixel clocks */
2168+ u16 hfp; /* Horizontal front porch */
2169+ /* Unit: pixel clocks */
2170+ u16 hbp; /* Horizontal back porch */
2171+ /* Unit: line clocks */
2172+ u16 vsw; /* Vertical synchronization pulse width */
2173+ /* Unit: line clocks */
2174+ u16 vfp; /* Vertical front porch */
2175+ /* Unit: line clocks */
2176+ u16 vbp; /* Vertical back porch */
2177+};
2178+
2179+#ifdef CONFIG_OMAP2_DSS_VENC
2180+/* Hardcoded timings for tv modes. Venc only uses these to
2181+ * identify the mode, and does not actually use the configs
2182+ * itself. However, the configs should be something that
2183+ * a normal monitor can also show */
2184+const extern struct omap_video_timings omap_dss_pal_timings;
2185+const extern struct omap_video_timings omap_dss_ntsc_timings;
2186+#endif
2187+
2188+struct omap_overlay_info {
2189+ bool enabled;
2190+
2191+ u32 paddr;
2192+ void __iomem *vaddr;
2193+ u16 screen_width;
2194+ u16 width;
2195+ u16 height;
2196+ enum omap_color_mode color_mode;
2197+ u8 rotation;
2198+ enum omap_dss_rotation_type rotation_type;
2199+ bool mirror;
2200+
2201+ u16 pos_x;
2202+ u16 pos_y;
2203+ u16 out_width; /* if 0, out_width == width */
2204+ u16 out_height; /* if 0, out_height == height */
2205+ u8 global_alpha;
2206+};
2207+
2208+struct omap_overlay {
2209+ struct kobject kobj;
2210+ struct list_head list;
2211+
2212+ /* static fields */
2213+ const char *name;
2214+ int id;
2215+ enum omap_color_mode supported_modes;
2216+ enum omap_overlay_caps caps;
2217+
2218+ /* dynamic fields */
2219+ struct omap_overlay_manager *manager;
2220+ struct omap_overlay_info info;
2221+
2222+ /* if true, info has been changed, but not applied() yet */
2223+ bool info_dirty;
2224+
2225+ int (*set_manager)(struct omap_overlay *ovl,
2226+ struct omap_overlay_manager *mgr);
2227+ int (*unset_manager)(struct omap_overlay *ovl);
2228+
2229+ int (*set_overlay_info)(struct omap_overlay *ovl,
2230+ struct omap_overlay_info *info);
2231+ void (*get_overlay_info)(struct omap_overlay *ovl,
2232+ struct omap_overlay_info *info);
2233+
2234+ int (*wait_for_go)(struct omap_overlay *ovl);
2235+};
2236+
2237+struct omap_overlay_manager_info {
2238+ u32 default_color;
2239+
2240+ enum omap_dss_trans_key_type trans_key_type;
2241+ u32 trans_key;
2242+ bool trans_enabled;
2243+
2244+ bool alpha_enabled;
2245+};
2246+
2247+struct omap_overlay_manager {
2248+ struct kobject kobj;
2249+ struct list_head list;
2250+
2251+ /* static fields */
2252+ const char *name;
2253+ int id;
2254+ enum omap_overlay_manager_caps caps;
2255+ int num_overlays;
2256+ struct omap_overlay **overlays;
2257+ enum omap_display_type supported_displays;
2258+
2259+ /* dynamic fields */
2260+ struct omap_dss_device *device;
2261+ struct omap_overlay_manager_info info;
2262+
2263+ bool device_changed;
2264+ /* if true, info has been changed but not applied() yet */
2265+ bool info_dirty;
2266+
2267+ int (*set_device)(struct omap_overlay_manager *mgr,
2268+ struct omap_dss_device *dssdev);
2269+ int (*unset_device)(struct omap_overlay_manager *mgr);
2270+
2271+ int (*set_manager_info)(struct omap_overlay_manager *mgr,
2272+ struct omap_overlay_manager_info *info);
2273+ void (*get_manager_info)(struct omap_overlay_manager *mgr,
2274+ struct omap_overlay_manager_info *info);
2275+
2276+ int (*apply)(struct omap_overlay_manager *mgr);
2277+ int (*wait_for_go)(struct omap_overlay_manager *mgr);
2278+};
2279+
2280+struct omap_dss_device {
2281+ struct device dev;
2282+
2283+ enum omap_display_type type;
2284+
2285+ union {
2286+ struct {
2287+ u8 data_lines;
2288+ } dpi;
2289+
2290+ struct {
2291+ u8 channel;
2292+ u8 data_lines;
2293+ } rfbi;
2294+
2295+ struct {
2296+ u8 datapairs;
2297+ } sdi;
2298+
2299+ struct {
2300+ u8 clk_lane;
2301+ u8 clk_pol;
2302+ u8 data1_lane;
2303+ u8 data1_pol;
2304+ u8 data2_lane;
2305+ u8 data2_pol;
2306+
2307+ struct {
2308+ u16 regn;
2309+ u16 regm;
2310+ u16 regm3;
2311+ u16 regm4;
2312+
2313+ u16 lp_clk_div;
2314+
2315+ u16 lck_div;
2316+ u16 pck_div;
2317+ } div;
2318+
2319+ bool ext_te;
2320+ u8 ext_te_gpio;
2321+ } dsi;
2322+
2323+ struct {
2324+ enum omap_dss_venc_type type;
2325+ bool invert_polarity;
2326+ } venc;
2327+ } phy;
2328+
2329+ struct {
2330+ struct omap_video_timings timings;
2331+
2332+ int acbi; /* ac-bias pin transitions per interrupt */
2333+ /* Unit: line clocks */
2334+ int acb; /* ac-bias pin frequency */
2335+
2336+ enum omap_panel_config config;
2337+
2338+ u8 recommended_bpp;
2339+
2340+ struct omap_dss_device *ctrl;
2341+ } panel;
2342+
2343+ struct {
2344+ u8 pixel_size;
2345+ struct rfbi_timings rfbi_timings;
2346+ struct omap_dss_device *panel;
2347+ } ctrl;
2348+
2349+ int reset_gpio;
2350+
2351+ int max_backlight_level;
2352+
2353+ const char *name;
2354+
2355+ /* used to match device to driver */
2356+ const char *driver_name;
2357+
2358+ void *data;
2359+
2360+ struct omap_dss_driver *driver;
2361+
2362+ /* helper variable for driver suspend/resume */
2363+ bool activate_after_resume;
2364+
2365+ enum omap_display_caps caps;
2366+
2367+ struct omap_overlay_manager *manager;
2368+
2369+ enum omap_dss_display_state state;
2370+
2371+ int (*enable)(struct omap_dss_device *dssdev);
2372+ void (*disable)(struct omap_dss_device *dssdev);
2373+
2374+ int (*suspend)(struct omap_dss_device *dssdev);
2375+ int (*resume)(struct omap_dss_device *dssdev);
2376+
2377+ void (*get_resolution)(struct omap_dss_device *dssdev,
2378+ u16 *xres, u16 *yres);
2379+ int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2380+
2381+ int (*check_timings)(struct omap_dss_device *dssdev,
2382+ struct omap_video_timings *timings);
2383+ void (*set_timings)(struct omap_dss_device *dssdev,
2384+ struct omap_video_timings *timings);
2385+ void (*get_timings)(struct omap_dss_device *dssdev,
2386+ struct omap_video_timings *timings);
2387+ int (*update)(struct omap_dss_device *dssdev,
2388+ u16 x, u16 y, u16 w, u16 h);
2389+ int (*sync)(struct omap_dss_device *dssdev);
2390+ int (*wait_vsync)(struct omap_dss_device *dssdev);
2391+
2392+ int (*set_update_mode)(struct omap_dss_device *dssdev,
2393+ enum omap_dss_update_mode);
2394+ enum omap_dss_update_mode (*get_update_mode)
2395+ (struct omap_dss_device *dssdev);
2396+
2397+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2398+ int (*get_te)(struct omap_dss_device *dssdev);
2399+
2400+ u8 (*get_rotate)(struct omap_dss_device *dssdev);
2401+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2402+
2403+ bool (*get_mirror)(struct omap_dss_device *dssdev);
2404+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2405+
2406+ int (*run_test)(struct omap_dss_device *dssdev, int test);
2407+ int (*memory_read)(struct omap_dss_device *dssdev,
2408+ void *buf, size_t size,
2409+ u16 x, u16 y, u16 w, u16 h);
2410+
2411+ int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2412+ u32 (*get_wss)(struct omap_dss_device *dssdev);
2413+
2414+ /* platform specific */
2415+ int (*platform_enable)(struct omap_dss_device *dssdev);
2416+ void (*platform_disable)(struct omap_dss_device *dssdev);
2417+ int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2418+ int (*get_backlight)(struct omap_dss_device *dssdev);
2419+};
2420+
2421+struct omap_dss_driver {
2422+ struct device_driver driver;
2423+
2424+ int (*probe)(struct omap_dss_device *);
2425+ void (*remove)(struct omap_dss_device *);
2426+
2427+ int (*enable)(struct omap_dss_device *display);
2428+ void (*disable)(struct omap_dss_device *display);
2429+ int (*suspend)(struct omap_dss_device *display);
2430+ int (*resume)(struct omap_dss_device *display);
2431+ int (*run_test)(struct omap_dss_device *display, int test);
2432+
2433+ void (*setup_update)(struct omap_dss_device *dssdev,
2434+ u16 x, u16 y, u16 w, u16 h);
2435+
2436+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2437+ int (*wait_for_te)(struct omap_dss_device *dssdev);
2438+
2439+ u8 (*get_rotate)(struct omap_dss_device *dssdev);
2440+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2441+
2442+ bool (*get_mirror)(struct omap_dss_device *dssdev);
2443+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2444+
2445+ int (*memory_read)(struct omap_dss_device *dssdev,
2446+ void *buf, size_t size,
2447+ u16 x, u16 y, u16 w, u16 h);
2448+};
2449+
2450+int omap_dss_register_driver(struct omap_dss_driver *);
2451+void omap_dss_unregister_driver(struct omap_dss_driver *);
2452+
2453+int omap_dss_register_device(struct omap_dss_device *);
2454+void omap_dss_unregister_device(struct omap_dss_device *);
2455+
2456+void omap_dss_get_device(struct omap_dss_device *dssdev);
2457+void omap_dss_put_device(struct omap_dss_device *dssdev);
2458+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2459+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2460+struct omap_dss_device *omap_dss_find_device(void *data,
2461+ int (*match)(struct omap_dss_device *dssdev, void *data));
2462+
2463+int omap_dss_start_device(struct omap_dss_device *dssdev);
2464+void omap_dss_stop_device(struct omap_dss_device *dssdev);
2465+
2466+int omap_dss_get_num_overlay_managers(void);
2467+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2468+
2469+int omap_dss_get_num_overlays(void);
2470+struct omap_overlay *omap_dss_get_overlay(int num);
2471+
2472+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2473+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2474+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2475+
2476+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2477+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2478+ unsigned long timeout);
2479+
2480+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2481+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2482+
2483+#endif
2484Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dma.h
2485===================================================================
2486--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2487@@ -0,0 +1,640 @@
2488+/*
2489+ * arch/arm/plat-omap/include/mach/dma.h
2490+ *
2491+ * Copyright (C) 2003 Nokia Corporation
2492+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2493+ *
2494+ * This program is free software; you can redistribute it and/or modify
2495+ * it under the terms of the GNU General Public License as published by
2496+ * the Free Software Foundation; either version 2 of the License, or
2497+ * (at your option) any later version.
2498+ *
2499+ * This program is distributed in the hope that it will be useful,
2500+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2501+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2502+ * GNU General Public License for more details.
2503+ *
2504+ * You should have received a copy of the GNU General Public License
2505+ * along with this program; if not, write to the Free Software
2506+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2507+ */
2508+#ifndef __ASM_ARCH_DMA_H
2509+#define __ASM_ARCH_DMA_H
2510+
2511+/* Hardware registers for omap1 */
2512+#define OMAP1_DMA_BASE (0xfffed800)
2513+
2514+#define OMAP1_DMA_GCR 0x400
2515+#define OMAP1_DMA_GSCR 0x404
2516+#define OMAP1_DMA_GRST 0x408
2517+#define OMAP1_DMA_HW_ID 0x442
2518+#define OMAP1_DMA_PCH2_ID 0x444
2519+#define OMAP1_DMA_PCH0_ID 0x446
2520+#define OMAP1_DMA_PCH1_ID 0x448
2521+#define OMAP1_DMA_PCHG_ID 0x44a
2522+#define OMAP1_DMA_PCHD_ID 0x44c
2523+#define OMAP1_DMA_CAPS_0_U 0x44e
2524+#define OMAP1_DMA_CAPS_0_L 0x450
2525+#define OMAP1_DMA_CAPS_1_U 0x452
2526+#define OMAP1_DMA_CAPS_1_L 0x454
2527+#define OMAP1_DMA_CAPS_2 0x456
2528+#define OMAP1_DMA_CAPS_3 0x458
2529+#define OMAP1_DMA_CAPS_4 0x45a
2530+#define OMAP1_DMA_PCH2_SR 0x460
2531+#define OMAP1_DMA_PCH0_SR 0x480
2532+#define OMAP1_DMA_PCH1_SR 0x482
2533+#define OMAP1_DMA_PCHD_SR 0x4c0
2534+
2535+/* Hardware registers for omap2 and omap3 */
2536+#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2537+#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2538+#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2539+
2540+#define OMAP_DMA4_REVISION 0x00
2541+#define OMAP_DMA4_GCR 0x78
2542+#define OMAP_DMA4_IRQSTATUS_L0 0x08
2543+#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2544+#define OMAP_DMA4_IRQSTATUS_L2 0x10
2545+#define OMAP_DMA4_IRQSTATUS_L3 0x14
2546+#define OMAP_DMA4_IRQENABLE_L0 0x18
2547+#define OMAP_DMA4_IRQENABLE_L1 0x1c
2548+#define OMAP_DMA4_IRQENABLE_L2 0x20
2549+#define OMAP_DMA4_IRQENABLE_L3 0x24
2550+#define OMAP_DMA4_SYSSTATUS 0x28
2551+#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2552+#define OMAP_DMA4_CAPS_0 0x64
2553+#define OMAP_DMA4_CAPS_2 0x6c
2554+#define OMAP_DMA4_CAPS_3 0x70
2555+#define OMAP_DMA4_CAPS_4 0x74
2556+
2557+#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2558+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2559+
2560+/* Common channel specific registers for omap1 */
2561+#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2562+#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2563+#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2564+#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2565+#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2566+#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2567+#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2568+#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2569+#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2570+#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2571+#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2572+#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2573+#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2574+#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2575+#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2576+
2577+/* Common channel specific registers for omap2 */
2578+#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2579+#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2580+#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2581+#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2582+#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2583+#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2584+#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2585+#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2586+#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2587+#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2588+#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2589+#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2590+#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2591+#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2592+
2593+/* Channel specific registers only on omap1 */
2594+#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2595+#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2596+#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2597+#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2598+#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2599+#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2600+#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2601+#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2602+#define OMAP1_DMA_CCEN(n) 0
2603+#define OMAP1_DMA_CCFN(n) 0
2604+
2605+/* Channel specific registers only on omap2 */
2606+#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2607+#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2608+#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2609+#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2610+#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2611+
2612+/* Additional registers available on OMAP4 */
2613+#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2614+#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2615+#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2616+
2617+/* Dummy defines to keep multi-omap compiles happy */
2618+#define OMAP1_DMA_REVISION 0
2619+#define OMAP1_DMA_IRQSTATUS_L0 0
2620+#define OMAP1_DMA_IRQENABLE_L0 0
2621+#define OMAP1_DMA_OCP_SYSCONFIG 0
2622+#define OMAP_DMA4_HW_ID 0
2623+#define OMAP_DMA4_CAPS_0_L 0
2624+#define OMAP_DMA4_CAPS_0_U 0
2625+#define OMAP_DMA4_CAPS_1_L 0
2626+#define OMAP_DMA4_CAPS_1_U 0
2627+#define OMAP_DMA4_GSCR 0
2628+#define OMAP_DMA4_CPC(n) 0
2629+
2630+#define OMAP_DMA4_LCH_CTRL(n) 0
2631+#define OMAP_DMA4_COLOR_L(n) 0
2632+#define OMAP_DMA4_COLOR_U(n) 0
2633+#define OMAP_DMA4_CCR2(n) 0
2634+#define OMAP1_DMA_CSSA(n) 0
2635+#define OMAP1_DMA_CDSA(n) 0
2636+#define OMAP_DMA4_CSSA_L(n) 0
2637+#define OMAP_DMA4_CSSA_U(n) 0
2638+#define OMAP_DMA4_CDSA_L(n) 0
2639+#define OMAP_DMA4_CDSA_U(n) 0
2640+#define OMAP1_DMA_COLOR(n) 0
2641+
2642+/*----------------------------------------------------------------------------*/
2643+
2644+/* DMA channels for omap1 */
2645+#define OMAP_DMA_NO_DEVICE 0
2646+#define OMAP_DMA_MCSI1_TX 1
2647+#define OMAP_DMA_MCSI1_RX 2
2648+#define OMAP_DMA_I2C_RX 3
2649+#define OMAP_DMA_I2C_TX 4
2650+#define OMAP_DMA_EXT_NDMA_REQ 5
2651+#define OMAP_DMA_EXT_NDMA_REQ2 6
2652+#define OMAP_DMA_UWIRE_TX 7
2653+#define OMAP_DMA_MCBSP1_TX 8
2654+#define OMAP_DMA_MCBSP1_RX 9
2655+#define OMAP_DMA_MCBSP3_TX 10
2656+#define OMAP_DMA_MCBSP3_RX 11
2657+#define OMAP_DMA_UART1_TX 12
2658+#define OMAP_DMA_UART1_RX 13
2659+#define OMAP_DMA_UART2_TX 14
2660+#define OMAP_DMA_UART2_RX 15
2661+#define OMAP_DMA_MCBSP2_TX 16
2662+#define OMAP_DMA_MCBSP2_RX 17
2663+#define OMAP_DMA_UART3_TX 18
2664+#define OMAP_DMA_UART3_RX 19
2665+#define OMAP_DMA_CAMERA_IF_RX 20
2666+#define OMAP_DMA_MMC_TX 21
2667+#define OMAP_DMA_MMC_RX 22
2668+#define OMAP_DMA_NAND 23
2669+#define OMAP_DMA_IRQ_LCD_LINE 24
2670+#define OMAP_DMA_MEMORY_STICK 25
2671+#define OMAP_DMA_USB_W2FC_RX0 26
2672+#define OMAP_DMA_USB_W2FC_RX1 27
2673+#define OMAP_DMA_USB_W2FC_RX2 28
2674+#define OMAP_DMA_USB_W2FC_TX0 29
2675+#define OMAP_DMA_USB_W2FC_TX1 30
2676+#define OMAP_DMA_USB_W2FC_TX2 31
2677+
2678+/* These are only for 1610 */
2679+#define OMAP_DMA_CRYPTO_DES_IN 32
2680+#define OMAP_DMA_SPI_TX 33
2681+#define OMAP_DMA_SPI_RX 34
2682+#define OMAP_DMA_CRYPTO_HASH 35
2683+#define OMAP_DMA_CCP_ATTN 36
2684+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2685+#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2686+#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2687+#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2688+#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2689+#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2690+#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2691+#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2692+#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2693+#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2694+#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2695+#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2696+#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2697+#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2698+#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2699+#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2700+#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2701+#define OMAP_DMA_MMC2_TX 54
2702+#define OMAP_DMA_MMC2_RX 55
2703+#define OMAP_DMA_CRYPTO_DES_OUT 56
2704+
2705+/* DMA channels for 24xx */
2706+#define OMAP24XX_DMA_NO_DEVICE 0
2707+#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2708+#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2709+#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2710+#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2711+#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2712+#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2713+#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2714+#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2715+#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2716+#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2717+#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2718+#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2719+#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2720+#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2721+#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2722+#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2723+#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2724+#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2725+#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2726+#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2727+#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2728+#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2729+#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2730+#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2731+#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2732+#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2733+#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2734+#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2735+#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2736+#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2737+#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2738+#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2739+#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2740+#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2741+#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2742+#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2743+#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2744+#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2745+#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2746+#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2747+#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2748+#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2749+#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2750+#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2751+#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2752+#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2753+#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2754+#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2755+#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2756+#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2757+#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2758+#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2759+#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2760+#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2761+#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2762+#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2763+#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2764+#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2765+#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2766+#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2767+#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2768+#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2769+#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2770+#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2771+#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2772+#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2773+#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2774+#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2775+#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2776+#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2777+#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2778+#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2779+#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2780+#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2781+#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2782+#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2783+#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2784+#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2785+#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2786+#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2787+#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2788+#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2789+#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2790+#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2791+#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2792+#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2793+#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2794+#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2795+#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2796+#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2797+#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2798+#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2799+#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2800+#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2801+#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2802+#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2803+#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2804+#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2805+
2806+/* DMA request lines for 44xx */
2807+#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2808+#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2809+#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2810+#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2811+#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2812+#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2813+#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2814+#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2815+#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2816+#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2817+#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2818+#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2819+#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2820+#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2821+#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2822+#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2823+#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2824+#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2825+#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2826+#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2827+#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2828+#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2829+#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2830+#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2831+#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2832+#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2833+#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2834+#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2835+#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2836+#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2837+#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2838+#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2839+#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2840+#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2841+#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2842+#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2843+#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2844+#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2845+#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2846+#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2847+#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2848+#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2849+#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2850+#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2851+#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2852+#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2853+#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2854+#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2855+#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2856+#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2857+#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2858+#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2859+#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2860+#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2861+#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2862+#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2863+#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2864+#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2865+#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2866+#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2867+#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2868+#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2869+#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2870+#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2871+#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2872+#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2873+#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2874+#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2875+#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2876+#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2877+#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2878+#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2879+#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2880+#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2881+#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2882+#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2883+#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2884+#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2885+#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2886+#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2887+#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2888+
2889+/*----------------------------------------------------------------------------*/
2890+
2891+#define OMAP1_DMA_TOUT_IRQ (1 << 0)
2892+#define OMAP_DMA_DROP_IRQ (1 << 1)
2893+#define OMAP_DMA_HALF_IRQ (1 << 2)
2894+#define OMAP_DMA_FRAME_IRQ (1 << 3)
2895+#define OMAP_DMA_LAST_IRQ (1 << 4)
2896+#define OMAP_DMA_BLOCK_IRQ (1 << 5)
2897+#define OMAP1_DMA_SYNC_IRQ (1 << 6)
2898+#define OMAP2_DMA_PKT_IRQ (1 << 7)
2899+#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
2900+#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
2901+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
2902+#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
2903+
2904+#define OMAP_DMA_CCR_EN (1 << 7)
2905+
2906+#define OMAP_DMA_DATA_TYPE_S8 0x00
2907+#define OMAP_DMA_DATA_TYPE_S16 0x01
2908+#define OMAP_DMA_DATA_TYPE_S32 0x02
2909+
2910+#define OMAP_DMA_SYNC_ELEMENT 0x00
2911+#define OMAP_DMA_SYNC_FRAME 0x01
2912+#define OMAP_DMA_SYNC_BLOCK 0x02
2913+#define OMAP_DMA_SYNC_PACKET 0x03
2914+
2915+#define OMAP_DMA_SRC_SYNC 0x01
2916+#define OMAP_DMA_DST_SYNC 0x00
2917+
2918+#define OMAP_DMA_PORT_EMIFF 0x00
2919+#define OMAP_DMA_PORT_EMIFS 0x01
2920+#define OMAP_DMA_PORT_OCP_T1 0x02
2921+#define OMAP_DMA_PORT_TIPB 0x03
2922+#define OMAP_DMA_PORT_OCP_T2 0x04
2923+#define OMAP_DMA_PORT_MPUI 0x05
2924+
2925+#define OMAP_DMA_AMODE_CONSTANT 0x00
2926+#define OMAP_DMA_AMODE_POST_INC 0x01
2927+#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
2928+#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
2929+
2930+#define DMA_DEFAULT_FIFO_DEPTH 0x10
2931+#define DMA_DEFAULT_ARB_RATE 0x01
2932+/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
2933+#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
2934+#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
2935+#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
2936+#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
2937+#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
2938+#define DMA_THREAD_FIFO_75 (0x01 << 14)
2939+#define DMA_THREAD_FIFO_25 (0x02 << 14)
2940+#define DMA_THREAD_FIFO_50 (0x03 << 14)
2941+
2942+/* DMA4_OCP_SYSCONFIG bits */
2943+#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
2944+#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
2945+#define DMA_SYSCONFIG_EMUFREE (1 << 5)
2946+#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
2947+#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
2948+#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
2949+
2950+#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
2951+#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
2952+
2953+#define DMA_IDLEMODE_SMARTIDLE 0x2
2954+#define DMA_IDLEMODE_NO_IDLE 0x1
2955+#define DMA_IDLEMODE_FORCE_IDLE 0x0
2956+
2957+/* Chaining modes*/
2958+#ifndef CONFIG_ARCH_OMAP1
2959+#define OMAP_DMA_STATIC_CHAIN 0x1
2960+#define OMAP_DMA_DYNAMIC_CHAIN 0x2
2961+#define OMAP_DMA_CHAIN_ACTIVE 0x1
2962+#define OMAP_DMA_CHAIN_INACTIVE 0x0
2963+#endif
2964+
2965+#define DMA_CH_PRIO_HIGH 0x1
2966+#define DMA_CH_PRIO_LOW 0x0 /* Def */
2967+
2968+enum omap_dma_burst_mode {
2969+ OMAP_DMA_DATA_BURST_DIS = 0,
2970+ OMAP_DMA_DATA_BURST_4,
2971+ OMAP_DMA_DATA_BURST_8,
2972+ OMAP_DMA_DATA_BURST_16,
2973+};
2974+
2975+enum end_type {
2976+ OMAP_DMA_LITTLE_ENDIAN = 0,
2977+ OMAP_DMA_BIG_ENDIAN
2978+};
2979+
2980+enum omap_dma_color_mode {
2981+ OMAP_DMA_COLOR_DIS = 0,
2982+ OMAP_DMA_CONSTANT_FILL,
2983+ OMAP_DMA_TRANSPARENT_COPY
2984+};
2985+
2986+enum omap_dma_write_mode {
2987+ OMAP_DMA_WRITE_NON_POSTED = 0,
2988+ OMAP_DMA_WRITE_POSTED,
2989+ OMAP_DMA_WRITE_LAST_NON_POSTED
2990+};
2991+
2992+enum omap_dma_channel_mode {
2993+ OMAP_DMA_LCH_2D = 0,
2994+ OMAP_DMA_LCH_G,
2995+ OMAP_DMA_LCH_P,
2996+ OMAP_DMA_LCH_PD
2997+};
2998+
2999+struct omap_dma_channel_params {
3000+ int data_type; /* data type 8,16,32 */
3001+ int elem_count; /* number of elements in a frame */
3002+ int frame_count; /* number of frames in a element */
3003+
3004+ int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3005+ int src_amode; /* constant, post increment, indexed,
3006+ double indexed */
3007+ unsigned long src_start; /* source address : physical */
3008+ int src_ei; /* source element index */
3009+ int src_fi; /* source frame index */
3010+
3011+ int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3012+ int dst_amode; /* constant, post increment, indexed,
3013+ double indexed */
3014+ unsigned long dst_start; /* source address : physical */
3015+ int dst_ei; /* source element index */
3016+ int dst_fi; /* source frame index */
3017+
3018+ int trigger; /* trigger attached if the channel is
3019+ synchronized */
3020+ int sync_mode; /* sycn on element, frame , block or packet */
3021+ int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3022+
3023+ int ie; /* interrupt enabled */
3024+
3025+ unsigned char read_prio;/* read priority */
3026+ unsigned char write_prio;/* write priority */
3027+
3028+#ifndef CONFIG_ARCH_OMAP1
3029+ enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3030+#endif
3031+};
3032+
3033+
3034+extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3035+extern int omap_request_dma(int dev_id, const char *dev_name,
3036+ void (*callback)(int lch, u16 ch_status, void *data),
3037+ void *data, int *dma_ch);
3038+extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3039+extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3040+extern void omap_free_dma(int ch);
3041+extern void omap_start_dma(int lch);
3042+extern void omap_stop_dma(int lch);
3043+extern void omap_set_dma_transfer_params(int lch, int data_type,
3044+ int elem_count, int frame_count,
3045+ int sync_mode,
3046+ int dma_trigger, int src_or_dst_synch);
3047+extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3048+ u32 color);
3049+extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3050+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3051+
3052+extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3053+ unsigned long src_start,
3054+ int src_ei, int src_fi);
3055+extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3056+extern void omap_set_dma_src_data_pack(int lch, int enable);
3057+extern void omap_set_dma_src_burst_mode(int lch,
3058+ enum omap_dma_burst_mode burst_mode);
3059+
3060+extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3061+ unsigned long dest_start,
3062+ int dst_ei, int dst_fi);
3063+extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3064+extern void omap_set_dma_dest_data_pack(int lch, int enable);
3065+extern void omap_set_dma_dest_burst_mode(int lch,
3066+ enum omap_dma_burst_mode burst_mode);
3067+
3068+extern void omap_set_dma_params(int lch,
3069+ struct omap_dma_channel_params *params);
3070+
3071+extern void omap_dma_link_lch(int lch_head, int lch_queue);
3072+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3073+
3074+extern int omap_set_dma_callback(int lch,
3075+ void (*callback)(int lch, u16 ch_status, void *data),
3076+ void *data);
3077+extern dma_addr_t omap_get_dma_src_pos(int lch);
3078+extern dma_addr_t omap_get_dma_dst_pos(int lch);
3079+extern void omap_clear_dma(int lch);
3080+extern int omap_get_dma_active_status(int lch);
3081+extern int omap_dma_running(void);
3082+extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3083+ int tparams);
3084+extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3085+ unsigned char write_prio);
3086+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3087+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3088+extern int omap_get_dma_index(int lch, int *ei, int *fi);
3089+
3090+void omap_dma_global_context_save(void);
3091+void omap_dma_global_context_restore(void);
3092+
3093+extern void omap_dma_disable_irq(int lch);
3094+
3095+/* Chaining APIs */
3096+#ifndef CONFIG_ARCH_OMAP1
3097+extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3098+ void (*callback) (int lch, u16 ch_status,
3099+ void *data),
3100+ int *chain_id, int no_of_chans,
3101+ int chain_mode,
3102+ struct omap_dma_channel_params params);
3103+extern int omap_free_dma_chain(int chain_id);
3104+extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3105+ int dest_start, int elem_count,
3106+ int frame_count, void *callbk_data);
3107+extern int omap_start_dma_chain_transfers(int chain_id);
3108+extern int omap_stop_dma_chain_transfers(int chain_id);
3109+extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3110+extern int omap_get_dma_chain_dst_pos(int chain_id);
3111+extern int omap_get_dma_chain_src_pos(int chain_id);
3112+
3113+extern int omap_modify_dma_chain_params(int chain_id,
3114+ struct omap_dma_channel_params params);
3115+extern int omap_dma_chain_status(int chain_id);
3116+#endif
3117+
3118+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3119+#include <mach/lcd_dma.h>
3120+#else
3121+static inline int omap_lcd_dma_running(void)
3122+{
3123+ return 0;
3124+}
3125+#endif
3126+
3127+#endif /* __ASM_ARCH_DMA_H */
3128Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dmtimer.h
3129===================================================================
3130--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3131@@ -0,0 +1,84 @@
3132+/*
3133+ * arch/arm/plat-omap/include/mach/dmtimer.h
3134+ *
3135+ * OMAP Dual-Mode Timers
3136+ *
3137+ * Copyright (C) 2005 Nokia Corporation
3138+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3139+ * PWM and clock framwork support by Timo Teras.
3140+ *
3141+ * This program is free software; you can redistribute it and/or modify it
3142+ * under the terms of the GNU General Public License as published by the
3143+ * Free Software Foundation; either version 2 of the License, or (at your
3144+ * option) any later version.
3145+ *
3146+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3147+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3148+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3149+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3150+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3151+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3152+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3153+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3154+ *
3155+ * You should have received a copy of the GNU General Public License along
3156+ * with this program; if not, write to the Free Software Foundation, Inc.,
3157+ * 675 Mass Ave, Cambridge, MA 02139, USA.
3158+ */
3159+
3160+#ifndef __ASM_ARCH_DMTIMER_H
3161+#define __ASM_ARCH_DMTIMER_H
3162+
3163+/* clock sources */
3164+#define OMAP_TIMER_SRC_SYS_CLK 0x00
3165+#define OMAP_TIMER_SRC_32_KHZ 0x01
3166+#define OMAP_TIMER_SRC_EXT_CLK 0x02
3167+
3168+/* timer interrupt enable bits */
3169+#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3170+#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3171+#define OMAP_TIMER_INT_MATCH (1 << 0)
3172+
3173+/* trigger types */
3174+#define OMAP_TIMER_TRIGGER_NONE 0x00
3175+#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3176+#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3177+
3178+struct omap_dm_timer;
3179+struct clk;
3180+
3181+int omap_dm_timer_init(void);
3182+
3183+struct omap_dm_timer *omap_dm_timer_request(void);
3184+struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3185+void omap_dm_timer_free(struct omap_dm_timer *timer);
3186+void omap_dm_timer_enable(struct omap_dm_timer *timer);
3187+void omap_dm_timer_disable(struct omap_dm_timer *timer);
3188+
3189+int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3190+
3191+u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3192+struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3193+
3194+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3195+void omap_dm_timer_start(struct omap_dm_timer *timer);
3196+void omap_dm_timer_stop(struct omap_dm_timer *timer);
3197+
3198+int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3199+void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3200+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3201+void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3202+void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3203+void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3204+
3205+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3206+
3207+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3208+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3209+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3210+void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3211+
3212+int omap_dm_timers_active(void);
3213+
3214+
3215+#endif /* __ASM_ARCH_DMTIMER_H */
3216Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dsp_common.h
3217===================================================================
3218--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3219@@ -0,0 +1,40 @@
3220+/*
3221+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3222+ *
3223+ * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3224+ *
3225+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3226+ *
3227+ * This program is free software; you can redistribute it and/or
3228+ * modify it under the terms of the GNU General Public License
3229+ * version 2 as published by the Free Software Foundation.
3230+ *
3231+ * This program is distributed in the hope that it will be useful, but
3232+ * WITHOUT ANY WARRANTY; without even the implied warranty of
3233+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3234+ * General Public License for more details.
3235+ *
3236+ * You should have received a copy of the GNU General Public License
3237+ * along with this program; if not, write to the Free Software
3238+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3239+ * 02110-1301 USA
3240+ *
3241+ */
3242+
3243+#ifndef ASM_ARCH_DSP_COMMON_H
3244+#define ASM_ARCH_DSP_COMMON_H
3245+
3246+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3247+extern void omap_dsp_request_mpui(void);
3248+extern void omap_dsp_release_mpui(void);
3249+extern int omap_dsp_request_mem(void);
3250+extern int omap_dsp_release_mem(void);
3251+#else
3252+static inline int omap_dsp_request_mem(void)
3253+{
3254+ return 0;
3255+}
3256+#define omap_dsp_release_mem() do {} while (0)
3257+#endif
3258+
3259+#endif /* ASM_ARCH_DSP_COMMON_H */
3260Index: linux-2.6.35/arch/arm/plat-omap/include/mach/fpga.h
3261===================================================================
3262--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3263@@ -0,0 +1,197 @@
3264+/*
3265+ * arch/arm/plat-omap/include/mach/fpga.h
3266+ *
3267+ * Interrupt handler for OMAP-1510 FPGA
3268+ *
3269+ * Copyright (C) 2001 RidgeRun, Inc.
3270+ * Author: Greg Lonnon <glonnon@ridgerun.com>
3271+ *
3272+ * Copyright (C) 2002 MontaVista Software, Inc.
3273+ *
3274+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3275+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3276+ *
3277+ * This program is free software; you can redistribute it and/or modify
3278+ * it under the terms of the GNU General Public License version 2 as
3279+ * published by the Free Software Foundation.
3280+ */
3281+
3282+#ifndef __ASM_ARCH_OMAP_FPGA_H
3283+#define __ASM_ARCH_OMAP_FPGA_H
3284+
3285+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3286+extern void omap1510_fpga_init_irq(void);
3287+#else
3288+#define omap1510_fpga_init_irq() (0)
3289+#endif
3290+
3291+#define fpga_read(reg) __raw_readb(reg)
3292+#define fpga_write(val, reg) __raw_writeb(val, reg)
3293+
3294+/*
3295+ * ---------------------------------------------------------------------------
3296+ * H2/P2 Debug board FPGA
3297+ * ---------------------------------------------------------------------------
3298+ */
3299+/* maps in the FPGA registers and the ETHR registers */
3300+#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3301+#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3302+#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3303+
3304+#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3305+#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3306+#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3307+#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3308+#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3309+#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3310+#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3311+#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3312+
3313+/* NOTE: most boards don't have a static mapping for the FPGA ... */
3314+struct h2p2_dbg_fpga {
3315+ /* offset 0x00 */
3316+ u16 smc91x[8];
3317+ /* offset 0x10 */
3318+ u16 fpga_rev;
3319+ u16 board_rev;
3320+ u16 gpio_outputs;
3321+ u16 leds;
3322+ /* offset 0x18 */
3323+ u16 misc_inputs;
3324+ u16 lan_status;
3325+ u16 lan_reset;
3326+ u16 reserved0;
3327+ /* offset 0x20 */
3328+ u16 ps2_data;
3329+ u16 ps2_ctrl;
3330+ /* plus also 4 rs232 ports ... */
3331+};
3332+
3333+/* LEDs definition on debug board (16 LEDs, all physically green) */
3334+#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3335+#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3336+#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3337+#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3338+/* cpu0 load-meter LEDs */
3339+#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3340+#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3341+#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3342+
3343+#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3344+#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3345+
3346+/*
3347+ * ---------------------------------------------------------------------------
3348+ * OMAP-1510 FPGA
3349+ * ---------------------------------------------------------------------------
3350+ */
3351+#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3352+#define OMAP1510_FPGA_SIZE SZ_4K
3353+#define OMAP1510_FPGA_START 0x08000000 /* PA */
3354+
3355+/* Revision */
3356+#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3357+#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3358+
3359+#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3360+#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3361+#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3362+#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3363+
3364+/* Interrupt status */
3365+#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3366+#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3367+
3368+/* Interrupt mask */
3369+#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3370+#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3371+
3372+/* Reset registers */
3373+#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3374+#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3375+
3376+#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3377+#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3378+#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3379+#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3380+#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3381+#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3382+#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3383+#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3384+#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3385+#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3386+
3387+#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3388+
3389+#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3390+#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3391+#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3392+#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3393+#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3394+#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3395+#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3396+#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3397+#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3398+#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3399+#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3400+
3401+#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3402+
3403+/*
3404+ * Power up Giga UART driver, turn on HID clock.
3405+ * Turn off BT power, since we're not using it and it
3406+ * draws power.
3407+ */
3408+#define OMAP1510_FPGA_RESET_VALUE 0x42
3409+
3410+#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3411+#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3412+#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3413+#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3414+#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3415+#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3416+#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3417+#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3418+
3419+/*
3420+ * Innovator/OMAP1510 FPGA HID register bit definitions
3421+ */
3422+#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3423+#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3424+#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3425+#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3426+#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3427+#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3428+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3429+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3430+
3431+/* The FPGA IRQ is cascaded through GPIO_13 */
3432+#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3433+
3434+/* IRQ Numbers for interrupts muxed through the FPGA */
3435+#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3436+#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3437+#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3438+#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3439+#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3440+#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3441+#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3442+#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3443+#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3444+#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3445+#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3446+#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3447+#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3448+#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3449+#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3450+#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3451+#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3452+#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3453+#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3454+#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3455+#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3456+#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3457+#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3458+#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3459+
3460+#endif
3461Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio.h
3462===================================================================
3463--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3464@@ -0,0 +1,129 @@
3465+/*
3466+ * arch/arm/plat-omap/include/mach/gpio.h
3467+ *
3468+ * OMAP GPIO handling defines and functions
3469+ *
3470+ * Copyright (C) 2003-2005 Nokia Corporation
3471+ *
3472+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3473+ *
3474+ * This program is free software; you can redistribute it and/or modify
3475+ * it under the terms of the GNU General Public License as published by
3476+ * the Free Software Foundation; either version 2 of the License, or
3477+ * (at your option) any later version.
3478+ *
3479+ * This program is distributed in the hope that it will be useful,
3480+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3481+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3482+ * GNU General Public License for more details.
3483+ *
3484+ * You should have received a copy of the GNU General Public License
3485+ * along with this program; if not, write to the Free Software
3486+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3487+ *
3488+ */
3489+
3490+#ifndef __ASM_ARCH_OMAP_GPIO_H
3491+#define __ASM_ARCH_OMAP_GPIO_H
3492+
3493+#include <linux/io.h>
3494+#include <mach/irqs.h>
3495+
3496+#define OMAP1_MPUIO_BASE 0xfffb5000
3497+
3498+#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3499+
3500+#define OMAP_MPUIO_INPUT_LATCH 0x00
3501+#define OMAP_MPUIO_OUTPUT 0x02
3502+#define OMAP_MPUIO_IO_CNTL 0x04
3503+#define OMAP_MPUIO_KBR_LATCH 0x08
3504+#define OMAP_MPUIO_KBC 0x0a
3505+#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3506+#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3507+#define OMAP_MPUIO_KBD_INT 0x10
3508+#define OMAP_MPUIO_GPIO_INT 0x12
3509+#define OMAP_MPUIO_KBD_MASKIT 0x14
3510+#define OMAP_MPUIO_GPIO_MASKIT 0x16
3511+#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3512+#define OMAP_MPUIO_LATCH 0x1a
3513+#else
3514+#define OMAP_MPUIO_INPUT_LATCH 0x00
3515+#define OMAP_MPUIO_OUTPUT 0x04
3516+#define OMAP_MPUIO_IO_CNTL 0x08
3517+#define OMAP_MPUIO_KBR_LATCH 0x10
3518+#define OMAP_MPUIO_KBC 0x14
3519+#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3520+#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3521+#define OMAP_MPUIO_KBD_INT 0x20
3522+#define OMAP_MPUIO_GPIO_INT 0x24
3523+#define OMAP_MPUIO_KBD_MASKIT 0x28
3524+#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3525+#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3526+#define OMAP_MPUIO_LATCH 0x34
3527+#endif
3528+
3529+#define OMAP34XX_NR_GPIOS 6
3530+
3531+#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3532+#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3533+
3534+#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3535+ IH_MPUIO_BASE + ((nr) & 0x0f) : \
3536+ IH_GPIO_BASE + (nr))
3537+
3538+extern int omap_gpio_init(void); /* Call from board init only */
3539+extern void omap2_gpio_prepare_for_retention(void);
3540+extern void omap2_gpio_resume_after_retention(void);
3541+extern void omap_set_gpio_debounce(int gpio, int enable);
3542+extern void omap_set_gpio_debounce_time(int gpio, int enable);
3543+extern void omap_gpio_save_context(void);
3544+extern void omap_gpio_restore_context(void);
3545+/*-------------------------------------------------------------------------*/
3546+
3547+/* Wrappers for "new style" GPIO calls, using the new infrastructure
3548+ * which lets us plug in FPGA, I2C, and other implementations.
3549+ * *
3550+ * The original OMAP-specfic calls should eventually be removed.
3551+ */
3552+
3553+#include <linux/errno.h>
3554+#include <asm-generic/gpio.h>
3555+
3556+static inline int gpio_get_value(unsigned gpio)
3557+{
3558+ return __gpio_get_value(gpio);
3559+}
3560+
3561+static inline void gpio_set_value(unsigned gpio, int value)
3562+{
3563+ __gpio_set_value(gpio, value);
3564+}
3565+
3566+static inline int gpio_cansleep(unsigned gpio)
3567+{
3568+ return __gpio_cansleep(gpio);
3569+}
3570+
3571+static inline int gpio_to_irq(unsigned gpio)
3572+{
3573+ return __gpio_to_irq(gpio);
3574+}
3575+
3576+static inline int irq_to_gpio(unsigned irq)
3577+{
3578+ int tmp;
3579+
3580+ /* omap1 SOC mpuio */
3581+ if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3582+ return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3583+
3584+ /* SOC gpio */
3585+ tmp = irq - IH_GPIO_BASE;
3586+ if (tmp < OMAP_MAX_GPIO_LINES)
3587+ return tmp;
3588+
3589+ /* we don't supply reverse mappings for non-SOC gpios */
3590+ return -EIO;
3591+}
3592+
3593+#endif
3594Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio-switch.h
3595===================================================================
3596--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3597@@ -0,0 +1,54 @@
3598+/*
3599+ * GPIO switch definitions
3600+ *
3601+ * Copyright (C) 2006 Nokia Corporation
3602+ *
3603+ * This program is free software; you can redistribute it and/or modify
3604+ * it under the terms of the GNU General Public License version 2 as
3605+ * published by the Free Software Foundation.
3606+ */
3607+
3608+#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3609+#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3610+
3611+#include <linux/types.h>
3612+
3613+/* Cover:
3614+ * high -> closed
3615+ * low -> open
3616+ * Connection:
3617+ * high -> connected
3618+ * low -> disconnected
3619+ * Activity:
3620+ * high -> active
3621+ * low -> inactive
3622+ *
3623+ */
3624+#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3625+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3626+#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3627+#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3628+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3629+
3630+struct omap_gpio_switch {
3631+ const char *name;
3632+ s16 gpio;
3633+ unsigned flags:4;
3634+ unsigned type:4;
3635+
3636+ /* Time in ms to debounce when transitioning from
3637+ * inactive state to active state. */
3638+ u16 debounce_rising;
3639+ /* Same for transition from active to inactive state. */
3640+ u16 debounce_falling;
3641+
3642+ /* notify board-specific code about state changes */
3643+ void (* notify)(void *data, int state);
3644+ void *notify_data;
3645+};
3646+
3647+/* Call at init time only */
3648+extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3649+ int count);
3650+
3651+#endif
3652Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc.h
3653===================================================================
3654--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3655@@ -0,0 +1,115 @@
3656+/*
3657+ * General-Purpose Memory Controller for OMAP2
3658+ *
3659+ * Copyright (C) 2005-2006 Nokia Corporation
3660+ *
3661+ * This program is free software; you can redistribute it and/or modify
3662+ * it under the terms of the GNU General Public License version 2 as
3663+ * published by the Free Software Foundation.
3664+ */
3665+
3666+#ifndef __OMAP2_GPMC_H
3667+#define __OMAP2_GPMC_H
3668+
3669+/* Maximum Number of Chip Selects */
3670+#define GPMC_CS_NUM 8
3671+
3672+#define GPMC_CS_CONFIG1 0x00
3673+#define GPMC_CS_CONFIG2 0x04
3674+#define GPMC_CS_CONFIG3 0x08
3675+#define GPMC_CS_CONFIG4 0x0c
3676+#define GPMC_CS_CONFIG5 0x10
3677+#define GPMC_CS_CONFIG6 0x14
3678+#define GPMC_CS_CONFIG7 0x18
3679+#define GPMC_CS_NAND_COMMAND 0x1c
3680+#define GPMC_CS_NAND_ADDRESS 0x20
3681+#define GPMC_CS_NAND_DATA 0x24
3682+
3683+#define GPMC_CONFIG 0x50
3684+#define GPMC_STATUS 0x54
3685+
3686+#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3687+#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3688+#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3689+#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3690+#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3691+#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3692+#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3693+#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3694+#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3695+#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3696+#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3697+#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3698+#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3699+#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3700+#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3701+#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3702+#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3703+#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3704+#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3705+#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3706+#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3707+#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3708+#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3709+#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3710+#define GPMC_CONFIG7_CSVALID (1 << 6)
3711+
3712+/*
3713+ * Note that all values in this struct are in nanoseconds, while
3714+ * the register values are in gpmc_fck cycles.
3715+ */
3716+struct gpmc_timings {
3717+ /* Minimum clock period for synchronous mode */
3718+ u16 sync_clk;
3719+
3720+ /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3721+ u16 cs_on; /* Assertion time */
3722+ u16 cs_rd_off; /* Read deassertion time */
3723+ u16 cs_wr_off; /* Write deassertion time */
3724+
3725+ /* ADV signal timings corresponding to GPMC_CONFIG3 */
3726+ u16 adv_on; /* Assertion time */
3727+ u16 adv_rd_off; /* Read deassertion time */
3728+ u16 adv_wr_off; /* Write deassertion time */
3729+
3730+ /* WE signals timings corresponding to GPMC_CONFIG4 */
3731+ u16 we_on; /* WE assertion time */
3732+ u16 we_off; /* WE deassertion time */
3733+
3734+ /* OE signals timings corresponding to GPMC_CONFIG4 */
3735+ u16 oe_on; /* OE assertion time */
3736+ u16 oe_off; /* OE deassertion time */
3737+
3738+ /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3739+ u16 page_burst_access; /* Multiple access word delay */
3740+ u16 access; /* Start-cycle to first data valid delay */
3741+ u16 rd_cycle; /* Total read cycle time */
3742+ u16 wr_cycle; /* Total write cycle time */
3743+
3744+ /* The following are only on OMAP3430 */
3745+ u16 wr_access; /* WRACCESSTIME */
3746+ u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3747+};
3748+
3749+extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3750+extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3751+extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3752+extern unsigned long gpmc_get_fclk_period(void);
3753+
3754+extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3755+extern u32 gpmc_cs_read_reg(int cs, int idx);
3756+extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3757+extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3758+extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3759+extern void gpmc_cs_free(int cs);
3760+extern int gpmc_cs_set_reserved(int cs, int reserved);
3761+extern int gpmc_cs_reserved(int cs);
3762+extern int gpmc_prefetch_enable(int cs, int dma_mode,
3763+ unsigned int u32_count, int is_write);
3764+extern void gpmc_prefetch_reset(void);
3765+extern int gpmc_prefetch_status(void);
3766+extern void omap3_gpmc_save_context(void);
3767+extern void omap3_gpmc_restore_context(void);
3768+extern void __init gpmc_init(void);
3769+
3770+#endif
3771Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3772===================================================================
3773--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3774@@ -0,0 +1,42 @@
3775+/*
3776+ * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3777+ *
3778+ * Copyright (C) 2009 Nokia Corporation
3779+ *
3780+ * This program is free software; you can redistribute it and/or modify
3781+ * it under the terms of the GNU General Public License version 2 as
3782+ * published by the Free Software Foundation.
3783+ */
3784+
3785+#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3786+
3787+#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3788+#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3789+#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3790+#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3791+
3792+struct omap_smc91x_platform_data {
3793+ int cs;
3794+ int gpio_irq;
3795+ int gpio_pwrdwn;
3796+ int gpio_reset;
3797+ int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3798+ u32 flags;
3799+ int (*retime)(void);
3800+};
3801+
3802+#if defined(CONFIG_SMC91X) || \
3803+ defined(CONFIG_SMC91X_MODULE)
3804+
3805+extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3806+
3807+#else
3808+
3809+#define board_smc91x_data NULL
3810+
3811+static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3812+{
3813+}
3814+
3815+#endif
3816+#endif
3817Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hardware.h
3818===================================================================
3819--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3820@@ -0,0 +1,290 @@
3821+/*
3822+ * arch/arm/plat-omap/include/mach/hardware.h
3823+ *
3824+ * Hardware definitions for TI OMAP processors and boards
3825+ *
3826+ * NOTE: Please put device driver specific defines into a separate header
3827+ * file for each driver.
3828+ *
3829+ * Copyright (C) 2001 RidgeRun, Inc.
3830+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3831+ *
3832+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3833+ * and Dirk Behme <dirk.behme@de.bosch.com>
3834+ *
3835+ * This program is free software; you can redistribute it and/or modify it
3836+ * under the terms of the GNU General Public License as published by the
3837+ * Free Software Foundation; either version 2 of the License, or (at your
3838+ * option) any later version.
3839+ *
3840+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3841+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3842+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3843+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3844+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3845+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3846+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3847+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3848+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3849+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3850+ *
3851+ * You should have received a copy of the GNU General Public License along
3852+ * with this program; if not, write to the Free Software Foundation, Inc.,
3853+ * 675 Mass Ave, Cambridge, MA 02139, USA.
3854+ */
3855+
3856+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3857+#define __ASM_ARCH_OMAP_HARDWARE_H
3858+
3859+#include <asm/sizes.h>
3860+#ifndef __ASSEMBLER__
3861+#include <asm/types.h>
3862+#include <plat/cpu.h>
3863+#endif
3864+#include <plat/serial.h>
3865+
3866+/*
3867+ * ---------------------------------------------------------------------------
3868+ * Common definitions for all OMAP processors
3869+ * NOTE: Put all processor or board specific parts to the special header
3870+ * files.
3871+ * ---------------------------------------------------------------------------
3872+ */
3873+
3874+/*
3875+ * ----------------------------------------------------------------------------
3876+ * Timers
3877+ * ----------------------------------------------------------------------------
3878+ */
3879+#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3880+#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3881+#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3882+#define MPU_TIMER_FREE (1 << 6)
3883+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
3884+#define MPU_TIMER_AR (1 << 1)
3885+#define MPU_TIMER_ST (1 << 0)
3886+
3887+/*
3888+ * ----------------------------------------------------------------------------
3889+ * Clocks
3890+ * ----------------------------------------------------------------------------
3891+ */
3892+#define CLKGEN_REG_BASE (0xfffece00)
3893+#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
3894+#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
3895+#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
3896+#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
3897+#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
3898+#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
3899+#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
3900+#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
3901+
3902+#define CK_RATEF 1
3903+#define CK_IDLEF 2
3904+#define CK_ENABLEF 4
3905+#define CK_SELECTF 8
3906+#define SETARM_IDLE_SHIFT
3907+
3908+/* DPLL control registers */
3909+#define DPLL_CTL (0xfffecf00)
3910+
3911+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
3912+#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
3913+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
3914+#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
3915+#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
3916+#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
3917+
3918+/*
3919+ * ---------------------------------------------------------------------------
3920+ * UPLD
3921+ * ---------------------------------------------------------------------------
3922+ */
3923+#define ULPD_REG_BASE (0xfffe0800)
3924+#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
3925+#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
3926+#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
3927+# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
3928+# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
3929+#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
3930+# define SOFT_UDC_REQ (1 << 4)
3931+# define SOFT_USB_CLK_REQ (1 << 3)
3932+# define SOFT_DPLL_REQ (1 << 0)
3933+#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
3934+#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
3935+#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
3936+#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
3937+#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
3938+# define DIS_MMC2_DPLL_REQ (1 << 11)
3939+# define DIS_MMC1_DPLL_REQ (1 << 10)
3940+# define DIS_UART3_DPLL_REQ (1 << 9)
3941+# define DIS_UART2_DPLL_REQ (1 << 8)
3942+# define DIS_UART1_DPLL_REQ (1 << 7)
3943+# define DIS_USB_HOST_DPLL_REQ (1 << 6)
3944+#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
3945+#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
3946+
3947+/*
3948+ * ---------------------------------------------------------------------------
3949+ * Watchdog timer
3950+ * ---------------------------------------------------------------------------
3951+ */
3952+
3953+/* Watchdog timer within the OMAP3.2 gigacell */
3954+#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
3955+#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
3956+#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3957+#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3958+#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
3959+
3960+/*
3961+ * ---------------------------------------------------------------------------
3962+ * Interrupts
3963+ * ---------------------------------------------------------------------------
3964+ */
3965+#ifdef CONFIG_ARCH_OMAP1
3966+
3967+/*
3968+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
3969+ * or something similar.. -- PFM.
3970+ */
3971+
3972+#define OMAP_IH1_BASE 0xfffecb00
3973+#define OMAP_IH2_BASE 0xfffe0000
3974+
3975+#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
3976+#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
3977+#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
3978+#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
3979+#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
3980+#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
3981+#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
3982+
3983+#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
3984+#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
3985+#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
3986+#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
3987+#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
3988+#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
3989+#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
3990+
3991+#define IRQ_ITR_REG_OFFSET 0x00
3992+#define IRQ_MIR_REG_OFFSET 0x04
3993+#define IRQ_SIR_IRQ_REG_OFFSET 0x10
3994+#define IRQ_SIR_FIQ_REG_OFFSET 0x14
3995+#define IRQ_CONTROL_REG_OFFSET 0x18
3996+#define IRQ_ISR_REG_OFFSET 0x9c
3997+#define IRQ_ILR0_REG_OFFSET 0x1c
3998+#define IRQ_GMR_REG_OFFSET 0xa0
3999+
4000+#endif
4001+
4002+/*
4003+ * ----------------------------------------------------------------------------
4004+ * System control registers
4005+ * ----------------------------------------------------------------------------
4006+ */
4007+#define MOD_CONF_CTRL_0 0xfffe1080
4008+#define MOD_CONF_CTRL_1 0xfffe1110
4009+
4010+/*
4011+ * ----------------------------------------------------------------------------
4012+ * Pin multiplexing registers
4013+ * ----------------------------------------------------------------------------
4014+ */
4015+#define FUNC_MUX_CTRL_0 0xfffe1000
4016+#define FUNC_MUX_CTRL_1 0xfffe1004
4017+#define FUNC_MUX_CTRL_2 0xfffe1008
4018+#define COMP_MODE_CTRL_0 0xfffe100c
4019+#define FUNC_MUX_CTRL_3 0xfffe1010
4020+#define FUNC_MUX_CTRL_4 0xfffe1014
4021+#define FUNC_MUX_CTRL_5 0xfffe1018
4022+#define FUNC_MUX_CTRL_6 0xfffe101C
4023+#define FUNC_MUX_CTRL_7 0xfffe1020
4024+#define FUNC_MUX_CTRL_8 0xfffe1024
4025+#define FUNC_MUX_CTRL_9 0xfffe1028
4026+#define FUNC_MUX_CTRL_A 0xfffe102C
4027+#define FUNC_MUX_CTRL_B 0xfffe1030
4028+#define FUNC_MUX_CTRL_C 0xfffe1034
4029+#define FUNC_MUX_CTRL_D 0xfffe1038
4030+#define PULL_DWN_CTRL_0 0xfffe1040
4031+#define PULL_DWN_CTRL_1 0xfffe1044
4032+#define PULL_DWN_CTRL_2 0xfffe1048
4033+#define PULL_DWN_CTRL_3 0xfffe104c
4034+#define PULL_DWN_CTRL_4 0xfffe10ac
4035+
4036+/* OMAP-1610 specific multiplexing registers */
4037+#define FUNC_MUX_CTRL_E 0xfffe1090
4038+#define FUNC_MUX_CTRL_F 0xfffe1094
4039+#define FUNC_MUX_CTRL_10 0xfffe1098
4040+#define FUNC_MUX_CTRL_11 0xfffe109c
4041+#define FUNC_MUX_CTRL_12 0xfffe10a0
4042+#define PU_PD_SEL_0 0xfffe10b4
4043+#define PU_PD_SEL_1 0xfffe10b8
4044+#define PU_PD_SEL_2 0xfffe10bc
4045+#define PU_PD_SEL_3 0xfffe10c0
4046+#define PU_PD_SEL_4 0xfffe10c4
4047+
4048+/* Timer32K for 1610 and 1710*/
4049+#define OMAP_TIMER32K_BASE 0xFFFBC400
4050+
4051+/*
4052+ * ---------------------------------------------------------------------------
4053+ * TIPB bus interface
4054+ * ---------------------------------------------------------------------------
4055+ */
4056+#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4057+#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4058+#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4059+#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4060+
4061+/*
4062+ * ----------------------------------------------------------------------------
4063+ * MPUI interface
4064+ * ----------------------------------------------------------------------------
4065+ */
4066+#define MPUI_BASE (0xfffec900)
4067+#define MPUI_CTRL (MPUI_BASE + 0x0)
4068+#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4069+#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4070+#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4071+#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4072+#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4073+#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4074+#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4075+
4076+/*
4077+ * ----------------------------------------------------------------------------
4078+ * LED Pulse Generator
4079+ * ----------------------------------------------------------------------------
4080+ */
4081+#define OMAP_LPG1_BASE 0xfffbd000
4082+#define OMAP_LPG2_BASE 0xfffbd800
4083+#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4084+#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4085+#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4086+#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4087+
4088+/*
4089+ * ----------------------------------------------------------------------------
4090+ * Pulse-Width Light
4091+ * ----------------------------------------------------------------------------
4092+ */
4093+#define OMAP_PWL_BASE 0xfffb5800
4094+#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4095+#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4096+
4097+/*
4098+ * ---------------------------------------------------------------------------
4099+ * Processor specific defines
4100+ * ---------------------------------------------------------------------------
4101+ */
4102+
4103+#include <plat/omap7xx.h>
4104+#include <plat/omap1510.h>
4105+#include <plat/omap16xx.h>
4106+#include <plat/omap24xx.h>
4107+#include <plat/omap34xx.h>
4108+#include <plat/omap44xx.h>
4109+
4110+#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4111Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hwa742.h
4112===================================================================
4113--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4114@@ -0,0 +1,8 @@
4115+#ifndef _HWA742_H
4116+#define _HWA742_H
4117+
4118+struct hwa742_platform_data {
4119+ unsigned te_connected:1;
4120+};
4121+
4122+#endif
4123Index: linux-2.6.35/arch/arm/plat-omap/include/mach/i2c.h
4124===================================================================
4125--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4126@@ -0,0 +1,39 @@
4127+/*
4128+ * Helper module for board specific I2C bus registration
4129+ *
4130+ * Copyright (C) 2009 Nokia Corporation.
4131+ *
4132+ * This program is free software; you can redistribute it and/or
4133+ * modify it under the terms of the GNU General Public License
4134+ * version 2 as published by the Free Software Foundation.
4135+ *
4136+ * This program is distributed in the hope that it will be useful, but
4137+ * WITHOUT ANY WARRANTY; without even the implied warranty of
4138+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4139+ * General Public License for more details.
4140+ *
4141+ * You should have received a copy of the GNU General Public License
4142+ * along with this program; if not, write to the Free Software
4143+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4144+ * 02110-1301 USA
4145+ *
4146+ */
4147+
4148+#include <linux/i2c.h>
4149+
4150+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4151+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4152+ struct i2c_board_info const *info,
4153+ unsigned len);
4154+#else
4155+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4156+ struct i2c_board_info const *info,
4157+ unsigned len)
4158+{
4159+ return 0;
4160+}
4161+#endif
4162+
4163+int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4164+ struct i2c_board_info const *info,
4165+ unsigned len);
4166Index: linux-2.6.35/arch/arm/plat-omap/include/mach/io.h
4167===================================================================
4168--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4169@@ -0,0 +1,287 @@
4170+/*
4171+ * arch/arm/plat-omap/include/mach/io.h
4172+ *
4173+ * IO definitions for TI OMAP processors and boards
4174+ *
4175+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
4176+ * Copyright (C) 1997-1999 Russell King
4177+ *
4178+ * Copyright (C) 2009 Texas Instruments
4179+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4180+ *
4181+ * This program is free software; you can redistribute it and/or modify it
4182+ * under the terms of the GNU General Public License as published by the
4183+ * Free Software Foundation; either version 2 of the License, or (at your
4184+ * option) any later version.
4185+ *
4186+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4187+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4188+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4189+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4190+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4191+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4192+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4193+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4194+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4195+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4196+ *
4197+ * You should have received a copy of the GNU General Public License along
4198+ * with this program; if not, write to the Free Software Foundation, Inc.,
4199+ * 675 Mass Ave, Cambridge, MA 02139, USA.
4200+ *
4201+ * Modifications:
4202+ * 06-12-1997 RMK Created.
4203+ * 07-04-1999 RMK Major cleanup
4204+ */
4205+
4206+#ifndef __ASM_ARM_ARCH_IO_H
4207+#define __ASM_ARM_ARCH_IO_H
4208+
4209+#include <mach/hardware.h>
4210+
4211+#define IO_SPACE_LIMIT 0xffffffff
4212+
4213+/*
4214+ * We don't actually have real ISA nor PCI buses, but there is so many
4215+ * drivers out there that might just work if we fake them...
4216+ */
4217+#define __io(a) __typesafe_io(a)
4218+#define __mem_pci(a) (a)
4219+
4220+/*
4221+ * ----------------------------------------------------------------------------
4222+ * I/O mapping
4223+ * ----------------------------------------------------------------------------
4224+ */
4225+
4226+#ifdef __ASSEMBLER__
4227+#define IOMEM(x) (x)
4228+#else
4229+#define IOMEM(x) ((void __force __iomem *)(x))
4230+#endif
4231+
4232+#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4233+#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4234+
4235+#define OMAP2_L3_IO_OFFSET 0x90000000
4236+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4237+
4238+
4239+#define OMAP2_L4_IO_OFFSET 0xb2000000
4240+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4241+
4242+#define OMAP4_L3_IO_OFFSET 0xb4000000
4243+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4244+
4245+#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4246+#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4247+
4248+#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4249+#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4250+
4251+#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4252+#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4253+
4254+/*
4255+ * ----------------------------------------------------------------------------
4256+ * Omap1 specific IO mapping
4257+ * ----------------------------------------------------------------------------
4258+ */
4259+
4260+#define OMAP1_IO_PHYS 0xFFFB0000
4261+#define OMAP1_IO_SIZE 0x40000
4262+#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4263+
4264+/*
4265+ * ----------------------------------------------------------------------------
4266+ * Omap2 specific IO mapping
4267+ * ----------------------------------------------------------------------------
4268+ */
4269+
4270+/* We map both L3 and L4 on OMAP2 */
4271+#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4272+#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4273+#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4274+#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4275+#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4276+#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4277+
4278+#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4279+#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4280+#define L4_WK_243X_SIZE SZ_1M
4281+#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4282+#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4283+ /* 0x6e000000 --> 0xfe000000 */
4284+#define OMAP243X_GPMC_SIZE SZ_1M
4285+#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4286+ /* 0x6D000000 --> 0xfd000000 */
4287+#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4288+#define OMAP243X_SDRC_SIZE SZ_1M
4289+#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4290+ /* 0x6c000000 --> 0xfc000000 */
4291+#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4292+#define OMAP243X_SMS_SIZE SZ_1M
4293+
4294+/* DSP */
4295+#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4296+#define DSP_MEM_24XX_VIRT 0xe0000000
4297+#define DSP_MEM_24XX_SIZE 0x28000
4298+#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4299+#define DSP_IPI_24XX_VIRT 0xe1000000
4300+#define DSP_IPI_24XX_SIZE SZ_4K
4301+#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4302+#define DSP_MMU_24XX_VIRT 0xe2000000
4303+#define DSP_MMU_24XX_SIZE SZ_4K
4304+
4305+/*
4306+ * ----------------------------------------------------------------------------
4307+ * Omap3 specific IO mapping
4308+ * ----------------------------------------------------------------------------
4309+ */
4310+
4311+/* We map both L3 and L4 on OMAP3 */
4312+#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4313+#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4314+#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4315+
4316+#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4317+#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4318+#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4319+
4320+/*
4321+ * Need to look at the Size 4M for L4.
4322+ * VPOM3430 was not working for Int controller
4323+ */
4324+
4325+#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4326+#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4327+#define L4_WK_34XX_SIZE SZ_1M
4328+
4329+#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4330+ /* 0x49000000 --> 0xfb000000 */
4331+#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4332+#define L4_PER_34XX_SIZE SZ_1M
4333+
4334+#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4335+ /* 0x54000000 --> 0xfe800000 */
4336+#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4337+#define L4_EMU_34XX_SIZE SZ_8M
4338+
4339+#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4340+ /* 0x6e000000 --> 0xfe000000 */
4341+#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4342+#define OMAP34XX_GPMC_SIZE SZ_1M
4343+
4344+#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4345+ /* 0x6c000000 --> 0xfc000000 */
4346+#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4347+#define OMAP343X_SMS_SIZE SZ_1M
4348+
4349+#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4350+ /* 0x6D000000 --> 0xfd000000 */
4351+#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4352+#define OMAP343X_SDRC_SIZE SZ_1M
4353+
4354+/* DSP */
4355+#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4356+#define DSP_MEM_34XX_VIRT 0xe0000000
4357+#define DSP_MEM_34XX_SIZE 0x28000
4358+#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4359+#define DSP_IPI_34XX_VIRT 0xe1000000
4360+#define DSP_IPI_34XX_SIZE SZ_4K
4361+#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4362+#define DSP_MMU_34XX_VIRT 0xe2000000
4363+#define DSP_MMU_34XX_SIZE SZ_4K
4364+
4365+/*
4366+ * ----------------------------------------------------------------------------
4367+ * Omap4 specific IO mapping
4368+ * ----------------------------------------------------------------------------
4369+ */
4370+
4371+/* We map both L3 and L4 on OMAP4 */
4372+#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4373+#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4374+#define L3_44XX_SIZE SZ_1M
4375+
4376+#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4377+#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4378+#define L4_44XX_SIZE SZ_4M
4379+
4380+
4381+#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4382+#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4383+#define L4_WK_44XX_SIZE SZ_1M
4384+
4385+#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4386+ /* 0x48000000 --> 0xfa000000 */
4387+#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4388+#define L4_PER_44XX_SIZE SZ_4M
4389+
4390+#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4391+ /* 0x49000000 --> 0xfb000000 */
4392+#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4393+#define L4_ABE_44XX_SIZE SZ_1M
4394+
4395+#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4396+ /* 0x54000000 --> 0xfe800000 */
4397+#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4398+#define L4_EMU_44XX_SIZE SZ_8M
4399+
4400+#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4401+ /* 0x50000000 --> 0xf9000000 */
4402+#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4403+#define OMAP44XX_GPMC_SIZE SZ_1M
4404+
4405+
4406+#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4407+ /* 0x4c000000 --> 0xfd100000 */
4408+#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4409+#define OMAP44XX_EMIF1_SIZE SZ_1M
4410+
4411+#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4412+ /* 0x4d000000 --> 0xfd200000 */
4413+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4414+#define OMAP44XX_EMIF2_SIZE SZ_1M
4415+
4416+#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4417+ /* 0x4e000000 --> 0xfd300000 */
4418+#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4419+#define OMAP44XX_DMM_SIZE SZ_1M
4420+/*
4421+ * ----------------------------------------------------------------------------
4422+ * Omap specific register access
4423+ * ----------------------------------------------------------------------------
4424+ */
4425+
4426+#ifndef __ASSEMBLER__
4427+
4428+/*
4429+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4430+ */
4431+
4432+extern u8 omap_readb(u32 pa);
4433+extern u16 omap_readw(u32 pa);
4434+extern u32 omap_readl(u32 pa);
4435+extern void omap_writeb(u8 v, u32 pa);
4436+extern void omap_writew(u16 v, u32 pa);
4437+extern void omap_writel(u32 v, u32 pa);
4438+
4439+struct omap_sdrc_params;
4440+
4441+extern void omap1_map_common_io(void);
4442+extern void omap1_init_common_hw(void);
4443+
4444+extern void omap2_map_common_io(void);
4445+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4446+ struct omap_sdrc_params *sdrc_cs1);
4447+
4448+#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4449+#define __arch_iounmap(v) omap_iounmap(v)
4450+
4451+void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4452+void omap_iounmap(volatile void __iomem *addr);
4453+
4454+#endif
4455+
4456+#endif
4457Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu2.h
4458===================================================================
4459--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4460@@ -0,0 +1,96 @@
4461+/*
4462+ * omap iommu: omap2 architecture specific definitions
4463+ *
4464+ * Copyright (C) 2008-2009 Nokia Corporation
4465+ *
4466+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4467+ *
4468+ * This program is free software; you can redistribute it and/or modify
4469+ * it under the terms of the GNU General Public License version 2 as
4470+ * published by the Free Software Foundation.
4471+ */
4472+
4473+#ifndef __MACH_IOMMU2_H
4474+#define __MACH_IOMMU2_H
4475+
4476+#include <linux/io.h>
4477+
4478+/*
4479+ * MMU Register offsets
4480+ */
4481+#define MMU_REVISION 0x00
4482+#define MMU_SYSCONFIG 0x10
4483+#define MMU_SYSSTATUS 0x14
4484+#define MMU_IRQSTATUS 0x18
4485+#define MMU_IRQENABLE 0x1c
4486+#define MMU_WALKING_ST 0x40
4487+#define MMU_CNTL 0x44
4488+#define MMU_FAULT_AD 0x48
4489+#define MMU_TTB 0x4c
4490+#define MMU_LOCK 0x50
4491+#define MMU_LD_TLB 0x54
4492+#define MMU_CAM 0x58
4493+#define MMU_RAM 0x5c
4494+#define MMU_GFLUSH 0x60
4495+#define MMU_FLUSH_ENTRY 0x64
4496+#define MMU_READ_CAM 0x68
4497+#define MMU_READ_RAM 0x6c
4498+#define MMU_EMU_FAULT_AD 0x70
4499+
4500+#define MMU_REG_SIZE 256
4501+
4502+/*
4503+ * MMU Register bit definitions
4504+ */
4505+#define MMU_LOCK_BASE_SHIFT 10
4506+#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4507+#define MMU_LOCK_BASE(x) \
4508+ ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4509+
4510+#define MMU_LOCK_VICT_SHIFT 4
4511+#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4512+#define MMU_LOCK_VICT(x) \
4513+ ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4514+
4515+#define MMU_CAM_VATAG_SHIFT 12
4516+#define MMU_CAM_VATAG_MASK \
4517+ ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4518+#define MMU_CAM_P (1 << 3)
4519+#define MMU_CAM_V (1 << 2)
4520+#define MMU_CAM_PGSZ_MASK 3
4521+#define MMU_CAM_PGSZ_1M (0 << 0)
4522+#define MMU_CAM_PGSZ_64K (1 << 0)
4523+#define MMU_CAM_PGSZ_4K (2 << 0)
4524+#define MMU_CAM_PGSZ_16M (3 << 0)
4525+
4526+#define MMU_RAM_PADDR_SHIFT 12
4527+#define MMU_RAM_PADDR_MASK \
4528+ ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4529+#define MMU_RAM_ENDIAN_SHIFT 9
4530+#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4531+#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4532+#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4533+#define MMU_RAM_ELSZ_SHIFT 7
4534+#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4535+#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4536+#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4537+#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4538+#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4539+#define MMU_RAM_MIXED_SHIFT 6
4540+#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4541+#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4542+
4543+/*
4544+ * register accessors
4545+ */
4546+static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4547+{
4548+ return __raw_readl(obj->regbase + offs);
4549+}
4550+
4551+static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4552+{
4553+ __raw_writel(val, obj->regbase + offs);
4554+}
4555+
4556+#endif /* __MACH_IOMMU2_H */
4557Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu.h
4558===================================================================
4559--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4560@@ -0,0 +1,168 @@
4561+/*
4562+ * omap iommu: main structures
4563+ *
4564+ * Copyright (C) 2008-2009 Nokia Corporation
4565+ *
4566+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4567+ *
4568+ * This program is free software; you can redistribute it and/or modify
4569+ * it under the terms of the GNU General Public License version 2 as
4570+ * published by the Free Software Foundation.
4571+ */
4572+
4573+#ifndef __MACH_IOMMU_H
4574+#define __MACH_IOMMU_H
4575+
4576+struct iotlb_entry {
4577+ u32 da;
4578+ u32 pa;
4579+ u32 pgsz, prsvd, valid;
4580+ union {
4581+ u16 ap;
4582+ struct {
4583+ u32 endian, elsz, mixed;
4584+ };
4585+ };
4586+};
4587+
4588+struct iommu {
4589+ const char *name;
4590+ struct module *owner;
4591+ struct clk *clk;
4592+ void __iomem *regbase;
4593+ struct device *dev;
4594+
4595+ unsigned int refcount;
4596+ struct mutex iommu_lock; /* global for this whole object */
4597+
4598+ /*
4599+ * We don't change iopgd for a situation like pgd for a task,
4600+ * but share it globally for each iommu.
4601+ */
4602+ u32 *iopgd;
4603+ spinlock_t page_table_lock; /* protect iopgd */
4604+
4605+ int nr_tlb_entries;
4606+
4607+ struct list_head mmap;
4608+ struct mutex mmap_lock; /* protect mmap */
4609+
4610+ int (*isr)(struct iommu *obj);
4611+
4612+ void *ctx; /* iommu context: registres saved area */
4613+};
4614+
4615+struct cr_regs {
4616+ union {
4617+ struct {
4618+ u16 cam_l;
4619+ u16 cam_h;
4620+ };
4621+ u32 cam;
4622+ };
4623+ union {
4624+ struct {
4625+ u16 ram_l;
4626+ u16 ram_h;
4627+ };
4628+ u32 ram;
4629+ };
4630+};
4631+
4632+struct iotlb_lock {
4633+ short base;
4634+ short vict;
4635+};
4636+
4637+/* architecture specific functions */
4638+struct iommu_functions {
4639+ unsigned long version;
4640+
4641+ int (*enable)(struct iommu *obj);
4642+ void (*disable)(struct iommu *obj);
4643+ u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4644+
4645+ void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4646+ void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4647+
4648+ struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4649+ int (*cr_valid)(struct cr_regs *cr);
4650+ u32 (*cr_to_virt)(struct cr_regs *cr);
4651+ void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4652+ ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4653+
4654+ u32 (*get_pte_attr)(struct iotlb_entry *e);
4655+
4656+ void (*save_ctx)(struct iommu *obj);
4657+ void (*restore_ctx)(struct iommu *obj);
4658+ ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4659+};
4660+
4661+struct iommu_platform_data {
4662+ const char *name;
4663+ const char *clk_name;
4664+ const int nr_tlb_entries;
4665+};
4666+
4667+#if defined(CONFIG_ARCH_OMAP1)
4668+#error "iommu for this processor not implemented yet"
4669+#else
4670+#include <plat/iommu2.h>
4671+#endif
4672+
4673+/*
4674+ * utilities for super page(16MB, 1MB, 64KB and 4KB)
4675+ */
4676+
4677+#define iopgsz_max(bytes) \
4678+ (((bytes) >= SZ_16M) ? SZ_16M : \
4679+ ((bytes) >= SZ_1M) ? SZ_1M : \
4680+ ((bytes) >= SZ_64K) ? SZ_64K : \
4681+ ((bytes) >= SZ_4K) ? SZ_4K : 0)
4682+
4683+#define bytes_to_iopgsz(bytes) \
4684+ (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4685+ ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4686+ ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4687+ ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4688+
4689+#define iopgsz_to_bytes(iopgsz) \
4690+ (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4691+ ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4692+ ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4693+ ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4694+
4695+#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4696+
4697+/*
4698+ * global functions
4699+ */
4700+extern u32 iommu_arch_version(void);
4701+
4702+extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4703+extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4704+
4705+extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4706+extern void flush_iotlb_page(struct iommu *obj, u32 da);
4707+extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4708+extern void flush_iotlb_all(struct iommu *obj);
4709+
4710+extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4711+extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4712+
4713+extern struct iommu *iommu_get(const char *name);
4714+extern void iommu_put(struct iommu *obj);
4715+
4716+extern void iommu_save_ctx(struct iommu *obj);
4717+extern void iommu_restore_ctx(struct iommu *obj);
4718+
4719+extern int install_iommu_arch(const struct iommu_functions *ops);
4720+extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4721+
4722+extern int foreach_iommu_device(void *data,
4723+ int (*fn)(struct device *, void *));
4724+
4725+extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4726+extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4727+
4728+#endif /* __MACH_IOMMU_H */
4729Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iovmm.h
4730===================================================================
4731--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4732@@ -0,0 +1,94 @@
4733+/*
4734+ * omap iommu: simple virtual address space management
4735+ *
4736+ * Copyright (C) 2008-2009 Nokia Corporation
4737+ *
4738+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4739+ *
4740+ * This program is free software; you can redistribute it and/or modify
4741+ * it under the terms of the GNU General Public License version 2 as
4742+ * published by the Free Software Foundation.
4743+ */
4744+
4745+#ifndef __IOMMU_MMAP_H
4746+#define __IOMMU_MMAP_H
4747+
4748+struct iovm_struct {
4749+ struct iommu *iommu; /* iommu object which this belongs to */
4750+ u32 da_start; /* area definition */
4751+ u32 da_end;
4752+ u32 flags; /* IOVMF_: see below */
4753+ struct list_head list; /* linked in ascending order */
4754+ const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4755+ void *va; /* mpu side mapped address */
4756+};
4757+
4758+/*
4759+ * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4760+ *
4761+ * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4762+ */
4763+#define IOVMF_SW_SHIFT 16
4764+#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4765+#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4766+#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4767+
4768+/*
4769+ * iovma: h/w flags derived from cam and ram attribute
4770+ */
4771+#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4772+#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4773+
4774+#define IOVMF_PGSZ_MASK (3 << 0)
4775+#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4776+#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4777+#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4778+#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4779+
4780+#define IOVMF_ENDIAN_MASK (1 << 9)
4781+#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4782+#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4783+
4784+#define IOVMF_ELSZ_MASK (3 << 7)
4785+#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4786+#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4787+#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4788+#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4789+
4790+#define IOVMF_MIXED_MASK (1 << 6)
4791+#define IOVMF_MIXED MMU_RAM_MIXED
4792+
4793+/*
4794+ * iovma: s/w flags, used for mapping and umapping internally.
4795+ */
4796+#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4797+#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4798+#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4799+
4800+/* "superpages" is supported just with physically linear pages */
4801+#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4802+#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4803+#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4804+
4805+#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4806+#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4807+#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4808+
4809+
4810+extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4811+extern u32 iommu_vmap(struct iommu *obj, u32 da,
4812+ const struct sg_table *sgt, u32 flags);
4813+extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4814+extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4815+ u32 flags);
4816+extern void iommu_vfree(struct iommu *obj, const u32 da);
4817+extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4818+ u32 flags);
4819+extern void iommu_kunmap(struct iommu *obj, u32 da);
4820+extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4821+ u32 flags);
4822+extern void iommu_kfree(struct iommu *obj, u32 da);
4823+
4824+extern void *da_to_va(struct iommu *obj, u32 da);
4825+
4826+#endif /* __IOMMU_MMAP_H */
4827Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irda.h
4828===================================================================
4829--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4830@@ -0,0 +1,33 @@
4831+/*
4832+ * arch/arm/plat-omap/include/mach/irda.h
4833+ *
4834+ * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4835+ *
4836+ * This program is free software; you can redistribute it and/or modify
4837+ * it under the terms of the GNU General Public License version 2 as
4838+ * published by the Free Software Foundation.
4839+ */
4840+#ifndef ASMARM_ARCH_IRDA_H
4841+#define ASMARM_ARCH_IRDA_H
4842+
4843+/* board specific transceiver capabilities */
4844+
4845+#define IR_SEL 1 /* Selects IrDA */
4846+#define IR_SIRMODE 2
4847+#define IR_FIRMODE 4
4848+#define IR_MIRMODE 8
4849+
4850+struct omap_irda_config {
4851+ int transceiver_cap;
4852+ int (*transceiver_mode)(struct device *dev, int mode);
4853+ int (*select_irda)(struct device *dev, int state);
4854+ int rx_channel;
4855+ int tx_channel;
4856+ unsigned long dest_start;
4857+ unsigned long src_start;
4858+ int tx_trigger;
4859+ int rx_trigger;
4860+ int mode;
4861+};
4862+
4863+#endif
4864Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irqs.h
4865===================================================================
4866--- /dev/null 1970-01-01 00:00:00.000000000 +0000
4867@@ -0,0 +1,506 @@
4868+/*
4869+ * arch/arm/plat-omap/include/mach/irqs.h
4870+ *
4871+ * Copyright (C) Greg Lonnon 2001
4872+ * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4873+ *
4874+ * Copyright (C) 2009 Texas Instruments
4875+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4876+ *
4877+ * This program is free software; you can redistribute it and/or modify
4878+ * it under the terms of the GNU General Public License as published by
4879+ * the Free Software Foundation; either version 2 of the License, or
4880+ * (at your option) any later version.
4881+ *
4882+ * This program is distributed in the hope that it will be useful,
4883+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4884+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4885+ * GNU General Public License for more details.
4886+ *
4887+ * You should have received a copy of the GNU General Public License
4888+ * along with this program; if not, write to the Free Software
4889+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4890+ *
4891+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
4892+ * are different.
4893+ */
4894+
4895+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
4896+#define __ASM_ARCH_OMAP15XX_IRQS_H
4897+
4898+/*
4899+ * IRQ numbers for interrupt handler 1
4900+ *
4901+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4902+ *
4903+ */
4904+#define INT_CAMERA 1
4905+#define INT_FIQ 3
4906+#define INT_RTDX 6
4907+#define INT_DSP_MMU_ABORT 7
4908+#define INT_HOST 8
4909+#define INT_ABORT 9
4910+#define INT_BRIDGE_PRIV 13
4911+#define INT_GPIO_BANK1 14
4912+#define INT_UART3 15
4913+#define INT_TIMER3 16
4914+#define INT_DMA_CH0_6 19
4915+#define INT_DMA_CH1_7 20
4916+#define INT_DMA_CH2_8 21
4917+#define INT_DMA_CH3 22
4918+#define INT_DMA_CH4 23
4919+#define INT_DMA_CH5 24
4920+#define INT_DMA_LCD 25
4921+#define INT_TIMER1 26
4922+#define INT_WD_TIMER 27
4923+#define INT_BRIDGE_PUB 28
4924+#define INT_TIMER2 30
4925+#define INT_LCD_CTRL 31
4926+
4927+/*
4928+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
4929+ */
4930+#define INT_1510_IH2_IRQ 0
4931+#define INT_1510_RES2 2
4932+#define INT_1510_SPI_TX 4
4933+#define INT_1510_SPI_RX 5
4934+#define INT_1510_DSP_MAILBOX1 10
4935+#define INT_1510_DSP_MAILBOX2 11
4936+#define INT_1510_RES12 12
4937+#define INT_1510_LB_MMU 17
4938+#define INT_1510_RES18 18
4939+#define INT_1510_LOCAL_BUS 29
4940+
4941+/*
4942+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
4943+ */
4944+#define INT_1610_IH2_IRQ 0
4945+#define INT_1610_IH2_FIQ 2
4946+#define INT_1610_McBSP2_TX 4
4947+#define INT_1610_McBSP2_RX 5
4948+#define INT_1610_DSP_MAILBOX1 10
4949+#define INT_1610_DSP_MAILBOX2 11
4950+#define INT_1610_LCD_LINE 12
4951+#define INT_1610_GPTIMER1 17
4952+#define INT_1610_GPTIMER2 18
4953+#define INT_1610_SSR_FIFO_0 29
4954+
4955+/*
4956+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
4957+ */
4958+#define INT_7XX_IH2_FIQ 0
4959+#define INT_7XX_IH2_IRQ 1
4960+#define INT_7XX_USB_NON_ISO 2
4961+#define INT_7XX_USB_ISO 3
4962+#define INT_7XX_ICR 4
4963+#define INT_7XX_EAC 5
4964+#define INT_7XX_GPIO_BANK1 6
4965+#define INT_7XX_GPIO_BANK2 7
4966+#define INT_7XX_GPIO_BANK3 8
4967+#define INT_7XX_McBSP2TX 10
4968+#define INT_7XX_McBSP2RX 11
4969+#define INT_7XX_McBSP2RX_OVF 12
4970+#define INT_7XX_LCD_LINE 14
4971+#define INT_7XX_GSM_PROTECT 15
4972+#define INT_7XX_TIMER3 16
4973+#define INT_7XX_GPIO_BANK5 17
4974+#define INT_7XX_GPIO_BANK6 18
4975+#define INT_7XX_SPGIO_WR 29
4976+
4977+/*
4978+ * IRQ numbers for interrupt handler 2
4979+ *
4980+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4981+ */
4982+#define IH2_BASE 32
4983+
4984+#define INT_KEYBOARD (1 + IH2_BASE)
4985+#define INT_uWireTX (2 + IH2_BASE)
4986+#define INT_uWireRX (3 + IH2_BASE)
4987+#define INT_I2C (4 + IH2_BASE)
4988+#define INT_MPUIO (5 + IH2_BASE)
4989+#define INT_USB_HHC_1 (6 + IH2_BASE)
4990+#define INT_McBSP3TX (10 + IH2_BASE)
4991+#define INT_McBSP3RX (11 + IH2_BASE)
4992+#define INT_McBSP1TX (12 + IH2_BASE)
4993+#define INT_McBSP1RX (13 + IH2_BASE)
4994+#define INT_UART1 (14 + IH2_BASE)
4995+#define INT_UART2 (15 + IH2_BASE)
4996+#define INT_BT_MCSI1TX (16 + IH2_BASE)
4997+#define INT_BT_MCSI1RX (17 + IH2_BASE)
4998+#define INT_SOSSI_MATCH (19 + IH2_BASE)
4999+#define INT_USB_W2FC (20 + IH2_BASE)
5000+#define INT_1WIRE (21 + IH2_BASE)
5001+#define INT_OS_TIMER (22 + IH2_BASE)
5002+#define INT_MMC (23 + IH2_BASE)
5003+#define INT_GAUGE_32K (24 + IH2_BASE)
5004+#define INT_RTC_TIMER (25 + IH2_BASE)
5005+#define INT_RTC_ALARM (26 + IH2_BASE)
5006+#define INT_MEM_STICK (27 + IH2_BASE)
5007+
5008+/*
5009+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
5010+ */
5011+#define INT_1510_DSP_MMU (28 + IH2_BASE)
5012+#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5013+
5014+/*
5015+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
5016+ */
5017+#define INT_1610_FAC (0 + IH2_BASE)
5018+#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5019+#define INT_1610_USB_OTG (8 + IH2_BASE)
5020+#define INT_1610_SoSSI (9 + IH2_BASE)
5021+#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5022+#define INT_1610_DSP_MMU (28 + IH2_BASE)
5023+#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5024+#define INT_1610_STI (32 + IH2_BASE)
5025+#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5026+#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5027+#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5028+#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5029+#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5030+#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5031+#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5032+#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5033+#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5034+#define INT_1610_MMC2 (42 + IH2_BASE)
5035+#define INT_1610_CF (43 + IH2_BASE)
5036+#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5037+#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5038+#define INT_1610_SPI (49 + IH2_BASE)
5039+#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5040+#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5041+#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5042+#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5043+#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5044+#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5045+#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5046+#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5047+#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5048+#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5049+#define INT_1610_NAND (63 + IH2_BASE)
5050+#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5051+
5052+/*
5053+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
5054+ */
5055+#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5056+#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5057+#define INT_7XX_CFCD (2 + IH2_BASE)
5058+#define INT_7XX_CFIREQ (3 + IH2_BASE)
5059+#define INT_7XX_I2C (4 + IH2_BASE)
5060+#define INT_7XX_PCC (5 + IH2_BASE)
5061+#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5062+#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5063+#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5064+#define INT_7XX_VLYNQ (9 + IH2_BASE)
5065+#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5066+#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5067+#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5068+#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5069+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5070+#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5071+#define INT_7XX_MCSI (16 + IH2_BASE)
5072+#define INT_7XX_uWireTX (17 + IH2_BASE)
5073+#define INT_7XX_uWireRX (18 + IH2_BASE)
5074+#define INT_7XX_SMC_CD (19 + IH2_BASE)
5075+#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5076+#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5077+#define INT_7XX_TIMER32K (22 + IH2_BASE)
5078+#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5079+#define INT_7XX_UPLD (24 + IH2_BASE)
5080+#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5081+#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5082+#define INT_7XX_USB_GENI (29 + IH2_BASE)
5083+#define INT_7XX_USB_OTG (30 + IH2_BASE)
5084+#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5085+#define INT_7XX_RNG (32 + IH2_BASE)
5086+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5087+#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5088+#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5089+#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5090+#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5091+#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5092+#define INT_7XX_MPUIO (39 + IH2_BASE)
5093+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5094+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5095+#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5096+#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5097+#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5098+#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5099+#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5100+#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5101+#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5102+#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5103+#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5104+#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5105+#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5106+#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5107+#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5108+#define INT_7XX_NAND (63 + IH2_BASE)
5109+
5110+#define INT_24XX_SYS_NIRQ 7
5111+#define INT_24XX_SDMA_IRQ0 12
5112+#define INT_24XX_SDMA_IRQ1 13
5113+#define INT_24XX_SDMA_IRQ2 14
5114+#define INT_24XX_SDMA_IRQ3 15
5115+#define INT_24XX_CAM_IRQ 24
5116+#define INT_24XX_DSS_IRQ 25
5117+#define INT_24XX_MAIL_U0_MPU 26
5118+#define INT_24XX_DSP_UMA 27
5119+#define INT_24XX_DSP_MMU 28
5120+#define INT_24XX_GPIO_BANK1 29
5121+#define INT_24XX_GPIO_BANK2 30
5122+#define INT_24XX_GPIO_BANK3 31
5123+#define INT_24XX_GPIO_BANK4 32
5124+#define INT_24XX_GPIO_BANK5 33
5125+#define INT_24XX_MAIL_U3_MPU 34
5126+#define INT_24XX_GPTIMER1 37
5127+#define INT_24XX_GPTIMER2 38
5128+#define INT_24XX_GPTIMER3 39
5129+#define INT_24XX_GPTIMER4 40
5130+#define INT_24XX_GPTIMER5 41
5131+#define INT_24XX_GPTIMER6 42
5132+#define INT_24XX_GPTIMER7 43
5133+#define INT_24XX_GPTIMER8 44
5134+#define INT_24XX_GPTIMER9 45
5135+#define INT_24XX_GPTIMER10 46
5136+#define INT_24XX_GPTIMER11 47
5137+#define INT_24XX_GPTIMER12 48
5138+#define INT_24XX_SHA1MD5 51
5139+#define INT_24XX_MCBSP4_IRQ_TX 54
5140+#define INT_24XX_MCBSP4_IRQ_RX 55
5141+#define INT_24XX_I2C1_IRQ 56
5142+#define INT_24XX_I2C2_IRQ 57
5143+#define INT_24XX_HDQ_IRQ 58
5144+#define INT_24XX_MCBSP1_IRQ_TX 59
5145+#define INT_24XX_MCBSP1_IRQ_RX 60
5146+#define INT_24XX_MCBSP2_IRQ_TX 62
5147+#define INT_24XX_MCBSP2_IRQ_RX 63
5148+#define INT_24XX_SPI1_IRQ 65
5149+#define INT_24XX_SPI2_IRQ 66
5150+#define INT_24XX_UART1_IRQ 72
5151+#define INT_24XX_UART2_IRQ 73
5152+#define INT_24XX_UART3_IRQ 74
5153+#define INT_24XX_USB_IRQ_GEN 75
5154+#define INT_24XX_USB_IRQ_NISO 76
5155+#define INT_24XX_USB_IRQ_ISO 77
5156+#define INT_24XX_USB_IRQ_HGEN 78
5157+#define INT_24XX_USB_IRQ_HSOF 79
5158+#define INT_24XX_USB_IRQ_OTG 80
5159+#define INT_24XX_MCBSP5_IRQ_TX 81
5160+#define INT_24XX_MCBSP5_IRQ_RX 82
5161+#define INT_24XX_MMC_IRQ 83
5162+#define INT_24XX_MMC2_IRQ 86
5163+#define INT_24XX_MCBSP3_IRQ_TX 89
5164+#define INT_24XX_MCBSP3_IRQ_RX 90
5165+#define INT_24XX_SPI3_IRQ 91
5166+
5167+#define INT_243X_MCBSP2_IRQ 16
5168+#define INT_243X_MCBSP3_IRQ 17
5169+#define INT_243X_MCBSP4_IRQ 18
5170+#define INT_243X_MCBSP5_IRQ 19
5171+#define INT_243X_MCBSP1_IRQ 64
5172+#define INT_243X_HS_USB_MC 92
5173+#define INT_243X_HS_USB_DMA 93
5174+#define INT_243X_CARKIT_IRQ 94
5175+
5176+#define INT_34XX_BENCH_MPU_EMUL 3
5177+#define INT_34XX_ST_MCBSP2_IRQ 4
5178+#define INT_34XX_ST_MCBSP3_IRQ 5
5179+#define INT_34XX_SSM_ABORT_IRQ 6
5180+#define INT_34XX_SYS_NIRQ 7
5181+#define INT_34XX_D2D_FW_IRQ 8
5182+#define INT_34XX_PRCM_MPU_IRQ 11
5183+#define INT_34XX_MCBSP1_IRQ 16
5184+#define INT_34XX_MCBSP2_IRQ 17
5185+#define INT_34XX_MCBSP3_IRQ 22
5186+#define INT_34XX_MCBSP4_IRQ 23
5187+#define INT_34XX_CAM_IRQ 24
5188+#define INT_34XX_MCBSP5_IRQ 27
5189+#define INT_34XX_GPIO_BANK1 29
5190+#define INT_34XX_GPIO_BANK2 30
5191+#define INT_34XX_GPIO_BANK3 31
5192+#define INT_34XX_GPIO_BANK4 32
5193+#define INT_34XX_GPIO_BANK5 33
5194+#define INT_34XX_GPIO_BANK6 34
5195+#define INT_34XX_USIM_IRQ 35
5196+#define INT_34XX_WDT3_IRQ 36
5197+#define INT_34XX_SPI4_IRQ 48
5198+#define INT_34XX_SHA1MD52_IRQ 49
5199+#define INT_34XX_FPKA_READY_IRQ 50
5200+#define INT_34XX_SHA1MD51_IRQ 51
5201+#define INT_34XX_RNG_IRQ 52
5202+#define INT_34XX_I2C3_IRQ 61
5203+#define INT_34XX_FPKA_ERROR_IRQ 64
5204+#define INT_34XX_PBIAS_IRQ 75
5205+#define INT_34XX_OHCI_IRQ 76
5206+#define INT_34XX_EHCI_IRQ 77
5207+#define INT_34XX_TLL_IRQ 78
5208+#define INT_34XX_PARTHASH_IRQ 79
5209+#define INT_34XX_MMC3_IRQ 94
5210+#define INT_34XX_GPT12_IRQ 95
5211+
5212+#define INT_34XX_BENCH_MPU_EMUL 3
5213+
5214+
5215+#define IRQ_GIC_START 32
5216+#define INT_44XX_LOCALTIMER_IRQ 29
5217+#define INT_44XX_LOCALWDT_IRQ 30
5218+
5219+#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5220+#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5221+#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5222+#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5223+#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5224+#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5225+#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5226+#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5227+#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5228+#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5229+#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5230+#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5231+#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5232+#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5233+#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5234+#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5235+#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5236+#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5237+#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5238+#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5239+#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5240+#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5241+#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5242+#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5243+#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5244+#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5245+#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5246+#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5247+#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5248+#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5249+#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5250+#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5251+#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5252+#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5253+#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5254+#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5255+#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5256+#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5257+#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5258+#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5259+#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5260+#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5261+#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5262+#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5263+#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5264+#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5265+#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5266+#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5267+#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5268+#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5269+#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5270+
5271+#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5272+#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5273+#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5274+#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5275+#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5276+#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5277+#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5278+
5279+#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5280+#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5281+#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5282+#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5283+#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5284+#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5285+#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5286+#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5287+#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5288+#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5289+#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5290+#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5291+#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5292+#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5293+#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5294+#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5295+#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5296+#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5297+#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5298+#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5299+#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5300+#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5301+#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5302+
5303+
5304+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5305+ * 16 MPUIO lines */
5306+#define OMAP_MAX_GPIO_LINES 192
5307+#define IH_GPIO_BASE (128 + IH2_BASE)
5308+#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5309+#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5310+
5311+/* External FPGA handles interrupts on Innovator boards */
5312+#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5313+#ifdef CONFIG_MACH_OMAP_INNOVATOR
5314+#define OMAP_FPGA_NR_IRQS 24
5315+#else
5316+#define OMAP_FPGA_NR_IRQS 0
5317+#endif
5318+#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5319+
5320+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5321+#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5322+#ifdef CONFIG_TWL4030_CORE
5323+#define TWL4030_BASE_NR_IRQS 8
5324+#define TWL4030_PWR_NR_IRQS 8
5325+#else
5326+#define TWL4030_BASE_NR_IRQS 0
5327+#define TWL4030_PWR_NR_IRQS 0
5328+#endif
5329+#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5330+#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5331+#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5332+
5333+/* External TWL4030 gpio interrupts are optional */
5334+#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5335+#ifdef CONFIG_GPIO_TWL4030
5336+#define TWL4030_GPIO_NR_IRQS 18
5337+#else
5338+#define TWL4030_GPIO_NR_IRQS 0
5339+#endif
5340+#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5341+
5342+#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5343+#ifdef CONFIG_TWL4030_CORE
5344+#define TWL6030_BASE_NR_IRQS 20
5345+#else
5346+#define TWL6030_BASE_NR_IRQS 0
5347+#endif
5348+#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5349+
5350+/* Total number of interrupts depends on the enabled blocks above */
5351+#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5352+#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5353+#else
5354+#define TWL_IRQ_END TWL6030_IRQ_END
5355+#endif
5356+
5357+#define NR_IRQS TWL_IRQ_END
5358+
5359+#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5360+
5361+#define INTCPS_NR_MIR_REGS 3
5362+#define INTCPS_NR_IRQS 96
5363+
5364+#ifndef __ASSEMBLY__
5365+extern void omap_init_irq(void);
5366+extern int omap_irq_pending(void);
5367+void omap_intc_save_context(void);
5368+void omap_intc_restore_context(void);
5369+#endif
5370+
5371+#include <mach/hardware.h>
5372+
5373+#endif
5374Index: linux-2.6.35/arch/arm/plat-omap/include/mach/keypad.h
5375===================================================================
5376--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5377@@ -0,0 +1,45 @@
5378+/*
5379+ * arch/arm/plat-omap/include/mach/keypad.h
5380+ *
5381+ * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5382+ *
5383+ * This program is free software; you can redistribute it and/or modify
5384+ * it under the terms of the GNU General Public License version 2 as
5385+ * published by the Free Software Foundation.
5386+ */
5387+#ifndef ASMARM_ARCH_KEYPAD_H
5388+#define ASMARM_ARCH_KEYPAD_H
5389+
5390+#warning: Please update the board to use matrix_keypad.h instead
5391+
5392+struct omap_kp_platform_data {
5393+ int rows;
5394+ int cols;
5395+ int *keymap;
5396+ unsigned int keymapsize;
5397+ unsigned int rep:1;
5398+ unsigned long delay;
5399+ unsigned int dbounce:1;
5400+ /* specific to OMAP242x*/
5401+ unsigned int *row_gpios;
5402+ unsigned int *col_gpios;
5403+};
5404+
5405+/* Group (0..3) -- when multiple keys are pressed, only the
5406+ * keys pressed in the same group are considered as pressed. This is
5407+ * in order to workaround certain crappy HW designs that produce ghost
5408+ * keypresses. */
5409+#define GROUP_0 (0 << 16)
5410+#define GROUP_1 (1 << 16)
5411+#define GROUP_2 (2 << 16)
5412+#define GROUP_3 (3 << 16)
5413+#define GROUP_MASK GROUP_3
5414+
5415+#define KEY_PERSISTENT 0x00800000
5416+#define KEYNUM_MASK 0x00EFFFFF
5417+#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5418+#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5419+ KEY_PERSISTENT)
5420+
5421+#endif
5422+
5423Index: linux-2.6.35/arch/arm/plat-omap/include/mach/lcd_mipid.h
5424===================================================================
5425--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5426@@ -0,0 +1,29 @@
5427+#ifndef __LCD_MIPID_H
5428+#define __LCD_MIPID_H
5429+
5430+enum mipid_test_num {
5431+ MIPID_TEST_RGB_LINES,
5432+};
5433+
5434+enum mipid_test_result {
5435+ MIPID_TEST_SUCCESS,
5436+ MIPID_TEST_INVALID,
5437+ MIPID_TEST_FAILED,
5438+};
5439+
5440+#ifdef __KERNEL__
5441+
5442+struct mipid_platform_data {
5443+ int nreset_gpio;
5444+ int data_lines;
5445+
5446+ void (*shutdown)(struct mipid_platform_data *pdata);
5447+ void (*set_bklight_level)(struct mipid_platform_data *pdata,
5448+ int level);
5449+ int (*get_bklight_level)(struct mipid_platform_data *pdata);
5450+ int (*get_bklight_max)(struct mipid_platform_data *pdata);
5451+};
5452+
5453+#endif
5454+
5455+#endif
5456Index: linux-2.6.35/arch/arm/plat-omap/include/mach/led.h
5457===================================================================
5458--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5459@@ -0,0 +1,24 @@
5460+/*
5461+ * arch/arm/plat-omap/include/mach/led.h
5462+ *
5463+ * Copyright (C) 2006 Samsung Electronics
5464+ * Kyungmin Park <kyungmin.park@samsung.com>
5465+ *
5466+ * This program is free software; you can redistribute it and/or modify
5467+ * it under the terms of the GNU General Public License version 2 as
5468+ * published by the Free Software Foundation.
5469+ */
5470+#ifndef ASMARM_ARCH_LED_H
5471+#define ASMARM_ARCH_LED_H
5472+
5473+struct omap_led_config {
5474+ struct led_classdev cdev;
5475+ s16 gpio;
5476+};
5477+
5478+struct omap_led_platform_data {
5479+ s16 nr_leds;
5480+ struct omap_led_config *leds;
5481+};
5482+
5483+#endif
5484Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mailbox.h
5485===================================================================
5486--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5487@@ -0,0 +1,111 @@
5488+/* mailbox.h */
5489+
5490+#ifndef MAILBOX_H
5491+#define MAILBOX_H
5492+
5493+#include <linux/wait.h>
5494+#include <linux/workqueue.h>
5495+#include <linux/blkdev.h>
5496+#include <linux/interrupt.h>
5497+
5498+typedef u32 mbox_msg_t;
5499+struct omap_mbox;
5500+
5501+typedef int __bitwise omap_mbox_irq_t;
5502+#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5503+#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5504+
5505+typedef int __bitwise omap_mbox_type_t;
5506+#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5507+#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5508+
5509+struct omap_mbox_ops {
5510+ omap_mbox_type_t type;
5511+ int (*startup)(struct omap_mbox *mbox);
5512+ void (*shutdown)(struct omap_mbox *mbox);
5513+ /* fifo */
5514+ mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5515+ void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5516+ int (*fifo_empty)(struct omap_mbox *mbox);
5517+ int (*fifo_full)(struct omap_mbox *mbox);
5518+ /* irq */
5519+ void (*enable_irq)(struct omap_mbox *mbox,
5520+ omap_mbox_irq_t irq);
5521+ void (*disable_irq)(struct omap_mbox *mbox,
5522+ omap_mbox_irq_t irq);
5523+ void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5524+ int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5525+ /* ctx */
5526+ void (*save_ctx)(struct omap_mbox *mbox);
5527+ void (*restore_ctx)(struct omap_mbox *mbox);
5528+};
5529+
5530+struct omap_mbox_queue {
5531+ spinlock_t lock;
5532+ struct request_queue *queue;
5533+ struct work_struct work;
5534+ struct tasklet_struct tasklet;
5535+ int (*callback)(void *);
5536+ struct omap_mbox *mbox;
5537+};
5538+
5539+struct omap_mbox {
5540+ char *name;
5541+ unsigned int irq;
5542+
5543+ struct omap_mbox_queue *txq, *rxq;
5544+
5545+ struct omap_mbox_ops *ops;
5546+
5547+ mbox_msg_t seq_snd, seq_rcv;
5548+
5549+ struct device *dev;
5550+
5551+ struct omap_mbox *next;
5552+ void *priv;
5553+
5554+ void (*err_notify)(void);
5555+};
5556+
5557+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5558+void omap_mbox_init_seq(struct omap_mbox *);
5559+
5560+struct omap_mbox *omap_mbox_get(const char *);
5561+void omap_mbox_put(struct omap_mbox *);
5562+
5563+int omap_mbox_register(struct device *parent, struct omap_mbox *);
5564+int omap_mbox_unregister(struct omap_mbox *);
5565+
5566+static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5567+{
5568+ if (!mbox->ops->save_ctx) {
5569+ dev_err(mbox->dev, "%s:\tno save\n", __func__);
5570+ return;
5571+ }
5572+
5573+ mbox->ops->save_ctx(mbox);
5574+}
5575+
5576+static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5577+{
5578+ if (!mbox->ops->restore_ctx) {
5579+ dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5580+ return;
5581+ }
5582+
5583+ mbox->ops->restore_ctx(mbox);
5584+}
5585+
5586+static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5587+ omap_mbox_irq_t irq)
5588+{
5589+ mbox->ops->enable_irq(mbox, irq);
5590+}
5591+
5592+static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5593+ omap_mbox_irq_t irq)
5594+{
5595+ mbox->ops->disable_irq(mbox, irq);
5596+}
5597+
5598+#endif /* MAILBOX_H */
5599Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcbsp.h
5600===================================================================
5601--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5602@@ -0,0 +1,462 @@
5603+/*
5604+ * arch/arm/plat-omap/include/mach/mcbsp.h
5605+ *
5606+ * Defines for Multi-Channel Buffered Serial Port
5607+ *
5608+ * Copyright (C) 2002 RidgeRun, Inc.
5609+ * Author: Steve Johnson
5610+ *
5611+ * This program is free software; you can redistribute it and/or modify
5612+ * it under the terms of the GNU General Public License as published by
5613+ * the Free Software Foundation; either version 2 of the License, or
5614+ * (at your option) any later version.
5615+ *
5616+ * This program is distributed in the hope that it will be useful,
5617+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5618+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5619+ * GNU General Public License for more details.
5620+ *
5621+ * You should have received a copy of the GNU General Public License
5622+ * along with this program; if not, write to the Free Software
5623+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5624+ *
5625+ */
5626+#ifndef __ASM_ARCH_OMAP_MCBSP_H
5627+#define __ASM_ARCH_OMAP_MCBSP_H
5628+
5629+#include <linux/completion.h>
5630+#include <linux/spinlock.h>
5631+
5632+#include <mach/hardware.h>
5633+#include <plat/clock.h>
5634+
5635+#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5636+#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5637+
5638+#define OMAP1510_MCBSP1_BASE 0xe1011800
5639+#define OMAP1510_MCBSP2_BASE 0xfffb1000
5640+#define OMAP1510_MCBSP3_BASE 0xe1017000
5641+
5642+#define OMAP1610_MCBSP1_BASE 0xe1011800
5643+#define OMAP1610_MCBSP2_BASE 0xfffb1000
5644+#define OMAP1610_MCBSP3_BASE 0xe1017000
5645+
5646+#define OMAP24XX_MCBSP1_BASE 0x48074000
5647+#define OMAP24XX_MCBSP2_BASE 0x48076000
5648+#define OMAP2430_MCBSP3_BASE 0x4808c000
5649+#define OMAP2430_MCBSP4_BASE 0x4808e000
5650+#define OMAP2430_MCBSP5_BASE 0x48096000
5651+
5652+#define OMAP34XX_MCBSP1_BASE 0x48074000
5653+#define OMAP34XX_MCBSP2_BASE 0x49022000
5654+#define OMAP34XX_MCBSP3_BASE 0x49024000
5655+#define OMAP34XX_MCBSP4_BASE 0x49026000
5656+#define OMAP34XX_MCBSP5_BASE 0x48096000
5657+
5658+#define OMAP44XX_MCBSP1_BASE 0x49022000
5659+#define OMAP44XX_MCBSP2_BASE 0x49024000
5660+#define OMAP44XX_MCBSP3_BASE 0x49026000
5661+#define OMAP44XX_MCBSP4_BASE 0x48074000
5662+
5663+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5664+
5665+#define OMAP_MCBSP_REG_DRR2 0x00
5666+#define OMAP_MCBSP_REG_DRR1 0x02
5667+#define OMAP_MCBSP_REG_DXR2 0x04
5668+#define OMAP_MCBSP_REG_DXR1 0x06
5669+#define OMAP_MCBSP_REG_SPCR2 0x08
5670+#define OMAP_MCBSP_REG_SPCR1 0x0a
5671+#define OMAP_MCBSP_REG_RCR2 0x0c
5672+#define OMAP_MCBSP_REG_RCR1 0x0e
5673+#define OMAP_MCBSP_REG_XCR2 0x10
5674+#define OMAP_MCBSP_REG_XCR1 0x12
5675+#define OMAP_MCBSP_REG_SRGR2 0x14
5676+#define OMAP_MCBSP_REG_SRGR1 0x16
5677+#define OMAP_MCBSP_REG_MCR2 0x18
5678+#define OMAP_MCBSP_REG_MCR1 0x1a
5679+#define OMAP_MCBSP_REG_RCERA 0x1c
5680+#define OMAP_MCBSP_REG_RCERB 0x1e
5681+#define OMAP_MCBSP_REG_XCERA 0x20
5682+#define OMAP_MCBSP_REG_XCERB 0x22
5683+#define OMAP_MCBSP_REG_PCR0 0x24
5684+#define OMAP_MCBSP_REG_RCERC 0x26
5685+#define OMAP_MCBSP_REG_RCERD 0x28
5686+#define OMAP_MCBSP_REG_XCERC 0x2A
5687+#define OMAP_MCBSP_REG_XCERD 0x2C
5688+#define OMAP_MCBSP_REG_RCERE 0x2E
5689+#define OMAP_MCBSP_REG_RCERF 0x30
5690+#define OMAP_MCBSP_REG_XCERE 0x32
5691+#define OMAP_MCBSP_REG_XCERF 0x34
5692+#define OMAP_MCBSP_REG_RCERG 0x36
5693+#define OMAP_MCBSP_REG_RCERH 0x38
5694+#define OMAP_MCBSP_REG_XCERG 0x3A
5695+#define OMAP_MCBSP_REG_XCERH 0x3C
5696+
5697+/* Dummy defines, these are not available on omap1 */
5698+#define OMAP_MCBSP_REG_XCCR 0x00
5699+#define OMAP_MCBSP_REG_RCCR 0x00
5700+
5701+#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5702+#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5703+
5704+#define AUDIO_MCBSP OMAP_MCBSP1
5705+#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5706+#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5707+
5708+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5709+ defined(CONFIG_ARCH_OMAP4)
5710+
5711+#define OMAP_MCBSP_REG_DRR2 0x00
5712+#define OMAP_MCBSP_REG_DRR1 0x04
5713+#define OMAP_MCBSP_REG_DXR2 0x08
5714+#define OMAP_MCBSP_REG_DXR1 0x0C
5715+#define OMAP_MCBSP_REG_DRR 0x00
5716+#define OMAP_MCBSP_REG_DXR 0x08
5717+#define OMAP_MCBSP_REG_SPCR2 0x10
5718+#define OMAP_MCBSP_REG_SPCR1 0x14
5719+#define OMAP_MCBSP_REG_RCR2 0x18
5720+#define OMAP_MCBSP_REG_RCR1 0x1C
5721+#define OMAP_MCBSP_REG_XCR2 0x20
5722+#define OMAP_MCBSP_REG_XCR1 0x24
5723+#define OMAP_MCBSP_REG_SRGR2 0x28
5724+#define OMAP_MCBSP_REG_SRGR1 0x2C
5725+#define OMAP_MCBSP_REG_MCR2 0x30
5726+#define OMAP_MCBSP_REG_MCR1 0x34
5727+#define OMAP_MCBSP_REG_RCERA 0x38
5728+#define OMAP_MCBSP_REG_RCERB 0x3C
5729+#define OMAP_MCBSP_REG_XCERA 0x40
5730+#define OMAP_MCBSP_REG_XCERB 0x44
5731+#define OMAP_MCBSP_REG_PCR0 0x48
5732+#define OMAP_MCBSP_REG_RCERC 0x4C
5733+#define OMAP_MCBSP_REG_RCERD 0x50
5734+#define OMAP_MCBSP_REG_XCERC 0x54
5735+#define OMAP_MCBSP_REG_XCERD 0x58
5736+#define OMAP_MCBSP_REG_RCERE 0x5C
5737+#define OMAP_MCBSP_REG_RCERF 0x60
5738+#define OMAP_MCBSP_REG_XCERE 0x64
5739+#define OMAP_MCBSP_REG_XCERF 0x68
5740+#define OMAP_MCBSP_REG_RCERG 0x6C
5741+#define OMAP_MCBSP_REG_RCERH 0x70
5742+#define OMAP_MCBSP_REG_XCERG 0x74
5743+#define OMAP_MCBSP_REG_XCERH 0x78
5744+#define OMAP_MCBSP_REG_SYSCON 0x8C
5745+#define OMAP_MCBSP_REG_THRSH2 0x90
5746+#define OMAP_MCBSP_REG_THRSH1 0x94
5747+#define OMAP_MCBSP_REG_IRQST 0xA0
5748+#define OMAP_MCBSP_REG_IRQEN 0xA4
5749+#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5750+#define OMAP_MCBSP_REG_XCCR 0xAC
5751+#define OMAP_MCBSP_REG_RCCR 0xB0
5752+
5753+#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5754+#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5755+
5756+#define AUDIO_MCBSP OMAP_MCBSP2
5757+#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5758+#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5759+
5760+#endif
5761+
5762+/************************** McBSP SPCR1 bit definitions ***********************/
5763+#define RRST 0x0001
5764+#define RRDY 0x0002
5765+#define RFULL 0x0004
5766+#define RSYNC_ERR 0x0008
5767+#define RINTM(value) ((value)<<4) /* bits 4:5 */
5768+#define ABIS 0x0040
5769+#define DXENA 0x0080
5770+#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5771+#define RJUST(value) ((value)<<13) /* bits 13:14 */
5772+#define ALB 0x8000
5773+#define DLB 0x8000
5774+
5775+/************************** McBSP SPCR2 bit definitions ***********************/
5776+#define XRST 0x0001
5777+#define XRDY 0x0002
5778+#define XEMPTY 0x0004
5779+#define XSYNC_ERR 0x0008
5780+#define XINTM(value) ((value)<<4) /* bits 4:5 */
5781+#define GRST 0x0040
5782+#define FRST 0x0080
5783+#define SOFT 0x0100
5784+#define FREE 0x0200
5785+
5786+/************************** McBSP PCR bit definitions *************************/
5787+#define CLKRP 0x0001
5788+#define CLKXP 0x0002
5789+#define FSRP 0x0004
5790+#define FSXP 0x0008
5791+#define DR_STAT 0x0010
5792+#define DX_STAT 0x0020
5793+#define CLKS_STAT 0x0040
5794+#define SCLKME 0x0080
5795+#define CLKRM 0x0100
5796+#define CLKXM 0x0200
5797+#define FSRM 0x0400
5798+#define FSXM 0x0800
5799+#define RIOEN 0x1000
5800+#define XIOEN 0x2000
5801+#define IDLE_EN 0x4000
5802+
5803+/************************** McBSP RCR1 bit definitions ************************/
5804+#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5805+#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5806+
5807+/************************** McBSP XCR1 bit definitions ************************/
5808+#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5809+#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5810+
5811+/*************************** McBSP RCR2 bit definitions ***********************/
5812+#define RDATDLY(value) (value) /* Bits 0:1 */
5813+#define RFIG 0x0004
5814+#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5815+#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5816+#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5817+#define RPHASE 0x8000
5818+
5819+/*************************** McBSP XCR2 bit definitions ***********************/
5820+#define XDATDLY(value) (value) /* Bits 0:1 */
5821+#define XFIG 0x0004
5822+#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5823+#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5824+#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5825+#define XPHASE 0x8000
5826+
5827+/************************* McBSP SRGR1 bit definitions ************************/
5828+#define CLKGDV(value) (value) /* Bits 0:7 */
5829+#define FWID(value) ((value)<<8) /* Bits 8:15 */
5830+
5831+/************************* McBSP SRGR2 bit definitions ************************/
5832+#define FPER(value) (value) /* Bits 0:11 */
5833+#define FSGM 0x1000
5834+#define CLKSM 0x2000
5835+#define CLKSP 0x4000
5836+#define GSYNC 0x8000
5837+
5838+/************************* McBSP MCR1 bit definitions *************************/
5839+#define RMCM 0x0001
5840+#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5841+#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5842+#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5843+
5844+/************************* McBSP MCR2 bit definitions *************************/
5845+#define XMCM(value) (value) /* Bits 0:1 */
5846+#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5847+#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5848+#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5849+
5850+/*********************** McBSP XCCR bit definitions *************************/
5851+#define EXTCLKGATE 0x8000
5852+#define PPCONNECT 0x4000
5853+#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5854+#define XFULL_CYCLE 0x0800
5855+#define DILB 0x0020
5856+#define XDMAEN 0x0008
5857+#define XDISABLE 0x0001
5858+
5859+/********************** McBSP RCCR bit definitions *************************/
5860+#define RFULL_CYCLE 0x0800
5861+#define RDMAEN 0x0008
5862+#define RDISABLE 0x0001
5863+
5864+/********************** McBSP SYSCONFIG bit definitions ********************/
5865+#define CLOCKACTIVITY(value) ((value)<<8)
5866+#define SIDLEMODE(value) ((value)<<3)
5867+#define ENAWAKEUP 0x0004
5868+#define SOFTRST 0x0002
5869+
5870+/********************** McBSP DMA operating modes **************************/
5871+#define MCBSP_DMA_MODE_ELEMENT 0
5872+#define MCBSP_DMA_MODE_THRESHOLD 1
5873+#define MCBSP_DMA_MODE_FRAME 2
5874+
5875+/********************** McBSP WAKEUPEN bit definitions *********************/
5876+#define XEMPTYEOFEN 0x4000
5877+#define XRDYEN 0x0400
5878+#define XEOFEN 0x0200
5879+#define XFSXEN 0x0100
5880+#define XSYNCERREN 0x0080
5881+#define RRDYEN 0x0008
5882+#define REOFEN 0x0004
5883+#define RFSREN 0x0002
5884+#define RSYNCERREN 0x0001
5885+
5886+/* we don't do multichannel for now */
5887+struct omap_mcbsp_reg_cfg {
5888+ u16 spcr2;
5889+ u16 spcr1;
5890+ u16 rcr2;
5891+ u16 rcr1;
5892+ u16 xcr2;
5893+ u16 xcr1;
5894+ u16 srgr2;
5895+ u16 srgr1;
5896+ u16 mcr2;
5897+ u16 mcr1;
5898+ u16 pcr0;
5899+ u16 rcerc;
5900+ u16 rcerd;
5901+ u16 xcerc;
5902+ u16 xcerd;
5903+ u16 rcere;
5904+ u16 rcerf;
5905+ u16 xcere;
5906+ u16 xcerf;
5907+ u16 rcerg;
5908+ u16 rcerh;
5909+ u16 xcerg;
5910+ u16 xcerh;
5911+ u16 xccr;
5912+ u16 rccr;
5913+};
5914+
5915+typedef enum {
5916+ OMAP_MCBSP1 = 0,
5917+ OMAP_MCBSP2,
5918+ OMAP_MCBSP3,
5919+ OMAP_MCBSP4,
5920+ OMAP_MCBSP5
5921+} omap_mcbsp_id;
5922+
5923+typedef int __bitwise omap_mcbsp_io_type_t;
5924+#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
5925+#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
5926+
5927+typedef enum {
5928+ OMAP_MCBSP_WORD_8 = 0,
5929+ OMAP_MCBSP_WORD_12,
5930+ OMAP_MCBSP_WORD_16,
5931+ OMAP_MCBSP_WORD_20,
5932+ OMAP_MCBSP_WORD_24,
5933+ OMAP_MCBSP_WORD_32,
5934+} omap_mcbsp_word_length;
5935+
5936+typedef enum {
5937+ OMAP_MCBSP_CLK_RISING = 0,
5938+ OMAP_MCBSP_CLK_FALLING,
5939+} omap_mcbsp_clk_polarity;
5940+
5941+typedef enum {
5942+ OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
5943+ OMAP_MCBSP_FS_ACTIVE_LOW,
5944+} omap_mcbsp_fs_polarity;
5945+
5946+typedef enum {
5947+ OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
5948+ OMAP_MCBSP_CLK_STP_MODE_DELAY,
5949+} omap_mcbsp_clk_stp_mode;
5950+
5951+
5952+/******* SPI specific mode **********/
5953+typedef enum {
5954+ OMAP_MCBSP_SPI_MASTER = 0,
5955+ OMAP_MCBSP_SPI_SLAVE,
5956+} omap_mcbsp_spi_mode;
5957+
5958+struct omap_mcbsp_spi_cfg {
5959+ omap_mcbsp_spi_mode spi_mode;
5960+ omap_mcbsp_clk_polarity rx_clock_polarity;
5961+ omap_mcbsp_clk_polarity tx_clock_polarity;
5962+ omap_mcbsp_fs_polarity fsx_polarity;
5963+ u8 clk_div;
5964+ omap_mcbsp_clk_stp_mode clk_stp_mode;
5965+ omap_mcbsp_word_length word_length;
5966+};
5967+
5968+/* Platform specific configuration */
5969+struct omap_mcbsp_ops {
5970+ void (*request)(unsigned int);
5971+ void (*free)(unsigned int);
5972+};
5973+
5974+struct omap_mcbsp_platform_data {
5975+ unsigned long phys_base;
5976+ u8 dma_rx_sync, dma_tx_sync;
5977+ u16 rx_irq, tx_irq;
5978+ struct omap_mcbsp_ops *ops;
5979+#ifdef CONFIG_ARCH_OMAP34XX
5980+ u16 buffer_size;
5981+#endif
5982+};
5983+
5984+struct omap_mcbsp {
5985+ struct device *dev;
5986+ unsigned long phys_base;
5987+ void __iomem *io_base;
5988+ u8 id;
5989+ u8 free;
5990+ omap_mcbsp_word_length rx_word_length;
5991+ omap_mcbsp_word_length tx_word_length;
5992+
5993+ omap_mcbsp_io_type_t io_type; /* IRQ or poll */
5994+ /* IRQ based TX/RX */
5995+ int rx_irq;
5996+ int tx_irq;
5997+
5998+ /* DMA stuff */
5999+ u8 dma_rx_sync;
6000+ short dma_rx_lch;
6001+ u8 dma_tx_sync;
6002+ short dma_tx_lch;
6003+
6004+ /* Completion queues */
6005+ struct completion tx_irq_completion;
6006+ struct completion rx_irq_completion;
6007+ struct completion tx_dma_completion;
6008+ struct completion rx_dma_completion;
6009+
6010+ /* Protect the field .free, while checking if the mcbsp is in use */
6011+ spinlock_t lock;
6012+ struct omap_mcbsp_platform_data *pdata;
6013+ struct clk *iclk;
6014+ struct clk *fclk;
6015+#ifdef CONFIG_ARCH_OMAP34XX
6016+ int dma_op_mode;
6017+ u16 max_tx_thres;
6018+ u16 max_rx_thres;
6019+#endif
6020+};
6021+extern struct omap_mcbsp **mcbsp_ptr;
6022+extern int omap_mcbsp_count;
6023+
6024+int omap_mcbsp_init(void);
6025+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6026+ int size);
6027+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6028+#ifdef CONFIG_ARCH_OMAP34XX
6029+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6030+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6031+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6032+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6033+int omap_mcbsp_get_dma_op_mode(unsigned int id);
6034+#else
6035+static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6036+{ }
6037+static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6038+{ }
6039+static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6040+static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6041+static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6042+#endif
6043+int omap_mcbsp_request(unsigned int id);
6044+void omap_mcbsp_free(unsigned int id);
6045+void omap_mcbsp_start(unsigned int id, int tx, int rx);
6046+void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6047+void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6048+u32 omap_mcbsp_recv_word(unsigned int id);
6049+
6050+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6051+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6052+int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6053+int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6054+
6055+
6056+/* SPI specific API */
6057+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6058+
6059+/* Polled read/write functions */
6060+int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6061+int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6062+int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6063+
6064+#endif
6065Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcspi.h
6066===================================================================
6067--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6068@@ -0,0 +1,15 @@
6069+#ifndef _OMAP2_MCSPI_H
6070+#define _OMAP2_MCSPI_H
6071+
6072+struct omap2_mcspi_platform_config {
6073+ unsigned short num_cs;
6074+};
6075+
6076+struct omap2_mcspi_device_config {
6077+ unsigned turbo_mode:1;
6078+
6079+ /* Do we want one channel enabled at the same time? */
6080+ unsigned single_channel:1;
6081+};
6082+
6083+#endif
6084Index: linux-2.6.35/arch/arm/plat-omap/include/mach/memory.h
6085===================================================================
6086--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6087@@ -0,0 +1,103 @@
6088+/*
6089+ * arch/arm/plat-omap/include/mach/memory.h
6090+ *
6091+ * Memory map for OMAP-1510 and 1610
6092+ *
6093+ * Copyright (C) 2000 RidgeRun, Inc.
6094+ * Author: Greg Lonnon <glonnon@ridgerun.com>
6095+ *
6096+ * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6097+ * Copyright (C) 1999 ARM Limited
6098+ *
6099+ * This program is free software; you can redistribute it and/or modify it
6100+ * under the terms of the GNU General Public License as published by the
6101+ * Free Software Foundation; either version 2 of the License, or (at your
6102+ * option) any later version.
6103+ *
6104+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6105+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6106+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6107+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6108+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6109+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6110+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6111+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6112+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6113+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6114+ *
6115+ * You should have received a copy of the GNU General Public License along
6116+ * with this program; if not, write to the Free Software Foundation, Inc.,
6117+ * 675 Mass Ave, Cambridge, MA 02139, USA.
6118+ */
6119+
6120+#ifndef __ASM_ARCH_MEMORY_H
6121+#define __ASM_ARCH_MEMORY_H
6122+
6123+/*
6124+ * Physical DRAM offset.
6125+ */
6126+#if defined(CONFIG_ARCH_OMAP1)
6127+#define PHYS_OFFSET UL(0x10000000)
6128+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6129+ defined(CONFIG_ARCH_OMAP4)
6130+#define PHYS_OFFSET UL(0x80000000)
6131+#endif
6132+
6133+/*
6134+ * Bus address is physical address, except for OMAP-1510 Local Bus.
6135+ * OMAP-1510 bus address is translated into a Local Bus address if the
6136+ * OMAP bus type is lbus. We do the address translation based on the
6137+ * device overriding the defaults used in the dma-mapping API.
6138+ * Note that the is_lbus_device() test is not very efficient on 1510
6139+ * because of the strncmp().
6140+ */
6141+#ifdef CONFIG_ARCH_OMAP15XX
6142+
6143+/*
6144+ * OMAP-1510 Local Bus address offset
6145+ */
6146+#define OMAP1510_LB_OFFSET UL(0x30000000)
6147+
6148+#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6149+#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6150+#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6151+
6152+#define __arch_page_to_dma(dev, page) \
6153+ ({ dma_addr_t __dma = page_to_phys(page); \
6154+ if (is_lbus_device(dev)) \
6155+ __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6156+ __dma; })
6157+
6158+#define __arch_dma_to_page(dev, addr) \
6159+ ({ dma_addr_t __dma = addr; \
6160+ if (is_lbus_device(dev)) \
6161+ __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6162+ phys_to_page(__dma); \
6163+ })
6164+
6165+#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6166+ lbus_to_virt(addr) : \
6167+ __phys_to_virt(addr)); })
6168+
6169+#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6170+ (dma_addr_t) (is_lbus_device(dev) ? \
6171+ virt_to_lbus(__addr) : \
6172+ __virt_to_phys(__addr)); })
6173+
6174+#endif /* CONFIG_ARCH_OMAP15XX */
6175+
6176+/* Override the ARM default */
6177+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6178+
6179+#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6180+#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6181+#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6182+#endif
6183+
6184+#define CONSISTENT_DMA_SIZE \
6185+ (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6186+
6187+#endif
6188+
6189+#endif
6190+
6191Index: linux-2.6.35/arch/arm/plat-omap/include/mach/menelaus.h
6192===================================================================
6193--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6194@@ -0,0 +1,49 @@
6195+/*
6196+ * arch/arm/plat-omap/include/mach/menelaus.h
6197+ *
6198+ * Functions to access Menelaus power management chip
6199+ */
6200+
6201+#ifndef __ASM_ARCH_MENELAUS_H
6202+#define __ASM_ARCH_MENELAUS_H
6203+
6204+struct device;
6205+
6206+struct menelaus_platform_data {
6207+ int (* late_init)(struct device *dev);
6208+};
6209+
6210+extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6211+ void *data);
6212+extern void menelaus_unregister_mmc_callback(void);
6213+extern int menelaus_set_mmc_opendrain(int slot, int enable);
6214+extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6215+
6216+extern int menelaus_set_vmem(unsigned int mV);
6217+extern int menelaus_set_vio(unsigned int mV);
6218+extern int menelaus_set_vmmc(unsigned int mV);
6219+extern int menelaus_set_vaux(unsigned int mV);
6220+extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6221+extern int menelaus_set_slot_sel(int enable);
6222+extern int menelaus_get_slot_pin_states(void);
6223+extern int menelaus_set_vcore_sw(unsigned int mV);
6224+extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6225+
6226+#define EN_VPLL_SLEEP (1 << 7)
6227+#define EN_VMMC_SLEEP (1 << 6)
6228+#define EN_VAUX_SLEEP (1 << 5)
6229+#define EN_VIO_SLEEP (1 << 4)
6230+#define EN_VMEM_SLEEP (1 << 3)
6231+#define EN_DC3_SLEEP (1 << 2)
6232+#define EN_DC2_SLEEP (1 << 1)
6233+#define EN_VC_SLEEP (1 << 0)
6234+
6235+extern int menelaus_set_regulator_sleep(int enable, u32 val);
6236+
6237+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6238+#define omap_has_menelaus() 1
6239+#else
6240+#define omap_has_menelaus() 0
6241+#endif
6242+
6243+#endif
6244Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mmc.h
6245===================================================================
6246--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6247@@ -0,0 +1,157 @@
6248+/*
6249+ * MMC definitions for OMAP2
6250+ *
6251+ * Copyright (C) 2006 Nokia Corporatio