| target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c |
|---|
| 101 | 101 | |
| 102 | 102 | #define JZ_MMC_CLK_RATE 24000000 |
| 103 | 103 | |
| 104 | #define JZ4740_MMC_MAX_TIMEOUT 10000000 |
| 105 | |
| 104 | 106 | struct jz4740_mmc_host { |
| 105 | 107 | struct mmc_host *mmc; |
| 106 | 108 | struct platform_device *pdev; |
| ... | ... | |
| 212 | 214 | j = i >> 3; |
| 213 | 215 | i = i & 0x7; |
| 214 | 216 | while (j) { |
| 215 | | timeout = 100000; |
| 217 | timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 216 | 218 | do { |
| 217 | 219 | status = readw(host->base + JZ_REG_MMC_IREG); |
| 218 | 220 | } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout); |
| 219 | | if (timeout == 0) |
| 221 | if (unlikely(timeout == 0)) |
| 220 | 222 | goto err_timeout; |
| 221 | 223 | |
| 222 | 224 | writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG); |
| ... | ... | |
| 233 | 235 | --j; |
| 234 | 236 | } |
| 235 | 237 | if (i) { |
| 236 | | timeout = 100000; |
| 238 | timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 237 | 239 | do { |
| 238 | 240 | status = readw(host->base + JZ_REG_MMC_IREG); |
| 239 | 241 | } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout); |
| 240 | | if (timeout == 0) |
| 242 | if (unlikely(timeout == 0)) |
| 241 | 243 | goto err_timeout; |
| 242 | 244 | |
| 243 | 245 | writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG); |
| ... | ... | |
| 256 | 258 | goto err; |
| 257 | 259 | |
| 258 | 260 | writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG); |
| 259 | | timeout = 100000; |
| 261 | timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 260 | 262 | do { |
| 261 | 263 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 262 | 264 | } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout); |
| 263 | | if (timeout == 0) |
| 265 | |
| 266 | if (unlikely(timeout == 0)) |
| 264 | 267 | goto err_timeout; |
| 265 | 268 | writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); |
| 266 | 269 | |
| ... | ... | |
| 312 | 315 | j = i >> 5; |
| 313 | 316 | i = i & 0x1f; |
| 314 | 317 | while (j) { |
| 315 | | timeout = 100000; |
| 318 | timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 316 | 319 | do { |
| 317 | 320 | status = readw(host->base + JZ_REG_MMC_IREG); |
| 318 | 321 | } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ) && --timeout); |
| ... | ... | |
| 336 | 339 | } |
| 337 | 340 | |
| 338 | 341 | while (i >= 4) { |
| 339 | | timeout = 100000; |
| 342 | timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 340 | 343 | do { |
| 341 | 344 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 342 | 345 | } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout); |
| ... | ... | |
| 416 | 419 | writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); |
| 417 | 420 | } |
| 418 | 421 | |
| 422 | |
| 419 | 423 | if (irq_reg & JZ_MMC_IRQ_SDIO) { |
| 420 | 424 | writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); |
| 421 | 425 | mmc_signal_sdio_irq(host->mmc); |
| ... | ... | |
| 466 | 470 | |
| 467 | 471 | static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) { |
| 468 | 472 | int div = 0; |
| 469 | | int real_rate = host->max_clock; |
| 473 | int real_rate; |
| 474 | |
| 470 | 475 | jz4740_mmc_clock_disable(host); |
| 476 | clk_set_rate(host->clk, JZ_MMC_CLK_RATE); |
| 477 | |
| 478 | real_rate = clk_get_rate(host->clk); |
| 471 | 479 | |
| 472 | | while ((real_rate >> 1) >= rate && div < 7) { |
| 480 | while (real_rate > rate && div < 7) { |
| 473 | 481 | ++div; |
| 474 | 482 | real_rate >>= 1; |
| 475 | 483 | } |
| 476 | | clk_set_rate(host->clk, JZ_MMC_CLK_RATE); |
| 477 | 484 | |
| 478 | 485 | writew(div, host->base + JZ_REG_MMC_CLKRT); |
| 479 | 486 | return real_rate; |
| ... | ... | |
| 543 | 550 | |
| 544 | 551 | host->waiting = 1; |
| 545 | 552 | jz4740_mmc_clock_enable(host, 1); |
| 546 | | mod_timer(&host->timeout_timer, 4*HZ); |
| 553 | mod_timer(&host->timeout_timer, jiffies + 5*HZ); |
| 547 | 554 | } |
| 548 | 555 | |
| 549 | 556 | static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host) |
| ... | ... | |
| 551 | 558 | uint32_t status; |
| 552 | 559 | struct mmc_command *cmd = host->req->cmd; |
| 553 | 560 | struct mmc_request *req = host->req; |
| 554 | | unsigned int timeout = 100000; |
| 555 | | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 561 | unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT; |
| 556 | 562 | |
| 557 | 563 | if (cmd->flags & MMC_RSP_PRESENT) |
| 558 | 564 | jz4740_mmc_read_response(host, cmd); |
| ... | ... | |
| 567 | 573 | if (req->stop) { |
| 568 | 574 | jz4740_mmc_send_command(host, req->stop); |
| 569 | 575 | do { |
| 570 | | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 571 | | } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0 && --timeout); |
| 576 | status = readw(host->base + JZ_REG_MMC_IREG); |
| 577 | } while ((status & JZ_MMC_IRQ_PRG_DONE) == 0 && --timeout); |
| 572 | 578 | writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG); |
| 573 | 579 | } |
| 574 | 580 | |
| 575 | | if (timeout == 0) |
| 581 | if (unlikely(timeout == 0)) |
| 576 | 582 | req->stop->error = -ETIMEDOUT; |
| 577 | 583 | |
| 578 | 584 | jz4740_mmc_request_done(host); |
