Date:2010-10-29 05:53:42 (9 years 8 months ago)
Author:Xiangfu Liu
Commit:a510aa32acf2db7519028511cc931319cfbe62c8
Message:[uboot-xburst] move lcd init more early

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
Files: package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c (1 diff)
package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h (4 diffs)
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile (3 diffs)
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c (12 diffs)

Change Details

package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c
7878
7979void lcd_ctrl_init (void *lcdbase)
8080{
81    __lcd_display_pin_init();
82
8381    jz_lcd_init_mem(lcdbase, &panel_info);
8482    jz_lcd_desc_init(&panel_info);
8583    jz_lcd_hw_init(&panel_info);
86
87    __lcd_display_on() ;
8884}
8985
9086/*
package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h
2222#ifndef __QI_LB60_GPM940B0_H__
2323#define __QI_LB60_GPM940B0_H__
2424
25#include <asm/io.h>
26
2725struct lcd_desc{
2826    unsigned int next_desc; /* LCDDAx */
2927    unsigned int databuf; /* LCDSAx */
...... 
9896    __gpio_set_pin(SPCK); \
9997    __gpio_clear_pin(SPDA); \
10098    __gpio_clear_pin(SPEN); \
101    udelay(25); \
10299    value=((a<<8)|(b&0xFF)); \
103100    for(no=0;no<16;no++) \
104101    { \
...... 
107104            __gpio_set_pin(SPDA); \
108105        else \
109106            __gpio_clear_pin(SPDA); \
110        udelay(25); \
111107        __gpio_set_pin(SPCK); \
112108        value=(value<<1); \
113        udelay(25); \
114109    } \
115110    __gpio_set_pin(SPEN); \
116    udelay(100); \
117111} while (0)
118112
119113#define __lcd_display_pin_init() \
...... 
127121#define __lcd_display_on() \
128122do { \
129123    __spi_write_reg1(0x05, 0x1e); \
130    __spi_write_reg1(0x05, 0xc6); \
124    __spi_write_reg1(0x05, 0x5e); \
131125    __spi_write_reg1(0x07, 0x8d); \
132126    __spi_write_reg1(0x13, 0x01); \
133    __spi_write_reg1(0x05, 0xc7); \
127    __spi_write_reg1(0x05, 0x5f); \
134128} while (0)
135129
136130#define __lcd_display_off() \
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile
6161        -o $(nandobj)u-boot-spl
6262
6363# create symbolic links for common files
64
65# from cpu directory
6664$(obj)start.S:
6765    @rm -f $(obj)start.S
6866    ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
...... 
8381    @rm -f $(obj)jz_serial.c
8482    ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
8583
86# from nand_spl directory
8784$(obj)nand_boot_jz4740.c:
8885    @rm -f $(obj)nand_boot_jz4740.c
8986    ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
90
91#########################################################################
87    ln -s $(SRCTREE)/drivers/video/nanonote_gpm940b0.h $(obj)nanonote_gpm940b0.h
9288
9389$(obj)%.o: $(obj)%.S
9490    $(CC) $(AFLAGS) -c -o $@ $<
...... 
9692$(obj)%.o: $(obj)%.c
9793    $(CC) $(CFLAGS) -c -o $@ $<
9894
99# defines $(obj).depend target
10095include $(SRCTREE)/rules.mk
10196
10297sinclude $(obj).depend
103
104#########################################################################
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
2121#include <common.h>
2222#include <nand.h>
2323
24#include <asm/io.h>
2524#include <asm/jz4740.h>
25#include "nanonote_gpm940b0.h"
2626
2727#define KEY_U_OUT (32 * 2 + 16)
2828#define KEY_U_IN (32 * 3 + 19)
...... 
3030/*
3131 * NAND flash definitions
3232 */
33
3433#define NAND_DATAPORT 0xb8000000
3534#define NAND_ADDRPORT 0xb8010000
3635#define NAND_COMMPORT 0xb8008000
3736
38#define ECC_BLOCK 512
39#define ECC_POS 6
40#define PAR_SIZE 9
41
4237#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
4338#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
4439#define __nand_ecc_rs_encoding() \
...... 
4843#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
4944#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
5045#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
51
52static inline void __nand_dev_ready(void)
53{
54    unsigned int timeout = 10000;
55    while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
56    while (!(REG_GPIO_PXPIN(2) & 0x40000000));
57}
58
5946#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
6047#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
6148#define __nand_data8() REG8(NAND_DATAPORT)
...... 
7562    #define NAND_ROW_CYCLE 2
7663#endif
7764
65static inline void __nand_dev_ready(void)
66{
67    unsigned int timeout = 10000;
68    while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
69    while (!(REG_GPIO_PXPIN(2) & 0x40000000));
70}
71
7872/*
7973 * NAND flash parameters
8074 */
...... 
8478static int page_per_block = 64;
8579static int bad_block_pos = 0;
8680static int block_size = 131072;
87
8881static unsigned char oob_buf[128] = {0};
8982
9083/*
...... 
198191    /*
199192     * Read page data
200193     */
201
202194    /* Send READ0 command */
203195    __nand_cmd(NAND_CMD_READ0);
204196
...... 
233225        __nand_ecc_rs_decoding();
234226
235227        /* Read data */
236        nand_read_buf((void *)tmpbuf, ECC_BLOCK);
228        nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE);
237229
238230        /* Set PAR values */
239        for (j = 0; j < PAR_SIZE; j++) {
240#if defined(CONFIG_SYS_NAND_ECC_POS)
241            *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
242#else
243            *paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
244#endif
245        }
231        for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++)
232            *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j];
246233
247234        /* Set PRDY */
248235        REG_EMC_NFECR |= EMC_NFECR_PRDY;
...... 
257244        stat = REG_EMC_NFINTS;
258245        if (stat & EMC_NFINTS_ERR) {
259246            /* Error occurred */
260            /* serial_puts("\n Error occurred\n"); */
247            /* serial_puts("Error occurred\n"); */
261248            if (stat & EMC_NFINTS_UNCOR) {
262249                /* Uncorrectable error occurred */
263                /* serial_puts("\nUncorrectable error occurred\n"); */
264            }
265            else {
250                /* serial_puts("Uncorrectable error occurred\n"); */
251            } else {
266252                unsigned int errcnt, index, mask;
267253
268254                errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
...... 
292278                }
293279            }
294280        }
295
296        tmpbuf += ECC_BLOCK;
281        tmpbuf += CONFIG_SYS_NAND_ECCSIZE;
297282    }
298283
299284    return 0;
...... 
342327    /*
343328     * Initialize SDRAM pins
344329     */
345    __gpio_as_sdram_32bit();
330    __gpio_as_sdram_16bit_4720();
346331
347332    /*
348333     * Initialize UART0 pins
349334     */
350335    __gpio_as_uart0();
351
352336    __gpio_jtag_to_uart0();
353337}
354338
...... 
375359    gpio_init();
376360    pll_init();
377361
362    __lcd_display_pin_init();
363    __lcd_display_on() ;
364
378365    serial_init();
379366    sdram_init();
380367    jz_nand_init();
...... 
392379    page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
393380    bad_block_pos = (page_size == 512) ? 5 : 0;
394381    oob_size = page_size / 32;
395    ecc_count = page_size / ECC_BLOCK;
382    ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE;
396383
397384    /*
398385     * Load U-Boot image from NAND into RAM

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