Date:2010-01-08 03:35:29 (3 years 4 months ago)
Author:Lars C.
Commit:a6402204c8f2bf4d89be9d9df29373ac582d0f12
Message:uboot: provide a working usbboot mode
Files: target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch (13 diffs)

Change Details

target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch
72067206index 0000000..6c3788f
72077207--- /dev/null
72087208+++ b/cpu/mips/usb_boot.S
7209@@ -0,0 +1,821 @@
7209@@ -0,0 +1,880 @@
72107210+/*
72117211+ * for jz4740 usb boot
72127212+ *
...... 
72407240+// So init caches first and then dispatch to a proper boot routine.
72417241+//----------------------------------------------------------------------
72427242+
7243+.macro load_addr reg addr
7244+ li \reg, 0x80000000
7245+ addiu \reg, \reg, \addr
7246+ la $2, usbboot_begin
7247+ subu \reg, \reg, $2
7248+.endm
7249+
7250+usb_boot:
7251+ //--------------------------------------------------------------
7252+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
7253+ //--------------------------------------------------------------
7254+ la $9, 0xB0000000 // CPCCR: Clock Control Register
7255+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
7256+ sw $8, 0($9)
7257+
7258+ la $9, 0xB0000010 // CPPCR: PLL Control Register
7259+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
7260+ sw $8, 0($9)
7261+
7262+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
7263+ nop
7264+
7265+ mtc0 $0, $16 // CP0_CONFIG
7266+ nop
7267+
7268+ // Relocate code to beginning of the ram
7269+
7270+ la $2, usbboot_begin
7271+ la $3, usbboot_end
7272+ li $4, 0x80000000
7273+
7274+1:
7275+ lw $5, 0($2)
7276+ sw $5, 0($4)
7277+ addiu $2, $2, 4
7278+ bne $2, $3, 1b
7279+ addiu $4, $4, 4
7280+
7281+ li $2, 0x80000000
7282+ ori $3, $2, 0
7283+ addiu $3, $3, usbboot_end
7284+ la $4, usbboot_begin
7285+ subu $3, $3, $4
7286+
7287+
7288+2:
7289+ cache 0x0, 0($2) // Index_Invalidate_I
7290+ cache 0x1, 0($2) // Index_Writeback_Inv_D
7291+ addiu $2, $2, 32
7292+ subu $4, $3, $2
7293+ bgtz $4, 2b
7294+ nop
7295+
7296+ load_addr $3, usb_boot_return
7297+
7298+ jr $3
7299+
7300+usbboot_begin:
7301+
72437302+init_caches:
72447303+ li $2, 3 // cacheable for kseg0 access
72457304+ mtc0 $2, $16 // CP0_CONFIG
...... 
72827341+ // $20: jump target address
72837342+ //--------------------------------------------------------------
72847343+xfer_d2i:
7285+ ori $2, $28, 0 // start address
7286+ add $3, $2, $19 // end addres
7287+ addiu $3, $3, -4
72887344+
7289+xfer_a_word:
7290+ lw $4, 0($2)
7291+ mtc0 $4, $28, 1 // CP0_DATALO
7292+ cache 0xc, 0($2) // Index_Store_Data_I
7293+ bne $2, $3, xfer_a_word
7294+ addiu $2, $2, 4
7345+ ori $8, $20, 0
7346+ addu $9, $8, $19 // total 16KB
72957347+
7296+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
7348+1:
7349+ cache 0x0, 0($8) // Index_Invalidate_I
7350+ cache 0x1, 0($8) // Index_Writeback_Inv_D
7351+ bne $8, $9, 1b
7352+ addiu $8, $8, 32
72977353+
7298+ jalr $20 // jump, and place the return address in $31
7354+ // flush write-buffer
7355+ sync
7356+
7357+ // Invalidate BTB
7358+ mfc0 $8, $16, 7 // CP0_CONFIG
7359+ nop
7360+ ori $8, 2
7361+ mtc0 $8, $16, 7
7362+ nop
7363+
7364+ // Overwrite config to disable ram initalisation
7365+ li $2, 0xff
7366+ sb $2, 20($20)
7367+
7368+ jalr $20
72997369+ nop
73007370+
73017371+icache_return:
...... 
73077377+ nop
73087378+
73097379+
7310+usb_boot:
7311+ //--------------------------------------------------------------
7312+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
7313+ //--------------------------------------------------------------
7314+ la $9, 0xB0000000 // CPCCR: Clock Control Register
7315+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
7316+ sw $8, 0($9)
7317+
7318+ la $9, 0xB0000010 // CPPCR: PLL Control Register
7319+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
7320+ sw $8, 0($9)
7321+
73227380+usb_boot_return:
73237381+ //--------------------------------------------------------------
73247382+ // Enable the USB PHY
...... 
73857443+
73867444+ //--------------------------------------------------------------
73877445+ // 2. Check and handle EP0 interrupt
7388+ //--------------------------------------------------------------
7446+ //--------------------------------------------------------------
73897447+check_intr_ep0in:
73907448+ lhu $10, 0x02($27) // read INTRIN
73917449+ andi $9, $10, 0x1 // check EP0 interrupt
...... 
74607518+ nop
74617519+
74627520+__ep0_get_cpu_info:
7463+ la $20, cpu_info_data // data pointer to transfer
7521+ load_addr $20, cpu_info_data // data pointer to transfer
74647522+ li $21, 8 // bytes left to transfer
74657523+ li $22, 1 // set EP0 to TX state
74667524+ li $23, 0 // NoData = 0
...... 
75247582+ or $20, $9, $8 // target address
75257583+
75267584+ b xfer_d2i
7527+ li $19, 0x4000 // 16KB data length
7585+ li $19, 0x2000 // 16KB data length
75287586+
75297587+__ep0_prog_start2:
75307588+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
...... 
76007658+ nop
76017659+
76027660+___ep0_get_dev_desc:
7603+ la $20, device_desc // data pointer
7661+ load_addr $20, device_desc // data pointer
76047662+ li $22, 1 // set EP0 to TX state
76057663+ sub $8, $21, 18
76067664+ blez $8, _ep0_idle_state_fini // wLength <= 18
...... 
76107668+ nop
76117669+
76127670+___ep0_get_dev_qualifier:
7613+ la $20, dev_qualifier // data pointer
7671+ load_addr $20, dev_qualifier // data pointer
76147672+ li $22, 1 // set EP0 to TX state
76157673+ sub $8, $21, 10
76167674+ blez $8, _ep0_idle_state_fini // wLength <= 10
...... 
76207678+ nop
76217679+
76227680+___ep0_get_conf_desc:
7623+ la $20, config_desc_fs // data pointer of FS mode
7681+ load_addr $20, config_desc_fs // data pointer of FS mode
76247682+ lbu $8, 0x01($27) // read POWER
76257683+ andi $8, 0x10 // test HS_MODE
76267684+ beqz $8, ___ep0_get_conf_desc2
76277685+ nop
7628+ la $20, config_desc_hs // data pointer of HS mode
7686+ load_addr $20, config_desc_hs // data pointer of HS mode
76297687+
76307688+___ep0_get_conf_desc2:
76317689+ li $22, 1 // set EP0 to TX state
...... 
76497707+ nop
76507708+
76517709+___ep0_get_string_lang_ids:
7652+ la $20, string_lang_ids // data pointer
7710+ load_addr $20, string_lang_ids // data pointer
76537711+ b _ep0_idle_state_fini
76547712+ li $21, 4 // data length
76557713+
76567714+___ep0_get_string_manufacture:
7657+ la $20, string_manufacture // data pointer
7715+ load_addr $20, string_manufacture // data pointer
76587716+ b _ep0_idle_state_fini
76597717+ li $21, 16 // data length
76607718+
76617719+___ep0_get_string_product:
7662+ la $20, string_product // data pointer
7720+ load_addr $20, string_product // data pointer
76637721+ b _ep0_idle_state_fini
76647722+ li $21, 46 // data length
76657723+
...... 
76757733+
76767734+ //--------------------------------------------------------------
76777735+ // 2.2 Handle EP0 TX state interrupt
7678+ //--------------------------------------------------------------
7679+ep0_tx_state:
7736+ //--------------------------------------------------------------
7737+ep0_tx_state:
76807738+ sub $9, $22, 1
76817739+ bnez $9, check_intr_ep1in
76827740+ nop
...... 
80268084+ .byte 0x30
80278085+ .byte 0x56
80288086+ .byte 0x31
8087+usbboot_end:
80298088+
80308089+ .set reorder
80318090diff --git a/include/asm-mips/jz4740.h b/include/asm-mips/jz4740.h

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