Date:2012-10-10 18:18:01 (1 year 6 months ago)
Author:Xiangfu
Commit:af862e9a69ccfc2363bc94b44b06490494cf87b7
Message:uboot-xburst: update to v2012.10-rc2

Files: package/uboot-xburst/Makefile (4 diffs)
package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/cache.S (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/config.mk (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/cpu.c (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/interrupts.c (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/jz4740.c (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/jz_serial.c (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/start.S (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/start_spl.S (1 diff)
package/uboot-xburst/files/arch/mips/cpu/xburst/usbboot.S (1 diff)
package/uboot-xburst/files/arch/mips/include/asm/jz4740.h (1 diff)
package/uboot-xburst/files/board/xburst/n516/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/n516/config.mk (1 diff)
package/uboot-xburst/files/board/xburst/n516/flash.c (1 diff)
package/uboot-xburst/files/board/xburst/n516/n516.c (1 diff)
package/uboot-xburst/files/board/xburst/n516/u-boot-nand.lds (1 diff)
package/uboot-xburst/files/board/xburst/n516/u-boot.lds (1 diff)
package/uboot-xburst/files/board/xburst/nanonote/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/nanonote/config.mk (1 diff)
package/uboot-xburst/files/board/xburst/nanonote/nanonote.c (1 diff)
package/uboot-xburst/files/board/xburst/nanonote/u-boot-nand.lds (1 diff)
package/uboot-xburst/files/board/xburst/nanonote/u-boot.lds (1 diff)
package/uboot-xburst/files/board/xburst/sakc/Makefile (1 diff)
package/uboot-xburst/files/board/xburst/sakc/config.mk (1 diff)
package/uboot-xburst/files/board/xburst/sakc/sakc.c (1 diff)
package/uboot-xburst/files/board/xburst/sakc/u-boot-nand.lds (1 diff)
package/uboot-xburst/files/board/xburst/sakc/u-boot.lds (1 diff)
package/uboot-xburst/files/drivers/mmc/jz_mmc.c (1 diff)
package/uboot-xburst/files/drivers/mmc/jz_mmc.h (1 diff)
package/uboot-xburst/files/drivers/mtd/nand/jz4740_nand.c (1 diff)
package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c (1 diff)
package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h (1 diff)
package/uboot-xburst/files/include/configs/n516.h (1 diff)
package/uboot-xburst/files/include/configs/nanonote.h (1 diff)
package/uboot-xburst/files/include/configs/qi_lb60.h (1 diff)
package/uboot-xburst/files/include/configs/sakc.h (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/n516/Makefile (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/n516/config.mk (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/n516/u-boot.lds (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/config.mk (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/u-boot.lds (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/sakc/Makefile (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/sakc/config.mk (1 diff)
package/uboot-xburst/files/nand_spl/board/xburst/sakc/u-boot.lds (1 diff)
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c (1 diff)
package/uboot-xburst/patches/0001-add-qi_lb60-spl-code-and-usbboot-code.patch (1 diff)
package/uboot-xburst/patches/0002-add-mmc-support.patch (1 diff)
package/uboot-xburst/patches/0003-add-more-boot-options-F1-F2-F3-F4-M-S.patch (1 diff)
package/uboot-xburst/patches/0004-add-nanonote-lcd-support.patch (1 diff)
package/uboot-xburst/patches/0005-enable-silent-console.patch (1 diff)
package/uboot-xburst/patches/001-xburst.patch (1 diff)
package/uboot-xburst/patches/009-add-n516.patch (1 diff)
package/uboot-xburst/patches/010-add-sakc.patch (1 diff)
package/uboot-xburst/patches/100-fix-c_size.patch (1 diff)
package/uboot-xburst/patches/200-add-more-boot-option.patch (1 diff)
package/uboot-xburst/patches/300-add-ubifs-support.patch (1 diff)
package/uboot-xburst/patches/310-enable-silent-console.patch (1 diff)
package/uboot-xburst/patches/400-change-load-kernel-size.patch (1 diff)

Change Details

package/uboot-xburst/Makefile
99include $(INCLUDE_DIR)/kernel.mk
1010
1111PKG_NAME:=u-boot
12PKG_VERSION:=2010.06
12PKG_VERSION:=2012.10-rc2
1313PKG_RELEASE:=1
1414
1515PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
16PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
16PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
1717PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
1818PKG_MD5SUM:=
1919PKG_TARGETS:=bin
...... 
3030  TITLE:=U-boot for the qi_lb60 board
3131endef
3232
33define uboot/avt2
34  TITLE:=U-boot for the avt2 board
35endef
36
37define uboot/sakc
38  TITLE:=U-boot for the sakc board
39endef
40
41define uboot/n516
42  TITLE:=U-boot for the N516 e-book reader
43  CONFIG:=n516_nand
44endef
45
46UBOOTS:=qi_lb60 n516 avt2 sakc
33UBOOTS:=qi_lb60
4734
4835define Package/uboot/template
4936define Package/uboot-xburst-$(1)
...... 
6956UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
7057endif
7158
72define Build/Prepare
73    $(CP) ./files/* $(PKG_BUILD_DIR)
74    find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
75    $(call Build/Prepare/Default)
76endef
77
7859define Build/Configure
7960    $(MAKE) -C $(PKG_BUILD_DIR) \
8061        $(UBOOT_CONFIG)_config
...... 
8364define Build/Compile
8465    $(MAKE) -C $(PKG_BUILD_DIR) \
8566        CROSS_COMPILE=$(TARGET_CROSS)
67    $(MAKE) -C $(PKG_BUILD_DIR) \
68        CROSS_COMPILE=$(TARGET_CROSS) spl/u-boot-spl.bin
69    dd if=$(PKG_BUILD_DIR)/spl/u-boot-spl.bin of=$(PKG_BUILD_DIR)/u-boot-spl-tmp.bin conv=sync bs=8192 count=1
70    dd if=$(PKG_BUILD_DIR)/spl/u-boot-spl.bin of=$(PKG_BUILD_DIR)/u-boot-spl-tmp.bin conv=sync,notrunc oflag=append bs=8192 count=1
71    tr '\0' '\377' < /dev/zero | dd of=$(PKG_BUILD_DIR)/u-boot-spl-tmp.bin conv=sync,notrunc oflag=append bs=16384 count=1
72    cat $(PKG_BUILD_DIR)/u-boot-spl-tmp.bin $(PKG_BUILD_DIR)/u-boot.bin > $(PKG_BUILD_DIR)/u-boot-nand.bin
8673endef
8774
8875define Package/uboot/install/template
package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile
1#
2# (C) Copyright 2000-2006
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
5# See file CREDITS for list of people who contributed to this
6# project.
7#
8# This program is free software; you can redistribute it and/or
9# modify it under the terms of the GNU General Public License as
10# published by the Free Software Foundation; either version 2 of
11# the License, or (at your option) any later version.
12#
13# This program is distributed in the hope that it will be useful,
14# but WITHOUT ANY WARRANTY; without even the implied warranty of
15# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16# GNU General Public License for more details.
17#
18# You should have received a copy of the GNU General Public License
19# along with this program; if not, write to the Free Software
20# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21# MA 02111-1307 USA
22#
23
24include $(TOPDIR)/config.mk
25
26LIB = $(obj)lib$(CPU).a
27
28START = start.o
29SOBJS-y =
30COBJS-y = cpu.o interrupts.o jz4740.o jz_serial.o
31
32SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
33OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
34START := $(addprefix $(obj),$(START))
35
36all: $(obj).depend $(START) $(LIB)
37
38$(LIB): $(OBJS)
39    $(AR) $(ARFLAGS) $@ $(OBJS)
40
41#########################################################################
42
43# defines $(obj).depend target
44include $(SRCTREE)/rules.mk
45
46sinclude $(obj).depend
47
48#########################################################################
package/uboot-xburst/files/arch/mips/cpu/xburst/cache.S
1/*
2 * Cache-handling routined for MIPS CPUs
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29#include <asm/addrspace.h>
30#include <asm/cacheops.h>
31
32#ifndef CONFIG_JzRISC
33
34    /* 16KB is the maximum size of instruction and data caches on
35     * MIPS 4K.
36     */
37#define MIPS_MAX_CACHE_SIZE 0x4000
38
39
40/*
41 * cacheop macro to automate cache operations
42 * first some helpers...
43 */
44#define _mincache(size, maxsize) \
45   bltu size,maxsize,9f ; \
46   move size,maxsize ; \
479:
48
49#define _align(minaddr, maxaddr, linesize) \
50   .set noat ; \
51   subu AT,linesize,1 ; \
52   not AT ; \
53   and minaddr,AT ; \
54   addu maxaddr,-1 ; \
55   and maxaddr,AT ; \
56   .set at
57
58/* general operations */
59#define doop1(op1) \
60   cache op1,0(a0)
61#define doop2(op1, op2) \
62   cache op1,0(a0) ; \
63   nop ; \
64   cache op2,0(a0)
65
66/* specials for cache initialisation */
67#define doop1lw(op1) \
68   lw zero,0(a0)
69#define doop1lw1(op1) \
70   cache op1,0(a0) ; \
71   lw zero,0(a0) ; \
72   cache op1,0(a0)
73#define doop121(op1,op2) \
74   cache op1,0(a0) ; \
75   nop; \
76   cache op2,0(a0) ; \
77   nop; \
78   cache op1,0(a0)
79
80#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
81   .set noreorder ; \
8210: doop##tag##ops ; \
83   bne minaddr,maxaddr,10b ; \
84   add minaddr,linesize ; \
85   .set reorder
86
87/* finally the cache operation macros */
88#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
89   blez n,11f ; \
90   addu n,kva ; \
91   _align(kva, n, cacheLineSize) ; \
92   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
9311:
94
95#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
96   _mincache(n, cacheSize); \
97   blez n,11f ; \
98   addu n,kva ; \
99   _align(kva, n, cacheLineSize) ; \
100   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
10111:
102
103#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
104   vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
105
106#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
107   icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
108
109/*
110* mips_cache_reset - low level initialisation of the primary caches
111*
112* This routine initialises the primary caches to ensure that they
113* have good parity. It must be called by the ROM before any cached locations
114* are used to prevent the possibility of data with bad parity being written to
115* memory.
116* To initialise the instruction cache it is essential that a source of data
117* with good parity is available. This routine
118* will initialise an area of memory starting at location zero to be used as
119* a source of parity.
120*
121* RETURNS: N/A
122*/
123    .globl mips_cache_reset
124    .ent mips_cache_reset
125mips_cache_reset:
126
127    li t2, CONFIG_SYS_ICACHE_SIZE
128    li t3, CONFIG_SYS_DCACHE_SIZE
129    li t4, CONFIG_SYS_CACHELINE_SIZE
130    move t5, t4
131
132
133    li v0, MIPS_MAX_CACHE_SIZE
134
135    /* Now clear that much memory starting from zero.
136     */
137
138    li a0, KSEG1
139    addu a1, a0, v0
140
1412: sw zero, 0(a0)
142    sw zero, 4(a0)
143    sw zero, 8(a0)
144    sw zero, 12(a0)
145    sw zero, 16(a0)
146    sw zero, 20(a0)
147    sw zero, 24(a0)
148    sw zero, 28(a0)
149    addu a0, 32
150    bltu a0, a1, 2b
151
152    /* Set invalid tag.
153     */
154
155    mtc0 zero, CP0_TAGLO
156
157   /*
158    * The caches are probably in an indeterminate state,
159    * so we force good parity into them by doing an
160    * invalidate, load/fill, invalidate for each line.
161    */
162
163    /* Assume bottom of RAM will generate good parity for the cache.
164     */
165
166    li a0, K0BASE
167    move a2, t2 # icacheSize
168    move a3, t4 # icacheLineSize
169    move a1, a2
170    icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
171
172    /* To support Orion/R4600, we initialise the data cache in 3 passes.
173     */
174
175    /* 1: initialise dcache tags.
176     */
177
178    li a0, K0BASE
179    move a2, t3 # dcacheSize
180    move a3, t5 # dcacheLineSize
181    move a1, a2
182    icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
183
184    /* 2: fill dcache.
185     */
186
187    li a0, K0BASE
188    move a2, t3 # dcacheSize
189    move a3, t5 # dcacheLineSize
190    move a1, a2
191    icacheopn(a0,a1,a2,a3,1lw,(dummy))
192
193    /* 3: clear dcache tags.
194     */
195
196    li a0, K0BASE
197    move a2, t3 # dcacheSize
198    move a3, t5 # dcacheLineSize
199    move a1, a2
200    icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
201
202    j ra
203    .end mips_cache_reset
204
205
206/*
207 * dcache_status - get cache status
208 *
209 * RETURNS: 0 - cache disabled; 1 - cache enabled
210 */
211    .globl dcache_status
212    .ent dcache_status
213dcache_status:
214
215    mfc0 v0, CP0_CONFIG
216    andi v0, v0, 1
217    j ra
218
219    .end dcache_status
220
221/*
222* dcache_disable - disable cache
223*
224* RETURNS: N/A
225*/
226    .globl dcache_disable
227    .ent dcache_disable
228dcache_disable:
229
230    mfc0 t0, CP0_CONFIG
231    li t1, -8
232    and t0, t0, t1
233    ori t0, t0, CONF_CM_UNCACHED
234    mtc0 t0, CP0_CONFIG
235    j ra
236
237    .end dcache_disable
238
239
240/*
241 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
242 *
243 * RETURNS: N/A
244 */
245#if defined(CONFIG_PURPLE)
246# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
247#else
248# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
249#endif
250    .globl mips_cache_lock
251    .ent mips_cache_lock
252mips_cache_lock:
253    li a1, K0BASE - CACHE_LOCK_SIZE
254    addu a0, a1
255    li a2, CACHE_LOCK_SIZE
256    li a3, CONFIG_SYS_CACHELINE_SIZE
257    move a1, a2
258    icacheop(a0,a1,a2,a3,0x1d)
259
260    j ra
261    .end mips_cache_lock
262
263#endif /* CONFIG_JzRISC */
package/uboot-xburst/files/arch/mips/cpu/xburst/config.mk
1#
2# (C) Copyright 2003
3# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4#
5# See file CREDITS for list of people who contributed to this
6# project.
7#
8# This program is free software; you can redistribute it and/or
9# modify it under the terms of the GNU General Public License as
10# published by the Free Software Foundation; either version 2 of
11# the License, or (at your option) any later version.
12#
13# This program is distributed in the hope that it will be useful,
14# but WITHOUT ANY WARRANTY; without even the implied warranty of
15# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16# GNU General Public License for more details.
17#
18# You should have received a copy of the GNU General Public License
19# along with this program; if not, write to the Free Software
20# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21# MA 02111-1307 USA
22#
23v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
24MIPSFLAGS:=$(shell \
25if [ "$v" -lt "14" ]; then \
26    echo "-mcpu=4kc"; \
27else \
28    echo "-march=4kc -mtune=4kc"; \
29fi)
30
31ENDIANNESS = -EL
32
33MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2
34
35PLATFORM_CPPFLAGS += $(MIPSFLAGS)
package/uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <netdev.h>
27#include <asm/mipsregs.h>
28#include <asm/cacheops.h>
29#include <asm/reboot.h>
30#include <asm/jz4740.h>
31
32#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
33
34#define cache_op(op,addr) \
35    __asm__ __volatile__( \
36    " .set push \n" \
37    " .set noreorder \n" \
38    " .set mips3\n\t \n" \
39    " cache %0, %1 \n" \
40    " .set pop \n" \
41    : \
42    : "i" (op), "R" (*(unsigned char *)(addr)))
43
44void __attribute__((weak)) _machine_restart(void)
45{
46    __wdt_select_extalclk();
47    __wdt_select_clk_div64();
48    __wdt_set_data(100);
49    __wdt_set_count(0);
50    __tcu_start_wdt_clock();
51    __wdt_start();
52    while(1);
53#if defined(CONFIG_JzRISC)
54    void (*f)(void) = (void *) 0xbfc00000;
55    f();
56#endif
57}
58
59int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
60{
61    _machine_restart();
62
63    fprintf(stderr, "*** reset failed ***\n");
64    return 0;
65}
66
67void flush_cache(ulong start_addr, ulong size)
68{
69    unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
70    unsigned long addr = start_addr & ~(lsize - 1);
71    unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
72
73    while (1) {
74        cache_op(Hit_Writeback_Inv_D, addr);
75        cache_op(Hit_Invalidate_I, addr);
76        if (addr == aend)
77            break;
78        addr += lsize;
79    }
80}
81
82void flush_dcache_range(ulong start_addr, ulong stop)
83{
84    unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
85    unsigned long addr = start_addr & ~(lsize - 1);
86    unsigned long aend = (stop - 1) & ~(lsize - 1);
87
88    while (1) {
89        cache_op(Hit_Writeback_Inv_D, addr);
90        if (addr == aend)
91            break;
92        addr += lsize;
93    }
94}
95
96void invalidate_dcache_range(ulong start_addr, ulong stop)
97{
98    unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
99    unsigned long addr = start_addr & ~(lsize - 1);
100    unsigned long aend = (stop - 1) & ~(lsize - 1);
101
102    while (1) {
103        cache_op(Hit_Invalidate_D, addr);
104        if (addr == aend)
105            break;
106        addr += lsize;
107    }
108}
109
110void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
111{
112    write_c0_entrylo0(low0);
113    write_c0_pagemask(pagemask);
114    write_c0_entrylo1(low1);
115    write_c0_entryhi(hi);
116    write_c0_index(index);
117    tlb_write_indexed();
118}
119
120#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */
121
122void flush_icache_all(void)
123{
124    u32 addr, t = 0;
125
126    asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
127    asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
128
129    for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
130         addr += CONFIG_SYS_CACHELINE_SIZE) {
131        asm volatile (
132            ".set mips3\n\t"
133            " cache %0, 0(%1)\n\t"
134            ".set mips2\n\t"
135            :
136            : "I" (Index_Store_Tag_I), "r"(addr));
137    }
138
139    /* invalicate btb */
140    asm volatile (
141        ".set mips32\n\t"
142        "mfc0 %0, $16, 7\n\t"
143        "nop\n\t"
144        "ori %0,2\n\t"
145        "mtc0 %0, $16, 7\n\t"
146        ".set mips2\n\t"
147        :
148        : "r" (t));
149}
150
151void flush_dcache_all(void)
152{
153    u32 addr;
154
155    for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
156         addr += CONFIG_SYS_CACHELINE_SIZE) {
157        asm volatile (
158            ".set mips3\n\t"
159            " cache %0, 0(%1)\n\t"
160            ".set mips2\n\t"
161            :
162            : "I" (Index_Writeback_Inv_D), "r"(addr));
163    }
164
165    asm volatile ("sync");
166}
167
168void flush_cache_all(void)
169{
170    flush_dcache_all();
171    flush_icache_all();
172}
package/uboot-xburst/files/arch/mips/cpu/xburst/interrupts.c
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26void enable_interrupts(void)
27{
28}
29
30int disable_interrupts(void)
31{
32    return 0;
33}
package/uboot-xburst/files/arch/mips/cpu/xburst/jz4740.c
1/*
2 * Jz4740 common routines
3 *
4 * Copyright (c) 2006
5 * Ingenic Semiconductor, <jlwei@ingenic.cn>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24
25#ifdef CONFIG_JZ4740
26#include <common.h>
27#include <command.h>
28#include <asm/jz4740.h>
29
30extern void board_early_init(void);
31
32/* PLL output clock = EXTAL * NF / (NR * NO)
33 *
34 * NF = FD + 2, NR = RD + 2
35 * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
36 */
37void pll_init(void)
38{
39    register unsigned int cfcr, plcr1;
40    int n2FR[33] = {
41        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
42        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
43        9
44    };
45    int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
46    int nf, pllout2;
47
48    cfcr = CPM_CPCCR_CLKOEN |
49        CPM_CPCCR_PCS |
50        (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
51        (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
52        (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
53        (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
54        (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
55
56    pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
57
58    /* Init USB Host clock, pllout2 must be n*48MHz */
59    REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
60
61    nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
62    plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
63        (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
64        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
65        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
66        CPM_CPPCR_PLLEN; /* enable PLL */
67
68    /* init PLL */
69    REG_CPM_CPCCR = cfcr;
70    REG_CPM_CPPCR = plcr1;
71}
72
73void pll_add_test(int new_freq)
74{
75    register unsigned int cfcr, plcr1;
76    int n2FR[33] = {
77        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
78        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
79        9
80    };
81    int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
82    int nf, pllout2;
83
84    cfcr = CPM_CPCCR_CLKOEN |
85        (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
86        (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
87        (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
88        (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
89        (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
90
91    pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
92
93    /* Init UHC clock */
94    REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
95
96    /* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */
97    nf = new_freq / 1000000; /* step length is 1M */
98    plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
99        (10 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
100        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
101        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
102        CPM_CPPCR_PLLEN; /* enable PLL */
103
104    /* init PLL */
105    REG_CPM_CPCCR = cfcr;
106    REG_CPM_CPPCR = plcr1;
107}
108
109void calc_clocks_add_test(void)
110{
111    DECLARE_GLOBAL_DATA_PTR;
112
113    unsigned int pllout;
114    unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
115
116    pllout = __cpm_get_pllout();
117
118    gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
119    gd->sys_clk = pllout / div[__cpm_get_hdiv()];
120    gd->per_clk = pllout / div[__cpm_get_pdiv()];
121    gd->mem_clk = pllout / div[__cpm_get_mdiv()];
122    gd->dev_clk = CONFIG_SYS_EXTAL;
123}
124
125void sdram_add_test(int new_freq)
126{
127    register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
128
129    unsigned int cas_latency_sdmr[2] = {
130        EMC_SDMR_CAS_2,
131        EMC_SDMR_CAS_3,
132    };
133
134    unsigned int cas_latency_dmcr[2] = {
135        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
136        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
137    };
138
139    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
140
141    cpu_clk = new_freq;
142    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
143
144    REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
145    REG_EMC_RTCOR = 0;
146    REG_EMC_RTCNT = 0;
147
148    /* Basic DMCR register value. */
149    dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
150        ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
151        (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
152        (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
153        EMC_DMCR_EPIN |
154        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
155
156    /* SDRAM timimg parameters */
157    ns = 1000000000 / mem_clk;
158
159#if 0
160    tmp = SDRAM_TRAS/ns;
161    if (tmp < 4) tmp = 4;
162    if (tmp > 11) tmp = 11;
163    dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
164
165    tmp = SDRAM_RCD/ns;
166    if (tmp > 3) tmp = 3;
167    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
168
169    tmp = SDRAM_TPC/ns;
170    if (tmp > 7) tmp = 7;
171    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
172
173    tmp = SDRAM_TRWL/ns;
174    if (tmp > 3) tmp = 3;
175    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
176
177    tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
178    if (tmp > 14) tmp = 14;
179    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
180#else
181    dmcr |= 0xfffc;
182#endif
183
184    /* First, precharge phase */
185    REG_EMC_DMCR = dmcr;
186
187    /* Set refresh registers */
188    tmp = SDRAM_TREF/ns;
189    tmp = tmp/64 + 1;
190    if (tmp > 0xff) tmp = 0xff;
191
192    REG_EMC_RTCOR = tmp;
193    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
194
195    /* SDRAM mode values */
196    sdmode = EMC_SDMR_BT_SEQ |
197         EMC_SDMR_OM_NORMAL |
198         EMC_SDMR_BL_4 |
199         cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
200
201    /* precharge all chip-selects */
202    REG8(EMC_SDMR0|sdmode) = 0;
203
204    /* wait for precharge, > 200us */
205    tmp = (cpu_clk / 1000000) * 200;
206    while (tmp--);
207
208    /* enable refresh and set SDRAM mode */
209    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
210
211    /* write sdram mode register for each chip-select */
212    REG8(EMC_SDMR0|sdmode) = 0;
213
214    /* everything is ok now */
215}
216
217void sdram_init(void)
218{
219    register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
220
221    unsigned int cas_latency_sdmr[2] = {
222        EMC_SDMR_CAS_2,
223        EMC_SDMR_CAS_3,
224    };
225
226    unsigned int cas_latency_dmcr[2] = {
227        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
228        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
229    };
230
231    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
232
233    cpu_clk = CONFIG_SYS_CPU_SPEED;
234    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
235
236    REG_EMC_BCR = 0; /* Disable bus release */
237    REG_EMC_RTCSR = 0; /* Disable clock for counting */
238
239    /* Fault DMCR value for mode register setting*/
240#define SDRAM_ROW0 11
241#define SDRAM_COL0 8
242#define SDRAM_BANK40 0
243
244    dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
245        ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
246        (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
247        (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
248        EMC_DMCR_EPIN |
249        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
250
251    /* Basic DMCR value */
252    dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
253        ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
254        (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
255        (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
256        EMC_DMCR_EPIN |
257        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
258
259    /* SDRAM timimg */
260    ns = 1000000000 / mem_clk;
261    tmp = SDRAM_TRAS/ns;
262    if (tmp < 4) tmp = 4;
263    if (tmp > 11) tmp = 11;
264    dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
265    tmp = SDRAM_RCD/ns;
266    if (tmp > 3) tmp = 3;
267    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
268    tmp = SDRAM_TPC/ns;
269    if (tmp > 7) tmp = 7;
270    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
271    tmp = SDRAM_TRWL/ns;
272    if (tmp > 3) tmp = 3;
273    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
274    tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
275    if (tmp > 14) tmp = 14;
276    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
277
278    /* SDRAM mode value */
279    sdmode = EMC_SDMR_BT_SEQ |
280         EMC_SDMR_OM_NORMAL |
281         EMC_SDMR_BL_4 |
282         cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
283
284    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
285    REG_EMC_DMCR = dmcr;
286    REG8(EMC_SDMR0|sdmode) = 0;
287
288    /* Wait for precharge, > 200us */
289    tmp = (cpu_clk / 1000000) * 1000;
290    while (tmp--);
291
292    /* Stage 2. Enable auto-refresh */
293    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
294
295    tmp = SDRAM_TREF/ns;
296    tmp = tmp/64 + 1;
297    if (tmp > 0xff) tmp = 0xff;
298    REG_EMC_RTCOR = tmp;
299    REG_EMC_RTCNT = 0;
300    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
301
302    /* Wait for number of auto-refresh cycles */
303    tmp = (cpu_clk / 1000000) * 1000;
304    while (tmp--);
305
306     /* Stage 3. Mode Register Set */
307    REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
308    REG8(EMC_SDMR0|sdmode) = 0;
309
310        /* Set back to basic DMCR value */
311    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
312
313    /* everything is ok now */
314}
315
316#ifndef CONFIG_NAND_SPL
317
318static void calc_clocks(void)
319{
320    DECLARE_GLOBAL_DATA_PTR;
321
322    unsigned int pllout;
323    unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
324
325    pllout = __cpm_get_pllout();
326
327    gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
328    gd->sys_clk = pllout / div[__cpm_get_hdiv()];
329    gd->per_clk = pllout / div[__cpm_get_pdiv()];
330    gd->mem_clk = pllout / div[__cpm_get_mdiv()];
331    gd->dev_clk = CONFIG_SYS_EXTAL;
332}
333
334static void rtc_init(void)
335{
336    unsigned long rtcsta;
337
338    while ( !__rtc_write_ready()) ;
339    __rtc_enable_alarm(); /* enable alarm */
340
341    while ( !__rtc_write_ready())
342        ;
343    REG_RTC_RGR = 0x00007fff; /* type value */
344
345    while ( !__rtc_write_ready())
346        ;
347    REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
348
349    while ( !__rtc_write_ready())
350        ;
351    REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
352#if 0
353    while ( !__rtc_write_ready())
354        ;
355    rtcsta = REG_RTC_HWRSR;
356    while ( !__rtc_write_ready())
357        ;
358    if (rtcsta & 0x33) {
359        if (rtcsta & 0x10) {
360            while ( !__rtc_write_ready())
361                ;
362            REG_RTC_RSR = 0x0;
363        }
364        while ( !__rtc_write_ready())
365            ;
366        REG_RTC_HWRSR = 0x0;
367    }
368#endif
369}
370
371/*
372 * jz4740 board init routine
373 */
374int jz_board_init(void)
375{
376    board_early_init(); /* init gpio, pll etc. */
377#ifndef CONFIG_NAND_U_BOOT
378    pll_init(); /* init PLL */
379    sdram_init(); /* init sdram memory */
380#endif
381    calc_clocks(); /* calc the clocks */
382    rtc_init(); /* init rtc on any reset: */
383    return 0;
384}
385
386/* U-Boot common routines */
387phys_size_t initdram(int board_type)
388{
389    u32 dmcr;
390    u32 rows, cols, dw, banks;
391    ulong size;
392
393    dmcr = REG_EMC_DMCR;
394    rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
395    cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
396    dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
397    banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
398
399    size = (1 << (rows + cols)) * dw * banks;
400
401    return size;
402}
403
404/*
405 * Timer routines
406 */
407
408#define TIMER_CHAN 0
409#define TIMER_FDATA 0xffff /* Timer full data value */
410#define TIMER_HZ CONFIG_SYS_HZ
411
412#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
413
414static ulong timestamp;
415static ulong lastdec;
416
417void reset_timer_masked (void);
418ulong get_timer_masked (void);
419void udelay_masked (unsigned long usec);
420
421/*
422 * timer without interrupts
423 */
424
425int timer_init(void)
426{
427    REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
428    REG_TCU_TCNT(TIMER_CHAN) = 0;
429    REG_TCU_TDHR(TIMER_CHAN) = 0;
430    REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
431
432    REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
433    REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
434    REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
435
436    lastdec = 0;
437    timestamp = 0;
438
439    return 0;
440}
441
442void reset_timer(void)
443{
444    reset_timer_masked ();
445}
446
447ulong get_timer(ulong base)
448{
449    return get_timer_masked () - base;
450}
451
452void set_timer(ulong t)
453{
454    timestamp = t;
455}
456
457void __udelay (unsigned long usec)
458{
459    ulong tmo,tmp;
460
461    /* normalize */
462    if (usec >= 1000) {
463        tmo = usec / 1000;
464        tmo *= TIMER_HZ;
465        tmo /= 1000;
466    }
467    else {
468        if (usec >= 1) {
469            tmo = usec * TIMER_HZ;
470            tmo /= (1000*1000);
471        }
472        else
473            tmo = 1;
474    }
475
476    /* check for rollover during this delay */
477    tmp = get_timer (0);
478    if ((tmp + tmo) < tmp )
479        reset_timer_masked(); /* timer would roll over */
480    else
481        tmo += tmp;
482
483    while (get_timer_masked () < tmo);
484}
485
486void reset_timer_masked (void)
487{
488    /* reset time */
489    lastdec = READ_TIMER;
490    timestamp = 0;
491}
492
493ulong get_timer_masked (void)
494{
495    ulong now = READ_TIMER;
496
497    if (lastdec <= now) {
498        /* normal mode */
499        timestamp += (now - lastdec);
500    } else {
501        /* we have an overflow ... */
502        timestamp += TIMER_FDATA + now - lastdec;
503    }
504    lastdec = now;
505
506    return timestamp;
507}
508
509void udelay_masked (unsigned long usec)
510{
511    ulong tmo;
512    ulong endtime;
513    signed long diff;
514
515    /* normalize */
516    if (usec >= 1000) {
517        tmo = usec / 1000;
518        tmo *= TIMER_HZ;
519        tmo /= 1000;
520    } else {
521        if (usec > 1) {
522            tmo = usec * TIMER_HZ;
523            tmo /= (1000*1000);
524        } else {
525            tmo = 1;
526        }
527    }
528
529    endtime = get_timer_masked () + tmo;
530
531    do {
532        ulong now = get_timer_masked ();
533        diff = endtime - now;
534    } while (diff >= 0);
535}
536
537/*
538 * This function is derived from PowerPC code (read timebase as long long).
539 * On MIPS it just returns the timer value.
540 */
541unsigned long long get_ticks(void)
542{
543    return get_timer(0);
544}
545
546/*
547 * This function is derived from PowerPC code (timebase clock frequency).
548 * On MIPS it returns the number of timer ticks per second.
549 */
550ulong get_tbclk (void)
551{
552    return TIMER_HZ;
553}
554
555#endif /* CONFIG_NAND_SPL */
556
557/* End of timer routine. */
558
559#endif
package/uboot-xburst/files/arch/mips/cpu/xburst/jz_serial.c
1/*
2 * Jz47xx UART support
3 *
4 * Hardcoded to UART 0 for now
5 * Options also hardcoded to 8N1
6 *
7 * Copyright (c) 2005
8 * Ingenic Semiconductor, <jlwei@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27
28#if defined(CONFIG_JZ4740)
29
30#include <common.h>
31
32#include <asm/jz4740.h>
33
34#undef UART_BASE
35#ifndef CONFIG_SYS_UART_BASE
36#define UART_BASE UART0_BASE
37#else
38#define UART_BASE CONFIG_SYS_UART_BASE
39#endif
40
41/******************************************************************************
42*
43* serial_init - initialize a channel
44*
45* This routine initializes the number of data bits, parity
46* and set the selected baud rate. Interrupts are disabled.
47* Set the modem control signals if the option is selected.
48*
49* RETURNS: N/A
50*/
51
52int serial_init (void)
53{
54#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
55    volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
56    volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
57    volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
58    volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
59
60    /* Disable port interrupts while changing hardware */
61    *uart_ier = 0;
62
63    /* Disable UART unit function */
64    *uart_fcr = ~UART_FCR_UUE;
65
66    /* Set both receiver and transmitter in UART mode (not SIR) */
67    *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
68
69    /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
70    *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
71
72    /* Set baud rate */
73    serial_setbrg();
74
75    /* Enable UART unit, enable and clear FIFO */
76    *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
77#endif
78    return 0;
79}
80
81void serial_setbrg (void)
82{
83    volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
84    volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
85    volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
86    u32 baud_div, tmp;
87
88    baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
89
90    tmp = *uart_lcr;
91    tmp |= UART_LCR_DLAB;
92    *uart_lcr = tmp;
93
94    *uart_dlhr = (baud_div >> 8) & 0xff;
95    *uart_dllr = baud_div & 0xff;
96
97    tmp &= ~UART_LCR_DLAB;
98    *uart_lcr = tmp;
99}
100
101void serial_putc (const char c)
102{
103    volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
104    volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
105
106    if (c == '\n') serial_putc ('\r');
107
108    /* Wait for fifo to shift out some bytes */
109    while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
110
111    *uart_tdr = (u8)c;
112}
113
114void serial_puts (const char *s)
115{
116    while (*s) {
117        serial_putc (*s++);
118    }
119}
120
121int serial_getc (void)
122{
123    volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
124
125    while (!serial_tstc());
126
127    return *uart_rdr;
128}
129
130int serial_tstc (void)
131{
132    volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
133
134    if (*uart_lsr & UART_LSR_DR) {
135        /* Data in rfifo */
136        return (1);
137    }
138    return 0;
139}
140
141#endif
package/uboot-xburst/files/arch/mips/cpu/xburst/start.S
1/*
2 * Startup Code for MIPS32 XBURST CPU-core
3 *
4 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29#include <asm/addrspace.h>
30#include <asm/cacheops.h>
31
32#include <asm/jz4740.h>
33
34    .set noreorder
35
36    .globl _start
37    .text
38_start:
39    /* Initialize GOT pointer.
40    */
41    bal 1f
42    nop
43    .word _GLOBAL_OFFSET_TABLE_
441:
45    move gp, ra
46    lw t1, 0(ra)
47    move gp, t1
48
49    li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
50    la sp, 0(t0)
51
52    la t9, board_init_f
53    j t9
54    nop
55
56/*
57 * void relocate_code (addr_sp, gd, addr_moni)
58 *
59 * This "function" does not return, instead it continues in RAM
60 * after relocating the monitor code.
61 *
62 * a0 = addr_sp
63 * a1 = gd
64 * a2 = destination address
65 */
66    .globl relocate_code
67    .ent relocate_code
68relocate_code:
69    move sp, a0 /* Set new stack pointer */
70
71    li t0, TEXT_BASE
72    la t3, in_ram
73    lw t2, -12(t3) /* t2 <-- uboot_end_data */
74    move t1, a2
75
76    /*
77     * Fix GOT pointer:
78     *
79     * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
80     */
81    move t6, gp
82    sub gp, TEXT_BASE
83    add gp, a2 /* gp now adjusted */
84    sub t6, gp, t6 /* t6 <-- relocation offset*/
85
86    /*
87     * t0 = source address
88     * t1 = target address
89     * t2 = source end address
90     */
911:
92    lw t3, 0(t0)
93    sw t3, 0(t1)
94    addu t0, 4
95    ble t0, t2, 1b
96    addu t1, 4 /* delay slot */
97
98    /* If caches were enabled, we would have to flush them here.
99     * flush d-cache */
100    .set mips32
101    li t0, KSEG0
102    addi t1, t0, CONFIG_SYS_DCACHE_SIZE
1032:
104    cache Index_Writeback_Inv_D, 0(t0)
105    bne t0, t1, 2b
106    addi t0, CONFIG_SYS_CACHELINE_SIZE
107
108    sync
109
110    /* flush i-cache */
111    li t0, KSEG0
112    addi t1, t0, CONFIG_SYS_ICACHE_SIZE
1133:
114    cache Index_Invalidate_I, 0(t0)
115    bne t0, t1, 3b
116    addi t0, CONFIG_SYS_CACHELINE_SIZE
117
118    /* Invalidate BTB */
119    mfc0 t0, CP0_CONFIG, 7
120    nop
121    ori t0, 2
122    mtc0 t0, CP0_CONFIG, 7
123    nop
124
125    .set mips0
126
127    /* Jump to where we've relocated ourselves.
128     */
129    addi t0, a2, in_ram - _start
130    j t0
131    nop
132
133    .word uboot_end_data
134    .word uboot_end
135    .word num_got_entries
136
137in_ram:
138    /* Now we want to update GOT */
139    lw t3, -4(t0) /* t3 <-- num_got_entries */
140    addi t4, gp, 8 /* Skipping first two entries. */
141    li t2, 2
1421:
143    lw t1, 0(t4)
144    beqz t1, 2f
145    add t1, t6
146    sw t1, 0(t4)
1472:
148    addi t2, 1
149    blt t2, t3, 1b
150    addi t4, 4 /* delay slot */
151
152    /* Clear BSS */
153    lw t1, -12(t0) /* t1 <-- uboot_end_data */
154    lw t2, -8(t0) /* t2 <-- uboot_end */
155    add t1, t6 /* adjust pointers */
156    add t2, t6
157
158    sub t1, 4
1591: addi t1, 4
160    bltl t1, t2, 1b
161    sw zero, 0(t1) /* delay slot */
162
163    move a0, a1
164    la t9, board_init_r
165    j t9
166    move a1, a2 /* delay slot */
167
168    .end relocate_code
169
package/uboot-xburst/files/arch/mips/cpu/xburst/start_spl.S
1/*
2 * Startup Code for MIPS32 XBURST CPU-core
3 *
4 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 3 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29#include <asm/addrspace.h>
30#include <asm/cacheops.h>
31
32#include <asm/jz4740.h>
33
34    .set noreorder
35
36    .globl _start
37    .text
38_start:
39    .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
40reset:
41    /*
42     * STATUS register
43     * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
44     */
45    li t0, 0x0040FC04
46    mtc0 t0, CP0_STATUS
47    /* CAUSE register
48     * IV=1, use the specical interrupt vector (0x200) */
49    li t1, 0x00800000
50    mtc0 t1, CP0_CAUSE
51
52    bal 1f
53    nop
54    .word _GLOBAL_OFFSET_TABLE_
551:
56    move gp, ra
57    lw t1, 0(ra)
58    move gp, t1
59
60    la sp, 0x80004000
61    la t9, nand_boot
62    j t9
63    nop
package/uboot-xburst/files/arch/mips/cpu/xburst/usbboot.S
1/*
2 * for jz4740 usb boot
3 *
4 * Copyright (c) 2009 Author: <jlwei@ingenic.cn>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24    .set noreorder
25    .globl usb_boot
26    .text
27
28//----------------------------------------------------------------------
29// Both NAND and USB boot load data to D-Cache first, then transfer
30// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
31// So init caches first and then dispatch to a proper boot routine.
32//----------------------------------------------------------------------
33
34.macro load_addr reg addr
35    li \reg, 0x80000000
36    addiu \reg, \reg, \addr
37    la $2, usbboot_begin
38    subu \reg, \reg, $2
39.endm
40
41usb_boot:
42    //--------------------------------------------------------------
43    // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
44    //--------------------------------------------------------------
45    la $9, 0xB0000000 // CPCCR: Clock Control Register
46    la $8, 0x42041110 // I:S:M:P=1:2:2:2
47    sw $8, 0($9)
48
49    la $9, 0xB0000010 // CPPCR: PLL Control Register
50    la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
51    sw $8, 0($9)
52
53    mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
54    nop
55
56    mtc0 $0, $16 // CP0_CONFIG
57    nop
58
59    // Relocate code to beginning of the ram
60
61    la $2, usbboot_begin
62    la $3, usbboot_end
63    li $4, 0x80000000
64
651:
66    lw $5, 0($2)
67    sw $5, 0($4)
68    addiu $2, $2, 4
69    bne $2, $3, 1b
70    addiu $4, $4, 4
71
72    li $2, 0x80000000
73    ori $3, $2, 0
74    addiu $3, $3, usbboot_end
75    la $4, usbboot_begin
76    subu $3, $3, $4
77
78
792:
80    cache 0x0, 0($2) // Index_Invalidate_I
81    cache 0x1, 0($2) // Index_Writeback_Inv_D
82    addiu $2, $2, 32
83    subu $4, $3, $2
84    bgtz $4, 2b
85    nop
86
87    load_addr $3, usb_boot_return
88
89    jr $3
90
91usbboot_begin:
92
93init_caches:
94    li $2, 3 // cacheable for kseg0 access
95    mtc0 $2, $16 // CP0_CONFIG
96    nop
97
98    li $2, 0x20000000 // enable idx-store-data cache insn
99    mtc0 $2, $26 // CP0_ERRCTL
100
101    ori $2, $28, 0 // start address
102    ori $3, $2, 0x3fe0 // end address, total 16KB
103    mtc0 $0, $28, 0 // CP0_TAGLO
104    mtc0 $0, $28, 1 // CP0_DATALO
105cache_clear_a_line:
106    cache 0x8, 0($2) // Index_Store_Tag_I
107    cache 0x9, 0($2) // Index_Store_Tag_D
108    bne $2, $3, cache_clear_a_line
109    addiu $2, $2, 32 // increment CACHE_LINE_SIZE
110
111    ori $2, $28, 0 // start address
112    ori $3, $2, 0x3fe0 // end address, total 16KB
113    la $4, 0x1ffff000 // physical address and 4KB page mask
114cache_alloc_a_line:
115    and $5, $2, $4
116    ori $5, $5, 1 // V bit of the physical tag
117    mtc0 $5, $28, 0 // CP0_TAGLO
118    cache 0x8, 0($2) // Index_Store_Tag_I
119    cache 0x9, 0($2) // Index_Store_Tag_D
120    bne $2, $3, cache_alloc_a_line
121    addiu $2, $2, 32 // increment CACHE_LINE_SIZE
122
123    nop
124    nop
125    nop
126    //--------------------------------------------------------------
127    // Transfer data from dcache to icache, then jump to icache.
128    //
129    // Input parameters:
130    //
131    // $19: data length in bytes
132    // $20: jump target address
133    //--------------------------------------------------------------
134xfer_d2i:
135
136    ori $8, $20, 0
137    addu $9, $8, $19 // total 16KB
138
1391:
140    cache 0x0, 0($8) // Index_Invalidate_I
141    cache 0x1, 0($8) // Index_Writeback_Inv_D
142    bne $8, $9, 1b
143    addiu $8, $8, 32
144
145    // flush write-buffer
146    sync
147
148    // Invalidate BTB
149    mfc0 $8, $16, 7 // CP0_CONFIG
150    nop
151    ori $8, 2
152    mtc0 $8, $16, 7
153    nop
154
155    // Overwrite config to disable ram initalisation
156    li $2, 0xff
157    sb $2, 20($20)
158
159    jalr $20
160    nop
161
162icache_return:
163    //--------------------------------------------------------------
164    // User code can return to here after executing itself in
165    // icache, by jumping to $31.
166    //--------------------------------------------------------------
167    b usb_boot_return
168    nop
169
170
171usb_boot_return:
172    //--------------------------------------------------------------
173    // Enable the USB PHY
174    //--------------------------------------------------------------
175    la $9, 0xB0000024 // CPM_SCR
176    lw $8, 0($9)
177    ori $8, 0x40 // USBPHY_ENABLE
178    sw $8, 0($9)
179
180    //--------------------------------------------------------------
181    // Initialize USB registers
182    //--------------------------------------------------------------
183    la $27, 0xb3040000 // USB registers base address
184
185    sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts
186    sh $0, 0x06($27) // INTRINE: disable EPIN interrutps
187    sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps
188
189    li $9, 0x61
190    sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN
191
192    //--------------------------------------------------------------
193    // Initialize USB states
194    //--------------------------------------------------------------
195    li $22, 0 // set EP0 to IDLE state
196    li $23, 1 // no data stage
197
198    //--------------------------------------------------------------
199    // Main loop of polling the usb commands
200    //--------------------------------------------------------------
201usb_command_loop:
202    lbu $9, 0x0a($27) // read INTRUSB
203    andi $9, 0x04 // check USB_INTR_RESET
204    beqz $9, check_intr_ep0in
205    nop
206
207    //--------------------------------------------------------------
208     // 1. Handle USB reset interrupt
209    //--------------------------------------------------------------
210handle_reset_intr:
211    lbu $9, 0x01($27) // read POWER
212    andi $9, 0x10 // test HS_MODE
213    bnez $9, _usb_set_maxpktsize
214    li $9, 512 // max packet size of HS mode
215    li $9, 64 // max packet size of FS mode
216
217_usb_set_maxpktsize:
218    li $8, 1
219    sb $8, 0x0e($27) // set INDEX 1
220
221    sh $9, 0x10($27) // INMAXP
222    sb $0, 0x13($27) // INCSRH
223    sh $9, 0x14($27) // OUTMAXP
224    sb $0, 0x17($27) // OUTCSRH
225
226_usb_flush_fifo:
227    li $8, 0x48 // INCSR_CDT && INCSR_FF
228    sb $8, 0x12($27) // INCSR
229    li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF
230    sb $8, 0x16($27) // OUTCSR
231
232    li $22, 0 // set EP0 to IDLE state
233    li $23, 1 // no data stage
234
235    //--------------------------------------------------------------
236    // 2. Check and handle EP0 interrupt
237    //--------------------------------------------------------------
238check_intr_ep0in:
239    lhu $10, 0x02($27) // read INTRIN
240    andi $9, $10, 0x1 // check EP0 interrupt
241    beqz $9, check_intr_ep1in
242    nop
243
244handle_ep0_intr:
245    sb $0, 0x0e($27) // set INDEX 0
246    lbu $11, 0x12($27) // read CSR0
247
248    andi $9, $11, 0x04 // check SENTSTALL
249    beqz $9, _ep0_setupend
250    nop
251
252_ep0_sentstall:
253    andi $9, $11, 0xdb
254    sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL
255    li $22, 0 // set EP0 to IDLE state
256
257_ep0_setupend:
258    andi $9, $11, 0x10 // check SETUPEND
259    beqz $9, ep0_idle_state
260    nop
261
262    ori $9, $11, 0x80
263    sb $9, 0x12($27) // set SVDSETUPEND
264    li $22, 0 // set EP0 to IDLE state
265
266ep0_idle_state:
267    bnez $22, ep0_tx_state
268    nop
269
270    //--------------------------------------------------------------
271    // 2.1 Handle EP0 IDLE state interrupt
272    //--------------------------------------------------------------
273    andi $9, $11, 0x01 // check OUTPKTRDY
274    beqz $9, check_intr_ep1in
275    nop
276
277    //--------------------------------------------------------------
278    // Read 8-bytes setup packet from the FIFO
279    //--------------------------------------------------------------
280    lw $25, 0x20($27) // first word of setup packet
281    lw $26, 0x20($27) // second word of setup packet
282
283    andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK
284    beqz $9, _ep0_std_req
285    nop
286
287    //--------------------------------------------------------------
288    // 2.1.1 Vendor-specific setup request
289    //--------------------------------------------------------------
290_ep0_vend_req:
291    li $22, 0 // set EP0 to IDLE state
292    li $23, 1 // NoData = 1
293
294    andi $9, $25, 0xff00 // check bRequest
295    srl $9, $9, 8
296    beqz $9, __ep0_get_cpu_info
297    sub $8, $9, 0x1
298    beqz $8, __ep0_set_data_address
299    sub $8, $9, 0x2
300    beqz $8, __ep0_set_data_length
301    sub $8, $9, 0x3
302    beqz $8, __ep0_flush_caches
303    sub $8, $9, 0x4
304    beqz $8, __ep0_prog_start1
305    sub $8, $9, 0x5
306    beqz $8, __ep0_prog_start2
307    nop
308    b _ep0_idle_state_fini // invalid request
309    nop
310
311__ep0_get_cpu_info:
312    load_addr $20, cpu_info_data // data pointer to transfer
313    li $21, 8 // bytes left to transfer
314    li $22, 1 // set EP0 to TX state
315    li $23, 0 // NoData = 0
316
317    b _ep0_idle_state_fini
318    nop
319
320__ep0_set_data_address:
321    li $9, 0xffff0000
322    and $9, $25, $9
323    andi $8, $26, 0xffff
324    or $20, $9, $8 // data address of next transfer
325
326    b _ep0_idle_state_fini
327    nop
328
329__ep0_set_data_length:
330    li $9, 0xffff0000
331    and $9, $25, $9
332    andi $8, $26, 0xffff
333    or $21, $9, $8 // data length of next transfer
334
335    li $9, 0x48 // SVDOUTPKTRDY and DATAEND
336    sb $9, 0x12($27) // CSR0
337
338    // We must write packet to FIFO before EP1-IN interrupt here.
339    b handle_epin1_intr
340    nop
341
342__ep0_flush_caches:
343    // Flush dcache and invalidate icache.
344    li $8, 0x80000000
345    addi $9, $8, 0x3fe0 // total 16KB
346
3471:
348    cache 0x0, 0($8) // Index_Invalidate_I
349    cache 0x1, 0($8) // Index_Writeback_Inv_D
350    bne $8, $9, 1b
351    addiu $8, $8, 32
352
353    // flush write-buffer
354    sync
355
356    // Invalidate BTB
357    mfc0 $8, $16, 7 // CP0_CONFIG
358    nop
359    ori $8, 2
360    mtc0 $8, $16, 7
361    nop
362
363    b _ep0_idle_state_fini
364    nop
365
366__ep0_prog_start1:
367    li $9, 0x48 // SVDOUTPKTRDY and DATAEND
368    sb $9, 0x12($27) // CSR0
369
370    li $9, 0xffff0000
371    and $9, $25, $9
372    andi $8, $26, 0xffff
373    or $20, $9, $8 // target address
374
375    b xfer_d2i
376    li $19, 0x2000 // 16KB data length
377
378__ep0_prog_start2:
379    li $9, 0x48 // SVDOUTPKTRDY and DATAEND
380    sb $9, 0x12($27) // CSR0
381
382    li $9, 0xffff0000
383    and $9, $25, $9
384    andi $8, $26, 0xffff
385    or $20, $9, $8 // target address
386
387    jalr $20 // jump, and place the return address in $31
388    nop
389
390__ep0_prog_start2_return:
391    // User code can return to here after executing itself, by jumping to $31.
392    b usb_boot_return
393    nop
394
395    //--------------------------------------------------------------
396    // 2.1.2 Standard setup request
397    //--------------------------------------------------------------
398_ep0_std_req:
399    andi $12, $25, 0xff00 // check bRequest
400    srl $12, $12, 8
401    sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS
402    bnez $9, __ep0_req_set_config
403    nop
404
405    //--------------------------------------------------------------
406    // Handle USB_REQ_SET_ADDRESS
407    //--------------------------------------------------------------
408__ep0_req_set_addr:
409    srl $9, $25, 16 // get wValue
410    sb $9, 0x0($27) // set FADDR
411    li $23, 1 // NoData = 1
412    b _ep0_idle_state_fini
413    nop
414
415__ep0_req_set_config:
416    sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION
417    bnez $9, __ep0_req_get_desc
418    nop
419
420    //--------------------------------------------------------------
421    // Handle USB_REQ_SET_CONFIGURATION
422    //--------------------------------------------------------------
423    li $23, 1 // NoData = 1
424    b _ep0_idle_state_fini
425    nop
426
427__ep0_req_get_desc:
428    sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR
429    bnez $9, _ep0_idle_state_fini
430    li $23, 1 // NoData = 1
431
432    //--------------------------------------------------------------
433    // Handle USB_REQ_GET_DESCRIPTOR
434    //--------------------------------------------------------------
435    li $23, 0 // NoData = 0
436
437    srl $9, $25, 24 // wValue >> 8
438    sub $8, $9, 0x01 // check USB_DT_DEVICE
439    beqz $8, ___ep0_get_dev_desc
440    srl $21, $26, 16 // get wLength
441    sub $8, $9, 0x02 // check USB_DT_CONFIG
442    beqz $8, ___ep0_get_conf_desc
443    sub $8, $9, 0x03 // check USB_DT_STRING
444    beqz $8, ___ep0_get_string_desc
445    sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER
446    beqz $8, ___ep0_get_dev_qualifier
447    nop
448    b _ep0_idle_state_fini
449    nop
450
451___ep0_get_dev_desc:
452    load_addr $20, device_desc // data pointer
453    li $22, 1 // set EP0 to TX state
454    sub $8, $21, 18
455    blez $8, _ep0_idle_state_fini // wLength <= 18
456    nop
457    li $21, 18 // max length of device_desc
458    b _ep0_idle_state_fini
459    nop
460
461___ep0_get_dev_qualifier:
462    load_addr $20, dev_qualifier // data pointer
463    li $22, 1 // set EP0 to TX state
464    sub $8, $21, 10
465    blez $8, _ep0_idle_state_fini // wLength <= 10
466    nop
467    li $21, 10 // max length of dev_qualifier
468    b _ep0_idle_state_fini
469    nop
470
471___ep0_get_conf_desc:
472    load_addr $20, config_desc_fs // data pointer of FS mode
473    lbu $8, 0x01($27) // read POWER
474    andi $8, 0x10 // test HS_MODE
475    beqz $8, ___ep0_get_conf_desc2
476    nop
477    load_addr $20, config_desc_hs // data pointer of HS mode
478
479___ep0_get_conf_desc2:
480    li $22, 1 // set EP0 to TX state
481    sub $8, $21, 32
482    blez $8, _ep0_idle_state_fini // wLength <= 32
483    nop
484    li $21, 32 // max length of config_desc
485    b _ep0_idle_state_fini
486    nop
487
488___ep0_get_string_desc:
489    li $22, 1 // set EP0 to TX state
490
491    srl $9, $25, 16 // wValue & 0xff
492    andi $9, 0xff
493
494    sub $8, $9, 1
495    beqz $8, ___ep0_get_string_manufacture
496    sub $8, $9, 2
497    beqz $8, ___ep0_get_string_product
498    nop
499
500___ep0_get_string_lang_ids:
501    load_addr $20, string_lang_ids // data pointer
502    b _ep0_idle_state_fini
503    li $21, 4 // data length
504
505___ep0_get_string_manufacture:
506    load_addr $20, string_manufacture // data pointer
507    b _ep0_idle_state_fini
508    li $21, 16 // data length
509
510___ep0_get_string_product:
511    load_addr $20, string_product // data pointer
512    b _ep0_idle_state_fini
513    li $21, 46 // data length
514
515_ep0_idle_state_fini:
516    li $9, 0x40 // SVDOUTPKTRDY
517    beqz $23, _ep0_idle_state_fini2
518    nop
519    ori $9, $9, 0x08 // DATAEND
520_ep0_idle_state_fini2:
521    sb $9, 0x12($27) // CSR0
522    beqz $22, check_intr_ep1in
523    nop
524
525    //--------------------------------------------------------------
526    // 2.2 Handle EP0 TX state interrupt
527    //--------------------------------------------------------------
528ep0_tx_state:
529    sub $9, $22, 1
530    bnez $9, check_intr_ep1in
531    nop
532
533    sub $9, $21, 64 // max packetsize
534    blez $9, _ep0_tx_state2 // data count <= 64
535    ori $19, $21, 0
536    li $19, 64
537
538_ep0_tx_state2:
539    beqz $19, _ep0_tx_state3 // send ZLP
540    ori $18, $19, 0 // record bytes to be transferred
541    sub $21, $21, $19 // decrement data count
542
543_ep0_fifo_write_loop:
544    lbu $9, 0($20) // read data
545    sb $9, 0x20($27) // load FIFO
546    sub $19, $19, 1 // decrement counter
547    bnez $19, _ep0_fifo_write_loop
548    addi $20, $20, 1 // increment data pointer
549
550    sub $9, $18, 64 // max packetsize
551    beqz $9, _ep0_tx_state4
552    nop
553
554_ep0_tx_state3:
555    // transferred bytes < max packetsize
556    li $9, 0x0a // set INPKTRDY and DATAEND
557    sb $9, 0x12($27) // CSR0
558    li $22, 0 // set EP0 to IDLE state
559    b check_intr_ep1in
560    nop
561
562_ep0_tx_state4:
563    // transferred bytes == max packetsize
564    li $9, 0x02 // set INPKTRDY
565    sb $9, 0x12($27) // CSR0
566    b check_intr_ep1in
567    nop
568
569    //--------------------------------------------------------------
570    // 3. Check and handle EP1 BULK-IN interrupt
571    //--------------------------------------------------------------
572check_intr_ep1in:
573    andi $9, $10, 0x2 // check EP1 IN interrupt
574    beqz $9, check_intr_ep1out
575    nop
576
577handle_epin1_intr:
578    li $9, 1
579    sb $9, 0x0e($27) // set INDEX 1
580    lbu $9, 0x12($27) // read INCSR
581
582    andi $8, $9, 0x2 // check INCSR_FFNOTEMPT
583    bnez $8, _epin1_tx_state4
584    nop
585
586_epin1_write_fifo:
587    lhu $9, 0x10($27) // get INMAXP
588    sub $8, $21, $9
589    blez $8, _epin1_tx_state1 // bytes left <= INMAXP
590    ori $19, $21, 0
591    ori $19, $9, 0
592
593_epin1_tx_state1:
594    beqz $19, _epin1_tx_state4 // No data
595    nop
596
597    sub $21, $21, $19 // decrement data count
598
599    srl $5, $19, 2 // # of word
600    andi $6, $19, 0x3 // # of byte
601    beqz $5, _epin1_tx_state2
602    nop
603
604_epin1_fifo_write_word:
605    lw $9, 0($20) // read data from source address
606    sw $9, 0x24($27) // write FIFO
607    sub $5, $5, 1 // decrement counter
608    bnez $5, _epin1_fifo_write_word
609    addiu $20, $20, 4 // increment dest address
610
611_epin1_tx_state2:
612    beqz $6, _epin1_tx_state3
613    nop
614
615_epin1_fifo_write_byte:
616    lbu $9, 0($20) // read data from source address
617    sb $9, 0x24($27) // write FIFO
618    sub $6, $6, 1 // decrement counter
619    bnez $6, _epin1_fifo_write_byte
620    addiu $20, $20, 1 // increment dest address
621
622_epin1_tx_state3:
623    li $9, 0x1
624    sb $9, 0x12($27) // INCSR, set INPKTRDY
625
626_epin1_tx_state4:
627    // nop
628
629    //--------------------------------------------------------------
630    // 4. Check and handle EP1 BULK-OUT interrupt
631    //--------------------------------------------------------------
632check_intr_ep1out:
633    lhu $9, 0x04($27) // read INTROUT
634    andi $9, 0x2
635    beqz $9, check_status_next
636    nop
637
638handle_epout1_intr:
639    li $9, 1
640    sb $9, 0x0e($27) // set INDEX 1
641
642    lbu $9, 0x16($27) // read OUTCSR
643    andi $9, 0x1 // check OUTPKTRDY
644    beqz $9, check_status_next
645    nop
646
647_epout1_read_fifo:
648    lhu $19, 0x18($27) // read OUTCOUNT
649    srl $5, $19, 2 // # of word
650    andi $6, $19, 0x3 // # of byte
651    beqz $5, _epout1_rx_state1
652    nop
653
654_epout1_fifo_read_word:
655    lw $9, 0x24($27) // read FIFO
656    sw $9, 0($20) // store to dest address
657    sub $5, $5, 1 // decrement counter
658    bnez $5, _epout1_fifo_read_word
659    addiu $20, $20, 4 // increment dest address
660
661_epout1_rx_state1:
662    beqz $6, _epout1_rx_state2
663    nop
664
665_epout1_fifo_read_byte:
666    lbu $9, 0x24($27) // read FIFO
667    sb $9, 0($20) // store to dest address
668    sub $6, $6, 1 // decrement counter
669    bnez $6, _epout1_fifo_read_byte
670    addiu $20, $20, 1 // increment dest address
671
672_epout1_rx_state2:
673    sb $0, 0x16($27) // clear OUTPKTRDY
674
675check_status_next:
676    b usb_command_loop
677    nop
678
679//--------------------------------------------------------------
680// Device/Configuration/Interface/Endpoint/String Descriptors
681//--------------------------------------------------------------
682
683    .align 2
684device_desc:
685    .byte 0x12 // bLength
686    .byte 0x01 // bDescriptorType
687    .byte 0x00 // bcdUSB
688    .byte 0x02 // bcdUSB
689    .byte 0x00 // bDeviceClass
690    .byte 0x00 // bDeviceSubClass
691    .byte 0x00 // bDeviceProtocol
692    .byte 0x40 // bMaxPacketSize0
693    .byte 0x1a // idVendor
694    .byte 0x60 // idVendor
695    .byte 0x40 // idProduct
696    .byte 0x47 // idProduct
697    .byte 0x00 // bcdDevice
698    .byte 0x01 // bcdDevice
699    .byte 0x01 // iManufacturer
700    .byte 0x02 // iProduct
701    .byte 0x00 // iSerialNumber
702    .byte 0x01 // bNumConfigurations
703
704    .align 2
705dev_qualifier:
706    .byte 0x0a // bLength
707    .byte 0x06 // bDescriptorType
708    .byte 0x00 // bcdUSB
709    .byte 0x02 // bcdUSB
710    .byte 0x00 // bDeviceClass
711    .byte 0x00 // bDeviceSubClass
712    .byte 0x00 // bDeviceProtocol
713    .byte 0x40 // bMaxPacketSize0
714    .byte 0x01 // bNumConfigurations
715    .byte 0x00 // bRESERVED
716
717    .align 2
718config_desc_hs:
719    .byte 0x09 // bLength
720    .byte 0x02 // bDescriptorType
721    .byte 0x20 // wTotalLength
722    .byte 0x00 // wTotalLength
723    .byte 0x01 // bNumInterfaces
724    .byte 0x01 // bConfigurationValue
725    .byte 0x00 // iConfiguration
726    .byte 0xc0 // bmAttributes
727    .byte 0x01 // MaxPower
728intf_desc_hs:
729    .byte 0x09 // bLength
730    .byte 0x04 // bDescriptorType
731    .byte 0x00 // bInterfaceNumber
732    .byte 0x00 // bAlternateSetting
733    .byte 0x02 // bNumEndpoints
734    .byte 0xff // bInterfaceClass
735    .byte 0x00 // bInterfaceSubClass
736    .byte 0x50 // bInterfaceProtocol
737    .byte 0x00 // iInterface
738ep1_desc_hs:
739    .byte 0x07 // bLength
740    .byte 0x05 // bDescriptorType
741    .byte 0x01 // bEndpointAddress
742    .byte 0x02 // bmAttributes
743    .byte 0x00 // wMaxPacketSize
744    .byte 0x02 // wMaxPacketSize
745    .byte 0x00 // bInterval
746ep2_desc_hs:
747    .byte 0x07 // bLength
748    .byte 0x05 // bDescriptorType
749    .byte 0x81 // bEndpointAddress
750    .byte 0x02 // bmAttributes
751    .byte 0x00 // wMaxPacketSize
752    .byte 0x02 // wMaxPacketSize
753    .byte 0x00 // bInterval
754
755    .align 2
756config_desc_fs:
757    .byte 0x09 // bLength
758    .byte 0x02 // bDescriptorType
759    .byte 0x20 // wTotalLength
760    .byte 0x00 // wTotalLength
761    .byte 0x01 // bNumInterfaces
762    .byte 0x01 // bConfigurationValue
763    .byte 0x00 // iConfiguration
764    .byte 0xc0 // bmAttributes
765    .byte 0x01 // MaxPower
766intf_desc_fs:
767    .byte 0x09 // bLength
768    .byte 0x04 // bDescriptorType
769    .byte 0x00 // bInterfaceNumber
770    .byte 0x00 // bAlternateSetting
771    .byte 0x02 // bNumEndpoints
772    .byte 0xff // bInterfaceClass
773    .byte 0x00 // bInterfaceSubClass
774    .byte 0x50 // bInterfaceProtocol
775    .byte 0x00 // iInterface
776ep1_desc_fs:
777    .byte 0x07 // bLength
778    .byte 0x05 // bDescriptorType
779    .byte 0x01 // bEndpointAddress
780    .byte 0x02 // bmAttributes
781    .byte 0x40 // wMaxPacketSize
782    .byte 0x00 // wMaxPacketSize
783    .byte 0x00 // bInterval
784ep2_desc_fs:
785    .byte 0x07 // bLength
786    .byte 0x05 // bDescriptorType
787    .byte 0x81 // bEndpointAddress
788    .byte 0x02 // bmAttributes
789    .byte 0x40 // wMaxPacketSize
790    .byte 0x00 // wMaxPacketSize
791    .byte 0x00 // bInterval
792
793    .align 2
794string_lang_ids:
795    .byte 0x04
796    .byte 0x03
797    .byte 0x09
798    .byte 0x04
799
800    .align 2
801string_manufacture:
802    .byte 0x10
803    .byte 0x03
804    .byte 0x49
805    .byte 0x00
806    .byte 0x6e
807    .byte 0x00
808    .byte 0x67
809    .byte 0x00
810    .byte 0x65
811    .byte 0x00
812    .byte 0x6e
813    .byte 0x00
814    .byte 0x69
815    .byte 0x00
816    .byte 0x63
817    .byte 0x00
818
819    .align 2
820string_product:
821    .byte 0x2e
822    .byte 0x03
823    .byte 0x4a
824    .byte 0x00
825    .byte 0x5a
826    .byte 0x00
827    .byte 0x34
828    .byte 0x00
829    .byte 0x37
830    .byte 0x00
831    .byte 0x34
832    .byte 0x00
833    .byte 0x30
834    .byte 0x00
835    .byte 0x20
836    .byte 0x00
837    .byte 0x55
838    .byte 0x00
839    .byte 0x53
840    .byte 0x00
841    .byte 0x42
842    .byte 0x00
843    .byte 0x20
844    .byte 0x00
845    .byte 0x42
846    .byte 0x00
847    .byte 0x6f
848    .byte 0x00
849    .byte 0x6f
850    .byte 0x00
851    .byte 0x74
852    .byte 0x00
853    .byte 0x20
854    .byte 0x00
855    .byte 0x44
856    .byte 0x00
857    .byte 0x65
858    .byte 0x00
859    .byte 0x76
860    .byte 0x00
861    .byte 0x69
862    .byte 0x00
863    .byte 0x63
864    .byte 0x00
865    .byte 0x65
866    .byte 0x00
867
868    .align 2
869cpu_info_data:
870    .byte 0x4a
871    .byte 0x5a
872    .byte 0x34
873    .byte 0x37
874    .byte 0x34
875    .byte 0x30
876    .byte 0x56
877    .byte 0x31
878usbboot_end:
879
880    .set reorder
package/uboot-xburst/files/arch/mips/include/asm/jz4740.h
1/*
2 * Include file for Ingenic Semiconductor's JZ4740 CPU.
3 */
4#ifndef __JZ4740_H__
5#define __JZ4740_H__
6
7#include <asm/addrspace.h>
8#include <asm/cacheops.h>
9
10#ifndef __ASSEMBLY__
11#define cache_unroll(base,op) \
12    __asm__ __volatile__(" \
13        .set noreorder; \
14        .set mips3; \
15        cache %1, (%0); \
16        .set mips0; \
17        .set reorder" \
18        : \
19        : "r" (base), \
20          "i" (op));
21
22static inline void jz_flush_dcache(void)
23{
24    unsigned long start;
25    unsigned long end;
26
27    start = KSEG0;
28    end = start + CONFIG_SYS_DCACHE_SIZE;
29    while (start < end) {
30        cache_unroll(start,Index_Writeback_Inv_D);
31        start += CONFIG_SYS_CACHELINE_SIZE;
32    }
33}
34
35static inline void jz_flush_icache(void)
36{
37    unsigned long start;
38    unsigned long end;
39
40    start = KSEG0;
41    end = start + CONFIG_SYS_ICACHE_SIZE;
42    while(start < end) {
43        cache_unroll(start,Index_Invalidate_I);
44        start += CONFIG_SYS_CACHELINE_SIZE;
45    }
46}
47
48#define REG8(addr) *((volatile u8 *)(addr))
49#define REG16(addr) *((volatile u16 *)(addr))
50#define REG32(addr) *((volatile u32 *)(addr))
51
52#endif /* !ASSEMBLY */
53
54/* Boot ROM Specification */
55/* NOR Boot config */
56#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
57#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
58#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
59
60/* NAND Boot config */
61#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
62#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
63#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
64#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
65
66
67/* Register Definitions */
68#define CPM_BASE 0xB0000000
69#define INTC_BASE 0xB0001000
70#define TCU_BASE 0xB0002000
71#define WDT_BASE 0xB0002000
72#define RTC_BASE 0xB0003000
73#define GPIO_BASE 0xB0010000
74#define AIC_BASE 0xB0020000
75#define ICDC_BASE 0xB0020000
76#define MSC_BASE 0xB0021000
77#define UART0_BASE 0xB0030000
78#define I2C_BASE 0xB0042000
79#define SSI_BASE 0xB0043000
80#define SADC_BASE 0xB0070000
81#define EMC_BASE 0xB3010000
82#define DMAC_BASE 0xB3020000
83#define UHC_BASE 0xB3030000
84#define UDC_BASE 0xB3040000
85#define LCD_BASE 0xB3050000
86#define SLCD_BASE 0xB3050000
87#define CIM_BASE 0xB3060000
88#define ETH_BASE 0xB3100000
89
90
91/*
92 * INTC (Interrupt Controller)
93 */
94#define INTC_ISR (INTC_BASE + 0x00)
95#define INTC_IMR (INTC_BASE + 0x04)
96#define INTC_IMSR (INTC_BASE + 0x08)
97#define INTC_IMCR (INTC_BASE + 0x0c)
98#define INTC_IPR (INTC_BASE + 0x10)
99
100#define REG_INTC_ISR REG32(INTC_ISR)
101#define REG_INTC_IMR REG32(INTC_IMR)
102#define REG_INTC_IMSR REG32(INTC_IMSR)
103#define REG_INTC_IMCR REG32(INTC_IMCR)
104#define REG_INTC_IPR REG32(INTC_IPR)
105
106/* 1st-level interrupts */
107#define IRQ_I2C 1
108#define IRQ_UHC 3
109#define IRQ_UART0 9
110#define IRQ_SADC 12
111#define IRQ_MSC 14
112#define IRQ_RTC 15
113#define IRQ_SSI 16
114#define IRQ_CIM 17
115#define IRQ_AIC 18
116#define IRQ_ETH 19
117#define IRQ_DMAC 20
118#define IRQ_TCU2 21
119#define IRQ_TCU1 22
120#define IRQ_TCU0 23
121#define IRQ_UDC 24
122#define IRQ_GPIO3 25
123#define IRQ_GPIO2 26
124#define IRQ_GPIO1 27
125#define IRQ_GPIO0 28
126#define IRQ_IPU 29
127#define IRQ_LCD 30
128
129/* 2nd-level interrupts */
130#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
131#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
132
133
134/*
135 * RTC
136 */
137#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
138#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
139#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
140#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
141
142#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
143#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
144#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
145#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
146#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
147#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
148
149#define REG_RTC_RCR REG32(RTC_RCR)
150#define REG_RTC_RSR REG32(RTC_RSR)
151#define REG_RTC_RSAR REG32(RTC_RSAR)
152#define REG_RTC_RGR REG32(RTC_RGR)
153#define REG_RTC_HCR REG32(RTC_HCR)
154#define REG_RTC_HWFCR REG32(RTC_HWFCR)
155#define REG_RTC_HRCR REG32(RTC_HRCR)
156#define REG_RTC_HWCR REG32(RTC_HWCR)
157#define REG_RTC_HWRSR REG32(RTC_HWRSR)
158#define REG_RTC_HSPR REG32(RTC_HSPR)
159
160/* RTC Control Register */
161#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
162#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
163#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
164#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
165#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
166#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
167#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
168
169/* RTC Regulator Register */
170#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
171#define RTC_RGR_ADJC_BIT 16
172#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
173#define RTC_RGR_NC1HZ_BIT 0
174#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
175
176/* Hibernate Control Register */
177#define RTC_HCR_PD (1 << 0) /* Power Down */
178
179/* Hibernate Wakeup Filter Counter Register */
180#define RTC_HWFCR_BIT 5
181#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
182
183/* Hibernate Reset Counter Register */
184#define RTC_HRCR_BIT 5
185#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
186
187/* Hibernate Wakeup Control Register */
188#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
189
190/* Hibernate Wakeup Status Register */
191#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
192#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
193#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
194#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
195
196/*************************************************************************
197 * CPM (Clock reset and Power control Management)
198 *************************************************************************/
199#define CPM_CPCCR (CPM_BASE+0x00)
200#define CPM_CPPCR (CPM_BASE+0x10)
201#define CPM_I2SCDR (CPM_BASE+0x60)
202#define CPM_LPCDR (CPM_BASE+0x64)
203#define CPM_MSCCDR (CPM_BASE+0x68)
204#define CPM_UHCCDR (CPM_BASE+0x6C)
205
206#define CPM_LCR (CPM_BASE+0x04)
207#define CPM_CLKGR (CPM_BASE+0x20)
208#define CPM_SCR (CPM_BASE+0x24)
209
210#define CPM_HCR (CPM_BASE+0x30)
211#define CPM_HWFCR (CPM_BASE+0x34)
212#define CPM_HRCR (CPM_BASE+0x38)
213#define CPM_HWCR (CPM_BASE+0x3c)
214#define CPM_HWSR (CPM_BASE+0x40)
215#define CPM_HSPR (CPM_BASE+0x44)
216
217#define CPM_RSR (CPM_BASE+0x08)
218
219
220#define REG_CPM_CPCCR REG32(CPM_CPCCR)
221#define REG_CPM_CPPCR REG32(CPM_CPPCR)
222#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
223#define REG_CPM_LPCDR REG32(CPM_LPCDR)
224#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
225#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
226
227#define REG_CPM_LCR REG32(CPM_LCR)
228#define REG_CPM_CLKGR REG32(CPM_CLKGR)
229#define REG_CPM_SCR REG32(CPM_SCR)
230#define REG_CPM_HCR REG32(CPM_HCR)
231#define REG_CPM_HWFCR REG32(CPM_HWFCR)
232#define REG_CPM_HRCR REG32(CPM_HRCR)
233#define REG_CPM_HWCR REG32(CPM_HWCR)
234#define REG_CPM_HWSR REG32(CPM_HWSR)
235#define REG_CPM_HSPR REG32(CPM_HSPR)
236
237#define REG_CPM_RSR REG32(CPM_RSR)
238
239
240/* Clock Control Register */
241#define CPM_CPCCR_I2CS (1 << 31)
242#define CPM_CPCCR_CLKOEN (1 << 30)
243#define CPM_CPCCR_UCS (1 << 29)
244#define CPM_CPCCR_UDIV_BIT 23
245#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
246#define CPM_CPCCR_CE (1 << 22)
247#define CPM_CPCCR_PCS (1 << 21)
248#define CPM_CPCCR_LDIV_BIT 16
249#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
250#define CPM_CPCCR_MDIV_BIT 12
251#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
252#define CPM_CPCCR_PDIV_BIT 8
253#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
254#define CPM_CPCCR_HDIV_BIT 4
255#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
256#define CPM_CPCCR_CDIV_BIT 0
257#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
258
259/* I2S Clock Divider Register */
260#define CPM_I2SCDR_I2SDIV_BIT 0
261#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
262
263/* LCD Pixel Clock Divider Register */
264#define CPM_LPCDR_PIXDIV_BIT 0
265#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
266
267/* MSC Clock Divider Register */
268#define CPM_MSCCDR_MSCDIV_BIT 0
269#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
270
271/* PLL Control Register */
272#define CPM_CPPCR_PLLM_BIT 23
273#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
274#define CPM_CPPCR_PLLN_BIT 18
275#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
276#define CPM_CPPCR_PLLOD_BIT 16
277#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
278#define CPM_CPPCR_PLLS (1 << 10)
279#define CPM_CPPCR_PLLBP (1 << 9)
280#define CPM_CPPCR_PLLEN (1 << 8)
281#define CPM_CPPCR_PLLST_BIT 0
282#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
283
284/* Low Power Control Register */
285#define CPM_LCR_DOZE_DUTY_BIT 3
286#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
287#define CPM_LCR_DOZE_ON (1 << 2)
288#define CPM_LCR_LPM_BIT 0
289#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
290  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
291  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
292
293/* Clock Gate Register */
294#define CPM_CLKGR_UART1 (1 << 15)
295#define CPM_CLKGR_UHC (1 << 14)
296#define CPM_CLKGR_IPU (1 << 13)
297#define CPM_CLKGR_DMAC (1 << 12)
298#define CPM_CLKGR_UDC (1 << 11)
299#define CPM_CLKGR_LCD (1 << 10)
300#define CPM_CLKGR_CIM (1 << 9)
301#define CPM_CLKGR_SADC (1 << 8)
302#define CPM_CLKGR_MSC (1 << 7)
303#define CPM_CLKGR_AIC1 (1 << 6)
304#define CPM_CLKGR_AIC2 (1 << 5)
305#define CPM_CLKGR_SSI (1 << 4)
306#define CPM_CLKGR_I2C (1 << 3)
307#define CPM_CLKGR_RTC (1 << 2)
308#define CPM_CLKGR_TCU (1 << 1)
309#define CPM_CLKGR_UART0 (1 << 0)
310
311/* Sleep Control Register */
312#define CPM_SCR_O1ST_BIT 8
313#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
314#define CPM_SCR_UDCPHY_ENABLE (1 << 6)
315#define CPM_SCR_USBPHY_DISABLE (1 << 7)
316#define CPM_SCR_OSC_ENABLE (1 << 4)
317
318/* Hibernate Control Register */
319#define CPM_HCR_PD (1 << 0)
320
321/* Wakeup Filter Counter Register in Hibernate Mode */
322#define CPM_HWFCR_TIME_BIT 0
323#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
324
325/* Reset Counter Register in Hibernate Mode */
326#define CPM_HRCR_TIME_BIT 0
327#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
328
329/* Wakeup Control Register in Hibernate Mode */
330#define CPM_HWCR_WLE_LOW (0 << 2)
331#define CPM_HWCR_WLE_HIGH (1 << 2)
332#define CPM_HWCR_PIN_WAKEUP (1 << 1)
333#define CPM_HWCR_RTC_WAKEUP (1 << 0)
334
335/* Wakeup Status Register in Hibernate Mode */
336#define CPM_HWSR_WSR_PIN (1 << 1)
337#define CPM_HWSR_WSR_RTC (1 << 0)
338
339/* Reset Status Register */
340#define CPM_RSR_HR (1 << 2)
341#define CPM_RSR_WR (1 << 1)
342#define CPM_RSR_PR (1 << 0)
343
344
345/*************************************************************************
346 * TCU (Timer Counter Unit)
347 *************************************************************************/
348#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
349#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
350#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
351#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
352#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
353#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
354#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
355#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
356#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
357#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
358#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
359#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
360#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
361#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
362#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
363#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
364#define TCU_TDFR1 (TCU_BASE + 0x50)
365#define TCU_TDHR1 (TCU_BASE + 0x54)
366#define TCU_TCNT1 (TCU_BASE + 0x58)
367#define TCU_TCSR1 (TCU_BASE + 0x5C)
368#define TCU_TDFR2 (TCU_BASE + 0x60)
369#define TCU_TDHR2 (TCU_BASE + 0x64)
370#define TCU_TCNT2 (TCU_BASE + 0x68)
371#define TCU_TCSR2 (TCU_BASE + 0x6C)
372#define TCU_TDFR3 (TCU_BASE + 0x70)
373#define TCU_TDHR3 (TCU_BASE + 0x74)
374#define TCU_TCNT3 (TCU_BASE + 0x78)
375#define TCU_TCSR3 (TCU_BASE + 0x7C)
376#define TCU_TDFR4 (TCU_BASE + 0x80)
377#define TCU_TDHR4 (TCU_BASE + 0x84)
378#define TCU_TCNT4 (TCU_BASE + 0x88)
379#define TCU_TCSR4 (TCU_BASE + 0x8C)
380#define TCU_TDFR5 (TCU_BASE + 0x90)
381#define TCU_TDHR5 (TCU_BASE + 0x94)
382#define TCU_TCNT5 (TCU_BASE + 0x98)
383#define TCU_TCSR5 (TCU_BASE + 0x9C)
384
385#define REG_TCU_TSR REG32(TCU_TSR)
386#define REG_TCU_TSSR REG32(TCU_TSSR)
387#define REG_TCU_TSCR REG32(TCU_TSCR)
388#define REG_TCU_TER REG8(TCU_TER)
389#define REG_TCU_TESR REG8(TCU_TESR)
390#define REG_TCU_TECR REG8(TCU_TECR)
391#define REG_TCU_TFR REG32(TCU_TFR)
392#define REG_TCU_TFSR REG32(TCU_TFSR)
393#define REG_TCU_TFCR REG32(TCU_TFCR)
394#define REG_TCU_TMR REG32(TCU_TMR)
395#define REG_TCU_TMSR REG32(TCU_TMSR)
396#define REG_TCU_TMCR REG32(TCU_TMCR)
397#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
398#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
399#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
400#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
401#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
402#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
403#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
404#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
405#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
406#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
407#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
408#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
409#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
410#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
411#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
412#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
413#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
414#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
415#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
416#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
417
418/* n = 0,1,2,3,4,5 */
419#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
420#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
421#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
422#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
423
424#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
425#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
426#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
427#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
428
429/* Register definitions */
430#define TCU_TCSR_PWM_SD (1 << 9)
431#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
432#define TCU_TCSR_PWM_EN (1 << 7)
433#define TCU_TCSR_PRESCALE_BIT 3
434#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
435#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
436#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
437#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
438#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
439#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
440#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
441#define TCU_TCSR_EXT_EN (1 << 2)
442#define TCU_TCSR_RTC_EN (1 << 1)
443#define TCU_TCSR_PCK_EN (1 << 0)
444
445#define TCU_TER_TCEN5 (1 << 5)
446#define TCU_TER_TCEN4 (1 << 4)
447#define TCU_TER_TCEN3 (1 << 3)
448#define TCU_TER_TCEN2 (1 << 2)
449#define TCU_TER_TCEN1 (1 << 1)
450#define TCU_TER_TCEN0 (1 << 0)
451
452#define TCU_TESR_TCST5 (1 << 5)
453#define TCU_TESR_TCST4 (1 << 4)
454#define TCU_TESR_TCST3 (1 << 3)
455#define TCU_TESR_TCST2 (1 << 2)
456#define TCU_TESR_TCST1 (1 << 1)
457#define TCU_TESR_TCST0 (1 << 0)
458
459#define TCU_TECR_TCCL5 (1 << 5)
460#define TCU_TECR_TCCL4 (1 << 4)
461#define TCU_TECR_TCCL3 (1 << 3)
462#define TCU_TECR_TCCL2 (1 << 2)
463#define TCU_TECR_TCCL1 (1 << 1)
464#define TCU_TECR_TCCL0 (1 << 0)
465
466#define TCU_TFR_HFLAG5 (1 << 21)
467#define TCU_TFR_HFLAG4 (1 << 20)
468#define TCU_TFR_HFLAG3 (1 << 19)
469#define TCU_TFR_HFLAG2 (1 << 18)
470#define TCU_TFR_HFLAG1 (1 << 17)
471#define TCU_TFR_HFLAG0 (1 << 16)
472#define TCU_TFR_FFLAG5 (1 << 5)
473#define TCU_TFR_FFLAG4 (1 << 4)
474#define TCU_TFR_FFLAG3 (1 << 3)
475#define TCU_TFR_FFLAG2 (1 << 2)
476#define TCU_TFR_FFLAG1 (1 << 1)
477#define TCU_TFR_FFLAG0 (1 << 0)
478
479#define TCU_TFSR_HFLAG5 (1 << 21)
480#define TCU_TFSR_HFLAG4 (1 << 20)
481#define TCU_TFSR_HFLAG3 (1 << 19)
482#define TCU_TFSR_HFLAG2 (1 << 18)
483#define TCU_TFSR_HFLAG1 (1 << 17)
484#define TCU_TFSR_HFLAG0 (1 << 16)
485#define TCU_TFSR_FFLAG5 (1 << 5)
486#define TCU_TFSR_FFLAG4 (1 << 4)
487#define TCU_TFSR_FFLAG3 (1 << 3)
488#define TCU_TFSR_FFLAG2 (1 << 2)
489#define TCU_TFSR_FFLAG1 (1 << 1)
490#define TCU_TFSR_FFLAG0 (1 << 0)
491
492#define TCU_TFCR_HFLAG5 (1 << 21)
493#define TCU_TFCR_HFLAG4 (1 << 20)
494#define TCU_TFCR_HFLAG3 (1 << 19)
495#define TCU_TFCR_HFLAG2 (1 << 18)
496#define TCU_TFCR_HFLAG1 (1 << 17)
497#define TCU_TFCR_HFLAG0 (1 << 16)
498#define TCU_TFCR_FFLAG5 (1 << 5)
499#define TCU_TFCR_FFLAG4 (1 << 4)
500#define TCU_TFCR_FFLAG3 (1 << 3)
501#define TCU_TFCR_FFLAG2 (1 << 2)
502#define TCU_TFCR_FFLAG1 (1 << 1)
503#define TCU_TFCR_FFLAG0 (1 << 0)
504
505#define TCU_TMR_HMASK5 (1 << 21)
506#define TCU_TMR_HMASK4 (1 << 20)
507#define TCU_TMR_HMASK3 (1 << 19)
508#define TCU_TMR_HMASK2 (1 << 18)
509#define TCU_TMR_HMASK1 (1 << 17)
510#define TCU_TMR_HMASK0 (1 << 16)
511#define TCU_TMR_FMASK5 (1 << 5)
512#define TCU_TMR_FMASK4 (1 << 4)
513#define TCU_TMR_FMASK3 (1 << 3)
514#define TCU_TMR_FMASK2 (1 << 2)
515#define TCU_TMR_FMASK1 (1 << 1)
516#define TCU_TMR_FMASK0 (1 << 0)
517
518#define TCU_TMSR_HMST5 (1 << 21)
519#define TCU_TMSR_HMST4 (1 << 20)
520#define TCU_TMSR_HMST3 (1 << 19)
521#define TCU_TMSR_HMST2 (1 << 18)
522#define TCU_TMSR_HMST1 (1 << 17)
523#define TCU_TMSR_HMST0 (1 << 16)
524#define TCU_TMSR_FMST5 (1 << 5)
525#define TCU_TMSR_FMST4 (1 << 4)
526#define TCU_TMSR_FMST3 (1 << 3)
527#define TCU_TMSR_FMST2 (1 << 2)
528#define TCU_TMSR_FMST1 (1 << 1)
529#define TCU_TMSR_FMST0 (1 << 0)
530
531#define TCU_TMCR_HMCL5 (1 << 21)
532#define TCU_TMCR_HMCL4 (1 << 20)
533#define TCU_TMCR_HMCL3 (1 << 19)
534#define TCU_TMCR_HMCL2 (1 << 18)
535#define TCU_TMCR_HMCL1 (1 << 17)
536#define TCU_TMCR_HMCL0 (1 << 16)
537#define TCU_TMCR_FMCL5 (1 << 5)
538#define TCU_TMCR_FMCL4 (1 << 4)
539#define TCU_TMCR_FMCL3 (1 << 3)
540#define TCU_TMCR_FMCL2 (1 << 2)
541#define TCU_TMCR_FMCL1 (1 << 1)
542#define TCU_TMCR_FMCL0 (1 << 0)
543
544#define TCU_TSR_WDTS (1 << 16)
545#define TCU_TSR_STOP5 (1 << 5)
546#define TCU_TSR_STOP4 (1 << 4)
547#define TCU_TSR_STOP3 (1 << 3)
548#define TCU_TSR_STOP2 (1 << 2)
549#define TCU_TSR_STOP1 (1 << 1)
550#define TCU_TSR_STOP0 (1 << 0)
551
552#define TCU_TSSR_WDTSS (1 << 16)
553#define TCU_TSSR_STPS5 (1 << 5)
554#define TCU_TSSR_STPS4 (1 << 4)
555#define TCU_TSSR_STPS3 (1 << 3)
556#define TCU_TSSR_STPS2 (1 << 2)
557#define TCU_TSSR_STPS1 (1 << 1)
558#define TCU_TSSR_STPS0 (1 << 0)
559
560#define TCU_TSSR_WDTSC (1 << 16)
561#define TCU_TSSR_STPC5 (1 << 5)
562#define TCU_TSSR_STPC4 (1 << 4)
563#define TCU_TSSR_STPC3 (1 << 3)
564#define TCU_TSSR_STPC2 (1 << 2)
565#define TCU_TSSR_STPC1 (1 << 1)
566#define TCU_TSSR_STPC0 (1 << 0)
567
568
569/*
570 * WDT (WatchDog Timer)
571 */
572#define WDT_TDR (WDT_BASE + 0x00)
573#define WDT_TCER (WDT_BASE + 0x04)
574#define WDT_TCNT (WDT_BASE + 0x08)
575#define WDT_TCSR (WDT_BASE + 0x0C)
576
577#define REG_WDT_TDR REG16(WDT_TDR)
578#define REG_WDT_TCER REG8(WDT_TCER)
579#define REG_WDT_TCNT REG16(WDT_TCNT)
580#define REG_WDT_TCSR REG16(WDT_TCSR)
581
582/* Register definition */
583#define WDT_TCSR_PRESCALE_BIT 3
584#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
585  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
586  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
587  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
588  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
589  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
590  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
591#define WDT_TCSR_EXT_EN (1 << 2)
592#define WDT_TCSR_RTC_EN (1 << 1)
593#define WDT_TCSR_PCK_EN (1 << 0)
594
595#define WDT_TCER_TCEN (1 << 0)
596
597
598/*
599 * DMAC (DMA Controller)
600 */
601
602#define MAX_DMA_NUM 6 /* max 6 channels */
603
604#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
605#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
606#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
607#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
608#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
609#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
610#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
611#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
612#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
613#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
614#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
615
616/* channel 0 */
617#define DMAC_DSAR0 DMAC_DSAR(0)
618#define DMAC_DTAR0 DMAC_DTAR(0)
619#define DMAC_DTCR0 DMAC_DTCR(0)
620#define DMAC_DRSR0 DMAC_DRSR(0)
621#define DMAC_DCCSR0 DMAC_DCCSR(0)
622#define DMAC_DCMD0 DMAC_DCMD(0)
623#define DMAC_DDA0 DMAC_DDA(0)
624
625/* channel 1 */
626#define DMAC_DSAR1 DMAC_DSAR(1)
627#define DMAC_DTAR1 DMAC_DTAR(1)
628#define DMAC_DTCR1 DMAC_DTCR(1)
629#define DMAC_DRSR1 DMAC_DRSR(1)
630#define DMAC_DCCSR1 DMAC_DCCSR(1)
631#define DMAC_DCMD1 DMAC_DCMD(1)
632#define DMAC_DDA1 DMAC_DDA(1)
633
634/* channel 2 */
635#define DMAC_DSAR2 DMAC_DSAR(2)
636#define DMAC_DTAR2 DMAC_DTAR(2)
637#define DMAC_DTCR2 DMAC_DTCR(2)
638#define DMAC_DRSR2 DMAC_DRSR(2)
639#define DMAC_DCCSR2 DMAC_DCCSR(2)
640#define DMAC_DCMD2 DMAC_DCMD(2)
641#define DMAC_DDA2 DMAC_DDA(2)
642
643/* channel 3 */
644#define DMAC_DSAR3 DMAC_DSAR(3)
645#define DMAC_DTAR3 DMAC_DTAR(3)
646#define DMAC_DTCR3 DMAC_DTCR(3)
647#define DMAC_DRSR3 DMAC_DRSR(3)
648#define DMAC_DCCSR3 DMAC_DCCSR(3)
649#define DMAC_DCMD3 DMAC_DCMD(3)
650#define DMAC_DDA3 DMAC_DDA(3)
651
652/* channel 4 */
653#define DMAC_DSAR4 DMAC_DSAR(4)
654#define DMAC_DTAR4 DMAC_DTAR(4)
655#define DMAC_DTCR4 DMAC_DTCR(4)
656#define DMAC_DRSR4 DMAC_DRSR(4)
657#define DMAC_DCCSR4 DMAC_DCCSR(4)
658#define DMAC_DCMD4 DMAC_DCMD(4)
659#define DMAC_DDA4 DMAC_DDA(4)
660
661/* channel 5 */
662#define DMAC_DSAR5 DMAC_DSAR(5)
663#define DMAC_DTAR5 DMAC_DTAR(5)
664#define DMAC_DTCR5 DMAC_DTCR(5)
665#define DMAC_DRSR5 DMAC_DRSR(5)
666#define DMAC_DCCSR5 DMAC_DCCSR(5)
667#define DMAC_DCMD5 DMAC_DCMD(5)
668#define DMAC_DDA5 DMAC_DDA(5)
669
670#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
671#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
672#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
673#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
674#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
675#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
676#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
677#define REG_DMAC_DMACR REG32(DMAC_DMACR)
678#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
679#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
680#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
681
682/* DMA request source register */
683#define DMAC_DRSR_RS_BIT 0
684#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
685#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
686#define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
687#define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
688#define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
689#define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
690#define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
691#define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
692#define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
693#define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
694#define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
695#define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
696#define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
697
698/* DMA channel control/status register */
699#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
700#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
701#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
702#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
703#define DMAC_DCCSR_AR (1 << 4) /* address error */
704#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
705#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
706#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
707#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
708
709/* DMA channel command register */
710#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
711#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
712#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
713#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
714  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
715  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
716  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
717  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
718  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
719  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
720  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
721  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
722  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
723  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
724  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
725  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
726  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
727  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
728  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
729  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
730#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
731#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
732  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
733  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
734  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
735#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
736#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
737  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
738  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
739  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
740#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
741#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
742  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
743  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
744  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
745  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
746  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
747#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
748#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
749#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
750#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
751#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
752#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
753
754/* DMA descriptor address register */
755#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
756#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
757#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
758#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
759
760/* DMA control register */
761#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
762#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
763  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
764  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
765  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
766  #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
767#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
768#define DMAC_DMACR_AR (1 << 2) /* address error flag */
769#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
770
771/* DMA doorbell register */
772#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
773#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
774#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
775#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
776#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
777#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
778
779/* DMA doorbell set register */
780#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
781#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
782#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
783#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
784#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
785#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
786
787/* DMA interrupt pending register */
788#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
789#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
790#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
791#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
792#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
793#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
794
795
796/*************************************************************************
797 * GPIO (General-Purpose I/O Ports)
798 *************************************************************************/
799#define MAX_GPIO_NUM 128
800
801/* = 0,1,2,3 */
802#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
803#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
804#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
805#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
806#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
807#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
808#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
809#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
810#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
811#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
812#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
813#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
814#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
815#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
816#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
817#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
818#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
819#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
820#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
821#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
822#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
823#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
824#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
825#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
826
827#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
828#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
829#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
830#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
831#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
832#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
833#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
834#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
835#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
836#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
837#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
838#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
839#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
840#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
841#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
842#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
843#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
844#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
845#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
846#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
847#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
848#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
849#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
850#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
851
852
853/*************************************************************************
854 * UART
855 *************************************************************************/
856
857#define IRDA_BASE UART0_BASE
858#define UART_BASE UART0_BASE
859#define UART_OFF 0x1000
860
861/* Register Offset */
862#define OFF_RDR (0x00) /* R 8b H'xx */
863#define OFF_TDR (0x00) /* W 8b H'xx */
864#define OFF_DLLR (0x00) /* RW 8b H'00 */
865#define OFF_DLHR (0x04) /* RW 8b H'00 */
866#define OFF_IER (0x04) /* RW 8b H'00 */
867#define OFF_ISR (0x08) /* R 8b H'01 */
868#define OFF_FCR (0x08) /* W 8b H'00 */
869#define OFF_LCR (0x0C) /* RW 8b H'00 */
870#define OFF_MCR (0x10) /* RW 8b H'00 */
871#define OFF_LSR (0x14) /* R 8b H'00 */
872#define OFF_MSR (0x18) /* R 8b H'00 */
873#define OFF_SPR (0x1C) /* RW 8b H'00 */
874#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
875#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
876#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
877
878/* Register Address */
879#define UART0_RDR (UART0_BASE + OFF_RDR)
880#define UART0_TDR (UART0_BASE + OFF_TDR)
881#define UART0_DLLR (UART0_BASE + OFF_DLLR)
882#define UART0_DLHR (UART0_BASE + OFF_DLHR)
883#define UART0_IER (UART0_BASE + OFF_IER)
884#define UART0_ISR (UART0_BASE + OFF_ISR)
885#define UART0_FCR (UART0_BASE + OFF_FCR)
886#define UART0_LCR (UART0_BASE + OFF_LCR)
887#define UART0_MCR (UART0_BASE + OFF_MCR)
888#define UART0_LSR (UART0_BASE + OFF_LSR)
889#define UART0_MSR (UART0_BASE + OFF_MSR)
890#define UART0_SPR (UART0_BASE + OFF_SPR)
891#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
892#define UART0_UMR (UART0_BASE + OFF_UMR)
893#define UART0_UACR (UART0_BASE + OFF_UACR)
894
895/*
896 * Define macros for UART_IER
897 * UART Interrupt Enable Register
898 */
899#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
900#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
901#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
902#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
903#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
904
905/*
906 * Define macros for UART_ISR
907 * UART Interrupt Status Register
908 */
909#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
910#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
911#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
912#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
913#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
914#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
915#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
916#define UART_ISR_FFMS_NO_FIFO (0 << 6)
917#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
918
919/*
920 * Define macros for UART_FCR
921 * UART FIFO Control Register
922 */
923#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
924#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
925#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
926#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
927#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
928#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
929#define UART_FCR_RTRG_1 (0 << 6)
930#define UART_FCR_RTRG_4 (1 << 6)
931#define UART_FCR_RTRG_8 (2 << 6)
932#define UART_FCR_RTRG_15 (3 << 6)
933
934/*
935 * Define macros for UART_LCR
936 * UART Line Control Register
937 */
938#define UART_LCR_WLEN (3 << 0) /* word length */
939#define UART_LCR_WLEN_5 (0 << 0)
940#define UART_LCR_WLEN_6 (1 << 0)
941#define UART_LCR_WLEN_7 (2 << 0)
942#define UART_LCR_WLEN_8 (3 << 0)
943#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
944                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
945#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
946                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
947#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
948                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
949
950#define UART_LCR_PE (1 << 3) /* 0: parity disable */
951#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
952#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
953#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
954#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
955
956/*
957 * Define macros for UART_LSR
958 * UART Line Status Register
959 */
960#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
961#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
962#define UART_LSR_PER (1 << 2) /* 0: no parity error */
963#define UART_LSR_FER (1 << 3) /* 0; no framing error */
964#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
965#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
966#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
967#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
968
969/*
970 * Define macros for UART_MCR
971 * UART Modem Control Register
972 */
973#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
974#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
975#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
976#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
977#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
978#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
979
980/*
981 * Define macros for UART_MSR
982 * UART Modem Status Register
983 */
984#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
985#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
986#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
987#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
988#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
989#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
990#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
991#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
992
993/*
994 * Define macros for SIRCR
995 * Slow IrDA Control Register
996 */
997#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
998#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
999#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1000                       1: 0 pulse width is 1.6us for 115.2Kbps */
1001#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1002#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1003
1004
1005/*************************************************************************
1006 * AIC (AC97/I2S Controller)
1007 *************************************************************************/
1008#define AIC_FR (AIC_BASE + 0x000)
1009#define AIC_CR (AIC_BASE + 0x004)
1010#define AIC_ACCR1 (AIC_BASE + 0x008)
1011#define AIC_ACCR2 (AIC_BASE + 0x00C)
1012#define AIC_I2SCR (AIC_BASE + 0x010)
1013#define AIC_SR (AIC_BASE + 0x014)
1014#define AIC_ACSR (AIC_BASE + 0x018)
1015#define AIC_I2SSR (AIC_BASE + 0x01C)
1016#define AIC_ACCAR (AIC_BASE + 0x020)
1017#define AIC_ACCDR (AIC_BASE + 0x024)
1018#define AIC_ACSAR (AIC_BASE + 0x028)
1019#define AIC_ACSDR (AIC_BASE + 0x02C)
1020#define AIC_I2SDIV (AIC_BASE + 0x030)
1021#define AIC_DR (AIC_BASE + 0x034)
1022
1023#define REG_AIC_FR REG32(AIC_FR)
1024#define REG_AIC_CR REG32(AIC_CR)
1025#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1026#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1027#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1028#define REG_AIC_SR REG32(AIC_SR)
1029#define REG_AIC_ACSR REG32(AIC_ACSR)
1030#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1031#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1032#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1033#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1034#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1035#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1036#define REG_AIC_DR REG32(AIC_DR)
1037
1038/* AIC Controller Configuration Register (AIC_FR) */
1039
1040#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1041#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1042#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1043#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1044#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1045#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1046#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1047#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1048#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1049#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1050
1051/* AIC Controller Common Control Register (AIC_CR) */
1052
1053#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1054#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1055  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1056  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1057  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1058  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1059  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1060#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1061#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1062  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1063  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1064  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1065  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1066  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1067#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1068#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1069#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1070#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1071#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1072#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1073#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1074#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1075#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1076#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1077#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1078#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1079#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1080
1081/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1082
1083#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1084#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1085  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1086  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1087  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1088  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1089  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1090  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1091  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1092  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1093  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1094  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1095#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1096#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1097  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1098  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1099  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1100  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1101  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1102  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1103  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1104  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1105  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1106  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1107
1108/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1109
1110#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1111#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1112#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1113#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1114#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1115  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1116  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1117  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1118  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1119#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1120#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1121  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1122  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1123  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1124  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1125#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1126#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1127#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1128#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1129
1130/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1131
1132#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1133#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1134#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1135  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1136  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1137  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1138  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1139  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1140#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1141
1142/* AIC Controller FIFO Status Register (AIC_SR) */
1143
1144#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1145#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1146#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1147#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1148#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1149#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1150#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1151#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1152
1153/* AIC Controller AC-link Status Register (AIC_ACSR) */
1154
1155#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1156#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1157#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1158#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1159#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1160#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1161
1162/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1163
1164#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1165
1166/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1167
1168#define AIC_ACCAR_CAR_BIT 0
1169#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1170
1171/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1172
1173#define AIC_ACCDR_CDR_BIT 0
1174#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1175
1176/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1177
1178#define AIC_ACSAR_SAR_BIT 0
1179#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1180
1181/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1182
1183#define AIC_ACSDR_SDR_BIT 0
1184#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1185
1186/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1187
1188#define AIC_I2SDIV_DIV_BIT 0
1189#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1190  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1191  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1192  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1193  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1194  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1195  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1196
1197
1198/*************************************************************************
1199 * ICDC (Internal CODEC)
1200 *************************************************************************/
1201#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1202#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1203#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1204#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1205#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1206#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1207#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1208
1209#define REG_ICDC_CR REG32(ICDC_CR)
1210#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1211#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1212#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1213#define REG_ICDC_APSR REG32(ICDC_APSR)
1214#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1215#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1216
1217/* ICDC Control Register */
1218#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1219#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1220#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1221#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1222  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1223  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1224  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1225  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1226  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1227  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1228  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1229  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1230  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1231#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1232#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1233  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1234  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1235  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1236  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1237#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1238#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1239  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1240  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1241  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1242  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1243#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1244#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1245#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1246#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1247#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1248#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1249#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1250#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1251#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1252#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1253#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1254#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1255
1256/* Anti-Pop WAIT Stage Timing Control Register */
1257#define ICDC_APWAIT_WAITSN_BIT 0
1258#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1259
1260/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1261#define ICDC_APPRE_PRESN_BIT 0
1262#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1263
1264/* Anti-Pop HPEN Stage Timing Control Register */
1265#define ICDC_APHPEN_HPENSN_BIT 0
1266#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1267
1268/* Anti-Pop Status Register */
1269#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1270#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1271#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1272#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1273  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1274#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1275  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1276  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1277  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1278  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1279#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1280#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1281
1282
1283/*************************************************************************
1284 * I2C
1285 *************************************************************************/
1286#define I2C_DR (I2C_BASE + 0x000)
1287#define I2C_CR (I2C_BASE + 0x004)
1288#define I2C_SR (I2C_BASE + 0x008)
1289#define I2C_GR (I2C_BASE + 0x00C)
1290
1291#define REG_I2C_DR REG8(I2C_DR)
1292#define REG_I2C_CR REG8(I2C_CR)
1293#define REG_I2C_SR REG8(I2C_SR)
1294#define REG_I2C_GR REG16(I2C_GR)
1295
1296/* I2C Control Register (I2C_CR) */
1297
1298#define I2C_CR_IEN (1 << 4)
1299#define I2C_CR_STA (1 << 3)
1300#define I2C_CR_STO (1 << 2)
1301#define I2C_CR_AC (1 << 1)
1302#define I2C_CR_I2CE (1 << 0)
1303
1304/* I2C Status Register (I2C_SR) */
1305
1306#define I2C_SR_STX (1 << 4)
1307#define I2C_SR_BUSY (1 << 3)
1308#define I2C_SR_TEND (1 << 2)
1309#define I2C_SR_DRF (1 << 1)
1310#define I2C_SR_ACKF (1 << 0)
1311
1312
1313/*************************************************************************
1314 * SSI
1315 *************************************************************************/
1316#define SSI_DR (SSI_BASE + 0x000)
1317#define SSI_CR0 (SSI_BASE + 0x004)
1318#define SSI_CR1 (SSI_BASE + 0x008)
1319#define SSI_SR (SSI_BASE + 0x00C)
1320#define SSI_ITR (SSI_BASE + 0x010)
1321#define SSI_ICR (SSI_BASE + 0x014)
1322#define SSI_GR (SSI_BASE + 0x018)
1323
1324#define REG_SSI_DR REG32(SSI_DR)
1325#define REG_SSI_CR0 REG16(SSI_CR0)
1326#define REG_SSI_CR1 REG32(SSI_CR1)
1327#define REG_SSI_SR REG32(SSI_SR)
1328#define REG_SSI_ITR REG16(SSI_ITR)
1329#define REG_SSI_ICR REG8(SSI_ICR)
1330#define REG_SSI_GR REG16(SSI_GR)
1331
1332/* SSI Data Register (SSI_DR) */
1333
1334#define SSI_DR_GPC_BIT 0
1335#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1336
1337/* SSI Control Register 0 (SSI_CR0) */
1338
1339#define SSI_CR0_SSIE (1 << 15)
1340#define SSI_CR0_TIE (1 << 14)
1341#define SSI_CR0_RIE (1 << 13)
1342#define SSI_CR0_TEIE (1 << 12)
1343#define SSI_CR0_REIE (1 << 11)
1344#define SSI_CR0_LOOP (1 << 10)
1345#define SSI_CR0_RFINE (1 << 9)
1346#define SSI_CR0_RFINC (1 << 8)
1347#define SSI_CR0_FSEL (1 << 6)
1348#define SSI_CR0_TFLUSH (1 << 2)
1349#define SSI_CR0_RFLUSH (1 << 1)
1350#define SSI_CR0_DISREV (1 << 0)
1351
1352/* SSI Control Register 1 (SSI_CR1) */
1353
1354#define SSI_CR1_FRMHL_BIT 30
1355#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1356  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1357  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1358  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1359  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1360#define SSI_CR1_TFVCK_BIT 28
1361#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1362  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1363  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1364  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1365  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1366#define SSI_CR1_TCKFI_BIT 26
1367#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1368  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1369  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1370  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1371  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1372#define SSI_CR1_LFST (1 << 25)
1373#define SSI_CR1_ITFRM (1 << 24)
1374#define SSI_CR1_UNFIN (1 << 23)
1375#define SSI_CR1_MULTS (1 << 22)
1376#define SSI_CR1_FMAT_BIT 20
1377#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1378  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1379  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1380  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1381  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1382#define SSI_CR1_TTRG_BIT 16
1383#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1384  #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1385  #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1386  #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1387  #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1388  #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1389  #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1390  #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1391  #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1392  #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1393  #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1394  #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1395  #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1396  #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1397  #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1398  #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1399  #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1400#define SSI_CR1_MCOM_BIT 12
1401#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1402  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1403  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1404  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1405  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1406  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1407  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1408  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1409  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1410  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1411  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1412  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1413  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1414  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1415  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1416  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1417  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1418#define SSI_CR1_RTRG_BIT 8
1419#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1420  #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1421  #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1422  #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1423  #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1424  #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1425  #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1426  #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1427  #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1428  #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1429  #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1430  #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1431  #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1432  #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1433  #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1434  #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1435  #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1436#define SSI_CR1_FLEN_BIT 4
1437#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1438  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1439  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1440  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1441  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1442  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1443  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1444  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1445  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1446  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1447  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1448  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1449  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1450  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1451  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1452  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1453  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1454#define SSI_CR1_PHA (1 << 1)
1455#define SSI_CR1_POL (1 << 0)
1456
1457/* SSI Status Register (SSI_SR) */
1458
1459#define SSI_SR_TFIFONUM_BIT 16
1460#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1461#define SSI_SR_RFIFONUM_BIT 8
1462#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1463#define SSI_SR_END (1 << 7)
1464#define SSI_SR_BUSY (1 << 6)
1465#define SSI_SR_TFF (1 << 5)
1466#define SSI_SR_RFE (1 << 4)
1467#define SSI_SR_TFHE (1 << 3)
1468#define SSI_SR_RFHF (1 << 2)
1469#define SSI_SR_UNDR (1 << 1)
1470#define SSI_SR_OVER (1 << 0)
1471
1472/* SSI Interval Time Control Register (SSI_ITR) */
1473
1474#define SSI_ITR_CNTCLK (1 << 15)
1475#define SSI_ITR_IVLTM_BIT 0
1476#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1477
1478
1479/*************************************************************************
1480 * MSC
1481 *************************************************************************/
1482#define MSC_STRPCL (MSC_BASE + 0x000)
1483#define MSC_STAT (MSC_BASE + 0x004)
1484#define MSC_CLKRT (MSC_BASE + 0x008)
1485#define MSC_CMDAT (MSC_BASE + 0x00C)
1486#define MSC_RESTO (MSC_BASE + 0x010)
1487#define MSC_RDTO (MSC_BASE + 0x014)
1488#define MSC_BLKLEN (MSC_BASE + 0x018)
1489#define MSC_NOB (MSC_BASE + 0x01C)
1490#define MSC_SNOB (MSC_BASE + 0x020)
1491#define MSC_IMASK (MSC_BASE + 0x024)
1492#define MSC_IREG (MSC_BASE + 0x028)
1493#define MSC_CMD (MSC_BASE + 0x02C)
1494#define MSC_ARG (MSC_BASE + 0x030)
1495#define MSC_RES (MSC_BASE + 0x034)
1496#define MSC_RXFIFO (MSC_BASE + 0x038)
1497#define MSC_TXFIFO (MSC_BASE + 0x03C)
1498
1499#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1500#define REG_MSC_STAT REG32(MSC_STAT)
1501#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1502#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1503#define REG_MSC_RESTO REG16(MSC_RESTO)
1504#define REG_MSC_RDTO REG16(MSC_RDTO)
1505#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1506#define REG_MSC_NOB REG16(MSC_NOB)
1507#define REG_MSC_SNOB REG16(MSC_SNOB)
1508#define REG_MSC_IMASK REG16(MSC_IMASK)
1509#define REG_MSC_IREG REG16(MSC_IREG)
1510#define REG_MSC_CMD REG8(MSC_CMD)
1511#define REG_MSC_ARG REG32(MSC_ARG)
1512#define REG_MSC_RES REG16(MSC_RES)
1513#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1514#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1515
1516/* MSC Clock and Control Register (MSC_STRPCL) */
1517
1518#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1519#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1520#define MSC_STRPCL_START_READWAIT (1 << 5)
1521#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1522#define MSC_STRPCL_RESET (1 << 3)
1523#define MSC_STRPCL_START_OP (1 << 2)
1524#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1525#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1526  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1527  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1528
1529/* MSC Status Register (MSC_STAT) */
1530
1531#define MSC_STAT_IS_RESETTING (1 << 15)
1532#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1533#define MSC_STAT_PRG_DONE (1 << 13)
1534#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1535#define MSC_STAT_END_CMD_RES (1 << 11)
1536#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1537#define MSC_STAT_IS_READWAIT (1 << 9)
1538#define MSC_STAT_CLK_EN (1 << 8)
1539#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1540#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1541#define MSC_STAT_CRC_RES_ERR (1 << 5)
1542#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1543#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1544#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1545  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1546  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1547  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1548#define MSC_STAT_TIME_OUT_RES (1 << 1)
1549#define MSC_STAT_TIME_OUT_READ (1 << 0)
1550
1551/* MSC Bus Clock Control Register (MSC_CLKRT) */
1552
1553#define MSC_CLKRT_CLK_RATE_BIT 0
1554#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1555  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1556  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1557  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1558  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1559  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1560  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1561  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1562  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1563
1564/* MSC Command Sequence Control Register (MSC_CMDAT) */
1565
1566#define MSC_CMDAT_IO_ABORT (1 << 11)
1567#define MSC_CMDAT_BUS_WIDTH_BIT 9
1568#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1569#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1570#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1571#define MSC_CMDAT_DMA_EN (1 << 8)
1572#define MSC_CMDAT_INIT (1 << 7)
1573#define MSC_CMDAT_BUSY (1 << 6)
1574#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1575#define MSC_CMDAT_WRITE (1 << 4)
1576#define MSC_CMDAT_READ (0 << 4)
1577#define MSC_CMDAT_DATA_EN (1 << 3)
1578#define MSC_CMDAT_RESPONSE_BIT 0
1579#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1580#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
1581#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
1582#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
1583#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
1584#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
1585#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
1586#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
1587
1588/* MSC Interrupts Mask Register (MSC_IMASK) */
1589#define MSC_IMASK_SDIO (1 << 7)
1590#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1591#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1592#define MSC_IMASK_END_CMD_RES (1 << 2)
1593#define MSC_IMASK_PRG_DONE (1 << 1)
1594#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1595
1596
1597/* MSC Interrupts Status Register (MSC_IREG) */
1598#define MSC_IREG_SDIO (1 << 7)
1599#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1600#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1601#define MSC_IREG_END_CMD_RES (1 << 2)
1602#define MSC_IREG_PRG_DONE (1 << 1)
1603#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1604
1605
1606/*
1607 * EMC (External Memory Controller)
1608 */
1609#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1610
1611#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1612#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1613#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1614#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1615#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1616#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1617#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1618#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1619#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1620#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1621
1622#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1623#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1624#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1625#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1626#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1627#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1628#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1629#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1630#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1631#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1632#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1633#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1634
1635#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1636#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1637#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1638#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1639#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1640#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1641
1642#define REG_EMC_BCR REG32(EMC_BCR)
1643
1644#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1645#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1646#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1647#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1648#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1649#define REG_EMC_SACR0 REG32(EMC_SACR0)
1650#define REG_EMC_SACR1 REG32(EMC_SACR1)
1651#define REG_EMC_SACR2 REG32(EMC_SACR2)
1652#define REG_EMC_SACR3 REG32(EMC_SACR3)
1653#define REG_EMC_SACR4 REG32(EMC_SACR4)
1654
1655#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1656#define REG_EMC_NFECR REG32(EMC_NFECR)
1657#define REG_EMC_NFECC REG32(EMC_NFECC)
1658#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1659#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1660#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1661#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1662#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1663#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1664#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1665#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1666#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1667
1668#define REG_EMC_DMCR REG32(EMC_DMCR)
1669#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1670#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1671#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1672#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1673
1674/* Static Memory Control Register */
1675#define EMC_SMCR_STRV_BIT 24
1676#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1677#define EMC_SMCR_TAW_BIT 20
1678#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1679#define EMC_SMCR_TBP_BIT 16
1680#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1681#define EMC_SMCR_TAH_BIT 12
1682#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1683#define EMC_SMCR_TAS_BIT 8
1684#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1685#define EMC_SMCR_BW_BIT 6
1686#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1687  #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1688  #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1689  #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1690#define EMC_SMCR_BCM (1 << 3)
1691#define EMC_SMCR_BL_BIT 1
1692#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1693  #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1694  #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1695  #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1696  #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1697#define EMC_SMCR_SMT (1 << 0)
1698
1699/* Static Memory Bank Addr Config Reg */
1700#define EMC_SACR_BASE_BIT 8
1701#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1702#define EMC_SACR_MASK_BIT 0
1703#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1704
1705/* NAND Flash Control/Status Register */
1706#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1707#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1708#define EMC_NFCSR_NFCE3 (1 << 5)
1709#define EMC_NFCSR_NFE3 (1 << 4)
1710#define EMC_NFCSR_NFCE2 (1 << 3)
1711#define EMC_NFCSR_NFE2 (1 << 2)
1712#define EMC_NFCSR_NFCE1 (1 << 1)
1713#define EMC_NFCSR_NFE1 (1 << 0)
1714
1715/* NAND Flash ECC Control Register */
1716#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1717#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1718#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1719#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1720#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1721#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1722#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1723
1724/* NAND Flash ECC Data Register */
1725#define EMC_NFECC_ECC2_BIT 16
1726#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1727#define EMC_NFECC_ECC1_BIT 8
1728#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1729#define EMC_NFECC_ECC0_BIT 0
1730#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1731
1732/* NAND Flash Interrupt Status Register */
1733#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1734#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1735#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1736#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1737#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1738#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1739#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1740
1741/* NAND Flash Interrupt Enable Register */
1742#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1743#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1744#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1745#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1746#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1747
1748/* NAND Flash RS Error Report Register */
1749#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1750#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1751#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1752#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1753
1754
1755/* DRAM Control Register */
1756#define EMC_DMCR_BW_BIT 31
1757#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1758#define EMC_DMCR_CA_BIT 26
1759#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1760  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1761  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1762  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1763  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1764  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1765#define EMC_DMCR_RMODE (1 << 25)
1766#define EMC_DMCR_RFSH (1 << 24)
1767#define EMC_DMCR_MRSET (1 << 23)
1768#define EMC_DMCR_RA_BIT 20
1769#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1770  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1771  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1772  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1773#define EMC_DMCR_BA_BIT 19
1774#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1775#define EMC_DMCR_PDM (1 << 18)
1776#define EMC_DMCR_EPIN (1 << 17)
1777#define EMC_DMCR_TRAS_BIT 13
1778#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1779#define EMC_DMCR_RCD_BIT 11
1780#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1781#define EMC_DMCR_TPC_BIT 8
1782#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1783#define EMC_DMCR_TRWL_BIT 5
1784#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1785#define EMC_DMCR_TRC_BIT 2
1786#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1787#define EMC_DMCR_TCL_BIT 0
1788#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1789
1790/* Refresh Time Control/Status Register */
1791#define EMC_RTCSR_CMF (1 << 7)
1792#define EMC_RTCSR_CKS_BIT 0
1793#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1794  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1795  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1796  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1797  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1798  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1799  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1800  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1801  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1802
1803/* SDRAM Bank Address Configuration Register */
1804#define EMC_DMAR_BASE_BIT 8
1805#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1806#define EMC_DMAR_MASK_BIT 0
1807#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1808
1809/* Mode Register of SDRAM bank 0 */
1810#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1811#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1812#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1813  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1814#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1815#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1816  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1817  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1818  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1819#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1820#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1821  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1822  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1823#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1824#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1825  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1826  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1827  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1828  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1829
1830#define EMC_SDMR_CAS2_16BIT \
1831  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1832#define EMC_SDMR_CAS2_32BIT \
1833  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1834#define EMC_SDMR_CAS3_16BIT \
1835  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1836#define EMC_SDMR_CAS3_32BIT \
1837  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1838
1839/*************************************************************************
1840 * CIM
1841 *************************************************************************/
1842#define CIM_CFG (CIM_BASE + 0x0000)
1843#define CIM_CTRL (CIM_BASE + 0x0004)
1844#define CIM_STATE (CIM_BASE + 0x0008)
1845#define CIM_IID (CIM_BASE + 0x000C)
1846#define CIM_RXFIFO (CIM_BASE + 0x0010)
1847#define CIM_DA (CIM_BASE + 0x0020)
1848#define CIM_FA (CIM_BASE + 0x0024)
1849#define CIM_FID (CIM_BASE + 0x0028)
1850#define CIM_CMD (CIM_BASE + 0x002C)
1851
1852#define REG_CIM_CFG REG32(CIM_CFG)
1853#define REG_CIM_CTRL REG32(CIM_CTRL)
1854#define REG_CIM_STATE REG32(CIM_STATE)
1855#define REG_CIM_IID REG32(CIM_IID)
1856#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1857#define REG_CIM_DA REG32(CIM_DA)
1858#define REG_CIM_FA REG32(CIM_FA)
1859#define REG_CIM_FID REG32(CIM_FID)
1860#define REG_CIM_CMD REG32(CIM_CMD)
1861
1862/* CIM Configuration Register (CIM_CFG) */
1863
1864#define CIM_CFG_INV_DAT (1 << 15)
1865#define CIM_CFG_VSP (1 << 14)
1866#define CIM_CFG_HSP (1 << 13)
1867#define CIM_CFG_PCP (1 << 12)
1868#define CIM_CFG_DUMMY_ZERO (1 << 9)
1869#define CIM_CFG_EXT_VSYNC (1 << 8)
1870#define CIM_CFG_PACK_BIT 4
1871#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1872  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1873  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1874  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1875  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1876  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1877  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1878  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1879  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1880#define CIM_CFG_DSM_BIT 0
1881#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1882  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1883  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1884  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1885  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1886
1887/* CIM Control Register (CIM_CTRL) */
1888
1889#define CIM_CTRL_MCLKDIV_BIT 24
1890#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1891#define CIM_CTRL_FRC_BIT 16
1892#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1893  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1894  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1895  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1896  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1897  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1898  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1899  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1900  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1901  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1902  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1903  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1904  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1905  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1906  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1907  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1908  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1909#define CIM_CTRL_VDDM (1 << 13)
1910#define CIM_CTRL_DMA_SOFM (1 << 12)
1911#define CIM_CTRL_DMA_EOFM (1 << 11)
1912#define CIM_CTRL_DMA_STOPM (1 << 10)
1913#define CIM_CTRL_RXF_TRIGM (1 << 9)
1914#define CIM_CTRL_RXF_OFM (1 << 8)
1915#define CIM_CTRL_RXF_TRIG_BIT 4
1916#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1917  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1918  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1919  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1920  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1921  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1922  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1923  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1924  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1925#define CIM_CTRL_DMA_EN (1 << 2)
1926#define CIM_CTRL_RXF_RST (1 << 1)
1927#define CIM_CTRL_ENA (1 << 0)
1928
1929/* CIM State Register (CIM_STATE) */
1930
1931#define CIM_STATE_DMA_SOF (1 << 6)
1932#define CIM_STATE_DMA_EOF (1 << 5)
1933#define CIM_STATE_DMA_STOP (1 << 4)
1934#define CIM_STATE_RXF_OF (1 << 3)
1935#define CIM_STATE_RXF_TRIG (1 << 2)
1936#define CIM_STATE_RXF_EMPTY (1 << 1)
1937#define CIM_STATE_VDD (1 << 0)
1938
1939/* CIM DMA Command Register (CIM_CMD) */
1940
1941#define CIM_CMD_SOFINT (1 << 31)
1942#define CIM_CMD_EOFINT (1 << 30)
1943#define CIM_CMD_STOP (1 << 28)
1944#define CIM_CMD_LEN_BIT 0
1945#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1946
1947
1948/*************************************************************************
1949 * SADC (Smart A/D Controller)
1950 *************************************************************************/
1951
1952#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1953#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1954#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1955#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1956#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1957#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1958#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1959#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1960#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1961
1962#define REG_SADC_ENA REG8(SADC_ENA)
1963#define REG_SADC_CFG REG32(SADC_CFG)
1964#define REG_SADC_CTRL REG8(SADC_CTRL)
1965#define REG_SADC_STATE REG8(SADC_STATE)
1966#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1967#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1968#define REG_SADC_TSDAT REG32(SADC_TSDAT)
1969#define REG_SADC_BATDAT REG16(SADC_BATDAT)
1970#define REG_SADC_SADDAT REG16(SADC_SADDAT)
1971
1972/* ADC Enable Register */
1973#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1974#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1975#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1976#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1977
1978/* ADC Configure Register */
1979#define SADC_CFG_CLKOUT_NUM_BIT 16
1980#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1981#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1982#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1983#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1984  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1985  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1986  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1987#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1988#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1989  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1990  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1991  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1992  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1993  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1994  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1995  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1996  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1997#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1998#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1999#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2000#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2001#define SADC_CFG_CMD_BIT 0 /* ADC Command */
2002#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2003  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2004  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2005  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2006  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2007  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2008  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2009  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2010  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2011  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2012  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2013  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2014  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2015  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2016
2017/* ADC Control Register */
2018#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2019#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2020#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2021#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2022#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2023
2024/* ADC Status Register */
2025#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2026#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2027#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2028#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2029#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2030#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2031#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2032#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2033
2034/* ADC Touch Screen Data Register */
2035#define SADC_TSDAT_DATA0_BIT 0
2036#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2037#define SADC_TSDAT_TYPE0 (1 << 15)
2038#define SADC_TSDAT_DATA1_BIT 16
2039#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2040#define SADC_TSDAT_TYPE1 (1 << 31)
2041
2042
2043/*************************************************************************
2044 * SLCD (Smart LCD Controller)
2045 *************************************************************************/
2046
2047#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2048#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2049#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2050#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2051#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2052
2053#define REG_SLCD_CFG REG32(SLCD_CFG)
2054#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2055#define REG_SLCD_STATE REG8(SLCD_STATE)
2056#define REG_SLCD_DATA REG32(SLCD_DATA)
2057#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2058
2059/* SLCD Configure Register */
2060#define SLCD_CFG_BURST_BIT 14
2061#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2062  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2063  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2064#define SLCD_CFG_DWIDTH_BIT 10
2065#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2066  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2067  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2068  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2069  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2070  #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2071  #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2072#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2073#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2074#define SLCD_CFG_CWIDTH_18BIT (2 << 8)
2075#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2076#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2077#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2078#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2079#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2080#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2081#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2082#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2083
2084/* SLCD Control Register */
2085#define SLCD_CTRL_DMA_EN (1 << 0)
2086
2087/* SLCD Status Register */
2088#define SLCD_STATE_BUSY (1 << 0)
2089
2090/* SLCD Data Register */
2091#define SLCD_DATA_RS_DATA (0 << 31)
2092#define SLCD_DATA_RS_COMMAND (1 << 31)
2093
2094/* SLCD FIFO Register */
2095#define SLCD_FIFO_RS_DATA (0 << 31)
2096#define SLCD_FIFO_RS_COMMAND (1 << 31)
2097
2098
2099/*************************************************************************
2100 * LCD (LCD Controller)
2101 *************************************************************************/
2102#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2103#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2104#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2105#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2106#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2107#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2108#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2109#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2110#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2111#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2112#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2113#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2114#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2115#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2116#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2117#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2118#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2119#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2120#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2121#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2122#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2123
2124#define REG_LCD_CFG REG32(LCD_CFG)
2125#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2126#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2127#define REG_LCD_VAT REG32(LCD_VAT)
2128#define REG_LCD_DAH REG32(LCD_DAH)
2129#define REG_LCD_DAV REG32(LCD_DAV)
2130#define REG_LCD_PS REG32(LCD_PS)
2131#define REG_LCD_CLS REG32(LCD_CLS)
2132#define REG_LCD_SPL REG32(LCD_SPL)
2133#define REG_LCD_REV REG32(LCD_REV)
2134#define REG_LCD_CTRL REG32(LCD_CTRL)
2135#define REG_LCD_STATE REG32(LCD_STATE)
2136#define REG_LCD_IID REG32(LCD_IID)
2137#define REG_LCD_DA0 REG32(LCD_DA0)
2138#define REG_LCD_SA0 REG32(LCD_SA0)
2139#define REG_LCD_FID0 REG32(LCD_FID0)
2140#define REG_LCD_CMD0 REG32(LCD_CMD0)
2141#define REG_LCD_DA1 REG32(LCD_DA1)
2142#define REG_LCD_SA1 REG32(LCD_SA1)
2143#define REG_LCD_FID1 REG32(LCD_FID1)
2144#define REG_LCD_CMD1 REG32(LCD_CMD1)
2145
2146/* LCD Configure Register */
2147#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2148#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2149  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2150  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2151#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2152#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2153#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2154#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2155#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2156#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2157#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2158#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2159#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2160#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2161#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2162#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2163#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2164#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2165#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2166#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2167#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2168#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2169#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2170  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2171  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2172  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2173#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2174#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2175  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2176  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2177  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2178  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2179  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2180  #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2181  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2182  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2183  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2184  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2185  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2186  #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2187  /* JZ47XX defines */
2188  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2189  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2190  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2191
2192
2193
2194/* Vertical Synchronize Register */
2195#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2196#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2197#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2198#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2199
2200/* Horizontal Synchronize Register */
2201#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2202#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2203#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2204#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2205
2206/* Virtual Area Setting Register */
2207#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2208#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2209#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2210#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2211
2212/* Display Area Horizontal Start/End Point Register */
2213#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2214#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2215#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2216#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2217
2218/* Display Area Vertical Start/End Point Register */
2219#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2220#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2221#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2222#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2223
2224/* PS Signal Setting */
2225#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2226#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2227#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2228#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2229
2230/* CLS Signal Setting */
2231#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2232#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2233#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2234#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2235
2236/* SPL Signal Setting */
2237#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2238#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2239#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2240#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2241
2242/* REV Signal Setting */
2243#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2244#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2245
2246/* LCD Control Register */
2247#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2248#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2249  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2250  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2251  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2252#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2253#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2254#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2255#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2256#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2257  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2258  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2259  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2260#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2261#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2262#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2263#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2264#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2265#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2266#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2267#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2268#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2269#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2270#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2271#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2272#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2273#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2274#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2275  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2276  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2277  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2278  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2279  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2280  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2281
2282/* LCD Status Register */
2283#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2284#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2285#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2286#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2287#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2288#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2289#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2290
2291/* DMA Command Register */
2292#define LCD_CMD_SOFINT (1 << 31)
2293#define LCD_CMD_EOFINT (1 << 30)
2294#define LCD_CMD_PAL (1 << 28)
2295#define LCD_CMD_LEN_BIT 0
2296#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2297
2298
2299/*************************************************************************
2300 * USB Device
2301 *************************************************************************/
2302#define USB_BASE UDC_BASE
2303
2304#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2305#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2306#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2307#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2308#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2309#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2310#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2311#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2312#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2313#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2314#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2315
2316#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2317#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2318#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2319#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2320#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2321#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2322#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2323#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2324
2325#define USB_FIFO_EP0 (USB_BASE + 0x20)
2326#define USB_FIFO_EP1 (USB_BASE + 0x24)
2327#define USB_FIFO_EP2 (USB_BASE + 0x28)
2328
2329#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2330#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2331
2332#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2333#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2334#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2335#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2336#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2337#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2338#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2339
2340
2341/* Power register bit masks */
2342#define USB_POWER_SUSPENDM 0x01
2343#define USB_POWER_RESUME 0x04
2344#define USB_POWER_HSMODE 0x10
2345#define USB_POWER_HSENAB 0x20
2346#define USB_POWER_SOFTCONN 0x40
2347
2348/* Interrupt register bit masks */
2349#define USB_INTR_SUSPEND 0x01
2350#define USB_INTR_RESUME 0x02
2351#define USB_INTR_RESET 0x04
2352
2353#define USB_INTR_EP0 0x0001
2354#define USB_INTR_INEP1 0x0002
2355#define USB_INTR_INEP2 0x0004
2356#define USB_INTR_OUTEP1 0x0002
2357
2358/* CSR0 bit masks */
2359#define USB_CSR0_OUTPKTRDY 0x01
2360#define USB_CSR0_INPKTRDY 0x02
2361#define USB_CSR0_SENTSTALL 0x04
2362#define USB_CSR0_DATAEND 0x08
2363#define USB_CSR0_SETUPEND 0x10
2364#define USB_CSR0_SENDSTALL 0x20
2365#define USB_CSR0_SVDOUTPKTRDY 0x40
2366#define USB_CSR0_SVDSETUPEND 0x80
2367
2368/* Endpoint CSR register bits */
2369#define USB_INCSRH_AUTOSET 0x80
2370#define USB_INCSRH_ISO 0x40
2371#define USB_INCSRH_MODE 0x20
2372#define USB_INCSRH_DMAREQENAB 0x10
2373#define USB_INCSRH_DMAREQMODE 0x04
2374#define USB_INCSR_CDT 0x40
2375#define USB_INCSR_SENTSTALL 0x20
2376#define USB_INCSR_SENDSTALL 0x10
2377#define USB_INCSR_FF 0x08
2378#define USB_INCSR_UNDERRUN 0x04
2379#define USB_INCSR_FFNOTEMPT 0x02
2380#define USB_INCSR_INPKTRDY 0x01
2381#define USB_OUTCSRH_AUTOCLR 0x80
2382#define USB_OUTCSRH_ISO 0x40
2383#define USB_OUTCSRH_DMAREQENAB 0x20
2384#define USB_OUTCSRH_DNYT 0x10
2385#define USB_OUTCSRH_DMAREQMODE 0x08
2386#define USB_OUTCSR_CDT 0x80
2387#define USB_OUTCSR_SENTSTALL 0x40
2388#define USB_OUTCSR_SENDSTALL 0x20
2389#define USB_OUTCSR_FF 0x10
2390#define USB_OUTCSR_DATAERR 0x08
2391#define USB_OUTCSR_OVERRUN 0x04
2392#define USB_OUTCSR_FFFULL 0x02
2393#define USB_OUTCSR_OUTPKTRDY 0x01
2394
2395/* Testmode register bits */
2396#define USB_TEST_SE0NAK 0x01
2397#define USB_TEST_J 0x02
2398#define USB_TEST_K 0x04
2399#define USB_TEST_PACKET 0x08
2400
2401/* DMA control bits */
2402#define USB_CNTL_ENA 0x01
2403#define USB_CNTL_DIR_IN 0x02
2404#define USB_CNTL_MODE_1 0x04
2405#define USB_CNTL_INTR_EN 0x08
2406#define USB_CNTL_EP(n) ((n) << 4)
2407#define USB_CNTL_BURST_0 (0 << 9)
2408#define USB_CNTL_BURST_4 (1 << 9)
2409#define USB_CNTL_BURST_8 (2 << 9)
2410#define USB_CNTL_BURST_16 (3 << 9)
2411
2412
2413
2414/* Module Operation Definitions */
2415#ifndef __ASSEMBLY__
2416
2417
2418/* GPIO Pins Description */
2419/* PORT 0: */
2420/* PIN/BIT N FUNC0 FUNC1 */
2421/* 0 D0 - */
2422/* 1 D1 - */
2423/* 2 D2 - */
2424/* 3 D3 - */
2425/* 4 D4 - */
2426/* 5 D5 - */
2427/* 6 D6 - */
2428/* 7 D7 - */
2429/* 8 D8 - */
2430/* 9 D9 - */
2431/* 10 D10 - */
2432/* 11 D11 - */
2433/* 12 D12 - */
2434/* 13 D13 - */
2435/* 14 D14 - */
2436/* 15 D15 - */
2437/* 16 D16 - */
2438/* 17 D17 - */
2439/* 18 D18 - */
2440/* 19 D19 - */
2441/* 20 D20 - */
2442/* 21 D21 - */
2443/* 22 D22 - */
2444/* 23 D23 - */
2445/* 24 D24 - */
2446/* 25 D25 - */
2447/* 26 D26 - */
2448/* 27 D27 - */
2449/* 28 D28 - */
2450/* 29 D29 - */
2451/* 30 D30 - */
2452/* 31 D31 - */
2453/*------------------------------------------------------ */
2454/* PORT 1: */
2455/* */
2456/* PIN/BIT N FUNC0 FUNC1 */
2457/* 0 A0 - */
2458/* 1 A1 - */
2459/* 2 A2 - */
2460/* 3 A3 - */
2461/* 4 A4 - */
2462/* 5 A5 - */
2463/* 6 A6 - */
2464/* 7 A7 - */
2465/* 8 A8 - */
2466/* 9 A9 - */
2467/* 10 A10 - */
2468/* 11 A11 - */
2469/* 12 A12 - */
2470/* 13 A13 - */
2471/* 14 A14 - */
2472/* 15 A15/CL - */
2473/* 16 A16/AL - */
2474/* 17 LCD_CLS A21 */
2475/* 18 LCD_SPL A22 */
2476/* 19 DCS# - */
2477/* 20 RAS# - */
2478/* 21 CAS# - */
2479/* 22 RDWE#/BUFD# - */
2480/* 23 CKE - */
2481/* 24 CKO - */
2482/* 25 CS1# - */
2483/* 26 CS2# - */
2484/* 27 CS3# - */
2485/* 28 CS4# - */
2486/* 29 RD# - */
2487/* 30 WR# - */
2488/* 31 WE0# - */
2489/* Note: PIN15&16 are CL&AL when connecting to NAND flash. */
2490/*------------------------------------------------------ */
2491/* PORT 2: */
2492/* */
2493/* PIN/BIT N FUNC0 FUNC1 */
2494/* 0 LCD_D0 - */
2495/* 1 LCD_D1 - */
2496/* 2 LCD_D2 - */
2497/* 3 LCD_D3 - */
2498/* 4 LCD_D4 - */
2499/* 5 LCD_D5 - */
2500/* 6 LCD_D6 - */
2501/* 7 LCD_D7 - */
2502/* 8 LCD_D8 - */
2503/* 9 LCD_D9 - */
2504/* 10 LCD_D10 - */
2505/* 11 LCD_D11 - */
2506/* 12 LCD_D12 - */
2507/* 13 LCD_D13 - */
2508/* 14 LCD_D14 - */
2509/* 15 LCD_D15 - */
2510/* 16 LCD_D16 - */
2511/* 17 LCD_D17 - */
2512/* 18 LCD_PCLK - */
2513/* 19 LCD_HSYNC - */
2514/* 20 LCD_VSYNC - */
2515/* 21 LCD_DE - */
2516/* 22 LCD_PS A19 */
2517/* 23 LCD_REV A20 */
2518/* 24 WE1# - */
2519/* 25 WE2# - */
2520/* 26 WE3# - */
2521/* 27 WAIT# - */
2522/* 28 FRE# - */
2523/* 29 FWE# - */
2524/* 30(NOTE:FRB#) - - */
2525/* 31 - - */
2526/* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */
2527/*------------------------------------------------------ */
2528/* PORT 3: */
2529/* */
2530/* PIN/BIT N FUNC0 FUNC1 */
2531/* 0 CIM_D0 - */
2532/* 1 CIM_D1 - */
2533/* 2 CIM_D2 - */
2534/* 3 CIM_D3 - */
2535/* 4 CIM_D4 - */
2536/* 5 CIM_D5 - */
2537/* 6 CIM_D6 - */
2538/* 7 CIM_D7 - */
2539/* 8 MSC_CMD - */
2540/* 9 MSC_CLK - */
2541/* 10 MSC_D0 - */
2542/* 11 MSC_D1 - */
2543/* 12 MSC_D2 - */
2544/* 13 MSC_D3 - */
2545/* 14 CIM_MCLK - */
2546/* 15 CIM_PCLK - */
2547/* 16 CIM_VSYNC - */
2548/* 17 CIM_HSYNC - */
2549/* 18 SSI_CLK SCLK_RSTN */
2550/* 19 SSI_CE0# BIT_CLK(AIC) */
2551/* 20 SSI_DT SDATA_OUT(AIC) */
2552/* 21 SSI_DR SDATA_IN(AIC) */
2553/* 22 SSI_CE1#&GPC SYNC(AIC) */
2554/* 23 PWM0 I2C_SDA */
2555/* 24 PWM1 I2C_SCK */
2556/* 25 PWM2 UART0_TxD */
2557/* 26 PWM3 UART0_RxD */
2558/* 27 PWM4 A17 */
2559/* 28 PWM5 A18 */
2560/* 29 - - */
2561/* 30 PWM6 UART0_CTS/UART1_RxD */
2562/* 31 PWM7 UART0_RTS/UART1_TxD */
2563/*
2564 * p is the port number (0,1,2,3)
2565 * o is the pin offset (0-31) inside the port
2566 * n is the absolute number of a pin (0-127), regardless of the port
2567 */
2568
2569/* Function Pins Mode */
2570
2571#define __gpio_as_func0(n) \
2572do { \
2573    unsigned int p, o; \
2574    p = (n) / 32; \
2575    o = (n) % 32; \
2576    REG_GPIO_PXFUNS(p) = (1 << o); \
2577    REG_GPIO_PXSELC(p) = (1 << o); \
2578} while (0)
2579
2580#define __gpio_as_func1(n) \
2581do { \
2582    unsigned int p, o; \
2583    p = (n) / 32; \
2584    o = (n) % 32; \
2585    REG_GPIO_PXFUNS(p) = (1 << o); \
2586    REG_GPIO_PXSELS(p) = (1 << o); \
2587} while (0)
2588
2589/*
2590 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2591 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2592 */
2593#define __gpio_as_sdram_32bit() \
2594do { \
2595    REG_GPIO_PXFUNS(0) = 0xffffffff; \
2596    REG_GPIO_PXSELC(0) = 0xffffffff; \
2597    REG_GPIO_PXPES(0) = 0xffffffff; \
2598    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2599    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2600    REG_GPIO_PXPES(1) = 0x81f9ffff; \
2601    REG_GPIO_PXFUNS(2) = 0x07000000; \
2602    REG_GPIO_PXSELC(2) = 0x07000000; \
2603    REG_GPIO_PXPES(2) = 0x07000000; \
2604} while (0)
2605
2606/*
2607 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2608 * RDWE#, CKO#, WE0#, WE1#
2609 */
2610#define __gpio_as_sdram_16bit_4720() \
2611do { \
2612    REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
2613    REG_GPIO_PXSELC(0) = 0x5442bfaa; \
2614    REG_GPIO_PXPES(0) = 0x5442bfaa; \
2615    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2616    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2617    REG_GPIO_PXPES(1) = 0x81f9ffff; \
2618    REG_GPIO_PXFUNS(2) = 0x01000000; \
2619    REG_GPIO_PXSELC(2) = 0x01000000; \
2620    REG_GPIO_PXPES(2) = 0x01000000; \
2621} while (0)
2622
2623/*
2624 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2625 * RDWE#, CKO#, WE0#, WE1#
2626 */
2627#define __gpio_as_sdram_16bit_4725() \
2628do { \
2629    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2630    REG_GPIO_PXSELC(0) = 0x0000ffff; \
2631    REG_GPIO_PXPES(0) = 0x0000ffff; \
2632    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2633    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2634    REG_GPIO_PXPES(1) = 0x81f9ffff; \
2635    REG_GPIO_PXFUNS(2) = 0x01000000; \
2636    REG_GPIO_PXSELC(2) = 0x01000000; \
2637    REG_GPIO_PXPES(2) = 0x01000000; \
2638} while (0)
2639
2640
2641/*
2642 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2643 */
2644#define __gpio_as_nand() \
2645do { \
2646    REG_GPIO_PXFUNS(1) = 0x02018000; \
2647    REG_GPIO_PXSELC(1) = 0x02018000; \
2648    REG_GPIO_PXPES(1) = 0x02018000; \
2649    REG_GPIO_PXFUNS(2) = 0x30000000; \
2650    REG_GPIO_PXSELC(2) = 0x30000000; \
2651    REG_GPIO_PXPES(2) = 0x30000000; \
2652    REG_GPIO_PXFUNC(2) = 0x40000000; \
2653    REG_GPIO_PXSELC(2) = 0x40000000; \
2654    REG_GPIO_PXDIRC(2) = 0x40000000; \
2655    REG_GPIO_PXPES(2) = 0x40000000; \
2656    REG_GPIO_PXFUNS(1) = 0x00400000; \
2657    REG_GPIO_PXSELC(1) = 0x00400000; \
2658} while (0)
2659
2660/*
2661 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2662 */
2663#define __gpio_as_nor_8bit() \
2664do { \
2665    REG_GPIO_PXFUNS(0) = 0x000000ff; \
2666    REG_GPIO_PXSELC(0) = 0x000000ff; \
2667    REG_GPIO_PXPES(0) = 0x000000ff; \
2668    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2669    REG_GPIO_PXSELC(1) = 0x7041ffff; \
2670    REG_GPIO_PXPES(1) = 0x7041ffff; \
2671    REG_GPIO_PXFUNS(1) = 0x00060000; \
2672    REG_GPIO_PXSELS(1) = 0x00060000; \
2673    REG_GPIO_PXPES(1) = 0x00060000; \
2674    REG_GPIO_PXFUNS(2) = 0x08000000; \
2675    REG_GPIO_PXSELC(2) = 0x08000000; \
2676    REG_GPIO_PXPES(2) = 0x08000000; \
2677    REG_GPIO_PXFUNS(2) = 0x00c00000; \
2678    REG_GPIO_PXSELS(2) = 0x00c00000; \
2679    REG_GPIO_PXPES(2) = 0x00c00000; \
2680    REG_GPIO_PXFUNS(3) = 0x18000000; \
2681    REG_GPIO_PXSELS(3) = 0x18000000; \
2682    REG_GPIO_PXPES(3) = 0x18000000; \
2683} while (0)
2684
2685/*
2686 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2687 */
2688#define __gpio_as_nor_16bit() \
2689do { \
2690    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2691    REG_GPIO_PXSELC(0) = 0x0000ffff; \
2692    REG_GPIO_PXPES(0) = 0x0000ffff; \
2693    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2694    REG_GPIO_PXSELC(1) = 0x7041ffff; \
2695    REG_GPIO_PXPES(1) = 0x7041ffff; \
2696    REG_GPIO_PXFUNS(1) = 0x00060000; \
2697    REG_GPIO_PXSELS(1) = 0x00060000; \
2698    REG_GPIO_PXPES(1) = 0x00060000; \
2699    REG_GPIO_PXFUNS(2) = 0x08000000; \
2700    REG_GPIO_PXSELC(2) = 0x08000000; \
2701    REG_GPIO_PXPES(2) = 0x08000000; \
2702    REG_GPIO_PXFUNS(2) = 0x00c00000; \
2703    REG_GPIO_PXSELS(2) = 0x00c00000; \
2704    REG_GPIO_PXPES(2) = 0x00c00000; \
2705    REG_GPIO_PXFUNS(3) = 0x18000000; \
2706    REG_GPIO_PXSELS(3) = 0x18000000; \
2707    REG_GPIO_PXPES(3) = 0x18000000; \
2708} while (0)
2709
2710/*
2711 * UART0_TxD, UART_RxD0
2712 */
2713#define __gpio_as_uart0() \
2714do { \
2715    REG_GPIO_PXFUNS(3) = 0x06000000; \
2716    REG_GPIO_PXSELS(3) = 0x06000000; \
2717    REG_GPIO_PXPES(3) = 0x06000000; \
2718} while (0)
2719
2720#define __gpio_jtag_to_uart0() \
2721do { \
2722    REG_GPIO_PXSELS(2) = 0x80000000; \
2723} while (0)
2724
2725/*
2726 * UART0_CTS, UART0_RTS
2727 */
2728#define __gpio_as_ctsrts() \
2729do { \
2730    REG_GPIO_PXFUNS(3) = 0xc0000000; \
2731    REG_GPIO_PXSELS(3) = 0xc0000000; \
2732    REG_GPIO_PXTRGC(3) = 0xc0000000; \
2733    REG_GPIO_PXPES(3) = 0xc0000000; \
2734} while (0)
2735
2736/*
2737 * UART1_TxD, UART1_RxD1
2738 */
2739#define __gpio_as_uart1() \
2740do { \
2741    REG_GPIO_PXFUNS(3) = 0xc0000000; \
2742    REG_GPIO_PXSELC(3) = 0xc0000000; \
2743    REG_GPIO_PXTRGS(3) = 0xc0000000; \
2744    REG_GPIO_PXPES(3) = 0xc0000000; \
2745} while (0)
2746
2747/*
2748 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2749 */
2750#define __gpio_as_lcd_16bit() \
2751do { \
2752    REG_GPIO_PXFUNS(2) = 0x003cffff; \
2753    REG_GPIO_PXSELC(2) = 0x003cffff; \
2754    REG_GPIO_PXPES(2) = 0x003cffff; \
2755} while (0)
2756
2757/*
2758 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2759 */
2760#define __gpio_as_lcd_18bit() \
2761do { \
2762    REG_GPIO_PXFUNS(2) = 0x003fffff; \
2763    REG_GPIO_PXSELC(2) = 0x003fffff; \
2764    REG_GPIO_PXPES(2) = 0x003fffff; \
2765} while (0)
2766
2767
2768/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2769#define __gpio_as_slcd_8bit() \
2770do { \
2771    REG_GPIO_PXFUNS(2) = 0x001800ff; \
2772    REG_GPIO_PXSELC(2) = 0x001800ff; \
2773} while (0)
2774
2775/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2776#define __gpio_as_slcd_9bit() \
2777do { \
2778    REG_GPIO_PXFUNS(2) = 0x001801ff; \
2779    REG_GPIO_PXSELC(2) = 0x001801ff; \
2780} while (0)
2781
2782/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
2783#define __gpio_as_slcd_16bit() \
2784do { \
2785    REG_GPIO_PXFUNS(2) = 0x0018ffff; \
2786    REG_GPIO_PXSELC(2) = 0x0018ffff; \
2787} while (0)
2788
2789/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
2790#define __gpio_as_slcd_18bit() \
2791do { \
2792    REG_GPIO_PXFUNS(2) = 0x001bffff; \
2793    REG_GPIO_PXSELC(2) = 0x001bffff; \
2794} while (0)
2795/*
2796 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2797 */
2798#define __gpio_as_cim() \
2799do { \
2800    REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
2801    REG_GPIO_PXSELC(3) = 0x0003c0ff; \
2802    REG_GPIO_PXPES(3) = 0x0003c0ff; \
2803} while (0)
2804
2805/*
2806 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2807 */
2808#define __gpio_as_aic() \
2809do { \
2810    REG_GPIO_PXFUNS(3) = 0x007c0000; \
2811    REG_GPIO_PXSELS(3) = 0x007c0000; \
2812    REG_GPIO_PXPES(3) = 0x007c0000; \
2813} while (0)
2814
2815/*
2816 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2817 */
2818#define __gpio_as_msc() \
2819do { \
2820    REG_GPIO_PXFUNS(3) = 0x00003f00; \
2821    REG_GPIO_PXSELC(3) = 0x00003f00; \
2822    REG_GPIO_PXPES(3) = 0x00003f00; \
2823} while (0)
2824
2825/*
2826 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2827 */
2828#define __gpio_as_ssi() \
2829do { \
2830    REG_GPIO_PXFUNS(3) = 0x003c0000; \
2831    REG_GPIO_PXSELC(3) = 0x003c0000; \
2832    REG_GPIO_PXPES(3) = 0x003c0000; \
2833} while (0)
2834
2835/*
2836 * I2C_SCK, I2C_SDA
2837 */
2838#define __gpio_as_i2c() \
2839do { \
2840    REG_GPIO_PXFUNS(3) = 0x01800000; \
2841    REG_GPIO_PXSELS(3) = 0x01800000; \
2842    REG_GPIO_PXPES(3) = 0x01800000; \
2843} while (0)
2844
2845/*
2846 * PWM0
2847 */
2848#define __gpio_as_pwm0() \
2849do { \
2850    REG_GPIO_PXFUNS(3) = 0x00800000; \
2851    REG_GPIO_PXSELC(3) = 0x00800000; \
2852    REG_GPIO_PXPES(3) = 0x00800000; \
2853} while (0)
2854
2855/*
2856 * PWM1
2857 */
2858#define __gpio_as_pwm1() \
2859do { \
2860    REG_GPIO_PXFUNS(3) = 0x01000000; \
2861    REG_GPIO_PXSELC(3) = 0x01000000; \
2862    REG_GPIO_PXPES(3) = 0x01000000; \
2863} while (0)
2864
2865/*
2866 * PWM2
2867 */
2868#define __gpio_as_pwm2() \
2869do { \
2870    REG_GPIO_PXFUNS(3) = 0x02000000; \
2871    REG_GPIO_PXSELC(3) = 0x02000000; \
2872    REG_GPIO_PXPES(3) = 0x02000000; \
2873} while (0)
2874
2875/*
2876 * PWM3
2877 */
2878#define __gpio_as_pwm3() \
2879do { \
2880    REG_GPIO_PXFUNS(3) = 0x04000000; \
2881    REG_GPIO_PXSELC(3) = 0x04000000; \
2882    REG_GPIO_PXPES(3) = 0x04000000; \
2883} while (0)
2884
2885/*
2886 * PWM4
2887 */
2888#define __gpio_as_pwm4() \
2889do { \
2890    REG_GPIO_PXFUNS(3) = 0x08000000; \
2891    REG_GPIO_PXSELC(3) = 0x08000000; \
2892    REG_GPIO_PXPES(3) = 0x08000000; \
2893} while (0)
2894
2895/*
2896 * PWM5
2897 */
2898#define __gpio_as_pwm5() \
2899do { \
2900    REG_GPIO_PXFUNS(3) = 0x10000000; \
2901    REG_GPIO_PXSELC(3) = 0x10000000; \
2902    REG_GPIO_PXPES(3) = 0x10000000; \
2903} while (0)
2904
2905/*
2906 * PWM6
2907 */
2908#define __gpio_as_pwm6() \
2909do { \
2910    REG_GPIO_PXFUNS(3) = 0x40000000; \
2911    REG_GPIO_PXSELC(3) = 0x40000000; \
2912    REG_GPIO_PXPES(3) = 0x40000000; \
2913} while (0)
2914
2915/*
2916 * PWM7
2917 */
2918#define __gpio_as_pwm7() \
2919do { \
2920    REG_GPIO_PXFUNS(3) = 0x80000000; \
2921    REG_GPIO_PXSELC(3) = 0x80000000; \
2922    REG_GPIO_PXPES(3) = 0x80000000; \
2923} while (0)
2924
2925/*
2926 * n = 0 ~ 7
2927 */
2928#define __gpio_as_pwm(n) __gpio_as_pwm##n()
2929
2930/* GPIO or Interrupt Mode */
2931
2932#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
2933
2934#define __gpio_port_as_output(p, o) \
2935do { \
2936    REG_GPIO_PXFUNC(p) = (1 << (o)); \
2937    REG_GPIO_PXSELC(p) = (1 << (o)); \
2938    REG_GPIO_PXDIRS(p) = (1 << (o)); \
2939} while (0)
2940
2941#define __gpio_port_as_input(p, o) \
2942do { \
2943    REG_GPIO_PXFUNC(p) = (1 << (o)); \
2944    REG_GPIO_PXSELC(p) = (1 << (o)); \
2945    REG_GPIO_PXDIRC(p) = (1 << (o)); \
2946} while (0)
2947
2948#define __gpio_as_output(n) \
2949do { \
2950    unsigned int p, o; \
2951    p = (n) / 32; \
2952    o = (n) % 32; \
2953    __gpio_port_as_output(p, o); \
2954} while (0)
2955
2956#define __gpio_as_input(n) \
2957do { \
2958    unsigned int p, o; \
2959    p = (n) / 32; \
2960    o = (n) % 32; \
2961    __gpio_port_as_input(p, o); \
2962} while (0)
2963
2964#define __gpio_set_pin(n) \
2965do { \
2966    unsigned int p, o; \
2967    p = (n) / 32; \
2968    o = (n) % 32; \
2969    REG_GPIO_PXDATS(p) = (1 << o); \
2970} while (0)
2971
2972#define __gpio_clear_pin(n) \
2973do { \
2974    unsigned int p, o; \
2975    p = (n) / 32; \
2976    o = (n) % 32; \
2977    REG_GPIO_PXDATC(p) = (1 << o); \
2978} while (0)
2979
2980#define __gpio_get_pin(n) \
2981({ \
2982    unsigned int p, o, v; \
2983    p = (n) / 32; \
2984    o = (n) % 32; \
2985    if (__gpio_get_port(p) & (1 << o)) \
2986        v = 1; \
2987    else \
2988        v = 0; \
2989    v; \
2990})
2991
2992#define __gpio_as_irq_high_level(n) \
2993do { \
2994    unsigned int p, o; \
2995    p = (n) / 32; \
2996    o = (n) % 32; \
2997    REG_GPIO_PXIMS(p) = (1 << o); \
2998    REG_GPIO_PXTRGC(p) = (1 << o); \
2999    REG_GPIO_PXFUNC(p) = (1 << o); \
3000    REG_GPIO_PXSELS(p) = (1 << o); \
3001    REG_GPIO_PXDIRS(p) = (1 << o); \
3002    REG_GPIO_PXFLGC(p) = (1 << o); \
3003    REG_GPIO_PXIMC(p) = (1 << o); \
3004} while (0)
3005
3006#define __gpio_as_irq_low_level(n) \
3007do { \
3008    unsigned int p, o; \
3009    p = (n) / 32; \
3010    o = (n) % 32; \
3011    REG_GPIO_PXIMS(p) = (1 << o); \
3012    REG_GPIO_PXTRGC(p) = (1 << o); \
3013    REG_GPIO_PXFUNC(p) = (1 << o); \
3014    REG_GPIO_PXSELS(p) = (1 << o); \
3015    REG_GPIO_PXDIRC(p) = (1 << o); \
3016    REG_GPIO_PXFLGC(p) = (1 << o); \
3017    REG_GPIO_PXIMC(p) = (1 << o); \
3018} while (0)
3019
3020#define __gpio_as_irq_rise_edge(n) \
3021do { \
3022    unsigned int p, o; \
3023    p = (n) / 32; \
3024    o = (n) % 32; \
3025    REG_GPIO_PXIMS(p) = (1 << o); \
3026    REG_GPIO_PXTRGS(p) = (1 << o); \
3027    REG_GPIO_PXFUNC(p) = (1 << o); \
3028    REG_GPIO_PXSELS(p) = (1 << o); \
3029    REG_GPIO_PXDIRS(p) = (1 << o); \
3030    REG_GPIO_PXFLGC(p) = (1 << o); \
3031    REG_GPIO_PXIMC(p) = (1 << o); \
3032} while (0)
3033
3034#define __gpio_as_irq_fall_edge(n) \
3035do { \
3036    unsigned int p, o; \
3037    p = (n) / 32; \
3038    o = (n) % 32; \
3039    REG_GPIO_PXIMS(p) = (1 << o); \
3040    REG_GPIO_PXTRGS(p) = (1 << o); \
3041    REG_GPIO_PXFUNC(p) = (1 << o); \
3042    REG_GPIO_PXSELS(p) = (1 << o); \
3043    REG_GPIO_PXDIRC(p) = (1 << o); \
3044    REG_GPIO_PXFLGC(p) = (1 << o); \
3045    REG_GPIO_PXIMC(p) = (1 << o); \
3046} while (0)
3047
3048#define __gpio_mask_irq(n) \
3049do { \
3050    unsigned int p, o; \
3051    p = (n) / 32; \
3052    o = (n) % 32; \
3053    REG_GPIO_PXIMS(p) = (1 << o); \
3054} while (0)
3055
3056#define __gpio_unmask_irq(n) \
3057do { \
3058    unsigned int p, o; \
3059    p = (n) / 32; \
3060    o = (n) % 32; \
3061    REG_GPIO_PXIMC(p) = (1 << o); \
3062} while (0)
3063
3064#define __gpio_ack_irq(n) \
3065do { \
3066    unsigned int p, o; \
3067    p = (n) / 32; \
3068    o = (n) % 32; \
3069    REG_GPIO_PXFLGC(p) = (1 << o); \
3070} while (0)
3071
3072#define __gpio_get_irq() \
3073({ \
3074    unsigned int p, i, tmp, v = 0; \
3075    for (p = 3; p >= 0; p--) { \
3076        tmp = REG_GPIO_PXFLG(p); \
3077        for (i = 0; i < 32; i++) \
3078            if (tmp & (1 << i)) \
3079                v = (32*p + i); \
3080    } \
3081    v; \
3082})
3083
3084#define __gpio_group_irq(n) \
3085({ \
3086    register int tmp, i; \
3087    tmp = REG_GPIO_PXFLG((n)); \
3088    for (i=31;i>=0;i--) \
3089        if (tmp & (1 << i)) \
3090            break; \
3091    i; \
3092})
3093
3094#define __gpio_enable_pull(n) \
3095do { \
3096    unsigned int p, o; \
3097    p = (n) / 32; \
3098    o = (n) % 32; \
3099    REG_GPIO_PXPEC(p) = (1 << o); \
3100} while (0)
3101
3102#define __gpio_disable_pull(n) \
3103do { \
3104    unsigned int p, o; \
3105    p = (n) / 32; \
3106    o = (n) % 32; \
3107    REG_GPIO_PXPES(p) = (1 << o); \
3108} while (0)
3109
3110
3111/***************************************************************************
3112 * CPM
3113 ***************************************************************************/
3114#define __cpm_get_pllm() \
3115    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3116#define __cpm_get_plln() \
3117    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3118#define __cpm_get_pllod() \
3119    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3120
3121#define __cpm_get_cdiv() \
3122    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3123#define __cpm_get_hdiv() \
3124    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3125#define __cpm_get_pdiv() \
3126    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3127#define __cpm_get_mdiv() \
3128    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3129#define __cpm_get_ldiv() \
3130    ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3131#define __cpm_get_udiv() \
3132    ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3133#define __cpm_get_i2sdiv() \
3134    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3135#define __cpm_get_pixdiv() \
3136    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3137#define __cpm_get_mscdiv() \
3138    ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3139
3140#define __cpm_set_cdiv(v) \
3141    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3142#define __cpm_set_hdiv(v) \
3143    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3144#define __cpm_set_pdiv(v) \
3145    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3146#define __cpm_set_mdiv(v) \
3147    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3148#define __cpm_set_ldiv(v) \
3149    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3150#define __cpm_set_udiv(v) \
3151    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3152#define __cpm_set_i2sdiv(v) \
3153    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3154#define __cpm_set_pixdiv(v) \
3155    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3156#define __cpm_set_mscdiv(v) \
3157    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3158
3159#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3160#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3161#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3162#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3163#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3164#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3165#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3166#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3167
3168#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3169#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3170#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3171
3172#define __cpm_get_cclk_doze_duty() \
3173    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3174#define __cpm_set_cclk_doze_duty(v) \
3175    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3176
3177#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3178#define __cpm_idle_mode() \
3179    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3180#define __cpm_sleep_mode() \
3181    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3182
3183#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
3184#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3185#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3186#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3187#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3188#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3189#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3190#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3191#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3192#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3193#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3194#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3195#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3196#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3197#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3198#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3199#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3200
3201#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3202#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3203#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3204#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3205#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3206#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3207#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3208#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3209#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3210#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3211#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3212#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3213#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3214#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3215#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3216#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3217#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3218
3219#define __cpm_get_o1st() \
3220    ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3221#define __cpm_set_o1st(v) \
3222    (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3223#define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE)
3224#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE)
3225#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3226
3227
3228#ifdef CONFIG_SYS_EXTAL
3229#define JZ_EXTAL CONFIG_SYS_EXTAL
3230#else
3231#define JZ_EXTAL 3686400
3232#endif
3233#define JZ_EXTAL2 32768 /* RTC clock */
3234
3235/* PLL output frequency */
3236static __inline__ unsigned int __cpm_get_pllout(void)
3237{
3238    unsigned long m, n, no, pllout;
3239    unsigned long cppcr = REG_CPM_CPPCR;
3240    unsigned long od[4] = {1, 2, 2, 4};
3241    if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3242        m = __cpm_get_pllm() + 2;
3243        n = __cpm_get_plln() + 2;
3244        no = od[__cpm_get_pllod()];
3245        pllout = ((JZ_EXTAL) / (n * no)) * m;
3246    } else
3247        pllout = JZ_EXTAL;
3248    return pllout;
3249}
3250
3251/* PLL output frequency for MSC/I2S/LCD/USB */
3252static __inline__ unsigned int __cpm_get_pllout2(void)
3253{
3254    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3255        return __cpm_get_pllout();
3256    else
3257        return __cpm_get_pllout()/2;
3258}
3259
3260/* CPU core clock */
3261static __inline__ unsigned int __cpm_get_cclk(void)
3262{
3263    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3264
3265    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3266}
3267
3268/* AHB system bus clock */
3269static __inline__ unsigned int __cpm_get_hclk(void)
3270{
3271    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3272
3273    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3274}
3275
3276/* Memory bus clock */
3277static __inline__ unsigned int __cpm_get_mclk(void)
3278{
3279    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3280
3281    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3282}
3283
3284/* APB peripheral bus clock */
3285static __inline__ unsigned int __cpm_get_pclk(void)
3286{
3287    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3288
3289    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3290}
3291
3292/* LCDC module clock */
3293static __inline__ unsigned int __cpm_get_lcdclk(void)
3294{
3295    return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3296}
3297
3298/* LCD pixel clock */
3299static __inline__ unsigned int __cpm_get_pixclk(void)
3300{
3301    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3302}
3303
3304/* I2S clock */
3305static __inline__ unsigned int __cpm_get_i2sclk(void)
3306{
3307    if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3308        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3309    }
3310    else {
3311        return JZ_EXTAL;
3312    }
3313}
3314
3315/* USB clock */
3316static __inline__ unsigned int __cpm_get_usbclk(void)
3317{
3318    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3319        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3320    }
3321    else {
3322        return JZ_EXTAL;
3323    }
3324}
3325
3326/* MSC clock */
3327static __inline__ unsigned int __cpm_get_mscclk(void)
3328{
3329    return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3330}
3331
3332/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3333static __inline__ unsigned int __cpm_get_extalclk(void)
3334{
3335    return JZ_EXTAL;
3336}
3337
3338/* RTC clock for CPM,INTC,RTC,TCU,WDT */
3339static __inline__ unsigned int __cpm_get_rtcclk(void)
3340{
3341    return JZ_EXTAL2;
3342}
3343
3344/*
3345 * Output 24MHz for SD and 16MHz for MMC.
3346 */
3347static inline void __cpm_select_msc_clk(int sd)
3348{
3349    unsigned int pllout2 = __cpm_get_pllout2();
3350    unsigned int div = 0;
3351
3352    if (sd) {
3353        div = pllout2 / 24000000;
3354    }
3355    else {
3356        div = pllout2 / 16000000;
3357    }
3358
3359    REG_CPM_MSCCDR = div - 1;
3360}
3361
3362/*
3363 * TCU
3364 */
3365/* where 'n' is the TCU channel */
3366#define __tcu_select_extalclk(n) \
3367    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3368#define __tcu_select_rtcclk(n) \
3369    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3370#define __tcu_select_pclk(n) \
3371    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3372
3373#define __tcu_select_clk_div1(n) \
3374    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3375#define __tcu_select_clk_div4(n) \
3376    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3377#define __tcu_select_clk_div16(n) \
3378    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3379#define __tcu_select_clk_div64(n) \
3380    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3381#define __tcu_select_clk_div256(n) \
3382    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3383#define __tcu_select_clk_div1024(n) \
3384    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3385
3386#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3387#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3388
3389#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3390#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3391
3392#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3393#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3394
3395#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3396#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3397
3398#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3399#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3400#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3401#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3402#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3403#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3404#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3405#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3406#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3407#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3408
3409#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3410#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3411
3412#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3413#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3414
3415#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3416#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3417
3418#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3419#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3420#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3421#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3422
3423
3424/***************************************************************************
3425 * WDT
3426 ***************************************************************************/
3427#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3428#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3429#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3430#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3431
3432#define __wdt_select_extalclk() \
3433    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3434#define __wdt_select_rtcclk() \
3435    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3436#define __wdt_select_pclk() \
3437    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3438
3439#define __wdt_select_clk_div1() \
3440    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3441#define __wdt_select_clk_div4() \
3442    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3443#define __wdt_select_clk_div16() \
3444    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3445#define __wdt_select_clk_div64() \
3446    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3447#define __wdt_select_clk_div256() \
3448    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3449#define __wdt_select_clk_div1024() \
3450    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3451
3452
3453/***************************************************************************
3454 * UART
3455 ***************************************************************************/
3456
3457#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3458#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3459
3460#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3461#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3462
3463#define __uart_enable_receive_irq() \
3464  ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3465#define __uart_disable_receive_irq() \
3466  ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3467
3468#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3469#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3470
3471#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3472
3473#define __uart_set_baud(devclk, baud) \
3474  do { \
3475    REG8(UART0_LCR) |= UARTLCR_DLAB; \
3476    REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3477    REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3478    REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3479  } while (0)
3480
3481#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3482#define __uart_clear_errors() \
3483  ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3484
3485#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3486#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3487#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3488#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3489#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3490#define __uart_receive_char() REG8(UART0_RDR)
3491#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3492#define __uart_enable_irda() \
3493  /* Tx high pulse as 0, Rx low pulse as 0 */ \
3494  ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3495
3496
3497/***************************************************************************
3498 * DMAC
3499 ***************************************************************************/
3500
3501/* n is the DMA channel (0 - 5) */
3502
3503#define __dmac_enable_module() \
3504  ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3505#define __dmac_disable_module() \
3506  ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3507
3508/* p=0,1,2,3 */
3509#define __dmac_set_priority(p) \
3510do { \
3511    REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
3512    REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
3513} while (0)
3514
3515#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3516#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3517
3518#define __dmac_enable_descriptor(n) \
3519  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3520#define __dmac_disable_descriptor(n) \
3521  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3522
3523#define __dmac_enable_channel(n) \
3524  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3525#define __dmac_disable_channel(n) \
3526  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3527#define __dmac_channel_enabled(n) \
3528  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3529
3530#define __dmac_channel_enable_irq(n) \
3531  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3532#define __dmac_channel_disable_irq(n) \
3533  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3534
3535#define __dmac_channel_transmit_halt_detected(n) \
3536  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3537#define __dmac_channel_transmit_end_detected(n) \
3538  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3539#define __dmac_channel_address_error_detected(n) \
3540  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3541#define __dmac_channel_count_terminated_detected(n) \
3542  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3543#define __dmac_channel_descriptor_invalid_detected(n) \
3544  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3545
3546#define __dmac_channel_clear_transmit_halt(n) \
3547  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3548#define __dmac_channel_clear_transmit_end(n) \
3549  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3550#define __dmac_channel_clear_address_error(n) \
3551  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3552#define __dmac_channel_clear_count_terminated(n) \
3553  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3554#define __dmac_channel_clear_descriptor_invalid(n) \
3555  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3556
3557#define __dmac_channel_set_single_mode(n) \
3558  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3559#define __dmac_channel_set_block_mode(n) \
3560  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3561
3562#define __dmac_channel_set_transfer_unit_32bit(n) \
3563do { \
3564    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3565    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3566} while (0)
3567
3568#define __dmac_channel_set_transfer_unit_16bit(n) \
3569do { \
3570    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3571    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
3572} while (0)
3573
3574#define __dmac_channel_set_transfer_unit_8bit(n) \
3575do { \
3576    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3577    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
3578} while (0)
3579
3580#define __dmac_channel_set_transfer_unit_16byte(n) \
3581do { \
3582    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3583    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
3584} while (0)
3585
3586#define __dmac_channel_set_transfer_unit_32byte(n) \
3587do { \
3588    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3589    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
3590} while (0)
3591
3592/* w=8,16,32 */
3593#define __dmac_channel_set_dest_port_width(n,w) \
3594do { \
3595    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
3596    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
3597} while (0)
3598
3599/* w=8,16,32 */
3600#define __dmac_channel_set_src_port_width(n,w) \
3601do { \
3602    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
3603    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
3604} while (0)
3605
3606/* v=0-15 */
3607#define __dmac_channel_set_rdil(n,v) \
3608do { \
3609    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
3610    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
3611} while (0)
3612
3613#define __dmac_channel_dest_addr_fixed(n) \
3614  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3615#define __dmac_channel_dest_addr_increment(n) \
3616  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3617
3618#define __dmac_channel_src_addr_fixed(n) \
3619  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3620#define __dmac_channel_src_addr_increment(n) \
3621  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3622
3623#define __dmac_channel_set_doorbell(n) \
3624  ( REG_DMAC_DMADBSR = (1 << (n)) )
3625
3626#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
3627#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3628
3629static __inline__ int __dmac_get_irq(void)
3630{
3631    int i;
3632    for (i = 0; i < MAX_DMA_NUM; i++)
3633        if (__dmac_channel_irq_detected(i))
3634            return i;
3635    return -1;
3636}
3637
3638
3639/***************************************************************************
3640 * AIC (AC'97 & I2S Controller)
3641 ***************************************************************************/
3642
3643#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
3644#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
3645
3646#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3647#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
3648
3649#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3650#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3651#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
3652
3653#define __aic_reset() \
3654do { \
3655        REG_AIC_FR |= AIC_FR_RST; \
3656} while(0)
3657
3658
3659#define __aic_set_transmit_trigger(n) \
3660do { \
3661    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
3662    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
3663} while(0)
3664
3665#define __aic_set_receive_trigger(n) \
3666do { \
3667    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
3668    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
3669} while(0)
3670
3671#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
3672#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
3673#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
3674#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
3675#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3676#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3677
3678#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
3679#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3680
3681#define __aic_enable_transmit_intr() \
3682  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3683#define __aic_disable_transmit_intr() \
3684  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3685#define __aic_enable_receive_intr() \
3686  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3687#define __aic_disable_receive_intr() \
3688  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3689
3690#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
3691#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3692#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
3693#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
3694
3695#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
3696#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
3697#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
3698#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3699#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
3700#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3701
3702#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
3703#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
3704#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
3705#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
3706#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
3707#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
3708
3709#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
3710#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
3711#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
3712#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
3713#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
3714#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
3715
3716#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3717#define __ac97_set_xs_mono() \
3718do { \
3719    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3720    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
3721} while(0)
3722#define __ac97_set_xs_stereo() \
3723do { \
3724    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3725    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
3726} while(0)
3727
3728/* In fact, only stereo is support now. */
3729#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3730#define __ac97_set_rs_mono() \
3731do { \
3732    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3733    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
3734} while(0)
3735#define __ac97_set_rs_stereo() \
3736do { \
3737    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3738    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
3739} while(0)
3740
3741#define __ac97_warm_reset_codec() \
3742 do { \
3743    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
3744    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
3745    udelay(2); \
3746    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
3747    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
3748 } while (0)
3749
3750#define __ac97_cold_reset_codec() \
3751 do { \
3752    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
3753    udelay(2); \
3754    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
3755 } while (0)
3756
3757/* n=8,16,18,20 */
3758#define __ac97_set_iass(n) \
3759 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3760#define __ac97_set_oass(n) \
3761 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3762
3763#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3764#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3765
3766/* n=8,16,18,20,24 */
3767/*#define __i2s_set_sample_size(n) \
3768 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3769
3770#define __i2s_set_oss_sample_size(n) \
3771 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3772#define __i2s_set_iss_sample_size(n) \
3773 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3774
3775#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3776#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3777
3778#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
3779#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
3780#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3781#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
3782
3783#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3784
3785#define __aic_get_transmit_resident() \
3786  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3787#define __aic_get_receive_count() \
3788  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3789
3790#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
3791#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
3792#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3793#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3794#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3795#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3796#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3797
3798#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3799
3800#define CODEC_READ_CMD (1 << 19)
3801#define CODEC_WRITE_CMD (0 << 19)
3802#define CODEC_REG_INDEX_BIT 12
3803#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
3804#define CODEC_REG_DATA_BIT 4
3805#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
3806
3807#define __ac97_out_rcmd_addr(reg) \
3808do { \
3809    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3810} while (0)
3811
3812#define __ac97_out_wcmd_addr(reg) \
3813do { \
3814    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3815} while (0)
3816
3817#define __ac97_out_data(value) \
3818do { \
3819    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
3820} while (0)
3821
3822#define __ac97_in_data() \
3823 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3824
3825#define __ac97_in_status_addr() \
3826 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3827
3828#define __i2s_set_sample_rate(i2sclk, sync) \
3829  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3830
3831#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
3832#define __aic_read_rfifo() ( REG_AIC_DR )
3833
3834#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
3835#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
3836
3837/* Define next ops for AC97 compatible */
3838
3839#define AC97_ACSR AIC_ACSR
3840
3841#define __ac97_enable() __aic_enable(); __aic_select_ac97()
3842#define __ac97_disable() __aic_disable()
3843#define __ac97_reset() __aic_reset()
3844
3845#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3846#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
3847
3848#define __ac97_enable_record() __aic_enable_record()
3849#define __ac97_disable_record() __aic_disable_record()
3850#define __ac97_enable_replay() __aic_enable_replay()
3851#define __ac97_disable_replay() __aic_disable_replay()
3852#define __ac97_enable_loopback() __aic_enable_loopback()
3853#define __ac97_disable_loopback() __aic_disable_loopback()
3854
3855#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
3856#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
3857#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
3858#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
3859
3860#define __ac97_transmit_request() __aic_transmit_request()
3861#define __ac97_receive_request() __aic_receive_request()
3862#define __ac97_transmit_underrun() __aic_transmit_underrun()
3863#define __ac97_receive_overrun() __aic_receive_overrun()
3864
3865#define __ac97_clear_errors() __aic_clear_errors()
3866
3867#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
3868#define __ac97_get_receive_count() __aic_get_receive_count()
3869
3870#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
3871#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
3872#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
3873#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
3874
3875#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
3876#define __ac97_read_rfifo() __aic_read_rfifo()
3877
3878/* Define next ops for I2S compatible */
3879
3880#define I2S_ACSR AIC_I2SSR
3881
3882#define __i2s_enable() __aic_enable(); __aic_select_i2s()
3883#define __i2s_disable() __aic_disable()
3884#define __i2s_reset() __aic_reset()
3885
3886#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3887#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
3888
3889#define __i2s_enable_record() __aic_enable_record()
3890#define __i2s_disable_record() __aic_disable_record()
3891#define __i2s_enable_replay() __aic_enable_replay()
3892#define __i2s_disable_replay() __aic_disable_replay()
3893#define __i2s_enable_loopback() __aic_enable_loopback()
3894#define __i2s_disable_loopback() __aic_disable_loopback()
3895
3896#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
3897#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
3898#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
3899#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
3900
3901#define __i2s_transmit_request() __aic_transmit_request()
3902#define __i2s_receive_request() __aic_receive_request()
3903#define __i2s_transmit_underrun() __aic_transmit_underrun()
3904#define __i2s_receive_overrun() __aic_receive_overrun()
3905
3906#define __i2s_clear_errors() __aic_clear_errors()
3907
3908#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
3909#define __i2s_get_receive_count() __aic_get_receive_count()
3910
3911#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
3912#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
3913#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
3914#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
3915
3916#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
3917#define __i2s_read_rfifo() __aic_read_rfifo()
3918
3919#define __i2s_reset_codec() \
3920 do { \
3921 } while (0)
3922
3923
3924/***************************************************************************
3925 * ICDC
3926 ***************************************************************************/
3927#define __i2s_internal_codec() __aic_internal_codec()
3928#define __i2s_external_codec() __aic_external_codec()
3929
3930/***************************************************************************
3931 * INTC
3932 ***************************************************************************/
3933#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
3934#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
3935#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
3936
3937
3938/***************************************************************************
3939 * I2C
3940 ***************************************************************************/
3941
3942#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
3943#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
3944
3945#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
3946#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
3947#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
3948#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
3949
3950#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
3951#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
3952#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
3953
3954#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
3955#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
3956#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
3957
3958#define __i2c_set_clk(dev_clk, i2c_clk) \
3959  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
3960
3961#define __i2c_read() ( REG_I2C_DR )
3962#define __i2c_write(val) ( REG_I2C_DR = (val) )
3963
3964
3965/***************************************************************************
3966 * MSC
3967 ***************************************************************************/
3968
3969#define __msc_start_op() \
3970  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
3971
3972#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
3973#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
3974#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
3975#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
3976#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
3977#define __msc_get_nob() ( REG_MSC_NOB )
3978#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
3979#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
3980#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
3981#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
3982
3983#define __msc_set_cmdat_bus_width1() \
3984do { \
3985    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
3986    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
3987} while(0)
3988
3989#define __msc_set_cmdat_bus_width4() \
3990do { \
3991    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
3992    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
3993} while(0)
3994
3995#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
3996#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
3997#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
3998#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
3999#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4000#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4001#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4002#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4003
4004/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4005#define __msc_set_cmdat_res_format(r) \
4006do { \
4007    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4008    REG_MSC_CMDAT |= (r); \
4009} while(0)
4010
4011#define __msc_clear_cmdat() \
4012  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4013  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4014  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4015
4016#define __msc_get_imask() ( REG_MSC_IMASK )
4017#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4018#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4019#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4020#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4021#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4022#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4023#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4024#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4025#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4026#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4027#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4028#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4029
4030/* n=0,1,2,3,4,5,6,7 */
4031#define __msc_set_clkrt(n) \
4032do { \
4033    REG_MSC_CLKRT = n; \
4034} while(0)
4035
4036#define __msc_get_ireg() ( REG_MSC_IREG )
4037#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4038#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4039#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4040#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4041#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4042#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4043#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4044#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4045
4046#define __msc_get_stat() ( REG_MSC_STAT )
4047#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4048#define __msc_stat_crc_err() \
4049  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4050#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4051#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4052#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4053#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4054#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4055
4056#define __msc_rd_resfifo() ( REG_MSC_RES )
4057#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4058#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4059
4060#define __msc_reset() \
4061do { \
4062    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4063     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4064} while (0)
4065
4066#define __msc_start_clk() \
4067do { \
4068    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4069} while (0)
4070
4071#define __msc_stop_clk() \
4072do { \
4073    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4074} while (0)
4075
4076#define MMC_CLK 19169200
4077#define SD_CLK 24576000
4078
4079/* msc_clk should little than pclk and little than clk retrieve from card */
4080#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4081do { \
4082    unsigned int rate, pclk, i; \
4083    pclk = dev_clk; \
4084    rate = type?SD_CLK:MMC_CLK; \
4085      if (msc_clk && msc_clk < pclk) \
4086            pclk = msc_clk; \
4087    i = 0; \
4088      while (pclk < rate) \
4089        { \
4090              i ++; \
4091              rate >>= 1; \
4092        } \
4093      lv = i; \
4094} while(0)
4095
4096/* divide rate to little than or equal to 400kHz */
4097#define __msc_calc_slow_clk_divisor(type, lv) \
4098do { \
4099    unsigned int rate, i; \
4100    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4101    i = 0; \
4102    while (rate > 0) \
4103        { \
4104              rate >>= 1; \
4105              i ++; \
4106        } \
4107      lv = i; \
4108} while(0)
4109
4110
4111/***************************************************************************
4112 * SSI
4113 ***************************************************************************/
4114
4115#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4116#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4117#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4118
4119#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4120
4121#define __ssi_select_ce2() \
4122do { \
4123    REG_SSI_CR0 |= SSI_CR0_FSEL; \
4124    REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
4125} while (0)
4126
4127#define __ssi_select_gpc() \
4128do { \
4129    REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
4130    REG_SSI_CR1 |= SSI_CR1_MULTS; \
4131} while (0)
4132
4133#define __ssi_enable_tx_intr() \
4134  ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4135
4136#define __ssi_disable_tx_intr() \
4137  ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4138
4139#define __ssi_enable_rx_intr() \
4140