Date:2010-05-09 17:40:25 (4 years 6 months ago)
Author:Xiangfu Liu
Commit:c0f7879da8420931e904fa529f439e4731faf7f7
Message:remove u-boot under target/linux/xburst/image, use package/uboot-xburst instead

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
Files: target/linux/xburst/image/Config.in (1 diff)
target/linux/xburst/image/Makefile (1 diff)
target/linux/xburst/image/u-boot/Makefile (1 diff)
target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch (1 diff)
target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch (1 diff)
target/linux/xburst/image/u-boot/patches/0003-add-sakc-support.patch (1 diff)

Change Details

target/linux/xburst/image/Config.in
1config XBURST_UBOOT
2    bool "Build U-Boot bootloader"
3    depends TARGET_xburst
4    default n
5
6config XBURST_UBOOT_TARGET
7    string "U-Boot target board"
8    depends TARGET_xburst
9    depends XBURST_UBOOT
10    default "qi_lb60"
11    help
12      For all supported boards there are ready-to-use default
13        configurations available; just type "<board_name>".
target/linux/xburst/image/Makefile
1717UBINIZE_OPTS = -m 2048 -p 128KiB -s 512
1818endif
1919
20ifneq ($(CONFIG_XBURST_UBOOT),)
21  define Build/Clean
22    $(MAKE) -C u-boot clean
23  endef
24
25  define Build/Compile
26    $(MAKE) -C u-boot compile
27  endef
28endif
29
3020define Image/BuildKernel
3121    cp $(LINUX_DIR)/arch/mips/boot/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage.bin
3222endef
target/linux/xburst/image/u-boot/Makefile
1#
2# Copyright (C) 2009 Qi Hardware, Inc.
3#
4# This is free software, licensed under the GNU General Public License v3
5# or any later.
6# See /LICENSE for more information.
7#
8
9include $(TOPDIR)/rules.mk
10include $(INCLUDE_DIR)/kernel.mk
11
12PKG_NAME:=u-boot
13PKG_VERSION:=2009.11
14
15PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
16PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
17PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
18PKG_CAT:=bzcat
19
20include $(INCLUDE_DIR)/package.mk
21
22UBOOT_CONFIG=$(strip $(subst ",, $(CONFIG_XBURST_UBOOT_TARGET)))
23
24define Build/Compile
25    $(MAKE) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIG)_config
26    $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=$(TARGET_CROSS)
27endef
28
29define Build/InstallDev
30    mkdir -p $(BIN_DIR)
31    cp $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/openwrt-$(BOARD)-u-boot.bin
32endef
33
34$(eval $(call Build/DefaultTargets))
target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch
1this patch include all the new files
2
3From: Xiangfu Liu <xiangfu@sharism.com>
4
5
6
7 board/qi_lb60/Makefile | 38
8 board/qi_lb60/config.mk | 31
9 board/qi_lb60/qi_lb60.c | 122 +
10 board/qi_lb60/u-boot-nand.lds | 63
11 board/qi_lb60/u-boot.lds | 63
12 cpu/mips/jz4740.c | 571 ++++
13 cpu/mips/jz4740_nand.c | 199 ++
14 cpu/mips/jz_i2c.c | 234 ++
15 cpu/mips/jz_mmc.c | 1404 +++++++++++
16 cpu/mips/jz_mmc.h | 113 +
17 cpu/mips/jz_serial.c | 159 +
18 cpu/mips/mmc_protocol.h | 273 ++
19 cpu/mips/qi_lb60_gpm940b0.c | 420 +++
20 cpu/mips/qi_lb60_gpm940b0.h | 212 ++
21 cpu/mips/usb_boot.S | 880 +++++++
22 include/asm-mips/jz4740.h | 4880 +++++++++++++++++++++++++++++++++++++
23 include/configs/qi_lb60.h | 215 ++
24 nand_spl/board/qi_lb60/Makefile | 104 +
25 nand_spl/board/qi_lb60/config.mk | 34
26 nand_spl/board/qi_lb60/u-boot.lds | 63
27 nand_spl/nand_boot_jz4740.c | 438 +++
28 21 files changed, 10516 insertions(+), 0 deletions(-)
29 create mode 100644 board/qi_lb60/Makefile
30 create mode 100644 board/qi_lb60/config.mk
31 create mode 100644 board/qi_lb60/qi_lb60.c
32 create mode 100644 board/qi_lb60/u-boot-nand.lds
33 create mode 100644 board/qi_lb60/u-boot.lds
34 create mode 100644 cpu/mips/jz4740.c
35 create mode 100644 cpu/mips/jz4740_nand.c
36 create mode 100644 cpu/mips/jz_i2c.c
37 create mode 100644 cpu/mips/jz_mmc.c
38 create mode 100644 cpu/mips/jz_mmc.h
39 create mode 100644 cpu/mips/jz_serial.c
40 create mode 100644 cpu/mips/mmc_protocol.h
41 create mode 100644 cpu/mips/qi_lb60_gpm940b0.c
42 create mode 100644 cpu/mips/qi_lb60_gpm940b0.h
43 create mode 100644 cpu/mips/usb_boot.S
44 create mode 100644 include/asm-mips/jz4740.h
45 create mode 100644 include/configs/qi_lb60.h
46 create mode 100644 nand_spl/board/qi_lb60/Makefile
47 create mode 100644 nand_spl/board/qi_lb60/config.mk
48 create mode 100644 nand_spl/board/qi_lb60/u-boot.lds
49 create mode 100644 nand_spl/nand_boot_jz4740.c
50
51
52diff --git a/board/qi_lb60/Makefile b/board/qi_lb60/Makefile
53new file mode 100644
54index 0000000..470447d
55+++ b/board/qi_lb60/Makefile
56@@ -0,0 +1,38 @@
57+#
58+# (C) Copyright 2006
59+# Ingenic Semiconductor, <jlwei@ingenic.cn>
60+#
61+# This program is free software; you can redistribute it and/or
62+# modify it under the terms of the GNU General Public License as
63+# published by the Free Software Foundation; either version 2 of
64+# the License, or (at your option) any later version.
65+#
66+# This program is distributed in the hope that it will be useful,
67+# but WITHOUT ANY WARRANTY; without even the implied warranty of
68+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
69+# GNU General Public License for more details.
70+#
71+# You should have received a copy of the GNU General Public License
72+# along with this program; if not, write to the Free Software
73+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
74+# MA 02111-1307 USA
75+#
76+
77+include $(TOPDIR)/config.mk
78+
79+LIB = lib$(BOARD).a
80+
81+OBJS = $(BOARD).o
82+SOBJS =
83+
84+$(LIB): .depend $(OBJS) $(SOBJS)
85+ $(AR) crv $@ $(OBJS) $(SOBJS)
86+
87+#########################################################################
88+
89+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
90+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
91+
92+sinclude .depend
93+
94+#########################################################################
95diff --git a/board/qi_lb60/config.mk b/board/qi_lb60/config.mk
96new file mode 100644
97index 0000000..858e6a2
98+++ b/board/qi_lb60/config.mk
99@@ -0,0 +1,31 @@
100+#
101+# (C) Copyright 2006 Qi Hardware, Inc.
102+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
103+#
104+# This program is free software; you can redistribute it and/or
105+# modify it under the terms of the GNU General Public License as
106+# published by the Free Software Foundation; either version 2 of
107+# the License, or (at your option) any later version.
108+#
109+# This program is distributed in the hope that it will be useful,
110+# but WITHOUT ANY WARRANTY; without even the implied warranty of
111+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
112+# GNU General Public License for more details.
113+#
114+# You should have received a copy of the GNU General Public License
115+# along with this program; if not, write to the Free Software
116+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
117+# MA 02111-1307 USA
118+#
119+
120+#
121+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
122+#
123+
124+ifndef TEXT_BASE
125+# ROM version
126+# TEXT_BASE = 0x88000000
127+
128+# RAM version
129+TEXT_BASE = 0x80100000
130+endif
131diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c
132new file mode 100644
133index 0000000..aa7b85b
134+++ b/board/qi_lb60/qi_lb60.c
135@@ -0,0 +1,122 @@
136+/*
137+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
138+ *
139+ * This program is free software; you can redistribute it and/or
140+ * modify it under the terms of the GNU General Public License
141+ * as published by the Free Software Foundation; either version
142+ * 3 of the License, or (at your option) any later version.
143+ */
144+
145+#include <common.h>
146+#include <command.h>
147+#include <asm/mipsregs.h>
148+#include <asm/jz4740.h>
149+
150+DECLARE_GLOBAL_DATA_PTR;
151+
152+static void gpio_init(void)
153+{
154+ /*
155+ * Initialize NAND Flash Pins
156+ */
157+ __gpio_as_nand();
158+
159+ /*
160+ * Initialize SDRAM pins
161+ */
162+ __gpio_as_sdram_32bit();
163+
164+ /*
165+ * Initialize LCD pins
166+ */
167+ __gpio_as_lcd_18bit();
168+
169+ /*
170+ * Initialize MSC pins
171+ */
172+ __gpio_as_msc();
173+
174+ /*
175+ * Initialize Other pins
176+ */
177+ unsigned int i;
178+ for (i = 0; i < 7; i++){
179+ __gpio_as_input(GPIO_KEYIN_BASE + i);
180+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
181+ }
182+
183+ for (i = 0; i < 8; i++) {
184+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
185+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
186+ }
187+
188+ /*
189+ * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
190+ * same gpio, init the gpio as uart0 cause a keyboard bug. so for
191+ * end user we disable the uart0
192+ */
193+ if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
194+ /* if pressed [S] */
195+ printf("[S] pressed, enable UART0\n");
196+ gd->boot_option = 5;
197+ __gpio_as_uart0();
198+ } else {
199+ printf("[S] not pressed, disable UART0\n");
200+ __gpio_as_input(GPIO_KEYIN_8);
201+ __gpio_enable_pull(GPIO_KEYIN_8);
202+ }
203+
204+ __gpio_as_output(GPIO_AUDIO_POP);
205+ __gpio_set_pin(GPIO_AUDIO_POP);
206+
207+ __gpio_as_output(GPIO_LCD_CS);
208+ __gpio_clear_pin(GPIO_LCD_CS);
209+
210+ __gpio_as_output(GPIO_AMP_EN);
211+ __gpio_clear_pin(GPIO_AMP_EN);
212+
213+ __gpio_as_output(GPIO_SDPW_EN);
214+ __gpio_disable_pull(GPIO_SDPW_EN);
215+ __gpio_clear_pin(GPIO_SDPW_EN);
216+
217+ __gpio_as_input(GPIO_SD_DETECT);
218+ __gpio_disable_pull(GPIO_SD_DETECT);
219+
220+ __gpio_as_input(GPIO_USB_DETECT);
221+ __gpio_enable_pull(GPIO_USB_DETECT);
222+
223+ if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
224+ printf("[M] pressed, boot from sd card\n");
225+ gd->boot_option = 1;
226+ }
227+}
228+
229+static void cpm_init(void)
230+{
231+ __cpm_stop_ipu();
232+ __cpm_stop_cim();
233+ __cpm_stop_i2c();
234+ __cpm_stop_ssi();
235+ __cpm_stop_uart1();
236+ __cpm_stop_sadc();
237+ __cpm_stop_uhc();
238+ __cpm_stop_aic1();
239+ __cpm_stop_aic2();
240+}
241+
242+void board_early_init(void)
243+{
244+ gpio_init();
245+ cpm_init();
246+}
247+
248+/* U-Boot common routines */
249+
250+int checkboard (void)
251+{
252+
253+ printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
254+ gd->cpu_clk/1000000);
255+
256+ return 0; /* success */
257+}
258diff --git a/board/qi_lb60/u-boot-nand.lds b/board/qi_lb60/u-boot-nand.lds
259new file mode 100644
260index 0000000..a15a96e
261+++ b/board/qi_lb60/u-boot-nand.lds
262@@ -0,0 +1,63 @@
263+/*
264+ * (C) Copyright 2006
265+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
266+ *
267+ * This program is free software; you can redistribute it and/or
268+ * modify it under the terms of the GNU General Public License as
269+ * published by the Free Software Foundation; either version 2 of
270+ * the License, or (at your option) any later version.
271+ *
272+ * This program is distributed in the hope that it will be useful,
273+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
274+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
275+ * GNU General Public License for more details.
276+ *
277+ * You should have received a copy of the GNU General Public License
278+ * along with this program; if not, write to the Free Software
279+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
280+ * MA 02111-1307 USA
281+ */
282+
283+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
284+
285+OUTPUT_ARCH(mips)
286+ENTRY(_start)
287+SECTIONS
288+{
289+ . = 0x00000000;
290+
291+ . = ALIGN(4);
292+ .text :
293+ {
294+ *(.text)
295+ }
296+
297+ . = ALIGN(4);
298+ .rodata : { *(.rodata) }
299+
300+ . = ALIGN(4);
301+ .data : { *(.data) }
302+
303+ . = ALIGN(4);
304+ .sdata : { *(.sdata) }
305+
306+ _gp = ALIGN(16);
307+
308+ __got_start = .;
309+ .got : { *(.got) }
310+ __got_end = .;
311+
312+ .sdata : { *(.sdata) }
313+
314+ __u_boot_cmd_start = .;
315+ .u_boot_cmd : { *(.u_boot_cmd) }
316+ __u_boot_cmd_end = .;
317+
318+ uboot_end_data = .;
319+ num_got_entries = (__got_end - __got_start) >> 2;
320+
321+ . = ALIGN(4);
322+ .sbss : { *(.sbss) }
323+ .bss : { *(.bss) }
324+ uboot_end = .;
325+}
326diff --git a/board/qi_lb60/u-boot.lds b/board/qi_lb60/u-boot.lds
327new file mode 100644
328index 0000000..a15a96e
329+++ b/board/qi_lb60/u-boot.lds
330@@ -0,0 +1,63 @@
331+/*
332+ * (C) Copyright 2006
333+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
334+ *
335+ * This program is free software; you can redistribute it and/or
336+ * modify it under the terms of the GNU General Public License as
337+ * published by the Free Software Foundation; either version 2 of
338+ * the License, or (at your option) any later version.
339+ *
340+ * This program is distributed in the hope that it will be useful,
341+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
342+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
343+ * GNU General Public License for more details.
344+ *
345+ * You should have received a copy of the GNU General Public License
346+ * along with this program; if not, write to the Free Software
347+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
348+ * MA 02111-1307 USA
349+ */
350+
351+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
352+
353+OUTPUT_ARCH(mips)
354+ENTRY(_start)
355+SECTIONS
356+{
357+ . = 0x00000000;
358+
359+ . = ALIGN(4);
360+ .text :
361+ {
362+ *(.text)
363+ }
364+
365+ . = ALIGN(4);
366+ .rodata : { *(.rodata) }
367+
368+ . = ALIGN(4);
369+ .data : { *(.data) }
370+
371+ . = ALIGN(4);
372+ .sdata : { *(.sdata) }
373+
374+ _gp = ALIGN(16);
375+
376+ __got_start = .;
377+ .got : { *(.got) }
378+ __got_end = .;
379+
380+ .sdata : { *(.sdata) }
381+
382+ __u_boot_cmd_start = .;
383+ .u_boot_cmd : { *(.u_boot_cmd) }
384+ __u_boot_cmd_end = .;
385+
386+ uboot_end_data = .;
387+ num_got_entries = (__got_end - __got_start) >> 2;
388+
389+ . = ALIGN(4);
390+ .sbss : { *(.sbss) }
391+ .bss : { *(.bss) }
392+ uboot_end = .;
393+}
394diff --git a/cpu/mips/jz4740.c b/cpu/mips/jz4740.c
395new file mode 100644
396index 0000000..c32d15e
397+++ b/cpu/mips/jz4740.c
398@@ -0,0 +1,571 @@
399+/*
400+ * Jz4740 common routines
401+ *
402+ * Copyright (c) 2006
403+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
404+ *
405+ * This program is free software; you can redistribute it and/or
406+ * modify it under the terms of the GNU General Public License as
407+ * published by the Free Software Foundation; either version 2 of
408+ * the License, or (at your option) any later version.
409+ *
410+ * This program is distributed in the hope that it will be useful,
411+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
412+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
413+ * GNU General Public License for more details.
414+ *
415+ * You should have received a copy of the GNU General Public License
416+ * along with this program; if not, write to the Free Software
417+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
418+ * MA 02111-1307 USA
419+ */
420+
421+#include <config.h>
422+
423+#include <common.h>
424+#include <command.h>
425+#include <asm/jz4740.h>
426+
427+extern void board_early_init(void);
428+
429+/* PLL output clock = EXTAL * NF / (NR * NO)
430+ *
431+ * NF = FD + 2, NR = RD + 2
432+ * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
433+ */
434+void pll_init(void)
435+{
436+ register unsigned int cfcr, plcr1;
437+ int n2FR[33] = {
438+ 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
439+ 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
440+ 9
441+ };
442+ int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
443+ int nf, pllout2;
444+
445+ cfcr = CPM_CPCCR_CLKOEN |
446+ CPM_CPCCR_PCS |
447+ (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
448+ (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
449+ (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
450+ (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
451+ (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
452+
453+ pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_CPU_SPEED : (CONFIG_CPU_SPEED / 2);
454+
455+ /* Init USB Host clock, pllout2 must be n*48MHz */
456+ REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
457+
458+ nf = CONFIG_CPU_SPEED * 2 / CONFIG_EXTAL;
459+ plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
460+ (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
461+ (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
462+ (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
463+ CPM_CPPCR_PLLEN; /* enable PLL */
464+
465+ /* init PLL */
466+ REG_CPM_CPCCR = cfcr;
467+ REG_CPM_CPPCR = plcr1;
468+}
469+
470+void pll_add_test(int new_freq)
471+{
472+ register unsigned int cfcr, plcr1;
473+ int n2FR[33] = {
474+ 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
475+ 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
476+ 9
477+ };
478+ int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
479+ int nf, pllout2;
480+
481+ cfcr = CPM_CPCCR_CLKOEN |
482+ (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
483+ (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
484+ (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
485+ (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
486+ (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
487+
488+ pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
489+
490+ /* Init UHC clock */
491+ REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
492+
493+ /* nf = new_freq * 2 / CONFIG_EXTAL; */
494+ nf = new_freq / 1000000; /* step length is 1M */
495+ plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
496+ (10 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
497+ (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
498+ (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
499+ CPM_CPPCR_PLLEN; /* enable PLL */
500+
501+ /* init PLL */
502+ REG_CPM_CPCCR = cfcr;
503+ REG_CPM_CPPCR = plcr1;
504+}
505+
506+void calc_clocks_add_test(void)
507+{
508+ DECLARE_GLOBAL_DATA_PTR;
509+
510+#ifndef CONFIG_FPGA
511+ unsigned int pllout;
512+ unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
513+
514+ pllout = __cpm_get_pllout();
515+
516+ gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
517+ gd->sys_clk = pllout / div[__cpm_get_hdiv()];
518+ gd->per_clk = pllout / div[__cpm_get_pdiv()];
519+ gd->mem_clk = pllout / div[__cpm_get_mdiv()];
520+ gd->dev_clk = CONFIG_EXTAL;
521+#else
522+ gd->cpu_clk = gd->sys_clk = gd->per_clk =
523+ gd->mem_clk = gd->dev_clk = CONFIG_EXTAL;
524+#endif
525+}
526+
527+void sdram_add_test(int new_freq)
528+{
529+ register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
530+
531+ unsigned int cas_latency_sdmr[2] = {
532+ EMC_SDMR_CAS_2,
533+ EMC_SDMR_CAS_3,
534+ };
535+
536+ unsigned int cas_latency_dmcr[2] = {
537+ 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
538+ 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
539+ };
540+
541+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
542+
543+ cpu_clk = new_freq;
544+ mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
545+
546+ REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
547+ REG_EMC_RTCOR = 0;
548+ REG_EMC_RTCNT = 0;
549+
550+ /* Basic DMCR register value. */
551+ dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
552+ ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
553+ (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
554+ (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
555+ EMC_DMCR_EPIN |
556+ cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
557+
558+ /* SDRAM timimg parameters */
559+ ns = 1000000000 / mem_clk;
560+
561+#if 0
562+ tmp = SDRAM_TRAS/ns;
563+ if (tmp < 4) tmp = 4;
564+ if (tmp > 11) tmp = 11;
565+ dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
566+
567+ tmp = SDRAM_RCD/ns;
568+ if (tmp > 3) tmp = 3;
569+ dmcr |= (tmp << EMC_DMCR_RCD_BIT);
570+
571+ tmp = SDRAM_TPC/ns;
572+ if (tmp > 7) tmp = 7;
573+ dmcr |= (tmp << EMC_DMCR_TPC_BIT);
574+
575+ tmp = SDRAM_TRWL/ns;
576+ if (tmp > 3) tmp = 3;
577+ dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
578+
579+ tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
580+ if (tmp > 14) tmp = 14;
581+ dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
582+#else
583+ dmcr |= 0xfffc;
584+#endif
585+
586+ /* First, precharge phase */
587+ REG_EMC_DMCR = dmcr;
588+
589+ /* Set refresh registers */
590+ tmp = SDRAM_TREF/ns;
591+ tmp = tmp/64 + 1;
592+ if (tmp > 0xff) tmp = 0xff;
593+
594+ REG_EMC_RTCOR = tmp;
595+ REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
596+
597+ /* SDRAM mode values */
598+ sdmode = EMC_SDMR_BT_SEQ |
599+ EMC_SDMR_OM_NORMAL |
600+ EMC_SDMR_BL_4 |
601+ cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
602+
603+ /* precharge all chip-selects */
604+ REG8(EMC_SDMR0|sdmode) = 0;
605+
606+ /* wait for precharge, > 200us */
607+ tmp = (cpu_clk / 1000000) * 200;
608+ while (tmp--);
609+
610+ /* enable refresh and set SDRAM mode */
611+ REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
612+
613+ /* write sdram mode register for each chip-select */
614+ REG8(EMC_SDMR0|sdmode) = 0;
615+
616+ /* everything is ok now */
617+}
618+
619+void sdram_init(void)
620+{
621+ register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
622+
623+ unsigned int cas_latency_sdmr[2] = {
624+ EMC_SDMR_CAS_2,
625+ EMC_SDMR_CAS_3,
626+ };
627+
628+ unsigned int cas_latency_dmcr[2] = {
629+ 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
630+ 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
631+ };
632+
633+ int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
634+
635+ cpu_clk = CONFIG_CPU_SPEED;
636+ mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
637+
638+ REG_EMC_BCR = 0; /* Disable bus release */
639+ REG_EMC_RTCSR = 0; /* Disable clock for counting */
640+
641+ /* Fault DMCR value for mode register setting*/
642+#define SDRAM_ROW0 11
643+#define SDRAM_COL0 8
644+#define SDRAM_BANK40 0
645+
646+ dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
647+ ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
648+ (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
649+ (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
650+ EMC_DMCR_EPIN |
651+ cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
652+
653+ /* Basic DMCR value */
654+ dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
655+ ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
656+ (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
657+ (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
658+ EMC_DMCR_EPIN |
659+ cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
660+
661+ /* SDRAM timimg */
662+ ns = 1000000000 / mem_clk;
663+ tmp = SDRAM_TRAS/ns;
664+ if (tmp < 4) tmp = 4;
665+ if (tmp > 11) tmp = 11;
666+ dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
667+ tmp = SDRAM_RCD/ns;
668+ if (tmp > 3) tmp = 3;
669+ dmcr |= (tmp << EMC_DMCR_RCD_BIT);
670+ tmp = SDRAM_TPC/ns;
671+ if (tmp > 7) tmp = 7;
672+ dmcr |= (tmp << EMC_DMCR_TPC_BIT);
673+ tmp = SDRAM_TRWL/ns;
674+ if (tmp > 3) tmp = 3;
675+ dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
676+ tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
677+ if (tmp > 14) tmp = 14;
678+ dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
679+
680+ /* SDRAM mode value */
681+ sdmode = EMC_SDMR_BT_SEQ |
682+ EMC_SDMR_OM_NORMAL |
683+ EMC_SDMR_BL_4 |
684+ cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
685+
686+ /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
687+ REG_EMC_DMCR = dmcr;
688+ REG8(EMC_SDMR0|sdmode) = 0;
689+
690+ /* Wait for precharge, > 200us */
691+ tmp = (cpu_clk / 1000000) * 1000;
692+ while (tmp--);
693+
694+ /* Stage 2. Enable auto-refresh */
695+ REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
696+
697+ tmp = SDRAM_TREF/ns;
698+ tmp = tmp/64 + 1;
699+ if (tmp > 0xff) tmp = 0xff;
700+ REG_EMC_RTCOR = tmp;
701+ REG_EMC_RTCNT = 0;
702+ REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
703+
704+ /* Wait for number of auto-refresh cycles */
705+ tmp = (cpu_clk / 1000000) * 1000;
706+ while (tmp--);
707+
708+ /* Stage 3. Mode Register Set */
709+ REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
710+ REG8(EMC_SDMR0|sdmode) = 0;
711+
712+ /* Set back to basic DMCR value */
713+ REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
714+
715+ /* everything is ok now */
716+}
717+
718+#ifndef CONFIG_NAND_SPL
719+
720+static void calc_clocks(void)
721+{
722+ DECLARE_GLOBAL_DATA_PTR;
723+
724+#ifndef CONFIG_FPGA
725+ unsigned int pllout;
726+ unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
727+
728+ pllout = __cpm_get_pllout();
729+
730+ gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
731+ gd->sys_clk = pllout / div[__cpm_get_hdiv()];
732+ gd->per_clk = pllout / div[__cpm_get_pdiv()];
733+ gd->mem_clk = pllout / div[__cpm_get_mdiv()];
734+ gd->dev_clk = CONFIG_EXTAL;
735+#else
736+ gd->cpu_clk = gd->sys_clk = gd->per_clk =
737+ gd->mem_clk = gd->dev_clk = CONFIG_EXTAL;
738+#endif
739+}
740+
741+static void rtc_init(void)
742+{
743+ unsigned long rtcsta;
744+
745+ while ( !__rtc_write_ready()) ;
746+ __rtc_enable_alarm(); /* enable alarm */
747+
748+ while ( !__rtc_write_ready())
749+ ;
750+ REG_RTC_RGR = 0x00007fff; /* type value */
751+
752+ while ( !__rtc_write_ready())
753+ ;
754+ REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
755+
756+ while ( !__rtc_write_ready())
757+ ;
758+ REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
759+#if 0
760+ while ( !__rtc_write_ready())
761+ ;
762+ rtcsta = REG_RTC_HWRSR;
763+ while ( !__rtc_write_ready())
764+ ;
765+ if (rtcsta & 0x33) {
766+ if (rtcsta & 0x10) {
767+ while ( !__rtc_write_ready())
768+ ;
769+ REG_RTC_RSR = 0x0;
770+ }
771+ while ( !__rtc_write_ready())
772+ ;
773+ REG_RTC_HWRSR = 0x0;
774+ }
775+#endif
776+}
777+
778+
779+/*
780+ * jz4740 board init routine
781+ */
782+int jz_board_init(void)
783+{
784+ board_early_init(); /* init gpio, pll etc. */
785+#ifndef CONFIG_NAND_U_BOOT
786+#ifndef CONFIG_FPGA
787+ pll_init(); /* init PLL */
788+#endif
789+ sdram_init(); /* init sdram memory */
790+#endif
791+ calc_clocks(); /* calc the clocks */
792+#ifndef CONFIG_FPGA
793+ rtc_init(); /* init rtc on any reset: */
794+#endif
795+ return 0;
796+}
797+
798+/* U-Boot common routines */
799+phys_size_t initdram(int board_type)
800+{
801+ u32 dmcr;
802+ u32 rows, cols, dw, banks;
803+ ulong size;
804+
805+ dmcr = REG_EMC_DMCR;
806+ rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
807+ cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
808+ dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
809+ banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
810+
811+ size = (1 << (rows + cols)) * dw * banks;
812+
813+ return size;
814+}
815+
816+/*
817+ * Timer routines
818+ */
819+
820+#define TIMER_CHAN 0
821+#define TIMER_FDATA 0xffff /* Timer full data value */
822+#define TIMER_HZ CONFIG_SYS_HZ
823+
824+#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
825+
826+static ulong timestamp;
827+static ulong lastdec;
828+
829+void reset_timer_masked (void);
830+ulong get_timer_masked (void);
831+void udelay_masked (unsigned long usec);
832+
833+/*
834+ * timer without interrupts
835+ */
836+
837+int timer_init(void)
838+{
839+ REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
840+ REG_TCU_TCNT(TIMER_CHAN) = 0;
841+ REG_TCU_TDHR(TIMER_CHAN) = 0;
842+ REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
843+
844+ REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
845+ REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
846+ REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
847+
848+ lastdec = 0;
849+ timestamp = 0;
850+
851+ return 0;
852+}
853+
854+void reset_timer(void)
855+{
856+ reset_timer_masked ();
857+}
858+
859+ulong get_timer(ulong base)
860+{
861+ return get_timer_masked () - base;
862+}
863+
864+void set_timer(ulong t)
865+{
866+ timestamp = t;
867+}
868+
869+void udelay (unsigned long usec)
870+{
871+ ulong tmo,tmp;
872+
873+ /* normalize */
874+ if (usec >= 1000) {
875+ tmo = usec / 1000;
876+ tmo *= TIMER_HZ;
877+ tmo /= 1000;
878+ }
879+ else {
880+ if (usec >= 1) {
881+ tmo = usec * TIMER_HZ;
882+ tmo /= (1000*1000);
883+ }
884+ else
885+ tmo = 1;
886+ }
887+
888+ /* check for rollover during this delay */
889+ tmp = get_timer (0);
890+ if ((tmp + tmo) < tmp )
891+ reset_timer_masked(); /* timer would roll over */
892+ else
893+ tmo += tmp;
894+
895+ while (get_timer_masked () < tmo);
896+}
897+
898+void reset_timer_masked (void)
899+{
900+ /* reset time */
901+ lastdec = READ_TIMER;
902+ timestamp = 0;
903+}
904+
905+ulong get_timer_masked (void)
906+{
907+ ulong now = READ_TIMER;
908+
909+ if (lastdec <= now) {
910+ /* normal mode */
911+ timestamp += (now - lastdec);
912+ } else {
913+ /* we have an overflow ... */
914+ timestamp += TIMER_FDATA + now - lastdec;
915+ }
916+ lastdec = now;
917+
918+ return timestamp;
919+}
920+
921+void udelay_masked (unsigned long usec)
922+{
923+ ulong tmo;
924+ ulong endtime;
925+ signed long diff;
926+
927+ /* normalize */
928+ if (usec >= 1000) {
929+ tmo = usec / 1000;
930+ tmo *= TIMER_HZ;
931+ tmo /= 1000;
932+ } else {
933+ if (usec > 1) {
934+ tmo = usec * TIMER_HZ;
935+ tmo /= (1000*1000);
936+ } else {
937+ tmo = 1;
938+ }
939+ }
940+
941+ endtime = get_timer_masked () + tmo;
942+
943+ do {
944+ ulong now = get_timer_masked ();
945+ diff = endtime - now;
946+ } while (diff >= 0);
947+}
948+
949+/*
950+ * This function is derived from PowerPC code (read timebase as long long).
951+ * On MIPS it just returns the timer value.
952+ */
953+unsigned long long get_ticks(void)
954+{
955+ return get_timer(0);
956+}
957+
958+/*
959+ * This function is derived from PowerPC code (timebase clock frequency).
960+ * On MIPS it returns the number of timer ticks per second.
961+ */
962+ulong get_tbclk (void)
963+{
964+ return TIMER_HZ;
965+}
966+
967+#endif /* CONFIG_NAND_SPL */
968+
969+/* End of timer routine. */
970\ No newline at end of file
971diff --git a/cpu/mips/jz4740_nand.c b/cpu/mips/jz4740_nand.c
972new file mode 100644
973index 0000000..c1d1511
974+++ b/cpu/mips/jz4740_nand.c
975@@ -0,0 +1,199 @@
976+/*
977+ * Platform independend driver for JZ4740.
978+ *
979+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
980+ * Author: <jlwei@ingenic.cn>
981+ *
982+ * This program is free software; you can redistribute it and/or
983+ * modify it under the terms of the GNU General Public License as
984+ * published by the Free Software Foundation; either version 2 of
985+ * the License, or (at your option) any later version.
986+ */
987+#include <common.h>
988+
989+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
990+
991+#include <nand.h>
992+#include <asm/jz4740.h>
993+#include <asm/io.h>
994+
995+#define PAR_SIZE 9
996+#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
997+#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
998+
999+#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
1000+
1001+#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
1002+#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
1003+#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
1004+#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
1005+
1006+static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
1007+{
1008+ struct nand_chip *this = mtd->priv;
1009+ unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
1010+
1011+ if (ctrl & NAND_CTRL_CHANGE) {
1012+ /* Change this to use I/O accessors. */
1013+ if (ctrl & NAND_NCE)
1014+ REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
1015+ else
1016+ REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
1017+ }
1018+
1019+ if (cmd == NAND_CMD_NONE)
1020+ return;
1021+
1022+ if (ctrl & NAND_CLE)
1023+ nandaddr |= 0x00008000;
1024+ else /* must be ALE */
1025+ nandaddr |= 0x00010000;
1026+
1027+ writeb(cmd, (uint8_t *)nandaddr);
1028+}
1029+
1030+static int jz_device_ready(struct mtd_info *mtd)
1031+{
1032+ int ready;
1033+ udelay(20); /* FIXME: add 20us delay */
1034+ ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
1035+ return ready;
1036+}
1037+
1038+/*
1039+ * EMC setup
1040+ */
1041+static void jz_device_setup(void)
1042+{
1043+ /* Set NFE bit */
1044+ REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
1045+ REG_EMC_SMCR1 = 0x094c4400;
1046+ /* REG_EMC_SMCR3 = 0x04444400; */
1047+}
1048+
1049+void board_nand_select_device(struct nand_chip *nand, int chip)
1050+{
1051+ /*
1052+ * Don't use "chip" to address the NAND device,
1053+ * generate the cs from the address where it is encoded.
1054+ */
1055+}
1056+
1057+static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
1058+ u_char* ecc_code)
1059+{
1060+ volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
1061+ short i;
1062+
1063+ __nand_ecc_encode_sync()
1064+ __nand_ecc_disable();
1065+
1066+ for(i = 0; i < PAR_SIZE; i++)
1067+ ecc_code[i] = *paraddr++;
1068+
1069+ return 0;
1070+}
1071+
1072+static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
1073+{
1074+ __nand_ecc_enable();
1075+ __nand_select_rs_ecc();
1076+
1077+ REG_EMC_NFINTS = 0x0;
1078+ if (NAND_ECC_READ == mode){
1079+ __nand_rs_ecc_decoding();
1080+ }
1081+ if (NAND_ECC_WRITE == mode){
1082+ __nand_rs_ecc_encoding();
1083+ }
1084+}
1085+
1086+/* Correct 1~9-bit errors in 512-bytes data */
1087+static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
1088+{
1089+ int i;
1090+
1091+ idx--;
1092+
1093+ i = idx + (idx >> 3);
1094+ if (i >= 512)
1095+ return;
1096+
1097+ mask <<= (idx & 0x7);
1098+
1099+ dat[i] ^= mask & 0xff;
1100+ if (i < 511)
1101+ dat[i+1] ^= (mask >> 8) & 0xff;
1102+}
1103+
1104+static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
1105+ u_char *read_ecc, u_char *calc_ecc)
1106+{
1107+ volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
1108+ short k;
1109+ u32 stat;
1110+ /* Set PAR values */
1111+
1112+ for (k = 0; k < PAR_SIZE; k++) {
1113+ *paraddr++ = read_ecc[k];
1114+ }
1115+
1116+ /* Set PRDY */
1117+ REG_EMC_NFECR |= EMC_NFECR_PRDY;
1118+
1119+ /* Wait for completion */
1120+ __nand_ecc_decode_sync();
1121+ __nand_ecc_disable();
1122+
1123+ /* Check decoding */
1124+ stat = REG_EMC_NFINTS;
1125+ if (stat & EMC_NFINTS_ERR) {
1126+ if (stat & EMC_NFINTS_UNCOR) {
1127+ printk("Uncorrectable error occurred\n");
1128+ return -1;
1129+ }
1130+ else {
1131+ u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
1132+ switch (errcnt) {
1133+ case 4:
1134+ jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
1135+ case 3:
1136+ jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
1137+ case 2:
1138+ jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
1139+ case 1:
1140+ jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
1141+ return 0;
1142+ default:
1143+ break;
1144+ }
1145+ }
1146+ }
1147+ /* no error need to be correct */
1148+ return 0;
1149+}
1150+
1151+/*
1152+ * Main initialization routine
1153+ */
1154+int board_nand_init(struct nand_chip *nand)
1155+{
1156+ jz_device_setup();
1157+
1158+ nand->cmd_ctrl = jz_hwcontrol;
1159+ nand->dev_ready = jz_device_ready;
1160+
1161+ /* FIXME: should use NAND_ECC_SOFT */
1162+ nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
1163+ nand->ecc.correct = jzsoc_nand_rs_correct_data;
1164+ nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
1165+ nand->ecc.mode = NAND_ECC_HW;
1166+ nand->ecc.size = 512;
1167+ nand->ecc.bytes = 9;
1168+
1169+ /* 20 us command delay time */
1170+ nand->chip_delay = 20;
1171+
1172+ return 0;
1173+}
1174+#endif /* (CONFIG_SYS_CMD_NAND) */
1175diff --git a/cpu/mips/jz_i2c.c b/cpu/mips/jz_i2c.c
1176new file mode 100644
1177index 0000000..9f3faee
1178+++ b/cpu/mips/jz_i2c.c
1179@@ -0,0 +1,234 @@
1180+/*
1181+ * This program is free software; you can redistribute it and/or modify it
1182+ * under the terms of the GNU General Public License as published by the
1183+ * Free Software Foundation; either version 2 of the License, or (at your
1184+ * option) any later version.
1185+ */
1186+
1187+
1188+#include <config.h>
1189+
1190+#if defined(CONFIG_JZ4730) || defined(CONFIG_JZ4740) || defined(CONFIG_JZ5730) || defined(CONFIG_JZ4750)
1191+
1192+#include <common.h>
1193+#include <malloc.h>
1194+#include <net.h>
1195+#include <command.h>
1196+#include <asm/io.h>
1197+#if defined(CONFIG_JZ4730)
1198+#include <asm/jz4730.h>
1199+#endif
1200+#if defined(CONFIG_JZ4740)
1201+#include <asm/jz4740.h>
1202+#endif
1203+#if defined(CONFIG_JZ5730)
1204+#include <asm/jz5730.h>
1205+#endif
1206+#if defined(CONFIG_JZ4750)
1207+#include <asm/jz4750.h>
1208+#endif
1209+
1210+
1211+/* I2C protocol */
1212+#define I2C_READ 1
1213+#define I2C_WRITE 0
1214+
1215+#define TIMEOUT 1000
1216+
1217+#define ETIMEDOUT 1
1218+
1219+
1220+static inline void my_udelay(int n )
1221+{
1222+ int i;
1223+ i=n*100;
1224+ while ( i-- )
1225+ ;
1226+}
1227+
1228+
1229+/*
1230+ * I2C bus protocol basic routines
1231+ */
1232+static int i2c_put_data(unsigned char data)
1233+{
1234+ unsigned int timeout = TIMEOUT*10;
1235+
1236+ __i2c_write(data);
1237+ __i2c_set_drf();
1238+ while (__i2c_check_drf() != 0);
1239+ while (!__i2c_transmit_ended());
1240+ while (!__i2c_received_ack() && timeout)
1241+ timeout--;
1242+
1243+ if (timeout)
1244+ return 0;
1245+ else
1246+ return -ETIMEDOUT;
1247+}
1248+
1249+static int i2c_get_data(unsigned char *data, int ack)
1250+{
1251+ int timeout = TIMEOUT*10;
1252+
1253+ if (!ack)
1254+ __i2c_send_nack();
1255+ else
1256+ __i2c_send_ack();
1257+
1258+ while (__i2c_check_drf() == 0 && timeout)
1259+ timeout--;
1260+
1261+ if (timeout) {
1262+ if (!ack)
1263+ __i2c_send_stop();
1264+ *data = __i2c_read();
1265+ __i2c_clear_drf();
1266+ return 0;
1267+ } else
1268+ return -ETIMEDOUT;
1269+}
1270+
1271+/*
1272+ * I2C interface
1273+ */
1274+void i2c_open(void)
1275+{
1276+ __i2c_set_clk(CONFIG_EXTAL, 10000); /* default 10 KHz */
1277+ __i2c_enable();
1278+}
1279+
1280+void i2c_close(void)
1281+{
1282+ my_udelay(300); /* wait for STOP goes over. */
1283+ __i2c_disable();
1284+}
1285+
1286+void i2c_setclk(unsigned int i2cclk)
1287+{
1288+ __i2c_set_clk(CONFIG_EXTAL, i2cclk);
1289+}
1290+
1291+int i2c_lseek(unsigned char device, unsigned char offset)
1292+{
1293+ __i2c_send_nack(); /* Master does not send ACK, slave sends it */
1294+ __i2c_send_start();
1295+ if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
1296+ goto device_err;
1297+ if (i2c_put_data(offset) < 0)
1298+ goto address_err;
1299+ return 0;
1300+ device_err:
1301+ printf("No I2C device (0x%02x) installed.\n", device);
1302+ __i2c_send_stop();
1303+ return -1;
1304+ address_err:
1305+ printf("No I2C device (0x%02x) response.\n", device);
1306+ __i2c_send_stop();
1307+ return -1;
1308+}
1309+
1310+int i2c_read(unsigned char device, unsigned char *buf,
1311+ unsigned char address, int count)
1312+{
1313+ int cnt = count;
1314+ int timeout = 5;
1315+
1316+L_try_again:
1317+
1318+ if (timeout < 0)
1319+ goto L_timeout;
1320+
1321+ __i2c_send_nack(); /* Master does not send ACK, slave sends it */
1322+ __i2c_send_start();
1323+ if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
1324+ goto device_werr;
1325+ if (i2c_put_data(address) < 0)
1326+ goto address_err;
1327+
1328+ __i2c_send_start();
1329+ if (i2c_put_data( (device << 1) | I2C_READ ) < 0)
1330+ goto device_rerr;
1331+ __i2c_send_ack(); /* Master sends ACK for continue reading */
1332+ while (cnt) {
1333+ if (cnt == 1) {
1334+ if (i2c_get_data(buf, 0) < 0)
1335+ break;
1336+ } else {
1337+ if (i2c_get_data(buf, 1) < 0)
1338+ break;
1339+ }
1340+ cnt--;
1341+ buf++;
1342+ }
1343+
1344+ __i2c_send_stop();
1345+ return count - cnt;
1346+ device_rerr:
1347+ device_werr:
1348+ address_err:
1349+ timeout --;
1350+ __i2c_send_stop();
1351+ goto L_try_again;
1352+
1353+L_timeout:
1354+ __i2c_send_stop();
1355+ printf("Read I2C device 0x%2x failed.\n", device);
1356+ return -1;
1357+}
1358+
1359+int i2c_write(unsigned char device, unsigned char *buf,
1360+ unsigned char address, int count)
1361+{
1362+ int cnt = count;
1363+ int cnt_in_pg;
1364+ int timeout = 5;
1365+ unsigned char *tmpbuf;
1366+ unsigned char tmpaddr;
1367+
1368+ __i2c_send_nack(); /* Master does not send ACK, slave sends it */
1369+
1370+ W_try_again:
1371+ if (timeout < 0)
1372+ goto W_timeout;
1373+
1374+ cnt = count;
1375+ tmpbuf = (unsigned char *)buf;
1376+ tmpaddr = address;
1377+
1378+ start_write_page:
1379+ cnt_in_pg = 0;
1380+ __i2c_send_start();
1381+ if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
1382+ goto device_err;
1383+ if (i2c_put_data(tmpaddr) < 0)
1384+ goto address_err;
1385+ while (cnt) {
1386+ if (++cnt_in_pg > 8) {
1387+ __i2c_send_stop();
1388+ my_udelay(1000);
1389+ tmpaddr += 8;
1390+ goto start_write_page;
1391+ }
1392+ if (i2c_put_data(*tmpbuf) < 0)
1393+ break;
1394+ cnt--;
1395+ tmpbuf++;
1396+ }
1397+ __i2c_send_stop();
1398+ return count - cnt;
1399+ device_err:
1400+ address_err:
1401+ timeout--;
1402+ __i2c_send_stop();
1403+ goto W_try_again;
1404+
1405+ W_timeout:
1406+ printf("Write I2C device 0x%2x failed.\n", device);
1407+ __i2c_send_stop();
1408+ return -1;
1409+}
1410+
1411+#endif /* CONFIG_JZ4730 || CONFIG_JZ4740 || CONFIG_JZ5730 */
1412+
1413+
1414diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c
1415new file mode 100644
1416index 0000000..ec0a518
1417+++ b/cpu/mips/jz_mmc.c
1418@@ -0,0 +1,1404 @@
1419+/*
1420+ * (C) Copyright 2003
1421+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
1422+ *
1423+ * See file CREDITS for list of people who contributed to this
1424+ * project.
1425+ *
1426+ * This program is free software; you can redistribute it and/or
1427+ * modify it under the terms of the GNU General Public License as
1428+ * published by the Free Software Foundation; either version 2 of
1429+ * the License, or (at your option) any later version.
1430+ *
1431+ * This program is distributed in the hope that it will be useful,
1432+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1433+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1434+ * GNU General Public License for more details.
1435+ *
1436+ * You should have received a copy of the GNU General Public License
1437+ * along with this program; if not, write to the Free Software
1438+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1439+ * MA 02111-1307 USA
1440+ */
1441+
1442+#include <config.h>
1443+#include <common.h>
1444+#include <part.h>
1445+
1446+#if defined CONFIG_JZ4740 || defined CONFIG_JZ4730
1447+#ifdef CONFIG_JZ4730
1448+#include <asm-mips/jz4730.h>
1449+#endif
1450+#ifdef CONFIG_JZ4740
1451+#include <asm-mips/jz4740.h>
1452+#endif
1453+
1454+#include "jz_mmc.h"
1455+
1456+#define CFG_MMC_BASE 0x80600000
1457+static int sd2_0 = 0;
1458+
1459+/*
1460+ * GPIO definition
1461+ */
1462+#define __msc_init_io() \
1463+do { \
1464+ __gpio_as_output(GPIO_SD_VCC_EN_N); \
1465+ __gpio_as_input(GPIO_SD_CD_N); \
1466+} while (0)
1467+
1468+#define __msc_enable_power() \
1469+do { \
1470+ __gpio_clear_pin(GPIO_SD_VCC_EN_N); \
1471+} while (0)
1472+
1473+#define __msc_disable_power() \
1474+do { \
1475+ __gpio_set_pin(GPIO_SD_VCC_EN_N); \
1476+} while (0)
1477+
1478+#define __msc_card_detected() \
1479+({ \
1480+ int detected = 1; \
1481+ __gpio_as_input(GPIO_SD_CD_N); \
1482+ if (!__gpio_get_pin(GPIO_SD_CD_N)) \
1483+ detected = 0; \
1484+ detected; \
1485+})
1486+
1487+/*
1488+ * Local functions
1489+ */
1490+
1491+#ifdef CONFIG_MMC
1492+extern int
1493+fat_register_device(block_dev_desc_t *dev_desc, int part_no);
1494+
1495+static block_dev_desc_t mmc_dev;
1496+
1497+block_dev_desc_t * mmc_get_dev(int dev)
1498+{
1499+ return ((block_dev_desc_t *)&mmc_dev);
1500+}
1501+
1502+/*
1503+ * FIXME needs to read cid and csd info to determine block size
1504+ * and other parameters
1505+ */
1506+static uchar mmc_buf[MMC_BLOCK_SIZE];
1507+static int mmc_ready = 0;
1508+static mmc_csd_t mmc_csd;
1509+static int use_4bit; /* Use 4-bit data bus */
1510+/*
1511+ * MMC Events
1512+ */
1513+#define MMC_EVENT_NONE 0x00 /* No events */
1514+#define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */
1515+#define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */
1516+#define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */
1517+
1518+
1519+#define MMC_IRQ_MASK() \
1520+do { \
1521+ REG_MSC_IMASK = 0xffff; \
1522+ REG_MSC_IREG = 0xffff; \
1523+} while (0)
1524+
1525+/* Stop the MMC clock and wait while it happens */
1526+static inline int jz_mmc_stop_clock(void)
1527+{
1528+ int timeout = 1000;
1529+
1530+ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
1531+
1532+ while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
1533+ timeout--;
1534+ if (timeout == 0) {
1535+ return MMC_ERROR_TIMEOUT;
1536+ }
1537+ udelay(1);
1538+ }
1539+ return MMC_NO_ERROR;
1540+}
1541+
1542+/* Start the MMC clock and operation */
1543+static inline int jz_mmc_start_clock(void)
1544+{
1545+ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
1546+ return MMC_NO_ERROR;
1547+}
1548+
1549+static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
1550+{
1551+ u32 clkrt;
1552+ u32 clk_src = is_sd ? 24000000: 16000000;
1553+
1554+ clkrt = 0;
1555+ while (rate < clk_src)
1556+ {
1557+ clkrt ++;
1558+ clk_src >>= 1;
1559+ }
1560+ return clkrt;
1561+}
1562+
1563+/* Set the MMC clock frequency */
1564+void jz_mmc_set_clock(int sd, u32 rate)
1565+{
1566+ jz_mmc_stop_clock();
1567+
1568+ /* Select clock source of MSC */
1569+ __cpm_select_msc_clk(sd);
1570+
1571+ /* Set clock dividor of MSC */
1572+ REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate);
1573+}
1574+
1575+static int jz_mmc_check_status(struct mmc_request *request)
1576+{
1577+ u32 status = REG_MSC_STAT;
1578+
1579+ /* Checking for response or data timeout */
1580+ if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) {
1581+ printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd);
1582+ return MMC_ERROR_TIMEOUT;
1583+ }
1584+
1585+ /* Checking for CRC error */
1586+ if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) {
1587+ printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status);
1588+ return MMC_ERROR_CRC;
1589+ }
1590+
1591+ return MMC_NO_ERROR;
1592+}
1593+
1594+/* Obtain response to the command and store it to response buffer */
1595+static void jz_mmc_get_response(struct mmc_request *request)
1596+{
1597+ int i;
1598+ u8 *buf;
1599+ u32 data;
1600+
1601+ DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd);
1602+
1603+ buf = request->response;
1604+ request->result = MMC_NO_ERROR;
1605+
1606+ switch (request->rtype) {
1607+ case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6:
1608+ case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5:
1609+ {
1610+ data = REG_MSC_RES;
1611+ buf[0] = (data >> 8) & 0xff;
1612+ buf[1] = data & 0xff;
1613+ data = REG_MSC_RES;
1614+ buf[2] = (data >> 8) & 0xff;
1615+ buf[3] = data & 0xff;
1616+ data = REG_MSC_RES;
1617+ buf[4] = data & 0xff;
1618+
1619+ DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n",
1620+ request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
1621+ break;
1622+ }
1623+ case RESPONSE_R2_CID: case RESPONSE_R2_CSD:
1624+ {
1625+ for (i = 0; i < 16; i += 2) {
1626+ data = REG_MSC_RES;
1627+ buf[i] = (data >> 8) & 0xff;
1628+ buf[i+1] = data & 0xff;
1629+ }
1630+ DEBUG(3, "request %d, response [", request->rtype);
1631+#if CONFIG_MMC_DEBUG_VERBOSE > 2
1632+ if (g_mmc_debug >= 3) {
1633+ int n;
1634+ for (n = 0; n < 17; n++)
1635+ printk("%02x ", buf[n]);
1636+ printk("]\n");
1637+ }
1638+#endif
1639+ break;
1640+ }
1641+ case RESPONSE_NONE:
1642+ DEBUG(3, "No response\n");
1643+ break;
1644+
1645+ default:
1646+ DEBUG(3, "unhandled response type for request %d\n", request->rtype);
1647+ break;
1648+ }
1649+}
1650+
1651+static int jz_mmc_receive_data(struct mmc_request *req)
1652+{
1653+ u32 stat, timeout, data, cnt;
1654+ u8 *buf = req->buffer;
1655+ u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
1656+
1657+ timeout = 0x3ffffff;
1658+
1659+ while (timeout) {
1660+ timeout--;
1661+ stat = REG_MSC_STAT;
1662+
1663+ if (stat & MSC_STAT_TIME_OUT_READ)
1664+ return MMC_ERROR_TIMEOUT;
1665+ else if (stat & MSC_STAT_CRC_READ_ERROR)
1666+ return MMC_ERROR_CRC;
1667+ else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
1668+ || (stat & MSC_STAT_DATA_FIFO_AFULL)) {
1669+ /* Ready to read data */
1670+ break;
1671+ }
1672+ udelay(1);
1673+ }
1674+ if (!timeout)
1675+ return MMC_ERROR_TIMEOUT;
1676+
1677+ /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
1678+ cnt = wblocklen;
1679+ while (cnt) {
1680+ data = REG_MSC_RXFIFO;
1681+ {
1682+ *buf++ = (u8)(data >> 0);
1683+ *buf++ = (u8)(data >> 8);
1684+ *buf++ = (u8)(data >> 16);
1685+ *buf++ = (u8)(data >> 24);
1686+ }
1687+ cnt --;
1688+ while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY))
1689+ ;
1690+ }
1691+ return MMC_NO_ERROR;
1692+}
1693+
1694+static int jz_mmc_transmit_data(struct mmc_request *req)
1695+{
1696+#if 0
1697+ u32 nob = req->nob;
1698+ u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
1699+ u8 *buf = req->buffer;
1700+ u32 *wbuf = (u32 *)buf;
1701+ u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */
1702+ u32 stat, timeout, data, cnt;
1703+
1704+ for (nob; nob >= 1; nob--) {
1705+ timeout = 0x3FFFFFF;
1706+
1707+ while (timeout) {
1708+ timeout--;
1709+ stat = REG_MSC_STAT;
1710+
1711+ if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS))
1712+ return MMC_ERROR_CRC;
1713+ else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) {
1714+ /* Ready to write data */
1715+ break;
1716+ }
1717+
1718+ udelay(1);
1719+ }
1720+
1721+ if (!timeout)
1722+ return MMC_ERROR_TIMEOUT;
1723+
1724+ /* Write data to TXFIFO */
1725+ cnt = wblocklen;
1726+ while (cnt) {
1727+ while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
1728+ ;
1729+
1730+ if (waligned) {
1731+ REG_MSC_TXFIFO = *wbuf++;
1732+ }
1733+ else {
1734+ data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24);
1735+ REG_MSC_TXFIFO = data;
1736+ }
1737+
1738+ cnt--;
1739+ }
1740+ }
1741+#endif
1742+ return MMC_NO_ERROR;
1743+}
1744+
1745+
1746+/*
1747+ * Name: int jz_mmc_exec_cmd()
1748+ * Function: send command to the card, and get a response
1749+ * Input: struct mmc_request *req : MMC/SD request
1750+ * Output: 0: right >0: error code
1751+ */
1752+int jz_mmc_exec_cmd(struct mmc_request *request)
1753+{
1754+ u32 cmdat = 0, events = 0;
1755+ int retval, timeout = 0x3fffff;
1756+
1757+ /* Indicate we have no result yet */
1758+ request->result = MMC_NO_RESPONSE;
1759+ if (request->cmd == MMC_CIM_RESET) {
1760+ /* On reset, 1-bit bus width */
1761+ use_4bit = 0;
1762+
1763+ /* Reset MMC/SD controller */
1764+ __msc_reset();
1765+
1766+ /* On reset, drop MMC clock down */
1767+ jz_mmc_set_clock(0, MMC_CLOCK_SLOW);
1768+
1769+ /* On reset, stop MMC clock */
1770+ jz_mmc_stop_clock();
1771+ }
1772+ if (request->cmd == MMC_SEND_OP_COND) {
1773+ DEBUG(3, "Have an MMC card\n");
1774+ /* always use 1bit for MMC */
1775+ use_4bit = 0;
1776+ }
1777+ if (request->cmd == SET_BUS_WIDTH) {
1778+ if (request->arg == 0x2) {
1779+ DEBUG(2, "Use 4-bit bus width\n");
1780+ use_4bit = 1;
1781+ }
1782+ else {
1783+ DEBUG(2, "Use 1-bit bus width\n");
1784+ use_4bit = 0;
1785+ }
1786+ }
1787+
1788+ /* stop clock */
1789+ jz_mmc_stop_clock();
1790+
1791+ /* mask all interrupts */
1792+ REG_MSC_IMASK = 0xffff;
1793+
1794+ /* clear status */
1795+ REG_MSC_IREG = 0xffff;
1796+
1797+ /* use 4-bit bus width when possible */
1798+ if (use_4bit)
1799+ cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
1800+
1801+ /* Set command type and events */
1802+ switch (request->cmd) {
1803+ /* MMC core extra command */
1804+ case MMC_CIM_RESET:
1805+ cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
1806+ break;
1807+
1808+ /* bc - broadcast - no response */
1809+ case MMC_GO_IDLE_STATE:
1810+ case MMC_SET_DSR:
1811+ break;
1812+
1813+ /* bcr - broadcast with response */
1814+ case MMC_SEND_OP_COND:
1815+ case MMC_ALL_SEND_CID:
1816+ case MMC_GO_IRQ_STATE:
1817+ break;
1818+
1819+ /* adtc - addressed with data transfer */
1820+ case MMC_READ_DAT_UNTIL_STOP:
1821+ case MMC_READ_SINGLE_BLOCK:
1822+ case MMC_READ_MULTIPLE_BLOCK:
1823+ case SEND_SCR:
1824+ cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
1825+ events = MMC_EVENT_RX_DATA_DONE;
1826+ break;
1827+
1828+ case MMC_WRITE_DAT_UNTIL_STOP:
1829+ case MMC_WRITE_BLOCK:
1830+ case MMC_WRITE_MULTIPLE_BLOCK:
1831+ case MMC_PROGRAM_CID:
1832+ case MMC_PROGRAM_CSD:
1833+ case MMC_SEND_WRITE_PROT:
1834+ case MMC_GEN_CMD:
1835+ case MMC_LOCK_UNLOCK:
1836+ cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
1837+ events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE;
1838+
1839+ break;
1840+
1841+ case MMC_STOP_TRANSMISSION:
1842+ events = MMC_EVENT_PROG_DONE;
1843+ break;
1844+
1845+ /* ac - no data transfer */
1846+ default:
1847+ break;
1848+ }
1849+
1850+ /* Set response type */
1851+ switch (request->rtype) {
1852+ case RESPONSE_NONE:
1853+ break;
1854+
1855+ case RESPONSE_R1B:
1856+ cmdat |= MSC_CMDAT_BUSY;
1857+ /*FALLTHRU*/
1858+ case RESPONSE_R1:
1859+ cmdat |= MSC_CMDAT_RESPONSE_R1;
1860+ break;
1861+ case RESPONSE_R2_CID:
1862+ case RESPONSE_R2_CSD:
1863+ cmdat |= MSC_CMDAT_RESPONSE_R2;
1864+ break;
1865+ case RESPONSE_R3:
1866+ cmdat |= MSC_CMDAT_RESPONSE_R3;
1867+ break;
1868+ case RESPONSE_R4:
1869+ cmdat |= MSC_CMDAT_RESPONSE_R4;
1870+ break;
1871+ case RESPONSE_R5:
1872+ cmdat |= MSC_CMDAT_RESPONSE_R5;
1873+ break;
1874+ case RESPONSE_R6:
1875+ cmdat |= MSC_CMDAT_RESPONSE_R6;
1876+ break;
1877+ default:
1878+ break;
1879+ }
1880+
1881+ /* Set command index */
1882+ if (request->cmd == MMC_CIM_RESET) {
1883+ REG_MSC_CMD = MMC_GO_IDLE_STATE;
1884+ } else {
1885+ REG_MSC_CMD = request->cmd;
1886+ }
1887+
1888+ /* Set argument */
1889+ REG_MSC_ARG = request->arg;
1890+
1891+ /* Set block length and nob */
1892+ if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */
1893+ REG_MSC_BLKLEN = 8;
1894+ REG_MSC_NOB = 1;
1895+ } else {
1896+ REG_MSC_BLKLEN = request->block_len;
1897+ REG_MSC_NOB = request->nob;
1898+ }
1899+
1900+ /* Set command */
1901+ REG_MSC_CMDAT = cmdat;
1902+
1903+ DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
1904+ cmdat, request->arg, request->rtype);
1905+
1906+ /* Start MMC/SD clock and send command to card */
1907+ jz_mmc_start_clock();
1908+
1909+ /* Wait for command completion */
1910+ while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES))
1911+ ;
1912+
1913+ if (timeout == 0)
1914+ return MMC_ERROR_TIMEOUT;
1915+
1916+ REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */
1917+
1918+ /* Check for status */
1919+ retval = jz_mmc_check_status(request);
1920+ if (retval) {
1921+ return retval;
1922+ }
1923+
1924+ /* Complete command with no response */
1925+ if (request->rtype == RESPONSE_NONE) {
1926+ return MMC_NO_ERROR;
1927+ }
1928+
1929+ /* Get response */
1930+ jz_mmc_get_response(request);
1931+
1932+ /* Start data operation */
1933+ if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) {
1934+ if (events & MMC_EVENT_RX_DATA_DONE) {
1935+ if (request->cmd == SEND_SCR) {
1936+ /* SD card returns SCR register as data.
1937+ MMC core expect it in the response buffer,
1938+ after normal response. */
1939+ request->buffer = (u8 *)((u32)request->response + 5);
1940+ }
1941+ jz_mmc_receive_data(request);
1942+ }
1943+
1944+ if (events & MMC_EVENT_TX_DATA_DONE) {
1945+ jz_mmc_transmit_data(request);
1946+ }
1947+
1948+ /* Wait for Data Done */
1949+ while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE))
1950+ ;
1951+ REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
1952+ }
1953+
1954+ /* Wait for Prog Done event */
1955+ if (events & MMC_EVENT_PROG_DONE) {
1956+ while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE))
1957+ ;
1958+ REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
1959+ }
1960+
1961+ /* Command completed */
1962+
1963+ return MMC_NO_ERROR; /* return successfully */
1964+}
1965+
1966+int mmc_block_read(u8 *dst, ulong src, ulong len)
1967+{
1968+
1969+ struct mmc_request request;
1970+ struct mmc_response_r1 r1;
1971+ int retval;
1972+
1973+ if (len == 0) {
1974+ return 0;
1975+ }
1976+ mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
1977+ retval = mmc_unpack_r1(&request, &r1, 0);
1978+ if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) {
1979+ return retval;
1980+ }
1981+
1982+ mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1);
1983+ if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
1984+ return retval;
1985+ }
1986+
1987+ if (sd2_0)
1988+ src /= len;
1989+
1990+ mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst);
1991+ if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
1992+ return retval;
1993+ }
1994+ return retval;
1995+}
1996+
1997+int mmc_block_write(ulong dst, uchar *src, int len)
1998+{
1999+ return 0;
2000+}
2001+
2002+int mmc_read(ulong src, uchar *dst, int size)
2003+{
2004+ ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
2005+ ulong mmc_block_size, mmc_block_address;
2006+
2007+ if (size == 0) {
2008+ return 0;
2009+ }
2010+
2011+ if (!mmc_ready) {
2012+ printf("MMC card is not ready\n");
2013+ return -1;
2014+ }
2015+
2016+ mmc_block_size = MMC_BLOCK_SIZE;
2017+ mmc_block_address = ~(mmc_block_size - 1);
2018+
2019+ src -= CFG_MMC_BASE;
2020+ end = src + size;
2021+ part_start = ~mmc_block_address & src;
2022+ part_end = ~mmc_block_address & end;
2023+ aligned_start = mmc_block_address & src;
2024+ aligned_end = mmc_block_address & end;
2025+ /* all block aligned accesses */
2026+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2027+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2028+ if (part_start) {
2029+ part_len = mmc_block_size - part_start;
2030+ debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2031+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2032+ if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
2033+ return -1;
2034+ }
2035+ memcpy(dst, mmc_buf+part_start, part_len);
2036+ dst += part_len;
2037+ src += part_len;
2038+ }
2039+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2040+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2041+ for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
2042+ debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2043+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2044+
2045+ if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
2046+ return -1;
2047+ }
2048+ }
2049+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2050+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2051+
2052+ if (part_end && src < end) {
2053+ if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
2054+ return -1;
2055+ }
2056+ memcpy(dst, mmc_buf, part_end);
2057+ }
2058+ return 0;
2059+
2060+}
2061+
2062+int mmc_write(uchar *src, ulong dst, int size)
2063+{
2064+ ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
2065+ ulong mmc_block_size, mmc_block_address;
2066+
2067+ if (size == 0) {
2068+ return 0;
2069+ }
2070+
2071+ if (!mmc_ready) {
2072+ printf("MMC card is not ready\n");
2073+ return -1;
2074+ }
2075+
2076+ mmc_block_size = MMC_BLOCK_SIZE;
2077+ mmc_block_address = ~(mmc_block_size - 1);
2078+
2079+ dst -= CFG_MMC_BASE;
2080+ end = dst + size;
2081+ part_start = ~mmc_block_address & dst;
2082+ part_end = ~mmc_block_address & end;
2083+ aligned_start = mmc_block_address & dst;
2084+ aligned_end = mmc_block_address & end;
2085+
2086+ /* all block aligned accesses */
2087+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2088+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2089+ if (part_start) {
2090+ part_len = mmc_block_size - part_start;
2091+ debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2092+ (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
2093+ if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
2094+ return -1;
2095+ }
2096+ memcpy(mmc_buf+part_start, src, part_len);
2097+ if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
2098+ return -1;
2099+ }
2100+ dst += part_len;
2101+ src += part_len;
2102+ }
2103+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2104+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2105+ for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
2106+ debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2107+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2108+ if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
2109+ return -1;
2110+ }
2111+ }
2112+ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2113+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2114+ if (part_end && dst < end) {
2115+ debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
2116+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
2117+ if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
2118+ return -1;
2119+ }
2120+ memcpy(mmc_buf, src, part_end);
2121+ if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
2122+ return -1;
2123+ }
2124+ }
2125+ return 0;
2126+}
2127+
2128+ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
2129+{
2130+ ulong src;
2131+ int mmc_block_size = MMC_BLOCK_SIZE;
2132+
2133+ src = blknr * mmc_block_size + CFG_MMC_BASE;
2134+ mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
2135+ return blkcnt;
2136+}
2137+
2138+int mmc_select_card(void)
2139+{
2140+ struct mmc_request request;
2141+ struct mmc_response_r1 r1;
2142+ int retval;
2143+
2144+ mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
2145+ retval = mmc_unpack_r1(&request, &r1, 0);
2146+ if (retval) {
2147+ return retval;
2148+ }
2149+
2150+ if (mmcinfo.sd) {
2151+ mmc_simple_cmd(&request, MMC_APP_CMD, mmcinfo.rca, RESPONSE_R1);
2152+ retval = mmc_unpack_r1(&request,&r1,0);
2153+ if (retval) {
2154+ return retval;
2155+ }
2156+ mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1);
2157+ retval = mmc_unpack_r1(&request,&r1,0);
2158+ if (retval) {
2159+ return retval;
2160+ }
2161+ }
2162+ return 0;
2163+}
2164+
2165+/*
2166+ * Configure card
2167+ */
2168+static void mmc_configure_card(void)
2169+{
2170+ u32 rate;
2171+
2172+ /* Get card info */
2173+ if (sd2_0)
2174+ mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10;
2175+ else
2176+ mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2));
2177+
2178+ mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len;
2179+
2180+ /* Fix the clock rate */
2181+ rate = mmc_tran_speed(mmcinfo.csd.tran_speed);
2182+ if (rate < MMC_CLOCK_SLOW)
2183+ rate = MMC_CLOCK_SLOW;
2184+ if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST))
2185+ rate = MMC_CLOCK_FAST;
2186+ if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST))
2187+ rate = SD_CLOCK_FAST;
2188+
2189+ DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate);
2190+
2191+ jz_mmc_set_clock(mmcinfo.sd, rate);
2192+}
2193+
2194+/*
2195+ * State machine routines to initialize card(s)
2196+ */
2197+
2198+/*
2199+ CIM_SINGLE_CARD_ACQ (frequency at 400 kHz)
2200+ --- Must enter from GO_IDLE_STATE ---
2201+ 1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41]
2202+ 2. SEND_OP_COND (Full Range) [CMD1] {optional}
2203+ 3. SEND_OP_COND (Set Range ) [CMD1]
2204+ If busy, delay and repeat step 2
2205+ 4. ALL_SEND_CID [CMD2]
2206+ If timeout, set an error (no cards found)
2207+ 5. SET_RELATIVE_ADDR [CMD3]
2208+ 6. SEND_CSD [CMD9]
2209+ 7. SET_DSR [CMD4] Only call this if (csd.dsr_imp).
2210+ 8. Set clock frequency (check available in csd.tran_speed)
2211+ */
2212+
2213+#define MMC_INIT_DOING 0
2214+#define MMC_INIT_PASSED 1
2215+#define MMC_INIT_FAILED 2
2216+
2217+static int mmc_init_card_state(struct mmc_request *request)
2218+{
2219+ struct mmc_response_r1 r1;
2220+ struct mmc_response_r3 r3;
2221+ int retval;
2222+ int ocr = 0x40300000;
2223+ int limit_41 = 0;
2224+
2225+ DEBUG(2,"mmc_init_card_state\n");
2226+
2227+ switch (request->cmd) {
2228+ case MMC_GO_IDLE_STATE: /* No response to parse */
2229+ if (mmcinfo.sd)
2230+ mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1);
2231+ else
2232+ mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
2233+ break;
2234+
2235+ case 8:
2236+ retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
2237+ mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
2238+ break;
2239+
2240+ case MMC_APP_CMD:
2241+ retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
2242+ if (retval & (limit_41 < 100)) {
2243+ DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n",
2244+ retval, mmc_result_to_string(retval));
2245+ limit_41++;
2246+ mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
2247+ } else if (limit_41 < 100) {
2248+ limit_41++;
2249+ mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
2250+ } else{
2251+ /* reset the card to idle*/
2252+ mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
2253+ mmcinfo.sd = 0;
2254+ }
2255+ break;
2256+
2257+ case SD_SEND_OP_COND:
2258+ retval = mmc_unpack_r3(request, &r3);
2259+ if (retval) {
2260+ /* Try MMC card */
2261+ mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
2262+ break;
2263+ }
2264+
2265+ DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
2266+
2267+ if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){
2268+ udelay(10000);
2269+ mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
2270+ }
2271+ else {
2272+ /* Set the data bus width to 4 bits */
2273+ mmcinfo.sd = 1; /* SD Card ready */
2274+ mmcinfo.state = CARD_STATE_READY;
2275+ mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
2276+ }
2277+ break;
2278+
2279+ case MMC_SEND_OP_COND:
2280+ retval = mmc_unpack_r3(request, &r3);
2281+ if (retval) {
2282+ DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n",
2283+ retval, mmc_result_to_string(retval));
2284+ return MMC_INIT_FAILED;
2285+ }
2286+
2287+ DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
2288+ if (!(r3.ocr & MMC_CARD_BUSY)) {
2289+ mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
2290+ }
2291+ else {
2292+ mmcinfo.sd = 0; /* MMC Card ready */
2293+ mmcinfo.state = CARD_STATE_READY;
2294+ mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
2295+ }
2296+ break;
2297+
2298+ case MMC_ALL_SEND_CID:
2299+ retval = mmc_unpack_cid( request, &mmcinfo.cid );
2300+ mmc_dev.if_type = IF_TYPE_MMC;
2301+ mmc_dev.part_type = PART_TYPE_DOS;
2302+ mmc_dev.dev = 0;
2303+ mmc_dev.lun = 0;
2304+ mmc_dev.type = 0;
2305+ /* FIXME fill in the correct size (is set to 32MByte) */
2306+ mmc_dev.blksz = 512;
2307+ mmc_dev.lba = 0x10000;
2308+ mmc_dev.removable = 0;
2309+
2310+ /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
2311+ if ( retval && (retval != MMC_ERROR_CRC)) {
2312+ DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n",
2313+ retval, mmc_result_to_string(retval));
2314+ return MMC_INIT_FAILED;
2315+ }
2316+ mmcinfo.state = CARD_STATE_IDENT;
2317+ if(mmcinfo.sd)
2318+ mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
2319+ else
2320+ mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
2321+ break;
2322+
2323+ case MMC_SET_RELATIVE_ADDR:
2324+ if (mmcinfo.sd) {
2325+ retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca);
2326+ mmcinfo.rca = mmcinfo.rca << 16;
2327+ DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status);
2328+ } else {
2329+ retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
2330+ mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16;
2331+ }
2332+ if (retval) {
2333+ DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n",
2334+ retval, mmc_result_to_string(retval));
2335+ return MMC_INIT_FAILED;
2336+ }
2337+
2338+ mmcinfo.state = CARD_STATE_STBY;
2339+ mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
2340+
2341+ break;
2342+
2343+ case MMC_SEND_CSD:
2344+ retval = mmc_unpack_csd(request, &mmcinfo.csd);
2345+ mmc_csd_t *csd = (mmc_csd_t *)retval;
2346+ memcpy(&mmc_csd, csd, sizeof(csd));
2347+ mmc_ready = 1;
2348+
2349+ printf("MMC card is ready\n");
2350+ /* FIXME add verbose printout for csd */
2351+
2352+ /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
2353+ if (retval && (retval != MMC_ERROR_CRC)) {
2354+ DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n",
2355+ retval, mmc_result_to_string(retval));
2356+ return MMC_INIT_FAILED;
2357+ }
2358+ if (mmcinfo.csd.dsr_imp) {
2359+ DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n");
2360+ }
2361+ mmc_configure_card();
2362+ return MMC_INIT_PASSED;
2363+
2364+ default:
2365+ DEBUG(0, "mmc_init_card_state: error! Illegal last cmd %d\n", request->cmd);
2366+ return MMC_INIT_FAILED;
2367+ }
2368+
2369+ return MMC_INIT_DOING;
2370+}
2371+
2372+int mmc_init_card(void)
2373+{
2374+ struct mmc_request request;
2375+ int retval;
2376+
2377+ mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */
2378+ mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
2379+ mmcinfo.sd = 1; /* assuming a SD card */
2380+
2381+ while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING)
2382+ ;
2383+
2384+ if (retval == MMC_INIT_PASSED)
2385+ return MMC_NO_ERROR;
2386+ else
2387+ return MMC_NO_RESPONSE;
2388+}
2389+
2390+int mmc_legacy_init(int verbose)
2391+{
2392+ if (!__msc_card_detected())
2393+ return 1;
2394+
2395+ printf("MMC card found\n");
2396+
2397+ /* Step-1: init GPIO */
2398+ __gpio_as_msc();
2399+
2400+ __msc_init_io();
2401+
2402+ /* Step-2: turn on power of card */
2403+ __msc_enable_power();
2404+
2405+ /* Step-3: Reset MSC Controller. */
2406+ __msc_reset();
2407+
2408+ /* Step-3: mask all IRQs. */
2409+ MMC_IRQ_MASK();
2410+
2411+ /* Step-4: stop MMC/SD clock */
2412+ jz_mmc_stop_clock();
2413+ mmc_init_card();
2414+ mmc_select_card();
2415+
2416+ mmc_dev.block_read = mmc_bread;
2417+ fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
2418+
2419+ return 0;
2420+}
2421+
2422+int mmc_ident(block_dev_desc_t *dev)
2423+{
2424+ return 0;
2425+}
2426+
2427+int mmc2info(ulong addr)
2428+{
2429+ /* FIXME hard codes to 32 MB device */
2430+ if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
2431+ return 1;
2432+ }
2433+ return 0;
2434+}
2435+/*
2436+ * Debugging functions
2437+ */
2438+
2439+static char * mmc_result_strings[] = {
2440+ "NO_RESPONSE",
2441+ "NO_ERROR",
2442+ "ERROR_OUT_OF_RANGE",
2443+ "ERROR_ADDRESS",
2444+ "ERROR_BLOCK_LEN",
2445+ "ERROR_ERASE_SEQ",
2446+ "ERROR_ERASE_PARAM",
2447+ "ERROR_WP_VIOLATION",
2448+ "ERROR_CARD_IS_LOCKED",
2449+ "ERROR_LOCK_UNLOCK_FAILED",
2450+ "ERROR_COM_CRC",
2451+ "ERROR_ILLEGAL_COMMAND",
2452+ "ERROR_CARD_ECC_FAILED",
2453+ "ERROR_CC",
2454+ "ERROR_GENERAL",
2455+ "ERROR_UNDERRUN",
2456+ "ERROR_OVERRUN",
2457+ "ERROR_CID_CSD_OVERWRITE",
2458+ "ERROR_STATE_MISMATCH",
2459+ "ERROR_HEADER_MISMATCH",
2460+ "ERROR_TIMEOUT",
2461+ "ERROR_CRC",
2462+ "ERROR_DRIVER_FAILURE",
2463+};
2464+
2465+char * mmc_result_to_string(int i)
2466+{
2467+ return mmc_result_strings[i+1];
2468+}
2469+
2470+static char * card_state_strings[] = {
2471+ "empty",
2472+ "idle",
2473+ "ready",
2474+ "ident",
2475+ "stby",
2476+ "tran",
2477+ "data",
2478+ "rcv",
2479+ "prg",
2480+ "dis",
2481+};
2482+
2483+static inline char * card_state_to_string(int i)
2484+{
2485+ return card_state_strings[i+1];
2486+}
2487+
2488+/*
2489+ * Utility functions
2490+ */
2491+
2492+#define PARSE_U32(_buf,_index) \
2493+ (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \
2494+ (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]);
2495+
2496+#define PARSE_U16(_buf,_index) \
2497+ (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]);
2498+
2499+int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
2500+{
2501+ u8 *buf = request->response;
2502+ int num = 0;
2503+
2504+ if (request->result)
2505+ return request->result;
2506+
2507+ csd->csd_structure = (buf[1] & 0xc0) >> 6;
2508+ if (csd->csd_structure)
2509+ sd2_0 = 1;
2510+ else
2511+ sd2_0 = 0;
2512+
2513+ switch (csd->csd_structure) {
2514+ case 0 :
2515+ csd->taac = buf[2];
2516+ csd->nsac = buf[3];
2517+ csd->tran_speed = buf[4];
2518+ csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
2519+ csd->read_bl_len = buf[6] & 0x0f;
2520+ /* for support 2GB card*/
2521+ if (csd->read_bl_len >= 10)
2522+ {
2523+ num = csd->read_bl_len - 9;
2524+ csd->read_bl_len = 9;
2525+ }
2526+
2527+ csd->read_bl_partial = (buf[7] & 0x80) ? 1 : 0;
2528+ csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0;
2529+ csd->read_blk_misalign = (buf[7] & 0x20) ? 1 : 0;
2530+ csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0;
2531+ csd->c_size = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6;
2532+
2533+ if (num)
2534+ csd->c_size = csd->c_size << num;
2535+
2536+
2537+ csd->vdd_r_curr_min = (buf[9] & 0x38) >> 3;
2538+ csd->vdd_r_curr_max = buf[9] & 0x07;
2539+ csd->vdd_w_curr_min = (buf[10] & 0xe0) >> 5;
2540+ csd->vdd_w_curr_max = (buf[10] & 0x1c) >> 2;
2541+ csd->c_size_mult = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7);
2542+ switch (csd->csd_structure) {
2543+ case CSD_STRUCT_VER_1_0:
2544+ case CSD_STRUCT_VER_1_1:
2545+ csd->erase.v22.sector_size = (buf[11] & 0x7c) >> 2;
2546+ csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
2547+
2548+ break;
2549+ case CSD_STRUCT_VER_1_2:
2550+ default:
2551+ csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2;
2552+ csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
2553+ break;
2554+ }
2555+ csd->wp_grp_size = buf[12] & 0x1f;
2556+ csd->wp_grp_enable = (buf[13] & 0x80) ? 1 : 0;
2557+ csd->default_ecc = (buf[13] & 0x60) >> 5;
2558+ csd->r2w_factor = (buf[13] & 0x1c) >> 2;
2559+ csd->write_bl_len = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6);
2560+ if (csd->write_bl_len >= 10)
2561+ csd->write_bl_len = 9;
2562+
2563+ csd->write_bl_partial = (buf[14] & 0x20) ? 1 : 0;
2564+ csd->file_format_grp = (buf[15] & 0x80) ? 1 : 0;
2565+ csd->copy = (buf[15] & 0x40) ? 1 : 0;
2566+ csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
2567+ csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
2568+ csd->file_format = (buf[15] & 0x0c) >> 2;
2569+ csd->ecc = buf[15] & 0x03;
2570+
2571+ DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
2572+ " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
2573+ " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
2574+ " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
2575+ " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
2576+ " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
2577+ " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
2578+ csd->csd_structure, csd->spec_vers,
2579+ csd->taac, csd->nsac, csd->tran_speed,
2580+ csd->ccc, csd->read_bl_len,
2581+ csd->read_bl_partial, csd->write_blk_misalign,
2582+ csd->read_blk_misalign, csd->dsr_imp,
2583+ csd->c_size, csd->vdd_r_curr_min,
2584+ csd->vdd_r_curr_max, csd->vdd_w_curr_min,
2585+ csd->vdd_w_curr_max, csd->c_size_mult,
2586+ csd->wp_grp_size, csd->wp_grp_enable,
2587+ csd->default_ecc, csd->r2w_factor,
2588+ csd->write_bl_len, csd->write_bl_partial,
2589+ csd->file_format_grp, csd->copy,
2590+ csd->perm_write_protect, csd->tmp_write_protect,
2591+ csd->file_format, csd->ecc);
2592+ switch (csd->csd_structure) {
2593+ case CSD_STRUCT_VER_1_0:
2594+ case CSD_STRUCT_VER_1_1:
2595+ DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
2596+ csd->erase.v22.sector_size,
2597+ csd->erase.v22.erase_grp_size);
2598+ break;
2599+ case CSD_STRUCT_VER_1_2:
2600+ default:
2601+ DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
2602+ csd->erase.v31.erase_grp_size,
2603+ csd->erase.v31.erase_grp_mult);
2604+ break;
2605+
2606+ }
2607+ break;
2608+
2609+ case 1 :
2610+ csd->taac = 0;
2611+ csd->nsac = 0;
2612+ csd->tran_speed = buf[4];
2613+ csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
2614+
2615+ csd->read_bl_len = 9;
2616+ csd->read_bl_partial = 0;
2617+ csd->write_blk_misalign = 0;
2618+ csd->read_blk_misalign = 0;
2619+ csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0;
2620+ csd->c_size = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ;
2621+ switch (csd->csd_structure) {
2622+ case CSD_STRUCT_VER_1_0:
2623+ case CSD_STRUCT_VER_1_1:
2624+ csd->erase.v22.sector_size = 0x7f;
2625+ csd->erase.v22.erase_grp_size = 0;
2626+ break;
2627+ case CSD_STRUCT_VER_1_2:
2628+ default:
2629+ csd->erase.v31.erase_grp_size = 0x7f;
2630+ csd->erase.v31.erase_grp_mult = 0;
2631+ break;
2632+ }
2633+ csd->wp_grp_size = 0;
2634+ csd->wp_grp_enable = 0;
2635+ csd->default_ecc = (buf[13] & 0x60) >> 5;
2636+ csd->r2w_factor = 4;/* Unused */
2637+ csd->write_bl_len = 9;
2638+
2639+ csd->write_bl_partial = 0;
2640+ csd->file_format_grp = 0;
2641+ csd->copy = (buf[15] & 0x40) ? 1 : 0;
2642+ csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
2643+ csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
2644+ csd->file_format = 0;
2645+ csd->ecc = buf[15] & 0x03;
2646+
2647+ DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
2648+ " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
2649+ " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
2650+ " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
2651+ " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
2652+ " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
2653+ " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
2654+ csd->csd_structure, csd->spec_vers,
2655+ csd->taac, csd->nsac, csd->tran_speed,
2656+ csd->ccc, csd->read_bl_len,
2657+ csd->read_bl_partial, csd->write_blk_misalign,
2658+ csd->read_blk_misalign, csd->dsr_imp,
2659+ csd->c_size, csd->vdd_r_curr_min,
2660+ csd->vdd_r_curr_max, csd->vdd_w_curr_min,
2661+ csd->vdd_w_curr_max, csd->c_size_mult,
2662+ csd->wp_grp_size, csd->wp_grp_enable,
2663+ csd->default_ecc, csd->r2w_factor,
2664+ csd->write_bl_len, csd->write_bl_partial,
2665+ csd->file_format_grp, csd->copy,
2666+ csd->perm_write_protect, csd->tmp_write_protect,
2667+ csd->file_format, csd->ecc);
2668+ switch (csd->csd_structure) {
2669+ case CSD_STRUCT_VER_1_0:
2670+ case CSD_STRUCT_VER_1_1:
2671+ DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
2672+ csd->erase.v22.sector_size,
2673+ csd->erase.v22.erase_grp_size);
2674+ break;
2675+ case CSD_STRUCT_VER_1_2:
2676+ default:
2677+ DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
2678+ csd->erase.v31.erase_grp_size,
2679+ csd->erase.v31.erase_grp_mult);
2680+ break;
2681+ }
2682+ }
2683+
2684+ if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
2685+
2686+ return 0;
2687+}
2688+
2689+int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state)
2690+{
2691+ u8 *buf = request->response;
2692+
2693+ if (request->result) return request->result;
2694+
2695+ r1->cmd = buf[0];
2696+ r1->status = PARSE_U32(buf,1);
2697+
2698+ DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
2699+
2700+ if (R1_STATUS(r1->status)) {
2701+ if (r1->status & R1_OUT_OF_RANGE) return MMC_ERROR_OUT_OF_RANGE;
2702+ if (r1->status & R1_ADDRESS_ERROR) return MMC_ERROR_ADDRESS;
2703+ if (r1->status & R1_BLOCK_LEN_ERROR) return MMC_ERROR_BLOCK_LEN;
2704+ if (r1->status & R1_ERASE_SEQ_ERROR) return MMC_ERROR_ERASE_SEQ;
2705+ if (r1->status & R1_ERASE_PARAM) return MMC_ERROR_ERASE_PARAM;
2706+ if (r1->status & R1_WP_VIOLATION) return MMC_ERROR_WP_VIOLATION;
2707+ /*if (r1->status & R1_CARD_IS_LOCKED) return MMC_ERROR_CARD_IS_LOCKED; */
2708+ if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED;
2709+ if (r1->status & R1_COM_CRC_ERROR) return MMC_ERROR_COM_CRC;
2710+ if (r1->status & R1_ILLEGAL_COMMAND) return MMC_ERROR_ILLEGAL_COMMAND;
2711+ if (r1->status & R1_CARD_ECC_FAILED) return MMC_ERROR_CARD_ECC_FAILED;
2712+ if (r1->status & R1_CC_ERROR) return MMC_ERROR_CC;
2713+ if (r1->status & R1_ERROR) return MMC_ERROR_GENERAL;
2714+ if (r1->status & R1_UNDERRUN) return MMC_ERROR_UNDERRUN;
2715+ if (r1->status & R1_OVERRUN) return MMC_ERROR_OVERRUN;
2716+ if (r1->status & R1_CID_CSD_OVERWRITE) return MMC_ERROR_CID_CSD_OVERWRITE;
2717+ }
2718+
2719+ if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH;
2720+
2721+ /* This should be last - it's the least dangerous error */
2722+
2723+ return 0;
2724+}
2725+
2726+int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr)
2727+{
2728+ u8 *buf = request->response;
2729+ if (request->result) return request->result;
2730+
2731+ *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
2732+ return mmc_unpack_r1(request, r1, state);
2733+
2734+}
2735+
2736+int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca)
2737+{
2738+ u8 *buf = request->response;
2739+
2740+ if (request->result) return request->result;
2741+
2742+ *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */
2743+
2744+ *(buf+1) = 0;
2745+ *(buf+2) = 0;
2746+
2747+ return mmc_unpack_r1(request, r1, state);
2748+}
2749+
2750+int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid)
2751+{
2752+ u8 *buf = request->response;
2753+ int i;
2754+
2755+ if (request->result) return request->result;
2756+
2757+ cid->mid = buf[1];
2758+ cid->oid = PARSE_U16(buf,2);
2759+ for (i = 0 ; i < 6 ; i++)
2760+ cid->pnm[i] = buf[4+i];
2761+ cid->pnm[6] = 0;
2762+ cid->prv = buf[10];
2763+ cid->psn = PARSE_U32(buf,11);
2764+ cid->mdt = buf[15];
2765+
2766+ DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n",
2767+ cid->mid, cid->oid, cid->pnm,
2768+ (cid->prv>>4), (cid->prv&0xf),
2769+ cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997);
2770+
2771+ if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
2772+ return 0;
2773+}
2774+
2775+int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3)
2776+{
2777+ u8 *buf = request->response;
2778+
2779+ if (request->result) return request->result;
2780+
2781+ r3->ocr = PARSE_U32(buf,1);
2782+ DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr);
2783+
2784+ if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
2785+ return 0;
2786+}
2787+
2788+#define KBPS 1
2789+#define MBPS 1000
2790+
2791+static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 };
2792+static u32 ts_mul[] = { 0, 1000, 1200, 1300, 1500, 2000, 2500, 3000,
2793+ 3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 };
2794+
2795+u32 mmc_tran_speed(u8 ts)
2796+{
2797+ u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3];
2798+
2799+ if (rate <= 0) {
2800+ DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts);
2801+ return 1;
2802+ }
2803+
2804+ return rate;
2805+}
2806+
2807+void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
2808+ u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer)
2809+{
2810+ request->cmd = cmd;
2811+ request->arg = arg;
2812+ request->rtype = rtype;
2813+ request->nob = nob;
2814+ request->block_len = block_len;
2815+ request->buffer = buffer;
2816+ request->cnt = nob * block_len;
2817+
2818+ jz_mmc_exec_cmd(request);
2819+}
2820+
2821+#endif /* CONFIG_MMC */
2822+#endif /* CONFIG_JZ4740 & CONFIG_JZ4730 */
2823diff --git a/cpu/mips/jz_mmc.h b/cpu/mips/jz_mmc.h
2824new file mode 100644
2825index 0000000..7f0fa1f
2826+++ b/cpu/mips/jz_mmc.h
2827@@ -0,0 +1,113 @@
2828+/*
2829+ * linux/drivers/mmc/jz_mmc.h
2830+ *
2831+ * Author: Vladimir Shebordaev, Igor Oblakov
2832+ * Copyright: MontaVista Software Inc.
2833+ *
2834+ * $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $
2835+ *
2836+ * This program is free software; you can redistribute it and/or modify
2837+ * it under the terms of the GNU General Public License version 2 as
2838+ * published by the Free Software Foundation.
2839+ */
2840+#ifndef __MMC_JZMMC_H__
2841+#define __MMC_JZMMC_H__
2842+
2843+#include "mmc_protocol.h"
2844+
2845+#define MMC_DEBUG_LEVEL 0 /* Enable Debug: 0 - no debug */
2846+
2847+#define MMC_BLOCK_SIZE 512 /* MMC/SD Block Size */
2848+
2849+#define ID_TO_RCA(x) ((x)+1)
2850+
2851+#define MMC_OCR_ARG 0x00ff8000 /* Argument of OCR */
2852+
2853+enum mmc_result_t {
2854+ MMC_NO_RESPONSE = -1,
2855+ MMC_NO_ERROR = 0,
2856+ MMC_ERROR_OUT_OF_RANGE,
2857+ MMC_ERROR_ADDRESS,
2858+ MMC_ERROR_BLOCK_LEN,
2859+ MMC_ERROR_ERASE_SEQ,
2860+ MMC_ERROR_ERASE_PARAM,
2861+ MMC_ERROR_WP_VIOLATION,
2862+ MMC_ERROR_CARD_IS_LOCKED,
2863+ MMC_ERROR_LOCK_UNLOCK_FAILED,
2864+ MMC_ERROR_COM_CRC,
2865+ MMC_ERROR_ILLEGAL_COMMAND,
2866+ MMC_ERROR_CARD_ECC_FAILED,
2867+ MMC_ERROR_CC,
2868+ MMC_ERROR_GENERAL,
2869+ MMC_ERROR_UNDERRUN,
2870+ MMC_ERROR_OVERRUN,
2871+ MMC_ERROR_CID_CSD_OVERWRITE,
2872+ MMC_ERROR_STATE_MISMATCH,
2873+ MMC_ERROR_HEADER_MISMATCH,
2874+ MMC_ERROR_TIMEOUT,
2875+ MMC_ERROR_CRC,
2876+ MMC_ERROR_DRIVER_FAILURE,
2877+};
2878+
2879+/* the information structure of MMC/SD Card */
2880+typedef struct MMC_INFO
2881+{
2882+ int id; /* Card index */
2883+ int sd; /* MMC or SD card */
2884+ int rca; /* RCA */
2885+ u32 scr; /* SCR 63:32*/
2886+ int flags; /* Ejected, inserted */
2887+ enum card_state state; /* empty, ident, ready, whatever */
2888+
2889+ /* Card specific information */
2890+ struct mmc_cid cid;
2891+ struct mmc_csd csd;
2892+ u32 block_num;
2893+ u32 block_len;
2894+ u32 erase_unit;
2895+} mmc_info;
2896+
2897+mmc_info mmcinfo;
2898+
2899+struct mmc_request {
2900+ int index; /* Slot index - used for CS lines */
2901+ int cmd; /* Command to send */
2902+ u32 arg; /* Argument to send */
2903+ enum mmc_rsp_t rtype; /* Response type expected */
2904+
2905+ /* Data transfer (these may be modified at the low level) */
2906+ u16 nob; /* Number of blocks to transfer*/
2907+ u16 block_len; /* Block length */
2908+ u8 *buffer; /* Data buffer */
2909+ u32 cnt; /* Data length, for PIO */
2910+
2911+ /* Results */
2912+ u8 response[18]; /* Buffer to store response - CRC is optional */
2913+ enum mmc_result_t result;
2914+};
2915+
2916+char * mmc_result_to_string(int);
2917+int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd);
2918+int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state);
2919+int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca);
2920+int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr);
2921+int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid);
2922+int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3);
2923+
2924+void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
2925+ u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer);
2926+u32 mmc_tran_speed(u8 ts);
2927+void jz_mmc_set_clock(int sd, u32 rate);
2928+void jz_mmc_hardware_init(void);
2929+
2930+static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype)
2931+{
2932+ mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0);
2933+}
2934+
2935+int mmc_legacy_init(int verbose);
2936+int mmc_read(ulong src, uchar *dst, int size);
2937+int mmc_write(uchar *src, ulong dst, int size);
2938+int mmc2info(ulong addr);
2939+
2940+#endif /* __MMC_JZMMC_H__ */
2941diff --git a/cpu/mips/jz_serial.c b/cpu/mips/jz_serial.c
2942new file mode 100644
2943index 0000000..1f06f32
2944+++ b/cpu/mips/jz_serial.c
2945@@ -0,0 +1,159 @@
2946+/*
2947+ * Jz47xx UART support
2948+ *
2949+ * Hardcoded to UART 0 for now
2950+ * Options also hardcoded to 8N1
2951+ *
2952+ * Copyright (c) 2005
2953+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
2954+ *
2955+ * This program is free software; you can redistribute it and/or
2956+ * modify it under the terms of the GNU General Public License as
2957+ * published by the Free Software Foundation; either version 2 of
2958+ * the License, or (at your option) any later version.
2959+ *
2960+ * This program is distributed in the hope that it will be useful,
2961+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2962+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2963+ * GNU General Public License for more details.
2964+ *
2965+ * You should have received a copy of the GNU General Public License
2966+ * along with this program; if not, write to the Free Software
2967+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2968+ * MA 02111-1307 USA
2969+ */
2970+
2971+#include <config.h>
2972+#include <common.h>
2973+
2974+#if defined(CONFIG_JZ4730)
2975+#include <asm/jz4730.h>
2976+#endif
2977+#if defined(CONFIG_JZ4740)
2978+#include <asm/jz4740.h>
2979+#endif
2980+#if defined(CONFIG_JZ4750)
2981+#include <asm/jz4750.h>
2982+#endif
2983+#if defined(CONFIG_JZ4750D)
2984+#include <asm/jz4750d.h>
2985+#endif
2986+#if defined(CONFIG_JZ5730)
2987+#include <asm/jz5730.h>
2988+#endif
2989+
2990+#undef UART_BASE
2991+#ifndef CONFIG_SYS_UART_BASE
2992+#define UART_BASE UART0_BASE
2993+#else
2994+#define UART_BASE CONFIG_SYS_UART_BASE
2995+#endif
2996+
2997+/*
2998+ * serial_init - initialize a channel
2999+ *
3000+ * This routine initializes the number of data bits, parity
3001+ * and set the selected baud rate. Interrupts are disabled.
3002+ * Set the modem control signals if the option is selected.
3003+ *
3004+ * RETURNS: N/A
3005+ */
3006+int serial_init (void)
3007+{
3008+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3009+ volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
3010+ volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
3011+ volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
3012+ volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
3013+
3014+ /* Disable port interrupts while changing hardware */
3015+ *uart_ier = 0;
3016+
3017+ /* Disable UART unit function */
3018+ *uart_fcr = ~UART_FCR_UUE;
3019+
3020+ /* Set both receiver and transmitter in UART mode (not SIR) */
3021+ *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
3022+
3023+ /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
3024+ *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
3025+
3026+ /* Set baud rate */
3027+ serial_setbrg();
3028+
3029+ /* Enable UART unit, enable and clear FIFO */
3030+ *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
3031+#endif
3032+ return 0;
3033+}
3034+
3035+void serial_setbrg (void)
3036+{
3037+ volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
3038+ volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
3039+ volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
3040+ u32 baud_div, tmp;
3041+
3042+#if defined(CONFIG_FPGA)
3043+ baud_div = (CONFIG_EXTAL / CFG_DIV) / 16 / CONFIG_BAUDRATE;
3044+#elif defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D)
3045+ if (CONFIG_EXTAL > 16000000) {
3046+ REG_CPM_CPCCR |= CPM_CPCCR_ECS;
3047+ baud_div = CONFIG_EXTAL / 32 / CONFIG_BAUDRATE;
3048+ } else {
3049+ REG_CPM_CPCCR &= ~CPM_CPCCR_ECS;
3050+ baud_div = CONFIG_EXTAL / 16 / CONFIG_BAUDRATE;
3051+ }
3052+#else /* CONFIG_JZ4740 | CONFIG_JZ4730 */
3053+ baud_div = CONFIG_EXTAL / 16 / CONFIG_BAUDRATE;
3054+#endif
3055+ tmp = *uart_lcr;
3056+ tmp |= UART_LCR_DLAB;
3057+ *uart_lcr = tmp;
3058+
3059+ *uart_dlhr = (baud_div >> 8) & 0xff;
3060+ *uart_dllr = baud_div & 0xff;
3061+
3062+ tmp &= ~UART_LCR_DLAB;
3063+ *uart_lcr = tmp;
3064+}
3065+
3066+void serial_putc (const char c)
3067+{
3068+ volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
3069+ volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
3070+
3071+ if (c == '\n') serial_putc ('\r');
3072+
3073+ /* Wait for fifo to shift out some bytes */
3074+ while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
3075+
3076+ *uart_tdr = (u8)c;
3077+}
3078+
3079+void serial_puts (const char *s)
3080+{
3081+ while (*s) {
3082+ serial_putc (*s++);
3083+ }
3084+}
3085+
3086+int serial_getc (void)
3087+{
3088+ volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
3089+
3090+ while (!serial_tstc());
3091+
3092+ return *uart_rdr;
3093+}
3094+
3095+int serial_tstc (void)
3096+{
3097+ volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
3098+
3099+ if (*uart_lsr & UART_LSR_DR) {
3100+ /* Data in rfifo */
3101+ return (1);
3102+ }
3103+ return 0;
3104+}
3105diff --git a/cpu/mips/mmc_protocol.h b/cpu/mips/mmc_protocol.h
3106new file mode 100644
3107index 0000000..9028cdf
3108+++ b/cpu/mips/mmc_protocol.h
3109@@ -0,0 +1,273 @@
3110+/*
3111+**********************************************************************
3112+*
3113+* uC/MMC
3114+*
3115+* (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc
3116+* All rights reserved.
3117+*
3118+***********************************************************************
3119+
3120+----------------------------------------------------------------------
3121+File : mmc_protocol.h
3122+Purpose : MMC protocol definitions.
3123+
3124+----------------------------------------------------------------------
3125+Version-Date-----Author-Explanation
3126+----------------------------------------------------------------------
3127+1.00.00 20060831 WeiJianli First release
3128+
3129+----------------------------------------------------------------------
3130+Known problems or limitations with current version
3131+----------------------------------------------------------------------
3132+(none)
3133+---------------------------END-OF-HEADER------------------------------
3134+*/
3135+
3136+#ifndef __MMC_PROTOCOL__
3137+#define __MMC_PROTOCOL__
3138+
3139+/* Standard MMC/SD clock speeds */
3140+#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */
3141+#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */
3142+#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */
3143+
3144+/* Extra MMC commands for state control */
3145+/* Use negative numbers to disambiguate */
3146+#define MMC_CIM_RESET -1
3147+
3148+/* Standard MMC commands (3.1) type argument response */
3149+ /* class 1 */
3150+#define MMC_GO_IDLE_STATE 0 /* bc */
3151+#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
3152+#define MMC_ALL_SEND_CID 2 /* bcr R2 */
3153+#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
3154+#define MMC_SET_DSR 4 /* bc [31:16] RCA */
3155+#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
3156+#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
3157+#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
3158+#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
3159+#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
3160+#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
3161+#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
3162+
3163+ /* class 2 */
3164+#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
3165+#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
3166+#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
3167+
3168+ /* class 3 */
3169+#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
3170+
3171+ /* class 4 */
3172+#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
3173+#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
3174+#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
3175+#define MMC_PROGRAM_CID 26 /* adtc R1 */
3176+#define MMC_PROGRAM_CSD 27 /* adtc R1 */
3177+
3178+ /* class 6 */
3179+#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
3180+#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
3181+#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
3182+
3183+ /* class 5 */
3184+#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
3185+#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
3186+#define MMC_ERASE 37 /* ac R1b */
3187+
3188+ /* class 9 */
3189+#define MMC_FAST_IO 39 /* ac <Complex> R4 */
3190+#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
3191+
3192+ /* class 7 */
3193+#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
3194+
3195+ /* class 8 */
3196+#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
3197+#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
3198+
3199+ /* SD class */
3200+#define SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */
3201+#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
3202+#define SEND_SCR 51 /* adtc [31:0] staff R1 */
3203+
3204+/* Don't change the order of these; they are used in dispatch tables */
3205+enum mmc_rsp_t {
3206+ RESPONSE_NONE = 0,
3207+ RESPONSE_R1 = 1,
3208+ RESPONSE_R1B = 2,
3209+ RESPONSE_R2_CID = 3,
3210+ RESPONSE_R2_CSD = 4,
3211+ RESPONSE_R3 = 5,
3212+ RESPONSE_R4 = 6,
3213+ RESPONSE_R5 = 7,
3214+ RESPONSE_R6 = 8,
3215+};
3216+
3217+
3218+/*
3219+ MMC status in R1
3220+ Type
3221+ e : error bit
3222+ s : status bit
3223+ r : detected and set for the actual command response
3224+ x : detected and set during command execution. the host must poll
3225+ the card by sending status command in order to read these bits.
3226+ Clear condition
3227+ a : according to the card state
3228+ b : always related to the previous command. Reception of
3229+ a valid command will clear it (with a delay of one command)
3230+ c : clear by read
3231+ */
3232+
3233+#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
3234+#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
3235+#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
3236+#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
3237+#define R1_ERASE_PARAM (1 << 27) /* ex, c */
3238+#define R1_WP_VIOLATION (1 << 26) /* erx, c */
3239+#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
3240+#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
3241+#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
3242+#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
3243+#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
3244+#define R1_CC_ERROR (1 << 20) /* erx, c */
3245+#define R1_ERROR (1 << 19) /* erx, c */
3246+#define R1_UNDERRUN (1 << 18) /* ex, c */
3247+#define R1_OVERRUN (1 << 17) /* ex, c */
3248+#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
3249+#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
3250+#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
3251+#define R1_ERASE_RESET (1 << 13) /* sr, c */
3252+#define R1_STATUS(x) (x & 0xFFFFE000)
3253+#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
3254+#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
3255+#define R1_APP_CMD (1 << 7) /* sr, c */
3256+
3257+enum card_state {
3258+ CARD_STATE_EMPTY = -1,
3259+ CARD_STATE_IDLE = 0,
3260+ CARD_STATE_READY = 1,
3261+ CARD_STATE_IDENT = 2,
3262+ CARD_STATE_STBY = 3,
3263+ CARD_STATE_TRAN = 4,
3264+ CARD_STATE_DATA = 5,
3265+ CARD_STATE_RCV = 6,
3266+ CARD_STATE_PRG = 7,
3267+ CARD_STATE_DIS = 8,
3268+};
3269+
3270+/* These are unpacked versions of the actual responses */
3271+
3272+ struct mmc_response_r1 {
3273+ u8 cmd;
3274+ u32 status;
3275+};
3276+
3277+typedef struct mmc_cid {
3278+ u8 mid;
3279+ u16 oid;
3280+ u8 pnm[7]; /* Product name (we null-terminate) */
3281+ u8 prv;
3282+ u32 psn;
3283+ u8 mdt;
3284+}mmc_cid_t;
3285+
3286+typedef struct mmc_csd {
3287+ u8 csd_structure;
3288+ u8 spec_vers;
3289+ u8 taac;
3290+ u8 nsac;
3291+ u8 tran_speed;
3292+ u16 ccc;
3293+ u8 read_bl_len;
3294+ u8 read_bl_partial;
3295+ u8 write_blk_misalign;
3296+ u8 read_blk_misalign;
3297+ u8 dsr_imp;
3298+ u16 c_size;
3299+ u8 vdd_r_curr_min;
3300+ u8 vdd_r_curr_max;
3301+ u8 vdd_w_curr_min;
3302+ u8 vdd_w_curr_max;
3303+ u8 c_size_mult;
3304+ union {
3305+ struct { /* MMC system specification version 3.1 */
3306+ u8 erase_grp_size;
3307+ u8 erase_grp_mult;
3308+ } v31;
3309+ struct { /* MMC system specification version 2.2 */
3310+ u8 sector_size;
3311+ u8 erase_grp_size;
3312+ } v22;
3313+ } erase;
3314+ u8 wp_grp_size;
3315+ u8 wp_grp_enable;
3316+ u8 default_ecc;
3317+ u8 r2w_factor;
3318+ u8 write_bl_len;
3319+ u8 write_bl_partial;
3320+ u8 file_format_grp;
3321+ u8 copy;
3322+ u8 perm_write_protect;
3323+ u8 tmp_write_protect;
3324+ u8 file_format;
3325+ u8 ecc;
3326+}mmc_csd_t;;
3327+
3328+struct mmc_response_r3 {
3329+ u32 ocr;
3330+};
3331+
3332+#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
3333+#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
3334+#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
3335+#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
3336+#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
3337+#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
3338+#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
3339+#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
3340+#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
3341+#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
3342+#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
3343+#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
3344+#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
3345+#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
3346+#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
3347+#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
3348+#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
3349+#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
3350+#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
3351+#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
3352+#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
3353+#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
3354+#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
3355+#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
3356+#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
3357+
3358+
3359+/* CSD field definitions */
3360+
3361+#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
3362+#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
3363+#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
3364+
3365+#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
3366+#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
3367+#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
3368+#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
3369+
3370+#if MMC_DEBUG_LEVEL
3371+
3372+#define DEBUG(n, args...) \
3373+ do { \
3374+ if (n <= MMC_DEBUG_LEVEL) { \
3375+ printf(args); \
3376+ } \
3377+ } while(0)
3378+#else
3379+#define DEBUG(n, args...)
3380+#endif /* MMC_DEBUG_EN */
3381+
3382+#endif /* __MMC_PROTOCOL__ */
3383diff --git a/cpu/mips/qi_lb60_gpm940b0.c b/cpu/mips/qi_lb60_gpm940b0.c
3384new file mode 100644
3385index 0000000..79af40e
3386+++ b/cpu/mips/qi_lb60_gpm940b0.c
3387@@ -0,0 +1,420 @@
3388+/*
3389+ * JzRISC lcd controller
3390+ *
3391+ * xiangfu liu <xiangfu.z@gmail.com>
3392+ *
3393+ * This program is free software; you can redistribute it and/or
3394+ * modify it under the terms of the GNU General Public License as
3395+ * published by the Free Software Foundation; either version 2 of
3396+ * the License, or (at your option) any later version.
3397+ *
3398+ * This program is distributed in the hope that it will be useful,
3399+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3400+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3401+ * GNU General Public License for more details.
3402+ *
3403+ * You should have received a copy of the GNU General Public License
3404+ * along with this program; if not, write to the Free Software
3405+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3406+ * MA 02111-1307 USA
3407+ */
3408+
3409+#include <config.h>
3410+#include <common.h>
3411+#include <lcd.h>
3412+
3413+#include <asm/io.h> /* virt_to_phys() */
3414+
3415+#include <asm/jz4740.h>
3416+#include "qi_lb60_gpm940b0.h"
3417+
3418+#define align2(n) (n)=((((n)+1)>>1)<<1)
3419+#define align4(n) (n)=((((n)+3)>>2)<<2)
3420+#define align8(n) (n)=((((n)+7)>>3)<<3)
3421+
3422+struct jzfb_info {
3423+ unsigned int cfg; /* panel mode and pin usage etc. */
3424+ unsigned int w;
3425+ unsigned int h;
3426+ unsigned int bpp; /* bit per pixel */
3427+ unsigned int fclk; /* frame clk */
3428+ unsigned int hsw; /* hsync width, in pclk */
3429+ unsigned int vsw; /* vsync width, in line count */
3430+ unsigned int elw; /* end of line, in pclk */
3431+ unsigned int blw; /* begin of line, in pclk */
3432+ unsigned int efw; /* end of frame, in line count */
3433+ unsigned int bfw; /* begin of frame, in line count */
3434+};
3435+
3436+static struct jzfb_info jzfb = {
3437+ MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
3438+ 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
3439+};
3440+
3441+vidinfo_t panel_info = {
3442+ 320, 240, LCD_BPP,
3443+};
3444+
3445+int lcd_line_length;
3446+
3447+int lcd_color_fg;
3448+int lcd_color_bg;
3449+/*
3450+ * Frame buffer memory information
3451+ */
3452+void *lcd_base; /* Start of framebuffer memory */
3453+void *lcd_console_address; /* Start of console buffer */
3454+
3455+short console_col;
3456+short console_row;
3457+
3458+void lcd_ctrl_init (void *lcdbase);
3459+void lcd_enable (void);
3460+void lcd_disable (void);
3461+
3462+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
3463+static void jz_lcd_desc_init(vidinfo_t *vid);
3464+static int jz_lcd_hw_init( vidinfo_t *vid );
3465+extern int flush_cache_all(void);
3466+
3467+void lcd_ctrl_init (void *lcdbase)
3468+{
3469+ __lcd_display_pin_init();
3470+
3471+ jz_lcd_init_mem(lcdbase, &panel_info);
3472+ jz_lcd_desc_init(&panel_info);
3473+ jz_lcd_hw_init(&panel_info);
3474+
3475+ __lcd_display_on() ;
3476+}
3477+
3478+/*
3479+ * Before enabled lcd controller, lcd registers should be configured correctly.
3480+ */
3481+
3482+void lcd_enable (void)
3483+{
3484+ REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
3485+ REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
3486+}
3487+
3488+void lcd_disable (void)
3489+{
3490+ REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
3491+ /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
3492+}
3493+
3494+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
3495+{
3496+ u_long palette_mem_size;
3497+ struct jz_fb_info *fbi = &vid->jz_fb;
3498+ int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
3499+
3500+ fbi->screen = (u_long)lcdbase;
3501+ fbi->palette_size = 256;
3502+ palette_mem_size = fbi->palette_size * sizeof(u16);
3503+
3504+ debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
3505+ /* locate palette and descs at end of page following fb */
3506+ fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
3507+
3508+ return 0;
3509+}
3510+
3511+static void jz_lcd_desc_init(vidinfo_t *vid)
3512+{
3513+ struct jz_fb_info * fbi;
3514+ fbi = &vid->jz_fb;
3515+ fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
3516+ fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
3517+ fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
3518+
3519+ #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
3520+
3521+ /* populate descriptors */
3522+ fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
3523+ fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
3524+ fbi->dmadesc_fblow->fidr = 0;
3525+ fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
3526+
3527+ fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
3528+
3529+ fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
3530+ fbi->dmadesc_fbhigh->fidr = 0;
3531+ fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
3532+
3533+ fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
3534+ fbi->dmadesc_palette->fidr = 0;
3535+ fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
3536+
3537+ if(NBITS(vid->vl_bpix) < 12)
3538+ {
3539+ /* assume any mode with <12 bpp is palette driven */
3540+ fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
3541+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
3542+ /* flips back and forth between pal and fbhigh */
3543+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
3544+ } else {
3545+ /* palette shouldn't be loaded in true-color mode */
3546+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
3547+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
3548+ }
3549+
3550+ flush_cache_all();
3551+}
3552+
3553+static int jz_lcd_hw_init(vidinfo_t *vid)
3554+{
3555+ struct jz_fb_info *fbi = &vid->jz_fb;
3556+ unsigned int val = 0;
3557+ unsigned int pclk;
3558+ unsigned int stnH;
3559+ int pll_div;
3560+
3561+ /* Setting Control register */
3562+ switch (jzfb.bpp) {
3563+ case 1:
3564+ val |= LCD_CTRL_BPP_1;
3565+ break;
3566+ case 2:
3567+ val |= LCD_CTRL_BPP_2;
3568+ break;
3569+ case 4:
3570+ val |= LCD_CTRL_BPP_4;
3571+ break;
3572+ case 8:
3573+ val |= LCD_CTRL_BPP_8;
3574+ break;
3575+ case 15:
3576+ val |= LCD_CTRL_RGB555;
3577+ case 16:
3578+ val |= LCD_CTRL_BPP_16;
3579+ break;
3580+ case 17 ... 32:
3581+ val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
3582+ break;
3583+
3584+ default:
3585+ printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
3586+ val |= LCD_CTRL_BPP_16;
3587+ break;
3588+ }
3589+
3590+ switch (jzfb.cfg & MODE_MASK) {
3591+ case MODE_STN_MONO_DUAL:
3592+ case MODE_STN_COLOR_DUAL:
3593+ case MODE_STN_MONO_SINGLE:
3594+ case MODE_STN_COLOR_SINGLE:
3595+ switch (jzfb.bpp) {
3596+ case 1:
3597+ /* val |= LCD_CTRL_PEDN; */
3598+ case 2:
3599+ val |= LCD_CTRL_FRC_2;
3600+ break;
3601+ case 4:
3602+ val |= LCD_CTRL_FRC_4;
3603+ break;
3604+ case 8:
3605+ default:
3606+ val |= LCD_CTRL_FRC_16;
3607+ break;
3608+ }
3609+ break;
3610+ }
3611+
3612+ val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
3613+ val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
3614+
3615+ switch (jzfb.cfg & MODE_MASK) {
3616+ case MODE_STN_MONO_DUAL:
3617+ case MODE_STN_COLOR_DUAL:
3618+ case MODE_STN_MONO_SINGLE:
3619+ case MODE_STN_COLOR_SINGLE:
3620+ switch (jzfb.cfg & STN_DAT_PINMASK) {
3621+ case STN_DAT_PIN1:
3622+ /* Do not adjust the hori-param value. */
3623+ break;
3624+ case STN_DAT_PIN2:
3625+ align2(jzfb.hsw);
3626+ align2(jzfb.elw);
3627+ align2(jzfb.blw);
3628+ break;
3629+ case STN_DAT_PIN4:
3630+ align4(jzfb.hsw);
3631+ align4(jzfb.elw);
3632+ align4(jzfb.blw);
3633+ break;
3634+ case STN_DAT_PIN8:
3635+ align8(jzfb.hsw);
3636+ align8(jzfb.elw);
3637+ align8(jzfb.blw);
3638+ break;
3639+ }
3640+ break;
3641+ }
3642+
3643+ REG_LCD_CTRL = val;
3644+
3645+ switch (jzfb.cfg & MODE_MASK) {
3646+ case MODE_STN_MONO_DUAL:
3647+ case MODE_STN_COLOR_DUAL:
3648+ case MODE_STN_MONO_SINGLE:
3649+ case MODE_STN_COLOR_SINGLE:
3650+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
3651+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
3652+ stnH = jzfb.h >> 1;
3653+ else
3654+ stnH = jzfb.h;
3655+
3656+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
3657+ REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
3658+
3659+ /* Screen setting */
3660+ REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
3661+ REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
3662+ REG_LCD_DAV = (0 << 16) | (stnH);
3663+
3664+ /* AC BIAs signal */
3665+ REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
3666+
3667+ break;
3668+
3669+ case MODE_TFT_GEN:
3670+ case MODE_TFT_SHARP:
3671+ case MODE_TFT_CASIO:
3672+ case MODE_TFT_SAMSUNG:
3673+ case MODE_8BIT_SERIAL_TFT:
3674+ case MODE_TFT_18BIT:
3675+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
3676+ REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
3677+ REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
3678+ REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
3679+ REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
3680+ | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
3681+ break;
3682+ }
3683+
3684+ switch (jzfb.cfg & MODE_MASK) {
3685+ case MODE_TFT_SAMSUNG:
3686+ {
3687+ unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
3688+ unsigned int rev_s, rev_e, inv_s, inv_e;
3689+
3690+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
3691+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
3692+
3693+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
3694+ tp_s = jzfb.blw + jzfb.w + 1;
3695+ tp_e = tp_s + 1;
3696+ /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
3697+ ckv_s = tp_s - pclk/(1000000000/4100);
3698+ ckv_e = tp_s + total;
3699+ rev_s = tp_s - 11; /* -11.5 clk */
3700+ rev_e = rev_s + total;
3701+ inv_s = tp_s;
3702+ inv_e = inv_s + total;
3703+ REG_LCD_CLS = (tp_s << 16) | tp_e;
3704+ REG_LCD_PS = (ckv_s << 16) | ckv_e;
3705+ REG_LCD_SPL = (rev_s << 16) | rev_e;
3706+ REG_LCD_REV = (inv_s << 16) | inv_e;
3707+ jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
3708+ break;
3709+ }
3710+ case MODE_TFT_SHARP:
3711+ {
3712+ unsigned int total, cls_s, cls_e, ps_s, ps_e;
3713+ unsigned int spl_s, spl_e, rev_s, rev_e;
3714+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
3715+ spl_s = 1;
3716+ spl_e = spl_s + 1;
3717+ cls_s = 0;
3718+ cls_e = total - 60; /* > 4us (pclk = 80ns) */
3719+ ps_s = cls_s;
3720+ ps_e = cls_e;
3721+ rev_s = total - 40; /* > 3us (pclk = 80ns) */
3722+ rev_e = rev_s + total;
3723+ jzfb.cfg |= STFT_PSHI;
3724+ REG_LCD_SPL = (spl_s << 16) | spl_e;
3725+ REG_LCD_CLS = (cls_s << 16) | cls_e;
3726+ REG_LCD_PS = (ps_s << 16) | ps_e;
3727+ REG_LCD_REV = (rev_s << 16) | rev_e;
3728+ break;
3729+ }
3730+ case MODE_TFT_CASIO:
3731+ break;
3732+ }
3733+
3734+ /* Configure the LCD panel */
3735+ REG_LCD_CFG = jzfb.cfg;
3736+
3737+ /* Timing setting */
3738+ __cpm_stop_lcd();
3739+
3740+ val = jzfb.fclk; /* frame clk */
3741+ if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
3742+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
3743+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
3744+ } else {
3745+ /* serial mode: Hsync period = 3*Width_Pixel */
3746+ pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
3747+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
3748+ }
3749+
3750+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
3751+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
3752+ pclk = (pclk * 3);
3753+
3754+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
3755+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
3756+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
3757+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
3758+ pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
3759+
3760+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
3761+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
3762+ pclk >>= 1;
3763+
3764+ pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
3765+ pll_div = pll_div ? 1 : 2 ;
3766+ val = ( __cpm_get_pllout()/pll_div ) / pclk;
3767+ val--;
3768+ if ( val > 0x1ff ) {
3769+ printf("CPM_LPCDR too large, set it to 0x1ff\n");
3770+ val = 0x1ff;
3771+ }
3772+ __cpm_set_pixdiv(val);
3773+
3774+ val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
3775+ if ( val > 150000000 ) {
3776+ printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
3777+ printf("Change LCDClock to 150MHz\n");
3778+ val = 150000000;
3779+ }
3780+ val = ( __cpm_get_pllout()/pll_div ) / val;
3781+ val--;
3782+ if ( val > 0x1f ) {
3783+ printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
3784+ val = 0x1f;
3785+ }
3786+ __cpm_set_ldiv( val );
3787+ REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
3788+
3789+ __cpm_start_lcd();
3790+ udelay(1000);
3791+
3792+ REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
3793+
3794+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
3795+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
3796+ REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
3797+
3798+ return 0;
3799+}
3800+
3801+void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
3802+{
3803+}
3804+
3805+void lcd_initcolregs (void)
3806+{
3807+}
3808diff --git a/cpu/mips/qi_lb60_gpm940b0.h b/cpu/mips/qi_lb60_gpm940b0.h
3809new file mode 100644
3810index 0000000..a4f8b0b
3811+++ b/cpu/mips/qi_lb60_gpm940b0.h
3812@@ -0,0 +1,212 @@
3813+/*
3814+ * JzRISC lcd controller
3815+ *
3816+ * xiangfu liu <xiangfu.z@gmail.com>
3817+ *
3818+ * This program is free software; you can redistribute it and/or
3819+ * modify it under the terms of the GNU General Public License as
3820+ * published by the Free Software Foundation; either version 2 of
3821+ * the License, or (at your option) any later version.
3822+ *
3823+ * This program is distributed in the hope that it will be useful,
3824+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3825+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3826+ * GNU General Public License for more details.
3827+ *
3828+ * You should have received a copy of the GNU General Public License
3829+ * along with this program; if not, write to the Free Software
3830+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3831+ * MA 02111-1307 USA
3832+ */
3833+
3834+#ifndef __QI_LB60_GPM940B0_H__
3835+#define __QI_LB60_GPM940B0_H__
3836+
3837+#include <asm/io.h>
3838+
3839+#define mdelay(n) udelay((n)*1000)
3840+
3841+#define NR_PALETTE 256
3842+
3843+struct lcd_desc{
3844+ unsigned int next_desc; /* LCDDAx */
3845+ unsigned int databuf; /* LCDSAx */
3846+ unsigned int frame_id; /* LCDFIDx */
3847+ unsigned int cmd; /* LCDCMDx */
3848+};
3849+
3850+#define MODE_MASK 0x0f
3851+#define MODE_TFT_GEN 0x00
3852+#define MODE_TFT_SHARP 0x01
3853+#define MODE_TFT_CASIO 0x02
3854+#define MODE_TFT_SAMSUNG 0x03
3855+#define MODE_CCIR656_NONINT 0x04
3856+#define MODE_CCIR656_INT 0x05
3857+#define MODE_STN_COLOR_SINGLE 0x08
3858+#define MODE_STN_MONO_SINGLE 0x09
3859+#define MODE_STN_COLOR_DUAL 0x0a
3860+#define MODE_STN_MONO_DUAL 0x0b
3861+#define MODE_8BIT_SERIAL_TFT 0x0c
3862+
3863+#define MODE_TFT_18BIT (1<<7)
3864+
3865+#define STN_DAT_PIN1 (0x00 << 4)
3866+#define STN_DAT_PIN2 (0x01 << 4)
3867+#define STN_DAT_PIN4 (0x02 << 4)
3868+#define STN_DAT_PIN8 (0x03 << 4)
3869+#define STN_DAT_PINMASK STN_DAT_PIN8
3870+
3871+#define STFT_PSHI (1 << 15)
3872+#define STFT_CLSHI (1 << 14)
3873+#define STFT_SPLHI (1 << 13)
3874+#define STFT_REVHI (1 << 12)
3875+
3876+#define SYNC_MASTER (0 << 16)
3877+#define SYNC_SLAVE (1 << 16)
3878+
3879+#define DE_P (0 << 9)
3880+#define DE_N (1 << 9)
3881+
3882+#define PCLK_P (0 << 10)
3883+#define PCLK_N (1 << 10)
3884+
3885+#define HSYNC_P (0 << 11)
3886+#define HSYNC_N (1 << 11)
3887+
3888+#define VSYNC_P (0 << 8)
3889+#define VSYNC_N (1 << 8)
3890+
3891+#define DATA_NORMAL (0 << 17)
3892+#define DATA_INVERSE (1 << 17)
3893+
3894+
3895+/* Jz LCDFB supported I/O controls. */
3896+#define FBIOSETBACKLIGHT 0x4688
3897+#define FBIODISPON 0x4689
3898+#define FBIODISPOFF 0x468a
3899+#define FBIORESET 0x468b
3900+#define FBIOPRINT_REG 0x468c
3901+
3902+/*
3903+ * LCD panel specific definition
3904+ */
3905+#define MODE 0xc9 /* 8bit serial RGB */
3906+#define SPEN (32*2+21) /*LCD_SPL */
3907+#define SPCK (32*2+23) /*LCD_CLS */
3908+#define SPDA (32*2+22) /*LCD_D12 */
3909+#define LCD_RET (32*3+27)
3910+
3911+#define __spi_write_reg1(reg, val) \
3912+do { \
3913+ unsigned char no;\
3914+ unsigned short value;\
3915+ unsigned char a=0;\
3916+ unsigned char b=0;\
3917+ a=reg;\
3918+ b=val;\
3919+ __gpio_set_pin(SPEN);\
3920+ __gpio_set_pin(SPCK);\
3921+ __gpio_clear_pin(SPDA);\
3922+ __gpio_clear_pin(SPEN);\
3923+ udelay(25);\
3924+ value=((a<<8)|(b&0xFF));\
3925+ for(no=0;no<16;no++)\
3926+ {\
3927+ __gpio_clear_pin(SPCK);\
3928+ if((value&0x8000)==0x8000)\
3929+ __gpio_set_pin(SPDA);\
3930+ else\
3931+ __gpio_clear_pin(SPDA);\
3932+ udelay(25);\
3933+ __gpio_set_pin(SPCK);\
3934+ value=(value<<1); \
3935+ udelay(25);\
3936+ }\
3937+ __gpio_set_pin(SPEN);\
3938+ udelay(100);\
3939+} while (0)
3940+
3941+#define __spi_write_reg(reg, val) \
3942+do {\
3943+ __spi_write_reg1((reg<<2|2), val);\
3944+ udelay(100); \
3945+}while(0)
3946+
3947+#define __lcd_special_pin_init() \
3948+do { \
3949+ __gpio_as_output(SPEN); /* use SPDA */\
3950+ __gpio_as_output(SPCK); /* use SPCK */\
3951+ __gpio_as_output(SPDA); /* use SPDA */\
3952+ __gpio_as_output(LCD_RET);\
3953+} while (0)
3954+
3955+#define __lcd_special_on() \
3956+do { \
3957+ udelay(50);\
3958+ __spi_write_reg1(0x05, 0x16); \
3959+ __spi_write_reg1(0x04, 0x0b); \
3960+ __spi_write_reg1(0x07, 0x8d); \
3961+ __spi_write_reg1(0x01, 0x95); \
3962+ __spi_write_reg1(0x08, 0xc0); \
3963+ __spi_write_reg1(0x03, 0x40); \
3964+ __spi_write_reg1(0x06, 0x75); \
3965+ __spi_write_reg1(0x13, 0x01); \
3966+ __spi_write_reg1(0x05, 0x57); \
3967+} while (0)
3968+
3969+#define __lcd_special_off() \
3970+do { \
3971+ __spi_write_reg1(0x05, 0x5e); \
3972+} while (0)
3973+
3974+#define __lcd_display_pin_init() \
3975+do { \
3976+ __lcd_special_pin_init();\
3977+ __gpio_as_pwm();\
3978+ __lcd_set_backlight_level(8);\
3979+} while (0)
3980+
3981+#define __lcd_display_on() \
3982+do { \
3983+ __lcd_set_backlight_level(8); \
3984+ __lcd_special_on();\
3985+} while (0)
3986+
3987+#define __lcd_display_off() \
3988+do { \
3989+ __lcd_set_backlight_level(0); \
3990+ __lcd_special_off();\
3991+} while (0)
3992+
3993+#define __lcd_set_backlight_level(n)\
3994+do { \
3995+ __gpio_as_output(LCD_RET); \
3996+ __gpio_set_pin(LCD_RET); \
3997+} while (0)
3998+
3999+#define __lcd_close_backlight() \
4000+do { \
4001+ __gpio_as_output(GPIO_PWM); \
4002+ __gpio_clear_pin(GPIO_PWM); \
4003+} while (0)
4004+
4005+#define __lcd_display_pin_init() \
4006+do { \
4007+ __gpio_as_output(GPIO_DISP_OFF_N); \
4008+ __cpm_start_tcu(); \
4009+ __lcd_special_pin_init(); \
4010+} while (0)
4011+
4012+#define __lcd_display_on() \
4013+do { \
4014+ __gpio_set_pin(GPIO_DISP_OFF_N); \
4015+ __lcd_special_on(); \
4016+} while (0)
4017+
4018+#define __lcd_display_off() \
4019+do { \
4020+ __lcd_special_off(); \
4021+ __gpio_clear_pin(GPIO_DISP_OFF_N); \
4022+} while (0)
4023+
4024+#endif /* __QI_LB60_GPM940B0_H__ */
4025diff --git a/cpu/mips/usb_boot.S b/cpu/mips/usb_boot.S
4026new file mode 100644
4027index 0000000..f556e04
4028+++ b/cpu/mips/usb_boot.S
4029@@ -0,0 +1,880 @@
4030+/*
4031+ * for jz4740 usb boot
4032+ *
4033+ * Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com>
4034+ *
4035+ * See file CREDITS for list of people who contributed to this
4036+ * project.
4037+ *
4038+ * This program is free software; you can redistribute it and/or
4039+ * modify it under the terms of the GNU General Public License as
4040+ * published by the Free Software Foundation; either version 2 of
4041+ * the License, or (at your option) any later version.
4042+ *
4043+ * This program is distributed in the hope that it will be useful,
4044+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4045+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4046+ * GNU General Public License for more details.
4047+ *
4048+ * You should have received a copy of the GNU General Public License
4049+ * along with this program; if not, write to the Free Software
4050+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4051+ * MA 02111-1307 USA
4052+ */
4053+ .set noreorder
4054+ .globl usb_boot
4055+ .text
4056+
4057+//----------------------------------------------------------------------
4058+// Both NAND and USB boot load data to D-Cache first, then transfer
4059+// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
4060+// So init caches first and then dispatch to a proper boot routine.
4061+//----------------------------------------------------------------------
4062+
4063+.macro load_addr reg addr
4064+ li \reg, 0x80000000
4065+ addiu \reg, \reg, \addr
4066+ la $2, usbboot_begin
4067+ subu \reg, \reg, $2
4068+.endm
4069+
4070+usb_boot:
4071+ //--------------------------------------------------------------
4072+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
4073+ //--------------------------------------------------------------
4074+ la $9, 0xB0000000 // CPCCR: Clock Control Register
4075+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
4076+ sw $8, 0($9)
4077+
4078+ la $9, 0xB0000010 // CPPCR: PLL Control Register
4079+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
4080+ sw $8, 0($9)
4081+
4082+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
4083+ nop
4084+
4085+ mtc0 $0, $16 // CP0_CONFIG
4086+ nop
4087+
4088+ // Relocate code to beginning of the ram
4089+
4090+ la $2, usbboot_begin
4091+ la $3, usbboot_end
4092+ li $4, 0x80000000
4093+
4094+1:
4095+ lw $5, 0($2)
4096+ sw $5, 0($4)
4097+ addiu $2, $2, 4
4098+ bne $2, $3, 1b
4099+ addiu $4, $4, 4
4100+
4101+ li $2, 0x80000000
4102+ ori $3, $2, 0
4103+ addiu $3, $3, usbboot_end
4104+ la $4, usbboot_begin
4105+ subu $3, $3, $4
4106+
4107+
4108+2:
4109+ cache 0x0, 0($2) // Index_Invalidate_I
4110+ cache 0x1, 0($2) // Index_Writeback_Inv_D
4111+ addiu $2, $2, 32
4112+ subu $4, $3, $2
4113+ bgtz $4, 2b
4114+ nop
4115+
4116+ load_addr $3, usb_boot_return
4117+
4118+ jr $3
4119+
4120+usbboot_begin:
4121+
4122+init_caches:
4123+ li $2, 3 // cacheable for kseg0 access
4124+ mtc0 $2, $16 // CP0_CONFIG
4125+ nop
4126+
4127+ li $2, 0x20000000 // enable idx-store-data cache insn
4128+ mtc0 $2, $26 // CP0_ERRCTL
4129+
4130+ ori $2, $28, 0 // start address
4131+ ori $3, $2, 0x3fe0 // end address, total 16KB
4132+ mtc0 $0, $28, 0 // CP0_TAGLO
4133+ mtc0 $0, $28, 1 // CP0_DATALO
4134+cache_clear_a_line:
4135+ cache 0x8, 0($2) // Index_Store_Tag_I
4136+ cache 0x9, 0($2) // Index_Store_Tag_D
4137+ bne $2, $3, cache_clear_a_line
4138+ addiu $2, $2, 32 // increment CACHE_LINE_SIZE
4139+
4140+ ori $2, $28, 0 // start address
4141+ ori $3, $2, 0x3fe0 // end address, total 16KB
4142+ la $4, 0x1ffff000 // physical address and 4KB page mask
4143+cache_alloc_a_line:
4144+ and $5, $2, $4
4145+ ori $5, $5, 1 // V bit of the physical tag
4146+ mtc0 $5, $28, 0 // CP0_TAGLO
4147+ cache 0x8, 0($2) // Index_Store_Tag_I
4148+ cache 0x9, 0($2) // Index_Store_Tag_D
4149+ bne $2, $3, cache_alloc_a_line
4150+ addiu $2, $2, 32 // increment CACHE_LINE_SIZE
4151+
4152+ nop
4153+ nop
4154+ nop
4155+ //--------------------------------------------------------------
4156+ // Transfer data from dcache to icache, then jump to icache.
4157+ //
4158+ // Input parameters:
4159+ //
4160+ // $19: data length in bytes
4161+ // $20: jump target address
4162+ //--------------------------------------------------------------
4163+xfer_d2i:
4164+
4165+ ori $8, $20, 0
4166+ addu $9, $8, $19 // total 16KB
4167+
4168+1:
4169+ cache 0x0, 0($8) // Index_Invalidate_I
4170+ cache 0x1, 0($8) // Index_Writeback_Inv_D
4171+ bne $8, $9, 1b
4172+ addiu $8, $8, 32
4173+
4174+ // flush write-buffer
4175+ sync
4176+
4177+ // Invalidate BTB
4178+ mfc0 $8, $16, 7 // CP0_CONFIG
4179+ nop
4180+ ori $8, 2
4181+ mtc0 $8, $16, 7
4182+ nop
4183+
4184+ // Overwrite config to disable ram initalisation
4185+ li $2, 0xff
4186+ sb $2, 20($20)
4187+
4188+ jalr $20
4189+ nop
4190+
4191+icache_return:
4192+ //--------------------------------------------------------------
4193+ // User code can return to here after executing itself in
4194+ // icache, by jumping to $31.
4195+ //--------------------------------------------------------------
4196+ b usb_boot_return
4197+ nop
4198+
4199+
4200+usb_boot_return:
4201+ //--------------------------------------------------------------
4202+ // Enable the USB PHY
4203+ //--------------------------------------------------------------
4204+ la $9, 0xB0000024 // CPM_SCR
4205+ lw $8, 0($9)
4206+ ori $8, 0x40 // USBPHY_ENABLE
4207+ sw $8, 0($9)
4208+
4209+ //--------------------------------------------------------------
4210+ // Initialize USB registers
4211+ //--------------------------------------------------------------
4212+ la $27, 0xb3040000 // USB registers base address
4213+
4214+ sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts
4215+ sh $0, 0x06($27) // INTRINE: disable EPIN interrutps
4216+ sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps
4217+
4218+ li $9, 0x61
4219+ sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN
4220+
4221+ //--------------------------------------------------------------
4222+ // Initialize USB states
4223+ //--------------------------------------------------------------
4224+ li $22, 0 // set EP0 to IDLE state
4225+ li $23, 1 // no data stage
4226+
4227+ //--------------------------------------------------------------
4228+ // Main loop of polling the usb commands
4229+ //--------------------------------------------------------------
4230+usb_command_loop:
4231+ lbu $9, 0x0a($27) // read INTRUSB
4232+ andi $9, 0x04 // check USB_INTR_RESET
4233+ beqz $9, check_intr_ep0in
4234+ nop
4235+
4236+ //--------------------------------------------------------------
4237+ // 1. Handle USB reset interrupt
4238+ //--------------------------------------------------------------
4239+handle_reset_intr:
4240+ lbu $9, 0x01($27) // read POWER
4241+ andi $9, 0x10 // test HS_MODE
4242+ bnez $9, _usb_set_maxpktsize
4243+ li $9, 512 // max packet size of HS mode
4244+ li $9, 64 // max packet size of FS mode
4245+
4246+_usb_set_maxpktsize:
4247+ li $8, 1
4248+ sb $8, 0x0e($27) // set INDEX 1
4249+
4250+ sh $9, 0x10($27) // INMAXP
4251+ sb $0, 0x13($27) // INCSRH
4252+ sh $9, 0x14($27) // OUTMAXP
4253+ sb $0, 0x17($27) // OUTCSRH
4254+
4255+_usb_flush_fifo:
4256+ li $8, 0x48 // INCSR_CDT && INCSR_FF
4257+ sb $8, 0x12($27) // INCSR
4258+ li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF
4259+ sb $8, 0x16($27) // OUTCSR
4260+
4261+ li $22, 0 // set EP0 to IDLE state
4262+ li $23, 1 // no data stage
4263+
4264+ //--------------------------------------------------------------
4265+ // 2. Check and handle EP0 interrupt
4266+ //--------------------------------------------------------------
4267+check_intr_ep0in:
4268+ lhu $10, 0x02($27) // read INTRIN
4269+ andi $9, $10, 0x1 // check EP0 interrupt
4270+ beqz $9, check_intr_ep1in
4271+ nop
4272+
4273+handle_ep0_intr:
4274+ sb $0, 0x0e($27) // set INDEX 0
4275+ lbu $11, 0x12($27) // read CSR0
4276+
4277+ andi $9, $11, 0x04 // check SENTSTALL
4278+ beqz $9, _ep0_setupend
4279+ nop
4280+
4281+_ep0_sentstall:
4282+ andi $9, $11, 0xdb
4283+ sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL
4284+ li $22, 0 // set EP0 to IDLE state
4285+
4286+_ep0_setupend:
4287+ andi $9, $11, 0x10 // check SETUPEND
4288+ beqz $9, ep0_idle_state
4289+ nop
4290+
4291+ ori $9, $11, 0x80
4292+ sb $9, 0x12($27) // set SVDSETUPEND
4293+ li $22, 0 // set EP0 to IDLE state
4294+
4295+ep0_idle_state:
4296+ bnez $22, ep0_tx_state
4297+ nop
4298+
4299+ //--------------------------------------------------------------
4300+ // 2.1 Handle EP0 IDLE state interrupt
4301+ //--------------------------------------------------------------
4302+ andi $9, $11, 0x01 // check OUTPKTRDY
4303+ beqz $9, check_intr_ep1in
4304+ nop
4305+
4306+ //--------------------------------------------------------------
4307+ // Read 8-bytes setup packet from the FIFO
4308+ //--------------------------------------------------------------
4309+ lw $25, 0x20($27) // first word of setup packet
4310+ lw $26, 0x20($27) // second word of setup packet
4311+
4312+ andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK
4313+ beqz $9, _ep0_std_req
4314+ nop
4315+
4316+ //--------------------------------------------------------------
4317+ // 2.1.1 Vendor-specific setup request
4318+ //--------------------------------------------------------------
4319+_ep0_vend_req:
4320+ li $22, 0 // set EP0 to IDLE state
4321+ li $23, 1 // NoData = 1
4322+
4323+ andi $9, $25, 0xff00 // check bRequest
4324+ srl $9, $9, 8
4325+ beqz $9, __ep0_get_cpu_info
4326+ sub $8, $9, 0x1
4327+ beqz $8, __ep0_set_data_address
4328+ sub $8, $9, 0x2
4329+ beqz $8, __ep0_set_data_length
4330+ sub $8, $9, 0x3
4331+ beqz $8, __ep0_flush_caches
4332+ sub $8, $9, 0x4
4333+ beqz $8, __ep0_prog_start1
4334+ sub $8, $9, 0x5
4335+ beqz $8, __ep0_prog_start2
4336+ nop
4337+ b _ep0_idle_state_fini // invalid request
4338+ nop
4339+
4340+__ep0_get_cpu_info:
4341+ load_addr $20, cpu_info_data // data pointer to transfer
4342+ li $21, 8 // bytes left to transfer
4343+ li $22, 1 // set EP0 to TX state
4344+ li $23, 0 // NoData = 0
4345+
4346+ b _ep0_idle_state_fini
4347+ nop
4348+
4349+__ep0_set_data_address:
4350+ li $9, 0xffff0000
4351+ and $9, $25, $9
4352+ andi $8, $26, 0xffff
4353+ or $20, $9, $8 // data address of next transfer
4354+
4355+ b _ep0_idle_state_fini
4356+ nop
4357+
4358+__ep0_set_data_length:
4359+ li $9, 0xffff0000
4360+ and $9, $25, $9
4361+ andi $8, $26, 0xffff
4362+ or $21, $9, $8 // data length of next transfer
4363+
4364+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
4365+ sb $9, 0x12($27) // CSR0
4366+
4367+ // We must write packet to FIFO before EP1-IN interrupt here.
4368+ b handle_epin1_intr
4369+ nop
4370+
4371+__ep0_flush_caches:
4372+ // Flush dcache and invalidate icache.
4373+ li $8, 0x80000000
4374+ addi $9, $8, 0x3fe0 // total 16KB
4375+
4376+1:
4377+ cache 0x0, 0($8) // Index_Invalidate_I
4378+ cache 0x1, 0($8) // Index_Writeback_Inv_D
4379+ bne $8, $9, 1b
4380+ addiu $8, $8, 32
4381+
4382+ // flush write-buffer
4383+ sync
4384+
4385+ // Invalidate BTB
4386+ mfc0 $8, $16, 7 // CP0_CONFIG
4387+ nop
4388+ ori $8, 2
4389+ mtc0 $8, $16, 7
4390+ nop
4391+
4392+ b _ep0_idle_state_fini
4393+ nop
4394+
4395+__ep0_prog_start1:
4396+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
4397+ sb $9, 0x12($27) // CSR0
4398+
4399+ li $9, 0xffff0000
4400+ and $9, $25, $9
4401+ andi $8, $26, 0xffff
4402+ or $20, $9, $8 // target address
4403+
4404+ b xfer_d2i
4405+ li $19, 0x2000 // 16KB data length
4406+
4407+__ep0_prog_start2:
4408+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
4409+ sb $9, 0x12($27) // CSR0
4410+
4411+ li $9, 0xffff0000
4412+ and $9, $25, $9
4413+ andi $8, $26, 0xffff
4414+ or $20, $9, $8 // target address
4415+
4416+ jalr $20 // jump, and place the return address in $31
4417+ nop
4418+
4419+__ep0_prog_start2_return:
4420+ // User code can return to here after executing itself, by jumping to $31.
4421+ b usb_boot_return
4422+ nop
4423+
4424+ //--------------------------------------------------------------
4425+ // 2.1.2 Standard setup request
4426+ //--------------------------------------------------------------
4427+_ep0_std_req:
4428+ andi $12, $25, 0xff00 // check bRequest
4429+ srl $12, $12, 8
4430+ sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS
4431+ bnez $9, __ep0_req_set_config
4432+ nop
4433+
4434+ //--------------------------------------------------------------
4435+ // Handle USB_REQ_SET_ADDRESS
4436+ //--------------------------------------------------------------
4437+__ep0_req_set_addr:
4438+ srl $9, $25, 16 // get wValue
4439+ sb $9, 0x0($27) // set FADDR
4440+ li $23, 1 // NoData = 1
4441+ b _ep0_idle_state_fini
4442+ nop
4443+
4444+__ep0_req_set_config:
4445+ sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION
4446+ bnez $9, __ep0_req_get_desc
4447+ nop
4448+
4449+ //--------------------------------------------------------------
4450+ // Handle USB_REQ_SET_CONFIGURATION
4451+ //--------------------------------------------------------------
4452+ li $23, 1 // NoData = 1
4453+ b _ep0_idle_state_fini
4454+ nop
4455+
4456+__ep0_req_get_desc:
4457+ sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR
4458+ bnez $9, _ep0_idle_state_fini
4459+ li $23, 1 // NoData = 1
4460+
4461+ //--------------------------------------------------------------
4462+ // Handle USB_REQ_GET_DESCRIPTOR
4463+ //--------------------------------------------------------------
4464+ li $23, 0 // NoData = 0
4465+
4466+ srl $9, $25, 24 // wValue >> 8
4467+ sub $8, $9, 0x01 // check USB_DT_DEVICE
4468+ beqz $8, ___ep0_get_dev_desc
4469+ srl $21, $26, 16 // get wLength
4470+ sub $8, $9, 0x02 // check USB_DT_CONFIG
4471+ beqz $8, ___ep0_get_conf_desc
4472+ sub $8, $9, 0x03 // check USB_DT_STRING
4473+ beqz $8, ___ep0_get_string_desc
4474+ sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER
4475+ beqz $8, ___ep0_get_dev_qualifier
4476+ nop
4477+ b _ep0_idle_state_fini
4478+ nop
4479+
4480+___ep0_get_dev_desc:
4481+ load_addr $20, device_desc // data pointer
4482+ li $22, 1 // set EP0 to TX state
4483+ sub $8, $21, 18
4484+ blez $8, _ep0_idle_state_fini // wLength <= 18
4485+ nop
4486+ li $21, 18 // max length of device_desc
4487+ b _ep0_idle_state_fini
4488+ nop
4489+
4490+___ep0_get_dev_qualifier:
4491+ load_addr $20, dev_qualifier // data pointer
4492+ li $22, 1 // set EP0 to TX state
4493+ sub $8, $21, 10
4494+ blez $8, _ep0_idle_state_fini // wLength <= 10
4495+ nop
4496+ li $21, 10 // max length of dev_qualifier
4497+ b _ep0_idle_state_fini
4498+ nop
4499+
4500+___ep0_get_conf_desc:
4501+ load_addr $20, config_desc_fs // data pointer of FS mode
4502+ lbu $8, 0x01($27) // read POWER
4503+ andi $8, 0x10 // test HS_MODE
4504+ beqz $8, ___ep0_get_conf_desc2
4505+ nop
4506+ load_addr $20, config_desc_hs // data pointer of HS mode
4507+
4508+___ep0_get_conf_desc2:
4509+ li $22, 1 // set EP0 to TX state
4510+ sub $8, $21, 32
4511+ blez $8, _ep0_idle_state_fini // wLength <= 32
4512+ nop
4513+ li $21, 32 // max length of config_desc
4514+ b _ep0_idle_state_fini
4515+ nop
4516+
4517+___ep0_get_string_desc:
4518+ li $22, 1 // set EP0 to TX state
4519+
4520+ srl $9, $25, 16 // wValue & 0xff
4521+ andi $9, 0xff
4522+
4523+ sub $8, $9, 1
4524+ beqz $8, ___ep0_get_string_manufacture
4525+ sub $8, $9, 2
4526+ beqz $8, ___ep0_get_string_product
4527+ nop
4528+
4529+___ep0_get_string_lang_ids:
4530+ load_addr $20, string_lang_ids // data pointer
4531+ b _ep0_idle_state_fini
4532+ li $21, 4 // data length
4533+
4534+___ep0_get_string_manufacture:
4535+ load_addr $20, string_manufacture // data pointer
4536+ b _ep0_idle_state_fini
4537+ li $21, 16 // data length
4538+
4539+___ep0_get_string_product:
4540+ load_addr $20, string_product // data pointer
4541+ b _ep0_idle_state_fini
4542+ li $21, 46 // data length
4543+
4544+_ep0_idle_state_fini:
4545+ li $9, 0x40 // SVDOUTPKTRDY
4546+ beqz $23, _ep0_idle_state_fini2
4547+ nop
4548+ ori $9, $9, 0x08 // DATAEND
4549+_ep0_idle_state_fini2:
4550+ sb $9, 0x12($27) // CSR0
4551+ beqz $22, check_intr_ep1in
4552+ nop
4553+
4554+ //--------------------------------------------------------------
4555+ // 2.2 Handle EP0 TX state interrupt
4556+ //--------------------------------------------------------------
4557+ep0_tx_state:
4558+ sub $9, $22, 1
4559+ bnez $9, check_intr_ep1in
4560+ nop
4561+
4562+ sub $9, $21, 64 // max packetsize
4563+ blez $9, _ep0_tx_state2 // data count <= 64
4564+ ori $19, $21, 0
4565+ li $19, 64
4566+
4567+_ep0_tx_state2:
4568+ beqz $19, _ep0_tx_state3 // send ZLP
4569+ ori $18, $19, 0 // record bytes to be transferred
4570+ sub $21, $21, $19 // decrement data count
4571+
4572+_ep0_fifo_write_loop:
4573+ lbu $9, 0($20) // read data
4574+ sb $9, 0x20($27) // load FIFO
4575+ sub $19, $19, 1 // decrement counter
4576+ bnez $19, _ep0_fifo_write_loop
4577+ addi $20, $20, 1 // increment data pointer
4578+
4579+ sub $9, $18, 64 // max packetsize
4580+ beqz $9, _ep0_tx_state4
4581+ nop
4582+
4583+_ep0_tx_state3:
4584+ // transferred bytes < max packetsize
4585+ li $9, 0x0a // set INPKTRDY and DATAEND
4586+ sb $9, 0x12($27) // CSR0
4587+ li $22, 0 // set EP0 to IDLE state
4588+ b check_intr_ep1in
4589+ nop
4590+
4591+_ep0_tx_state4:
4592+ // transferred bytes == max packetsize
4593+ li $9, 0x02 // set INPKTRDY
4594+ sb $9, 0x12($27) // CSR0
4595+ b check_intr_ep1in
4596+ nop
4597+
4598+ //--------------------------------------------------------------
4599+ // 3. Check and handle EP1 BULK-IN interrupt
4600+ //--------------------------------------------------------------
4601+check_intr_ep1in:
4602+ andi $9, $10, 0x2 // check EP1 IN interrupt
4603+ beqz $9, check_intr_ep1out
4604+ nop
4605+
4606+handle_epin1_intr:
4607+ li $9, 1
4608+ sb $9, 0x0e($27) // set INDEX 1
4609+ lbu $9, 0x12($27) // read INCSR
4610+
4611+ andi $8, $9, 0x2 // check INCSR_FFNOTEMPT
4612+ bnez $8, _epin1_tx_state4
4613+ nop
4614+
4615+_epin1_write_fifo:
4616+ lhu $9, 0x10($27) // get INMAXP
4617+ sub $8, $21, $9
4618+ blez $8, _epin1_tx_state1 // bytes left <= INMAXP
4619+ ori $19, $21, 0
4620+ ori $19, $9, 0
4621+
4622+_epin1_tx_state1:
4623+ beqz $19, _epin1_tx_state4 // No data
4624+ nop
4625+
4626+ sub $21, $21, $19 // decrement data count
4627+
4628+ srl $5, $19, 2 // # of word
4629+ andi $6, $19, 0x3 // # of byte
4630+ beqz $5, _epin1_tx_state2
4631+ nop
4632+
4633+_epin1_fifo_write_word:
4634+ lw $9, 0($20) // read data from source address
4635+ sw $9, 0x24($27) // write FIFO
4636+ sub $5, $5, 1 // decrement counter
4637+ bnez $5, _epin1_fifo_write_word
4638+ addiu $20, $20, 4 // increment dest address
4639+
4640+_epin1_tx_state2:
4641+ beqz $6, _epin1_tx_state3
4642+ nop
4643+
4644+_epin1_fifo_write_byte:
4645+ lbu $9, 0($20) // read data from source address
4646+ sb $9, 0x24($27) // write FIFO
4647+ sub $6, $6, 1 // decrement counter
4648+ bnez $6, _epin1_fifo_write_byte
4649+ addiu $20, $20, 1 // increment dest address
4650+
4651+_epin1_tx_state3:
4652+ li $9, 0x1
4653+ sb $9, 0x12($27) // INCSR, set INPKTRDY
4654+
4655+_epin1_tx_state4:
4656+ // nop
4657+
4658+ //--------------------------------------------------------------
4659+ // 4. Check and handle EP1 BULK-OUT interrupt
4660+ //--------------------------------------------------------------
4661+check_intr_ep1out:
4662+ lhu $9, 0x04($27) // read INTROUT
4663+ andi $9, 0x2
4664+ beqz $9, check_status_next
4665+ nop
4666+
4667+handle_epout1_intr:
4668+ li $9, 1
4669+ sb $9, 0x0e($27) // set INDEX 1
4670+
4671+ lbu $9, 0x16($27) // read OUTCSR
4672+ andi $9, 0x1 // check OUTPKTRDY
4673+ beqz $9, check_status_next
4674+ nop
4675+
4676+_epout1_read_fifo:
4677+ lhu $19, 0x18($27) // read OUTCOUNT
4678+ srl $5, $19, 2 // # of word
4679+ andi $6, $19, 0x3 // # of byte
4680+ beqz $5, _epout1_rx_state1
4681+ nop
4682+
4683+_epout1_fifo_read_word:
4684+ lw $9, 0x24($27) // read FIFO
4685+ sw $9, 0($20) // store to dest address
4686+ sub $5, $5, 1 // decrement counter
4687+ bnez $5, _epout1_fifo_read_word
4688+ addiu $20, $20, 4 // increment dest address
4689+
4690+_epout1_rx_state1:
4691+ beqz $6, _epout1_rx_state2
4692+ nop
4693+
4694+_epout1_fifo_read_byte:
4695+ lbu $9, 0x24($27) // read FIFO
4696+ sb $9, 0($20) // store to dest address
4697+ sub $6, $6, 1 // decrement counter
4698+ bnez $6, _epout1_fifo_read_byte
4699+ addiu $20, $20, 1 // increment dest address
4700+
4701+_epout1_rx_state2:
4702+ sb $0, 0x16($27) // clear OUTPKTRDY
4703+
4704+check_status_next:
4705+ b usb_command_loop
4706+ nop
4707+
4708+//--------------------------------------------------------------
4709+// Device/Configuration/Interface/Endpoint/String Descriptors
4710+//--------------------------------------------------------------
4711+
4712+ .align 2
4713+device_desc:
4714+ .byte 0x12 // bLength
4715+ .byte 0x01 // bDescriptorType
4716+ .byte 0x00 // bcdUSB
4717+ .byte 0x02 // bcdUSB
4718+ .byte 0x00 // bDeviceClass
4719+ .byte 0x00 // bDeviceSubClass
4720+ .byte 0x00 // bDeviceProtocol
4721+ .byte 0x40 // bMaxPacketSize0
4722+ .byte 0x1a // idVendor
4723+ .byte 0x60 // idVendor
4724+ .byte 0x40 // idProduct
4725+ .byte 0x47 // idProduct
4726+ .byte 0x00 // bcdDevice
4727+ .byte 0x01 // bcdDevice
4728+ .byte 0x01 // iManufacturer
4729+ .byte 0x02 // iProduct
4730+ .byte 0x00 // iSerialNumber
4731+ .byte 0x01 // bNumConfigurations
4732+
4733+ .align 2
4734+dev_qualifier:
4735+ .byte 0x0a // bLength
4736+ .byte 0x06 // bDescriptorType
4737+ .byte 0x00 // bcdUSB
4738+ .byte 0x02 // bcdUSB
4739+ .byte 0x00 // bDeviceClass
4740+ .byte 0x00 // bDeviceSubClass
4741+ .byte 0x00 // bDeviceProtocol
4742+ .byte 0x40 // bMaxPacketSize0
4743+ .byte 0x01 // bNumConfigurations
4744+ .byte 0x00 // bRESERVED
4745+
4746+ .align 2
4747+config_desc_hs:
4748+ .byte 0x09 // bLength
4749+ .byte 0x02 // bDescriptorType
4750+ .byte 0x20 // wTotalLength
4751+ .byte 0x00 // wTotalLength
4752+ .byte 0x01 // bNumInterfaces
4753+ .byte 0x01 // bConfigurationValue
4754+ .byte 0x00 // iConfiguration
4755+ .byte 0xc0 // bmAttributes
4756+ .byte 0x01 // MaxPower
4757+intf_desc_hs:
4758+ .byte 0x09 // bLength
4759+ .byte 0x04 // bDescriptorType
4760+ .byte 0x00 // bInterfaceNumber
4761+ .byte 0x00 // bAlternateSetting
4762+ .byte 0x02 // bNumEndpoints
4763+ .byte 0xff // bInterfaceClass
4764+ .byte 0x00 // bInterfaceSubClass
4765+ .byte 0x50 // bInterfaceProtocol
4766+ .byte 0x00 // iInterface
4767+ep1_desc_hs:
4768+ .byte 0x07 // bLength
4769+ .byte 0x05 // bDescriptorType
4770+ .byte 0x01 // bEndpointAddress
4771+ .byte 0x02 // bmAttributes
4772+ .byte 0x00 // wMaxPacketSize
4773+ .byte 0x02 // wMaxPacketSize
4774+ .byte 0x00 // bInterval
4775+ep2_desc_hs:
4776+ .byte 0x07 // bLength
4777+ .byte 0x05 // bDescriptorType
4778+ .byte 0x81 // bEndpointAddress
4779+ .byte 0x02 // bmAttributes
4780+ .byte 0x00 // wMaxPacketSize
4781+ .byte 0x02 // wMaxPacketSize
4782+ .byte 0x00 // bInterval
4783+
4784+ .align 2
4785+config_desc_fs:
4786+ .byte 0x09 // bLength
4787+ .byte 0x02 // bDescriptorType
4788+ .byte 0x20 // wTotalLength
4789+ .byte 0x00 // wTotalLength
4790+ .byte 0x01 // bNumInterfaces
4791+ .byte 0x01 // bConfigurationValue
4792+ .byte 0x00 // iConfiguration
4793+ .byte 0xc0 // bmAttributes
4794+ .byte 0x01 // MaxPower
4795+intf_desc_fs:
4796+ .byte 0x09 // bLength
4797+ .byte 0x04 // bDescriptorType
4798+ .byte 0x00 // bInterfaceNumber
4799+ .byte 0x00 // bAlternateSetting
4800+ .byte 0x02 // bNumEndpoints
4801+ .byte 0xff // bInterfaceClass
4802+ .byte 0x00 // bInterfaceSubClass
4803+ .byte 0x50 // bInterfaceProtocol
4804+ .byte 0x00 // iInterface
4805+ep1_desc_fs:
4806+ .byte 0x07 // bLength
4807+ .byte 0x05 // bDescriptorType
4808+ .byte 0x01 // bEndpointAddress
4809+ .byte 0x02 // bmAttributes
4810+ .byte 0x40 // wMaxPacketSize
4811+ .byte 0x00 // wMaxPacketSize
4812+ .byte 0x00 // bInterval
4813+ep2_desc_fs:
4814+ .byte 0x07 // bLength
4815+ .byte 0x05 // bDescriptorType
4816+ .byte 0x81 // bEndpointAddress
4817+ .byte 0x02 // bmAttributes
4818+ .byte 0x40 // wMaxPacketSize
4819+ .byte 0x00 // wMaxPacketSize
4820+ .byte 0x00 // bInterval
4821+
4822+ .align 2
4823+string_lang_ids:
4824+ .byte 0x04
4825+ .byte 0x03
4826+ .byte 0x09
4827+ .byte 0x04
4828+
4829+ .align 2
4830+string_manufacture:
4831+ .byte 0x10
4832+ .byte 0x03
4833+ .byte 0x49
4834+ .byte 0x00
4835+ .byte 0x6e
4836+ .byte 0x00
4837+ .byte 0x67
4838+ .byte 0x00
4839+ .byte 0x65
4840+ .byte 0x00
4841+ .byte 0x6e
4842+ .byte 0x00
4843+ .byte 0x69
4844+ .byte 0x00
4845+ .byte 0x63
4846+ .byte 0x00
4847+
4848+ .align 2
4849+string_product:
4850+ .byte 0x2e
4851+ .byte 0x03
4852+ .byte 0x4a
4853+ .byte 0x00
4854+ .byte 0x5a
4855+ .byte 0x00
4856+ .byte 0x34
4857+ .byte 0x00
4858+ .byte 0x37
4859+ .byte 0x00
4860+ .byte 0x34
4861+ .byte 0x00
4862+ .byte 0x30
4863+ .byte 0x00
4864+ .byte 0x20
4865+ .byte 0x00
4866+ .byte 0x55
4867+ .byte 0x00
4868+ .byte 0x53
4869+ .byte 0x00
4870+ .byte 0x42
4871+ .byte 0x00
4872+ .byte 0x20
4873+ .byte 0x00
4874+ .byte 0x42
4875+ .byte 0x00
4876+ .byte 0x6f
4877+ .byte 0x00
4878+ .byte 0x6f
4879+ .byte 0x00
4880+ .byte 0x74
4881+ .byte 0x00
4882+ .byte 0x20
4883+ .byte 0x00
4884+ .byte 0x44
4885+ .byte 0x00
4886+ .byte 0x65
4887+ .byte 0x00
4888+ .byte 0x76
4889+ .byte 0x00
4890+ .byte 0x69
4891+ .byte 0x00
4892+ .byte 0x63
4893+ .byte 0x00
4894+ .byte 0x65
4895+ .byte 0x00
4896+
4897+ .align 2
4898+cpu_info_data:
4899+ .byte 0x4a
4900+ .byte 0x5a
4901+ .byte 0x34
4902+ .byte 0x37
4903+ .byte 0x34
4904+ .byte 0x30
4905+ .byte 0x56
4906+ .byte 0x31
4907+usbboot_end:
4908+
4909+ .set reorder
4910diff --git a/include/asm-mips/jz4740.h b/include/asm-mips/jz4740.h
4911new file mode 100644
4912index 0000000..2840bc0
4913+++ b/include/asm-mips/jz4740.h
4914@@ -0,0 +1,4880 @@
4915+/*
4916+ * Include file for Ingenic Semiconductor's JZ4740 CPU.
4917+ */
4918+#ifndef __JZ4740_H__
4919+#define __JZ4740_H__
4920+
4921+#ifndef __ASSEMBLY__
4922+#define UCOS_CSP 0
4923+
4924+#if UCOS_CSP
4925+#define __KERNEL__
4926+#include <bsp.h>
4927+#include <types.h>
4928+
4929+#include <sysdefs.h>
4930+#include <cacheops.h>
4931+#define KSEG0 KSEG0BASE
4932+#else
4933+#include <asm/addrspace.h>
4934+#include <asm/cacheops.h>
4935+#endif
4936+
4937+#define cache_unroll(base,op) \
4938+ __asm__ __volatile__(" \
4939+ .set noreorder; \
4940+ .set mips3; \
4941+ cache %1, (%0); \
4942+ .set mips0; \
4943+ .set reorder" \
4944+ : \
4945+ : "r" (base), \
4946+ "i" (op));
4947+
4948+static inline void jz_flush_dcache(void)
4949+{
4950+ unsigned long start;
4951+ unsigned long end;
4952+
4953+ start = KSEG0;
4954+ end = start + CONFIG_SYS_DCACHE_SIZE;
4955+ while (start < end) {
4956+ cache_unroll(start,Index_Writeback_Inv_D);
4957+ start += CONFIG_SYS_CACHELINE_SIZE;
4958+ }
4959+}
4960+
4961+static inline void jz_flush_icache(void)
4962+{
4963+ unsigned long start;
4964+ unsigned long end;
4965+
4966+ start = KSEG0;
4967+ end = start + CONFIG_SYS_ICACHE_SIZE;
4968+ while(start < end) {
4969+ cache_unroll(start,Index_Invalidate_I);
4970+ start += CONFIG_SYS_CACHELINE_SIZE;
4971+ }
4972+}
4973+
4974+/* cpu pipeline flush */
4975+static inline void jz_sync(void)
4976+{
4977+ __asm__ volatile ("sync");
4978+}
4979+
4980+static inline void jz_writeb(u32 address, u8 value)
4981+{
4982+ *((volatile u8 *)address) = value;
4983+}
4984+
4985+static inline void jz_writew(u32 address, u16 value)
4986+{
4987+ *((volatile u16 *)address) = value;
4988+}
4989+
4990+static inline void jz_writel(u32 address, u32 value)
4991+{
4992+ *((volatile u32 *)address) = value;
4993+}
4994+
4995+static inline u8 jz_readb(u32 address)
4996+{
4997+ return *((volatile u8 *)address);
4998+}
4999+
5000+static inline u16 jz_readw(u32 address)
5001+{
5002+ return *((volatile u16 *)address);
5003+}
5004+
5005+static inline u32 jz_readl(u32 address)
5006+{
5007+ return *((volatile u32 *)address);
5008+}
5009+
5010+#define REG8(addr) *((volatile u8 *)(addr))
5011+#define REG16(addr) *((volatile u16 *)(addr))
5012+#define REG32(addr) *((volatile u32 *)(addr))
5013+
5014+#else
5015+
5016+#define REG8(addr) (addr)
5017+#define REG16(addr) (addr)
5018+#define REG32(addr) (addr)
5019+
5020+#endif /* !ASSEMBLY */
5021+
5022+/* Boot ROM Specification */
5023+/* NOR Boot config */
5024+#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
5025+#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
5026+#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
5027+
5028+/* NAND Boot config */
5029+#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
5030+#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
5031+#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
5032+#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
5033+
5034+
5035+/* Register Definitions */
5036+#define CPM_BASE 0xB0000000
5037+#define INTC_BASE 0xB0001000
5038+#define TCU_BASE 0xB0002000
5039+#define WDT_BASE 0xB0002000
5040+#define RTC_BASE 0xB0003000
5041+#define GPIO_BASE 0xB0010000
5042+#define AIC_BASE 0xB0020000
5043+#define ICDC_BASE 0xB0020000
5044+#define MSC_BASE 0xB0021000
5045+#define UART0_BASE 0xB0030000
5046+#define I2C_BASE 0xB0042000
5047+#define SSI_BASE 0xB0043000
5048+#define SADC_BASE 0xB0070000
5049+#define EMC_BASE 0xB3010000
5050+#define DMAC_BASE 0xB3020000
5051+#define UHC_BASE 0xB3030000
5052+#define UDC_BASE 0xB3040000
5053+#define LCD_BASE 0xB3050000
5054+#define SLCD_BASE 0xB3050000
5055+#define CIM_BASE 0xB3060000
5056+#define ETH_BASE 0xB3100000
5057+
5058+
5059+/*
5060+ * INTC (Interrupt Controller)
5061+ */
5062+#define INTC_ISR (INTC_BASE + 0x00)
5063+#define INTC_IMR (INTC_BASE + 0x04)
5064+#define INTC_IMSR (INTC_BASE + 0x08)
5065+#define INTC_IMCR (INTC_BASE + 0x0c)
5066+#define INTC_IPR (INTC_BASE + 0x10)
5067+
5068+#define REG_INTC_ISR REG32(INTC_ISR)
5069+#define REG_INTC_IMR REG32(INTC_IMR)
5070+#define REG_INTC_IMSR REG32(INTC_IMSR)
5071+#define REG_INTC_IMCR REG32(INTC_IMCR)
5072+#define REG_INTC_IPR REG32(INTC_IPR)
5073+
5074+/* 1st-level interrupts */
5075+#define IRQ_I2C 1
5076+#define IRQ_UHC 3
5077+#define IRQ_UART0 9
5078+#define IRQ_SADC 12
5079+#define IRQ_MSC 14
5080+#define IRQ_RTC 15
5081+#define IRQ_SSI 16
5082+#define IRQ_CIM 17
5083+#define IRQ_AIC 18
5084+#define IRQ_ETH 19
5085+#define IRQ_DMAC 20
5086+#define IRQ_TCU2 21
5087+#define IRQ_TCU1 22
5088+#define IRQ_TCU0 23
5089+#define IRQ_UDC 24
5090+#define IRQ_GPIO3 25
5091+#define IRQ_GPIO2 26
5092+#define IRQ_GPIO1 27
5093+#define IRQ_GPIO0 28
5094+#define IRQ_IPU 29
5095+#define IRQ_LCD 30
5096+
5097+/* 2nd-level interrupts */
5098+#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
5099+#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
5100+
5101+
5102+/*
5103+ * RTC
5104+ */
5105+#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
5106+#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
5107+#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
5108+#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
5109+
5110+#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
5111+#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
5112+#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
5113+#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
5114+#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
5115+#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
5116+
5117+#define REG_RTC_RCR REG32(RTC_RCR)
5118+#define REG_RTC_RSR REG32(RTC_RSR)
5119+#define REG_RTC_RSAR REG32(RTC_RSAR)
5120+#define REG_RTC_RGR REG32(RTC_RGR)
5121+#define REG_RTC_HCR REG32(RTC_HCR)
5122+#define REG_RTC_HWFCR REG32(RTC_HWFCR)
5123+#define REG_RTC_HRCR REG32(RTC_HRCR)
5124+#define REG_RTC_HWCR REG32(RTC_HWCR)
5125+#define REG_RTC_HWRSR REG32(RTC_HWRSR)
5126+#define REG_RTC_HSPR REG32(RTC_HSPR)
5127+
5128+/* RTC Control Register */
5129+#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
5130+#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
5131+#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
5132+#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
5133+#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
5134+#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
5135+#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
5136+
5137+/* RTC Regulator Register */
5138+#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
5139+#define RTC_RGR_ADJC_BIT 16
5140+#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
5141+#define RTC_RGR_NC1HZ_BIT 0
5142+#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
5143+
5144+/* Hibernate Control Register */
5145+#define RTC_HCR_PD (1 << 0) /* Power Down */
5146+
5147+/* Hibernate Wakeup Filter Counter Register */
5148+#define RTC_HWFCR_BIT 5
5149+#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
5150+
5151+/* Hibernate Reset Counter Register */
5152+#define RTC_HRCR_BIT 5
5153+#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
5154+
5155+/* Hibernate Wakeup Control Register */
5156+#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
5157+
5158+/* Hibernate Wakeup Status Register */
5159+#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
5160+#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
5161+#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
5162+#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
5163+
5164+
5165+/*************************************************************************
5166+ * CPM (Clock reset and Power control Management)
5167+ *************************************************************************/
5168+#define CPM_CPCCR (CPM_BASE+0x00)
5169+#define CPM_CPPCR (CPM_BASE+0x10)
5170+#define CPM_I2SCDR (CPM_BASE+0x60)
5171+#define CPM_LPCDR (CPM_BASE+0x64)
5172+#define CPM_MSCCDR (CPM_BASE+0x68)
5173+#define CPM_UHCCDR (CPM_BASE+0x6C)
5174+
5175+#define CPM_LCR (CPM_BASE+0x04)
5176+#define CPM_CLKGR (CPM_BASE+0x20)
5177+#define CPM_SCR (CPM_BASE+0x24)
5178+
5179+#define CPM_HCR (CPM_BASE+0x30)
5180+#define CPM_HWFCR (CPM_BASE+0x34)
5181+#define CPM_HRCR (CPM_BASE+0x38)
5182+#define CPM_HWCR (CPM_BASE+0x3c)
5183+#define CPM_HWSR (CPM_BASE+0x40)
5184+#define CPM_HSPR (CPM_BASE+0x44)
5185+
5186+#define CPM_RSR (CPM_BASE+0x08)
5187+
5188+
5189+#define REG_CPM_CPCCR REG32(CPM_CPCCR)
5190+#define REG_CPM_CPPCR REG32(CPM_CPPCR)
5191+#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
5192+#define REG_CPM_LPCDR REG32(CPM_LPCDR)
5193+#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
5194+#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
5195+
5196+#define REG_CPM_LCR REG32(CPM_LCR)
5197+#define REG_CPM_CLKGR REG32(CPM_CLKGR)
5198+#define REG_CPM_SCR REG32(CPM_SCR)
5199+#define REG_CPM_HCR REG32(CPM_HCR)
5200+#define REG_CPM_HWFCR REG32(CPM_HWFCR)
5201+#define REG_CPM_HRCR REG32(CPM_HRCR)
5202+#define REG_CPM_HWCR REG32(CPM_HWCR)
5203+#define REG_CPM_HWSR REG32(CPM_HWSR)
5204+#define REG_CPM_HSPR REG32(CPM_HSPR)
5205+
5206+#define REG_CPM_RSR REG32(CPM_RSR)
5207+
5208+
5209+/* Clock Control Register */
5210+#define CPM_CPCCR_I2CS (1 << 31)
5211+#define CPM_CPCCR_CLKOEN (1 << 30)
5212+#define CPM_CPCCR_UCS (1 << 29)
5213+#define CPM_CPCCR_UDIV_BIT 23
5214+#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
5215+#define CPM_CPCCR_CE (1 << 22)
5216+#define CPM_CPCCR_PCS (1 << 21)
5217+#define CPM_CPCCR_LDIV_BIT 16
5218+#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
5219+#define CPM_CPCCR_MDIV_BIT 12
5220+#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
5221+#define CPM_CPCCR_PDIV_BIT 8
5222+#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
5223+#define CPM_CPCCR_HDIV_BIT 4
5224+#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
5225+#define CPM_CPCCR_CDIV_BIT 0
5226+#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
5227+
5228+/* I2S Clock Divider Register */
5229+#define CPM_I2SCDR_I2SDIV_BIT 0
5230+#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
5231+
5232+/* LCD Pixel Clock Divider Register */
5233+#define CPM_LPCDR_PIXDIV_BIT 0
5234+#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
5235+
5236+/* MSC Clock Divider Register */
5237+#define CPM_MSCCDR_MSCDIV_BIT 0
5238+#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
5239+
5240+/* PLL Control Register */
5241+#define CPM_CPPCR_PLLM_BIT 23
5242+#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
5243+#define CPM_CPPCR_PLLN_BIT 18
5244+#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
5245+#define CPM_CPPCR_PLLOD_BIT 16
5246+#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
5247+#define CPM_CPPCR_PLLS (1 << 10)
5248+#define CPM_CPPCR_PLLBP (1 << 9)
5249+#define CPM_CPPCR_PLLEN (1 << 8)
5250+#define CPM_CPPCR_PLLST_BIT 0
5251+#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
5252+
5253+/* Low Power Control Register */
5254+#define CPM_LCR_DOZE_DUTY_BIT 3
5255+#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
5256+#define CPM_LCR_DOZE_ON (1 << 2)
5257+#define CPM_LCR_LPM_BIT 0
5258+#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
5259+ #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
5260+ #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
5261+
5262+/* Clock Gate Register */
5263+#define CPM_CLKGR_UART1 (1 << 15)
5264+#define CPM_CLKGR_UHC (1 << 14)
5265+#define CPM_CLKGR_IPU (1 << 13)
5266+#define CPM_CLKGR_DMAC (1 << 12)
5267+#define CPM_CLKGR_UDC (1 << 11)
5268+#define CPM_CLKGR_LCD (1 << 10)
5269+#define CPM_CLKGR_CIM (1 << 9)
5270+#define CPM_CLKGR_SADC (1 << 8)
5271+#define CPM_CLKGR_MSC (1 << 7)
5272+#define CPM_CLKGR_AIC1 (1 << 6)
5273+#define CPM_CLKGR_AIC2 (1 << 5)
5274+#define CPM_CLKGR_SSI (1 << 4)
5275+#define CPM_CLKGR_I2C (1 << 3)
5276+#define CPM_CLKGR_RTC (1 << 2)
5277+#define CPM_CLKGR_TCU (1 << 1)
5278+#define CPM_CLKGR_UART0 (1 << 0)
5279+
5280+/* Sleep Control Register */
5281+#define CPM_SCR_O1ST_BIT 8
5282+#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
5283+#define CPM_SCR_USBPHY_ENABLE (1 << 6)
5284+#define CPM_SCR_OSC_ENABLE (1 << 4)
5285+
5286+/* Hibernate Control Register */
5287+#define CPM_HCR_PD (1 << 0)
5288+
5289+/* Wakeup Filter Counter Register in Hibernate Mode */
5290+#define CPM_HWFCR_TIME_BIT 0
5291+#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
5292+
5293+/* Reset Counter Register in Hibernate Mode */
5294+#define CPM_HRCR_TIME_BIT 0
5295+#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
5296+
5297+/* Wakeup Control Register in Hibernate Mode */
5298+#define CPM_HWCR_WLE_LOW (0 << 2)
5299+#define CPM_HWCR_WLE_HIGH (1 << 2)
5300+#define CPM_HWCR_PIN_WAKEUP (1 << 1)
5301+#define CPM_HWCR_RTC_WAKEUP (1 << 0)
5302+
5303+/* Wakeup Status Register in Hibernate Mode */
5304+#define CPM_HWSR_WSR_PIN (1 << 1)
5305+#define CPM_HWSR_WSR_RTC (1 << 0)
5306+
5307+/* Reset Status Register */
5308+#define CPM_RSR_HR (1 << 2)
5309+#define CPM_RSR_WR (1 << 1)
5310+#define CPM_RSR_PR (1 << 0)
5311+
5312+
5313+/*************************************************************************
5314+ * TCU (Timer Counter Unit)
5315+ *************************************************************************/
5316+#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
5317+#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
5318+#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
5319+#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
5320+#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
5321+#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
5322+#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
5323+#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
5324+#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
5325+#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
5326+#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
5327+#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
5328+#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
5329+#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
5330+#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
5331+#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
5332+#define TCU_TDFR1 (TCU_BASE + 0x50)
5333+#define TCU_TDHR1 (TCU_BASE + 0x54)
5334+#define TCU_TCNT1 (TCU_BASE + 0x58)
5335+#define TCU_TCSR1 (TCU_BASE + 0x5C)
5336+#define TCU_TDFR2 (TCU_BASE + 0x60)
5337+#define TCU_TDHR2 (TCU_BASE + 0x64)
5338+#define TCU_TCNT2 (TCU_BASE + 0x68)
5339+#define TCU_TCSR2 (TCU_BASE + 0x6C)
5340+#define TCU_TDFR3 (TCU_BASE + 0x70)
5341+#define TCU_TDHR3 (TCU_BASE + 0x74)
5342+#define TCU_TCNT3 (TCU_BASE + 0x78)
5343+#define TCU_TCSR3 (TCU_BASE + 0x7C)
5344+#define TCU_TDFR4 (TCU_BASE + 0x80)
5345+#define TCU_TDHR4 (TCU_BASE + 0x84)
5346+#define TCU_TCNT4 (TCU_BASE + 0x88)
5347+#define TCU_TCSR4 (TCU_BASE + 0x8C)
5348+#define TCU_TDFR5 (TCU_BASE + 0x90)
5349+#define TCU_TDHR5 (TCU_BASE + 0x94)
5350+#define TCU_TCNT5 (TCU_BASE + 0x98)
5351+#define TCU_TCSR5 (TCU_BASE + 0x9C)
5352+
5353+#define REG_TCU_TSR REG32(TCU_TSR)
5354+#define REG_TCU_TSSR REG32(TCU_TSSR)
5355+#define REG_TCU_TSCR REG32(TCU_TSCR)
5356+#define REG_TCU_TER REG8(TCU_TER)
5357+#define REG_TCU_TESR REG8(TCU_TESR)
5358+#define REG_TCU_TECR REG8(TCU_TECR)
5359+#define REG_TCU_TFR REG32(TCU_TFR)
5360+#define REG_TCU_TFSR REG32(TCU_TFSR)
5361+#define REG_TCU_TFCR REG32(TCU_TFCR)
5362+#define REG_TCU_TMR REG32(TCU_TMR)
5363+#define REG_TCU_TMSR REG32(TCU_TMSR)
5364+#define REG_TCU_TMCR REG32(TCU_TMCR)
5365+#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
5366+#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
5367+#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
5368+#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
5369+#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
5370+#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
5371+#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
5372+#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
5373+#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
5374+#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
5375+#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
5376+#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
5377+#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
5378+#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
5379+#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
5380+#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
5381+#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
5382+#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
5383+#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
5384+#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
5385+
5386+/* n = 0,1,2,3,4,5 */
5387+#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
5388+#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
5389+#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
5390+#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
5391+
5392+#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
5393+#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
5394+#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
5395+#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
5396+
5397+/* Register definitions */
5398+#define TCU_TCSR_PWM_SD (1 << 9)
5399+#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
5400+#define TCU_TCSR_PWM_EN (1 << 7)
5401+#define TCU_TCSR_PRESCALE_BIT 3
5402+#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
5403+#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
5404+#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
5405+#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
5406+#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
5407+#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
5408+#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
5409+#define TCU_TCSR_EXT_EN (1 << 2)
5410+#define TCU_TCSR_RTC_EN (1 << 1)
5411+#define TCU_TCSR_PCK_EN (1 << 0)
5412+
5413+#define TCU_TER_TCEN5 (1 << 5)
5414+#define TCU_TER_TCEN4 (1 << 4)
5415+#define TCU_TER_TCEN3 (1 << 3)
5416+#define TCU_TER_TCEN2 (1 << 2)
5417+#define TCU_TER_TCEN1 (1 << 1)
5418+#define TCU_TER_TCEN0 (1 << 0)
5419+
5420+#define TCU_TESR_TCST5 (1 << 5)
5421+#define TCU_TESR_TCST4 (1 << 4)
5422+#define TCU_TESR_TCST3 (1 << 3)
5423+#define TCU_TESR_TCST2 (1 << 2)
5424+#define TCU_TESR_TCST1 (1 << 1)
5425+#define TCU_TESR_TCST0 (1 << 0)
5426+
5427+#define TCU_TECR_TCCL5 (1 << 5)
5428+#define TCU_TECR_TCCL4 (1 << 4)
5429+#define TCU_TECR_TCCL3 (1 << 3)
5430+#define TCU_TECR_TCCL2 (1 << 2)
5431+#define TCU_TECR_TCCL1 (1 << 1)
5432+#define TCU_TECR_TCCL0 (1 << 0)
5433+
5434+#define TCU_TFR_HFLAG5 (1 << 21)
5435+#define TCU_TFR_HFLAG4 (1 << 20)
5436+#define TCU_TFR_HFLAG3 (1 << 19)
5437+#define TCU_TFR_HFLAG2 (1 << 18)
5438+#define TCU_TFR_HFLAG1 (1 << 17)
5439+#define TCU_TFR_HFLAG0 (1 << 16)
5440+#define TCU_TFR_FFLAG5 (1 << 5)
5441+#define TCU_TFR_FFLAG4 (1 << 4)
5442+#define TCU_TFR_FFLAG3 (1 << 3)
5443+#define TCU_TFR_FFLAG2 (1 << 2)
5444+#define TCU_TFR_FFLAG1 (1 << 1)
5445+#define TCU_TFR_FFLAG0 (1 << 0)
5446+
5447+#define TCU_TFSR_HFLAG5 (1 << 21)
5448+#define TCU_TFSR_HFLAG4 (1 << 20)
5449+#define TCU_TFSR_HFLAG3 (1 << 19)
5450+#define TCU_TFSR_HFLAG2 (1 << 18)
5451+#define TCU_TFSR_HFLAG1 (1 << 17)
5452+#define TCU_TFSR_HFLAG0 (1 << 16)
5453+#define TCU_TFSR_FFLAG5 (1 << 5)
5454+#define TCU_TFSR_FFLAG4 (1 << 4)
5455+#define TCU_TFSR_FFLAG3 (1 << 3)
5456+#define TCU_TFSR_FFLAG2 (1 << 2)
5457+#define TCU_TFSR_FFLAG1 (1 << 1)
5458+#define TCU_TFSR_FFLAG0 (1 << 0)
5459+
5460+#define TCU_TFCR_HFLAG5 (1 << 21)
5461+#define TCU_TFCR_HFLAG4 (1 << 20)
5462+#define TCU_TFCR_HFLAG3 (1 << 19)
5463+#define TCU_TFCR_HFLAG2 (1 << 18)
5464+#define TCU_TFCR_HFLAG1 (1 << 17)
5465+#define TCU_TFCR_HFLAG0 (1 << 16)
5466+#define TCU_TFCR_FFLAG5 (1 << 5)
5467+#define TCU_TFCR_FFLAG4 (1 << 4)
5468+#define TCU_TFCR_FFLAG3 (1 << 3)
5469+#define TCU_TFCR_FFLAG2 (1 << 2)
5470+#define TCU_TFCR_FFLAG1 (1 << 1)
5471+#define TCU_TFCR_FFLAG0 (1 << 0)
5472+
5473+#define TCU_TMR_HMASK5 (1 << 21)
5474+#define TCU_TMR_HMASK4 (1 << 20)
5475+#define TCU_TMR_HMASK3 (1 << 19)
5476+#define TCU_TMR_HMASK2 (1 << 18)
5477+#define TCU_TMR_HMASK1 (1 << 17)
5478+#define TCU_TMR_HMASK0 (1 << 16)
5479+#define TCU_TMR_FMASK5 (1 << 5)
5480+#define TCU_TMR_FMASK4 (1 << 4)
5481+#define TCU_TMR_FMASK3 (1 << 3)
5482+#define TCU_TMR_FMASK2 (1 << 2)
5483+#define TCU_TMR_FMASK1 (1 << 1)
5484+#define TCU_TMR_FMASK0 (1 << 0)
5485+
5486+#define TCU_TMSR_HMST5 (1 << 21)
5487+#define TCU_TMSR_HMST4 (1 << 20)
5488+#define TCU_TMSR_HMST3 (1 << 19)
5489+#define TCU_TMSR_HMST2 (1 << 18)
5490+#define TCU_TMSR_HMST1 (1 << 17)
5491+#define TCU_TMSR_HMST0 (1 << 16)
5492+#define TCU_TMSR_FMST5 (1 << 5)
5493+#define TCU_TMSR_FMST4 (1 << 4)
5494+#define TCU_TMSR_FMST3 (1 << 3)
5495+#define TCU_TMSR_FMST2 (1 << 2)
5496+#define TCU_TMSR_FMST1 (1 << 1)
5497+#define TCU_TMSR_FMST0 (1 << 0)
5498+
5499+#define TCU_TMCR_HMCL5 (1 << 21)
5500+#define TCU_TMCR_HMCL4 (1 << 20)
5501+#define TCU_TMCR_HMCL3 (1 << 19)
5502+#define TCU_TMCR_HMCL2 (1 << 18)
5503+#define TCU_TMCR_HMCL1 (1 << 17)
5504+#define TCU_TMCR_HMCL0 (1 << 16)
5505+#define TCU_TMCR_FMCL5 (1 << 5)
5506+#define TCU_TMCR_FMCL4 (1 << 4)
5507+#define TCU_TMCR_FMCL3 (1 << 3)
5508+#define TCU_TMCR_FMCL2 (1 << 2)
5509+#define TCU_TMCR_FMCL1 (1 << 1)
5510+#define TCU_TMCR_FMCL0 (1 << 0)
5511+
5512+#define TCU_TSR_WDTS (1 << 16)
5513+#define TCU_TSR_STOP5 (1 << 5)
5514+#define TCU_TSR_STOP4 (1 << 4)
5515+#define TCU_TSR_STOP3 (1 << 3)
5516+#define TCU_TSR_STOP2 (1 << 2)
5517+#define TCU_TSR_STOP1 (1 << 1)
5518+#define TCU_TSR_STOP0 (1 << 0)
5519+
5520+#define TCU_TSSR_WDTSS (1 << 16)
5521+#define TCU_TSSR_STPS5 (1 << 5)
5522+#define TCU_TSSR_STPS4 (1 << 4)
5523+#define TCU_TSSR_STPS3 (1 << 3)
5524+#define TCU_TSSR_STPS2 (1 << 2)
5525+#define TCU_TSSR_STPS1 (1 << 1)
5526+#define TCU_TSSR_STPS0 (1 << 0)
5527+
5528+#define TCU_TSSR_WDTSC (1 << 16)
5529+#define TCU_TSSR_STPC5 (1 << 5)
5530+#define TCU_TSSR_STPC4 (1 << 4)
5531+#define TCU_TSSR_STPC3 (1 << 3)
5532+#define TCU_TSSR_STPC2 (1 << 2)
5533+#define TCU_TSSR_STPC1 (1 << 1)
5534+#define TCU_TSSR_STPC0 (1 << 0)
5535+
5536+
5537+/*
5538+ * WDT (WatchDog Timer)
5539+ */
5540+#define WDT_TDR (WDT_BASE + 0x00)
5541+#define WDT_TCER (WDT_BASE + 0x04)
5542+#define WDT_TCNT (WDT_BASE + 0x08)
5543+#define WDT_TCSR (WDT_BASE + 0x0C)
5544+
5545+#define REG_WDT_TDR REG16(WDT_TDR)
5546+#define REG_WDT_TCER REG8(WDT_TCER)
5547+#define REG_WDT_TCNT REG16(WDT_TCNT)
5548+#define REG_WDT_TCSR REG16(WDT_TCSR)
5549+
5550+/* Register definition */
5551+#define WDT_TCSR_PRESCALE_BIT 3
5552+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
5553+ #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
5554+ #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
5555+ #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
5556+ #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
5557+ #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
5558+ #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
5559+#define WDT_TCSR_EXT_EN (1 << 2)
5560+#define WDT_TCSR_RTC_EN (1 << 1)
5561+#define WDT_TCSR_PCK_EN (1 << 0)
5562+
5563+#define WDT_TCER_TCEN (1 << 0)
5564+
5565+
5566+/*
5567+ * DMAC (DMA Controller)
5568+ */
5569+
5570+#define MAX_DMA_NUM 6 /* max 6 channels */
5571+
5572+#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
5573+#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
5574+#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
5575+#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
5576+#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
5577+#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
5578+#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
5579+#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
5580+#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
5581+#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
5582+#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
5583+
5584+/* channel 0 */
5585+#define DMAC_DSAR0 DMAC_DSAR(0)
5586+#define DMAC_DTAR0 DMAC_DTAR(0)
5587+#define DMAC_DTCR0 DMAC_DTCR(0)
5588+#define DMAC_DRSR0 DMAC_DRSR(0)
5589+#define DMAC_DCCSR0 DMAC_DCCSR(0)
5590+#define DMAC_DCMD0 DMAC_DCMD(0)
5591+#define DMAC_DDA0 DMAC_DDA(0)
5592+
5593+/* channel 1 */
5594+#define DMAC_DSAR1 DMAC_DSAR(1)
5595+#define DMAC_DTAR1 DMAC_DTAR(1)
5596+#define DMAC_DTCR1 DMAC_DTCR(1)
5597+#define DMAC_DRSR1 DMAC_DRSR(1)
5598+#define DMAC_DCCSR1 DMAC_DCCSR(1)
5599+#define DMAC_DCMD1 DMAC_DCMD(1)
5600+#define DMAC_DDA1 DMAC_DDA(1)
5601+
5602+/* channel 2 */
5603+#define DMAC_DSAR2 DMAC_DSAR(2)
5604+#define DMAC_DTAR2 DMAC_DTAR(2)
5605+#define DMAC_DTCR2 DMAC_DTCR(2)
5606+#define DMAC_DRSR2 DMAC_DRSR(2)
5607+#define DMAC_DCCSR2 DMAC_DCCSR(2)
5608+#define DMAC_DCMD2 DMAC_DCMD(2)
5609+#define DMAC_DDA2 DMAC_DDA(2)
5610+
5611+/* channel 3 */
5612+#define DMAC_DSAR3 DMAC_DSAR(3)
5613+#define DMAC_DTAR3 DMAC_DTAR(3)
5614+#define DMAC_DTCR3 DMAC_DTCR(3)
5615+#define DMAC_DRSR3 DMAC_DRSR(3)
5616+#define DMAC_DCCSR3 DMAC_DCCSR(3)
5617+#define DMAC_DCMD3 DMAC_DCMD(3)
5618+#define DMAC_DDA3 DMAC_DDA(3)
5619+
5620+/* channel 4 */
5621+#define DMAC_DSAR4 DMAC_DSAR(4)
5622+#define DMAC_DTAR4 DMAC_DTAR(4)
5623+#define DMAC_DTCR4 DMAC_DTCR(4)
5624+#define DMAC_DRSR4 DMAC_DRSR(4)
5625+#define DMAC_DCCSR4 DMAC_DCCSR(4)
5626+#define DMAC_DCMD4 DMAC_DCMD(4)
5627+#define DMAC_DDA4 DMAC_DDA(4)
5628+
5629+/* channel 5 */
5630+#define DMAC_DSAR5 DMAC_DSAR(5)
5631+#define DMAC_DTAR5 DMAC_DTAR(5)
5632+#define DMAC_DTCR5 DMAC_DTCR(5)
5633+#define DMAC_DRSR5 DMAC_DRSR(5)
5634+#define DMAC_DCCSR5 DMAC_DCCSR(5)
5635+#define DMAC_DCMD5 DMAC_DCMD(5)
5636+#define DMAC_DDA5 DMAC_DDA(5)
5637+
5638+#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
5639+#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
5640+#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
5641+#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
5642+#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
5643+#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
5644+#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
5645+#define REG_DMAC_DMACR REG32(DMAC_DMACR)
5646+#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
5647+#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
5648+#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
5649+
5650+/* DMA request source register */
5651+#define DMAC_DRSR_RS_BIT 0
5652+#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
5653+#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
5654+#define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
5655+#define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
5656+#define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
5657+#define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
5658+#define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
5659+#define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
5660+#define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
5661+#define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
5662+#define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
5663+#define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
5664+#define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
5665+
5666+/* DMA channel control/status register */
5667+#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
5668+#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
5669+#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
5670+#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
5671+#define DMAC_DCCSR_AR (1 << 4) /* address error */
5672+#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
5673+#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
5674+#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
5675+#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
5676+
5677+/* DMA channel command register */
5678+#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
5679+#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
5680+#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
5681+#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
5682+ #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
5683+ #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
5684+ #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
5685+ #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
5686+ #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
5687+ #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
5688+ #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
5689+ #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
5690+ #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
5691+ #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
5692+ #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
5693+ #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
5694+ #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
5695+ #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
5696+ #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
5697+ #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
5698+#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
5699+#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
5700+ #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
5701+ #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
5702+ #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
5703+#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
5704+#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
5705+ #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
5706+ #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
5707+ #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
5708+#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
5709+#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
5710+ #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
5711+ #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
5712+ #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
5713+ #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
5714+ #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
5715+#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
5716+#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
5717+#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
5718+#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
5719+#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
5720+#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
5721+
5722+/* DMA descriptor address register */
5723+#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
5724+#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
5725+#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
5726+#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
5727+
5728+/* DMA control register */
5729+#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
5730+#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
5731+ #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
5732+ #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
5733+ #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
5734+ #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
5735+#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
5736+#define DMAC_DMACR_AR (1 << 2) /* address error flag */
5737+#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
5738+
5739+/* DMA doorbell register */
5740+#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
5741+#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
5742+#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
5743+#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
5744+#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
5745+#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
5746+
5747+/* DMA doorbell set register */
5748+#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
5749+#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
5750+#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
5751+#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
5752+#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
5753+#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
5754+
5755+/* DMA interrupt pending register */
5756+#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
5757+#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
5758+#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
5759+#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
5760+#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
5761+#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
5762+
5763+
5764+/*************************************************************************
5765+ * GPIO (General-Purpose I/O Ports)
5766+ *************************************************************************/
5767+#define MAX_GPIO_NUM 128
5768+
5769+/* = 0,1,2,3 */
5770+#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
5771+#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
5772+#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
5773+#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
5774+#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
5775+#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
5776+#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
5777+#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
5778+#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
5779+#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
5780+#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
5781+#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
5782+#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
5783+#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
5784+#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
5785+#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
5786+#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
5787+#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
5788+#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
5789+#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
5790+#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
5791+#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
5792+#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
5793+#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
5794+
5795+#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
5796+#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
5797+#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
5798+#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
5799+#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
5800+#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
5801+#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
5802+#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
5803+#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
5804+#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
5805+#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
5806+#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
5807+#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
5808+#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
5809+#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
5810+#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
5811+#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
5812+#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
5813+#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
5814+#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
5815+#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
5816+#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
5817+#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
5818+#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
5819+
5820+
5821+/*************************************************************************
5822+ * UART
5823+ *************************************************************************/
5824+
5825+#define IRDA_BASE UART0_BASE
5826+#define UART_BASE UART0_BASE
5827+#define UART_OFF 0x1000
5828+
5829+/* Register Offset */
5830+#define OFF_RDR (0x00) /* R 8b H'xx */
5831+#define OFF_TDR (0x00) /* W 8b H'xx */
5832+#define OFF_DLLR (0x00) /* RW 8b H'00 */
5833+#define OFF_DLHR (0x04) /* RW 8b H'00 */
5834+#define OFF_IER (0x04) /* RW 8b H'00 */
5835+#define OFF_ISR (0x08) /* R 8b H'01 */
5836+#define OFF_FCR (0x08) /* W 8b H'00 */
5837+#define OFF_LCR (0x0C) /* RW 8b H'00 */
5838+#define OFF_MCR (0x10) /* RW 8b H'00 */
5839+#define OFF_LSR (0x14) /* R 8b H'00 */
5840+#define OFF_MSR (0x18) /* R 8b H'00 */
5841+#define OFF_SPR (0x1C) /* RW 8b H'00 */
5842+#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
5843+#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
5844+#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
5845+
5846+/* Register Address */
5847+#define UART0_RDR (UART0_BASE + OFF_RDR)
5848+#define UART0_TDR (UART0_BASE + OFF_TDR)
5849+#define UART0_DLLR (UART0_BASE + OFF_DLLR)
5850+#define UART0_DLHR (UART0_BASE + OFF_DLHR)
5851+#define UART0_IER (UART0_BASE + OFF_IER)
5852+#define UART0_ISR (UART0_BASE + OFF_ISR)
5853+#define UART0_FCR (UART0_BASE + OFF_FCR)
5854+#define UART0_LCR (UART0_BASE + OFF_LCR)
5855+#define UART0_MCR (UART0_BASE + OFF_MCR)
5856+#define UART0_LSR (UART0_BASE + OFF_LSR)
5857+#define UART0_MSR (UART0_BASE + OFF_MSR)
5858+#define UART0_SPR (UART0_BASE + OFF_SPR)
5859+#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
5860+#define UART0_UMR (UART0_BASE + OFF_UMR)
5861+#define UART0_UACR (UART0_BASE + OFF_UACR)
5862+
5863+/*
5864+ * Define macros for UART_IER
5865+ * UART Interrupt Enable Register
5866+ */
5867+#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
5868+#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
5869+#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
5870+#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
5871+#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
5872+
5873+/*
5874+ * Define macros for UART_ISR
5875+ * UART Interrupt Status Register
5876+ */
5877+#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
5878+#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
5879+#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
5880+#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
5881+#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
5882+#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
5883+#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
5884+#define UART_ISR_FFMS_NO_FIFO (0 << 6)
5885+#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
5886+
5887+/*
5888+ * Define macros for UART_FCR
5889+ * UART FIFO Control Register
5890+ */
5891+#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
5892+#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
5893+#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
5894+#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
5895+#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
5896+#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
5897+#define UART_FCR_RTRG_1 (0 << 6)
5898+#define UART_FCR_RTRG_4 (1 << 6)
5899+#define UART_FCR_RTRG_8 (2 << 6)
5900+#define UART_FCR_RTRG_15 (3 << 6)
5901+
5902+/*
5903+ * Define macros for UART_LCR
5904+ * UART Line Control Register
5905+ */
5906+#define UART_LCR_WLEN (3 << 0) /* word length */
5907+#define UART_LCR_WLEN_5 (0 << 0)
5908+#define UART_LCR_WLEN_6 (1 << 0)
5909+#define UART_LCR_WLEN_7 (2 << 0)
5910+#define UART_LCR_WLEN_8 (3 << 0)
5911+#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
5912+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
5913+#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
5914+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
5915+#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
5916+ 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
5917+
5918+#define UART_LCR_PE (1 << 3) /* 0: parity disable */
5919+#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
5920+#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
5921+#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
5922+#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
5923+
5924+/*
5925+ * Define macros for UART_LSR
5926+ * UART Line Status Register
5927+ */
5928+#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
5929+#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
5930+#define UART_LSR_PER (1 << 2) /* 0: no parity error */
5931+#define UART_LSR_FER (1 << 3) /* 0; no framing error */
5932+#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
5933+#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
5934+#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
5935+#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
5936+
5937+/*
5938+ * Define macros for UART_MCR
5939+ * UART Modem Control Register
5940+ */
5941+#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
5942+#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
5943+#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
5944+#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
5945+#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
5946+#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
5947+
5948+/*
5949+ * Define macros for UART_MSR
5950+ * UART Modem Status Register
5951+ */
5952+#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
5953+#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
5954+#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
5955+#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
5956+#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
5957+#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
5958+#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
5959+#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
5960+
5961+/*
5962+ * Define macros for SIRCR
5963+ * Slow IrDA Control Register
5964+ */
5965+#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
5966+#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
5967+#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
5968+ 1: 0 pulse width is 1.6us for 115.2Kbps */
5969+#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
5970+#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
5971+
5972+
5973+/*************************************************************************
5974+ * AIC (AC97/I2S Controller)
5975+ *************************************************************************/
5976+#define AIC_FR (AIC_BASE + 0x000)
5977+#define AIC_CR (AIC_BASE + 0x004)
5978+#define AIC_ACCR1 (AIC_BASE + 0x008)
5979+#define AIC_ACCR2 (AIC_BASE + 0x00C)
5980+#define AIC_I2SCR (AIC_BASE + 0x010)
5981+#define AIC_SR (AIC_BASE + 0x014)
5982+#define AIC_ACSR (AIC_BASE + 0x018)
5983+#define AIC_I2SSR (AIC_BASE + 0x01C)
5984+#define AIC_ACCAR (AIC_BASE + 0x020)
5985+#define AIC_ACCDR (AIC_BASE + 0x024)
5986+#define AIC_ACSAR (AIC_BASE + 0x028)
5987+#define AIC_ACSDR (AIC_BASE + 0x02C)
5988+#define AIC_I2SDIV (AIC_BASE + 0x030)
5989+#define AIC_DR (AIC_BASE + 0x034)
5990+
5991+#define REG_AIC_FR REG32(AIC_FR)
5992+#define REG_AIC_CR REG32(AIC_CR)
5993+#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
5994+#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
5995+#define REG_AIC_I2SCR REG32(AIC_I2SCR)
5996+#define REG_AIC_SR REG32(AIC_SR)
5997+#define REG_AIC_ACSR REG32(AIC_ACSR)
5998+#define REG_AIC_I2SSR REG32(AIC_I2SSR)
5999+#define REG_AIC_ACCAR REG32(AIC_ACCAR)
6000+#define REG_AIC_ACCDR REG32(AIC_ACCDR)
6001+#define REG_AIC_ACSAR REG32(AIC_ACSAR)
6002+#define REG_AIC_ACSDR REG32(AIC_ACSDR)
6003+#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
6004+#define REG_AIC_DR REG32(AIC_DR)
6005+
6006+/* AIC Controller Configuration Register (AIC_FR) */
6007+
6008+#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
6009+#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
6010+#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
6011+#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
6012+#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
6013+#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
6014+#define AIC_FR_RST (1 << 3) /* AIC registers reset */
6015+#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
6016+#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
6017+#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
6018+
6019+/* AIC Controller Common Control Register (AIC_CR) */
6020+
6021+#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
6022+#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
6023+ #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
6024+ #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
6025+ #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
6026+ #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
6027+ #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
6028+#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
6029+#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
6030+ #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
6031+ #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
6032+ #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
6033+ #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
6034+ #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
6035+#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
6036+#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
6037+#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
6038+#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
6039+#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
6040+#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
6041+#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
6042+#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
6043+#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
6044+#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
6045+#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
6046+#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
6047+#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
6048+
6049+/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
6050+
6051+#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
6052+#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
6053+ #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
6054+ #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
6055+ #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
6056+ #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
6057+ #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
6058+ #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
6059+ #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
6060+ #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
6061+ #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
6062+ #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
6063+#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
6064+#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
6065+ #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
6066+ #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
6067+ #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
6068+ #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
6069+ #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
6070+ #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
6071+ #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
6072+ #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
6073+ #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
6074+ #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
6075+
6076+/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
6077+
6078+#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
6079+#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
6080+#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
6081+#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
6082+#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
6083+ #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
6084+ #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
6085+ #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
6086+ #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
6087+#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
6088+#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
6089+ #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
6090+ #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
6091+ #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
6092+ #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
6093+#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
6094+#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
6095+#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
6096+#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
6097+
6098+/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
6099+
6100+#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
6101+#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
6102+#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
6103+ #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
6104+ #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
6105+ #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
6106+ #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
6107+ #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
6108+#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
6109+
6110+/* AIC Controller FIFO Status Register (AIC_SR) */
6111+
6112+#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
6113+#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
6114+#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
6115+#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
6116+#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
6117+#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
6118+#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
6119+#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
6120+
6121+/* AIC Controller AC-link Status Register (AIC_ACSR) */
6122+
6123+#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
6124+#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
6125+#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
6126+#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
6127+#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
6128+#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
6129+
6130+/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
6131+
6132+#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
6133+
6134+/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
6135+
6136+#define AIC_ACCAR_CAR_BIT 0
6137+#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
6138+
6139+/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
6140+
6141+#define AIC_ACCDR_CDR_BIT 0
6142+#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
6143+
6144+/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
6145+
6146+#define AIC_ACSAR_SAR_BIT 0
6147+#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
6148+
6149+/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
6150+
6151+#define AIC_ACSDR_SDR_BIT 0
6152+#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
6153+
6154+/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
6155+
6156+#define AIC_I2SDIV_DIV_BIT 0
6157+#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
6158+ #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
6159+ #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
6160+ #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
6161+ #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
6162+ #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
6163+ #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
6164+
6165+
6166+/*************************************************************************
6167+ * ICDC (Internal CODEC)
6168+ *************************************************************************/
6169+#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
6170+#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
6171+#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
6172+#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
6173+#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
6174+#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
6175+#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
6176+
6177+#define REG_ICDC_CR REG32(ICDC_CR)
6178+#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
6179+#define REG_ICDC_APPRE REG32(ICDC_APPRE)
6180+#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
6181+#define REG_ICDC_APSR REG32(ICDC_APSR)
6182+#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
6183+#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
6184+
6185+/* ICDC Control Register */
6186+#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
6187+#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
6188+#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
6189+#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
6190+ #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
6191+ #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
6192+ #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
6193+ #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
6194+ #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
6195+ #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
6196+ #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
6197+ #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
6198+ #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
6199+#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
6200+#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
6201+ #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
6202+ #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
6203+ #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
6204+ #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
6205+#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
6206+#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
6207+ #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
6208+ #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
6209+ #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
6210+ #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
6211+#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
6212+#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
6213+#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
6214+#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
6215+#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
6216+#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
6217+#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
6218+#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
6219+#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
6220+#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
6221+#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
6222+#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
6223+
6224+/* Anti-Pop WAIT Stage Timing Control Register */
6225+#define ICDC_APWAIT_WAITSN_BIT 0
6226+#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
6227+
6228+/* Anti-Pop HPEN-PRE Stage Timing Control Register */
6229+#define ICDC_APPRE_PRESN_BIT 0
6230+#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
6231+
6232+/* Anti-Pop HPEN Stage Timing Control Register */
6233+#define ICDC_APHPEN_HPENSN_BIT 0
6234+#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
6235+
6236+/* Anti-Pop Status Register */
6237+#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
6238+#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
6239+#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
6240+#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
6241+ #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
6242+#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
6243+ #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
6244+ #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
6245+ #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
6246+ #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
6247+#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
6248+#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
6249+
6250+
6251+/*************************************************************************
6252+ * I2C
6253+ *************************************************************************/
6254+#define I2C_DR (I2C_BASE + 0x000)
6255+#define I2C_CR (I2C_BASE + 0x004)
6256+#define I2C_SR (I2C_BASE + 0x008)
6257+#define I2C_GR (I2C_BASE + 0x00C)
6258+
6259+#define REG_I2C_DR REG8(I2C_DR)
6260+#define REG_I2C_CR REG8(I2C_CR)
6261+#define REG_I2C_SR REG8(I2C_SR)
6262+#define REG_I2C_GR REG16(I2C_GR)
6263+
6264+/* I2C Control Register (I2C_CR) */
6265+
6266+#define I2C_CR_IEN (1 << 4)
6267+#define I2C_CR_STA (1 << 3)
6268+#define I2C_CR_STO (1 << 2)
6269+#define I2C_CR_AC (1 << 1)
6270+#define I2C_CR_I2CE (1 << 0)
6271+
6272+/* I2C Status Register (I2C_SR) */
6273+
6274+#define I2C_SR_STX (1 << 4)
6275+#define I2C_SR_BUSY (1 << 3)
6276+#define I2C_SR_TEND (1 << 2)
6277+#define I2C_SR_DRF (1 << 1)
6278+#define I2C_SR_ACKF (1 << 0)
6279+
6280+
6281+/*************************************************************************
6282+ * SSI
6283+ *************************************************************************/
6284+#define SSI_DR (SSI_BASE + 0x000)
6285+#define SSI_CR0 (SSI_BASE + 0x004)
6286+#define SSI_CR1 (SSI_BASE + 0x008)
6287+#define SSI_SR (SSI_BASE + 0x00C)
6288+#define SSI_ITR (SSI_BASE + 0x010)
6289+#define SSI_ICR (SSI_BASE + 0x014)
6290+#define SSI_GR (SSI_BASE + 0x018)
6291+
6292+#define REG_SSI_DR REG32(SSI_DR)
6293+#define REG_SSI_CR0 REG16(SSI_CR0)
6294+#define REG_SSI_CR1 REG32(SSI_CR1)
6295+#define REG_SSI_SR REG32(SSI_SR)
6296+#define REG_SSI_ITR REG16(SSI_ITR)
6297+#define REG_SSI_ICR REG8(SSI_ICR)
6298+#define REG_SSI_GR REG16(SSI_GR)
6299+
6300+/* SSI Data Register (SSI_DR) */
6301+
6302+#define SSI_DR_GPC_BIT 0
6303+#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
6304+
6305+/* SSI Control Register 0 (SSI_CR0) */
6306+
6307+#define SSI_CR0_SSIE (1 << 15)
6308+#define SSI_CR0_TIE (1 << 14)
6309+#define SSI_CR0_RIE (1 << 13)
6310+#define SSI_CR0_TEIE (1 << 12)
6311+#define SSI_CR0_REIE (1 << 11)
6312+#define SSI_CR0_LOOP (1 << 10)
6313+#define SSI_CR0_RFINE (1 << 9)
6314+#define SSI_CR0_RFINC (1 << 8)
6315+#define SSI_CR0_FSEL (1 << 6)
6316+#define SSI_CR0_TFLUSH (1 << 2)
6317+#define SSI_CR0_RFLUSH (1 << 1)
6318+#define SSI_CR0_DISREV (1 << 0)
6319+
6320+/* SSI Control Register 1 (SSI_CR1) */
6321+
6322+#define SSI_CR1_FRMHL_BIT 30
6323+#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
6324+ #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
6325+ #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
6326+ #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
6327+ #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
6328+#define SSI_CR1_TFVCK_BIT 28
6329+#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
6330+ #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
6331+ #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
6332+ #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
6333+ #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
6334+#define SSI_CR1_TCKFI_BIT 26
6335+#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
6336+ #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
6337+ #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
6338+ #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
6339+ #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
6340+#define SSI_CR1_LFST (1 << 25)
6341+#define SSI_CR1_ITFRM (1 << 24)
6342+#define SSI_CR1_UNFIN (1 << 23)
6343+#define SSI_CR1_MULTS (1 << 22)
6344+#define SSI_CR1_FMAT_BIT 20
6345+#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
6346+ #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
6347+ #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
6348+ #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
6349+ #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
6350+#define SSI_CR1_TTRG_BIT 16
6351+#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
6352+ #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
6353+ #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
6354+ #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
6355+ #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
6356+ #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
6357+ #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
6358+ #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
6359+ #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
6360+ #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
6361+ #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
6362+ #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
6363+ #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
6364+ #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
6365+ #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
6366+ #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
6367+ #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
6368+#define SSI_CR1_MCOM_BIT 12
6369+#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
6370+ #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
6371+ #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
6372+ #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
6373+ #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
6374+ #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
6375+ #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
6376+ #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
6377+ #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
6378+ #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
6379+ #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
6380+ #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
6381+ #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
6382+ #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
6383+ #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
6384+ #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
6385+ #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
6386+#define SSI_CR1_RTRG_BIT 8
6387+#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
6388+ #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
6389+ #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
6390+ #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
6391+ #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
6392+ #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
6393+ #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
6394+ #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
6395+ #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
6396+ #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
6397+ #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
6398+ #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
6399+ #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
6400+ #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
6401+ #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
6402+ #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
6403+ #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
6404+#define SSI_CR1_FLEN_BIT 4
6405+#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
6406+ #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
6407+ #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
6408+ #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
6409+ #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
6410+ #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
6411+ #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
6412+ #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
6413+ #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
6414+ #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
6415+ #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
6416+ #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
6417+ #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
6418+ #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
6419+ #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
6420+ #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
6421+ #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
6422+#define SSI_CR1_PHA (1 << 1)
6423+#define SSI_CR1_POL (1 << 0)
6424+
6425+/* SSI Status Register (SSI_SR) */
6426+
6427+#define SSI_SR_TFIFONUM_BIT 16
6428+#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
6429+#define SSI_SR_RFIFONUM_BIT 8
6430+#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
6431+#define SSI_SR_END (1 << 7)
6432+#define SSI_SR_BUSY (1 << 6)
6433+#define SSI_SR_TFF (1 << 5)
6434+#define SSI_SR_RFE (1 << 4)
6435+#define SSI_SR_TFHE (1 << 3)
6436+#define SSI_SR_RFHF (1 << 2)
6437+#define SSI_SR_UNDR (1 << 1)
6438+#define SSI_SR_OVER (1 << 0)
6439+
6440+/* SSI Interval Time Control Register (SSI_ITR) */
6441+
6442+#define SSI_ITR_CNTCLK (1 << 15)
6443+#define SSI_ITR_IVLTM_BIT 0
6444+#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
6445+
6446+
6447+/*************************************************************************
6448+ * MSC
6449+ *************************************************************************/
6450+#define MSC_STRPCL (MSC_BASE + 0x000)
6451+#define MSC_STAT (MSC_BASE + 0x004)
6452+#define MSC_CLKRT (MSC_BASE + 0x008)
6453+#define MSC_CMDAT (MSC_BASE + 0x00C)
6454+#define MSC_RESTO (MSC_BASE + 0x010)
6455+#define MSC_RDTO (MSC_BASE + 0x014)
6456+#define MSC_BLKLEN (MSC_BASE + 0x018)
6457+#define MSC_NOB (MSC_BASE + 0x01C)
6458+#define MSC_SNOB (MSC_BASE + 0x020)
6459+#define MSC_IMASK (MSC_BASE + 0x024)
6460+#define MSC_IREG (MSC_BASE + 0x028)
6461+#define MSC_CMD (MSC_BASE + 0x02C)
6462+#define MSC_ARG (MSC_BASE + 0x030)
6463+#define MSC_RES (MSC_BASE + 0x034)
6464+#define MSC_RXFIFO (MSC_BASE + 0x038)
6465+#define MSC_TXFIFO (MSC_BASE + 0x03C)
6466+
6467+#define REG_MSC_STRPCL REG16(MSC_STRPCL)
6468+#define REG_MSC_STAT REG32(MSC_STAT)
6469+#define REG_MSC_CLKRT REG16(MSC_CLKRT)
6470+#define REG_MSC_CMDAT REG32(MSC_CMDAT)
6471+#define REG_MSC_RESTO REG16(MSC_RESTO)
6472+#define REG_MSC_RDTO REG16(MSC_RDTO)
6473+#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
6474+#define REG_MSC_NOB REG16(MSC_NOB)
6475+#define REG_MSC_SNOB REG16(MSC_SNOB)
6476+#define REG_MSC_IMASK REG16(MSC_IMASK)
6477+#define REG_MSC_IREG REG16(MSC_IREG)
6478+#define REG_MSC_CMD REG8(MSC_CMD)
6479+#define REG_MSC_ARG REG32(MSC_ARG)
6480+#define REG_MSC_RES REG16(MSC_RES)
6481+#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
6482+#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
6483+
6484+/* MSC Clock and Control Register (MSC_STRPCL) */
6485+
6486+#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
6487+#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
6488+#define MSC_STRPCL_START_READWAIT (1 << 5)
6489+#define MSC_STRPCL_STOP_READWAIT (1 << 4)
6490+#define MSC_STRPCL_RESET (1 << 3)
6491+#define MSC_STRPCL_START_OP (1 << 2)
6492+#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
6493+#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
6494+ #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
6495+ #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
6496+
6497+/* MSC Status Register (MSC_STAT) */
6498+
6499+#define MSC_STAT_IS_RESETTING (1 << 15)
6500+#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
6501+#define MSC_STAT_PRG_DONE (1 << 13)
6502+#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
6503+#define MSC_STAT_END_CMD_RES (1 << 11)
6504+#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
6505+#define MSC_STAT_IS_READWAIT (1 << 9)
6506+#define MSC_STAT_CLK_EN (1 << 8)
6507+#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
6508+#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
6509+#define MSC_STAT_CRC_RES_ERR (1 << 5)
6510+#define MSC_STAT_CRC_READ_ERROR (1 << 4)
6511+#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
6512+#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
6513+ #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
6514+ #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
6515+ #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
6516+#define MSC_STAT_TIME_OUT_RES (1 << 1)
6517+#define MSC_STAT_TIME_OUT_READ (1 << 0)
6518+
6519+/* MSC Bus Clock Control Register (MSC_CLKRT) */
6520+
6521+#define MSC_CLKRT_CLK_RATE_BIT 0
6522+#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
6523+ #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
6524+ #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
6525+ #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
6526+ #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
6527+ #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
6528+ #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
6529+ #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
6530+ #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
6531+
6532+/* MSC Command Sequence Control Register (MSC_CMDAT) */
6533+
6534+#define MSC_CMDAT_IO_ABORT (1 << 11)
6535+#define MSC_CMDAT_BUS_WIDTH_BIT 9
6536+#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
6537+ #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
6538+ #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
6539+ #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
6540+ #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
6541+#define MSC_CMDAT_DMA_EN (1 << 8)
6542+#define MSC_CMDAT_INIT (1 << 7)
6543+#define MSC_CMDAT_BUSY (1 << 6)
6544+#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
6545+#define MSC_CMDAT_WRITE (1 << 4)
6546+#define MSC_CMDAT_READ (0 << 4)
6547+#define MSC_CMDAT_DATA_EN (1 << 3)
6548+#define MSC_CMDAT_RESPONSE_BIT 0
6549+#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
6550+ #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
6551+ #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
6552+ #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
6553+ #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
6554+ #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
6555+ #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
6556+ #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
6557+
6558+#define CMDAT_DMA_EN (1 << 8)
6559+#define CMDAT_INIT (1 << 7)
6560+#define CMDAT_BUSY (1 << 6)
6561+#define CMDAT_STREAM (1 << 5)
6562+#define CMDAT_WRITE (1 << 4)
6563+#define CMDAT_DATA_EN (1 << 3)
6564+
6565+/* MSC Interrupts Mask Register (MSC_IMASK) */
6566+
6567+#define MSC_IMASK_SDIO (1 << 7)
6568+#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
6569+#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
6570+#define MSC_IMASK_END_CMD_RES (1 << 2)
6571+#define MSC_IMASK_PRG_DONE (1 << 1)
6572+#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
6573+
6574+
6575+/* MSC Interrupts Status Register (MSC_IREG) */
6576+
6577+#define MSC_IREG_SDIO (1 << 7)
6578+#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
6579+#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
6580+#define MSC_IREG_END_CMD_RES (1 << 2)
6581+#define MSC_IREG_PRG_DONE (1 << 1)
6582+#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
6583+
6584+
6585+/*************************************************************************
6586+ * EMC (External Memory Controller)
6587+ *************************************************************************/
6588+#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
6589+
6590+#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
6591+#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
6592+#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
6593+#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
6594+#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
6595+#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
6596+#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
6597+#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
6598+#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
6599+#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
6600+
6601+#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
6602+#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
6603+#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
6604+#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
6605+#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
6606+#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
6607+#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
6608+#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
6609+#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
6610+#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
6611+#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
6612+#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
6613+
6614+#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
6615+#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
6616+#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
6617+#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
6618+#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
6619+#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
6620+
6621+#define REG_EMC_BCR REG32(EMC_BCR)
6622+
6623+#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
6624+#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
6625+#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
6626+#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
6627+#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
6628+#define REG_EMC_SACR0 REG32(EMC_SACR0)
6629+#define REG_EMC_SACR1 REG32(EMC_SACR1)
6630+#define REG_EMC_SACR2 REG32(EMC_SACR2)
6631+#define REG_EMC_SACR3 REG32(EMC_SACR3)
6632+#define REG_EMC_SACR4 REG32(EMC_SACR4)
6633+
6634+#define REG_EMC_NFCSR REG32(EMC_NFCSR)
6635+#define REG_EMC_NFECR REG32(EMC_NFECR)
6636+#define REG_EMC_NFECC REG32(EMC_NFECC)
6637+#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
6638+#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
6639+#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
6640+#define REG_EMC_NFINTS REG32(EMC_NFINTS)
6641+#define REG_EMC_NFINTE REG32(EMC_NFINTE)
6642+#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
6643+#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
6644+#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
6645+#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
6646+
6647+#define REG_EMC_DMCR REG32(EMC_DMCR)
6648+#define REG_EMC_RTCSR REG16(EMC_RTCSR)
6649+#define REG_EMC_RTCNT REG16(EMC_RTCNT)
6650+#define REG_EMC_RTCOR REG16(EMC_RTCOR)
6651+#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
6652+
6653+/* Static Memory Control Register */
6654+#define EMC_SMCR_STRV_BIT 24
6655+#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
6656+#define EMC_SMCR_TAW_BIT 20
6657+#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
6658+#define EMC_SMCR_TBP_BIT 16
6659+#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
6660+#define EMC_SMCR_TAH_BIT 12
6661+#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
6662+#define EMC_SMCR_TAS_BIT 8
6663+#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
6664+#define EMC_SMCR_BW_BIT 6
6665+#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
6666+ #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
6667+ #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
6668+ #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
6669+#define EMC_SMCR_BCM (1 << 3)
6670+#define EMC_SMCR_BL_BIT 1
6671+#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
6672+ #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
6673+ #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
6674+ #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
6675+ #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
6676+#define EMC_SMCR_SMT (1 << 0)
6677+
6678+/* Static Memory Bank Addr Config Reg */
6679+#define EMC_SACR_BASE_BIT 8
6680+#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
6681+#define EMC_SACR_MASK_BIT 0
6682+#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
6683+
6684+/* NAND Flash Control/Status Register */
6685+#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
6686+#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
6687+#define EMC_NFCSR_NFCE3 (1 << 5)
6688+#define EMC_NFCSR_NFE3 (1 << 4)
6689+#define EMC_NFCSR_NFCE2 (1 << 3)
6690+#define EMC_NFCSR_NFE2 (1 << 2)
6691+#define EMC_NFCSR_NFCE1 (1 << 1)
6692+#define EMC_NFCSR_NFE1 (1 << 0)
6693+
6694+/* NAND Flash ECC Control Register */
6695+#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
6696+#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
6697+#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
6698+#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
6699+#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
6700+#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
6701+#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
6702+
6703+/* NAND Flash ECC Data Register */
6704+#define EMC_NFECC_ECC2_BIT 16
6705+#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
6706+#define EMC_NFECC_ECC1_BIT 8
6707+#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
6708+#define EMC_NFECC_ECC0_BIT 0
6709+#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
6710+
6711+/* NAND Flash Interrupt Status Register */
6712+#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
6713+#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
6714+#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
6715+#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
6716+#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
6717+#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
6718+#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
6719+
6720+/* NAND Flash Interrupt Enable Register */
6721+#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
6722+#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
6723+#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
6724+#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
6725+#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
6726+
6727+/* NAND Flash RS Error Report Register */
6728+#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
6729+#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
6730+#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
6731+#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
6732+
6733+
6734+/* DRAM Control Register */
6735+#define EMC_DMCR_BW_BIT 31
6736+#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
6737+#define EMC_DMCR_CA_BIT 26
6738+#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
6739+ #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
6740+ #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
6741+ #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
6742+ #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
6743+ #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
6744+#define EMC_DMCR_RMODE (1 << 25)
6745+#define EMC_DMCR_RFSH (1 << 24)
6746+#define EMC_DMCR_MRSET (1 << 23)
6747+#define EMC_DMCR_RA_BIT 20
6748+#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
6749+ #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
6750+ #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
6751+ #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
6752+#define EMC_DMCR_BA_BIT 19
6753+#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
6754+#define EMC_DMCR_PDM (1 << 18)
6755+#define EMC_DMCR_EPIN (1 << 17)
6756+#define EMC_DMCR_TRAS_BIT 13
6757+#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
6758+#define EMC_DMCR_RCD_BIT 11
6759+#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
6760+#define EMC_DMCR_TPC_BIT 8
6761+#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
6762+#define EMC_DMCR_TRWL_BIT 5
6763+#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
6764+#define EMC_DMCR_TRC_BIT 2
6765+#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
6766+#define EMC_DMCR_TCL_BIT 0
6767+#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
6768+
6769+/* Refresh Time Control/Status Register */
6770+#define EMC_RTCSR_CMF (1 << 7)
6771+#define EMC_RTCSR_CKS_BIT 0
6772+#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
6773+ #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
6774+ #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
6775+ #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
6776+ #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
6777+ #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
6778+ #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
6779+ #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
6780+ #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
6781+
6782+/* SDRAM Bank Address Configuration Register */
6783+#define EMC_DMAR_BASE_BIT 8
6784+#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
6785+#define EMC_DMAR_MASK_BIT 0
6786+#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
6787+
6788+/* Mode Register of SDRAM bank 0 */
6789+#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
6790+#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
6791+#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
6792+ #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
6793+#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
6794+#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
6795+ #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
6796+ #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
6797+ #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
6798+#define EMC_SDMR_BT_BIT 3 /* Burst Type */
6799+#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
6800+ #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
6801+ #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
6802+#define EMC_SDMR_BL_BIT 0 /* Burst Length */
6803+#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
6804+ #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
6805+ #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
6806+ #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
6807+ #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
6808+
6809+#define EMC_SDMR_CAS2_16BIT \
6810+ (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
6811+#define EMC_SDMR_CAS2_32BIT \
6812+ (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
6813+#define EMC_SDMR_CAS3_16BIT \
6814+ (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
6815+#define EMC_SDMR_CAS3_32BIT \
6816+ (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
6817+
6818+/*************************************************************************
6819+ * CIM
6820+ *************************************************************************/
6821+#define CIM_CFG (CIM_BASE + 0x0000)
6822+#define CIM_CTRL (CIM_BASE + 0x0004)
6823+#define CIM_STATE (CIM_BASE + 0x0008)
6824+#define CIM_IID (CIM_BASE + 0x000C)
6825+#define CIM_RXFIFO (CIM_BASE + 0x0010)
6826+#define CIM_DA (CIM_BASE + 0x0020)
6827+#define CIM_FA (CIM_BASE + 0x0024)
6828+#define CIM_FID (CIM_BASE + 0x0028)
6829+#define CIM_CMD (CIM_BASE + 0x002C)
6830+
6831+#define REG_CIM_CFG REG32(CIM_CFG)
6832+#define REG_CIM_CTRL REG32(CIM_CTRL)
6833+#define REG_CIM_STATE REG32(CIM_STATE)
6834+#define REG_CIM_IID REG32(CIM_IID)
6835+#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
6836+#define REG_CIM_DA REG32(CIM_DA)
6837+#define REG_CIM_FA REG32(CIM_FA)
6838+#define REG_CIM_FID REG32(CIM_FID)
6839+#define REG_CIM_CMD REG32(CIM_CMD)
6840+
6841+/* CIM Configuration Register (CIM_CFG) */
6842+
6843+#define CIM_CFG_INV_DAT (1 << 15)
6844+#define CIM_CFG_VSP (1 << 14)
6845+#define CIM_CFG_HSP (1 << 13)
6846+#define CIM_CFG_PCP (1 << 12)
6847+#define CIM_CFG_DUMMY_ZERO (1 << 9)
6848+#define CIM_CFG_EXT_VSYNC (1 << 8)
6849+#define CIM_CFG_PACK_BIT 4
6850+#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
6851+ #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
6852+ #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
6853+ #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
6854+ #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
6855+ #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
6856+ #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
6857+ #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
6858+ #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
6859+#define CIM_CFG_DSM_BIT 0
6860+#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
6861+ #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
6862+ #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
6863+ #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
6864+ #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
6865+
6866+/* CIM Control Register (CIM_CTRL) */
6867+
6868+#define CIM_CTRL_MCLKDIV_BIT 24
6869+#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
6870+#define CIM_CTRL_FRC_BIT 16
6871+#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
6872+ #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
6873+ #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
6874+ #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
6875+ #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
6876+ #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
6877+ #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
6878+ #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
6879+ #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
6880+ #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
6881+ #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
6882+ #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
6883+ #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
6884+ #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
6885+ #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
6886+ #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
6887+ #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
6888+#define CIM_CTRL_VDDM (1 << 13)
6889+#define CIM_CTRL_DMA_SOFM (1 << 12)
6890+#define CIM_CTRL_DMA_EOFM (1 << 11)
6891+#define CIM_CTRL_DMA_STOPM (1 << 10)
6892+#define CIM_CTRL_RXF_TRIGM (1 << 9)
6893+#define CIM_CTRL_RXF_OFM (1 << 8)
6894+#define CIM_CTRL_RXF_TRIG_BIT 4
6895+#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
6896+ #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
6897+ #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
6898+ #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
6899+ #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
6900+ #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
6901+ #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
6902+ #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
6903+ #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
6904+#define CIM_CTRL_DMA_EN (1 << 2)
6905+#define CIM_CTRL_RXF_RST (1 << 1)
6906+#define CIM_CTRL_ENA (1 << 0)
6907+
6908+/* CIM State Register (CIM_STATE) */
6909+
6910+#define CIM_STATE_DMA_SOF (1 << 6)
6911+#define CIM_STATE_DMA_EOF (1 << 5)
6912+#define CIM_STATE_DMA_STOP (1 << 4)
6913+#define CIM_STATE_RXF_OF (1 << 3)
6914+#define CIM_STATE_RXF_TRIG (1 << 2)
6915+#define CIM_STATE_RXF_EMPTY (1 << 1)
6916+#define CIM_STATE_VDD (1 << 0)
6917+
6918+/* CIM DMA Command Register (CIM_CMD) */
6919+
6920+#define CIM_CMD_SOFINT (1 << 31)
6921+#define CIM_CMD_EOFINT (1 << 30)
6922+#define CIM_CMD_STOP (1 << 28)
6923+#define CIM_CMD_LEN_BIT 0
6924+#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
6925+
6926+
6927+/*************************************************************************
6928+ * SADC (Smart A/D Controller)
6929+ *************************************************************************/
6930+
6931+#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
6932+#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
6933+#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
6934+#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
6935+#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
6936+#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
6937+#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
6938+#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
6939+#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
6940+
6941+#define REG_SADC_ENA REG8(SADC_ENA)
6942+#define REG_SADC_CFG REG32(SADC_CFG)
6943+#define REG_SADC_CTRL REG8(SADC_CTRL)
6944+#define REG_SADC_STATE REG8(SADC_STATE)
6945+#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
6946+#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
6947+#define REG_SADC_TSDAT REG32(SADC_TSDAT)
6948+#define REG_SADC_BATDAT REG16(SADC_BATDAT)
6949+#define REG_SADC_SADDAT REG16(SADC_SADDAT)
6950+
6951+/* ADC Enable Register */
6952+#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
6953+#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
6954+#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
6955+#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
6956+
6957+/* ADC Configure Register */
6958+#define SADC_CFG_CLKOUT_NUM_BIT 16
6959+#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
6960+#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
6961+#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
6962+#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
6963+ #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
6964+ #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
6965+ #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
6966+#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
6967+#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
6968+ #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
6969+ #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
6970+ #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
6971+ #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
6972+ #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
6973+ #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
6974+ #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
6975+ #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
6976+#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
6977+#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
6978+#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
6979+#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
6980+#define SADC_CFG_CMD_BIT 0 /* ADC Command */
6981+#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
6982+ #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
6983+ #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
6984+ #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
6985+ #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
6986+ #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
6987+ #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
6988+ #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
6989+ #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
6990+ #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
6991+ #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
6992+ #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
6993+ #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
6994+ #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
6995+
6996+/* ADC Control Register */
6997+#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
6998+#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
6999+#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
7000+#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
7001+#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
7002+
7003+/* ADC Status Register */
7004+#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
7005+#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
7006+#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
7007+#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
7008+#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
7009+#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
7010+#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
7011+#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
7012+
7013+/* ADC Touch Screen Data Register */
7014+#define SADC_TSDAT_DATA0_BIT 0
7015+#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
7016+#define SADC_TSDAT_TYPE0 (1 << 15)
7017+#define SADC_TSDAT_DATA1_BIT 16
7018+#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
7019+#define SADC_TSDAT_TYPE1 (1 << 31)
7020+
7021+
7022+/*************************************************************************
7023+ * SLCD (Smart LCD Controller)
7024+ *************************************************************************/
7025+
7026+#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
7027+#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
7028+#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
7029+#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
7030+#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
7031+
7032+#define REG_SLCD_CFG REG32(SLCD_CFG)
7033+#define REG_SLCD_CTRL REG8(SLCD_CTRL)
7034+#define REG_SLCD_STATE REG8(SLCD_STATE)
7035+#define REG_SLCD_DATA REG32(SLCD_DATA)
7036+#define REG_SLCD_FIFO REG32(SLCD_FIFO)
7037+
7038+/* SLCD Configure Register */
7039+#define SLCD_CFG_BURST_BIT 14
7040+#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
7041+ #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
7042+ #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
7043+#define SLCD_CFG_DWIDTH_BIT 10
7044+#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
7045+ #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
7046+ #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
7047+ #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
7048+ #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
7049+ #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
7050+ #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
7051+#define SLCD_CFG_CWIDT