Date:2010-01-11 03:20:39 (3 years 4 months ago)
Author:Lars C.
Commit:ded8f6c1150e3fe99d3a5e675c8158e8ff8a55d5
Message:jz4740: strip lots of now unused defines regs.h
Files: target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/clock.h (1 diff)
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/regs.h (6 diffs)
target/linux/xburst/files-2.6.31/arch/mips/jz4740/dma.c (1 diff)
target/linux/xburst/files-2.6.31/arch/mips/jz4740/reset.c (2 diffs)
target/linux/xburst/files-2.6.31/arch/mips/jz4740/setup.c (3 diffs)
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.c (3 diffs)

Change Details

target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/clock.h
1515#ifndef __ASM_JZ4740_CLOCK_H__
1616#define __ASM_JZ4740_CLOCK_H__
1717
18#include <asm/mach-jz4740/regs.h>
19
1820#ifndef JZ_EXTAL
1921//#define JZ_EXTAL 3686400 /* 3.6864 MHz */
2022#define JZ_EXTAL 12000000 /* 3.6864 MHz */
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/regs.h
5252#define IPU_BASE 0xB3080000
5353#define ETH_BASE 0xB3100000
5454
55
56/*************************************************************************
57 * INTC (Interrupt Controller)
58 *************************************************************************/
59#define INTC_ISR (INTC_BASE + 0x00)
60#define INTC_IMR (INTC_BASE + 0x04)
61#define INTC_IMSR (INTC_BASE + 0x08)
62#define INTC_IMCR (INTC_BASE + 0x0c)
63#define INTC_IPR (INTC_BASE + 0x10)
64
65#define REG_INTC_ISR REG32(INTC_ISR)
66#define REG_INTC_IMR REG32(INTC_IMR)
67#define REG_INTC_IMSR REG32(INTC_IMSR)
68#define REG_INTC_IMCR REG32(INTC_IMCR)
69#define REG_INTC_IPR REG32(INTC_IPR)
70
71#define NUM_DMA 6
72#define NUM_GPIO 128
73/*************************************************************************
74 * RTC
75 *************************************************************************/
76#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
77#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
78#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
79#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
80
81#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
82#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
83#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
84#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
85#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
86#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
87
88#define REG_RTC_RCR REG32(RTC_RCR)
89#define REG_RTC_RSR REG32(RTC_RSR)
90#define REG_RTC_RSAR REG32(RTC_RSAR)
91#define REG_RTC_RGR REG32(RTC_RGR)
92#define REG_RTC_HCR REG32(RTC_HCR)
93#define REG_RTC_HWFCR REG32(RTC_HWFCR)
94#define REG_RTC_HRCR REG32(RTC_HRCR)
95#define REG_RTC_HWCR REG32(RTC_HWCR)
96#define REG_RTC_HWRSR REG32(RTC_HWRSR)
97#define REG_RTC_HSPR REG32(RTC_HSPR)
98
99/* RTC Control Register */
100#define RTC_RCR_WRDY_BIT 7
101#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
102#define RTC_RCR_1HZ_BIT 6
103#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
104#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
105#define RTC_RCR_AF_BIT 4
106#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
107#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
108#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
109#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
110
111/* RTC Regulator Register */
112#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
113#define RTC_RGR_ADJC_BIT 16
114#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
115#define RTC_RGR_NC1HZ_BIT 0
116#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
117
118/* Hibernate Control Register */
119#define RTC_HCR_PD (1 << 0) /* Power Down */
120
121/* Hibernate Wakeup Filter Counter Register */
122#define RTC_HWFCR_BIT 5
123#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
124
125/* Hibernate Reset Counter Register */
126#define RTC_HRCR_BIT 5
127#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
128
129/* Hibernate Wakeup Control Register */
130#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
131
132/* Hibernate Wakeup Status Register */
133#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
134#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
135#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
136#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
137
138
13955/*************************************************************************
14056 * CPM (Clock reset and Power control Management)
14157 *************************************************************************/
...... 
16076
16177#define CPM_RSR (CPM_BASE+0x08)
16278
163
16479#define REG_CPM_CPCCR REG32(CPM_CPCCR)
16580#define REG_CPM_CPPCR REG32(CPM_CPPCR)
16681#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
...... 
18196
18297#define REG_CPM_RSR REG32(CPM_RSR)
18398
184
18599/* Clock Control Register */
186100#define CPM_CPCCR_I2CS (1 << 31)
187101#define CPM_CPCCR_CLKOEN (1 << 30)
...... 
294208#define CPM_RSR_WR (1 << 1)
295209#define CPM_RSR_PR (1 << 0)
296210
297
298/*************************************************************************
299 * TCU (Timer Counter Unit)
300 *************************************************************************/
301#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
302#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
303#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
304#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
305#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
306#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
307#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
308#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
309#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
310#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
311#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
312#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
313#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
314#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
315#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
316#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
317#define TCU_TDFR1 (TCU_BASE + 0x50)
318#define TCU_TDHR1 (TCU_BASE + 0x54)
319#define TCU_TCNT1 (TCU_BASE + 0x58)
320#define TCU_TCSR1 (TCU_BASE + 0x5C)
321#define TCU_TDFR2 (TCU_BASE + 0x60)
322#define TCU_TDHR2 (TCU_BASE + 0x64)
323#define TCU_TCNT2 (TCU_BASE + 0x68)
324#define TCU_TCSR2 (TCU_BASE + 0x6C)
325#define TCU_TDFR3 (TCU_BASE + 0x70)
326#define TCU_TDHR3 (TCU_BASE + 0x74)
327#define TCU_TCNT3 (TCU_BASE + 0x78)
328#define TCU_TCSR3 (TCU_BASE + 0x7C)
329#define TCU_TDFR4 (TCU_BASE + 0x80)
330#define TCU_TDHR4 (TCU_BASE + 0x84)
331#define TCU_TCNT4 (TCU_BASE + 0x88)
332#define TCU_TCSR4 (TCU_BASE + 0x8C)
333#define TCU_TDFR5 (TCU_BASE + 0x90)
334#define TCU_TDHR5 (TCU_BASE + 0x94)
335#define TCU_TCNT5 (TCU_BASE + 0x98)
336#define TCU_TCSR5 (TCU_BASE + 0x9C)
337
338#define REG_TCU_TSR REG32(TCU_TSR)
339#define REG_TCU_TSSR REG32(TCU_TSSR)
340#define REG_TCU_TSCR REG32(TCU_TSCR)
341#define REG_TCU_TER REG8(TCU_TER)
342#define REG_TCU_TESR REG8(TCU_TESR)
343#define REG_TCU_TECR REG8(TCU_TECR)
344#define REG_TCU_TFR REG32(TCU_TFR)
345#define REG_TCU_TFSR REG32(TCU_TFSR)
346#define REG_TCU_TFCR REG32(TCU_TFCR)
347#define REG_TCU_TMR REG32(TCU_TMR)
348#define REG_TCU_TMSR REG32(TCU_TMSR)
349#define REG_TCU_TMCR REG32(TCU_TMCR)
350#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
351#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
352#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
353#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
354#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
355#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
356#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
357#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
358#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
359#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
360#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
361#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
362#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
363#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
364#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
365#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
366#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
367#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
368#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
369#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
370
371// n = 0,1,2,3,4,5
372#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
373#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
374#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
375#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
376
377#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
378#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
379#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
380#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
381
382// Register definitions
383#define TCU_TCSR_PWM_SD (1 << 9)
384#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
385#define TCU_TCSR_PWM_EN (1 << 7)
386#define TCU_TCSR_PRESCALE_BIT 3
387#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
388  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
389  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
390  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
391  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
392  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
393  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
394#define TCU_TCSR_EXT_EN (1 << 2)
395#define TCU_TCSR_RTC_EN (1 << 1)
396#define TCU_TCSR_PCK_EN (1 << 0)
397
398#define TCU_TER_TCEN5 (1 << 5)
399#define TCU_TER_TCEN4 (1 << 4)
400#define TCU_TER_TCEN3 (1 << 3)
401#define TCU_TER_TCEN2 (1 << 2)
402#define TCU_TER_TCEN1 (1 << 1)
403#define TCU_TER_TCEN0 (1 << 0)
404
405#define TCU_TESR_TCST5 (1 << 5)
406#define TCU_TESR_TCST4 (1 << 4)
407#define TCU_TESR_TCST3 (1 << 3)
408#define TCU_TESR_TCST2 (1 << 2)
409#define TCU_TESR_TCST1 (1 << 1)
410#define TCU_TESR_TCST0 (1 << 0)
411
412#define TCU_TECR_TCCL5 (1 << 5)
413#define TCU_TECR_TCCL4 (1 << 4)
414#define TCU_TECR_TCCL3 (1 << 3)
415#define TCU_TECR_TCCL2 (1 << 2)
416#define TCU_TECR_TCCL1 (1 << 1)
417#define TCU_TECR_TCCL0 (1 << 0)
418
419#define TCU_TFR_HFLAG5 (1 << 21)
420#define TCU_TFR_HFLAG4 (1 << 20)
421#define TCU_TFR_HFLAG3 (1 << 19)
422#define TCU_TFR_HFLAG2 (1 << 18)
423#define TCU_TFR_HFLAG1 (1 << 17)
424#define TCU_TFR_HFLAG0 (1 << 16)
425#define TCU_TFR_FFLAG5 (1 << 5)
426#define TCU_TFR_FFLAG4 (1 << 4)
427#define TCU_TFR_FFLAG3 (1 << 3)
428#define TCU_TFR_FFLAG2 (1 << 2)
429#define TCU_TFR_FFLAG1 (1 << 1)
430#define TCU_TFR_FFLAG0 (1 << 0)
431
432#define TCU_TFSR_HFLAG5 (1 << 21)
433#define TCU_TFSR_HFLAG4 (1 << 20)
434#define TCU_TFSR_HFLAG3 (1 << 19)
435#define TCU_TFSR_HFLAG2 (1 << 18)
436#define TCU_TFSR_HFLAG1 (1 << 17)
437#define TCU_TFSR_HFLAG0 (1 << 16)
438#define TCU_TFSR_FFLAG5 (1 << 5)
439#define TCU_TFSR_FFLAG4 (1 << 4)
440#define TCU_TFSR_FFLAG3 (1 << 3)
441#define TCU_TFSR_FFLAG2 (1 << 2)
442#define TCU_TFSR_FFLAG1 (1 << 1)
443#define TCU_TFSR_FFLAG0 (1 << 0)
444
445#define TCU_TFCR_HFLAG5 (1 << 21)
446#define TCU_TFCR_HFLAG4 (1 << 20)
447#define TCU_TFCR_HFLAG3 (1 << 19)
448#define TCU_TFCR_HFLAG2 (1 << 18)
449#define TCU_TFCR_HFLAG1 (1 << 17)
450#define TCU_TFCR_HFLAG0 (1 << 16)
451#define TCU_TFCR_FFLAG5 (1 << 5)
452#define TCU_TFCR_FFLAG4 (1 << 4)
453#define TCU_TFCR_FFLAG3 (1 << 3)
454#define TCU_TFCR_FFLAG2 (1 << 2)
455#define TCU_TFCR_FFLAG1 (1 << 1)
456#define TCU_TFCR_FFLAG0 (1 << 0)
457
458#define TCU_TMR_HMASK5 (1 << 21)
459#define TCU_TMR_HMASK4 (1 << 20)
460#define TCU_TMR_HMASK3 (1 << 19)
461#define TCU_TMR_HMASK2 (1 << 18)
462#define TCU_TMR_HMASK1 (1 << 17)
463#define TCU_TMR_HMASK0 (1 << 16)
464#define TCU_TMR_FMASK5 (1 << 5)
465#define TCU_TMR_FMASK4 (1 << 4)
466#define TCU_TMR_FMASK3 (1 << 3)
467#define TCU_TMR_FMASK2 (1 << 2)
468#define TCU_TMR_FMASK1 (1 << 1)
469#define TCU_TMR_FMASK0 (1 << 0)
470
471#define TCU_TMSR_HMST5 (1 << 21)
472#define TCU_TMSR_HMST4 (1 << 20)
473#define TCU_TMSR_HMST3 (1 << 19)
474#define TCU_TMSR_HMST2 (1 << 18)
475#define TCU_TMSR_HMST1 (1 << 17)
476#define TCU_TMSR_HMST0 (1 << 16)
477#define TCU_TMSR_FMST5 (1 << 5)
478#define TCU_TMSR_FMST4 (1 << 4)
479#define TCU_TMSR_FMST3 (1 << 3)
480#define TCU_TMSR_FMST2 (1 << 2)
481#define TCU_TMSR_FMST1 (1 << 1)
482#define TCU_TMSR_FMST0 (1 << 0)
483
484#define TCU_TMCR_HMCL5 (1 << 21)
485#define TCU_TMCR_HMCL4 (1 << 20)
486#define TCU_TMCR_HMCL3 (1 << 19)
487#define TCU_TMCR_HMCL2 (1 << 18)
488#define TCU_TMCR_HMCL1 (1 << 17)
489#define TCU_TMCR_HMCL0 (1 << 16)
490#define TCU_TMCR_FMCL5 (1 << 5)
491#define TCU_TMCR_FMCL4 (1 << 4)
492#define TCU_TMCR_FMCL3 (1 << 3)
493#define TCU_TMCR_FMCL2 (1 << 2)
494#define TCU_TMCR_FMCL1 (1 << 1)
495#define TCU_TMCR_FMCL0 (1 << 0)
496
497#define TCU_TSR_WDTS (1 << 16)
498#define TCU_TSR_STOP5 (1 << 5)
499#define TCU_TSR_STOP4 (1 << 4)
500#define TCU_TSR_STOP3 (1 << 3)
501#define TCU_TSR_STOP2 (1 << 2)
502#define TCU_TSR_STOP1 (1 << 1)
503#define TCU_TSR_STOP0 (1 << 0)
504
505#define TCU_TSSR_WDTSS (1 << 16)
506#define TCU_TSSR_STPS5 (1 << 5)
507#define TCU_TSSR_STPS4 (1 << 4)
508#define TCU_TSSR_STPS3 (1 << 3)
509#define TCU_TSSR_STPS2 (1 << 2)
510#define TCU_TSSR_STPS1 (1 << 1)
511#define TCU_TSSR_STPS0 (1 << 0)
512
513#define TCU_TSSR_WDTSC (1 << 16)
514#define TCU_TSSR_STPC5 (1 << 5)
515#define TCU_TSSR_STPC4 (1 << 4)
516#define TCU_TSSR_STPC3 (1 << 3)
517#define TCU_TSSR_STPC2 (1 << 2)
518#define TCU_TSSR_STPC1 (1 << 1)
519#define TCU_TSSR_STPC0 (1 << 0)
520
521
522/*************************************************************************
523 * WDT (WatchDog Timer)
524 *************************************************************************/
525#define WDT_TDR (WDT_BASE + 0x00)
526#define WDT_TCER (WDT_BASE + 0x04)
527#define WDT_TCNT (WDT_BASE + 0x08)
528#define WDT_TCSR (WDT_BASE + 0x0C)
529
530#define REG_WDT_TDR REG16(WDT_TDR)
531#define REG_WDT_TCER REG8(WDT_TCER)
532#define REG_WDT_TCNT REG16(WDT_TCNT)
533#define REG_WDT_TCSR REG16(WDT_TCSR)
534
535// Register definition
536#define WDT_TCSR_PRESCALE_BIT 3
537#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
538  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
539  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
540  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
541  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
542  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
543  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
544#define WDT_TCSR_EXT_EN (1 << 2)
545#define WDT_TCSR_RTC_EN (1 << 1)
546#define WDT_TCSR_PCK_EN (1 << 0)
547
548#define WDT_TCER_TCEN (1 << 0)
549
550
551/*************************************************************************
552 * DMAC (DMA Controller)
553 *************************************************************************/
554
555#define MAX_DMA_NUM 6 /* max 6 channels */
556
557#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
558#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
559#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
560#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
561#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
562#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
563#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
564#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
565#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
566#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
567#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
568
569// channel 0
570#define DMAC_DSAR0 DMAC_DSAR(0)
571#define DMAC_DTAR0 DMAC_DTAR(0)
572#define DMAC_DTCR0 DMAC_DTCR(0)
573#define DMAC_DRSR0 DMAC_DRSR(0)
574#define DMAC_DCCSR0 DMAC_DCCSR(0)
575#define DMAC_DCMD0 DMAC_DCMD(0)
576#define DMAC_DDA0 DMAC_DDA(0)
577
578// channel 1
579#define DMAC_DSAR1 DMAC_DSAR(1)
580#define DMAC_DTAR1 DMAC_DTAR(1)
581#define DMAC_DTCR1 DMAC_DTCR(1)
582#define DMAC_DRSR1 DMAC_DRSR(1)
583#define DMAC_DCCSR1 DMAC_DCCSR(1)
584#define DMAC_DCMD1 DMAC_DCMD(1)
585#define DMAC_DDA1 DMAC_DDA(1)
586
587// channel 2
588#define DMAC_DSAR2 DMAC_DSAR(2)
589#define DMAC_DTAR2 DMAC_DTAR(2)
590#define DMAC_DTCR2 DMAC_DTCR(2)
591#define DMAC_DRSR2 DMAC_DRSR(2)
592#define DMAC_DCCSR2 DMAC_DCCSR(2)
593#define DMAC_DCMD2 DMAC_DCMD(2)
594#define DMAC_DDA2 DMAC_DDA(2)
595
596// channel 3
597#define DMAC_DSAR3 DMAC_DSAR(3)
598#define DMAC_DTAR3 DMAC_DTAR(3)
599#define DMAC_DTCR3 DMAC_DTCR(3)
600#define DMAC_DRSR3 DMAC_DRSR(3)
601#define DMAC_DCCSR3 DMAC_DCCSR(3)
602#define DMAC_DCMD3 DMAC_DCMD(3)
603#define DMAC_DDA3 DMAC_DDA(3)
604
605// channel 4
606#define DMAC_DSAR4 DMAC_DSAR(4)
607#define DMAC_DTAR4 DMAC_DTAR(4)
608#define DMAC_DTCR4 DMAC_DTCR(4)
609#define DMAC_DRSR4 DMAC_DRSR(4)
610#define DMAC_DCCSR4 DMAC_DCCSR(4)
611#define DMAC_DCMD4 DMAC_DCMD(4)
612#define DMAC_DDA4 DMAC_DDA(4)
613
614// channel 5
615#define DMAC_DSAR5 DMAC_DSAR(5)
616#define DMAC_DTAR5 DMAC_DTAR(5)
617#define DMAC_DTCR5 DMAC_DTCR(5)
618#define DMAC_DRSR5 DMAC_DRSR(5)
619#define DMAC_DCCSR5 DMAC_DCCSR(5)
620#define DMAC_DCMD5 DMAC_DCMD(5)
621#define DMAC_DDA5 DMAC_DDA(5)
622
623#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
624#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
625#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
626#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
627#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
628#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
629#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
630#define REG_DMAC_DMACR REG32(DMAC_DMACR)
631#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
632#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
633#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
634
635// DMA request source register
636#define DMAC_DRSR_RS_BIT 0
637#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
638  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
639  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
640  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
641  #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
642  #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
643  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
644  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
645  #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
646  #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
647  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
648  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
649  #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
650
651// DMA channel control/status register
652#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
653#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
654#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
655#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
656#define DMAC_DCCSR_AR (1 << 4) /* address error */
657#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
658#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
659#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
660#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
661
662// DMA channel command register
663#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
664#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
665#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
666#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
667  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
668  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
669  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
670  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
671  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
672  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
673  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
674  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
675  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
676  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
677  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
678  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
679  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
680  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
681  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
682  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
683#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
684#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
685  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
686  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
687  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
688#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
689#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
690  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
691  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
692  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
693#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
694#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
695  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
696  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
697  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
698  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
699  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
700#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
701#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
702#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
703#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
704#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
705#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
706
707// DMA descriptor address register
708#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
709#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
710#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
711#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
712
713// DMA control register
714#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
715#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
716  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
717  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
718  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
719  #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
720#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
721#define DMAC_DMACR_AR (1 << 2) /* address error flag */
722#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
723
724// DMA doorbell register
725#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
726#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
727#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
728#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
729#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
730#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
731
732// DMA doorbell set register
733#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
734#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
735#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
736#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
737#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
738#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
739
740// DMA interrupt pending register
741#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
742#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
743#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
744#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
745#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
746#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
747
748
749/*************************************************************************
750 * GPIO (General-Purpose I/O Ports)
751 *************************************************************************/
752#define MAX_GPIO_NUM 128
753
754//n = 0,1,2,3
755#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
756#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
757#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
758#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
759#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
760#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
761#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
762#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
763#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
764#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
765#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
766#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
767#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
768#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
769#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
770#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
771#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
772#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
773#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
774#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
775#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
776#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
777#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
778#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag Clear Register */
779
780#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
781#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
782#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
783#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
784#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
785#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
786#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
787#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
788#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
789#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
790#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
791#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
792#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
793#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
794#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
795#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
796#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
797#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
798#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
799#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
800#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
801#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
802#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
803#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
804
805
806211/*************************************************************************
807212 * UART
808213 *************************************************************************/
...... 
945350
946351
947352/*************************************************************************
948 * AIC (AC97/I2S Controller)
949 *************************************************************************/
950#define AIC_FR (AIC_BASE + 0x000)
951#define AIC_CR (AIC_BASE + 0x004)
952#define AIC_ACCR1 (AIC_BASE + 0x008)
953#define AIC_ACCR2 (AIC_BASE + 0x00C)
954#define AIC_I2SCR (AIC_BASE + 0x010)
955#define AIC_SR (AIC_BASE + 0x014)
956#define AIC_ACSR (AIC_BASE + 0x018)
957#define AIC_I2SSR (AIC_BASE + 0x01C)
958#define AIC_ACCAR (AIC_BASE + 0x020)
959#define AIC_ACCDR (AIC_BASE + 0x024)
960#define AIC_ACSAR (AIC_BASE + 0x028)
961#define AIC_ACSDR (AIC_BASE + 0x02C)
962#define AIC_I2SDIV (AIC_BASE + 0x030)
963#define AIC_DR (AIC_BASE + 0x034)
964
965#define REG_AIC_FR REG32(AIC_FR)
966#define REG_AIC_CR REG32(AIC_CR)
967#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
968#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
969#define REG_AIC_I2SCR REG32(AIC_I2SCR)
970#define REG_AIC_SR REG32(AIC_SR)
971#define REG_AIC_ACSR REG32(AIC_ACSR)
972#define REG_AIC_I2SSR REG32(AIC_I2SSR)
973#define REG_AIC_ACCAR REG32(AIC_ACCAR)
974#define REG_AIC_ACCDR REG32(AIC_ACCDR)
975#define REG_AIC_ACSAR REG32(AIC_ACSAR)
976#define REG_AIC_ACSDR REG32(AIC_ACSDR)
977#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
978#define REG_AIC_DR REG32(AIC_DR)
979
980/* AIC Controller Configuration Register (AIC_FR) */
981
982#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
983#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
984#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
985#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
986#define AIC_FR_LSMP (1 << 6) /* Play Zero sample or last sample */
987#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
988#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
989#define AIC_FR_RST (1 << 3) /* AIC registers reset */
990#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
991#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
992#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
993
994/* AIC Controller Common Control Register (AIC_CR) */
995
996#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
997#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
998  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
999  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1000  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1001  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1002  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1003#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1004#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1005  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1006  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1007  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1008  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1009  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1010#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1011#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1012#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1013#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1014#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1015#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1016#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1017#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1018#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1019#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1020#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1021#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1022#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1023
1024/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1025
1026#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1027#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1028  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1029  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1030  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1031  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1032  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1033  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1034  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1035  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1036  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1037  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1038#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1039#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1040  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1041  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1042  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1043  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1044  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1045  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1046  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1047  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1048  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1049  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1050
1051/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1052
1053#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1054#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1055#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1056#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1057#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1058  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1059  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1060  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1061  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1062#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1063#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1064  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1065  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1066  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1067  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1068#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1069#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1070#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1071#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1072
1073/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1074
1075#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1076#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1077#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1078  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1079  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1080  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1081  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1082  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1083#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1084
1085/* AIC Controller FIFO Status Register (AIC_SR) */
1086
1087#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1088#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1089#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1090#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1091#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1092#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1093#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1094#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1095
1096/* AIC Controller AC-link Status Register (AIC_ACSR) */
1097
1098#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1099#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1100#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1101#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1102#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1103#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1104
1105/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1106
1107#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1108
1109/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1110
1111#define AIC_ACCAR_CAR_BIT 0
1112#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1113
1114/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1115
1116#define AIC_ACCDR_CDR_BIT 0
1117#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1118
1119/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1120
1121#define AIC_ACSAR_SAR_BIT 0
1122#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1123
1124/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1125
1126#define AIC_ACSDR_SDR_BIT 0
1127#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1128
1129/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1130
1131#define AIC_I2SDIV_DIV_BIT 0
1132#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1133  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1134  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1135  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1136  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1137  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1138  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1139
1140
1141/*************************************************************************
1142 * ICDC (Internal CODEC)
1143 *************************************************************************/
1144#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1145#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1146#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1147#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1148#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1149#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1150#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1151
1152#define REG_ICDC_CR REG32(ICDC_CR)
1153#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1154#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1155#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1156#define REG_ICDC_APSR REG32(ICDC_APSR)
1157#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1158#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1159
1160/* ICDC Control Register */
1161#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1162#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1163#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1164#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1165  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1166  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1167  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1168  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1169  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1170  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1171  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1172  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1173  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1174#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1175#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1176  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1177  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1178  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1179  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1180#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1181#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1182  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1183  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1184  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1185  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1186#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1187#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1188#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1189#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1190#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1191#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1192#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1193#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1194#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1195#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1196#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1197#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1198
1199/* Anti-Pop WAIT Stage Timing Control Register */
1200#define ICDC_APWAIT_WAITSN_BIT 0
1201#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1202
1203/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1204#define ICDC_APPRE_PRESN_BIT 0
1205#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1206
1207/* Anti-Pop HPEN Stage Timing Control Register */
1208#define ICDC_APHPEN_HPENSN_BIT 0
1209#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1210
1211/* Anti-Pop Status Register */
1212#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1213#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1214#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1215#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1216  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1217#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1218  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1219  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1220  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1221  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1222#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1223#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1224
1225
1226/*************************************************************************
1227 * I2C
1228 *************************************************************************/
1229#define I2C_DR (I2C_BASE + 0x000)
1230#define I2C_CR (I2C_BASE + 0x004)
1231#define I2C_SR (I2C_BASE + 0x008)
1232#define I2C_GR (I2C_BASE + 0x00C)
1233
1234#define REG_I2C_DR REG8(I2C_DR)
1235#define REG_I2C_CR REG8(I2C_CR)
1236#define REG_I2C_SR REG8(I2C_SR)
1237#define REG_I2C_GR REG16(I2C_GR)
1238
1239/* I2C Control Register (I2C_CR) */
1240
1241#define I2C_CR_IEN (1 << 4)
1242#define I2C_CR_STA (1 << 3)
1243#define I2C_CR_STO (1 << 2)
1244#define I2C_CR_AC (1 << 1)
1245#define I2C_CR_I2CE (1 << 0)
1246
1247/* I2C Status Register (I2C_SR) */
1248
1249#define I2C_SR_STX (1 << 4)
1250#define I2C_SR_BUSY (1 << 3)
1251#define I2C_SR_TEND (1 << 2)
1252#define I2C_SR_DRF (1 << 1)
1253#define I2C_SR_ACKF (1 << 0)
1254
1255
1256/*************************************************************************
1257 * SSI
1258 *************************************************************************/
1259#define SSI_DR (SSI_BASE + 0x000)
1260#define SSI_CR0 (SSI_BASE + 0x004)
1261#define SSI_CR1 (SSI_BASE + 0x008)
1262#define SSI_SR (SSI_BASE + 0x00C)
1263#define SSI_ITR (SSI_BASE + 0x010)
1264#define SSI_ICR (SSI_BASE + 0x014)
1265#define SSI_GR (SSI_BASE + 0x018)
1266
1267#define REG_SSI_DR REG32(SSI_DR)
1268#define REG_SSI_CR0 REG16(SSI_CR0)
1269#define REG_SSI_CR1 REG32(SSI_CR1)
1270#define REG_SSI_SR REG32(SSI_SR)
1271#define REG_SSI_ITR REG16(SSI_ITR)
1272#define REG_SSI_ICR REG8(SSI_ICR)
1273#define REG_SSI_GR REG16(SSI_GR)
1274
1275/* SSI Data Register (SSI_DR) */
1276
1277#define SSI_DR_GPC_BIT 0
1278#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1279
1280/* SSI Control Register 0 (SSI_CR0) */
1281
1282#define SSI_CR0_SSIE (1 << 15)
1283#define SSI_CR0_TIE (1 << 14)
1284#define SSI_CR0_RIE (1 << 13)
1285#define SSI_CR0_TEIE (1 << 12)
1286#define SSI_CR0_REIE (1 << 11)
1287#define SSI_CR0_LOOP (1 << 10)
1288#define SSI_CR0_RFINE (1 << 9)
1289#define SSI_CR0_RFINC (1 << 8)
1290#define SSI_CR0_FSEL (1 << 6)
1291#define SSI_CR0_TFLUSH (1 << 2)
1292#define SSI_CR0_RFLUSH (1 << 1)
1293#define SSI_CR0_DISREV (1 << 0)
1294
1295/* SSI Control Register 1 (SSI_CR1) */
1296
1297#define SSI_CR1_FRMHL_BIT 30
1298#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1299  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1300  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1301  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1302  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1303#define SSI_CR1_TFVCK_BIT 28
1304#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1305  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1306  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1307  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1308  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1309#define SSI_CR1_TCKFI_BIT 26
1310#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1311  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1312  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1313  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1314  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1315#define SSI_CR1_LFST (1 << 25)
1316#define SSI_CR1_ITFRM (1 << 24)
1317#define SSI_CR1_UNFIN (1 << 23)
1318#define SSI_CR1_MULTS (1 << 22)
1319#define SSI_CR1_FMAT_BIT 20
1320#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1321  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1322  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1323  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1324  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1325#define SSI_CR1_TTRG_BIT 16
1326#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1327  #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1328  #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1329  #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1330  #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1331  #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1332  #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1333  #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1334  #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1335  #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1336  #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1337  #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1338  #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1339  #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1340  #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1341  #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1342  #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1343#define SSI_CR1_MCOM_BIT 12
1344#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1345  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1346  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1347  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1348  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1349  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1350  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1351  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1352  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1353  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1354  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1355  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1356  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1357  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1358  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1359  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1360  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1361#define SSI_CR1_RTRG_BIT 8
1362#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1363  #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1364  #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1365  #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1366  #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1367  #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1368  #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1369  #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1370  #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1371  #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1372  #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1373  #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1374  #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1375  #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1376  #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1377  #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1378  #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1379#define SSI_CR1_FLEN_BIT 4
1380#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1381  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1382  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1383  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1384  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1385  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1386  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1387  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1388  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1389  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1390  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1391  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1392  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1393  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1394  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1395  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1396  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1397#define SSI_CR1_PHA (1 << 1)
1398#define SSI_CR1_POL (1 << 0)
1399
1400/* SSI Status Register (SSI_SR) */
1401
1402#define SSI_SR_TFIFONUM_BIT 16
1403#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1404#define SSI_SR_RFIFONUM_BIT 8
1405#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1406#define SSI_SR_END (1 << 7)
1407#define SSI_SR_BUSY (1 << 6)
1408#define SSI_SR_TFF (1 << 5)
1409#define SSI_SR_RFE (1 << 4)
1410#define SSI_SR_TFHE (1 << 3)
1411#define SSI_SR_RFHF (1 << 2)
1412#define SSI_SR_UNDR (1 << 1)
1413#define SSI_SR_OVER (1 << 0)
1414
1415/* SSI Interval Time Control Register (SSI_ITR) */
1416
1417#define SSI_ITR_CNTCLK (1 << 15)
1418#define SSI_ITR_IVLTM_BIT 0
1419#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1420
1421
1422/*************************************************************************
1423 * MSC
1424 *************************************************************************/
1425#define MSC_STRPCL (MSC_BASE + 0x000)
1426#define MSC_STAT (MSC_BASE + 0x004)
1427#define MSC_CLKRT (MSC_BASE + 0x008)
1428#define MSC_CMDAT (MSC_BASE + 0x00C)
1429#define MSC_RESTO (MSC_BASE + 0x010)
1430#define MSC_RDTO (MSC_BASE + 0x014)
1431#define MSC_BLKLEN (MSC_BASE + 0x018)
1432#define MSC_NOB (MSC_BASE + 0x01C)
1433#define MSC_SNOB (MSC_BASE + 0x020)
1434#define MSC_IMASK (MSC_BASE + 0x024)
1435#define MSC_IREG (MSC_BASE + 0x028)
1436#define MSC_CMD (MSC_BASE + 0x02C)
1437#define MSC_ARG (MSC_BASE + 0x030)
1438#define MSC_RES (MSC_BASE + 0x034)
1439#define MSC_RXFIFO (MSC_BASE + 0x038)
1440#define MSC_TXFIFO (MSC_BASE + 0x03C)
1441
1442#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1443#define REG_MSC_STAT REG32(MSC_STAT)
1444#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1445#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1446#define REG_MSC_RESTO REG16(MSC_RESTO)
1447#define REG_MSC_RDTO REG16(MSC_RDTO)
1448#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1449#define REG_MSC_NOB REG16(MSC_NOB)
1450#define REG_MSC_SNOB REG16(MSC_SNOB)
1451#define REG_MSC_IMASK REG16(MSC_IMASK)
1452#define REG_MSC_IREG REG16(MSC_IREG)
1453#define REG_MSC_CMD REG8(MSC_CMD)
1454#define REG_MSC_ARG REG32(MSC_ARG)
1455#define REG_MSC_RES REG16(MSC_RES)
1456#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1457#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1458
1459/* MSC Clock and Control Register (MSC_STRPCL) */
1460
1461#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1462#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1463#define MSC_STRPCL_START_READWAIT (1 << 5)
1464#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1465#define MSC_STRPCL_RESET (1 << 3)
1466#define MSC_STRPCL_START_OP (1 << 2)
1467#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1468#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1469  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1470  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1471
1472/* MSC Status Register (MSC_STAT) */
1473
1474#define MSC_STAT_IS_RESETTING (1 << 15)
1475#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1476#define MSC_STAT_PRG_DONE (1 << 13)
1477#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1478#define MSC_STAT_END_CMD_RES (1 << 11)
1479#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1480#define MSC_STAT_IS_READWAIT (1 << 9)
1481#define MSC_STAT_CLK_EN (1 << 8)
1482#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1483#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1484#define MSC_STAT_CRC_RES_ERR (1 << 5)
1485#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1486#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1487#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1488  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1489  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1490  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1491#define MSC_STAT_TIME_OUT_RES (1 << 1)
1492#define MSC_STAT_TIME_OUT_READ (1 << 0)
1493
1494/* MSC Bus Clock Control Register (MSC_CLKRT) */
1495
1496#define MSC_CLKRT_CLK_RATE_BIT 0
1497#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1498  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1499  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1500  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1501  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1502  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1503  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1504  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1505  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1506
1507/* MSC Command Sequence Control Register (MSC_CMDAT) */
1508
1509#define MSC_CMDAT_IO_ABORT (1 << 11)
1510#define MSC_CMDAT_BUS_WIDTH_BIT 9
1511#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1512  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1513  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1514  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1515  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1516#define MSC_CMDAT_DMA_EN (1 << 8)
1517#define MSC_CMDAT_INIT (1 << 7)
1518#define MSC_CMDAT_BUSY (1 << 6)
1519#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1520#define MSC_CMDAT_WRITE (1 << 4)
1521#define MSC_CMDAT_READ (0 << 4)
1522#define MSC_CMDAT_DATA_EN (1 << 3)
1523#define MSC_CMDAT_RESPONSE_BIT 0
1524#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1525  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1526  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1527  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1528  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1529  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1530  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1531  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1532
1533#define CMDAT_DMA_EN (1 << 8)
1534#define CMDAT_INIT (1 << 7)
1535#define CMDAT_BUSY (1 << 6)
1536#define CMDAT_STREAM (1 << 5)
1537#define CMDAT_WRITE (1 << 4)
1538#define CMDAT_DATA_EN (1 << 3)
1539
1540/* MSC Interrupts Mask Register (MSC_IMASK) */
1541
1542#define MSC_IMASK_SDIO (1 << 7)
1543#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1544#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1545#define MSC_IMASK_END_CMD_RES (1 << 2)
1546#define MSC_IMASK_PRG_DONE (1 << 1)
1547#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1548
1549
1550/* MSC Interrupts Status Register (MSC_IREG) */
1551
1552#define MSC_IREG_SDIO (1 << 7)
1553#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1554#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1555#define MSC_IREG_END_CMD_RES (1 << 2)
1556#define MSC_IREG_PRG_DONE (1 << 1)
1557#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1558
1559
1560/*************************************************************************
1561353 * EMC (External Memory Controller)
1562354 *************************************************************************/
1563355#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
...... 
1787579#define EMC_SDMR_CAS3_32BIT \
1788580  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1789581
1790
1791582/*************************************************************************
1792 * CIM
583 * WDT (WatchDog Timer)
1793584 *************************************************************************/
1794#define CIM_CFG (CIM_BASE + 0x0000)
1795#define CIM_CTRL (CIM_BASE + 0x0004)
1796#define CIM_STATE (CIM_BASE + 0x0008)
1797#define CIM_IID (CIM_BASE + 0x000C)
1798#define CIM_RXFIFO (CIM_BASE + 0x0010)
1799#define CIM_DA (CIM_BASE + 0x0020)
1800#define CIM_FA (CIM_BASE + 0x0024)
1801#define CIM_FID (CIM_BASE + 0x0028)
1802#define CIM_CMD (CIM_BASE + 0x002C)
1803
1804#define REG_CIM_CFG REG32(CIM_CFG)
1805#define REG_CIM_CTRL REG32(CIM_CTRL)
1806#define REG_CIM_STATE REG32(CIM_STATE)
1807#define REG_CIM_IID REG32(CIM_IID)
1808#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1809#define REG_CIM_DA REG32(CIM_DA)
1810#define REG_CIM_FA REG32(CIM_FA)
1811#define REG_CIM_FID REG32(CIM_FID)
1812#define REG_CIM_CMD REG32(CIM_CMD)
1813
1814/* CIM Configuration Register (CIM_CFG) */
1815
1816#define CIM_CFG_INV_DAT (1 << 15)
1817#define CIM_CFG_VSP (1 << 14)
1818#define CIM_CFG_HSP (1 << 13)
1819#define CIM_CFG_PCP (1 << 12)
1820#define CIM_CFG_DUMMY_ZERO (1 << 9)
1821#define CIM_CFG_EXT_VSYNC (1 << 8)
1822#define CIM_CFG_PACK_BIT 4
1823#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1824  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1825  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1826  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1827  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1828  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1829  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1830  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1831  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1832#define CIM_CFG_DSM_BIT 0
1833#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1834  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1835  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1836  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1837  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1838
1839/* CIM Control Register (CIM_CTRL) */
1840
1841#define CIM_CTRL_MCLKDIV_BIT 24
1842#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1843#define CIM_CTRL_FRC_BIT 16
1844#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1845  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1846  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1847  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1848  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1849  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1850  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1851  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1852  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1853  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1854  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1855  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1856  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1857  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1858  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1859  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1860  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1861#define CIM_CTRL_VDDM (1 << 13)
1862#define CIM_CTRL_DMA_SOFM (1 << 12)
1863#define CIM_CTRL_DMA_EOFM (1 << 11)
1864#define CIM_CTRL_DMA_STOPM (1 << 10)
1865#define CIM_CTRL_RXF_TRIGM (1 << 9)
1866#define CIM_CTRL_RXF_OFM (1 << 8)
1867#define CIM_CTRL_RXF_TRIG_BIT 4
1868#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1869  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1870  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1871  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1872  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1873  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1874  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1875  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1876  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1877#define CIM_CTRL_DMA_EN (1 << 2)
1878#define CIM_CTRL_RXF_RST (1 << 1)
1879#define CIM_CTRL_ENA (1 << 0)
1880
1881/* CIM State Register (CIM_STATE) */
1882
1883#define CIM_STATE_DMA_SOF (1 << 6)
1884#define CIM_STATE_DMA_EOF (1 << 5)
1885#define CIM_STATE_DMA_STOP (1 << 4)
1886#define CIM_STATE_RXF_OF (1 << 3)
1887#define CIM_STATE_RXF_TRIG (1 << 2)
1888#define CIM_STATE_RXF_EMPTY (1 << 1)
1889#define CIM_STATE_VDD (1 << 0)
1890
1891/* CIM DMA Command Register (CIM_CMD) */
1892
1893#define CIM_CMD_SOFINT (1 << 31)
1894#define CIM_CMD_EOFINT (1 << 30)
1895#define CIM_CMD_STOP (1 << 28)
1896#define CIM_CMD_LEN_BIT 0
1897#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
585#define WDT_TDR (WDT_BASE + 0x00)
586#define WDT_TCER (WDT_BASE + 0x04)
587#define WDT_TCNT (WDT_BASE + 0x08)
588#define WDT_TCSR (WDT_BASE + 0x0C)
589
590#define REG_WDT_TDR REG16(WDT_TDR)
591#define REG_WDT_TCER REG8(WDT_TCER)
592#define REG_WDT_TCNT REG16(WDT_TCNT)
593#define REG_WDT_TCSR REG16(WDT_TCSR)
594
595// Register definition
596#define WDT_TCSR_PRESCALE_BIT 3
597#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
598  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
599  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
600  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
601  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
602  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
603  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
604#define WDT_TCSR_EXT_EN (1 << 2)
605#define WDT_TCSR_RTC_EN (1 << 1)
606#define WDT_TCSR_PCK_EN (1 << 0)
1898607
608#define WDT_TCER_TCEN (1 << 0)
1899609
1900610/*************************************************************************
1901 * SADC (Smart A/D Controller)
611 * RTC
1902612 *************************************************************************/
613#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
614#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
615#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
616#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
1903617
1904#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1905#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1906#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1907#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1908#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1909#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1910#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1911#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1912#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1913
1914#define REG_SADC_ENA REG8(SADC_ENA)
1915#define REG_SADC_CFG REG32(SADC_CFG)
1916#define REG_SADC_CTRL REG8(SADC_CTRL)
1917#define REG_SADC_STATE REG8(SADC_STATE)
1918#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1919#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1920#define REG_SADC_TSDAT REG32(SADC_TSDAT)
1921#define REG_SADC_BATDAT REG16(SADC_BATDAT)
1922#define REG_SADC_SADDAT REG16(SADC_SADDAT)
1923
1924/* ADC Enable Register */
1925#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1926#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1927#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1928#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1929
1930/* ADC Configure Register */
1931#define SADC_CFG_EXIN (1 << 30)
1932#define SADC_CFG_CLKOUT_NUM_BIT 16
1933#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1934#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1935#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1936#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1937  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1938  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1939  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1940#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1941#define SADC_CFG_DNUM_BIT 18 /* Sample Number */
1942#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1943  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1944  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1945  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1946  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1947  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1948  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1949  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1950  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1951  #define SADC_CFG_SNUM(x) ((x) << SADC_CFG_SNUM_BIT)
1952  #define SADC_CFG_DNUM(x) ((x) << SADC_CFG_DNUM_BIT)
1953#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1954#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1955#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
1956#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
1957#define SADC_CFG_CMD_BIT 0 /* ADC Command */
1958#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
1959  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
1960  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
1961  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
1962  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
1963  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
1964  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
1965  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
1966  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
1967  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
1968  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
1969  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
1970  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
1971  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
1972
1973/* ADC Control Register */
1974#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
1975#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
1976#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
1977#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
1978#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
1979
1980/* ADC Status Register */
1981#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
1982#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
1983#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
1984#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
1985#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
1986#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
1987#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
1988#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
1989
1990/* ADC Touch Screen Data Register */
1991#define SADC_TSDAT_DATA0_BIT 0
1992#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
1993#define SADC_TSDAT_TYPE0 (1 << 15)
1994#define SADC_TSDAT_DATA1_BIT 16
1995#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
1996#define SADC_TSDAT_TYPE1 (1 << 31)
618#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
619#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
620#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
621#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
622#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
623#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
1997624
625#define REG_RTC_RCR REG32(RTC_RCR)
626#define REG_RTC_RSR REG32(RTC_RSR)
627#define REG_RTC_RSAR REG32(RTC_RSAR)
628#define REG_RTC_RGR REG32(RTC_RGR)
629#define REG_RTC_HCR REG32(RTC_HCR)
630#define REG_RTC_HWFCR REG32(RTC_HWFCR)
631#define REG_RTC_HRCR REG32(RTC_HRCR)
632#define REG_RTC_HWCR REG32(RTC_HWCR)
633#define REG_RTC_HWRSR REG32(RTC_HWRSR)
634#define REG_RTC_HSPR REG32(RTC_HSPR)
1998635
1999/*************************************************************************
2000 * SLCD (Smart LCD Controller)
2001 *************************************************************************/
636/* RTC Control Register */
637#define RTC_RCR_WRDY_BIT 7
638#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
639#define RTC_RCR_1HZ_BIT 6
640#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
641#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
642#define RTC_RCR_AF_BIT 4
643#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
644#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
645#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
646#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
2002647
2003#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2004#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2005#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2006#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2007#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2008
2009#define REG_SLCD_CFG REG32(SLCD_CFG)
2010#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2011#define REG_SLCD_STATE REG8(SLCD_STATE)
2012#define REG_SLCD_DATA REG32(SLCD_DATA)
2013#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2014
2015/* SLCD Configure Register */
2016#define SLCD_CFG_BURST_BIT 14
2017#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2018  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2019  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2020#define SLCD_CFG_DWIDTH_BIT 10
2021#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2022  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2023  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2024  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2025  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2026  #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2027  #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
2028#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2029#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2030#define SLCD_CFG_CWIDTH_18BIT (2 << 8)
2031#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2032#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2033#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2034#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2035#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2036#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2037#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2038#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2039
2040/* SLCD Control Register */
2041#define SLCD_CTRL_DMA_EN (1 << 0)
2042
2043/* SLCD Status Register */
2044#define SLCD_STATE_BUSY (1 << 0)
2045
2046/* SLCD Data Register */
2047#define SLCD_DATA_RS_DATA (0 << 31)
2048#define SLCD_DATA_RS_COMMAND (1 << 31)
2049
2050/* SLCD FIFO Register */
2051#define SLCD_FIFO_RS_DATA (0 << 31)
2052#define SLCD_FIFO_RS_COMMAND (1 << 31)
648/* RTC Regulator Register */
649#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
650#define RTC_RGR_ADJC_BIT 16
651#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
652#define RTC_RGR_NC1HZ_BIT 0
653#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
2053654
655/* Hibernate Control Register */
656#define RTC_HCR_PD (1 << 0) /* Power Down */
2054657
2055/*************************************************************************
2056 * LCD (LCD Controller)
2057 *************************************************************************/
2058#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2059#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2060#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2061#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2062#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2063#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2064#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2065#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2066#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2067#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2068#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2069#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2070#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2071#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2072#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2073#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2074#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2075#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2076#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2077#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2078#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2079
2080#define REG_LCD_CFG REG32(LCD_CFG)
2081#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2082#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2083#define REG_LCD_VAT REG32(LCD_VAT)
2084#define REG_LCD_DAH REG32(LCD_DAH)
2085#define REG_LCD_DAV REG32(LCD_DAV)
2086#define REG_LCD_PS REG32(LCD_PS)
2087#define REG_LCD_CLS REG32(LCD_CLS)
2088#define REG_LCD_SPL REG32(LCD_SPL)
2089#define REG_LCD_REV REG32(LCD_REV)
2090#define REG_LCD_CTRL REG32(LCD_CTRL)
2091#define REG_LCD_STATE REG32(LCD_STATE)
2092#define REG_LCD_IID REG32(LCD_IID)
2093#define REG_LCD_DA0 REG32(LCD_DA0)
2094#define REG_LCD_SA0 REG32(LCD_SA0)
2095#define REG_LCD_FID0 REG32(LCD_FID0)
2096#define REG_LCD_CMD0 REG32(LCD_CMD0)
2097#define REG_LCD_DA1 REG32(LCD_DA1)
2098#define REG_LCD_SA1 REG32(LCD_SA1)
2099#define REG_LCD_FID1 REG32(LCD_FID1)
2100#define REG_LCD_CMD1 REG32(LCD_CMD1)
2101
2102/* LCD Configure Register */
2103#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2104#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2105  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2106  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2107#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2108#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2109#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2110#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2111#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2112#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2113#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2114#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2115#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2116#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2117#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2118#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2119#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2120#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2121#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2122#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2123#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2124#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2125#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2126  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2127  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2128  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2129#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2130#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2131  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2132  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2133  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2134  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2135  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2136  #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
2137  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2138  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2139  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2140  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2141  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2142  /* JZ47XX defines */
2143  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2144  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2145  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2146
2147
2148
2149/* Vertical Synchronize Register */
2150#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2151#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2152#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2153#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2154
2155/* Horizontal Synchronize Register */
2156#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2157#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2158#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2159#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2160
2161/* Virtual Area Setting Register */
2162#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2163#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2164#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2165#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2166
2167/* Display Area Horizontal Start/End Point Register */
2168#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2169#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2170#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2171#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2172
2173/* Display Area Vertical Start/End Point Register */
2174#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2175#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2176#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2177#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2178
2179/* PS Signal Setting */
2180#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2181#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2182#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2183#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2184
2185/* CLS Signal Setting */
2186#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2187#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2188#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2189#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2190
2191/* SPL Signal Setting */
2192#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2193#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2194#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2195#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2196
2197/* REV Signal Setting */
2198#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2199#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2200
2201/* LCD Control Register */
2202#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2203#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2204  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2205  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2206  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2207#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2208#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2209#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2210#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2211#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2212  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2213  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2214  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2215#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2216#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2217#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2218#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2219#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2220#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2221#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2222#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2223#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2224#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2225#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2226#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2227#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2228#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2229#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2230  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2231  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2232  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2233  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2234  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2235  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2236
2237/* LCD Status Register */
2238#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2239#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2240#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2241#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2242#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2243#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2244#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2245
2246/* DMA Command Register */
2247#define LCD_CMD_SOFINT (1 << 31)
2248#define LCD_CMD_EOFINT (1 << 30)
2249#define LCD_CMD_PAL (1 << 28)
2250#define LCD_CMD_LEN_BIT 0
2251#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
658/* Hibernate Wakeup Filter Counter Register */
659#define RTC_HWFCR_BIT 5
660#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
2252661
662/* Hibernate Reset Counter Register */
663#define RTC_HRCR_BIT 5
664#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
2253665
2254/*************************************************************************
2255 * USB Device
2256 *************************************************************************/
2257#define USB_BASE UDC_BASE
2258
2259#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2260#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2261#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2262#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2263#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2264#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2265#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2266#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2267#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2268#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2269#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2270
2271#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2272#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2273#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2274#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2275#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2276#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2277#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2278#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2279
2280#define USB_FIFO_EP0 (USB_BASE + 0x20)
2281#define USB_FIFO_EP1 (USB_BASE + 0x24)
2282#define USB_FIFO_EP2 (USB_BASE + 0x28)
2283
2284#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2285#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2286
2287#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2288#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2289#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2290#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2291#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2292#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2293#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2294
2295
2296/* Power register bit masks */
2297#define USB_POWER_SUSPENDM 0x01
2298#define USB_POWER_RESUME 0x04
2299#define USB_POWER_HSMODE 0x10
2300#define USB_POWER_HSENAB 0x20
2301#define USB_POWER_SOFTCONN 0x40
2302
2303/* Interrupt register bit masks */
2304#define USB_INTR_SUSPEND 0x01
2305#define USB_INTR_RESUME 0x02
2306#define USB_INTR_RESET 0x04
2307
2308#define USB_INTR_EP0 0x0001
2309#define USB_INTR_INEP1 0x0002
2310#define USB_INTR_INEP2 0x0004
2311#define USB_INTR_OUTEP1 0x0002
2312
2313/* CSR0 bit masks */
2314#define USB_CSR0_OUTPKTRDY 0x01
2315#define USB_CSR0_INPKTRDY 0x02
2316#define USB_CSR0_SENTSTALL 0x04
2317#define USB_CSR0_DATAEND 0x08
2318#define USB_CSR0_SETUPEND 0x10
2319#define USB_CSR0_SENDSTALL 0x20
2320#define USB_CSR0_SVDOUTPKTRDY 0x40
2321#define USB_CSR0_SVDSETUPEND 0x80
2322
2323/* Endpoint CSR register bits */
2324#define USB_INCSRH_AUTOSET 0x80
2325#define USB_INCSRH_ISO 0x40
2326#define USB_INCSRH_MODE 0x20
2327#define USB_INCSRH_DMAREQENAB 0x10
2328#define USB_INCSRH_DMAREQMODE 0x04
2329#define USB_INCSR_CDT 0x40
2330#define USB_INCSR_SENTSTALL 0x20
2331#define USB_INCSR_SENDSTALL 0x10
2332#define USB_INCSR_FF 0x08
2333#define USB_INCSR_UNDERRUN 0x04
2334#define USB_INCSR_FFNOTEMPT 0x02
2335#define USB_INCSR_INPKTRDY 0x01
2336#define USB_OUTCSRH_AUTOCLR 0x80
2337#define USB_OUTCSRH_ISO 0x40
2338#define USB_OUTCSRH_DMAREQENAB 0x20
2339#define USB_OUTCSRH_DNYT 0x10
2340#define USB_OUTCSRH_DMAREQMODE 0x08
2341#define USB_OUTCSR_CDT 0x80
2342#define USB_OUTCSR_SENTSTALL 0x40
2343#define USB_OUTCSR_SENDSTALL 0x20
2344#define USB_OUTCSR_FF 0x10
2345#define USB_OUTCSR_DATAERR 0x08
2346#define USB_OUTCSR_OVERRUN 0x04
2347#define USB_OUTCSR_FFFULL 0x02
2348#define USB_OUTCSR_OUTPKTRDY 0x01
2349
2350/* Testmode register bits */
2351#define USB_TEST_SE0NAK 0x01
2352#define USB_TEST_J 0x02
2353#define USB_TEST_K 0x04
2354#define USB_TEST_PACKET 0x08
2355
2356/* DMA control bits */
2357#define USB_CNTL_ENA 0x01
2358#define USB_CNTL_DIR_IN 0x02
2359#define USB_CNTL_MODE_1 0x04
2360#define USB_CNTL_INTR_EN 0x08
2361#define USB_CNTL_EP(n) ((n) << 4)
2362#define USB_CNTL_BURST_0 (0 << 9)
2363#define USB_CNTL_BURST_4 (1 << 9)
2364#define USB_CNTL_BURST_8 (2 << 9)
2365#define USB_CNTL_BURST_16 (3 << 9)
666/* Hibernate Wakeup Control Register */
667#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
668
669/* Hibernate Wakeup Status Register */
670#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
671#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
672#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
673#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
2366674
2367675#endif /* __JZ4740_REGS_H__ */
target/linux/xburst/files-2.6.31/arch/mips/jz4740/dma.c
1818#include <linux/spinlock.h>
1919#include <linux/interrupt.h>
2020
21#include <asm/mach-jz4740/regs.h>
2221#include <linux/dma-mapping.h>
2322#include <asm/mach-jz4740/dma.h>
24#include <linux/delay.h>
23#include <asm/mach-jz4740/regs.h>
2524
2625#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
2726#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
target/linux/xburst/files-2.6.31/arch/mips/jz4740/reset.c
1818#include <asm/reboot.h>
1919#include <asm/system.h>
2020#include <asm/mach-jz4740/regs.h>
21#include <asm/mach-jz4740/timer.h>
2122#include <asm/mach-jz4740/jz4740.h>
2223
2324void jz_restart(char *command)
...... 
2627    REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
2728    REG_WDT_TCNT = 0;
2829    REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
29    REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
30    jz4740_timer_enable_watchdog();
3031    REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
3132    while (1);
3233}
target/linux/xburst/files-2.6.31/arch/mips/jz4740/setup.c
2323#include <linux/string.h>
2424#include <linux/kernel.h>
2525#include <linux/io.h>
26#include <linux/irq.h>
2726#include <linux/ioport.h>
2827#include <linux/tty.h>
2928#include <linux/serial.h>
...... 
4140#include <asm/mach-jz4740/clock.h>
4241#include <asm/mach-jz4740/serial.h>
4342
44extern char * __init prom_getcmdline(void);
43extern char *__init prom_getcmdline(void);
4544extern void __init jz_board_setup(void);
4645extern void jz_restart(char *);
4746extern void jz_halt(void);
...... 
5756    __cpm_idle_mode();
5857}
5958
59
6060static void __init jz_serial_setup(void)
6161{
6262#ifdef CONFIG_SERIAL_8250
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.c
3737#include <asm/io.h>
3838#include <asm/irq.h>
3939#include <asm/system.h>
40#include <asm/mach-jz4740/regs.h>
4140#include <asm/mach-jz4740/clock.h>
4241
4342#include "jz4740_udc.h"
...... 
4948#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
5049#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
5150#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
52#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
51    #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
5352#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
5453#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
5554#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
...... 
7675#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
7776#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
7877
78/* Power register bit masks */
79#define USB_POWER_SUSPENDM 0x01
80#define USB_POWER_RESUME 0x04
81#define USB_POWER_HSMODE 0x10
82#define USB_POWER_HSENAB 0x20
83#define USB_POWER_SOFTCONN 0x40
84
85/* Interrupt register bit masks */
86#define USB_INTR_SUSPEND 0x01
87#define USB_INTR_RESUME 0x02
88#define USB_INTR_RESET 0x04
89
90#define USB_INTR_EP0 0x0001
91#define USB_INTR_INEP1 0x0002
92#define USB_INTR_INEP2 0x0004
93#define USB_INTR_OUTEP1 0x0002
94
95/* CSR0 bit masks */
96#define USB_CSR0_OUTPKTRDY 0x01
97#define USB_CSR0_INPKTRDY 0x02
98#define USB_CSR0_SENTSTALL 0x04
99#define USB_CSR0_DATAEND 0x08
100#define USB_CSR0_SETUPEND 0x10
101#define USB_CSR0_SENDSTALL 0x20
102#define USB_CSR0_SVDOUTPKTRDY 0x40
103#define USB_CSR0_SVDSETUPEND 0x80
104
105/* Endpoint CSR register bits */
106#define USB_INCSRH_AUTOSET 0x80
107#define USB_INCSRH_ISO 0x40
108#define USB_INCSRH_MODE 0x20
109#define USB_INCSRH_DMAREQENAB 0x10
110#define USB_INCSRH_DMAREQMODE 0x04
111#define USB_INCSR_CDT 0x40
112#define USB_INCSR_SENTSTALL 0x20
113#define USB_INCSR_SENDSTALL 0x10
114#define USB_INCSR_FF 0x08
115#define USB_INCSR_UNDERRUN 0x04
116#define USB_INCSR_FFNOTEMPT 0x02
117#define USB_INCSR_INPKTRDY 0x01
118#define USB_OUTCSRH_AUTOCLR 0x80
119#define USB_OUTCSRH_ISO 0x40
120#define USB_OUTCSRH_DMAREQENAB 0x20
121#define USB_OUTCSRH_DNYT 0x10
122#define USB_OUTCSRH_DMAREQMODE 0x08
123#define USB_OUTCSR_CDT 0x80
124#define USB_OUTCSR_SENTSTALL 0x40
125#define USB_OUTCSR_SENDSTALL 0x20
126#define USB_OUTCSR_FF 0x10
127#define USB_OUTCSR_DATAERR 0x08
128#define USB_OUTCSR_OVERRUN 0x04
129#define USB_OUTCSR_FFFULL 0x02
130#define USB_OUTCSR_OUTPKTRDY 0x01
131
132/* Testmode register bits */
133#define USB_TEST_SE0NAK 0x01
134#define USB_TEST_J 0x02
135#define USB_TEST_K 0x04
136#define USB_TEST_PACKET 0x08
137
138/* DMA control bits */
139#define USB_CNTL_ENA 0x01
140#define USB_CNTL_DIR_IN 0x02
141#define USB_CNTL_MODE_1 0x04
142#define USB_CNTL_INTR_EN 0x08
143#define USB_CNTL_EP(n) ((n) << 4)
144#define USB_CNTL_BURST_0 (0 << 9)
145#define USB_CNTL_BURST_4 (1 << 9)
146#define USB_CNTL_BURST_8 (2 << 9)
147#define USB_CNTL_BURST_16 (3 << 9)
148
149
79150#ifndef DEBUG
80151# define DEBUG(fmt,args...) do {} while(0)
81152#endif

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