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Source at commit 8007d48 created 13 years 8 months ago. By juhosg, generic: rtl8366: add common rtl8366_sw_{get,set}_vlan_ports functions | |
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1 | /* |
2 | * Platform driver for the Realtek RTL8366S ethernet switch |
3 | * |
4 | * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> |
5 | * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License version 2 as published |
9 | * by the Free Software Foundation. |
10 | */ |
11 | |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/delay.h> |
17 | #include <linux/skbuff.h> |
18 | #include <linux/rtl8366s.h> |
19 | |
20 | #include "rtl8366_smi.h" |
21 | |
22 | #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver" |
23 | #define RTL8366S_DRIVER_VER "0.2.2" |
24 | |
25 | #define RTL8366S_PHY_NO_MAX 4 |
26 | #define RTL8366S_PHY_PAGE_MAX 7 |
27 | #define RTL8366S_PHY_ADDR_MAX 31 |
28 | |
29 | /* Switch Global Configuration register */ |
30 | #define RTL8366S_SGCR 0x0000 |
31 | #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0) |
32 | #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4) |
33 | #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3) |
34 | #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0) |
35 | #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1) |
36 | #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2) |
37 | #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3) |
38 | #define RTL8366S_SGCR_EN_VLAN BIT(13) |
39 | |
40 | /* Port Enable Control register */ |
41 | #define RTL8366S_PECR 0x0001 |
42 | |
43 | /* Switch Security Control registers */ |
44 | #define RTL8366S_SSCR0 0x0002 |
45 | #define RTL8366S_SSCR1 0x0003 |
46 | #define RTL8366S_SSCR2 0x0004 |
47 | #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0) |
48 | |
49 | #define RTL8366S_RESET_CTRL_REG 0x0100 |
50 | #define RTL8366S_CHIP_CTRL_RESET_HW 1 |
51 | #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1) |
52 | |
53 | #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104 |
54 | #define RTL8366S_CHIP_VERSION_MASK 0xf |
55 | #define RTL8366S_CHIP_ID_REG 0x0105 |
56 | #define RTL8366S_CHIP_ID_8366 0x8366 |
57 | |
58 | /* PHY registers control */ |
59 | #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028 |
60 | #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029 |
61 | |
62 | #define RTL8366S_PHY_CTRL_READ 1 |
63 | #define RTL8366S_PHY_CTRL_WRITE 0 |
64 | |
65 | #define RTL8366S_PHY_REG_MASK 0x1f |
66 | #define RTL8366S_PHY_PAGE_OFFSET 5 |
67 | #define RTL8366S_PHY_PAGE_MASK (0x7 << 5) |
68 | #define RTL8366S_PHY_NO_OFFSET 9 |
69 | #define RTL8366S_PHY_NO_MASK (0x1f << 9) |
70 | |
71 | /* LED control registers */ |
72 | #define RTL8366S_LED_BLINKRATE_REG 0x0420 |
73 | #define RTL8366S_LED_BLINKRATE_BIT 0 |
74 | #define RTL8366S_LED_BLINKRATE_MASK 0x0007 |
75 | |
76 | #define RTL8366S_LED_CTRL_REG 0x0421 |
77 | #define RTL8366S_LED_0_1_CTRL_REG 0x0422 |
78 | #define RTL8366S_LED_2_3_CTRL_REG 0x0423 |
79 | |
80 | #define RTL8366S_MIB_COUNT 33 |
81 | #define RTL8366S_GLOBAL_MIB_COUNT 1 |
82 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040 |
83 | #define RTL8366S_MIB_COUNTER_BASE 0x1000 |
84 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008 |
85 | #define RTL8366S_MIB_COUNTER_BASE2 0x1180 |
86 | #define RTL8366S_MIB_CTRL_REG 0x11F0 |
87 | #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF |
88 | #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001 |
89 | #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002 |
90 | |
91 | #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004 |
92 | #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003 |
93 | #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC |
94 | |
95 | |
96 | #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058 |
97 | #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \ |
98 | (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4) |
99 | #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf |
100 | #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) |
101 | |
102 | |
103 | #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B |
104 | #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185 |
105 | |
106 | #define RTL8366S_VLAN_TB_CTRL_REG 0x010F |
107 | |
108 | #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180 |
109 | #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01 |
110 | #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01 |
111 | |
112 | #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2) |
113 | |
114 | #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379 |
115 | |
116 | #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060 |
117 | #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003 |
118 | #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004 |
119 | #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010 |
120 | #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020 |
121 | #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040 |
122 | #define RTL8366S_PORT_STATUS_AN_MASK 0x0080 |
123 | |
124 | |
125 | #define RTL8366S_PORT_NUM_CPU 5 |
126 | #define RTL8366S_NUM_PORTS 6 |
127 | #define RTL8366S_NUM_VLANS 16 |
128 | #define RTL8366S_NUM_LEDGROUPS 4 |
129 | #define RTL8366S_NUM_VIDS 4096 |
130 | #define RTL8366S_PRIORITYMAX 7 |
131 | #define RTL8366S_FIDMAX 7 |
132 | |
133 | |
134 | #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */ |
135 | #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */ |
136 | #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */ |
137 | #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */ |
138 | |
139 | #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */ |
140 | #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */ |
141 | |
142 | #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \ |
143 | RTL8366S_PORT_2 | \ |
144 | RTL8366S_PORT_3 | \ |
145 | RTL8366S_PORT_4 | \ |
146 | RTL8366S_PORT_UNKNOWN | \ |
147 | RTL8366S_PORT_CPU) |
148 | |
149 | #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \ |
150 | RTL8366S_PORT_2 | \ |
151 | RTL8366S_PORT_3 | \ |
152 | RTL8366S_PORT_4 | \ |
153 | RTL8366S_PORT_UNKNOWN) |
154 | |
155 | #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \ |
156 | RTL8366S_PORT_2 | \ |
157 | RTL8366S_PORT_3 | \ |
158 | RTL8366S_PORT_4) |
159 | |
160 | #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \ |
161 | RTL8366S_PORT_CPU) |
162 | |
163 | #define RTL8366S_VLAN_VID_MASK 0xfff |
164 | #define RTL8366S_VLAN_PRIORITY_SHIFT 12 |
165 | #define RTL8366S_VLAN_PRIORITY_MASK 0x7 |
166 | #define RTL8366S_VLAN_MEMBER_MASK 0x3f |
167 | #define RTL8366S_VLAN_UNTAG_SHIFT 6 |
168 | #define RTL8366S_VLAN_UNTAG_MASK 0x3f |
169 | #define RTL8366S_VLAN_FID_SHIFT 12 |
170 | #define RTL8366S_VLAN_FID_MASK 0x7 |
171 | |
172 | static struct rtl8366_mib_counter rtl8366s_mib_counters[] = { |
173 | { 0, 0, 4, "IfInOctets" }, |
174 | { 0, 4, 4, "EtherStatsOctets" }, |
175 | { 0, 8, 2, "EtherStatsUnderSizePkts" }, |
176 | { 0, 10, 2, "EtherFragments" }, |
177 | { 0, 12, 2, "EtherStatsPkts64Octets" }, |
178 | { 0, 14, 2, "EtherStatsPkts65to127Octets" }, |
179 | { 0, 16, 2, "EtherStatsPkts128to255Octets" }, |
180 | { 0, 18, 2, "EtherStatsPkts256to511Octets" }, |
181 | { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, |
182 | { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, |
183 | { 0, 24, 2, "EtherOversizeStats" }, |
184 | { 0, 26, 2, "EtherStatsJabbers" }, |
185 | { 0, 28, 2, "IfInUcastPkts" }, |
186 | { 0, 30, 2, "EtherStatsMulticastPkts" }, |
187 | { 0, 32, 2, "EtherStatsBroadcastPkts" }, |
188 | { 0, 34, 2, "EtherStatsDropEvents" }, |
189 | { 0, 36, 2, "Dot3StatsFCSErrors" }, |
190 | { 0, 38, 2, "Dot3StatsSymbolErrors" }, |
191 | { 0, 40, 2, "Dot3InPauseFrames" }, |
192 | { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, |
193 | { 0, 44, 4, "IfOutOctets" }, |
194 | { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, |
195 | { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, |
196 | { 0, 52, 2, "Dot3sDeferredTransmissions" }, |
197 | { 0, 54, 2, "Dot3StatsLateCollisions" }, |
198 | { 0, 56, 2, "EtherStatsCollisions" }, |
199 | { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, |
200 | { 0, 60, 2, "Dot3OutPauseFrames" }, |
201 | { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, |
202 | |
203 | /* |
204 | * The following counters are accessible at a different |
205 | * base address. |
206 | */ |
207 | { 1, 0, 2, "Dot1dTpPortInDiscards" }, |
208 | { 1, 2, 2, "IfOutUcastPkts" }, |
209 | { 1, 4, 2, "IfOutMulticastPkts" }, |
210 | { 1, 6, 2, "IfOutBroadcastPkts" }, |
211 | }; |
212 | |
213 | #define REG_WR(_smi, _reg, _val) \ |
214 | do { \ |
215 | err = rtl8366_smi_write_reg(_smi, _reg, _val); \ |
216 | if (err) \ |
217 | return err; \ |
218 | } while (0) |
219 | |
220 | #define REG_RMW(_smi, _reg, _mask, _val) \ |
221 | do { \ |
222 | err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ |
223 | if (err) \ |
224 | return err; \ |
225 | } while (0) |
226 | |
227 | static int rtl8366s_reset_chip(struct rtl8366_smi *smi) |
228 | { |
229 | int timeout = 10; |
230 | u32 data; |
231 | |
232 | rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG, |
233 | RTL8366S_CHIP_CTRL_RESET_HW); |
234 | do { |
235 | msleep(1); |
236 | if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data)) |
237 | return -EIO; |
238 | |
239 | if (!(data & RTL8366S_CHIP_CTRL_RESET_HW)) |
240 | break; |
241 | } while (--timeout); |
242 | |
243 | if (!timeout) { |
244 | printk("Timeout waiting for the switch to reset\n"); |
245 | return -EIO; |
246 | } |
247 | |
248 | return 0; |
249 | } |
250 | |
251 | static int rtl8366s_hw_init(struct rtl8366_smi *smi) |
252 | { |
253 | int err; |
254 | |
255 | /* set maximum packet length to 1536 bytes */ |
256 | REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK, |
257 | RTL8366S_SGCR_MAX_LENGTH_1536); |
258 | |
259 | /* enable all ports */ |
260 | REG_WR(smi, RTL8366S_PECR, 0); |
261 | |
262 | /* disable learning for all ports */ |
263 | REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL); |
264 | |
265 | /* disable auto ageing for all ports */ |
266 | REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL); |
267 | |
268 | /* |
269 | * discard VLAN tagged packets if the port is not a member of |
270 | * the VLAN with which the packets is associated. |
271 | */ |
272 | REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL); |
273 | |
274 | /* don't drop packets whose DA has not been learned */ |
275 | REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0); |
276 | |
277 | return 0; |
278 | } |
279 | |
280 | static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, |
281 | u32 phy_no, u32 page, u32 addr, u32 *data) |
282 | { |
283 | u32 reg; |
284 | int ret; |
285 | |
286 | if (phy_no > RTL8366S_PHY_NO_MAX) |
287 | return -EINVAL; |
288 | |
289 | if (page > RTL8366S_PHY_PAGE_MAX) |
290 | return -EINVAL; |
291 | |
292 | if (addr > RTL8366S_PHY_ADDR_MAX) |
293 | return -EINVAL; |
294 | |
295 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
296 | RTL8366S_PHY_CTRL_READ); |
297 | if (ret) |
298 | return ret; |
299 | |
300 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
301 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
302 | (addr & RTL8366S_PHY_REG_MASK); |
303 | |
304 | ret = rtl8366_smi_write_reg(smi, reg, 0); |
305 | if (ret) |
306 | return ret; |
307 | |
308 | ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data); |
309 | if (ret) |
310 | return ret; |
311 | |
312 | return 0; |
313 | } |
314 | |
315 | static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi, |
316 | u32 phy_no, u32 page, u32 addr, u32 data) |
317 | { |
318 | u32 reg; |
319 | int ret; |
320 | |
321 | if (phy_no > RTL8366S_PHY_NO_MAX) |
322 | return -EINVAL; |
323 | |
324 | if (page > RTL8366S_PHY_PAGE_MAX) |
325 | return -EINVAL; |
326 | |
327 | if (addr > RTL8366S_PHY_ADDR_MAX) |
328 | return -EINVAL; |
329 | |
330 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
331 | RTL8366S_PHY_CTRL_WRITE); |
332 | if (ret) |
333 | return ret; |
334 | |
335 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
336 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
337 | (addr & RTL8366S_PHY_REG_MASK); |
338 | |
339 | ret = rtl8366_smi_write_reg(smi, reg, data); |
340 | if (ret) |
341 | return ret; |
342 | |
343 | return 0; |
344 | } |
345 | |
346 | static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, |
347 | int port, unsigned long long *val) |
348 | { |
349 | int i; |
350 | int err; |
351 | u32 addr, data; |
352 | u64 mibvalue; |
353 | |
354 | if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT) |
355 | return -EINVAL; |
356 | |
357 | switch (rtl8366s_mib_counters[counter].base) { |
358 | case 0: |
359 | addr = RTL8366S_MIB_COUNTER_BASE + |
360 | RTL8366S_MIB_COUNTER_PORT_OFFSET * port; |
361 | break; |
362 | |
363 | case 1: |
364 | addr = RTL8366S_MIB_COUNTER_BASE2 + |
365 | RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port; |
366 | break; |
367 | |
368 | default: |
369 | return -EINVAL; |
370 | } |
371 | |
372 | addr += rtl8366s_mib_counters[counter].offset; |
373 | |
374 | /* |
375 | * Writing access counter address first |
376 | * then ASIC will prepare 64bits counter wait for being retrived |
377 | */ |
378 | data = 0; /* writing data will be discard by ASIC */ |
379 | err = rtl8366_smi_write_reg(smi, addr, data); |
380 | if (err) |
381 | return err; |
382 | |
383 | /* read MIB control register */ |
384 | err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data); |
385 | if (err) |
386 | return err; |
387 | |
388 | if (data & RTL8366S_MIB_CTRL_BUSY_MASK) |
389 | return -EBUSY; |
390 | |
391 | if (data & RTL8366S_MIB_CTRL_RESET_MASK) |
392 | return -EIO; |
393 | |
394 | mibvalue = 0; |
395 | for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) { |
396 | err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data); |
397 | if (err) |
398 | return err; |
399 | |
400 | mibvalue = (mibvalue << 16) | (data & 0xFFFF); |
401 | } |
402 | |
403 | *val = mibvalue; |
404 | return 0; |
405 | } |
406 | |
407 | static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, |
408 | struct rtl8366_vlan_4k *vlan4k) |
409 | { |
410 | u32 data[2]; |
411 | int err; |
412 | int i; |
413 | |
414 | memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); |
415 | |
416 | if (vid >= RTL8366S_NUM_VIDS) |
417 | return -EINVAL; |
418 | |
419 | /* write VID */ |
420 | err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, |
421 | vid & RTL8366S_VLAN_VID_MASK); |
422 | if (err) |
423 | return err; |
424 | |
425 | /* write table access control word */ |
426 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
427 | RTL8366S_TABLE_VLAN_READ_CTRL); |
428 | if (err) |
429 | return err; |
430 | |
431 | for (i = 0; i < 2; i++) { |
432 | err = rtl8366_smi_read_reg(smi, |
433 | RTL8366S_VLAN_TABLE_READ_BASE + i, |
434 | &data[i]); |
435 | if (err) |
436 | return err; |
437 | } |
438 | |
439 | vlan4k->vid = vid; |
440 | vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
441 | RTL8366S_VLAN_UNTAG_MASK; |
442 | vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
443 | vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
444 | RTL8366S_VLAN_FID_MASK; |
445 | |
446 | return 0; |
447 | } |
448 | |
449 | static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi, |
450 | const struct rtl8366_vlan_4k *vlan4k) |
451 | { |
452 | u32 data[2]; |
453 | int err; |
454 | int i; |
455 | |
456 | if (vlan4k->vid >= RTL8366S_NUM_VIDS || |
457 | vlan4k->member > RTL8366S_PORT_ALL || |
458 | vlan4k->untag > RTL8366S_PORT_ALL || |
459 | vlan4k->fid > RTL8366S_FIDMAX) |
460 | return -EINVAL; |
461 | |
462 | data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK; |
463 | data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) | |
464 | ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) << |
465 | RTL8366S_VLAN_UNTAG_SHIFT) | |
466 | ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) << |
467 | RTL8366S_VLAN_FID_SHIFT); |
468 | |
469 | for (i = 0; i < 2; i++) { |
470 | err = rtl8366_smi_write_reg(smi, |
471 | RTL8366S_VLAN_TABLE_WRITE_BASE + i, |
472 | data[i]); |
473 | if (err) |
474 | return err; |
475 | } |
476 | |
477 | /* write table access control word */ |
478 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
479 | RTL8366S_TABLE_VLAN_WRITE_CTRL); |
480 | |
481 | return err; |
482 | } |
483 | |
484 | static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
485 | struct rtl8366_vlan_mc *vlanmc) |
486 | { |
487 | u32 data[2]; |
488 | int err; |
489 | int i; |
490 | |
491 | memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); |
492 | |
493 | if (index >= RTL8366S_NUM_VLANS) |
494 | return -EINVAL; |
495 | |
496 | for (i = 0; i < 2; i++) { |
497 | err = rtl8366_smi_read_reg(smi, |
498 | RTL8366S_VLAN_MC_BASE(index) + i, |
499 | &data[i]); |
500 | if (err) |
501 | return err; |
502 | } |
503 | |
504 | vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK; |
505 | vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) & |
506 | RTL8366S_VLAN_PRIORITY_MASK; |
507 | vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
508 | RTL8366S_VLAN_UNTAG_MASK; |
509 | vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
510 | vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
511 | RTL8366S_VLAN_FID_MASK; |
512 | |
513 | return 0; |
514 | } |
515 | |
516 | static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
517 | const struct rtl8366_vlan_mc *vlanmc) |
518 | { |
519 | u32 data[2]; |
520 | int err; |
521 | int i; |
522 | |
523 | if (index >= RTL8366S_NUM_VLANS || |
524 | vlanmc->vid >= RTL8366S_NUM_VIDS || |
525 | vlanmc->priority > RTL8366S_PRIORITYMAX || |
526 | vlanmc->member > RTL8366S_PORT_ALL || |
527 | vlanmc->untag > RTL8366S_PORT_ALL || |
528 | vlanmc->fid > RTL8366S_FIDMAX) |
529 | return -EINVAL; |
530 | |
531 | data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) | |
532 | ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) << |
533 | RTL8366S_VLAN_PRIORITY_SHIFT); |
534 | data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) | |
535 | ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) << |
536 | RTL8366S_VLAN_UNTAG_SHIFT) | |
537 | ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) << |
538 | RTL8366S_VLAN_FID_SHIFT); |
539 | |
540 | for (i = 0; i < 2; i++) { |
541 | err = rtl8366_smi_write_reg(smi, |
542 | RTL8366S_VLAN_MC_BASE(index) + i, |
543 | data[i]); |
544 | if (err) |
545 | return err; |
546 | } |
547 | |
548 | return 0; |
549 | } |
550 | |
551 | static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val) |
552 | { |
553 | u32 data; |
554 | int err; |
555 | |
556 | if (port >= RTL8366S_NUM_PORTS) |
557 | return -EINVAL; |
558 | |
559 | err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
560 | &data); |
561 | if (err) |
562 | return err; |
563 | |
564 | *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) & |
565 | RTL8366S_PORT_VLAN_CTRL_MASK; |
566 | |
567 | return 0; |
568 | } |
569 | |
570 | static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index) |
571 | { |
572 | if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS) |
573 | return -EINVAL; |
574 | |
575 | return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
576 | RTL8366S_PORT_VLAN_CTRL_MASK << |
577 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port), |
578 | (index & RTL8366S_PORT_VLAN_CTRL_MASK) << |
579 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port)); |
580 | } |
581 | |
582 | static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable) |
583 | { |
584 | return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN, |
585 | (enable) ? RTL8366S_SGCR_EN_VLAN : 0); |
586 | } |
587 | |
588 | static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable) |
589 | { |
590 | return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG, |
591 | 1, (enable) ? 1 : 0); |
592 | } |
593 | |
594 | static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) |
595 | { |
596 | if (vlan == 0 || vlan >= RTL8366S_NUM_VLANS) |
597 | return 0; |
598 | |
599 | return 1; |
600 | } |
601 | |
602 | static int rtl8366s_sw_reset_mibs(struct switch_dev *dev, |
603 | const struct switch_attr *attr, |
604 | struct switch_val *val) |
605 | { |
606 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
607 | |
608 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2)); |
609 | } |
610 | |
611 | static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev, |
612 | const struct switch_attr *attr, |
613 | struct switch_val *val) |
614 | { |
615 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
616 | u32 data; |
617 | |
618 | if (attr->ofs == 1) { |
619 | rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data); |
620 | |
621 | if (data & RTL8366S_SGCR_EN_VLAN) |
622 | val->value.i = 1; |
623 | else |
624 | val->value.i = 0; |
625 | } else if (attr->ofs == 2) { |
626 | rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data); |
627 | |
628 | if (data & 0x0001) |
629 | val->value.i = 1; |
630 | else |
631 | val->value.i = 0; |
632 | } |
633 | |
634 | return 0; |
635 | } |
636 | |
637 | static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev, |
638 | const struct switch_attr *attr, |
639 | struct switch_val *val) |
640 | { |
641 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
642 | u32 data; |
643 | |
644 | rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data); |
645 | |
646 | val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK)); |
647 | |
648 | return 0; |
649 | } |
650 | |
651 | static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev, |
652 | const struct switch_attr *attr, |
653 | struct switch_val *val) |
654 | { |
655 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
656 | |
657 | if (val->value.i >= 6) |
658 | return -EINVAL; |
659 | |
660 | return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, |
661 | RTL8366S_LED_BLINKRATE_MASK, |
662 | val->value.i); |
663 | } |
664 | |
665 | static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev, |
666 | const struct switch_attr *attr, |
667 | struct switch_val *val) |
668 | { |
669 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
670 | |
671 | if (attr->ofs == 1) |
672 | return rtl8366s_vlan_set_vlan(smi, val->value.i); |
673 | else |
674 | return rtl8366s_vlan_set_4ktable(smi, val->value.i); |
675 | } |
676 | |
677 | static const char *rtl8366s_speed_str(unsigned speed) |
678 | { |
679 | switch (speed) { |
680 | case 0: |
681 | return "10baseT"; |
682 | case 1: |
683 | return "100baseT"; |
684 | case 2: |
685 | return "1000baseT"; |
686 | } |
687 | |
688 | return "unknown"; |
689 | } |
690 | |
691 | static int rtl8366s_sw_get_port_link(struct switch_dev *dev, |
692 | const struct switch_attr *attr, |
693 | struct switch_val *val) |
694 | { |
695 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
696 | u32 len = 0, data = 0; |
697 | |
698 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
699 | return -EINVAL; |
700 | |
701 | memset(smi->buf, '\0', sizeof(smi->buf)); |
702 | rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + |
703 | (val->port_vlan / 2), &data); |
704 | |
705 | if (val->port_vlan % 2) |
706 | data = data >> 8; |
707 | |
708 | if (data & RTL8366S_PORT_STATUS_LINK_MASK) { |
709 | len = snprintf(smi->buf, sizeof(smi->buf), |
710 | "port:%d link:up speed:%s %s-duplex %s%s%s", |
711 | val->port_vlan, |
712 | rtl8366s_speed_str(data & |
713 | RTL8366S_PORT_STATUS_SPEED_MASK), |
714 | (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ? |
715 | "full" : "half", |
716 | (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ? |
717 | "tx-pause ": "", |
718 | (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ? |
719 | "rx-pause " : "", |
720 | (data & RTL8366S_PORT_STATUS_AN_MASK) ? |
721 | "nway ": ""); |
722 | } else { |
723 | len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down", |
724 | val->port_vlan); |
725 | } |
726 | |
727 | val->value.s = smi->buf; |
728 | val->len = len; |
729 | |
730 | return 0; |
731 | } |
732 | |
733 | static int rtl8366s_sw_set_port_led(struct switch_dev *dev, |
734 | const struct switch_attr *attr, |
735 | struct switch_val *val) |
736 | { |
737 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
738 | u32 data; |
739 | u32 mask; |
740 | u32 reg; |
741 | |
742 | if (val->port_vlan >= RTL8366S_NUM_PORTS || |
743 | (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN) |
744 | return -EINVAL; |
745 | |
746 | if (val->port_vlan == RTL8366S_PORT_NUM_CPU) { |
747 | reg = RTL8366S_LED_BLINKRATE_REG; |
748 | mask = 0xF << 4; |
749 | data = val->value.i << 4; |
750 | } else { |
751 | reg = RTL8366S_LED_CTRL_REG; |
752 | mask = 0xF << (val->port_vlan * 4), |
753 | data = val->value.i << (val->port_vlan * 4); |
754 | } |
755 | |
756 | return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data); |
757 | } |
758 | |
759 | static int rtl8366s_sw_get_port_led(struct switch_dev *dev, |
760 | const struct switch_attr *attr, |
761 | struct switch_val *val) |
762 | { |
763 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
764 | u32 data = 0; |
765 | |
766 | if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS) |
767 | return -EINVAL; |
768 | |
769 | rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data); |
770 | val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; |
771 | |
772 | return 0; |
773 | } |
774 | |
775 | static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev, |
776 | const struct switch_attr *attr, |
777 | struct switch_val *val) |
778 | { |
779 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
780 | |
781 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
782 | return -EINVAL; |
783 | |
784 | |
785 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, |
786 | 0, (1 << (val->port_vlan + 3))); |
787 | } |
788 | |
789 | static int rtl8366s_sw_reset_switch(struct switch_dev *dev) |
790 | { |
791 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
792 | int err; |
793 | |
794 | err = rtl8366s_reset_chip(smi); |
795 | if (err) |
796 | return err; |
797 | |
798 | err = rtl8366s_hw_init(smi); |
799 | if (err) |
800 | return err; |
801 | |
802 | return rtl8366_reset_vlan(smi); |
803 | } |
804 | |
805 | static struct switch_attr rtl8366s_globals[] = { |
806 | { |
807 | .type = SWITCH_TYPE_INT, |
808 | .name = "enable_vlan", |
809 | .description = "Enable VLAN mode", |
810 | .set = rtl8366s_sw_set_vlan_enable, |
811 | .get = rtl8366s_sw_get_vlan_enable, |
812 | .max = 1, |
813 | .ofs = 1 |
814 | }, { |
815 | .type = SWITCH_TYPE_INT, |
816 | .name = "enable_vlan4k", |
817 | .description = "Enable VLAN 4K mode", |
818 | .set = rtl8366s_sw_set_vlan_enable, |
819 | .get = rtl8366s_sw_get_vlan_enable, |
820 | .max = 1, |
821 | .ofs = 2 |
822 | }, { |
823 | .type = SWITCH_TYPE_NOVAL, |
824 | .name = "reset_mibs", |
825 | .description = "Reset all MIB counters", |
826 | .set = rtl8366s_sw_reset_mibs, |
827 | }, { |
828 | .type = SWITCH_TYPE_INT, |
829 | .name = "blinkrate", |
830 | .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms," |
831 | " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)", |
832 | .set = rtl8366s_sw_set_blinkrate, |
833 | .get = rtl8366s_sw_get_blinkrate, |
834 | .max = 5 |
835 | }, |
836 | }; |
837 | |
838 | static struct switch_attr rtl8366s_port[] = { |
839 | { |
840 | .type = SWITCH_TYPE_STRING, |
841 | .name = "link", |
842 | .description = "Get port link information", |
843 | .max = 1, |
844 | .set = NULL, |
845 | .get = rtl8366s_sw_get_port_link, |
846 | }, { |
847 | .type = SWITCH_TYPE_NOVAL, |
848 | .name = "reset_mib", |
849 | .description = "Reset single port MIB counters", |
850 | .set = rtl8366s_sw_reset_port_mibs, |
851 | }, { |
852 | .type = SWITCH_TYPE_STRING, |
853 | .name = "mib", |
854 | .description = "Get MIB counters for port", |
855 | .max = 33, |
856 | .set = NULL, |
857 | .get = rtl8366_sw_get_port_mib, |
858 | }, { |
859 | .type = SWITCH_TYPE_INT, |
860 | .name = "led", |
861 | .description = "Get/Set port group (0 - 3) led mode (0 - 15)", |
862 | .max = 15, |
863 | .set = rtl8366s_sw_set_port_led, |
864 | .get = rtl8366s_sw_get_port_led, |
865 | }, |
866 | }; |
867 | |
868 | static struct switch_attr rtl8366s_vlan[] = { |
869 | { |
870 | .type = SWITCH_TYPE_STRING, |
871 | .name = "info", |
872 | .description = "Get vlan information", |
873 | .max = 1, |
874 | .set = NULL, |
875 | .get = rtl8366_sw_get_vlan_info, |
876 | }, |
877 | }; |
878 | |
879 | /* template */ |
880 | static struct switch_dev rtl8366_switch_dev = { |
881 | .name = "RTL8366S", |
882 | .cpu_port = RTL8366S_PORT_NUM_CPU, |
883 | .ports = RTL8366S_NUM_PORTS, |
884 | .vlans = RTL8366S_NUM_VLANS, |
885 | .attr_global = { |
886 | .attr = rtl8366s_globals, |
887 | .n_attr = ARRAY_SIZE(rtl8366s_globals), |
888 | }, |
889 | .attr_port = { |
890 | .attr = rtl8366s_port, |
891 | .n_attr = ARRAY_SIZE(rtl8366s_port), |
892 | }, |
893 | .attr_vlan = { |
894 | .attr = rtl8366s_vlan, |
895 | .n_attr = ARRAY_SIZE(rtl8366s_vlan), |
896 | }, |
897 | |
898 | .get_vlan_ports = rtl8366_sw_get_vlan_ports, |
899 | .set_vlan_ports = rtl8366_sw_set_vlan_ports, |
900 | .get_port_pvid = rtl8366_sw_get_port_pvid, |
901 | .set_port_pvid = rtl8366_sw_set_port_pvid, |
902 | .reset_switch = rtl8366s_sw_reset_switch, |
903 | }; |
904 | |
905 | static int rtl8366s_switch_init(struct rtl8366_smi *smi) |
906 | { |
907 | struct switch_dev *dev = &smi->sw_dev; |
908 | int err; |
909 | |
910 | memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev)); |
911 | dev->priv = smi; |
912 | dev->devname = dev_name(smi->parent); |
913 | |
914 | err = register_switch(dev, NULL); |
915 | if (err) |
916 | dev_err(smi->parent, "switch registration failed\n"); |
917 | |
918 | return err; |
919 | } |
920 | |
921 | static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi) |
922 | { |
923 | unregister_switch(&smi->sw_dev); |
924 | } |
925 | |
926 | static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg) |
927 | { |
928 | struct rtl8366_smi *smi = bus->priv; |
929 | u32 val = 0; |
930 | int err; |
931 | |
932 | err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val); |
933 | if (err) |
934 | return 0xffff; |
935 | |
936 | return val; |
937 | } |
938 | |
939 | static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) |
940 | { |
941 | struct rtl8366_smi *smi = bus->priv; |
942 | u32 t; |
943 | int err; |
944 | |
945 | err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val); |
946 | /* flush write */ |
947 | (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t); |
948 | |
949 | return err; |
950 | } |
951 | |
952 | static int rtl8366s_mii_bus_match(struct mii_bus *bus) |
953 | { |
954 | return (bus->read == rtl8366s_mii_read && |
955 | bus->write == rtl8366s_mii_write); |
956 | } |
957 | |
958 | static int rtl8366s_setup(struct rtl8366_smi *smi) |
959 | { |
960 | int ret; |
961 | |
962 | ret = rtl8366s_reset_chip(smi); |
963 | if (ret) |
964 | return ret; |
965 | |
966 | ret = rtl8366s_hw_init(smi); |
967 | return ret; |
968 | } |
969 | |
970 | static int rtl8366s_detect(struct rtl8366_smi *smi) |
971 | { |
972 | u32 chip_id = 0; |
973 | u32 chip_ver = 0; |
974 | int ret; |
975 | |
976 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id); |
977 | if (ret) { |
978 | dev_err(smi->parent, "unable to read chip id\n"); |
979 | return ret; |
980 | } |
981 | |
982 | switch (chip_id) { |
983 | case RTL8366S_CHIP_ID_8366: |
984 | break; |
985 | default: |
986 | dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); |
987 | return -ENODEV; |
988 | } |
989 | |
990 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG, |
991 | &chip_ver); |
992 | if (ret) { |
993 | dev_err(smi->parent, "unable to read chip version\n"); |
994 | return ret; |
995 | } |
996 | |
997 | dev_info(smi->parent, "RTL%04x ver. %u chip found\n", |
998 | chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK); |
999 | |
1000 | return 0; |
1001 | } |
1002 | |
1003 | static struct rtl8366_smi_ops rtl8366s_smi_ops = { |
1004 | .detect = rtl8366s_detect, |
1005 | .setup = rtl8366s_setup, |
1006 | |
1007 | .mii_read = rtl8366s_mii_read, |
1008 | .mii_write = rtl8366s_mii_write, |
1009 | |
1010 | .get_vlan_mc = rtl8366s_get_vlan_mc, |
1011 | .set_vlan_mc = rtl8366s_set_vlan_mc, |
1012 | .get_vlan_4k = rtl8366s_get_vlan_4k, |
1013 | .set_vlan_4k = rtl8366s_set_vlan_4k, |
1014 | .get_mc_index = rtl8366s_get_mc_index, |
1015 | .set_mc_index = rtl8366s_set_mc_index, |
1016 | .get_mib_counter = rtl8366_get_mib_counter, |
1017 | .is_vlan_valid = rtl8366s_is_vlan_valid, |
1018 | }; |
1019 | |
1020 | static int __init rtl8366s_probe(struct platform_device *pdev) |
1021 | { |
1022 | static int rtl8366_smi_version_printed; |
1023 | struct rtl8366s_platform_data *pdata; |
1024 | struct rtl8366_smi *smi; |
1025 | int err; |
1026 | |
1027 | if (!rtl8366_smi_version_printed++) |
1028 | printk(KERN_NOTICE RTL8366S_DRIVER_DESC |
1029 | " version " RTL8366S_DRIVER_VER"\n"); |
1030 | |
1031 | pdata = pdev->dev.platform_data; |
1032 | if (!pdata) { |
1033 | dev_err(&pdev->dev, "no platform data specified\n"); |
1034 | err = -EINVAL; |
1035 | goto err_out; |
1036 | } |
1037 | |
1038 | smi = rtl8366_smi_alloc(&pdev->dev); |
1039 | if (!smi) { |
1040 | err = -ENOMEM; |
1041 | goto err_out; |
1042 | } |
1043 | |
1044 | smi->gpio_sda = pdata->gpio_sda; |
1045 | smi->gpio_sck = pdata->gpio_sck; |
1046 | smi->ops = &rtl8366s_smi_ops; |
1047 | smi->cpu_port = RTL8366S_PORT_NUM_CPU; |
1048 | smi->num_ports = RTL8366S_NUM_PORTS; |
1049 | smi->num_vlan_mc = RTL8366S_NUM_VLANS; |
1050 | smi->mib_counters = rtl8366s_mib_counters; |
1051 | smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters); |
1052 | |
1053 | err = rtl8366_smi_init(smi); |
1054 | if (err) |
1055 | goto err_free_smi; |
1056 | |
1057 | platform_set_drvdata(pdev, smi); |
1058 | |
1059 | err = rtl8366s_switch_init(smi); |
1060 | if (err) |
1061 | goto err_clear_drvdata; |
1062 | |
1063 | return 0; |
1064 | |
1065 | err_clear_drvdata: |
1066 | platform_set_drvdata(pdev, NULL); |
1067 | rtl8366_smi_cleanup(smi); |
1068 | err_free_smi: |
1069 | kfree(smi); |
1070 | err_out: |
1071 | return err; |
1072 | } |
1073 | |
1074 | static int rtl8366s_phy_config_init(struct phy_device *phydev) |
1075 | { |
1076 | if (!rtl8366s_mii_bus_match(phydev->bus)) |
1077 | return -EINVAL; |
1078 | |
1079 | return 0; |
1080 | } |
1081 | |
1082 | static int rtl8366s_phy_config_aneg(struct phy_device *phydev) |
1083 | { |
1084 | return 0; |
1085 | } |
1086 | |
1087 | static struct phy_driver rtl8366s_phy_driver = { |
1088 | .phy_id = 0x001cc960, |
1089 | .name = "Realtek RTL8366S", |
1090 | .phy_id_mask = 0x1ffffff0, |
1091 | .features = PHY_GBIT_FEATURES, |
1092 | .config_aneg = rtl8366s_phy_config_aneg, |
1093 | .config_init = rtl8366s_phy_config_init, |
1094 | .read_status = genphy_read_status, |
1095 | .driver = { |
1096 | .owner = THIS_MODULE, |
1097 | }, |
1098 | }; |
1099 | |
1100 | static int __devexit rtl8366s_remove(struct platform_device *pdev) |
1101 | { |
1102 | struct rtl8366_smi *smi = platform_get_drvdata(pdev); |
1103 | |
1104 | if (smi) { |
1105 | rtl8366s_switch_cleanup(smi); |
1106 | platform_set_drvdata(pdev, NULL); |
1107 | rtl8366_smi_cleanup(smi); |
1108 | kfree(smi); |
1109 | } |
1110 | |
1111 | return 0; |
1112 | } |
1113 | |
1114 | static struct platform_driver rtl8366s_driver = { |
1115 | .driver = { |
1116 | .name = RTL8366S_DRIVER_NAME, |
1117 | .owner = THIS_MODULE, |
1118 | }, |
1119 | .probe = rtl8366s_probe, |
1120 | .remove = __devexit_p(rtl8366s_remove), |
1121 | }; |
1122 | |
1123 | static int __init rtl8366s_module_init(void) |
1124 | { |
1125 | int ret; |
1126 | ret = platform_driver_register(&rtl8366s_driver); |
1127 | if (ret) |
1128 | return ret; |
1129 | |
1130 | ret = phy_driver_register(&rtl8366s_phy_driver); |
1131 | if (ret) |
1132 | goto err_platform_unregister; |
1133 | |
1134 | return 0; |
1135 | |
1136 | err_platform_unregister: |
1137 | platform_driver_unregister(&rtl8366s_driver); |
1138 | return ret; |
1139 | } |
1140 | module_init(rtl8366s_module_init); |
1141 | |
1142 | static void __exit rtl8366s_module_exit(void) |
1143 | { |
1144 | phy_driver_unregister(&rtl8366s_phy_driver); |
1145 | platform_driver_unregister(&rtl8366s_driver); |
1146 | } |
1147 | module_exit(rtl8366s_module_exit); |
1148 | |
1149 | MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC); |
1150 | MODULE_VERSION(RTL8366S_DRIVER_VER); |
1151 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
1152 | MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>"); |
1153 | MODULE_LICENSE("GPL v2"); |
1154 | MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME); |
1155 |