Root/package/uboot-xburst/files/include/configs/nanonote.h

Source at commit 8eccd43ba2bd33f91b2373704c4ecd36cf3f5ba5 created 8 years 11 months ago.
By Xiangfu Liu, uboot silent console
1/*
2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
8 */
9
10/*
11 * This file contains the configuration parameters for the NanoNote.
12 */
13#ifndef __CONFIG_NANONOTE_H
14#define __CONFIG_NANONOTE_H
15
16#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
17#define CONFIG_JzRISC 1 /* JzRISC core */
18#define CONFIG_JZSOC 1 /* Jz SoC */
19#define CONFIG_JZ4740 1 /* Jz4740 SoC */
20#define CONFIG_NAND_JZ4740
21#define CONFIG_JZ4740_MMC
22#define CONFIG_NANONOTE
23
24#define BOOT_FROM_SDCARD 1
25#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
26
27#define CONFIG_LCD 1 /* LCD support */
28#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
29#define CONFIG_SYS_WHITE_ON_BLACK
30#define CONFIG_VIDEO_GPM940B0
31
32#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
33#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
34#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
35#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
36
37#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
38#define CONFIG_BAUDRATE 57600
39#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
40
41#define CONFIG_MMC 1
42#define CONFIG_FAT 1
43#define CONFIG_DOS_PARTITION 1
44#define CONFIG_SKIP_LOWLEVEL_INIT 1
45#define CONFIG_BOARD_EARLY_INIT_F 1
46#define CONFIG_SYS_NO_FLASH 1
47#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
48#define CONFIG_ENV_OVERWRITE 1
49
50#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
51#define CONFIG_BOOTDELAY 0
52/*
53 * Command line configuration.
54 */
55#define CONFIG_CMD_BOOTD /* bootd */
56#define CONFIG_CMD_CONSOLE /* coninfo */
57#define CONFIG_CMD_ECHO /* echo arguments */
58
59#define CONFIG_CMD_LOADB /* loadb */
60#define CONFIG_CMD_LOADS /* loads */
61#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
62#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
63#define CONFIG_CMD_RUN /* run command in env variable */
64#define CONFIG_CMD_SAVEENV /* saveenv */
65#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
66#define CONFIG_CMD_SOURCE /* "source" command support */
67
68#define CONFIG_CMD_NAND
69#define CONFIG_CMD_MMC
70#define CONFIG_CMD_FAT
71#define CONFIG_CMD_EXT2
72
73/*
74 * Serial download configuration
75 */
76#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
77#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
78
79/*
80 * Miscellaneous configurable options
81 */
82#define CONFIG_SYS_LONGHELP /* undef to save memory */
83#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */
84#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
85#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
86/* Print Buffer Size */
87#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
88
89#define CONFIG_SYS_MALLOC_LEN 896 * 1024
90#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
91
92#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
93#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
94#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
95#define CONFIG_SYS_MEMTEST_START 0x80100000
96#define CONFIG_SYS_MEMTEST_END 0x80800000
97
98#define CONFIG_SILENT_CONSOLE 1 /* Enable support for silent boot */
99#define CONFIG_SYS_DEVICE_NULLDEV 1 /* Enable output sink */
100
101/*
102 * Environment
103 */
104#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
105
106/*
107 * NAND FLASH configuration
108 */
109#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
110
111/* NAND Boot config code */
112#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
113
114#define NANONOTE_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
115                   * if board nand flash is 2GB, set to 2
116                   * for change the PAGE_SIZE and BLOCK_SIZE
117                   * will delete when there is no 1GB flash
118                   */
119
120#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
121/* nand chip block size */
122#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
123/* nand bad block was marked at this page in a block, start from 0 */
124#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
125/* ECC offset position in oob area, default value is 6 if it isn't defined */
126#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
127#define CONFIG_SYS_NAND_ECCSIZE 512
128#define CONFIG_SYS_NAND_ECCBYTES 9
129
130#define CONFIG_SYS_NAND_BASE 0xB8000000
131#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
132#define NAND_MAX_CHIPS 1
133#define CONFIG_SYS_MAX_NAND_DEVICE 1
134#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
135
136/*
137 * IPL (Initial Program Loader, integrated inside CPU)
138 * Will load first 8k from NAND (SPL) into cache and execute it from there.
139 *
140 * SPL (Secondary Program Loader)
141 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
142 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
143 * controller and the NAND controller so that the special U-Boot image can be
144 * loaded from NAND to SDRAM.
145 *
146 * NUB (NAND U-Boot)
147 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
148 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
149 *
150 */
151#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
152#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
153/* Start NUB from this addr*/
154
155/*
156 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
157 */
158#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
159#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
160
161#define CONFIG_ENV_SIZE (4 << 10)
162#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
163#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
164
165/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */
166#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
167
168/*
169 * SDRAM Info.
170 */
171#define CONFIG_NR_DRAM_BANKS 1
172
173/*
174 * Cache Configuration
175 */
176#define CONFIG_SYS_DCACHE_SIZE 16384
177#define CONFIG_SYS_ICACHE_SIZE 16384
178#define CONFIG_SYS_CACHELINE_SIZE 32
179
180/*
181 * GPIO definition
182 */
183#define GPIO_LCD_CS (2 * 32 + 21)
184#define GPIO_AMP_EN (3 * 32 + 4)
185
186#define GPIO_SDPW_EN (3 * 32 + 2)
187#define GPIO_SD_DETECT (3 * 32 + 0)
188
189#define GPIO_BUZZ_PWM (3 * 32 + 27)
190#define GPIO_USB_DETECT (3 * 32 + 28)
191
192#define GPIO_AUDIO_POP (1 * 32 + 29)
193#define GPIO_COB_TEST (1 * 32 + 30)
194
195#define GPIO_KEYOUT_BASE (2 * 32 + 10)
196#define GPIO_KEYIN_BASE (3 * 32 + 18)
197#define GPIO_KEYIN_8 (3 * 32 + 26)
198
199#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
200#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
201
202#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
203#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
204#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
205#endif /* __CONFIG_NANONOTE_H */
206

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