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Source at commit b51c58b created 13 years 4 months ago. By Xiangfu Liu, this patch add uboot-xburst package uboot-xburst-avt2 uboot-xburst-n516 uboot-xburst-qi_lb60 uboot-xburst-sakc | |
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1 | /* |
2 | * Cache-handling routined for MIPS CPUs |
3 | * |
4 | * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> |
5 | * |
6 | * See file CREDITS for list of people who contributed to this |
7 | * project. |
8 | * |
9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License as |
11 | * published by the Free Software Foundation; either version 2 of |
12 | * the License, or (at your option) any later version. |
13 | * |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | * GNU General Public License for more details. |
18 | * |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
22 | * MA 02111-1307 USA |
23 | */ |
24 | |
25 | #include <config.h> |
26 | #include <version.h> |
27 | #include <asm/regdef.h> |
28 | #include <asm/mipsregs.h> |
29 | #include <asm/addrspace.h> |
30 | #include <asm/cacheops.h> |
31 | |
32 | #ifndef CONFIG_JzRISC |
33 | |
34 | /* 16KB is the maximum size of instruction and data caches on |
35 | * MIPS 4K. |
36 | */ |
37 | #define MIPS_MAX_CACHE_SIZE 0x4000 |
38 | |
39 | |
40 | /* |
41 | * cacheop macro to automate cache operations |
42 | * first some helpers... |
43 | */ |
44 | #define _mincache(size, maxsize) \ |
45 | bltu size,maxsize,9f ; \ |
46 | move size,maxsize ; \ |
47 | 9: |
48 | |
49 | #define _align(minaddr, maxaddr, linesize) \ |
50 | .set noat ; \ |
51 | subu AT,linesize,1 ; \ |
52 | not AT ; \ |
53 | and minaddr,AT ; \ |
54 | addu maxaddr,-1 ; \ |
55 | and maxaddr,AT ; \ |
56 | .set at |
57 | |
58 | /* general operations */ |
59 | #define doop1(op1) \ |
60 | cache op1,0(a0) |
61 | #define doop2(op1, op2) \ |
62 | cache op1,0(a0) ; \ |
63 | nop ; \ |
64 | cache op2,0(a0) |
65 | |
66 | /* specials for cache initialisation */ |
67 | #define doop1lw(op1) \ |
68 | lw zero,0(a0) |
69 | #define doop1lw1(op1) \ |
70 | cache op1,0(a0) ; \ |
71 | lw zero,0(a0) ; \ |
72 | cache op1,0(a0) |
73 | #define doop121(op1,op2) \ |
74 | cache op1,0(a0) ; \ |
75 | nop; \ |
76 | cache op2,0(a0) ; \ |
77 | nop; \ |
78 | cache op1,0(a0) |
79 | |
80 | #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ |
81 | .set noreorder ; \ |
82 | 10: doop##tag##ops ; \ |
83 | bne minaddr,maxaddr,10b ; \ |
84 | add minaddr,linesize ; \ |
85 | .set reorder |
86 | |
87 | /* finally the cache operation macros */ |
88 | #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ |
89 | blez n,11f ; \ |
90 | addu n,kva ; \ |
91 | _align(kva, n, cacheLineSize) ; \ |
92 | _oploopn(kva, n, cacheLineSize, tag, ops) ; \ |
93 | 11: |
94 | |
95 | #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ |
96 | _mincache(n, cacheSize); \ |
97 | blez n,11f ; \ |
98 | addu n,kva ; \ |
99 | _align(kva, n, cacheLineSize) ; \ |
100 | _oploopn(kva, n, cacheLineSize, tag, ops) ; \ |
101 | 11: |
102 | |
103 | #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ |
104 | vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) |
105 | |
106 | #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ |
107 | icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) |
108 | |
109 | /* |
110 | * mips_cache_reset - low level initialisation of the primary caches |
111 | * |
112 | * This routine initialises the primary caches to ensure that they |
113 | * have good parity. It must be called by the ROM before any cached locations |
114 | * are used to prevent the possibility of data with bad parity being written to |
115 | * memory. |
116 | * To initialise the instruction cache it is essential that a source of data |
117 | * with good parity is available. This routine |
118 | * will initialise an area of memory starting at location zero to be used as |
119 | * a source of parity. |
120 | * |
121 | * RETURNS: N/A |
122 | */ |
123 | .globl mips_cache_reset |
124 | .ent mips_cache_reset |
125 | mips_cache_reset: |
126 | |
127 | li t2, CONFIG_SYS_ICACHE_SIZE |
128 | li t3, CONFIG_SYS_DCACHE_SIZE |
129 | li t4, CONFIG_SYS_CACHELINE_SIZE |
130 | move t5, t4 |
131 | |
132 | |
133 | li v0, MIPS_MAX_CACHE_SIZE |
134 | |
135 | /* Now clear that much memory starting from zero. |
136 | */ |
137 | |
138 | li a0, KSEG1 |
139 | addu a1, a0, v0 |
140 | |
141 | 2: sw zero, 0(a0) |
142 | sw zero, 4(a0) |
143 | sw zero, 8(a0) |
144 | sw zero, 12(a0) |
145 | sw zero, 16(a0) |
146 | sw zero, 20(a0) |
147 | sw zero, 24(a0) |
148 | sw zero, 28(a0) |
149 | addu a0, 32 |
150 | bltu a0, a1, 2b |
151 | |
152 | /* Set invalid tag. |
153 | */ |
154 | |
155 | mtc0 zero, CP0_TAGLO |
156 | |
157 | /* |
158 | * The caches are probably in an indeterminate state, |
159 | * so we force good parity into them by doing an |
160 | * invalidate, load/fill, invalidate for each line. |
161 | */ |
162 | |
163 | /* Assume bottom of RAM will generate good parity for the cache. |
164 | */ |
165 | |
166 | li a0, K0BASE |
167 | move a2, t2 # icacheSize |
168 | move a3, t4 # icacheLineSize |
169 | move a1, a2 |
170 | icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) |
171 | |
172 | /* To support Orion/R4600, we initialise the data cache in 3 passes. |
173 | */ |
174 | |
175 | /* 1: initialise dcache tags. |
176 | */ |
177 | |
178 | li a0, K0BASE |
179 | move a2, t3 # dcacheSize |
180 | move a3, t5 # dcacheLineSize |
181 | move a1, a2 |
182 | icacheop(a0,a1,a2,a3,Index_Store_Tag_D) |
183 | |
184 | /* 2: fill dcache. |
185 | */ |
186 | |
187 | li a0, K0BASE |
188 | move a2, t3 # dcacheSize |
189 | move a3, t5 # dcacheLineSize |
190 | move a1, a2 |
191 | icacheopn(a0,a1,a2,a3,1lw,(dummy)) |
192 | |
193 | /* 3: clear dcache tags. |
194 | */ |
195 | |
196 | li a0, K0BASE |
197 | move a2, t3 # dcacheSize |
198 | move a3, t5 # dcacheLineSize |
199 | move a1, a2 |
200 | icacheop(a0,a1,a2,a3,Index_Store_Tag_D) |
201 | |
202 | j ra |
203 | .end mips_cache_reset |
204 | |
205 | |
206 | /* |
207 | * dcache_status - get cache status |
208 | * |
209 | * RETURNS: 0 - cache disabled; 1 - cache enabled |
210 | */ |
211 | .globl dcache_status |
212 | .ent dcache_status |
213 | dcache_status: |
214 | |
215 | mfc0 v0, CP0_CONFIG |
216 | andi v0, v0, 1 |
217 | j ra |
218 | |
219 | .end dcache_status |
220 | |
221 | /* |
222 | * dcache_disable - disable cache |
223 | * |
224 | * RETURNS: N/A |
225 | */ |
226 | .globl dcache_disable |
227 | .ent dcache_disable |
228 | dcache_disable: |
229 | |
230 | mfc0 t0, CP0_CONFIG |
231 | li t1, -8 |
232 | and t0, t0, t1 |
233 | ori t0, t0, CONF_CM_UNCACHED |
234 | mtc0 t0, CP0_CONFIG |
235 | j ra |
236 | |
237 | .end dcache_disable |
238 | |
239 | |
240 | /* |
241 | * mips_cache_lock - lock RAM area pointed to by a0 in cache. |
242 | * |
243 | * RETURNS: N/A |
244 | */ |
245 | #if defined(CONFIG_PURPLE) |
246 | # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) |
247 | #else |
248 | # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE) |
249 | #endif |
250 | .globl mips_cache_lock |
251 | .ent mips_cache_lock |
252 | mips_cache_lock: |
253 | li a1, K0BASE - CACHE_LOCK_SIZE |
254 | addu a0, a1 |
255 | li a2, CACHE_LOCK_SIZE |
256 | li a3, CONFIG_SYS_CACHELINE_SIZE |
257 | move a1, a2 |
258 | icacheop(a0,a1,a2,a3,0x1d) |
259 | |
260 | j ra |
261 | .end mips_cache_lock |
262 | |
263 | #endif /* CONFIG_JzRISC */ |
264 |