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Source at commit dc637c9 created 12 years 4 months ago. By Xiangfu Liu, xburst: ben nanonote: first add WPAN(atben,atusb) driver take from qi-kernel.git thanks to Werner | |
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1 | From 2dc84f90409839e6a85bd9e25394a387c86d12a1 Mon Sep 17 00:00:00 2001 |
2 | From: Xiangfu Liu <xiangfu@macbook.openmobilefree.net> |
3 | Date: Wed, 14 Sep 2011 14:29:58 +0800 |
4 | Subject: [PATCH 29/32] Add new jz4740_lcd.h |
5 | |
6 | --- |
7 | drivers/video/jz4740_fb.c | 78 +---------------------------------- |
8 | drivers/video/jz4740_lcd.h | 99 ++++++++++++++++++++++++++++++++++++++++++++ |
9 | 2 files changed, 100 insertions(+), 77 deletions(-) |
10 | create mode 100644 drivers/video/jz4740_lcd.h |
11 | |
12 | diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c |
13 | index de36693..6b48367 100644 |
14 | --- a/drivers/video/jz4740_fb.c |
15 | +++ b/drivers/video/jz4740_fb.c |
16 | @@ -29,83 +29,7 @@ |
17 | #include <asm/mach-jz4740/jz4740_fb.h> |
18 | #include <asm/mach-jz4740/gpio.h> |
19 | |
20 | -#define JZ_REG_LCD_CFG 0x00 |
21 | -#define JZ_REG_LCD_VSYNC 0x04 |
22 | -#define JZ_REG_LCD_HSYNC 0x08 |
23 | -#define JZ_REG_LCD_VAT 0x0C |
24 | -#define JZ_REG_LCD_DAH 0x10 |
25 | -#define JZ_REG_LCD_DAV 0x14 |
26 | -#define JZ_REG_LCD_PS 0x18 |
27 | -#define JZ_REG_LCD_CLS 0x1C |
28 | -#define JZ_REG_LCD_SPL 0x20 |
29 | -#define JZ_REG_LCD_REV 0x24 |
30 | -#define JZ_REG_LCD_CTRL 0x30 |
31 | -#define JZ_REG_LCD_STATE 0x34 |
32 | -#define JZ_REG_LCD_IID 0x38 |
33 | -#define JZ_REG_LCD_DA0 0x40 |
34 | -#define JZ_REG_LCD_SA0 0x44 |
35 | -#define JZ_REG_LCD_FID0 0x48 |
36 | -#define JZ_REG_LCD_CMD0 0x4C |
37 | -#define JZ_REG_LCD_DA1 0x50 |
38 | -#define JZ_REG_LCD_SA1 0x54 |
39 | -#define JZ_REG_LCD_FID1 0x58 |
40 | -#define JZ_REG_LCD_CMD1 0x5C |
41 | - |
42 | -#define JZ_LCD_CFG_SLCD BIT(31) |
43 | -#define JZ_LCD_CFG_PS_DISABLE BIT(23) |
44 | -#define JZ_LCD_CFG_CLS_DISABLE BIT(22) |
45 | -#define JZ_LCD_CFG_SPL_DISABLE BIT(21) |
46 | -#define JZ_LCD_CFG_REV_DISABLE BIT(20) |
47 | -#define JZ_LCD_CFG_HSYNCM BIT(19) |
48 | -#define JZ_LCD_CFG_PCLKM BIT(18) |
49 | -#define JZ_LCD_CFG_INV BIT(17) |
50 | -#define JZ_LCD_CFG_SYNC_DIR BIT(16) |
51 | -#define JZ_LCD_CFG_PS_POLARITY BIT(15) |
52 | -#define JZ_LCD_CFG_CLS_POLARITY BIT(14) |
53 | -#define JZ_LCD_CFG_SPL_POLARITY BIT(13) |
54 | -#define JZ_LCD_CFG_REV_POLARITY BIT(12) |
55 | -#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) |
56 | -#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) |
57 | -#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) |
58 | -#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) |
59 | -#define JZ_LCD_CFG_18_BIT BIT(7) |
60 | -#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) |
61 | -#define JZ_LCD_CFG_MODE_MASK 0xf |
62 | - |
63 | -#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) |
64 | -#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) |
65 | -#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) |
66 | -#define JZ_LCD_CTRL_RGB555 BIT(27) |
67 | -#define JZ_LCD_CTRL_OFUP BIT(26) |
68 | -#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) |
69 | -#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) |
70 | -#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) |
71 | -#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) |
72 | -#define JZ_LCD_CTRL_EOF_IRQ BIT(13) |
73 | -#define JZ_LCD_CTRL_SOF_IRQ BIT(12) |
74 | -#define JZ_LCD_CTRL_OFU_IRQ BIT(11) |
75 | -#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) |
76 | -#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) |
77 | -#define JZ_LCD_CTRL_DD_IRQ BIT(8) |
78 | -#define JZ_LCD_CTRL_QDD_IRQ BIT(7) |
79 | -#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) |
80 | -#define JZ_LCD_CTRL_LSB_FISRT BIT(5) |
81 | -#define JZ_LCD_CTRL_DISABLE BIT(4) |
82 | -#define JZ_LCD_CTRL_ENABLE BIT(3) |
83 | -#define JZ_LCD_CTRL_BPP_1 0x0 |
84 | -#define JZ_LCD_CTRL_BPP_2 0x1 |
85 | -#define JZ_LCD_CTRL_BPP_4 0x2 |
86 | -#define JZ_LCD_CTRL_BPP_8 0x3 |
87 | -#define JZ_LCD_CTRL_BPP_15_16 0x4 |
88 | -#define JZ_LCD_CTRL_BPP_18_24 0x5 |
89 | - |
90 | -#define JZ_LCD_CMD_SOF_IRQ BIT(15) |
91 | -#define JZ_LCD_CMD_EOF_IRQ BIT(16) |
92 | -#define JZ_LCD_CMD_ENABLE_PAL BIT(12) |
93 | - |
94 | -#define JZ_LCD_SYNC_MASK 0x3ff |
95 | - |
96 | -#define JZ_LCD_STATE_DISABLED BIT(0) |
97 | +#include "jz4740_lcd.h" |
98 | |
99 | struct jzfb_framedesc { |
100 | uint32_t next; |
101 | diff --git a/drivers/video/jz4740_lcd.h b/drivers/video/jz4740_lcd.h |
102 | new file mode 100644 |
103 | index 0000000..ac7caa5 |
104 | --- /dev/null |
105 | +++ b/drivers/video/jz4740_lcd.h |
106 | @@ -0,0 +1,99 @@ |
107 | +/* |
108 | + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de> |
109 | + * JZ4720/JZ4740 SoC LCD framebuffer driver |
110 | + * |
111 | + * This program is free software; you can redistribute it and/or modify it |
112 | + * under the terms of the GNU General Public License as published by the |
113 | + * Free Software Foundation; either version 2 of the License, or (at your |
114 | + * option) any later version. |
115 | + * |
116 | + * You should have received a copy of the GNU General Public License along |
117 | + * with this program; if not, write to the Free Software Foundation, Inc., |
118 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
119 | + * |
120 | + */ |
121 | + |
122 | +#ifndef __JZ4740_LCD_H__ |
123 | +#define __JZ4740_LCD_H__ |
124 | + |
125 | +#include <linux/bitops.h> |
126 | + |
127 | +#define JZ_REG_LCD_CFG 0x00 |
128 | +#define JZ_REG_LCD_VSYNC 0x04 |
129 | +#define JZ_REG_LCD_HSYNC 0x08 |
130 | +#define JZ_REG_LCD_VAT 0x0C |
131 | +#define JZ_REG_LCD_DAH 0x10 |
132 | +#define JZ_REG_LCD_DAV 0x14 |
133 | +#define JZ_REG_LCD_PS 0x18 |
134 | +#define JZ_REG_LCD_CLS 0x1C |
135 | +#define JZ_REG_LCD_SPL 0x20 |
136 | +#define JZ_REG_LCD_REV 0x24 |
137 | +#define JZ_REG_LCD_CTRL 0x30 |
138 | +#define JZ_REG_LCD_STATE 0x34 |
139 | +#define JZ_REG_LCD_IID 0x38 |
140 | +#define JZ_REG_LCD_DA0 0x40 |
141 | +#define JZ_REG_LCD_SA0 0x44 |
142 | +#define JZ_REG_LCD_FID0 0x48 |
143 | +#define JZ_REG_LCD_CMD0 0x4C |
144 | +#define JZ_REG_LCD_DA1 0x50 |
145 | +#define JZ_REG_LCD_SA1 0x54 |
146 | +#define JZ_REG_LCD_FID1 0x58 |
147 | +#define JZ_REG_LCD_CMD1 0x5C |
148 | + |
149 | +#define JZ_LCD_CFG_SLCD BIT(31) |
150 | +#define JZ_LCD_CFG_PS_DISABLE BIT(23) |
151 | +#define JZ_LCD_CFG_CLS_DISABLE BIT(22) |
152 | +#define JZ_LCD_CFG_SPL_DISABLE BIT(21) |
153 | +#define JZ_LCD_CFG_REV_DISABLE BIT(20) |
154 | +#define JZ_LCD_CFG_HSYNCM BIT(19) |
155 | +#define JZ_LCD_CFG_PCLKM BIT(18) |
156 | +#define JZ_LCD_CFG_INV BIT(17) |
157 | +#define JZ_LCD_CFG_SYNC_DIR BIT(16) |
158 | +#define JZ_LCD_CFG_PS_POLARITY BIT(15) |
159 | +#define JZ_LCD_CFG_CLS_POLARITY BIT(14) |
160 | +#define JZ_LCD_CFG_SPL_POLARITY BIT(13) |
161 | +#define JZ_LCD_CFG_REV_POLARITY BIT(12) |
162 | +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) |
163 | +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) |
164 | +#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) |
165 | +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) |
166 | +#define JZ_LCD_CFG_18_BIT BIT(7) |
167 | +#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) |
168 | +#define JZ_LCD_CFG_MODE_MASK 0xf |
169 | + |
170 | +#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) |
171 | +#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) |
172 | +#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) |
173 | +#define JZ_LCD_CTRL_RGB555 BIT(27) |
174 | +#define JZ_LCD_CTRL_OFUP BIT(26) |
175 | +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) |
176 | +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) |
177 | +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) |
178 | +#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) |
179 | +#define JZ_LCD_CTRL_EOF_IRQ BIT(13) |
180 | +#define JZ_LCD_CTRL_SOF_IRQ BIT(12) |
181 | +#define JZ_LCD_CTRL_OFU_IRQ BIT(11) |
182 | +#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) |
183 | +#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) |
184 | +#define JZ_LCD_CTRL_DD_IRQ BIT(8) |
185 | +#define JZ_LCD_CTRL_QDD_IRQ BIT(7) |
186 | +#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) |
187 | +#define JZ_LCD_CTRL_LSB_FISRT BIT(5) |
188 | +#define JZ_LCD_CTRL_DISABLE BIT(4) |
189 | +#define JZ_LCD_CTRL_ENABLE BIT(3) |
190 | +#define JZ_LCD_CTRL_BPP_1 0x0 |
191 | +#define JZ_LCD_CTRL_BPP_2 0x1 |
192 | +#define JZ_LCD_CTRL_BPP_4 0x2 |
193 | +#define JZ_LCD_CTRL_BPP_8 0x3 |
194 | +#define JZ_LCD_CTRL_BPP_15_16 0x4 |
195 | +#define JZ_LCD_CTRL_BPP_18_24 0x5 |
196 | + |
197 | +#define JZ_LCD_CMD_SOF_IRQ BIT(15) |
198 | +#define JZ_LCD_CMD_EOF_IRQ BIT(16) |
199 | +#define JZ_LCD_CMD_ENABLE_PAL BIT(12) |
200 | + |
201 | +#define JZ_LCD_SYNC_MASK 0x3ff |
202 | + |
203 | +#define JZ_LCD_STATE_DISABLED BIT(0) |
204 | + |
205 | +#endif /*__JZ4740_LCD_H__*/ |
206 | -- |
207 | 1.7.4.1 |
208 | |
209 |