Root/package/uboot-ifxmips/files/drivers/ifx_sw.c

1/*
2 * DANUBE internal switch ethernet driver.
3 *
4 * (C) Copyright 2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27#include <common.h>
28
29#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30    && defined(CONFIG_DANUBE_SWITCH)
31
32#include <malloc.h>
33#include <net.h>
34#include <asm/danube.h>
35#include <asm/addrspace.h>
36#include <asm/pinstrap.h>
37
38#define MII_MODE 1
39#define REV_MII_MODE 2
40
41#define TX_CHAN_NO 7
42#define RX_CHAN_NO 6
43
44#define NUM_RX_DESC PKTBUFSRX
45#define NUM_TX_DESC 8
46#define MAX_PACKET_SIZE 1536
47#define TOUT_LOOP 100
48#define PHY0_ADDR 1 /*fixme: set the correct value here*/
49
50#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value
51#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
52
53#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value
54#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
55
56#define TANTOS_CHIP_ID 0x2599
57
58typedef struct
59{
60    union
61    {
62        struct
63        {
64            volatile u32 OWN :1;
65            volatile u32 C :1;
66            volatile u32 Sop :1;
67            volatile u32 Eop :1;
68            volatile u32 reserved :3;
69            volatile u32 Byteoffset :2;
70            volatile u32 reserve :7;
71            volatile u32 DataLen :16;
72        }field;
73
74        volatile u32 word;
75    }status;
76
77    volatile u32 DataPtr;
78} danube_rx_descriptor_t;
79
80typedef struct
81{
82    union
83    {
84        struct
85        {
86            volatile u32 OWN :1;
87            volatile u32 C :1;
88            volatile u32 Sop :1;
89            volatile u32 Eop :1;
90            volatile u32 Byteoffset :5;
91            volatile u32 reserved :7;
92            volatile u32 DataLen :16;
93        }field;
94
95        volatile u32 word;
96    }status;
97
98    volatile u32 DataPtr;
99} danube_tx_descriptor_t;
100
101
102
103
104static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
105static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
106static int tx_num, rx_num;
107
108int danube_switch_init(struct eth_device *dev, bd_t * bis);
109int danube_switch_send(struct eth_device *dev, volatile void *packet,int length);
110int danube_switch_recv(struct eth_device *dev);
111void danube_switch_halt(struct eth_device *dev);
112static void danube_init_switch_chip(int mode);
113static void danube_dma_init(void);
114
115
116
117int danube_switch_initialize(bd_t * bis)
118{
119    struct eth_device *dev;
120    unsigned short chipid;
121
122#if 0
123    printf("Entered danube_switch_initialize()\n");
124#endif
125
126    if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
127    {
128        printf("Failed to allocate memory\n");
129        return 0;
130    }
131    memset(dev, 0, sizeof(*dev));
132
133    danube_dma_init();
134    danube_init_switch_chip(REV_MII_MODE);
135
136#ifdef CLK_OUT2_25MHZ
137    *DANUBE_GPIO_P0_DIR=0x0000ae78;
138    *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
139    //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
140    *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
141    *DANUBE_CGU_IFCCR=0x00400010;
142    *DANUBE_GPIO_P0_OD=0x0000ae78;
143#endif
144
145    /*patch for 6996*/
146
147    *DANUBE_RCU_RST_REQ |=1;
148    mdelay(200);
149    *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
150    mdelay(1);
151    /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
152    *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
153    */
154    /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
155    *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
156    */
157    /***************/
158    sprintf(dev->name, "danube Switch");
159    dev->init = danube_switch_init;
160    dev->halt = danube_switch_halt;
161    dev->send = danube_switch_send;
162    dev->recv = danube_switch_recv;
163
164    eth_register(dev);
165
166    while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
167    *DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000;
168    while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
169    chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff);
170
171    if (chipid != TANTOS_CHIP_ID) // not tantos switch.
172    {
173        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
174        *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
175        while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000);
176        *DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F;
177        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
178        *DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F;
179        //while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
180        //*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F;
181        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
182        *DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F;
183        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
184        *DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F;
185        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
186        *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
187        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
188        *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
189#ifdef CLK_OUT2_25MHZ
190        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
191        *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000;
192#endif
193    }
194    else // Tantos switch chip
195    {
196        //printf("Tantos Switch detected!!\n\r");
197
198        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
199        *DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004;
200
201        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
202        *DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004;
203
204        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
205        *DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773;
206
207        /* Software workaround. */
208        /* PHY reset from P0 to P4. */
209        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
210
211        mdelay(1);
212        *DANUBE_PPE_ETOP_MDIO_ACC =0x81218000;
213        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
214        mdelay(1);
215        /* P0 */
216        *DANUBE_PPE_ETOP_MDIO_ACC =0x81200400;
217        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
218        mdelay(1);
219        /* P1 */
220        *DANUBE_PPE_ETOP_MDIO_ACC =0x81200420;
221        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
222        mdelay(1);
223        /* P2 */
224        *DANUBE_PPE_ETOP_MDIO_ACC =0x81200440;
225        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
226        mdelay(1);
227        /* P3 */
228        *DANUBE_PPE_ETOP_MDIO_ACC =0x81200460;
229        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
230        mdelay(1);
231        /* p4 */
232        *DANUBE_PPE_ETOP_MDIO_ACC =0x81200480;
233        while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
234        mdelay(1);
235    }
236
237    return 1;
238}
239
240int danube_switch_init(struct eth_device *dev, bd_t * bis)
241{
242    int i;
243
244    tx_num=0;
245    rx_num=0;
246
247    /* Reset DMA */
248// serial_puts("i \n\0");
249
250    *DANUBE_DMA_CS=RX_CHAN_NO;
251    *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
252    *DANUBE_DMA_CPOLL= 0x80000040;
253    /*set descriptor base*/
254    *DANUBE_DMA_CDBA=(u32)rx_des_ring;
255    *DANUBE_DMA_CDLEN=NUM_RX_DESC;
256    *DANUBE_DMA_CIE = 0;
257    *DANUBE_DMA_CCTRL=0x30000;
258
259    *DANUBE_DMA_CS=TX_CHAN_NO;
260    *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
261    *DANUBE_DMA_CPOLL= 0x80000040;
262    *DANUBE_DMA_CDBA=(u32)tx_des_ring;
263    *DANUBE_DMA_CDLEN=NUM_TX_DESC;
264    *DANUBE_DMA_CIE = 0;
265    *DANUBE_DMA_CCTRL=0x30100;
266
267    for(i=0;i < NUM_RX_DESC; i++)
268    {
269        danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]);
270        rx_desc->status.word=0;
271        rx_desc->status.field.OWN=1;
272        rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
273        rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]);
274    }
275
276    for(i=0;i < NUM_TX_DESC; i++)
277    {
278        danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]);
279        memset(tx_desc, 0, sizeof(tx_des_ring[0]));
280    }
281        /* turn on DMA rx & tx channel
282        */
283    *DANUBE_DMA_CS=RX_CHAN_NO;
284    *DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/
285
286    return 0;
287}
288
289void danube_switch_halt(struct eth_device *dev)
290{
291    int i;
292    for(i=0;i<8;i++)
293    {
294        *DANUBE_DMA_CS=i;
295        *DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/
296    }
297// udelay(1000000);
298}
299
300int danube_switch_send(struct eth_device *dev, volatile void *packet,int length)
301{
302
303    int i;
304    int res = -1;
305
306    danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]);
307
308    if (length <= 0)
309    {
310        printf ("%s: bad packet size: %d\n", dev->name, length);
311        goto Done;
312    }
313
314    for(i=0; tx_desc->status.field.OWN==1; i++)
315    {
316        if(i>=TOUT_LOOP)
317        {
318            printf("NO Tx Descriptor...");
319            goto Done;
320        }
321    }
322
323    //serial_putc('s');
324
325    tx_desc->status.field.Sop=1;
326    tx_desc->status.field.Eop=1;
327    tx_desc->status.field.C=0;
328    tx_desc->DataPtr = (u32)KSEG1ADDR(packet);
329    if(length<60)
330        tx_desc->status.field.DataLen = 60;
331    else
332        tx_desc->status.field.DataLen = (u32)length;
333
334    asm("SYNC");
335    tx_desc->status.field.OWN=1;
336
337    res=length;
338    tx_num++;
339    if(tx_num==NUM_TX_DESC) tx_num=0;
340    *DANUBE_DMA_CS=TX_CHAN_NO;
341
342    if(!(*DANUBE_DMA_CCTRL & 1))
343        *DANUBE_DMA_CCTRL|=1;
344
345Done:
346    return res;
347}
348
349int danube_switch_recv(struct eth_device *dev)
350{
351    int length = 0;
352    danube_rx_descriptor_t * rx_desc;
353
354    for (;;)
355    {
356        rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
357
358        if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1))
359        {
360            break;
361        }
362
363        length = rx_desc->status.field.DataLen;
364        if (length)
365        {
366            NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4);
367        // serial_putc('*');
368        }
369        else
370        {
371            printf("Zero length!!!\n");
372        }
373
374        rx_desc->status.field.Sop=0;
375        rx_desc->status.field.Eop=0;
376        rx_desc->status.field.C=0;
377        rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
378        rx_desc->status.field.OWN=1;
379        rx_num++;
380        if(rx_num==NUM_RX_DESC) rx_num=0;
381
382    }
383
384    return length;
385}
386
387
388static void danube_init_switch_chip(int mode)
389{
390    /*get and set mac address for MAC*/
391    char *tmp;
392    tmp = getenv ("ethaddr");
393    if (NULL == tmp) {
394        printf("Can't get environment ethaddr!!!\n");
395    // return NULL;
396    } else {
397        printf("ethaddr=%s\n", tmp);
398    }
399    *DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF;
400    *DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6;
401    *DANUBE_PPE32_ENET_MAC_CFG = 0x187;
402
403    // turn on port0, set to rmii and turn off port1.
404    if (mode==REV_MII_MODE)
405    {
406        *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a;
407    }
408    else if (mode == MII_MODE)
409    {
410        *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008;
411    }
412
413    *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen.
414    *ENET_MAC_CFG |= 1<<11; /*enable the crc*/
415    return;
416}
417
418
419static void danube_dma_init(void)
420{
421// serial_puts("d \n\0");
422
423    *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
424    /* Reset DMA */
425    *DANUBE_DMA_CTRL|=1;
426    *DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/
427
428    /* Clear Interrupt Status Register */
429    *DANUBE_DMA_IRNCR=0xfffff;
430    /*disable all the dma interrupts*/
431    *DANUBE_DMA_IRNEN=0;
432    /*disable channel 0 and channel 1 interrupts*/
433
434    *DANUBE_DMA_CS=RX_CHAN_NO;
435    *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
436    *DANUBE_DMA_CPOLL= 0x80000040;
437    /*set descriptor base*/
438    *DANUBE_DMA_CDBA=(u32)rx_des_ring;
439    *DANUBE_DMA_CDLEN=NUM_RX_DESC;
440    *DANUBE_DMA_CIE = 0;
441    *DANUBE_DMA_CCTRL=0x30000;
442
443    *DANUBE_DMA_CS=TX_CHAN_NO;
444    *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
445    *DANUBE_DMA_CPOLL= 0x80000040;
446    *DANUBE_DMA_CDBA=(u32)tx_des_ring;
447    *DANUBE_DMA_CDLEN=NUM_TX_DESC;
448    *DANUBE_DMA_CIE = 0;
449    *DANUBE_DMA_CCTRL=0x30100;
450    /*enable the poll function and set the poll counter*/
451    //*DANUBE_DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
452    /*set port properties, enable endian conversion for switch*/
453    *DANUBE_DMA_PS=0;
454    *DANUBE_DMA_PCTRL|=0xf<<8;/*enable 32 bit endian conversion*/
455
456    return;
457}
458
459#endif
460

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