| 1 | --- a/arch/mips/kernel/traps.c |
| 2 | +++ b/arch/mips/kernel/traps.c |
| 3 | @@ -1255,9 +1255,22 @@ void *set_except_vector(int n, void *add |
| 4 | |
| 5 | exception_handlers[n] = handler; |
| 6 | if (n == 0 && cpu_has_divec) { |
| 7 | - *(u32 *)(ebase + 0x200) = 0x08000000 | |
| 8 | - (0x03ffffff & (handler >> 2)); |
| 9 | - local_flush_icache_range(ebase + 0x200, ebase + 0x204); |
| 10 | + if ((handler ^ (ebase + 4)) & 0xfc000000) { |
| 11 | + /* lui k0, 0x0000 */ |
| 12 | + *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16); |
| 13 | + /* ori k0, 0x0000 */ |
| 14 | + *(u32 *)(ebase + 0x204) = |
| 15 | + 0x375a0000 | (handler & 0xffff); |
| 16 | + /* jr k0 */ |
| 17 | + *(u32 *)(ebase + 0x208) = 0x03400008; |
| 18 | + /* nop */ |
| 19 | + *(u32 *)(ebase + 0x20C) = 0x00000000; |
| 20 | + flush_icache_range(ebase + 0x200, ebase + 0x210); |
| 21 | + } else { |
| 22 | + *(u32 *)(ebase + 0x200) = |
| 23 | + 0x08000000 | (0x03ffffff & (handler >> 2)); |
| 24 | + flush_icache_range(ebase + 0x200, ebase + 0x204); |
| 25 | + } |
| 26 | } |
| 27 | return (void *)old_handler; |
| 28 | } |
| 29 | --- a/arch/mips/include/asm/page.h |
| 30 | +++ b/arch/mips/include/asm/page.h |
| 31 | @@ -200,8 +200,10 @@ typedef struct { unsigned long pgprot; } |
| 32 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ |
| 33 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) |
| 34 | |
| 35 | -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) |
| 36 | -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) |
| 37 | +#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ |
| 38 | + PHYS_OFFSET) |
| 39 | +#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \ |
| 40 | + PHYS_OFFSET) |
| 41 | |
| 42 | #include <asm-generic/memory_model.h> |
| 43 | #include <asm-generic/getorder.h> |
| 44 | |
