| 1 | /* |
| 2 | * Atheros AR71xx SoC specific platform data definitions |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published |
| 9 | * by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __ASM_MACH_AR71XX_PLATFORM_H |
| 13 | #define __ASM_MACH_AR71XX_PLATFORM_H |
| 14 | |
| 15 | #include <linux/if_ether.h> |
| 16 | #include <linux/skbuff.h> |
| 17 | #include <linux/phy.h> |
| 18 | #include <linux/spi/spi.h> |
| 19 | |
| 20 | struct ag71xx_platform_data { |
| 21 | phy_interface_t phy_if_mode; |
| 22 | u32 phy_mask; |
| 23 | int speed; |
| 24 | int duplex; |
| 25 | u32 reset_bit; |
| 26 | u32 mii_if; |
| 27 | u8 mac_addr[ETH_ALEN]; |
| 28 | struct device *mii_bus_dev; |
| 29 | |
| 30 | u8 has_gbit:1; |
| 31 | u8 is_ar91xx:1; |
| 32 | u8 is_ar724x:1; |
| 33 | u8 has_ar8216:1; |
| 34 | |
| 35 | void (* ddr_flush)(void); |
| 36 | void (* set_pll)(int speed); |
| 37 | |
| 38 | u32 fifo_cfg1; |
| 39 | u32 fifo_cfg2; |
| 40 | u32 fifo_cfg3; |
| 41 | }; |
| 42 | |
| 43 | struct ag71xx_mdio_platform_data { |
| 44 | u32 phy_mask; |
| 45 | int is_ar7240; |
| 46 | }; |
| 47 | |
| 48 | struct ar71xx_ehci_platform_data { |
| 49 | u8 is_ar91xx; |
| 50 | }; |
| 51 | |
| 52 | struct ar71xx_spi_platform_data { |
| 53 | unsigned bus_num; |
| 54 | unsigned num_chipselect; |
| 55 | u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); |
| 56 | }; |
| 57 | |
| 58 | #define AR71XX_SPI_CS_INACTIVE 0 |
| 59 | #define AR71XX_SPI_CS_ACTIVE 1 |
| 60 | |
| 61 | #endif /* __ASM_MACH_AR71XX_PLATFORM_H */ |
| 62 | |
