Root/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c

1/*
2 * Atheros AR71xx PCI host controller driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/resource.h>
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/pci.h>
19#include <linux/pci_regs.h>
20#include <linux/interrupt.h>
21
22#include <asm/mach-ar71xx/ar71xx.h>
23#include <asm/mach-ar71xx/pci.h>
24
25#undef DEBUG
26#ifdef DEBUG
27#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
28#else
29#define DBG(fmt, args...)
30#endif
31
32#define AR71XX_PCI_DELAY 100 /* msecs */
33
34#if 0
35#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
36#else
37#define PCI_IDSEL_BASE 0
38#endif
39
40static void __iomem *ar71xx_pcicfg_base;
41static DEFINE_SPINLOCK(ar71xx_pci_lock);
42static int ar71xx_pci_fixup_enable;
43
44static inline void ar71xx_pci_delay(void)
45{
46    mdelay(AR71XX_PCI_DELAY);
47}
48
49/* Byte lane enable bits */
50static u8 ble_table[4][4] = {
51    {0x0, 0xf, 0xf, 0xf},
52    {0xe, 0xd, 0xb, 0x7},
53    {0xc, 0xf, 0x3, 0xf},
54    {0xf, 0xf, 0xf, 0xf},
55};
56
57static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
58{
59    u32 t;
60
61    t = ble_table[size & 3][where & 3];
62    BUG_ON(t == 0xf);
63    t <<= (local) ? 20 : 4;
64    return t;
65}
66
67static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
68                    int where)
69{
70    u32 ret;
71
72    if (!bus->number) {
73        /* type 0 */
74        ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
75            | (PCI_FUNC(devfn) << 8) | (where & ~3);
76    } else {
77        /* type 1 */
78        ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
79            | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
80    }
81
82    return ret;
83}
84
85int ar71xx_pci_be_handler(int is_fixup)
86{
87    void __iomem *base = ar71xx_pcicfg_base;
88    u32 pci_err;
89    u32 ahb_err;
90
91    pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;
92    if (pci_err) {
93        if (!is_fixup)
94            printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
95                pci_err,
96                __raw_readl(base + PCI_REG_PCI_ERR_ADDR));
97
98        __raw_writel(pci_err, base + PCI_REG_PCI_ERR);
99    }
100
101    ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;
102    if (ahb_err) {
103        if (!is_fixup)
104            printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
105                __raw_readl(base + PCI_REG_AHB_ERR_ADDR));
106
107        __raw_writel(ahb_err, base + PCI_REG_AHB_ERR);
108    }
109
110    return ((ahb_err | pci_err) ? 1 : 0);
111}
112
113static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
114            unsigned int devfn, int where, int size, u32 cmd)
115{
116    void __iomem *base = ar71xx_pcicfg_base;
117    u32 addr;
118
119    addr = ar71xx_pci_bus_addr(bus, devfn, where);
120
121    DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
122        bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
123        where, size, addr);
124
125    __raw_writel(addr, base + PCI_REG_CFG_AD);
126    __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
127             base + PCI_REG_CFG_CBE);
128
129    return ar71xx_pci_be_handler(1);
130}
131
132static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
133                  int where, int size, u32 *value)
134{
135    void __iomem *base = ar71xx_pcicfg_base;
136    static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
137    unsigned long flags;
138    u32 data;
139    int ret;
140
141    ret = PCIBIOS_SUCCESSFUL;
142
143    DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
144            PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
145
146    spin_lock_irqsave(&ar71xx_pci_lock, flags);
147
148    if (bus->number == 0 && devfn == 0) {
149        u32 t;
150
151        t = PCI_CRP_CMD_READ | (where & ~3);
152
153        __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
154        data = __raw_readl(base + PCI_REG_CRP_RDDATA);
155
156        DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
157
158    } else {
159        int err;
160
161        err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
162                        PCI_CFG_CMD_READ);
163
164        if (err == 0) {
165            data = __raw_readl(base + PCI_REG_CFG_RDDATA);
166        } else {
167            ret = PCIBIOS_DEVICE_NOT_FOUND;
168            data = ~0;
169        }
170    }
171
172    spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
173
174    DBG("PCI: read config: data=%08x raw=%08x\n",
175        (data >> (8 * (where & 3))) & mask[size & 7], data);
176
177    *value = (data >> (8 * (where & 3))) & mask[size & 7];
178
179    return ret;
180}
181
182static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
183                   int where, int size, u32 value)
184{
185    void __iomem *base = ar71xx_pcicfg_base;
186    unsigned long flags;
187    int ret;
188
189    DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
190        bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
191        where, size, value);
192
193    value = value << (8 * (where & 3));
194    ret = PCIBIOS_SUCCESSFUL;
195
196    spin_lock_irqsave(&ar71xx_pci_lock, flags);
197    if (bus->number == 0 && devfn == 0) {
198        u32 t;
199
200        t = PCI_CRP_CMD_WRITE | (where & ~3);
201        t |= ar71xx_pci_get_ble(where, size, 1);
202
203        DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
204
205        __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
206        __raw_writel(value, base + PCI_REG_CRP_WRDATA);
207    } else {
208        int err;
209
210        err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
211                        PCI_CFG_CMD_WRITE);
212
213        if (err == 0)
214            __raw_writel(value, base + PCI_REG_CFG_WRDATA);
215        else
216            ret = PCIBIOS_DEVICE_NOT_FOUND;
217    }
218    spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
219
220    return ret;
221}
222
223static void ar71xx_pci_fixup(struct pci_dev *dev)
224{
225    u32 t;
226
227    if (!ar71xx_pci_fixup_enable)
228        return;
229
230    if (dev->bus->number != 0 || dev->devfn != 0)
231        return;
232
233    DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
234        dev->vendor, dev->device);
235
236    /* setup COMMAND register */
237    t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
238      | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
239
240    pci_write_config_word(dev, PCI_COMMAND, t);
241}
242DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
243
244int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
245                  uint8_t pin)
246{
247    int irq = -1;
248    int i;
249
250    slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
251
252    for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
253        struct ar71xx_pci_irq *entry;
254
255        entry = &ar71xx_pci_irq_map[i];
256        if (entry->slot == slot && entry->pin == pin) {
257            irq = entry->irq;
258            break;
259        }
260    }
261
262    if (irq < 0) {
263        printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
264                pin, pci_name((struct pci_dev *)dev));
265    } else {
266        printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
267                irq, pin, pci_name((struct pci_dev *)dev));
268    }
269
270    return irq;
271}
272
273static struct pci_ops ar71xx_pci_ops = {
274    .read = ar71xx_pci_read_config,
275    .write = ar71xx_pci_write_config,
276};
277
278static struct resource ar71xx_pci_io_resource = {
279    .name = "PCI IO space",
280    .start = 0,
281    .end = 0,
282    .flags = IORESOURCE_IO,
283};
284
285static struct resource ar71xx_pci_mem_resource = {
286    .name = "PCI memory space",
287    .start = AR71XX_PCI_MEM_BASE,
288    .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
289    .flags = IORESOURCE_MEM
290};
291
292static struct pci_controller ar71xx_pci_controller = {
293    .pci_ops = &ar71xx_pci_ops,
294    .mem_resource = &ar71xx_pci_mem_resource,
295    .io_resource = &ar71xx_pci_io_resource,
296};
297
298static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
299{
300    void __iomem *base = ar71xx_reset_base;
301    u32 pending;
302
303    pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
304          __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
305
306    if (pending & PCI_INT_DEV0)
307        generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
308
309    else if (pending & PCI_INT_DEV1)
310        generic_handle_irq(AR71XX_PCI_IRQ_DEV1);
311
312    else if (pending & PCI_INT_DEV2)
313        generic_handle_irq(AR71XX_PCI_IRQ_DEV2);
314
315    else if (pending & PCI_INT_CORE)
316        generic_handle_irq(AR71XX_PCI_IRQ_CORE);
317
318    else
319        spurious_interrupt();
320}
321
322static void ar71xx_pci_irq_unmask(unsigned int irq)
323{
324    void __iomem *base = ar71xx_reset_base;
325    u32 t;
326
327    irq -= AR71XX_PCI_IRQ_BASE;
328
329    t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
330    __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
331
332    /* flush write */
333    (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
334}
335
336static void ar71xx_pci_irq_mask(unsigned int irq)
337{
338    void __iomem *base = ar71xx_reset_base;
339    u32 t;
340
341    irq -= AR71XX_PCI_IRQ_BASE;
342
343    t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
344    __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
345
346    /* flush write */
347    (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
348}
349
350static struct irq_chip ar71xx_pci_irq_chip = {
351    .name = "AR71XX PCI ",
352    .mask = ar71xx_pci_irq_mask,
353    .unmask = ar71xx_pci_irq_unmask,
354    .mask_ack = ar71xx_pci_irq_mask,
355};
356
357static void __init ar71xx_pci_irq_init(void)
358{
359    void __iomem *base = ar71xx_reset_base;
360    int i;
361
362    __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
363    __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
364
365    for (i = AR71XX_PCI_IRQ_BASE;
366         i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
367        irq_desc[i].status = IRQ_DISABLED;
368        set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
369                     handle_level_irq);
370    }
371
372    set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
373}
374
375int __init ar71xx_pcibios_init(void)
376{
377    void __iomem *ddr_base = ar71xx_ddr_base;
378
379    ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
380    ar71xx_pci_delay();
381
382    ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
383    ar71xx_pci_delay();
384
385    ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
386                        AR71XX_PCI_CFG_SIZE);
387    if (ar71xx_pcicfg_base == NULL)
388        return -ENOMEM;
389
390    __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
391    __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
392    __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
393    __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
394    __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
395    __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
396    __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
397    __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
398
399    ar71xx_pci_delay();
400
401    /* clear bus errors */
402    (void)ar71xx_pci_be_handler(1);
403
404    ar71xx_pci_fixup_enable = 1;
405    ar71xx_pci_irq_init();
406    register_pci_controller(&ar71xx_pci_controller);
407
408    return 0;
409}
410

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