Root/target/linux/atheros/patches-2.6.30/100-board.patch

1--- a/arch/mips/Kconfig
2+++ b/arch/mips/Kconfig
3@@ -60,6 +60,19 @@ config BCM47XX
4     help
5      Support for BCM47XX based boards
6 
7+config ATHEROS_AR231X
8+ bool "Atheros 231x/531x SoC support"
9+ select CEVT_R4K
10+ select CSRC_R4K
11+ select DMA_NONCOHERENT
12+ select IRQ_CPU
13+ select SYS_HAS_CPU_MIPS32_R1
14+ select SYS_SUPPORTS_BIG_ENDIAN
15+ select SYS_SUPPORTS_32BIT_KERNEL
16+ select GENERIC_GPIO
17+ help
18+ Support for AR231x and AR531x based boards
19+
20 config MIPS_COBALT
21     bool "Cobalt Server"
22     select CEVT_R4K
23@@ -633,6 +646,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
24 
25 endchoice
26 
27+source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/basler/excite/Kconfig"
30 source "arch/mips/jazz/Kconfig"
31--- a/arch/mips/Makefile
32+++ b/arch/mips/Makefile
33@@ -283,6 +283,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips
34 load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
35 
36 #
37+# Atheros AR5312/AR2312 WiSoC
38+#
39+core-$(CONFIG_ATHEROS_AR231X) += arch/mips/ar231x/
40+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
41+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
42+
43+#
44 # Cobalt Server
45 #
46 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
47--- /dev/null
48+++ b/arch/mips/ar231x/Kconfig
49@@ -0,0 +1,17 @@
50+config ATHEROS_AR5312
51+ bool "Atheros 5312/2312+ support"
52+ depends on ATHEROS_AR231X
53+ default y
54+
55+config ATHEROS_AR2315
56+ bool "Atheros 2315+ support"
57+ depends on ATHEROS_AR231X
58+ select DMA_NONCOHERENT
59+ select CEVT_R4K
60+ select CSRC_R4K
61+ select IRQ_CPU
62+ select SYS_HAS_CPU_MIPS32_R1
63+ select SYS_SUPPORTS_32BIT_KERNEL
64+ select SYS_SUPPORTS_BIG_ENDIAN
65+ select GENERIC_GPIO
66+ default y
67--- /dev/null
68+++ b/arch/mips/ar231x/Makefile
69@@ -0,0 +1,13 @@
70+#
71+# This file is subject to the terms and conditions of the GNU General Public
72+# License. See the file "COPYING" in the main directory of this archive
73+# for more details.
74+#
75+# Copyright (C) 2006 FON Technology, SL.
76+# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
77+# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
78+#
79+
80+obj-y += board.o prom.o devices.o
81+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
82+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
83--- /dev/null
84+++ b/arch/mips/ar231x/board.c
85@@ -0,0 +1,251 @@
86+/*
87+ * This file is subject to the terms and conditions of the GNU General Public
88+ * License. See the file "COPYING" in the main directory of this archive
89+ * for more details.
90+ *
91+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
92+ * Copyright (C) 2006 FON Technology, SL.
93+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
94+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
95+ */
96+
97+#include <linux/autoconf.h>
98+#include <linux/init.h>
99+#include <linux/module.h>
100+#include <linux/types.h>
101+#include <linux/string.h>
102+#include <linux/platform_device.h>
103+#include <linux/kernel.h>
104+#include <linux/random.h>
105+#include <linux/etherdevice.h>
106+#include <asm/irq_cpu.h>
107+#include <asm/reboot.h>
108+#include <asm/io.h>
109+
110+#include <ar231x_platform.h>
111+#include "devices.h"
112+#include "ar5312.h"
113+#include "ar2315.h"
114+
115+void (*ar231x_irq_dispatch)(void);
116+
117+static inline bool
118+check_radio_magic(u8 *addr)
119+{
120+ addr += 0x7a; /* offset for flash magic */
121+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
122+ return 1;
123+ }
124+ return 0;
125+}
126+
127+static inline bool
128+check_board_data(u8 *flash_limit, u8 *addr, bool broken)
129+{
130+ /* config magic found */
131+ if (*((u32 *)addr) == AR531X_BD_MAGIC)
132+ return 1;
133+
134+ if (!broken)
135+ return 0;
136+
137+ if (check_radio_magic(addr + 0xf8))
138+ ar231x_board.radio = addr + 0xf8;
139+ if ((addr < flash_limit + 0x10000) &&
140+ check_radio_magic(addr + 0x10000))
141+ ar231x_board.radio = addr + 0x10000;
142+
143+ if (ar231x_board.radio) {
144+ /* broken board data detected, use radio data to find the offset,
145+ * user will fix this */
146+ return 1;
147+ }
148+ return 0;
149+}
150+
151+static u8 *
152+find_board_config(u8 *flash_limit, bool broken)
153+{
154+ u8 *addr;
155+ int found = 0;
156+
157+ for (addr = flash_limit - 0x1000;
158+ addr >= flash_limit - 0x30000;
159+ addr -= 0x1000) {
160+
161+ if (check_board_data(flash_limit, addr, broken)) {
162+ found = 1;
163+ break;
164+ }
165+ }
166+
167+ if (!found)
168+ addr = NULL;
169+
170+ return addr;
171+}
172+
173+static u8 *
174+find_radio_config(u8 *flash_limit, u8 *board_config)
175+{
176+ int found;
177+ u8 *radio_config;
178+
179+ /*
180+ * Now find the start of Radio Configuration data, using heuristics:
181+ * Search forward from Board Configuration data by 0x1000 bytes
182+ * at a time until we find non-0xffffffff.
183+ */
184+ found = 0;
185+ for (radio_config = board_config + 0x1000;
186+ (radio_config < flash_limit);
187+ radio_config += 0x1000) {
188+ if ((*(u32 *)radio_config != 0xffffffff) &&
189+ check_radio_magic(radio_config)) {
190+ found = 1;
191+ break;
192+ }
193+ }
194+
195+ /* AR2316 relocates radio config to new location */
196+ if (!found) {
197+ for (radio_config = board_config + 0xf8;
198+ (radio_config < flash_limit - 0x1000 + 0xf8);
199+ radio_config += 0x1000) {
200+ if ((*(u32 *)radio_config != 0xffffffff) &&
201+ check_radio_magic(radio_config)) {
202+ found = 1;
203+ break;
204+ }
205+ }
206+ }
207+
208+ if (!found) {
209+ printk("Could not find Radio Configuration data\n");
210+ radio_config = 0;
211+ }
212+
213+ return (u8 *) radio_config;
214+}
215+
216+int __init
217+ar231x_find_config(u8 *flash_limit)
218+{
219+ struct ar231x_boarddata *config;
220+ unsigned int rcfg_size;
221+ int broken_boarddata = 0;
222+ u8 *bcfg, *rcfg;
223+ u8 *board_data;
224+ u8 *radio_data;
225+ u32 offset;
226+
227+ ar231x_board.config = NULL;
228+ ar231x_board.radio = NULL;
229+ /* Copy the board and radio data to RAM, because accessing the mapped
230+ * memory of the flash directly after booting is not safe */
231+
232+ /* Try to find valid board and radio data */
233+ bcfg = find_board_config(flash_limit, false);
234+
235+ /* If that fails, try to at least find valid radio data */
236+ if (!bcfg) {
237+ bcfg = find_board_config(flash_limit, true);
238+ broken_boarddata = 1;
239+ }
240+
241+ if (!bcfg) {
242+ printk(KERN_WARNING "WARNING: No board configuration data found!\n");
243+ return -ENODEV;
244+ }
245+
246+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
247+ ar231x_board.config = (struct ar231x_boarddata *) board_data;
248+ memcpy(board_data, bcfg, 0x100);
249+ if (broken_boarddata) {
250+ printk(KERN_WARNING "WARNING: broken board data detected\n");
251+ config = ar231x_board.config;
252+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
253+ printk(KERN_INFO "Fixing up empty mac addresses\n");
254+ config->resetConfigGpio = 0xffff;
255+ config->sysLedGpio = 0xffff;
256+ random_ether_addr(config->wlan0_mac);
257+ config->wlan0_mac[0] &= ~0x06;
258+ random_ether_addr(config->enet0_mac);
259+ random_ether_addr(config->enet1_mac);
260+ }
261+ }
262+
263+
264+ /* Radio config starts 0x100 bytes after board config, regardless
265+ * of what the physical layout on the flash chip looks like */
266+
267+ if (ar231x_board.radio)
268+ rcfg = (u8 *) ar231x_board.radio;
269+ else
270+ rcfg = find_radio_config(flash_limit, bcfg);
271+
272+ if (!rcfg)
273+ return -ENODEV;
274+
275+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
276+ ar231x_board.radio = radio_data;
277+ offset = radio_data - board_data;
278+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
279+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
280+ memcpy(radio_data, rcfg, rcfg_size);
281+
282+ return 0;
283+}
284+
285+static void
286+ar231x_halt(void)
287+{
288+ local_irq_disable();
289+ while (1);
290+}
291+
292+void __init
293+plat_mem_setup(void)
294+{
295+ _machine_halt = ar231x_halt;
296+ pm_power_off = ar231x_halt;
297+
298+ ar5312_plat_setup();
299+ ar2315_plat_setup();
300+
301+ /* Disable data watchpoints */
302+ write_c0_watchlo0(0);
303+}
304+
305+
306+asmlinkage void
307+plat_irq_dispatch(void)
308+{
309+ ar231x_irq_dispatch();
310+}
311+
312+void __init
313+plat_time_init(void)
314+{
315+ ar5312_time_init();
316+ ar2315_time_init();
317+}
318+
319+unsigned int __cpuinit
320+get_c0_compare_int(void)
321+{
322+ return CP0_LEGACY_COMPARE_IRQ;
323+}
324+
325+void __init
326+arch_init_irq(void)
327+{
328+ clear_c0_status(ST0_IM);
329+ mips_cpu_irq_init();
330+
331+ /* Initialize interrupt controllers */
332+ ar5312_irq_init();
333+ ar2315_irq_init();
334+}
335+
336+
337--- /dev/null
338+++ b/arch/mips/ar231x/prom.c
339@@ -0,0 +1,37 @@
340+/*
341+ * This file is subject to the terms and conditions of the GNU General Public
342+ * License. See the file "COPYING" in the main directory of this archive
343+ * for more details.
344+ *
345+ * Copyright MontaVista Software Inc
346+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
347+ * Copyright (C) 2006 FON Technology, SL.
348+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
349+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
350+ */
351+
352+/*
353+ * Prom setup file for ar531x
354+ */
355+
356+#include <linux/init.h>
357+#include <linux/autoconf.h>
358+#include <linux/kernel.h>
359+#include <linux/string.h>
360+#include <linux/mm.h>
361+#include <linux/bootmem.h>
362+
363+#include <asm/bootinfo.h>
364+#include <asm/addrspace.h>
365+#include "ar5312.h"
366+#include "ar2315.h"
367+
368+void __init prom_init(void)
369+{
370+ ar5312_prom_init();
371+ ar2315_prom_init();
372+}
373+
374+void __init prom_free_prom_memory(void)
375+{
376+}
377--- /dev/null
378+++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
379@@ -0,0 +1,83 @@
380+#ifndef __AR531X_PLATFORM_H
381+#define __AR531X_PLATFORM_H
382+
383+/*
384+ * This is board-specific data that is stored in a "fixed" location in flash.
385+ * It is shared across operating systems, so it should not be changed lightly.
386+ * The main reason we need it is in order to extract the ethernet MAC
387+ * address(es).
388+ */
389+struct ar231x_boarddata {
390+ u32 magic; /* board data is valid */
391+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
392+ u16 cksum; /* checksum (starting with BD_REV 2) */
393+ u16 rev; /* revision of this struct */
394+#define BD_REV 4
395+ char boardName[64]; /* Name of board */
396+ u16 major; /* Board major number */
397+ u16 minor; /* Board minor number */
398+ u32 flags; /* Board configuration */
399+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
400+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
401+#define BD_UART1 0x00000004 /* UART1 is stuffed */
402+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
403+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
404+#define BD_SYSLED 0x00000020 /* System LED stuffed */
405+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
406+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
407+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
408+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
409+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
410+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
411+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
412+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
413+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
414+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
415+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
416+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
417+ u16 resetConfigGpio; /* Reset factory GPIO pin */
418+ u16 sysLedGpio; /* System LED GPIO pin */
419+
420+ u32 cpuFreq; /* CPU core frequency in Hz */
421+ u32 sysFreq; /* System frequency in Hz */
422+ u32 cntFreq; /* Calculated C0_COUNT frequency */
423+
424+ u8 wlan0_mac[6];
425+ u8 enet0_mac[6];
426+ u8 enet1_mac[6];
427+
428+ u16 pciId; /* Pseudo PCIID for common code */
429+ u16 memCap; /* cap bank1 in MB */
430+
431+ /* version 3 */
432+ u8 wlan1_mac[6]; /* (ar5212) */
433+};
434+
435+#define BOARD_CONFIG_BUFSZ 0x1000
436+
437+/*
438+ * Platform device information for the Wireless MAC
439+ */
440+struct ar231x_board_config {
441+ u16 devid;
442+
443+ /* board config data */
444+ struct ar231x_boarddata *config;
445+
446+ /* radio calibration data */
447+ const char *radio;
448+};
449+
450+/*
451+ * Platform device information for the Ethernet MAC
452+ */
453+struct ar231x_eth {
454+ u32 reset_base;
455+ u32 reset_mac;
456+ u32 reset_phy;
457+ u32 phy_base;
458+ struct ar231x_board_config *config;
459+ char *macaddr;
460+};
461+
462+#endif /* __AR531X_PLATFORM_H */
463--- /dev/null
464+++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
465@@ -0,0 +1,84 @@
466+/*
467+ * Atheros SoC specific CPU feature overrides
468+ *
469+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
470+ *
471+ * This file was derived from: include/asm-mips/cpu-features.h
472+ * Copyright (C) 2003, 2004 Ralf Baechle
473+ * Copyright (C) 2004 Maciej W. Rozycki
474+ *
475+ * This program is free software; you can redistribute it and/or modify it
476+ * under the terms of the GNU General Public License version 2 as published
477+ * by the Free Software Foundation.
478+ *
479+ */
480+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
481+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
482+
483+/*
484+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
485+ */
486+#define cpu_has_tlb 1
487+#define cpu_has_4kex 1
488+#define cpu_has_3k_cache 0
489+#define cpu_has_4k_cache 1
490+#define cpu_has_tx39_cache 0
491+#define cpu_has_sb1_cache 0
492+#define cpu_has_fpu 0
493+#define cpu_has_32fpr 0
494+#define cpu_has_counter 1
495+/* #define cpu_has_watch ? */
496+/* #define cpu_has_divec ? */
497+/* #define cpu_has_vce ? */
498+/* #define cpu_has_cache_cdex_p ? */
499+/* #define cpu_has_cache_cdex_s ? */
500+/* #define cpu_has_prefetch ? */
501+/* #define cpu_has_mcheck ? */
502+#define cpu_has_ejtag 1
503+
504+#if !defined(CONFIG_ATHEROS_AR5312)
505+# define cpu_has_llsc 1
506+#else
507+/*
508+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
509+ * ll/sc instructions.
510+ */
511+# define cpu_has_llsc 0
512+#endif
513+
514+#define cpu_has_mips16 0
515+#define cpu_has_mdmx 0
516+#define cpu_has_mips3d 0
517+#define cpu_has_smartmips 0
518+
519+/* #define cpu_has_vtag_icache ? */
520+/* #define cpu_has_dc_aliases ? */
521+/* #define cpu_has_ic_fills_f_dc ? */
522+/* #define cpu_has_pindexed_dcache ? */
523+
524+/* #define cpu_icache_snoops_remote_store ? */
525+
526+#define cpu_has_mips32r1 1
527+
528+#if !defined(CONFIG_ATHEROS_AR5312)
529+# define cpu_has_mips32r2 1
530+#endif
531+
532+#define cpu_has_mips64r1 0
533+#define cpu_has_mips64r2 0
534+
535+#define cpu_has_dsp 0
536+#define cpu_has_mipsmt 0
537+
538+/* #define cpu_has_nofpuex ? */
539+#define cpu_has_64bits 0
540+#define cpu_has_64bit_zero_reg 0
541+#define cpu_has_64bit_gp_regs 0
542+#define cpu_has_64bit_addresses 0
543+
544+/* #define cpu_has_inclusive_pcaches ? */
545+
546+/* #define cpu_dcache_line_size() ? */
547+/* #define cpu_icache_line_size() ? */
548+
549+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
550--- /dev/null
551+++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
552@@ -0,0 +1,62 @@
553+/*
554+ * This file is subject to the terms and conditions of the GNU General Public
555+ * License. See the file "COPYING" in the main directory of this archive
556+ * for more details.
557+ *
558+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
559+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
560+ *
561+ */
562+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
563+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
564+
565+#define PCI_DMA_OFFSET 0x20000000
566+
567+struct device;
568+
569+static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
570+{
571+ return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
572+}
573+
574+static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
575+{
576+ return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
577+}
578+
579+static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
580+{
581+ return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
582+}
583+
584+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
585+{
586+}
587+
588+static inline int plat_dma_supported(struct device *dev, u64 mask)
589+{
590+ return 1;
591+}
592+
593+static inline void plat_extra_sync_for_device(struct device *dev)
594+{
595+ return;
596+}
597+
598+static inline int plat_dma_mapping_error(struct device *dev,
599+ dma_addr_t dma_addr)
600+{
601+ return 0;
602+}
603+
604+static inline int plat_device_is_coherent(struct device *dev)
605+{
606+#ifdef CONFIG_DMA_COHERENT
607+ return 1;
608+#endif
609+#ifdef CONFIG_DMA_NONCOHERENT
610+ return 0;
611+#endif
612+}
613+
614+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
615--- /dev/null
616+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
617@@ -0,0 +1,79 @@
618+#ifndef _ATHEROS_GPIO_H_
619+#define _ATHEROS_GPIO_H_
620+
621+#include <ar231x.h>
622+
623+struct ar231x_gpiodev {
624+ u32 valid_mask;
625+ u32 (*get_output)(void);
626+ u32 (*set_output)(u32 mask, u32 val);
627+ u32 (*get)(void);
628+ u32 (*set)(u32 mask, u32 val);
629+};
630+
631+extern const struct ar231x_gpiodev *ar231x_gpiodev;
632+
633+/*
634+ * Wrappers for the generic GPIO layer
635+ */
636+
637+static inline int gpio_direction_input(unsigned gpio) {
638+ u32 mask = 1 << gpio;
639+
640+ if (!(ar231x_gpiodev->valid_mask & mask))
641+ return -ENXIO;
642+
643+ ar231x_gpiodev->set_output(mask, 0);
644+ return 0;
645+}
646+
647+static inline void gpio_set_value(unsigned gpio, int value) {
648+ u32 mask = 1 << gpio;
649+
650+ if (!(ar231x_gpiodev->valid_mask & mask))
651+ return;
652+
653+ ar231x_gpiodev->set(mask, (!!value) * mask);
654+}
655+
656+static inline int gpio_direction_output(unsigned gpio, int value) {
657+ u32 mask = 1 << gpio;
658+
659+ if (!(ar231x_gpiodev->valid_mask & mask))
660+ return -ENXIO;
661+
662+ ar231x_gpiodev->set_output(mask, mask);
663+ ar231x_gpiodev->set(mask, (!!value) * mask);
664+ return 0;
665+}
666+
667+/* Reads the gpio pin. Unchecked function */
668+static inline int gpio_get_value(unsigned gpio) {
669+ u32 mask = 1 << gpio;
670+
671+ if (!(ar231x_gpiodev->valid_mask & mask))
672+ return 0;
673+
674+ return !!(ar231x_gpiodev->get() & mask);
675+}
676+
677+static inline int gpio_request(unsigned gpio, const char *label) {
678+ return 0;
679+}
680+
681+static inline void gpio_free(unsigned gpio) {
682+}
683+
684+/* Returns IRQ to attach for gpio. Unchecked function */
685+static inline int gpio_to_irq(unsigned gpio) {
686+ return AR531X_GPIO_IRQ(gpio);
687+}
688+
689+/* Returns gpio for IRQ attached. Unchecked function */
690+static inline int irq_to_gpio(unsigned irq) {
691+ return (irq - (AR531X_GPIO_IRQ(0)));
692+}
693+
694+#include <asm-generic/gpio.h> /* cansleep wrappers */
695+
696+#endif
697--- /dev/null
698+++ b/arch/mips/include/asm/mach-ar231x/reset.h
699@@ -0,0 +1,6 @@
700+#ifndef __AR531X_RESET_H
701+#define __AR531X_RESET_H
702+
703+void ar531x_disable_reset_button(void);
704+
705+#endif /* __AR531X_RESET_H */
706--- /dev/null
707+++ b/arch/mips/include/asm/mach-ar231x/war.h
708@@ -0,0 +1,25 @@
709+/*
710+ * This file is subject to the terms and conditions of the GNU General Public
711+ * License. See the file "COPYING" in the main directory of this archive
712+ * for more details.
713+ *
714+ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
715+ */
716+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
717+#define __ASM_MIPS_MACH_ATHEROS_WAR_H
718+
719+#define R4600_V1_INDEX_ICACHEOP_WAR 0
720+#define R4600_V1_HIT_CACHEOP_WAR 0
721+#define R4600_V2_HIT_CACHEOP_WAR 0
722+#define R5432_CP0_INTERRUPT_WAR 0
723+#define BCM1250_M3_WAR 0
724+#define SIBYTE_1956_WAR 0
725+#define MIPS4K_ICACHE_REFILL_WAR 0
726+#define MIPS_CACHE_SYNC_WAR 0
727+#define TX49XX_ICACHE_INDEX_INV_WAR 0
728+#define RM9000_CDEX_SMP_WAR 0
729+#define ICACHE_REFILLS_WORKAROUND_WAR 0
730+#define R10000_LLSC_WAR 0
731+#define MIPS34K_MISSED_ITLB_WAR 0
732+
733+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
734--- /dev/null
735+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
736@@ -0,0 +1,580 @@
737+/*
738+ * Register definitions for AR2315+
739+ *
740+ * This file is subject to the terms and conditions of the GNU General Public
741+ * License. See the file "COPYING" in the main directory of this archive
742+ * for more details.
743+ *
744+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
745+ * Copyright (C) 2006 FON Technology, SL.
746+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
747+ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
748+ */
749+
750+#ifndef __AR2315_REG_H
751+#define __AR2315_REG_H
752+
753+/*
754+ * IRQs
755+ */
756+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
757+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
758+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
759+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
760+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
761+
762+/*
763+ * Address map
764+ */
765+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
766+#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */
767+#define AR2315_PCI 0xB0100000 /* PCI MMR */
768+#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */
769+#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */
770+#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */
771+#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
772+#define AR2315_UART0 0xB1100003 /* UART MMR */
773+#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */
774+#define AR2315_PCIEXT 0x80000000 /* pci external */
775+
776+/*
777+ * Reset Register
778+ */
779+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
780+
781+#define AR2315_RESET_COLD_AHB 0x00000001
782+#define AR2315_RESET_COLD_APB 0x00000002
783+#define AR2315_RESET_COLD_CPU 0x00000004
784+#define AR2315_RESET_COLD_CPUWARM 0x00000008
785+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
786+#define AR2317_RESET_SYSTEM 0x00000010
787+
788+
789+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
790+
791+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
792+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
793+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
794+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
795+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
796+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
797+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
798+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
799+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
800+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
801+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
802+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
803+
804+/*
805+ * AHB master arbitration control
806+ */
807+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
808+
809+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
810+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
811+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
812+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
813+#define AR2315_ARB_PCI 0x00000010 /* PCI */
814+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
815+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
816+
817+/*
818+ * Config Register
819+ */
820+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
821+
822+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
823+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
824+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
825+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
826+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
827+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
828+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
829+
830+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
831+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
832+#define AR2315_CONFIG_PCIAHB 0x00000800
833+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
834+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
835+#define AR2315_CONFIG_CPU_DRAM 0x00010000
836+#define AR2315_CONFIG_CPU_PCI 0x00020000
837+#define AR2315_CONFIG_CPU_MMR 0x00040000
838+#define AR2315_CONFIG_BIG 0x00000400
839+
840+
841+/*
842+ * NMI control
843+ */
844+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
845+
846+#define AR2315_NMI_EN 1
847+
848+/*
849+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
850+ */
851+#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
852+
853+#define AR2315_REV_MAJ 0x00f0
854+#define AR2315_REV_MAJ_S 4
855+#define AR2315_REV_MIN 0x000f
856+#define AR2315_REV_MIN_S 0
857+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
858+
859+/*
860+ * Interface Enable
861+ */
862+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
863+
864+#define AR2315_IF_MASK 0x00000007
865+#define AR2315_IF_DISABLED 0
866+#define AR2315_IF_PCI 1
867+#define AR2315_IF_TS_LOCAL 2
868+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
869+#define AR2315_IF_LOCAL_HOST 0x00000008
870+#define AR2315_IF_PCI_HOST 0x00000010
871+#define AR2315_IF_PCI_INTR 0x00000020
872+#define AR2315_IF_PCI_CLK_MASK 0x00030000
873+#define AR2315_IF_PCI_CLK_INPUT 0
874+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
875+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
876+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
877+#define AR2315_IF_PCI_CLK_SHIFT 16
878+
879+/*
880+ * APB Interrupt control
881+ */
882+
883+#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
884+#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
885+#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
886+
887+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
888+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
889+#define AR2315_ISR_SPI 0x0004 /* SPI bus */
890+#define AR2315_ISR_AHB 0x0008 /* AHB error */
891+#define AR2315_ISR_APB 0x0010 /* APB error */
892+#define AR2315_ISR_TIMER 0x0020 /* timer */
893+#define AR2315_ISR_GPIO 0x0040 /* GPIO */
894+#define AR2315_ISR_WD 0x0080 /* watchdog */
895+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
896+
897+#define AR2315_GISR_MISC 0x0001
898+#define AR2315_GISR_WLAN0 0x0002
899+#define AR2315_GISR_MPEGTS_RSVD 0x0004
900+#define AR2315_GISR_LOCALPCI 0x0008
901+#define AR2315_GISR_WMACPOLL 0x0010
902+#define AR2315_GISR_TIMER 0x0020
903+#define AR2315_GISR_ETHERNET 0x0040
904+
905+/*
906+ * Interrupt routing from IO to the processor IP bits
907+ * Define our inter mask and level
908+ */
909+#define AR2315_INTR_MISCIO SR_IBIT3
910+#define AR2315_INTR_WLAN0 SR_IBIT4
911+#define AR2315_INTR_ENET0 SR_IBIT5
912+#define AR2315_INTR_LOCALPCI SR_IBIT6
913+#define AR2315_INTR_WMACPOLL SR_IBIT7
914+#define AR2315_INTR_COMPARE SR_IBIT8
915+
916+/*
917+ * Timers
918+ */
919+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
920+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
921+#define AR2315_WD (AR2315_DSLBASE + 0x0038)
922+#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
923+
924+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
925+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
926+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
927+
928+/*
929+ * CPU Performance Counters
930+ */
931+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
932+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
933+
934+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
935+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
936+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
937+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
938+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
939+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
940+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
941+
942+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
943+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
944+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
945+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
946+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
947+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
948+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
949+
950+/*
951+ * AHB Error Reporting.
952+ */
953+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
954+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
955+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
956+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
957+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
958+
959+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
960+ /* write 1 to clear all bits in ERR0 */
961+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
962+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
963+
964+#define AR2315_PROCERR_HMAST 0x0000000f
965+#define AR2315_PROCERR_HMAST_DFLT 0
966+#define AR2315_PROCERR_HMAST_WMAC 1
967+#define AR2315_PROCERR_HMAST_ENET 2
968+#define AR2315_PROCERR_HMAST_PCIENDPT 3
969+#define AR2315_PROCERR_HMAST_LOCAL 4
970+#define AR2315_PROCERR_HMAST_CPU 5
971+#define AR2315_PROCERR_HMAST_PCITGT 6
972+
973+#define AR2315_PROCERR_HMAST_S 0
974+#define AR2315_PROCERR_HWRITE 0x00000010
975+#define AR2315_PROCERR_HSIZE 0x00000060
976+#define AR2315_PROCERR_HSIZE_S 5
977+#define AR2315_PROCERR_HTRANS 0x00000180
978+#define AR2315_PROCERR_HTRANS_S 7
979+#define AR2315_PROCERR_HBURST 0x00000e00
980+#define AR2315_PROCERR_HBURST_S 9
981+
982+/*
983+ * Clock Control
984+ */
985+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
986+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
987+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
988+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
989+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
990+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
991+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
992+
993+/* PLLc Control fields */
994+#define PLLC_REF_DIV_M 0x00000003
995+#define PLLC_REF_DIV_S 0
996+#define PLLC_FDBACK_DIV_M 0x0000007C
997+#define PLLC_FDBACK_DIV_S 2
998+#define PLLC_ADD_FDBACK_DIV_M 0x00000080
999+#define PLLC_ADD_FDBACK_DIV_S 7
1000+#define PLLC_CLKC_DIV_M 0x0001c000
1001+#define PLLC_CLKC_DIV_S 14
1002+#define PLLC_CLKM_DIV_M 0x00700000
1003+#define PLLC_CLKM_DIV_S 20
1004+
1005+/* CPU CLK Control fields */
1006+#define CPUCLK_CLK_SEL_M 0x00000003
1007+#define CPUCLK_CLK_SEL_S 0
1008+#define CPUCLK_CLK_DIV_M 0x0000000c
1009+#define CPUCLK_CLK_DIV_S 2
1010+
1011+/* AMBA CLK Control fields */
1012+#define AMBACLK_CLK_SEL_M 0x00000003
1013+#define AMBACLK_CLK_SEL_S 0
1014+#define AMBACLK_CLK_DIV_M 0x0000000c
1015+#define AMBACLK_CLK_DIV_S 2
1016+
1017+/*
1018+ * GPIO
1019+ */
1020+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1021+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1022+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1023+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1024+
1025+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1026+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1027+#define AR2315_GPIO_CR_I(x) (0) /* input */
1028+
1029+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1030+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1031+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1032+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1033+
1034+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1035+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1036+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1037+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1038+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1039+
1040+#define AR2315_RESET_GPIO 5
1041+#define AR2315_NUM_GPIO 22
1042+
1043+/*
1044+ * PCI Clock Control
1045+ */
1046+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1047+
1048+#define AR2315_PCICLK_INPUT_M 0x3
1049+#define AR2315_PCICLK_INPUT_S 0
1050+
1051+#define AR2315_PCICLK_PLLC_CLKM 0
1052+#define AR2315_PCICLK_PLLC_CLKM1 1
1053+#define AR2315_PCICLK_PLLC_CLKC 2
1054+#define AR2315_PCICLK_REF_CLK 3
1055+
1056+#define AR2315_PCICLK_DIV_M 0xc
1057+#define AR2315_PCICLK_DIV_S 2
1058+
1059+#define AR2315_PCICLK_IN_FREQ 0
1060+#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1061+#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1062+#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1063+
1064+/*
1065+ * Observation Control Register
1066+ */
1067+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1068+#define OCR_GPIO0_IRIN 0x0040
1069+#define OCR_GPIO1_IROUT 0x0080
1070+#define OCR_GPIO3_RXCLR 0x0200
1071+
1072+/*
1073+ * General Clock Control
1074+ */
1075+
1076+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1077+#define MISCCLK_PLLBYPASS_EN 0x00000001
1078+#define MISCCLK_PROCREFCLK 0x00000002
1079+
1080+/*
1081+ * SDRAM Controller
1082+ * - No read or write buffers are included.
1083+ */
1084+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1085+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1086+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1087+
1088+#define SDRAM_DATA_WIDTH_M 0x00006000
1089+#define SDRAM_DATA_WIDTH_S 13
1090+
1091+#define SDRAM_COL_WIDTH_M 0x00001E00
1092+#define SDRAM_COL_WIDTH_S 9
1093+
1094+#define SDRAM_ROW_WIDTH_M 0x000001E0
1095+#define SDRAM_ROW_WIDTH_S 5
1096+
1097+#define SDRAM_BANKADDR_BITS_M 0x00000018
1098+#define SDRAM_BANKADDR_BITS_S 3
1099+
1100+/*
1101+ * SPI Flash Interface Registers
1102+ */
1103+
1104+#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1105+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1106+#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1107+
1108+#define SPI_CTL_START 0x00000100
1109+#define SPI_CTL_BUSY 0x00010000
1110+#define SPI_CTL_TXCNT_MASK 0x0000000f
1111+#define SPI_CTL_RXCNT_MASK 0x000000f0
1112+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1113+#define SPI_CTL_SIZE_MASK 0x00060000
1114+
1115+#define SPI_CTL_CLK_SEL_MASK 0x03000000
1116+#define SPI_OPCODE_MASK 0x000000ff
1117+
1118+/*
1119+ * PCI Bus Interface Registers
1120+ */
1121+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1122+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1123+
1124+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1125+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1126+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1127+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1128+#define AR2315_PCIMISC_RST_MODE 0x00000030
1129+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1130+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1131+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1132+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1133+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1134+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1135+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1136+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1137+
1138+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1139+
1140+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1141+
1142+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1143+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1144+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1145+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1146+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1147+
1148+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1149+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1150+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1151+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1152+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1153+
1154+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1155+
1156+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1157+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1158+
1159+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1160+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1161+
1162+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1163+
1164+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1165+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1166+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1167+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1168+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1169+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1170+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1171+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1172+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1173+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1174+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1175+#define AR2315_PCI_EXT_INT 0x02000000
1176+#define AR2315_PCI_ABORT_INT 0x04000000
1177+
1178+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1179+
1180+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1181+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1182+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1183+
1184+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1185+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1186+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1187+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1188+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1189+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1190+
1191+
1192+/*
1193+ * Local Bus Interface Registers
1194+ */
1195+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1196+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1197+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1198+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1199+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1200+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1201+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1202+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1203+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1204+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1205+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1206+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1207+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1208+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1209+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1210+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1211+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1212+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1213+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1214+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1215+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1216+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1217+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1218+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1219+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1220+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1221+
1222+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1223+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1224+
1225+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1226+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1227+
1228+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1229+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1230+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1231+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1232+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1233+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1234+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1235+#define AR2315_LBM_TIMEOUT_SHFT 7
1236+#define AR2315_LBM_PORTMUX 0x07000000
1237+
1238+
1239+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1240+
1241+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1242+#define AR2315_LB_TXEN_0 0x01
1243+#define AR2315_LB_TXEN_1 0x02
1244+#define AR2315_LB_TXEN_2 0x04
1245+#define AR2315_LB_TXEN_3 0x08
1246+
1247+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1248+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1249+
1250+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1251+#define AR2315_LB_RXEN 0x01
1252+
1253+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1254+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1255+
1256+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1257+#define AR2315_INT_TX_DESC 0x0001
1258+#define AR2315_INT_TX_OK 0x0002
1259+#define AR2315_INT_TX_ERR 0x0004
1260+#define AR2315_INT_TX_EOF 0x0008
1261+#define AR2315_INT_RX_DESC 0x0010
1262+#define AR2315_INT_RX_OK 0x0020
1263+#define AR2315_INT_RX_ERR 0x0040
1264+#define AR2315_INT_RX_EOF 0x0080
1265+#define AR2315_INT_TX_TRUNC 0x0100
1266+#define AR2315_INT_TX_STARVE 0x0200
1267+#define AR2315_INT_LB_TIMEOUT 0x0400
1268+#define AR2315_INT_LB_ERR 0x0800
1269+#define AR2315_INT_MBOX_WR 0x1000
1270+#define AR2315_INT_MBOX_RD 0x2000
1271+
1272+/* Bit definitions for INT MASK are the same as INT_STATUS */
1273+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1274+
1275+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1276+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1277+
1278+/*
1279+ * IR Interface Registers
1280+ */
1281+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1282+
1283+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1284+
1285+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1286+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1287+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1288+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1289+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1290+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1291+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1292+
1293+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1294+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1295+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1296+
1297+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1298+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1299+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1300+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1301+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1302+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1303+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1304+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1305+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1306+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1307+
1308+#define HOST_PCI_DEV_ID 3
1309+#define HOST_PCI_MBAR0 0x10000000
1310+#define HOST_PCI_MBAR1 0x20000000
1311+#define HOST_PCI_MBAR2 0x30000000
1312+
1313+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1314+#define PCI_DEVICE_MEM_SPACE 0x800000
1315+
1316+#endif /* __AR2315_REG_H */
1317--- /dev/null
1318+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1319@@ -0,0 +1,236 @@
1320+/*
1321+ * This file is subject to the terms and conditions of the GNU General Public
1322+ * License. See the file "COPYING" in the main directory of this archive
1323+ * for more details.
1324+ *
1325+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1326+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1327+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1328+ */
1329+
1330+#ifndef AR5312_H
1331+#define AR5312_H
1332+
1333+#include <asm/addrspace.h>
1334+
1335+/*
1336+ * IRQs
1337+ */
1338+
1339+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1340+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1341+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1342+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1343+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1344+
1345+
1346+/* Address Map */
1347+#define AR531X_WLAN0 0x18000000
1348+#define AR531X_WLAN1 0x18500000
1349+#define AR531X_ENET0 0x18100000
1350+#define AR531X_ENET1 0x18200000
1351+#define AR531X_SDRAMCTL 0x18300000
1352+#define AR531X_FLASHCTL 0x18400000
1353+#define AR531X_APBBASE 0x1c000000
1354+#define AR531X_FLASH 0x1e000000
1355+#define AR531X_UART0 0xbc000003 /* UART MMR */
1356+
1357+/*
1358+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1359+ * should be considered available. The AR5312 supports 2 enet MACS,
1360+ * even though many reference boards only actually use 1 of them
1361+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1362+ * The AR2312 supports 1 enet MAC.
1363+ */
1364+#define AR531X_NUM_ENET_MAC 2
1365+
1366+/*
1367+ * Need these defines to determine true number of ethernet MACs
1368+ */
1369+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1370+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1371+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1372+#define AR531X_RADIO_MASK_OFF 0xc8
1373+#define AR531X_RADIO0_MASK 0x0003
1374+#define AR531X_RADIO1_MASK 0x000c
1375+#define AR531X_RADIO1_S 2
1376+
1377+/*
1378+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1379+ * should be considered available.
1380+ */
1381+#define AR531X_NUM_WMAC 2
1382+
1383+/* Reset/Timer Block Address Map */
1384+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1385+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1386+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1387+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1388+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1389+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1390+#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1391+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1392+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1393+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1394+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1395+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1396+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1397+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1398+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1399+
1400+/* AR531X_WD_CTRL register bit field definitions */
1401+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1402+#define AR531X_WD_CTRL_NMI 0x0001
1403+#define AR531X_WD_CTRL_RESET 0x0002
1404+
1405+/* AR531X_ISR register bit field definitions */
1406+#define AR531X_ISR_NONE 0x0000
1407+#define AR531X_ISR_TIMER 0x0001
1408+#define AR531X_ISR_AHBPROC 0x0002
1409+#define AR531X_ISR_AHBDMA 0x0004
1410+#define AR531X_ISR_GPIO 0x0008
1411+#define AR531X_ISR_UART0 0x0010
1412+#define AR531X_ISR_UART0DMA 0x0020
1413+#define AR531X_ISR_WD 0x0040
1414+#define AR531X_ISR_LOCAL 0x0080
1415+
1416+/* AR531X_RESET register bit field definitions */
1417+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1418+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1419+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1420+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1421+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1422+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1423+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1424+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1425+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1426+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1427+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1428+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1429+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1430+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1431+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1432+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1433+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1434+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1435+
1436+#define AR531X_RESET_WMAC0_BITS \
1437+ AR531X_RESET_WLAN0 |\
1438+ AR531X_RESET_WARM_WLAN0_MAC |\
1439+ AR531X_RESET_WARM_WLAN0_BB
1440+
1441+#define AR531X_RESERT_WMAC1_BITS \
1442+ AR531X_RESET_WLAN1 |\
1443+ AR531X_RESET_WARM_WLAN1_MAC |\
1444+ AR531X_RESET_WARM_WLAN1_BB
1445+
1446+/* AR5312_CLOCKCTL1 register bit field definitions */
1447+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1448+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1449+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1450+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1451+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1452+
1453+/* Valid for AR5312 and AR2312 */
1454+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1455+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1456+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1457+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1458+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1459+
1460+/* Valid for AR2313 */
1461+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1462+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1463+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1464+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1465+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1466+
1467+
1468+/* AR531X_ENABLE register bit field definitions */
1469+#define AR531X_ENABLE_WLAN0 0x0001
1470+#define AR531X_ENABLE_ENET0 0x0002
1471+#define AR531X_ENABLE_ENET1 0x0004
1472+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1473+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1474+#define AR531X_ENABLE_WLAN1 \
1475+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1476+
1477+/* AR531X_REV register bit field definitions */
1478+#define AR531X_REV_WMAC_MAJ 0xf000
1479+#define AR531X_REV_WMAC_MAJ_S 12
1480+#define AR531X_REV_WMAC_MIN 0x0f00
1481+#define AR531X_REV_WMAC_MIN_S 8
1482+#define AR531X_REV_MAJ 0x00f0
1483+#define AR531X_REV_MAJ_S 4
1484+#define AR531X_REV_MIN 0x000f
1485+#define AR531X_REV_MIN_S 0
1486+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1487+
1488+/* Major revision numbers, bits 7..4 of Revision ID register */
1489+#define AR531X_REV_MAJ_AR5312 0x4
1490+#define AR531X_REV_MAJ_AR2313 0x5
1491+
1492+/* Minor revision numbers, bits 3..0 of Revision ID register */
1493+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1494+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1495+
1496+/* AR531X_FLASHCTL register bit field definitions */
1497+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1498+#define FLASHCTL_IDCY_S 0
1499+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1500+#define FLASHCTL_WST1_S 5
1501+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1502+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1503+#define FLASHCTL_WST2_S 11
1504+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1505+#define FLASHCTL_AC_S 16
1506+#define FLASHCTL_AC_128K 0x00000000
1507+#define FLASHCTL_AC_256K 0x00010000
1508+#define FLASHCTL_AC_512K 0x00020000
1509+#define FLASHCTL_AC_1M 0x00030000
1510+#define FLASHCTL_AC_2M 0x00040000
1511+#define FLASHCTL_AC_4M 0x00050000
1512+#define FLASHCTL_AC_8M 0x00060000
1513+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1514+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1515+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1516+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1517+#define FLASHCTL_WP 0x04000000 /* Write protect */
1518+#define FLASHCTL_BM 0x08000000 /* Burst mode */
1519+#define FLASHCTL_MW 0x30000000 /* Memory width */
1520+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1521+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1522+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1523+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1524+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1525+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1526+
1527+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1528+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1529+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1530+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1531+
1532+/* ARM SDRAM Controller -- just enough to determine memory size */
1533+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1534+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1535+#define MEM_CFG1_AC0_S 8
1536+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1537+#define MEM_CFG1_AC1_S 12
1538+
1539+/* GPIO Address Map */
1540+#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1541+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1542+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1543+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1544+
1545+/* GPIO Control Register bit field definitions */
1546+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1547+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1548+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1549+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1550+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1551+#define AR531X_NUM_GPIO 8
1552+
1553+
1554+#endif
1555+
1556--- /dev/null
1557+++ b/arch/mips/ar231x/ar5312.c
1558@@ -0,0 +1,549 @@
1559+/*
1560+ * This file is subject to the terms and conditions of the GNU General Public
1561+ * License. See the file "COPYING" in the main directory of this archive
1562+ * for more details.
1563+ *
1564+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1565+ * Copyright (C) 2006 FON Technology, SL.
1566+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1567+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1568+ */
1569+
1570+/*
1571+ * Platform devices for Atheros SoCs
1572+ */
1573+
1574+#include <linux/autoconf.h>
1575+#include <linux/init.h>
1576+#include <linux/module.h>
1577+#include <linux/types.h>
1578+#include <linux/string.h>
1579+#include <linux/mtd/physmap.h>
1580+#include <linux/platform_device.h>
1581+#include <linux/kernel.h>
1582+#include <linux/reboot.h>
1583+#include <linux/leds.h>
1584+#include <asm/bootinfo.h>
1585+#include <asm/reboot.h>
1586+#include <asm/time.h>
1587+#include <asm/irq.h>
1588+#include <asm/io.h>
1589+#include <gpio.h>
1590+
1591+#include <ar231x_platform.h>
1592+#include <ar5312_regs.h>
1593+#include <ar231x.h>
1594+#include "devices.h"
1595+#include "ar5312.h"
1596+
1597+static void
1598+ar5312_misc_irq_dispatch(void)
1599+{
1600+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1601+
1602+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1603+ do_IRQ(AR531X_MISC_IRQ_TIMER);
1604+ (void)ar231x_read_reg(AR531X_TIMER);
1605+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1606+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1607+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1608+ do_IRQ(AR531X_MISC_IRQ_UART0);
1609+ else if (ar231x_misc_intrs & AR531X_ISR_WD)
1610+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1611+ else
1612+ do_IRQ(AR531X_MISC_IRQ_NONE);
1613+}
1614+
1615+static asmlinkage void
1616+ar5312_irq_dispatch(void)
1617+{
1618+ int pending = read_c0_status() & read_c0_cause();
1619+
1620+ if (pending & CAUSEF_IP2)
1621+ do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1622+ else if (pending & CAUSEF_IP3)
1623+ do_IRQ(AR5312_IRQ_ENET0_INTRS);
1624+ else if (pending & CAUSEF_IP4)
1625+ do_IRQ(AR5312_IRQ_ENET1_INTRS);
1626+ else if (pending & CAUSEF_IP5)
1627+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1628+ else if (pending & CAUSEF_IP6)
1629+ ar5312_misc_irq_dispatch();
1630+ else if (pending & CAUSEF_IP7)
1631+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
1632+}
1633+
1634+
1635+/* Enable the specified AR531X_MISC_IRQ interrupt */
1636+static void
1637+ar5312_misc_intr_enable(unsigned int irq)
1638+{
1639+ unsigned int imr;
1640+
1641+ imr = ar231x_read_reg(AR531X_IMR);
1642+ imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1643+ ar231x_write_reg(AR531X_IMR, imr);
1644+}
1645+
1646+/* Disable the specified AR531X_MISC_IRQ interrupt */
1647+static void
1648+ar5312_misc_intr_disable(unsigned int irq)
1649+{
1650+ unsigned int imr;
1651+
1652+ imr = ar231x_read_reg(AR531X_IMR);
1653+ imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1654+ ar231x_write_reg(AR531X_IMR, imr);
1655+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1656+}
1657+
1658+static void
1659+ar5312_misc_intr_end(unsigned int irq)
1660+{
1661+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1662+ ar5312_misc_intr_enable(irq);
1663+}
1664+
1665+static struct irq_chip ar5312_misc_intr_controller = {
1666+ .name = "AR5312-MISC",
1667+ .disable = ar5312_misc_intr_disable,
1668+ .ack = ar5312_misc_intr_disable,
1669+ .mask_ack = ar5312_misc_intr_disable,
1670+ .mask = ar5312_misc_intr_disable,
1671+ .unmask = ar5312_misc_intr_enable,
1672+ .end = ar5312_misc_intr_end,
1673+};
1674+
1675+
1676+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1677+{
1678+ u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1679+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1680+ u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1681+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1682+
1683+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1684+ procAddr, proc1, dmaAddr, dma1);
1685+
1686+ machine_restart("AHB error"); /* Catastrophic failure */
1687+ return IRQ_HANDLED;
1688+}
1689+
1690+
1691+static struct irqaction ar5312_ahb_proc_interrupt = {
1692+ .handler = ar5312_ahb_proc_handler,
1693+ .flags = IRQF_DISABLED,
1694+ .name = "ar5312_ahb_proc_interrupt",
1695+};
1696+
1697+
1698+static struct irqaction cascade = {
1699+ .handler = no_action,
1700+ .flags = IRQF_DISABLED,
1701+ .name = "cascade",
1702+};
1703+
1704+void __init ar5312_irq_init(void)
1705+{
1706+ int i;
1707+
1708+ if (!is_5312())
1709+ return;
1710+
1711+ ar231x_irq_dispatch = ar5312_irq_dispatch;
1712+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1713+ int irq = AR531X_MISC_IRQ_BASE + i;
1714+ set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller,
1715+ handle_level_irq);
1716+ }
1717+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1718+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1719+}
1720+
1721+const struct ar231x_gpiodev ar5312_gpiodev;
1722+
1723+static u32
1724+ar5312_gpio_get_output(void)
1725+{
1726+ u32 reg;
1727+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1728+ reg &= ar5312_gpiodev.valid_mask;
1729+ return reg;
1730+}
1731+
1732+static u32
1733+ar5312_gpio_set_output(u32 mask, u32 val)
1734+{
1735+ u32 reg;
1736+
1737+ reg = ar231x_read_reg(AR531X_GPIO_CR);
1738+ reg |= mask;
1739+ reg &= ~val;
1740+ ar231x_write_reg(AR531X_GPIO_CR, reg);
1741+ return reg;
1742+}
1743+
1744+static u32
1745+ar5312_gpio_get(void)
1746+{
1747+ u32 reg;
1748+ reg = ar231x_read_reg(AR531X_GPIO_DI);
1749+ reg &= ar5312_gpiodev.valid_mask;
1750+ return reg;
1751+}
1752+
1753+static u32
1754+ar5312_gpio_set(u32 mask, u32 value)
1755+{
1756+ u32 reg;
1757+ reg = ar231x_read_reg(AR531X_GPIO_DO);
1758+ reg &= ~mask;
1759+ reg |= value;
1760+ ar231x_write_reg(AR531X_GPIO_DO, reg);
1761+ return reg;
1762+}
1763+
1764+const struct ar231x_gpiodev ar5312_gpiodev = {
1765+ .valid_mask = (1 << 8) - 1,
1766+ .get_output = ar5312_gpio_get_output,
1767+ .set_output = ar5312_gpio_set_output,
1768+ .get = ar5312_gpio_get,
1769+ .set = ar5312_gpio_set,
1770+};
1771+
1772+static struct physmap_flash_data ar5312_flash_data = {
1773+ .width = 2,
1774+};
1775+
1776+static struct resource ar5312_flash_resource = {
1777+ .start = AR531X_FLASH,
1778+ .end = AR531X_FLASH + 0x800000 - 1,
1779+ .flags = IORESOURCE_MEM,
1780+};
1781+
1782+static struct ar231x_eth ar5312_eth0_data = {
1783+ .reset_base = AR531X_RESET,
1784+ .reset_mac = AR531X_RESET_ENET0,
1785+ .reset_phy = AR531X_RESET_EPHY0,
1786+ .phy_base = KSEG1ADDR(AR531X_ENET0),
1787+ .config = &ar231x_board,
1788+};
1789+
1790+static struct ar231x_eth ar5312_eth1_data = {
1791+ .reset_base = AR531X_RESET,
1792+ .reset_mac = AR531X_RESET_ENET1,
1793+ .reset_phy = AR531X_RESET_EPHY1,
1794+ .phy_base = KSEG1ADDR(AR531X_ENET1),
1795+ .config = &ar231x_board,
1796+};
1797+
1798+static struct platform_device ar5312_physmap_flash = {
1799+ .name = "physmap-flash",
1800+ .id = 0,
1801+ .dev.platform_data = &ar5312_flash_data,
1802+ .resource = &ar5312_flash_resource,
1803+ .num_resources = 1,
1804+};
1805+
1806+#ifdef CONFIG_LEDS_GPIO
1807+static struct gpio_led ar5312_leds[] = {
1808+ { .name = "wlan", .gpio = 0, .active_low = 1, },
1809+};
1810+
1811+static const struct gpio_led_platform_data ar5312_led_data = {
1812+ .num_leds = ARRAY_SIZE(ar5312_leds),
1813+ .leds = (void *) ar5312_leds,
1814+};
1815+
1816+static struct platform_device ar5312_gpio_leds = {
1817+ .name = "leds-gpio",
1818+ .id = -1,
1819+ .dev.platform_data = (void *) &ar5312_led_data,
1820+};
1821+#endif
1822+
1823+/*
1824+ * NB: This mapping size is larger than the actual flash size,
1825+ * but this shouldn't be a problem here, because the flash
1826+ * will simply be mapped multiple times.
1827+ */
1828+static char __init *ar5312_flash_limit(void)
1829+{
1830+ u32 ctl;
1831+ /*
1832+ * Configure flash bank 0.
1833+ * Assume 8M window size. Flash will be aliased if it's smaller
1834+ */
1835+ ctl = FLASHCTL_E |
1836+ FLASHCTL_AC_8M |
1837+ FLASHCTL_RBLE |
1838+ (0x01 << FLASHCTL_IDCY_S) |
1839+ (0x07 << FLASHCTL_WST1_S) |
1840+ (0x07 << FLASHCTL_WST2_S) |
1841+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1842+
1843+ ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1844+
1845+ /* Disable other flash banks */
1846+ ar231x_write_reg(AR531X_FLASHCTL1,
1847+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1848+
1849+ ar231x_write_reg(AR531X_FLASHCTL2,
1850+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1851+
1852+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1853+}
1854+
1855+int __init ar5312_init_devices(void)
1856+{
1857+ struct ar231x_boarddata *config;
1858+ u32 fctl = 0;
1859+ const u8 *radio;
1860+ u8 *c;
1861+
1862+ if (!is_5312())
1863+ return 0;
1864+
1865+ /* Locate board/radio config data */
1866+ ar231x_find_config(ar5312_flash_limit());
1867+ config = ar231x_board.config;
1868+
1869+
1870+ /*
1871+ * Chip IDs and hardware detection for some Atheros
1872+ * models are really broken!
1873+ *
1874+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1875+ * as indication for AR2312, which is otherwise
1876+ * indistinguishable from the real AR5312.
1877+ */
1878+ if (ar231x_board.radio) {
1879+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1880+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1881+ config->flags |= BD_ISCASPER;
1882+ } else
1883+ radio = NULL;
1884+
1885+ /* AR2313 has CPU minor rev. 10 */
1886+ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1887+ ar231x_devtype = DEV_TYPE_AR2313;
1888+
1889+ /* AR2312 shares the same Silicon ID as AR5312 */
1890+ else if (config->flags & BD_ISCASPER)
1891+ ar231x_devtype = DEV_TYPE_AR2312;
1892+
1893+ /* Everything else is probably AR5312 or compatible */
1894+ else
1895+ ar231x_devtype = DEV_TYPE_AR5312;
1896+
1897+ /* fixup flash width */
1898+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1899+ switch (fctl) {
1900+ case FLASHCTL_MWx16:
1901+ ar5312_flash_data.width = 2;
1902+ break;
1903+ case FLASHCTL_MWx8:
1904+ default:
1905+ ar5312_flash_data.width = 1;
1906+ break;
1907+ }
1908+
1909+ platform_device_register(&ar5312_physmap_flash);
1910+
1911+#ifdef CONFIG_LEDS_GPIO
1912+ ar5312_leds[0].gpio = config->sysLedGpio;
1913+ platform_device_register(&ar5312_gpio_leds);
1914+#endif
1915+
1916+ /* Fix up MAC addresses if necessary */
1917+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1918+ memcpy(config->enet0_mac, config->enet1_mac, 6);
1919+
1920+ /* If ENET0 and ENET1 have the same mac address,
1921+ * increment the one from ENET1 */
1922+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1923+ c = config->enet1_mac + 5;
1924+ while ((c >= config->enet1_mac) && !(++(*c)))
1925+ c--;
1926+ }
1927+
1928+ switch(ar231x_devtype) {
1929+ case DEV_TYPE_AR5312:
1930+ ar5312_eth0_data.macaddr = config->enet0_mac;
1931+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1932+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1933+
1934+ ar5312_eth1_data.macaddr = config->enet1_mac;
1935+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1936+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1937+
1938+ if (!ar231x_board.radio)
1939+ return 0;
1940+
1941+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) &&
1942+ (config->flags & BD_WLAN0))
1943+ ar231x_add_wmac(0, AR531X_WLAN0,
1944+ AR5312_IRQ_WLAN0_INTRS);
1945+
1946+ break;
1947+ /*
1948+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1949+ * of ENET1. Atheros calls it 'twisted' for a reason :)
1950+ */
1951+ case DEV_TYPE_AR2312:
1952+ case DEV_TYPE_AR2313:
1953+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1954+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1955+ ar5312_eth1_data.macaddr = config->enet0_mac;
1956+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1957+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1958+
1959+ if (!ar231x_board.radio)
1960+ return 0;
1961+ break;
1962+ default:
1963+ break;
1964+ }
1965+
1966+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) &&
1967+ (config->flags & BD_WLAN1))
1968+ ar231x_add_wmac(1, AR531X_WLAN1,
1969+ AR5312_IRQ_WLAN1_INTRS);
1970+
1971+ return 0;
1972+}
1973+
1974+
1975+static void ar5312_restart(char *command)
1976+{
1977+ /* reset the system */
1978+ local_irq_disable();
1979+ while(1) {
1980+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1981+ }
1982+}
1983+
1984+
1985+/*
1986+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1987+ * to determine the predevisor value.
1988+ */
1989+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
1990+
1991+
1992+static int __init
1993+ar5312_cpu_frequency(void)
1994+{
1995+ unsigned int result;
1996+ unsigned int predivide_mask, predivide_shift;
1997+ unsigned int multiplier_mask, multiplier_shift;
1998+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
1999+ unsigned int doubler_mask;
2000+ u16 devid;
2001+
2002+ /* Trust the bootrom's idea of cpu frequency. */
2003+ if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2004+ return result;
2005+
2006+ devid = ar231x_read_reg(AR531X_REV);
2007+ devid &= AR531X_REV_MAJ;
2008+ devid >>= AR531X_REV_MAJ_S;
2009+ if (devid == AR531X_REV_MAJ_AR2313) {
2010+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2011+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2012+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2013+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2014+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2015+ } else { /* AR5312 and AR2312 */
2016+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2017+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2018+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2019+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2020+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2021+ }
2022+
2023+ /*
2024+ * Clocking is derived from a fixed 40MHz input clock.
2025+ *
2026+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2027+ * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2028+ * flash, Timer, Watchdog Timer)
2029+ *
2030+ * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2031+ *
2032+ * So, for example, with a PLL multiplier of 5, we have
2033+ *
2034+ * cpuFreq = 200MHz
2035+ * sysFreq = 50MHz
2036+ * cntFreq = 100MHz
2037+ *
2038+ * We compute the CPU frequency, based on PLL settings.
2039+ */
2040+
2041+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2042+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2043+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2044+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2045+
2046+ if (clockCtl1 & doubler_mask) {
2047+ multiplier = multiplier << 1;
2048+ }
2049+ return (40000000 / preDivisor) * multiplier;
2050+}
2051+
2052+static inline int
2053+ar5312_sys_frequency(void)
2054+{
2055+ return ar5312_cpu_frequency() / 4;
2056+}
2057+
2058+void __init
2059+ar5312_time_init(void)
2060+{
2061+ if (!is_5312())
2062+ return;
2063+
2064+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2065+}
2066+
2067+
2068+void __init
2069+ar5312_prom_init(void)
2070+{
2071+ u32 memsize, memcfg, bank0AC, bank1AC;
2072+ u32 devid;
2073+
2074+ if (!is_5312())
2075+ return;
2076+
2077+ /* Detect memory size */
2078+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2079+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2080+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2081+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2082+ + (bank1AC ? (1 << (bank1AC+1)) : 0);
2083+ memsize <<= 20;
2084+ add_memory_region(0, memsize, BOOT_MEM_RAM);
2085+
2086+ devid = ar231x_read_reg(AR531X_REV);
2087+ devid >>= AR531X_REV_WMAC_MIN_S;
2088+ devid &= AR531X_REV_CHIP;
2089+ ar231x_board.devid = (u16) devid;
2090+ ar231x_gpiodev = &ar5312_gpiodev;
2091+}
2092+
2093+void __init
2094+ar5312_plat_setup(void)
2095+{
2096+ if (!is_5312())
2097+ return;
2098+
2099+ /* Clear any lingering AHB errors */
2100+ ar231x_read_reg(AR531X_PROCADDR);
2101+ ar231x_read_reg(AR531X_DMAADDR);
2102+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2103+
2104+ _machine_restart = ar5312_restart;
2105+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2106+}
2107+
2108--- /dev/null
2109+++ b/arch/mips/ar231x/ar2315.c
2110@@ -0,0 +1,658 @@
2111+/*
2112+ * This file is subject to the terms and conditions of the GNU General Public
2113+ * License. See the file "COPYING" in the main directory of this archive
2114+ * for more details.
2115+ *
2116+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2117+ * Copyright (C) 2006 FON Technology, SL.
2118+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2119+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2120+ */
2121+
2122+/*
2123+ * Platform devices for Atheros SoCs
2124+ */
2125+
2126+#include <linux/autoconf.h>
2127+#include <linux/init.h>
2128+#include <linux/module.h>
2129+#include <linux/types.h>
2130+#include <linux/string.h>
2131+#include <linux/platform_device.h>
2132+#include <linux/kernel.h>
2133+#include <linux/reboot.h>
2134+#include <linux/delay.h>
2135+#include <linux/leds.h>
2136+#include <asm/bootinfo.h>
2137+#include <asm/reboot.h>
2138+#include <asm/time.h>
2139+#include <asm/irq.h>
2140+#include <asm/io.h>
2141+#include <asm/gpio.h>
2142+
2143+#include <ar231x_platform.h>
2144+#include <ar2315_regs.h>
2145+#include <ar231x.h>
2146+#include "devices.h"
2147+#include "ar2315.h"
2148+
2149+static u32 gpiointmask = 0, gpiointval = 0;
2150+
2151+static inline void ar2315_gpio_irq(void)
2152+{
2153+ u32 pend;
2154+ int bit = -1;
2155+
2156+ /* only do one gpio interrupt at a time */
2157+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2158+
2159+ if (pend) {
2160+ bit = fls(pend) - 1;
2161+ pend &= ~(1 << bit);
2162+ gpiointval ^= (1 << bit);
2163+ }
2164+
2165+ if (!pend)
2166+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2167+
2168+ /* Enable interrupt with edge detection */
2169+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2170+ return;
2171+
2172+ if (bit >= 0)
2173+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2174+}
2175+
2176+
2177+/*
2178+ * Called when an interrupt is received, this function
2179+ * determines exactly which interrupt it was, and it
2180+ * invokes the appropriate handler.
2181+ *
2182+ * Implicitly, we also define interrupt priority by
2183+ * choosing which to dispatch first.
2184+ */
2185+static asmlinkage void
2186+ar2315_irq_dispatch(void)
2187+{
2188+ int pending = read_c0_status() & read_c0_cause();
2189+
2190+ if (pending & CAUSEF_IP3)
2191+ do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2192+ else if (pending & CAUSEF_IP4)
2193+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
2194+ else if (pending & CAUSEF_IP2) {
2195+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2196+
2197+ if (misc_intr & AR2315_ISR_SPI)
2198+ do_IRQ(AR531X_MISC_IRQ_SPI);
2199+ else if (misc_intr & AR2315_ISR_TIMER)
2200+ do_IRQ(AR531X_MISC_IRQ_TIMER);
2201+ else if (misc_intr & AR2315_ISR_AHB)
2202+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2203+ else if (misc_intr & AR2315_ISR_GPIO)
2204+ ar2315_gpio_irq();
2205+ else if (misc_intr & AR2315_ISR_UART0)
2206+ do_IRQ(AR531X_MISC_IRQ_UART0);
2207+ else if (misc_intr & AR2315_ISR_WD)
2208+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2209+ else
2210+ do_IRQ(AR531X_MISC_IRQ_NONE);
2211+ } else if (pending & CAUSEF_IP7)
2212+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
2213+}
2214+
2215+static void ar2315_set_gpiointmask(int gpio, int level)
2216+{
2217+ u32 reg;
2218+
2219+ reg = ar231x_read_reg(AR2315_GPIO_INT);
2220+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2221+ reg |= gpio | AR2315_GPIO_INT_LVL(level);
2222+ ar231x_write_reg(AR2315_GPIO_INT, reg);
2223+}
2224+
2225+static void ar2315_gpio_intr_enable(unsigned int irq)
2226+{
2227+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2228+
2229+ /* Enable interrupt with edge detection */
2230+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2231+ return;
2232+
2233+ gpiointmask |= (1 << gpio);
2234+ ar2315_set_gpiointmask(gpio, 3);
2235+}
2236+
2237+static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
2238+{
2239+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2240+
2241+ /* reconfigure GPIO line as input */
2242+ ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2243+ ar2315_gpio_intr_enable(irq);
2244+ return 0;
2245+}
2246+
2247+static void ar2315_gpio_intr_disable(unsigned int irq)
2248+{
2249+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2250+
2251+ /* Disable interrupt */
2252+ gpiointmask &= ~(1 << gpio);
2253+ ar2315_set_gpiointmask(gpio, 0);
2254+}
2255+
2256+static void
2257+ar2315_gpio_intr_end(unsigned int irq)
2258+{
2259+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2260+ ar2315_gpio_intr_enable(irq);
2261+}
2262+
2263+static struct irq_chip ar2315_gpio_intr_controller = {
2264+ .typename = "AR2315-GPIO",
2265+ .startup = ar2315_gpio_intr_startup,
2266+ .ack = ar2315_gpio_intr_disable,
2267+ .mask_ack = ar2315_gpio_intr_disable,
2268+ .mask = ar2315_gpio_intr_disable,
2269+ .unmask = ar2315_gpio_intr_enable,
2270+ .end = ar2315_gpio_intr_end,
2271+};
2272+
2273+static void
2274+ar2315_misc_intr_enable(unsigned int irq)
2275+{
2276+ unsigned int imr;
2277+
2278+ imr = ar231x_read_reg(AR2315_IMR);
2279+ switch(irq) {
2280+ case AR531X_MISC_IRQ_SPI:
2281+ imr |= AR2315_ISR_SPI;
2282+ break;
2283+ case AR531X_MISC_IRQ_TIMER:
2284+ imr |= AR2315_ISR_TIMER;
2285+ break;
2286+ case AR531X_MISC_IRQ_AHB_PROC:
2287+ imr |= AR2315_ISR_AHB;
2288+ break;
2289+ case AR531X_MISC_IRQ_GPIO:
2290+ imr |= AR2315_ISR_GPIO;
2291+ break;
2292+ case AR531X_MISC_IRQ_UART0:
2293+ imr |= AR2315_ISR_UART0;
2294+ break;
2295+ case AR531X_MISC_IRQ_WATCHDOG:
2296+ imr |= AR2315_ISR_WD;
2297+ break;
2298+ default:
2299+ break;
2300+ }
2301+ ar231x_write_reg(AR2315_IMR, imr);
2302+}
2303+
2304+static void
2305+ar2315_misc_intr_disable(unsigned int irq)
2306+{
2307+ unsigned int imr;
2308+
2309+ imr = ar231x_read_reg(AR2315_IMR);
2310+ switch(irq) {
2311+ case AR531X_MISC_IRQ_SPI:
2312+ imr &= ~AR2315_ISR_SPI;
2313+ break;
2314+ case AR531X_MISC_IRQ_TIMER:
2315+ imr &= ~AR2315_ISR_TIMER;
2316+ break;
2317+ case AR531X_MISC_IRQ_AHB_PROC:
2318+ imr &= ~AR2315_ISR_AHB;
2319+ break;
2320+ case AR531X_MISC_IRQ_GPIO:
2321+ imr &= ~AR2315_ISR_GPIO;
2322+ break;
2323+ case AR531X_MISC_IRQ_UART0:
2324+ imr &= ~AR2315_ISR_UART0;
2325+ break;
2326+ case AR531X_MISC_IRQ_WATCHDOG:
2327+ imr &= ~AR2315_ISR_WD;
2328+ break;
2329+ default:
2330+ break;
2331+ }
2332+ ar231x_write_reg(AR2315_IMR, imr);
2333+}
2334+
2335+static void
2336+ar2315_misc_intr_end(unsigned int irq)
2337+{
2338+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2339+ ar2315_misc_intr_enable(irq);
2340+}
2341+
2342+
2343+static struct irq_chip ar2315_misc_intr_controller = {
2344+ .typename = "AR2315-MISC",
2345+ .ack = ar2315_misc_intr_disable,
2346+ .mask_ack = ar2315_misc_intr_disable,
2347+ .mask = ar2315_misc_intr_disable,
2348+ .unmask = ar2315_misc_intr_enable,
2349+ .end = ar2315_misc_intr_end,
2350+};
2351+
2352+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2353+{
2354+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2355+ ar231x_read_reg(AR2315_AHB_ERR1);
2356+
2357+ printk(KERN_ERR "AHB fatal error\n");
2358+ machine_restart("AHB error"); /* Catastrophic failure */
2359+
2360+ return IRQ_HANDLED;
2361+}
2362+
2363+static struct irqaction ar2315_ahb_proc_interrupt = {
2364+ .handler = ar2315_ahb_proc_handler,
2365+ .flags = IRQF_DISABLED,
2366+ .name = "ar2315_ahb_proc_interrupt",
2367+};
2368+
2369+static struct irqaction cascade = {
2370+ .handler = no_action,
2371+ .flags = IRQF_DISABLED,
2372+ .name = "cascade",
2373+};
2374+
2375+void
2376+ar2315_irq_init(void)
2377+{
2378+ int i;
2379+
2380+ if (!is_2315())
2381+ return;
2382+
2383+ ar231x_irq_dispatch = ar2315_irq_dispatch;
2384+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2385+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2386+ int irq = AR531X_MISC_IRQ_BASE + i;
2387+ set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller,
2388+ handle_level_irq);
2389+ }
2390+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2391+ int irq = AR531X_GPIO_IRQ_BASE + i;
2392+ set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2393+ handle_level_irq);
2394+ }
2395+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2396+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2397+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2398+}
2399+
2400+const struct ar231x_gpiodev ar2315_gpiodev;
2401+
2402+static u32
2403+ar2315_gpio_get_output(void)
2404+{
2405+ u32 reg;
2406+ reg = ar231x_read_reg(AR2315_GPIO_CR);
2407+ reg &= ar2315_gpiodev.valid_mask;
2408+ return reg;
2409+}
2410+
2411+static u32
2412+ar2315_gpio_set_output(u32 mask, u32 val)
2413+{
2414+ u32 reg;
2415+
2416+ reg = ar231x_read_reg(AR2315_GPIO_CR);
2417+ reg &= ~mask;
2418+ reg |= val;
2419+ ar231x_write_reg(AR2315_GPIO_CR, reg);
2420+ return reg;
2421+}
2422+
2423+static u32
2424+ar2315_gpio_get(void)
2425+{
2426+ u32 reg;
2427+ reg = ar231x_read_reg(AR2315_GPIO_DI);
2428+ reg &= ar2315_gpiodev.valid_mask;
2429+ return reg;
2430+}
2431+
2432+static u32
2433+ar2315_gpio_set(u32 mask, u32 value)
2434+{
2435+ u32 reg;
2436+ reg = ar231x_read_reg(AR2315_GPIO_DO);
2437+ reg &= ~mask;
2438+ reg |= value;
2439+ ar231x_write_reg(AR2315_GPIO_DO, reg);
2440+ return reg;
2441+}
2442+
2443+const struct ar231x_gpiodev ar2315_gpiodev = {
2444+ .valid_mask = (1 << 22) - 1,
2445+ .get_output = ar2315_gpio_get_output,
2446+ .set_output = ar2315_gpio_set_output,
2447+ .get = ar2315_gpio_get,
2448+ .set = ar2315_gpio_set,
2449+};
2450+
2451+static struct ar231x_eth ar2315_eth_data = {
2452+ .reset_base = AR2315_RESET,
2453+ .reset_mac = AR2315_RESET_ENET0,
2454+ .reset_phy = AR2315_RESET_EPHY0,
2455+ .phy_base = AR2315_ENET0,
2456+ .config = &ar231x_board,
2457+};
2458+
2459+static struct resource ar2315_spiflash_res[] = {
2460+ {
2461+ .name = "flash_base",
2462+ .flags = IORESOURCE_MEM,
2463+ .start = KSEG1ADDR(AR2315_SPI_READ),
2464+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2465+ },
2466+ {
2467+ .name = "flash_regs",
2468+ .flags = IORESOURCE_MEM,
2469+ .start = 0x11300000,
2470+ .end = 0x11300012,
2471+ },
2472+};
2473+
2474+static struct platform_device ar2315_spiflash = {
2475+ .id = 0,
2476+ .name = "spiflash",
2477+ .resource = ar2315_spiflash_res,
2478+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2479+};
2480+
2481+static struct platform_device ar2315_wdt = {
2482+ .id = 0,
2483+ .name = "ar2315_wdt",
2484+};
2485+
2486+#define SPI_FLASH_CTL 0x00
2487+#define SPI_FLASH_OPCODE 0x04
2488+#define SPI_FLASH_DATA 0x08
2489+
2490+static inline u32
2491+spiflash_read_reg(int reg)
2492+{
2493+ return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg);
2494+}
2495+
2496+static inline void
2497+spiflash_write_reg(int reg, u32 data)
2498+{
2499+ ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data);
2500+}
2501+
2502+static u32
2503+spiflash_wait_status(void)
2504+{
2505+ u32 reg;
2506+
2507+ do {
2508+ reg = spiflash_read_reg(SPI_FLASH_CTL);
2509+ } while (reg & SPI_CTL_BUSY);
2510+
2511+ return reg;
2512+}
2513+
2514+static u8
2515+spiflash_probe(void)
2516+{
2517+ u32 reg;
2518+
2519+ reg = spiflash_wait_status();
2520+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2521+ reg |= (1 << 4) | 4 | SPI_CTL_START;
2522+
2523+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2524+ spiflash_write_reg(SPI_FLASH_CTL, reg);
2525+
2526+ reg = spiflash_wait_status();
2527+ reg = spiflash_read_reg(SPI_FLASH_DATA);
2528+ reg &= 0xff;
2529+
2530+ return (u8) reg;
2531+}
2532+
2533+
2534+#define STM_8MBIT_SIGNATURE 0x13
2535+#define STM_16MBIT_SIGNATURE 0x14
2536+#define STM_32MBIT_SIGNATURE 0x15
2537+#define STM_64MBIT_SIGNATURE 0x16
2538+#define STM_128MBIT_SIGNATURE 0x17
2539+
2540+static u8 __init *
2541+ar2315_flash_limit(void)
2542+{
2543+ u32 flash_size = 0;
2544+
2545+ /* probe the flash chip size */
2546+ switch(spiflash_probe()) {
2547+ case STM_8MBIT_SIGNATURE:
2548+ flash_size = 0x00100000;
2549+ break;
2550+ case STM_16MBIT_SIGNATURE:
2551+ flash_size = 0x00200000;
2552+ break;
2553+ case STM_32MBIT_SIGNATURE:
2554+ flash_size = 0x00400000;
2555+ break;
2556+ case STM_64MBIT_SIGNATURE:
2557+ flash_size = 0x00800000;
2558+ break;
2559+ case STM_128MBIT_SIGNATURE:
2560+ flash_size = 0x01000000;
2561+ break;
2562+ }
2563+
2564+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2565+ flash_size - 1;
2566+ return (u8 *) ar2315_spiflash_res[0].end + 1;
2567+}
2568+
2569+#ifdef CONFIG_LEDS_GPIO
2570+static struct gpio_led ar2315_leds[6];
2571+static struct gpio_led_platform_data ar2315_led_data = {
2572+ .leds = (void *) ar2315_leds,
2573+};
2574+
2575+static struct platform_device ar2315_gpio_leds = {
2576+ .name = "leds-gpio",
2577+ .id = -1,
2578+ .dev = {
2579+ .platform_data = (void *) &ar2315_led_data,
2580+ }
2581+};
2582+
2583+static void __init
2584+ar2315_init_gpio(void)
2585+{
2586+ static char led_names[6][6];
2587+ int i, led = 0;
2588+
2589+ ar2315_led_data.num_leds = 0;
2590+ for(i = 1; i < 8; i++)
2591+ {
2592+ if((i == AR2315_RESET_GPIO) ||
2593+ (i == ar231x_board.config->resetConfigGpio))
2594+ continue;
2595+
2596+ if(i == ar231x_board.config->sysLedGpio)
2597+ strcpy(led_names[led], "wlan");
2598+ else
2599+ sprintf(led_names[led], "gpio%d", i);
2600+
2601+ ar2315_leds[led].name = led_names[led];
2602+ ar2315_leds[led].gpio = i;
2603+ ar2315_leds[led].active_low = 0;
2604+ led++;
2605+ }
2606+ ar2315_led_data.num_leds = led;
2607+ platform_device_register(&ar2315_gpio_leds);
2608+}
2609+#else
2610+static inline void ar2315_init_gpio(void)
2611+{
2612+}
2613+#endif
2614+
2615+int __init
2616+ar2315_init_devices(void)
2617+{
2618+ if (!is_2315())
2619+ return 0;
2620+
2621+ /* Find board configuration */
2622+ ar231x_find_config(ar2315_flash_limit());
2623+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2624+
2625+ ar2315_init_gpio();
2626+ platform_device_register(&ar2315_wdt);
2627+ platform_device_register(&ar2315_spiflash);
2628+ ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS,
2629+ &ar2315_eth_data);
2630+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2631+
2632+ return 0;
2633+}
2634+
2635+static void
2636+ar2315_restart(char *command)
2637+{
2638+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2639+
2640+ local_irq_disable();
2641+
2642+ /* try reset the system via reset control */
2643+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2644+
2645+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2646+ * give it some time to attempt a gpio based hardware reset
2647+ * (atheros reference design workaround) */
2648+ gpio_direction_output(AR2315_RESET_GPIO, 0);
2649+ mdelay(100);
2650+
2651+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2652+ * workaround. Attempt to jump to the mips reset location -
2653+ * the boot loader itself might be able to recover the system */
2654+ mips_reset_vec();
2655+}
2656+
2657+
2658+/*
2659+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2660+ * to determine the predevisor value.
2661+ */
2662+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2663+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2664+
2665+static unsigned int __init
2666+ar2315_sys_clk(unsigned int clockCtl)
2667+{
2668+ unsigned int pllcCtrl,cpuDiv;
2669+ unsigned int pllcOut,refdiv,fdiv,divby2;
2670+ unsigned int clkDiv;
2671+
2672+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2673+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2674+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2675+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2676+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2677+ divby2 += 1;
2678+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2679+
2680+
2681+ /* clkm input selected */
2682+ switch(clockCtl & CPUCLK_CLK_SEL_M) {
2683+ case 0:
2684+ case 1:
2685+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2686+ break;
2687+ case 2:
2688+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2689+ break;
2690+ default:
2691+ pllcOut = 40000000;
2692+ clkDiv = 1;
2693+ break;
2694+ }
2695+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2696+ cpuDiv = cpuDiv * 2 ?: 1;
2697+ return (pllcOut/(clkDiv * cpuDiv));
2698+}
2699+
2700+static inline unsigned int
2701+ar2315_cpu_frequency(void)
2702+{
2703+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2704+}
2705+
2706+static inline unsigned int
2707+ar2315_apb_frequency(void)
2708+{
2709+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2710+}
2711+
2712+void __init
2713+ar2315_time_init(void)
2714+{
2715+ if (!is_2315())
2716+ return;
2717+
2718+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2719+}
2720+
2721+void __init
2722+ar2315_prom_init(void)
2723+{
2724+ u32 memsize, memcfg, devid;
2725+
2726+ if (!is_2315())
2727+ return;
2728+
2729+ memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2730+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2731+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2732+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2733+ memsize <<= 3;
2734+ add_memory_region(0, memsize, BOOT_MEM_RAM);
2735+
2736+ /* Detect the hardware based on the device ID */
2737+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2738+ switch(devid) {
2739+ case 0x90:
2740+ case 0x91:
2741+ ar231x_devtype = DEV_TYPE_AR2317;
2742+ break;
2743+ default:
2744+ ar231x_devtype = DEV_TYPE_AR2315;
2745+ break;
2746+ }
2747+ ar231x_gpiodev = &ar2315_gpiodev;
2748+ ar231x_board.devid = devid;
2749+}
2750+
2751+void __init
2752+ar2315_plat_setup(void)
2753+{
2754+ u32 config;
2755+
2756+ if (!is_2315())
2757+ return;
2758+
2759+ /* Clear any lingering AHB errors */
2760+ config = read_c0_config();
2761+ write_c0_config(config & ~0x3);
2762+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2763+ ar231x_read_reg(AR2315_AHB_ERR1);
2764+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2765+
2766+ _machine_restart = ar2315_restart;
2767+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2768+}
2769--- /dev/null
2770+++ b/arch/mips/ar231x/ar2315.h
2771@@ -0,0 +1,37 @@
2772+#ifndef __AR2315_H
2773+#define __AR2315_H
2774+
2775+#ifdef CONFIG_ATHEROS_AR2315
2776+
2777+extern void ar2315_irq_init(void);
2778+extern int ar2315_init_devices(void);
2779+extern void ar2315_prom_init(void);
2780+extern void ar2315_plat_setup(void);
2781+extern void ar2315_time_init(void);
2782+
2783+#else
2784+
2785+static inline void ar2315_irq_init(void)
2786+{
2787+}
2788+
2789+static inline int ar2315_init_devices(void)
2790+{
2791+ return 0;
2792+}
2793+
2794+static inline void ar2315_prom_init(void)
2795+{
2796+}
2797+
2798+static inline void ar2315_plat_setup(void)
2799+{
2800+}
2801+
2802+static inline void ar2315_time_init(void)
2803+{
2804+}
2805+
2806+#endif
2807+
2808+#endif
2809--- /dev/null
2810+++ b/arch/mips/ar231x/ar5312.h
2811@@ -0,0 +1,38 @@
2812+#ifndef __AR5312_H
2813+#define __AR5312_H
2814+
2815+#ifdef CONFIG_ATHEROS_AR5312
2816+
2817+extern void ar5312_irq_init(void);
2818+extern int ar5312_init_devices(void);
2819+extern void ar5312_prom_init(void);
2820+extern void ar5312_plat_setup(void);
2821+extern void ar5312_time_init(void);
2822+extern void ar5312_time_init(void);
2823+
2824+#else
2825+
2826+static inline void ar5312_irq_init(void)
2827+{
2828+}
2829+
2830+static inline int ar5312_init_devices(void)
2831+{
2832+ return 0;
2833+}
2834+
2835+static inline void ar5312_prom_init(void)
2836+{
2837+}
2838+
2839+static inline void ar5312_plat_setup(void)
2840+{
2841+}
2842+
2843+static inline void ar5312_time_init(void)
2844+{
2845+}
2846+
2847+#endif
2848+
2849+#endif
2850--- /dev/null
2851+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2852@@ -0,0 +1,54 @@
2853+#ifndef __AR531X_H
2854+#define __AR531X_H
2855+
2856+#define AR531X_MISC_IRQ_BASE 0x20
2857+#define AR531X_GPIO_IRQ_BASE 0x30
2858+
2859+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2860+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2861+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2862+
2863+/* Miscellaneous interrupts, which share IP6 */
2864+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2865+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2866+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2867+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2868+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2869+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2870+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2871+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2872+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2873+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2874+#define AR531X_MISC_IRQ_COUNT 10
2875+
2876+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2877+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2878+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2879+#define AR531X_GPIO_IRQ_COUNT 22
2880+
2881+static inline u32
2882+ar231x_read_reg(u32 reg)
2883+{
2884+ return __raw_readl((u32 *) KSEG1ADDR(reg));
2885+}
2886+
2887+static inline void
2888+ar231x_write_reg(u32 reg, u32 val)
2889+{
2890+ __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2891+}
2892+
2893+static inline u32
2894+ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2895+{
2896+ u32 ret;
2897+
2898+ ret = ar231x_read_reg(reg);
2899+ ret &= ~mask;
2900+ ret |= val;
2901+ ar231x_write_reg(reg, ret);
2902+
2903+ return ret;
2904+}
2905+
2906+#endif
2907--- /dev/null
2908+++ b/arch/mips/ar231x/devices.h
2909@@ -0,0 +1,37 @@
2910+#ifndef __AR231X_DEVICES_H
2911+#define __AR231X_DEVICES_H
2912+
2913+enum {
2914+ /* handled by ar5312.c */
2915+ DEV_TYPE_AR2312,
2916+ DEV_TYPE_AR2313,
2917+ DEV_TYPE_AR5312,
2918+
2919+ /* handled by ar2315.c */
2920+ DEV_TYPE_AR2315,
2921+ DEV_TYPE_AR2316,
2922+ DEV_TYPE_AR2317,
2923+
2924+ DEV_TYPE_UNKNOWN
2925+};
2926+
2927+extern int ar231x_devtype;
2928+extern struct ar231x_board_config ar231x_board;
2929+extern asmlinkage void (*ar231x_irq_dispatch)(void);
2930+
2931+extern int ar231x_find_config(u8 *flash_limit);
2932+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2933+extern int ar231x_add_wmac(int nr, u32 base, int irq);
2934+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2935+
2936+static inline bool is_2315(void)
2937+{
2938+ return (current_cpu_data.cputype == CPU_4KEC);
2939+}
2940+
2941+static inline bool is_5312(void)
2942+{
2943+ return !is_2315();
2944+}
2945+
2946+#endif
2947--- /dev/null
2948+++ b/arch/mips/ar231x/devices.c
2949@@ -0,0 +1,175 @@
2950+#include <linux/kernel.h>
2951+#include <linux/init.h>
2952+#include <linux/serial.h>
2953+#include <linux/serial_core.h>
2954+#include <linux/serial_8250.h>
2955+#include <linux/platform_device.h>
2956+#include <ar231x_platform.h>
2957+#include <ar231x.h>
2958+#include "devices.h"
2959+#include "ar5312.h"
2960+#include "ar2315.h"
2961+
2962+struct ar231x_board_config ar231x_board;
2963+int ar231x_devtype = DEV_TYPE_UNKNOWN;
2964+const struct ar231x_gpiodev *ar231x_gpiodev;
2965+EXPORT_SYMBOL(ar231x_gpiodev);
2966+
2967+static struct resource ar231x_eth0_res[] = {
2968+ {
2969+ .name = "eth0_membase",
2970+ .flags = IORESOURCE_MEM,
2971+ },
2972+ {
2973+ .name = "eth0_irq",
2974+ .flags = IORESOURCE_IRQ,
2975+ }
2976+};
2977+
2978+static struct resource ar231x_eth1_res[] = {
2979+ {
2980+ .name = "eth1_membase",
2981+ .flags = IORESOURCE_MEM,
2982+ },
2983+ {
2984+ .name = "eth1_irq",
2985+ .flags = IORESOURCE_IRQ,
2986+ }
2987+};
2988+
2989+static struct platform_device ar231x_eth[] = {
2990+ {
2991+ .id = 0,
2992+ .name = "ar231x-eth",
2993+ .resource = ar231x_eth0_res,
2994+ .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2995+ },
2996+ {
2997+ .id = 1,
2998+ .name = "ar231x-eth",
2999+ .resource = ar231x_eth1_res,
3000+ .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3001+ }
3002+};
3003+
3004+static struct resource ar231x_wmac0_res[] = {
3005+ {
3006+ .name = "wmac0_membase",
3007+ .flags = IORESOURCE_MEM,
3008+ },
3009+ {
3010+ .name = "wmac0_irq",
3011+ .flags = IORESOURCE_IRQ,
3012+ }
3013+};
3014+
3015+static struct resource ar231x_wmac1_res[] = {
3016+ {
3017+ .name = "wmac1_membase",
3018+ .flags = IORESOURCE_MEM,
3019+ },
3020+ {
3021+ .name = "wmac1_irq",
3022+ .flags = IORESOURCE_IRQ,
3023+ }
3024+};
3025+
3026+
3027+static struct platform_device ar231x_wmac[] = {
3028+ {
3029+ .id = 0,
3030+ .name = "ar231x-wmac",
3031+ .resource = ar231x_wmac0_res,
3032+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3033+ .dev.platform_data = &ar231x_board,
3034+ },
3035+ {
3036+ .id = 1,
3037+ .name = "ar231x-wmac",
3038+ .resource = ar231x_wmac1_res,
3039+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3040+ .dev.platform_data = &ar231x_board,
3041+ },
3042+};
3043+
3044+static const char *devtype_strings[] = {
3045+ [DEV_TYPE_AR5312] = "Atheros AR5312",
3046+ [DEV_TYPE_AR2312] = "Atheros AR2312",
3047+ [DEV_TYPE_AR2313] = "Atheros AR2313",
3048+ [DEV_TYPE_AR2315] = "Atheros AR2315",
3049+ [DEV_TYPE_AR2316] = "Atheros AR2316",
3050+ [DEV_TYPE_AR2317] = "Atheros AR2317",
3051+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3052+};
3053+
3054+const char *get_system_type(void)
3055+{
3056+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3057+ !devtype_strings[ar231x_devtype])
3058+ return devtype_strings[DEV_TYPE_UNKNOWN];
3059+ return devtype_strings[ar231x_devtype];
3060+}
3061+
3062+
3063+int __init
3064+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3065+{
3066+ struct resource *res;
3067+
3068+ ar231x_eth[nr].dev.platform_data = pdata;
3069+ res = &ar231x_eth[nr].resource[0];
3070+ res->start = base;
3071+ res->end = base + 0x2000 - 1;
3072+ res++;
3073+ res->start = irq;
3074+ res->end = irq;
3075+ return platform_device_register(&ar231x_eth[nr]);
3076+}
3077+
3078+void __init
3079+ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3080+{
3081+ struct uart_port s;
3082+
3083+ memset(&s, 0, sizeof(s));
3084+
3085+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3086+ s.iotype = UPIO_MEM;
3087+ s.irq = AR531X_MISC_IRQ_UART0;
3088+ s.regshift = 2;
3089+ s.mapbase = mapbase;
3090+ s.uartclk = uartclk;
3091+ s.membase = (void __iomem *)s.mapbase;
3092+
3093+ early_serial_setup(&s);
3094+}
3095+
3096+int __init
3097+ar231x_add_wmac(int nr, u32 base, int irq)
3098+{
3099+ struct resource *res;
3100+
3101+ ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3102+ res = &ar231x_wmac[nr].resource[0];
3103+ res->start = base;
3104+ res->end = base + 0x10000 - 1;
3105+ res++;
3106+ res->start = irq;
3107+ res->end = irq;
3108+ return platform_device_register(&ar231x_wmac[nr]);
3109+}
3110+
3111+static int __init ar231x_register_devices(void)
3112+{
3113+ static struct resource res = {
3114+ .start = 0xFFFFFFFF,
3115+ };
3116+
3117+ platform_device_register_simple("GPIODEV", 0, &res, 1);
3118+ ar5312_init_devices();
3119+ ar2315_init_devices();
3120+
3121+ return 0;
3122+}
3123+
3124+device_initcall(ar231x_register_devices);
3125

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