Root/target/linux/atheros/patches-2.6.32/100-board.patch

1--- a/arch/mips/Kconfig
2+++ b/arch/mips/Kconfig
3@@ -96,6 +96,19 @@ config BCM63XX
4     help
5      Support for BCM63XX based boards
6 
7+config ATHEROS_AR231X
8+ bool "Atheros 231x/531x SoC support"
9+ select CEVT_R4K
10+ select CSRC_R4K
11+ select DMA_NONCOHERENT
12+ select IRQ_CPU
13+ select SYS_HAS_CPU_MIPS32_R1
14+ select SYS_SUPPORTS_BIG_ENDIAN
15+ select SYS_SUPPORTS_32BIT_KERNEL
16+ select GENERIC_GPIO
17+ help
18+ Support for AR231x and AR531x based boards
19+
20 config MIPS_COBALT
21     bool "Cobalt Server"
22     select CEVT_R4K
23@@ -673,6 +686,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
24 
25 endchoice
26 
27+source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/basler/excite/Kconfig"
30 source "arch/mips/bcm63xx/Kconfig"
31--- a/arch/mips/Makefile
32+++ b/arch/mips/Makefile
33@@ -298,6 +298,13 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctr
34 
35 
36 #
37+# Atheros AR5312/AR2312 WiSoC
38+#
39+core-$(CONFIG_ATHEROS_AR231X) += arch/mips/ar231x/
40+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
41+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
42+
43+#
44 # Cobalt Server
45 #
46 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
47--- /dev/null
48+++ b/arch/mips/ar231x/Kconfig
49@@ -0,0 +1,17 @@
50+config ATHEROS_AR5312
51+ bool "Atheros 5312/2312+ support"
52+ depends on ATHEROS_AR231X
53+ default y
54+
55+config ATHEROS_AR2315
56+ bool "Atheros 2315+ support"
57+ depends on ATHEROS_AR231X
58+ select DMA_NONCOHERENT
59+ select CEVT_R4K
60+ select CSRC_R4K
61+ select IRQ_CPU
62+ select SYS_HAS_CPU_MIPS32_R1
63+ select SYS_SUPPORTS_32BIT_KERNEL
64+ select SYS_SUPPORTS_BIG_ENDIAN
65+ select GENERIC_GPIO
66+ default y
67--- /dev/null
68+++ b/arch/mips/ar231x/Makefile
69@@ -0,0 +1,13 @@
70+#
71+# This file is subject to the terms and conditions of the GNU General Public
72+# License. See the file "COPYING" in the main directory of this archive
73+# for more details.
74+#
75+# Copyright (C) 2006 FON Technology, SL.
76+# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
77+# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
78+#
79+
80+obj-y += board.o prom.o devices.o
81+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
82+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
83--- /dev/null
84+++ b/arch/mips/ar231x/board.c
85@@ -0,0 +1,251 @@
86+/*
87+ * This file is subject to the terms and conditions of the GNU General Public
88+ * License. See the file "COPYING" in the main directory of this archive
89+ * for more details.
90+ *
91+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
92+ * Copyright (C) 2006 FON Technology, SL.
93+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
94+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
95+ */
96+
97+#include <linux/autoconf.h>
98+#include <linux/init.h>
99+#include <linux/module.h>
100+#include <linux/types.h>
101+#include <linux/string.h>
102+#include <linux/platform_device.h>
103+#include <linux/kernel.h>
104+#include <linux/random.h>
105+#include <linux/etherdevice.h>
106+#include <asm/irq_cpu.h>
107+#include <asm/reboot.h>
108+#include <asm/io.h>
109+
110+#include <ar231x_platform.h>
111+#include "devices.h"
112+#include "ar5312.h"
113+#include "ar2315.h"
114+
115+void (*ar231x_irq_dispatch)(void);
116+
117+static inline bool
118+check_radio_magic(u8 *addr)
119+{
120+ addr += 0x7a; /* offset for flash magic */
121+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
122+ return 1;
123+ }
124+ return 0;
125+}
126+
127+static inline bool
128+check_board_data(u8 *flash_limit, u8 *addr, bool broken)
129+{
130+ /* config magic found */
131+ if (*((u32 *)addr) == AR531X_BD_MAGIC)
132+ return 1;
133+
134+ if (!broken)
135+ return 0;
136+
137+ if (check_radio_magic(addr + 0xf8))
138+ ar231x_board.radio = addr + 0xf8;
139+ if ((addr < flash_limit + 0x10000) &&
140+ check_radio_magic(addr + 0x10000))
141+ ar231x_board.radio = addr + 0x10000;
142+
143+ if (ar231x_board.radio) {
144+ /* broken board data detected, use radio data to find the offset,
145+ * user will fix this */
146+ return 1;
147+ }
148+ return 0;
149+}
150+
151+static u8 *
152+find_board_config(u8 *flash_limit, bool broken)
153+{
154+ u8 *addr;
155+ int found = 0;
156+
157+ for (addr = flash_limit - 0x1000;
158+ addr >= flash_limit - 0x30000;
159+ addr -= 0x1000) {
160+
161+ if (check_board_data(flash_limit, addr, broken)) {
162+ found = 1;
163+ break;
164+ }
165+ }
166+
167+ if (!found)
168+ addr = NULL;
169+
170+ return addr;
171+}
172+
173+static u8 *
174+find_radio_config(u8 *flash_limit, u8 *board_config)
175+{
176+ int found;
177+ u8 *radio_config;
178+
179+ /*
180+ * Now find the start of Radio Configuration data, using heuristics:
181+ * Search forward from Board Configuration data by 0x1000 bytes
182+ * at a time until we find non-0xffffffff.
183+ */
184+ found = 0;
185+ for (radio_config = board_config + 0x1000;
186+ (radio_config < flash_limit);
187+ radio_config += 0x1000) {
188+ if ((*(u32 *)radio_config != 0xffffffff) &&
189+ check_radio_magic(radio_config)) {
190+ found = 1;
191+ break;
192+ }
193+ }
194+
195+ /* AR2316 relocates radio config to new location */
196+ if (!found) {
197+ for (radio_config = board_config + 0xf8;
198+ (radio_config < flash_limit - 0x1000 + 0xf8);
199+ radio_config += 0x1000) {
200+ if ((*(u32 *)radio_config != 0xffffffff) &&
201+ check_radio_magic(radio_config)) {
202+ found = 1;
203+ break;
204+ }
205+ }
206+ }
207+
208+ if (!found) {
209+ printk("Could not find Radio Configuration data\n");
210+ radio_config = 0;
211+ }
212+
213+ return (u8 *) radio_config;
214+}
215+
216+int __init
217+ar231x_find_config(u8 *flash_limit)
218+{
219+ struct ar231x_boarddata *config;
220+ unsigned int rcfg_size;
221+ int broken_boarddata = 0;
222+ u8 *bcfg, *rcfg;
223+ u8 *board_data;
224+ u8 *radio_data;
225+ u32 offset;
226+
227+ ar231x_board.config = NULL;
228+ ar231x_board.radio = NULL;
229+ /* Copy the board and radio data to RAM, because accessing the mapped
230+ * memory of the flash directly after booting is not safe */
231+
232+ /* Try to find valid board and radio data */
233+ bcfg = find_board_config(flash_limit, false);
234+
235+ /* If that fails, try to at least find valid radio data */
236+ if (!bcfg) {
237+ bcfg = find_board_config(flash_limit, true);
238+ broken_boarddata = 1;
239+ }
240+
241+ if (!bcfg) {
242+ printk(KERN_WARNING "WARNING: No board configuration data found!\n");
243+ return -ENODEV;
244+ }
245+
246+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
247+ ar231x_board.config = (struct ar231x_boarddata *) board_data;
248+ memcpy(board_data, bcfg, 0x100);
249+ if (broken_boarddata) {
250+ printk(KERN_WARNING "WARNING: broken board data detected\n");
251+ config = ar231x_board.config;
252+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
253+ printk(KERN_INFO "Fixing up empty mac addresses\n");
254+ config->resetConfigGpio = 0xffff;
255+ config->sysLedGpio = 0xffff;
256+ random_ether_addr(config->wlan0_mac);
257+ config->wlan0_mac[0] &= ~0x06;
258+ random_ether_addr(config->enet0_mac);
259+ random_ether_addr(config->enet1_mac);
260+ }
261+ }
262+
263+
264+ /* Radio config starts 0x100 bytes after board config, regardless
265+ * of what the physical layout on the flash chip looks like */
266+
267+ if (ar231x_board.radio)
268+ rcfg = (u8 *) ar231x_board.radio;
269+ else
270+ rcfg = find_radio_config(flash_limit, bcfg);
271+
272+ if (!rcfg)
273+ return -ENODEV;
274+
275+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
276+ ar231x_board.radio = radio_data;
277+ offset = radio_data - board_data;
278+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
279+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
280+ memcpy(radio_data, rcfg, rcfg_size);
281+
282+ return 0;
283+}
284+
285+static void
286+ar231x_halt(void)
287+{
288+ local_irq_disable();
289+ while (1);
290+}
291+
292+void __init
293+plat_mem_setup(void)
294+{
295+ _machine_halt = ar231x_halt;
296+ pm_power_off = ar231x_halt;
297+
298+ ar5312_plat_setup();
299+ ar2315_plat_setup();
300+
301+ /* Disable data watchpoints */
302+ write_c0_watchlo0(0);
303+}
304+
305+
306+asmlinkage void
307+plat_irq_dispatch(void)
308+{
309+ ar231x_irq_dispatch();
310+}
311+
312+void __init
313+plat_time_init(void)
314+{
315+ ar5312_time_init();
316+ ar2315_time_init();
317+}
318+
319+unsigned int __cpuinit
320+get_c0_compare_int(void)
321+{
322+ return CP0_LEGACY_COMPARE_IRQ;
323+}
324+
325+void __init
326+arch_init_irq(void)
327+{
328+ clear_c0_status(ST0_IM);
329+ mips_cpu_irq_init();
330+
331+ /* Initialize interrupt controllers */
332+ ar5312_irq_init();
333+ ar2315_irq_init();
334+}
335+
336+
337--- /dev/null
338+++ b/arch/mips/ar231x/prom.c
339@@ -0,0 +1,37 @@
340+/*
341+ * This file is subject to the terms and conditions of the GNU General Public
342+ * License. See the file "COPYING" in the main directory of this archive
343+ * for more details.
344+ *
345+ * Copyright MontaVista Software Inc
346+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
347+ * Copyright (C) 2006 FON Technology, SL.
348+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
349+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
350+ */
351+
352+/*
353+ * Prom setup file for ar531x
354+ */
355+
356+#include <linux/init.h>
357+#include <linux/autoconf.h>
358+#include <linux/kernel.h>
359+#include <linux/string.h>
360+#include <linux/mm.h>
361+#include <linux/bootmem.h>
362+
363+#include <asm/bootinfo.h>
364+#include <asm/addrspace.h>
365+#include "ar5312.h"
366+#include "ar2315.h"
367+
368+void __init prom_init(void)
369+{
370+ ar5312_prom_init();
371+ ar2315_prom_init();
372+}
373+
374+void __init prom_free_prom_memory(void)
375+{
376+}
377--- /dev/null
378+++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
379@@ -0,0 +1,83 @@
380+#ifndef __AR531X_PLATFORM_H
381+#define __AR531X_PLATFORM_H
382+
383+/*
384+ * This is board-specific data that is stored in a "fixed" location in flash.
385+ * It is shared across operating systems, so it should not be changed lightly.
386+ * The main reason we need it is in order to extract the ethernet MAC
387+ * address(es).
388+ */
389+struct ar231x_boarddata {
390+ u32 magic; /* board data is valid */
391+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
392+ u16 cksum; /* checksum (starting with BD_REV 2) */
393+ u16 rev; /* revision of this struct */
394+#define BD_REV 4
395+ char boardName[64]; /* Name of board */
396+ u16 major; /* Board major number */
397+ u16 minor; /* Board minor number */
398+ u32 flags; /* Board configuration */
399+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
400+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
401+#define BD_UART1 0x00000004 /* UART1 is stuffed */
402+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
403+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
404+#define BD_SYSLED 0x00000020 /* System LED stuffed */
405+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
406+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
407+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
408+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
409+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
410+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
411+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
412+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
413+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
414+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
415+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
416+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
417+ u16 resetConfigGpio; /* Reset factory GPIO pin */
418+ u16 sysLedGpio; /* System LED GPIO pin */
419+
420+ u32 cpuFreq; /* CPU core frequency in Hz */
421+ u32 sysFreq; /* System frequency in Hz */
422+ u32 cntFreq; /* Calculated C0_COUNT frequency */
423+
424+ u8 wlan0_mac[6];
425+ u8 enet0_mac[6];
426+ u8 enet1_mac[6];
427+
428+ u16 pciId; /* Pseudo PCIID for common code */
429+ u16 memCap; /* cap bank1 in MB */
430+
431+ /* version 3 */
432+ u8 wlan1_mac[6]; /* (ar5212) */
433+};
434+
435+#define BOARD_CONFIG_BUFSZ 0x1000
436+
437+/*
438+ * Platform device information for the Wireless MAC
439+ */
440+struct ar231x_board_config {
441+ u16 devid;
442+
443+ /* board config data */
444+ struct ar231x_boarddata *config;
445+
446+ /* radio calibration data */
447+ const char *radio;
448+};
449+
450+/*
451+ * Platform device information for the Ethernet MAC
452+ */
453+struct ar231x_eth {
454+ u32 reset_base;
455+ u32 reset_mac;
456+ u32 reset_phy;
457+ u32 phy_base;
458+ struct ar231x_board_config *config;
459+ char *macaddr;
460+};
461+
462+#endif /* __AR531X_PLATFORM_H */
463--- /dev/null
464+++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
465@@ -0,0 +1,84 @@
466+/*
467+ * Atheros SoC specific CPU feature overrides
468+ *
469+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
470+ *
471+ * This file was derived from: include/asm-mips/cpu-features.h
472+ * Copyright (C) 2003, 2004 Ralf Baechle
473+ * Copyright (C) 2004 Maciej W. Rozycki
474+ *
475+ * This program is free software; you can redistribute it and/or modify it
476+ * under the terms of the GNU General Public License version 2 as published
477+ * by the Free Software Foundation.
478+ *
479+ */
480+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
481+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
482+
483+/*
484+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
485+ */
486+#define cpu_has_tlb 1
487+#define cpu_has_4kex 1
488+#define cpu_has_3k_cache 0
489+#define cpu_has_4k_cache 1
490+#define cpu_has_tx39_cache 0
491+#define cpu_has_sb1_cache 0
492+#define cpu_has_fpu 0
493+#define cpu_has_32fpr 0
494+#define cpu_has_counter 1
495+/* #define cpu_has_watch ? */
496+/* #define cpu_has_divec ? */
497+/* #define cpu_has_vce ? */
498+/* #define cpu_has_cache_cdex_p ? */
499+/* #define cpu_has_cache_cdex_s ? */
500+/* #define cpu_has_prefetch ? */
501+/* #define cpu_has_mcheck ? */
502+#define cpu_has_ejtag 1
503+
504+#if !defined(CONFIG_ATHEROS_AR5312)
505+# define cpu_has_llsc 1
506+#else
507+/*
508+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
509+ * ll/sc instructions.
510+ */
511+# define cpu_has_llsc 0
512+#endif
513+
514+#define cpu_has_mips16 0
515+#define cpu_has_mdmx 0
516+#define cpu_has_mips3d 0
517+#define cpu_has_smartmips 0
518+
519+/* #define cpu_has_vtag_icache ? */
520+/* #define cpu_has_dc_aliases ? */
521+/* #define cpu_has_ic_fills_f_dc ? */
522+/* #define cpu_has_pindexed_dcache ? */
523+
524+/* #define cpu_icache_snoops_remote_store ? */
525+
526+#define cpu_has_mips32r1 1
527+
528+#if !defined(CONFIG_ATHEROS_AR5312)
529+# define cpu_has_mips32r2 1
530+#endif
531+
532+#define cpu_has_mips64r1 0
533+#define cpu_has_mips64r2 0
534+
535+#define cpu_has_dsp 0
536+#define cpu_has_mipsmt 0
537+
538+/* #define cpu_has_nofpuex ? */
539+#define cpu_has_64bits 0
540+#define cpu_has_64bit_zero_reg 0
541+#define cpu_has_64bit_gp_regs 0
542+#define cpu_has_64bit_addresses 0
543+
544+/* #define cpu_has_inclusive_pcaches ? */
545+
546+/* #define cpu_dcache_line_size() ? */
547+/* #define cpu_icache_line_size() ? */
548+
549+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
550--- /dev/null
551+++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
552@@ -0,0 +1,64 @@
553+/*
554+ * This file is subject to the terms and conditions of the GNU General Public
555+ * License. See the file "COPYING" in the main directory of this archive
556+ * for more details.
557+ *
558+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
559+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
560+ *
561+ */
562+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
563+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
564+
565+#define PCI_DMA_OFFSET 0x20000000
566+
567+struct device;
568+
569+static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
570+{
571+ return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
572+}
573+
574+static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
575+{
576+ return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
577+}
578+
579+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
580+ dma_addr_t dma_addr)
581+{
582+ return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
583+}
584+
585+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
586+ size_t size, enum dma_data_direction direction)
587+{
588+}
589+
590+static inline int plat_dma_supported(struct device *dev, u64 mask)
591+{
592+ return 1;
593+}
594+
595+static inline void plat_extra_sync_for_device(struct device *dev)
596+{
597+ return;
598+}
599+
600+static inline int plat_dma_mapping_error(struct device *dev,
601+ dma_addr_t dma_addr)
602+{
603+ return 0;
604+}
605+
606+static inline int plat_device_is_coherent(struct device *dev)
607+{
608+#ifdef CONFIG_DMA_COHERENT
609+ return 1;
610+#endif
611+#ifdef CONFIG_DMA_NONCOHERENT
612+ return 0;
613+#endif
614+}
615+
616+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
617--- /dev/null
618+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
619@@ -0,0 +1,79 @@
620+#ifndef _ATHEROS_GPIO_H_
621+#define _ATHEROS_GPIO_H_
622+
623+#include <ar231x.h>
624+
625+struct ar231x_gpiodev {
626+ u32 valid_mask;
627+ u32 (*get_output)(void);
628+ u32 (*set_output)(u32 mask, u32 val);
629+ u32 (*get)(void);
630+ u32 (*set)(u32 mask, u32 val);
631+};
632+
633+extern const struct ar231x_gpiodev *ar231x_gpiodev;
634+
635+/*
636+ * Wrappers for the generic GPIO layer
637+ */
638+
639+static inline int gpio_direction_input(unsigned gpio) {
640+ u32 mask = 1 << gpio;
641+
642+ if (!(ar231x_gpiodev->valid_mask & mask))
643+ return -ENXIO;
644+
645+ ar231x_gpiodev->set_output(mask, 0);
646+ return 0;
647+}
648+
649+static inline void gpio_set_value(unsigned gpio, int value) {
650+ u32 mask = 1 << gpio;
651+
652+ if (!(ar231x_gpiodev->valid_mask & mask))
653+ return;
654+
655+ ar231x_gpiodev->set(mask, (!!value) * mask);
656+}
657+
658+static inline int gpio_direction_output(unsigned gpio, int value) {
659+ u32 mask = 1 << gpio;
660+
661+ if (!(ar231x_gpiodev->valid_mask & mask))
662+ return -ENXIO;
663+
664+ ar231x_gpiodev->set_output(mask, mask);
665+ ar231x_gpiodev->set(mask, (!!value) * mask);
666+ return 0;
667+}
668+
669+/* Reads the gpio pin. Unchecked function */
670+static inline int gpio_get_value(unsigned gpio) {
671+ u32 mask = 1 << gpio;
672+
673+ if (!(ar231x_gpiodev->valid_mask & mask))
674+ return 0;
675+
676+ return !!(ar231x_gpiodev->get() & mask);
677+}
678+
679+static inline int gpio_request(unsigned gpio, const char *label) {
680+ return 0;
681+}
682+
683+static inline void gpio_free(unsigned gpio) {
684+}
685+
686+/* Returns IRQ to attach for gpio. Unchecked function */
687+static inline int gpio_to_irq(unsigned gpio) {
688+ return AR531X_GPIO_IRQ(gpio);
689+}
690+
691+/* Returns gpio for IRQ attached. Unchecked function */
692+static inline int irq_to_gpio(unsigned irq) {
693+ return (irq - (AR531X_GPIO_IRQ(0)));
694+}
695+
696+#include <asm-generic/gpio.h> /* cansleep wrappers */
697+
698+#endif
699--- /dev/null
700+++ b/arch/mips/include/asm/mach-ar231x/reset.h
701@@ -0,0 +1,6 @@
702+#ifndef __AR531X_RESET_H
703+#define __AR531X_RESET_H
704+
705+void ar531x_disable_reset_button(void);
706+
707+#endif /* __AR531X_RESET_H */
708--- /dev/null
709+++ b/arch/mips/include/asm/mach-ar231x/war.h
710@@ -0,0 +1,25 @@
711+/*
712+ * This file is subject to the terms and conditions of the GNU General Public
713+ * License. See the file "COPYING" in the main directory of this archive
714+ * for more details.
715+ *
716+ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
717+ */
718+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
719+#define __ASM_MIPS_MACH_ATHEROS_WAR_H
720+
721+#define R4600_V1_INDEX_ICACHEOP_WAR 0
722+#define R4600_V1_HIT_CACHEOP_WAR 0
723+#define R4600_V2_HIT_CACHEOP_WAR 0
724+#define R5432_CP0_INTERRUPT_WAR 0
725+#define BCM1250_M3_WAR 0
726+#define SIBYTE_1956_WAR 0
727+#define MIPS4K_ICACHE_REFILL_WAR 0
728+#define MIPS_CACHE_SYNC_WAR 0
729+#define TX49XX_ICACHE_INDEX_INV_WAR 0
730+#define RM9000_CDEX_SMP_WAR 0
731+#define ICACHE_REFILLS_WORKAROUND_WAR 0
732+#define R10000_LLSC_WAR 0
733+#define MIPS34K_MISSED_ITLB_WAR 0
734+
735+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
736--- /dev/null
737+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
738@@ -0,0 +1,580 @@
739+/*
740+ * Register definitions for AR2315+
741+ *
742+ * This file is subject to the terms and conditions of the GNU General Public
743+ * License. See the file "COPYING" in the main directory of this archive
744+ * for more details.
745+ *
746+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
747+ * Copyright (C) 2006 FON Technology, SL.
748+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
749+ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
750+ */
751+
752+#ifndef __AR2315_REG_H
753+#define __AR2315_REG_H
754+
755+/*
756+ * IRQs
757+ */
758+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
759+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
760+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
761+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
762+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
763+
764+/*
765+ * Address map
766+ */
767+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
768+#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */
769+#define AR2315_PCI 0xB0100000 /* PCI MMR */
770+#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */
771+#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */
772+#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */
773+#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
774+#define AR2315_UART0 0xB1100003 /* UART MMR */
775+#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */
776+#define AR2315_PCIEXT 0x80000000 /* pci external */
777+
778+/*
779+ * Reset Register
780+ */
781+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
782+
783+#define AR2315_RESET_COLD_AHB 0x00000001
784+#define AR2315_RESET_COLD_APB 0x00000002
785+#define AR2315_RESET_COLD_CPU 0x00000004
786+#define AR2315_RESET_COLD_CPUWARM 0x00000008
787+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
788+#define AR2317_RESET_SYSTEM 0x00000010
789+
790+
791+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
792+
793+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
794+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
795+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
796+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
797+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
798+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
799+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
800+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
801+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
802+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
803+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
804+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
805+
806+/*
807+ * AHB master arbitration control
808+ */
809+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
810+
811+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
812+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
813+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
814+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
815+#define AR2315_ARB_PCI 0x00000010 /* PCI */
816+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
817+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
818+
819+/*
820+ * Config Register
821+ */
822+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
823+
824+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
825+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
826+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
827+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
828+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
829+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
830+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
831+
832+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
833+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
834+#define AR2315_CONFIG_PCIAHB 0x00000800
835+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
836+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
837+#define AR2315_CONFIG_CPU_DRAM 0x00010000
838+#define AR2315_CONFIG_CPU_PCI 0x00020000
839+#define AR2315_CONFIG_CPU_MMR 0x00040000
840+#define AR2315_CONFIG_BIG 0x00000400
841+
842+
843+/*
844+ * NMI control
845+ */
846+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
847+
848+#define AR2315_NMI_EN 1
849+
850+/*
851+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
852+ */
853+#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
854+
855+#define AR2315_REV_MAJ 0x00f0
856+#define AR2315_REV_MAJ_S 4
857+#define AR2315_REV_MIN 0x000f
858+#define AR2315_REV_MIN_S 0
859+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
860+
861+/*
862+ * Interface Enable
863+ */
864+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
865+
866+#define AR2315_IF_MASK 0x00000007
867+#define AR2315_IF_DISABLED 0
868+#define AR2315_IF_PCI 1
869+#define AR2315_IF_TS_LOCAL 2
870+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
871+#define AR2315_IF_LOCAL_HOST 0x00000008
872+#define AR2315_IF_PCI_HOST 0x00000010
873+#define AR2315_IF_PCI_INTR 0x00000020
874+#define AR2315_IF_PCI_CLK_MASK 0x00030000
875+#define AR2315_IF_PCI_CLK_INPUT 0
876+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
877+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
878+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
879+#define AR2315_IF_PCI_CLK_SHIFT 16
880+
881+/*
882+ * APB Interrupt control
883+ */
884+
885+#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
886+#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
887+#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
888+
889+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
890+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
891+#define AR2315_ISR_SPI 0x0004 /* SPI bus */
892+#define AR2315_ISR_AHB 0x0008 /* AHB error */
893+#define AR2315_ISR_APB 0x0010 /* APB error */
894+#define AR2315_ISR_TIMER 0x0020 /* timer */
895+#define AR2315_ISR_GPIO 0x0040 /* GPIO */
896+#define AR2315_ISR_WD 0x0080 /* watchdog */
897+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
898+
899+#define AR2315_GISR_MISC 0x0001
900+#define AR2315_GISR_WLAN0 0x0002
901+#define AR2315_GISR_MPEGTS_RSVD 0x0004
902+#define AR2315_GISR_LOCALPCI 0x0008
903+#define AR2315_GISR_WMACPOLL 0x0010
904+#define AR2315_GISR_TIMER 0x0020
905+#define AR2315_GISR_ETHERNET 0x0040
906+
907+/*
908+ * Interrupt routing from IO to the processor IP bits
909+ * Define our inter mask and level
910+ */
911+#define AR2315_INTR_MISCIO SR_IBIT3
912+#define AR2315_INTR_WLAN0 SR_IBIT4
913+#define AR2315_INTR_ENET0 SR_IBIT5
914+#define AR2315_INTR_LOCALPCI SR_IBIT6
915+#define AR2315_INTR_WMACPOLL SR_IBIT7
916+#define AR2315_INTR_COMPARE SR_IBIT8
917+
918+/*
919+ * Timers
920+ */
921+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
922+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
923+#define AR2315_WD (AR2315_DSLBASE + 0x0038)
924+#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
925+
926+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
927+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
928+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
929+
930+/*
931+ * CPU Performance Counters
932+ */
933+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
934+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
935+
936+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
937+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
938+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
939+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
940+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
941+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
942+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
943+
944+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
945+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
946+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
947+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
948+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
949+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
950+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
951+
952+/*
953+ * AHB Error Reporting.
954+ */
955+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
956+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
957+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
958+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
959+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
960+
961+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
962+ /* write 1 to clear all bits in ERR0 */
963+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
964+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
965+
966+#define AR2315_PROCERR_HMAST 0x0000000f
967+#define AR2315_PROCERR_HMAST_DFLT 0
968+#define AR2315_PROCERR_HMAST_WMAC 1
969+#define AR2315_PROCERR_HMAST_ENET 2
970+#define AR2315_PROCERR_HMAST_PCIENDPT 3
971+#define AR2315_PROCERR_HMAST_LOCAL 4
972+#define AR2315_PROCERR_HMAST_CPU 5
973+#define AR2315_PROCERR_HMAST_PCITGT 6
974+
975+#define AR2315_PROCERR_HMAST_S 0
976+#define AR2315_PROCERR_HWRITE 0x00000010
977+#define AR2315_PROCERR_HSIZE 0x00000060
978+#define AR2315_PROCERR_HSIZE_S 5
979+#define AR2315_PROCERR_HTRANS 0x00000180
980+#define AR2315_PROCERR_HTRANS_S 7
981+#define AR2315_PROCERR_HBURST 0x00000e00
982+#define AR2315_PROCERR_HBURST_S 9
983+
984+/*
985+ * Clock Control
986+ */
987+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
988+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
989+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
990+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
991+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
992+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
993+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
994+
995+/* PLLc Control fields */
996+#define PLLC_REF_DIV_M 0x00000003
997+#define PLLC_REF_DIV_S 0
998+#define PLLC_FDBACK_DIV_M 0x0000007C
999+#define PLLC_FDBACK_DIV_S 2
1000+#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1001+#define PLLC_ADD_FDBACK_DIV_S 7
1002+#define PLLC_CLKC_DIV_M 0x0001c000
1003+#define PLLC_CLKC_DIV_S 14
1004+#define PLLC_CLKM_DIV_M 0x00700000
1005+#define PLLC_CLKM_DIV_S 20
1006+
1007+/* CPU CLK Control fields */
1008+#define CPUCLK_CLK_SEL_M 0x00000003
1009+#define CPUCLK_CLK_SEL_S 0
1010+#define CPUCLK_CLK_DIV_M 0x0000000c
1011+#define CPUCLK_CLK_DIV_S 2
1012+
1013+/* AMBA CLK Control fields */
1014+#define AMBACLK_CLK_SEL_M 0x00000003
1015+#define AMBACLK_CLK_SEL_S 0
1016+#define AMBACLK_CLK_DIV_M 0x0000000c
1017+#define AMBACLK_CLK_DIV_S 2
1018+
1019+/*
1020+ * GPIO
1021+ */
1022+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1023+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1024+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1025+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1026+
1027+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1028+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1029+#define AR2315_GPIO_CR_I(x) (0) /* input */
1030+
1031+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1032+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1033+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1034+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1035+
1036+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1037+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1038+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1039+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1040+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1041+
1042+#define AR2315_RESET_GPIO 5
1043+#define AR2315_NUM_GPIO 22
1044+
1045+/*
1046+ * PCI Clock Control
1047+ */
1048+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1049+
1050+#define AR2315_PCICLK_INPUT_M 0x3
1051+#define AR2315_PCICLK_INPUT_S 0
1052+
1053+#define AR2315_PCICLK_PLLC_CLKM 0
1054+#define AR2315_PCICLK_PLLC_CLKM1 1
1055+#define AR2315_PCICLK_PLLC_CLKC 2
1056+#define AR2315_PCICLK_REF_CLK 3
1057+
1058+#define AR2315_PCICLK_DIV_M 0xc
1059+#define AR2315_PCICLK_DIV_S 2
1060+
1061+#define AR2315_PCICLK_IN_FREQ 0
1062+#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1063+#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1064+#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1065+
1066+/*
1067+ * Observation Control Register
1068+ */
1069+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1070+#define OCR_GPIO0_IRIN 0x0040
1071+#define OCR_GPIO1_IROUT 0x0080
1072+#define OCR_GPIO3_RXCLR 0x0200
1073+
1074+/*
1075+ * General Clock Control
1076+ */
1077+
1078+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1079+#define MISCCLK_PLLBYPASS_EN 0x00000001
1080+#define MISCCLK_PROCREFCLK 0x00000002
1081+
1082+/*
1083+ * SDRAM Controller
1084+ * - No read or write buffers are included.
1085+ */
1086+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1087+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1088+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1089+
1090+#define SDRAM_DATA_WIDTH_M 0x00006000
1091+#define SDRAM_DATA_WIDTH_S 13
1092+
1093+#define SDRAM_COL_WIDTH_M 0x00001E00
1094+#define SDRAM_COL_WIDTH_S 9
1095+
1096+#define SDRAM_ROW_WIDTH_M 0x000001E0
1097+#define SDRAM_ROW_WIDTH_S 5
1098+
1099+#define SDRAM_BANKADDR_BITS_M 0x00000018
1100+#define SDRAM_BANKADDR_BITS_S 3
1101+
1102+/*
1103+ * SPI Flash Interface Registers
1104+ */
1105+
1106+#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1107+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1108+#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1109+
1110+#define SPI_CTL_START 0x00000100
1111+#define SPI_CTL_BUSY 0x00010000
1112+#define SPI_CTL_TXCNT_MASK 0x0000000f
1113+#define SPI_CTL_RXCNT_MASK 0x000000f0
1114+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1115+#define SPI_CTL_SIZE_MASK 0x00060000
1116+
1117+#define SPI_CTL_CLK_SEL_MASK 0x03000000
1118+#define SPI_OPCODE_MASK 0x000000ff
1119+
1120+/*
1121+ * PCI Bus Interface Registers
1122+ */
1123+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1124+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1125+
1126+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1127+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1128+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1129+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1130+#define AR2315_PCIMISC_RST_MODE 0x00000030
1131+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1132+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1133+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1134+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1135+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1136+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1137+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1138+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1139+
1140+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1141+
1142+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1143+
1144+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1145+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1146+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1147+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1148+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1149+
1150+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1151+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1152+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1153+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1154+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1155+
1156+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1157+
1158+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1159+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1160+
1161+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1162+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1163+
1164+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1165+
1166+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1167+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1168+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1169+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1170+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1171+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1172+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1173+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1174+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1175+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1176+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1177+#define AR2315_PCI_EXT_INT 0x02000000
1178+#define AR2315_PCI_ABORT_INT 0x04000000
1179+
1180+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1181+
1182+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1183+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1184+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1185+
1186+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1187+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1188+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1189+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1190+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1191+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1192+
1193+
1194+/*
1195+ * Local Bus Interface Registers
1196+ */
1197+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1198+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1199+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1200+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1201+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1202+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1203+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1204+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1205+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1206+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1207+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1208+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1209+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1210+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1211+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1212+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1213+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1214+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1215+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1216+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1217+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1218+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1219+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1220+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1221+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1222+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1223+
1224+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1225+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1226+
1227+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1228+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1229+
1230+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1231+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1232+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1233+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1234+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1235+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1236+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1237+#define AR2315_LBM_TIMEOUT_SHFT 7
1238+#define AR2315_LBM_PORTMUX 0x07000000
1239+
1240+
1241+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1242+
1243+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1244+#define AR2315_LB_TXEN_0 0x01
1245+#define AR2315_LB_TXEN_1 0x02
1246+#define AR2315_LB_TXEN_2 0x04
1247+#define AR2315_LB_TXEN_3 0x08
1248+
1249+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1250+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1251+
1252+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1253+#define AR2315_LB_RXEN 0x01
1254+
1255+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1256+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1257+
1258+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1259+#define AR2315_INT_TX_DESC 0x0001
1260+#define AR2315_INT_TX_OK 0x0002
1261+#define AR2315_INT_TX_ERR 0x0004
1262+#define AR2315_INT_TX_EOF 0x0008
1263+#define AR2315_INT_RX_DESC 0x0010
1264+#define AR2315_INT_RX_OK 0x0020
1265+#define AR2315_INT_RX_ERR 0x0040
1266+#define AR2315_INT_RX_EOF 0x0080
1267+#define AR2315_INT_TX_TRUNC 0x0100
1268+#define AR2315_INT_TX_STARVE 0x0200
1269+#define AR2315_INT_LB_TIMEOUT 0x0400
1270+#define AR2315_INT_LB_ERR 0x0800
1271+#define AR2315_INT_MBOX_WR 0x1000
1272+#define AR2315_INT_MBOX_RD 0x2000
1273+
1274+/* Bit definitions for INT MASK are the same as INT_STATUS */
1275+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1276+
1277+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1278+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1279+
1280+/*
1281+ * IR Interface Registers
1282+ */
1283+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1284+
1285+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1286+
1287+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1288+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1289+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1290+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1291+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1292+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1293+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1294+
1295+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1296+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1297+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1298+
1299+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1300+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1301+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1302+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1303+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1304+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1305+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1306+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1307+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1308+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1309+
1310+#define HOST_PCI_DEV_ID 3
1311+#define HOST_PCI_MBAR0 0x10000000
1312+#define HOST_PCI_MBAR1 0x20000000
1313+#define HOST_PCI_MBAR2 0x30000000
1314+
1315+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1316+#define PCI_DEVICE_MEM_SPACE 0x800000
1317+
1318+#endif /* __AR2315_REG_H */
1319--- /dev/null
1320+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1321@@ -0,0 +1,236 @@
1322+/*
1323+ * This file is subject to the terms and conditions of the GNU General Public
1324+ * License. See the file "COPYING" in the main directory of this archive
1325+ * for more details.
1326+ *
1327+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1328+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1329+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1330+ */
1331+
1332+#ifndef AR5312_H
1333+#define AR5312_H
1334+
1335+#include <asm/addrspace.h>
1336+
1337+/*
1338+ * IRQs
1339+ */
1340+
1341+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1342+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1343+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1344+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1345+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1346+
1347+
1348+/* Address Map */
1349+#define AR531X_WLAN0 0x18000000
1350+#define AR531X_WLAN1 0x18500000
1351+#define AR531X_ENET0 0x18100000
1352+#define AR531X_ENET1 0x18200000
1353+#define AR531X_SDRAMCTL 0x18300000
1354+#define AR531X_FLASHCTL 0x18400000
1355+#define AR531X_APBBASE 0x1c000000
1356+#define AR531X_FLASH 0x1e000000
1357+#define AR531X_UART0 0xbc000003 /* UART MMR */
1358+
1359+/*
1360+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1361+ * should be considered available. The AR5312 supports 2 enet MACS,
1362+ * even though many reference boards only actually use 1 of them
1363+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1364+ * The AR2312 supports 1 enet MAC.
1365+ */
1366+#define AR531X_NUM_ENET_MAC 2
1367+
1368+/*
1369+ * Need these defines to determine true number of ethernet MACs
1370+ */
1371+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1372+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1373+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1374+#define AR531X_RADIO_MASK_OFF 0xc8
1375+#define AR531X_RADIO0_MASK 0x0003
1376+#define AR531X_RADIO1_MASK 0x000c
1377+#define AR531X_RADIO1_S 2
1378+
1379+/*
1380+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1381+ * should be considered available.
1382+ */
1383+#define AR531X_NUM_WMAC 2
1384+
1385+/* Reset/Timer Block Address Map */
1386+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1387+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1388+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1389+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1390+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1391+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1392+#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1393+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1394+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1395+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1396+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1397+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1398+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1399+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1400+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1401+
1402+/* AR531X_WD_CTRL register bit field definitions */
1403+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1404+#define AR531X_WD_CTRL_NMI 0x0001
1405+#define AR531X_WD_CTRL_RESET 0x0002
1406+
1407+/* AR531X_ISR register bit field definitions */
1408+#define AR531X_ISR_NONE 0x0000
1409+#define AR531X_ISR_TIMER 0x0001
1410+#define AR531X_ISR_AHBPROC 0x0002
1411+#define AR531X_ISR_AHBDMA 0x0004
1412+#define AR531X_ISR_GPIO 0x0008
1413+#define AR531X_ISR_UART0 0x0010
1414+#define AR531X_ISR_UART0DMA 0x0020
1415+#define AR531X_ISR_WD 0x0040
1416+#define AR531X_ISR_LOCAL 0x0080
1417+
1418+/* AR531X_RESET register bit field definitions */
1419+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1420+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1421+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1422+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1423+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1424+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1425+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1426+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1427+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1428+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1429+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1430+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1431+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1432+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1433+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1434+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1435+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1436+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1437+
1438+#define AR531X_RESET_WMAC0_BITS \
1439+ AR531X_RESET_WLAN0 |\
1440+ AR531X_RESET_WARM_WLAN0_MAC |\
1441+ AR531X_RESET_WARM_WLAN0_BB
1442+
1443+#define AR531X_RESERT_WMAC1_BITS \
1444+ AR531X_RESET_WLAN1 |\
1445+ AR531X_RESET_WARM_WLAN1_MAC |\
1446+ AR531X_RESET_WARM_WLAN1_BB
1447+
1448+/* AR5312_CLOCKCTL1 register bit field definitions */
1449+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1450+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1451+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1452+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1453+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1454+
1455+/* Valid for AR5312 and AR2312 */
1456+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1457+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1458+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1459+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1460+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1461+
1462+/* Valid for AR2313 */
1463+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1464+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1465+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1466+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1467+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1468+
1469+
1470+/* AR531X_ENABLE register bit field definitions */
1471+#define AR531X_ENABLE_WLAN0 0x0001
1472+#define AR531X_ENABLE_ENET0 0x0002
1473+#define AR531X_ENABLE_ENET1 0x0004
1474+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1475+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1476+#define AR531X_ENABLE_WLAN1 \
1477+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1478+
1479+/* AR531X_REV register bit field definitions */
1480+#define AR531X_REV_WMAC_MAJ 0xf000
1481+#define AR531X_REV_WMAC_MAJ_S 12
1482+#define AR531X_REV_WMAC_MIN 0x0f00
1483+#define AR531X_REV_WMAC_MIN_S 8
1484+#define AR531X_REV_MAJ 0x00f0
1485+#define AR531X_REV_MAJ_S 4
1486+#define AR531X_REV_MIN 0x000f
1487+#define AR531X_REV_MIN_S 0
1488+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1489+
1490+/* Major revision numbers, bits 7..4 of Revision ID register */
1491+#define AR531X_REV_MAJ_AR5312 0x4
1492+#define AR531X_REV_MAJ_AR2313 0x5
1493+
1494+/* Minor revision numbers, bits 3..0 of Revision ID register */
1495+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1496+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1497+
1498+/* AR531X_FLASHCTL register bit field definitions */
1499+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1500+#define FLASHCTL_IDCY_S 0
1501+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1502+#define FLASHCTL_WST1_S 5
1503+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1504+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1505+#define FLASHCTL_WST2_S 11
1506+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1507+#define FLASHCTL_AC_S 16
1508+#define FLASHCTL_AC_128K 0x00000000
1509+#define FLASHCTL_AC_256K 0x00010000
1510+#define FLASHCTL_AC_512K 0x00020000
1511+#define FLASHCTL_AC_1M 0x00030000
1512+#define FLASHCTL_AC_2M 0x00040000
1513+#define FLASHCTL_AC_4M 0x00050000
1514+#define FLASHCTL_AC_8M 0x00060000
1515+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1516+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1517+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1518+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1519+#define FLASHCTL_WP 0x04000000 /* Write protect */
1520+#define FLASHCTL_BM 0x08000000 /* Burst mode */
1521+#define FLASHCTL_MW 0x30000000 /* Memory width */
1522+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1523+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1524+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1525+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1526+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1527+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1528+
1529+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1530+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1531+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1532+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1533+
1534+/* ARM SDRAM Controller -- just enough to determine memory size */
1535+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1536+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1537+#define MEM_CFG1_AC0_S 8
1538+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1539+#define MEM_CFG1_AC1_S 12
1540+
1541+/* GPIO Address Map */
1542+#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1543+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1544+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1545+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1546+
1547+/* GPIO Control Register bit field definitions */
1548+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1549+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1550+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1551+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1552+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1553+#define AR531X_NUM_GPIO 8
1554+
1555+
1556+#endif
1557+
1558--- /dev/null
1559+++ b/arch/mips/ar231x/ar5312.c
1560@@ -0,0 +1,549 @@
1561+/*
1562+ * This file is subject to the terms and conditions of the GNU General Public
1563+ * License. See the file "COPYING" in the main directory of this archive
1564+ * for more details.
1565+ *
1566+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1567+ * Copyright (C) 2006 FON Technology, SL.
1568+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1569+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1570+ */
1571+
1572+/*
1573+ * Platform devices for Atheros SoCs
1574+ */
1575+
1576+#include <linux/autoconf.h>
1577+#include <linux/init.h>
1578+#include <linux/module.h>
1579+#include <linux/types.h>
1580+#include <linux/string.h>
1581+#include <linux/mtd/physmap.h>
1582+#include <linux/platform_device.h>
1583+#include <linux/kernel.h>
1584+#include <linux/reboot.h>
1585+#include <linux/leds.h>
1586+#include <asm/bootinfo.h>
1587+#include <asm/reboot.h>
1588+#include <asm/time.h>
1589+#include <asm/irq.h>
1590+#include <asm/io.h>
1591+#include <gpio.h>
1592+
1593+#include <ar231x_platform.h>
1594+#include <ar5312_regs.h>
1595+#include <ar231x.h>
1596+#include "devices.h"
1597+#include "ar5312.h"
1598+
1599+static void
1600+ar5312_misc_irq_dispatch(void)
1601+{
1602+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1603+
1604+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1605+ do_IRQ(AR531X_MISC_IRQ_TIMER);
1606+ (void)ar231x_read_reg(AR531X_TIMER);
1607+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1608+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1609+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1610+ do_IRQ(AR531X_MISC_IRQ_UART0);
1611+ else if (ar231x_misc_intrs & AR531X_ISR_WD)
1612+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1613+ else
1614+ do_IRQ(AR531X_MISC_IRQ_NONE);
1615+}
1616+
1617+static asmlinkage void
1618+ar5312_irq_dispatch(void)
1619+{
1620+ int pending = read_c0_status() & read_c0_cause();
1621+
1622+ if (pending & CAUSEF_IP2)
1623+ do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1624+ else if (pending & CAUSEF_IP3)
1625+ do_IRQ(AR5312_IRQ_ENET0_INTRS);
1626+ else if (pending & CAUSEF_IP4)
1627+ do_IRQ(AR5312_IRQ_ENET1_INTRS);
1628+ else if (pending & CAUSEF_IP5)
1629+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1630+ else if (pending & CAUSEF_IP6)
1631+ ar5312_misc_irq_dispatch();
1632+ else if (pending & CAUSEF_IP7)
1633+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
1634+}
1635+
1636+
1637+/* Enable the specified AR531X_MISC_IRQ interrupt */
1638+static void
1639+ar5312_misc_intr_enable(unsigned int irq)
1640+{
1641+ unsigned int imr;
1642+
1643+ imr = ar231x_read_reg(AR531X_IMR);
1644+ imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1645+ ar231x_write_reg(AR531X_IMR, imr);
1646+}
1647+
1648+/* Disable the specified AR531X_MISC_IRQ interrupt */
1649+static void
1650+ar5312_misc_intr_disable(unsigned int irq)
1651+{
1652+ unsigned int imr;
1653+
1654+ imr = ar231x_read_reg(AR531X_IMR);
1655+ imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1656+ ar231x_write_reg(AR531X_IMR, imr);
1657+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1658+}
1659+
1660+static void
1661+ar5312_misc_intr_end(unsigned int irq)
1662+{
1663+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1664+ ar5312_misc_intr_enable(irq);
1665+}
1666+
1667+static struct irq_chip ar5312_misc_intr_controller = {
1668+ .name = "AR5312-MISC",
1669+ .disable = ar5312_misc_intr_disable,
1670+ .ack = ar5312_misc_intr_disable,
1671+ .mask_ack = ar5312_misc_intr_disable,
1672+ .mask = ar5312_misc_intr_disable,
1673+ .unmask = ar5312_misc_intr_enable,
1674+ .end = ar5312_misc_intr_end,
1675+};
1676+
1677+
1678+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1679+{
1680+ u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1681+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1682+ u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1683+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1684+
1685+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1686+ procAddr, proc1, dmaAddr, dma1);
1687+
1688+ machine_restart("AHB error"); /* Catastrophic failure */
1689+ return IRQ_HANDLED;
1690+}
1691+
1692+
1693+static struct irqaction ar5312_ahb_proc_interrupt = {
1694+ .handler = ar5312_ahb_proc_handler,
1695+ .flags = IRQF_DISABLED,
1696+ .name = "ar5312_ahb_proc_interrupt",
1697+};
1698+
1699+
1700+static struct irqaction cascade = {
1701+ .handler = no_action,
1702+ .flags = IRQF_DISABLED,
1703+ .name = "cascade",
1704+};
1705+
1706+void __init ar5312_irq_init(void)
1707+{
1708+ int i;
1709+
1710+ if (!is_5312())
1711+ return;
1712+
1713+ ar231x_irq_dispatch = ar5312_irq_dispatch;
1714+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1715+ int irq = AR531X_MISC_IRQ_BASE + i;
1716+ set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller,
1717+ handle_level_irq);
1718+ }
1719+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1720+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1721+}
1722+
1723+const struct ar231x_gpiodev ar5312_gpiodev;
1724+
1725+static u32
1726+ar5312_gpio_get_output(void)
1727+{
1728+ u32 reg;
1729+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1730+ reg &= ar5312_gpiodev.valid_mask;
1731+ return reg;
1732+}
1733+
1734+static u32
1735+ar5312_gpio_set_output(u32 mask, u32 val)
1736+{
1737+ u32 reg;
1738+
1739+ reg = ar231x_read_reg(AR531X_GPIO_CR);
1740+ reg |= mask;
1741+ reg &= ~val;
1742+ ar231x_write_reg(AR531X_GPIO_CR, reg);
1743+ return reg;
1744+}
1745+
1746+static u32
1747+ar5312_gpio_get(void)
1748+{
1749+ u32 reg;
1750+ reg = ar231x_read_reg(AR531X_GPIO_DI);
1751+ reg &= ar5312_gpiodev.valid_mask;
1752+ return reg;
1753+}
1754+
1755+static u32
1756+ar5312_gpio_set(u32 mask, u32 value)
1757+{
1758+ u32 reg;
1759+ reg = ar231x_read_reg(AR531X_GPIO_DO);
1760+ reg &= ~mask;
1761+ reg |= value;
1762+ ar231x_write_reg(AR531X_GPIO_DO, reg);
1763+ return reg;
1764+}
1765+
1766+const struct ar231x_gpiodev ar5312_gpiodev = {
1767+ .valid_mask = (1 << 8) - 1,
1768+ .get_output = ar5312_gpio_get_output,
1769+ .set_output = ar5312_gpio_set_output,
1770+ .get = ar5312_gpio_get,
1771+ .set = ar5312_gpio_set,
1772+};
1773+
1774+static struct physmap_flash_data ar5312_flash_data = {
1775+ .width = 2,
1776+};
1777+
1778+static struct resource ar5312_flash_resource = {
1779+ .start = AR531X_FLASH,
1780+ .end = AR531X_FLASH + 0x800000 - 1,
1781+ .flags = IORESOURCE_MEM,
1782+};
1783+
1784+static struct ar231x_eth ar5312_eth0_data = {
1785+ .reset_base = AR531X_RESET,
1786+ .reset_mac = AR531X_RESET_ENET0,
1787+ .reset_phy = AR531X_RESET_EPHY0,
1788+ .phy_base = KSEG1ADDR(AR531X_ENET0),
1789+ .config = &ar231x_board,
1790+};
1791+
1792+static struct ar231x_eth ar5312_eth1_data = {
1793+ .reset_base = AR531X_RESET,
1794+ .reset_mac = AR531X_RESET_ENET1,
1795+ .reset_phy = AR531X_RESET_EPHY1,
1796+ .phy_base = KSEG1ADDR(AR531X_ENET1),
1797+ .config = &ar231x_board,
1798+};
1799+
1800+static struct platform_device ar5312_physmap_flash = {
1801+ .name = "physmap-flash",
1802+ .id = 0,
1803+ .dev.platform_data = &ar5312_flash_data,
1804+ .resource = &ar5312_flash_resource,
1805+ .num_resources = 1,
1806+};
1807+
1808+#ifdef CONFIG_LEDS_GPIO
1809+static struct gpio_led ar5312_leds[] = {
1810+ { .name = "wlan", .gpio = 0, .active_low = 1, },
1811+};
1812+
1813+static const struct gpio_led_platform_data ar5312_led_data = {
1814+ .num_leds = ARRAY_SIZE(ar5312_leds),
1815+ .leds = (void *) ar5312_leds,
1816+};
1817+
1818+static struct platform_device ar5312_gpio_leds = {
1819+ .name = "leds-gpio",
1820+ .id = -1,
1821+ .dev.platform_data = (void *) &ar5312_led_data,
1822+};
1823+#endif
1824+
1825+/*
1826+ * NB: This mapping size is larger than the actual flash size,
1827+ * but this shouldn't be a problem here, because the flash
1828+ * will simply be mapped multiple times.
1829+ */
1830+static char __init *ar5312_flash_limit(void)
1831+{
1832+ u32 ctl;
1833+ /*
1834+ * Configure flash bank 0.
1835+ * Assume 8M window size. Flash will be aliased if it's smaller
1836+ */
1837+ ctl = FLASHCTL_E |
1838+ FLASHCTL_AC_8M |
1839+ FLASHCTL_RBLE |
1840+ (0x01 << FLASHCTL_IDCY_S) |
1841+ (0x07 << FLASHCTL_WST1_S) |
1842+ (0x07 << FLASHCTL_WST2_S) |
1843+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1844+
1845+ ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1846+
1847+ /* Disable other flash banks */
1848+ ar231x_write_reg(AR531X_FLASHCTL1,
1849+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1850+
1851+ ar231x_write_reg(AR531X_FLASHCTL2,
1852+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1853+
1854+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1855+}
1856+
1857+int __init ar5312_init_devices(void)
1858+{
1859+ struct ar231x_boarddata *config;
1860+ u32 fctl = 0;
1861+ const u8 *radio;
1862+ u8 *c;
1863+
1864+ if (!is_5312())
1865+ return 0;
1866+
1867+ /* Locate board/radio config data */
1868+ ar231x_find_config(ar5312_flash_limit());
1869+ config = ar231x_board.config;
1870+
1871+
1872+ /*
1873+ * Chip IDs and hardware detection for some Atheros
1874+ * models are really broken!
1875+ *
1876+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1877+ * as indication for AR2312, which is otherwise
1878+ * indistinguishable from the real AR5312.
1879+ */
1880+ if (ar231x_board.radio) {
1881+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1882+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1883+ config->flags |= BD_ISCASPER;
1884+ } else
1885+ radio = NULL;
1886+
1887+ /* AR2313 has CPU minor rev. 10 */
1888+ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1889+ ar231x_devtype = DEV_TYPE_AR2313;
1890+
1891+ /* AR2312 shares the same Silicon ID as AR5312 */
1892+ else if (config->flags & BD_ISCASPER)
1893+ ar231x_devtype = DEV_TYPE_AR2312;
1894+
1895+ /* Everything else is probably AR5312 or compatible */
1896+ else
1897+ ar231x_devtype = DEV_TYPE_AR5312;
1898+
1899+ /* fixup flash width */
1900+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1901+ switch (fctl) {
1902+ case FLASHCTL_MWx16:
1903+ ar5312_flash_data.width = 2;
1904+ break;
1905+ case FLASHCTL_MWx8:
1906+ default:
1907+ ar5312_flash_data.width = 1;
1908+ break;
1909+ }
1910+
1911+ platform_device_register(&ar5312_physmap_flash);
1912+
1913+#ifdef CONFIG_LEDS_GPIO
1914+ ar5312_leds[0].gpio = config->sysLedGpio;
1915+ platform_device_register(&ar5312_gpio_leds);
1916+#endif
1917+
1918+ /* Fix up MAC addresses if necessary */
1919+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1920+ memcpy(config->enet0_mac, config->enet1_mac, 6);
1921+
1922+ /* If ENET0 and ENET1 have the same mac address,
1923+ * increment the one from ENET1 */
1924+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1925+ c = config->enet1_mac + 5;
1926+ while ((c >= config->enet1_mac) && !(++(*c)))
1927+ c--;
1928+ }
1929+
1930+ switch(ar231x_devtype) {
1931+ case DEV_TYPE_AR5312:
1932+ ar5312_eth0_data.macaddr = config->enet0_mac;
1933+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1934+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1935+
1936+ ar5312_eth1_data.macaddr = config->enet1_mac;
1937+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1938+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1939+
1940+ if (!ar231x_board.radio)
1941+ return 0;
1942+
1943+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) &&
1944+ (config->flags & BD_WLAN0))
1945+ ar231x_add_wmac(0, AR531X_WLAN0,
1946+ AR5312_IRQ_WLAN0_INTRS);
1947+
1948+ break;
1949+ /*
1950+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1951+ * of ENET1. Atheros calls it 'twisted' for a reason :)
1952+ */
1953+ case DEV_TYPE_AR2312:
1954+ case DEV_TYPE_AR2313:
1955+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1956+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1957+ ar5312_eth1_data.macaddr = config->enet0_mac;
1958+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1959+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1960+
1961+ if (!ar231x_board.radio)
1962+ return 0;
1963+ break;
1964+ default:
1965+ break;
1966+ }
1967+
1968+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) &&
1969+ (config->flags & BD_WLAN1))
1970+ ar231x_add_wmac(1, AR531X_WLAN1,
1971+ AR5312_IRQ_WLAN1_INTRS);
1972+
1973+ return 0;
1974+}
1975+
1976+
1977+static void ar5312_restart(char *command)
1978+{
1979+ /* reset the system */
1980+ local_irq_disable();
1981+ while(1) {
1982+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1983+ }
1984+}
1985+
1986+
1987+/*
1988+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1989+ * to determine the predevisor value.
1990+ */
1991+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
1992+
1993+
1994+static int __init
1995+ar5312_cpu_frequency(void)
1996+{
1997+ unsigned int result;
1998+ unsigned int predivide_mask, predivide_shift;
1999+ unsigned int multiplier_mask, multiplier_shift;
2000+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
2001+ unsigned int doubler_mask;
2002+ u16 devid;
2003+
2004+ /* Trust the bootrom's idea of cpu frequency. */
2005+ if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2006+ return result;
2007+
2008+ devid = ar231x_read_reg(AR531X_REV);
2009+ devid &= AR531X_REV_MAJ;
2010+ devid >>= AR531X_REV_MAJ_S;
2011+ if (devid == AR531X_REV_MAJ_AR2313) {
2012+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2013+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2014+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2015+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2016+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2017+ } else { /* AR5312 and AR2312 */
2018+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2019+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2020+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2021+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2022+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2023+ }
2024+
2025+ /*
2026+ * Clocking is derived from a fixed 40MHz input clock.
2027+ *
2028+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2029+ * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2030+ * flash, Timer, Watchdog Timer)
2031+ *
2032+ * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2033+ *
2034+ * So, for example, with a PLL multiplier of 5, we have
2035+ *
2036+ * cpuFreq = 200MHz
2037+ * sysFreq = 50MHz
2038+ * cntFreq = 100MHz
2039+ *
2040+ * We compute the CPU frequency, based on PLL settings.
2041+ */
2042+
2043+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2044+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2045+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2046+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2047+
2048+ if (clockCtl1 & doubler_mask) {
2049+ multiplier = multiplier << 1;
2050+ }
2051+ return (40000000 / preDivisor) * multiplier;
2052+}
2053+
2054+static inline int
2055+ar5312_sys_frequency(void)
2056+{
2057+ return ar5312_cpu_frequency() / 4;
2058+}
2059+
2060+void __init
2061+ar5312_time_init(void)
2062+{
2063+ if (!is_5312())
2064+ return;
2065+
2066+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2067+}
2068+
2069+
2070+void __init
2071+ar5312_prom_init(void)
2072+{
2073+ u32 memsize, memcfg, bank0AC, bank1AC;
2074+ u32 devid;
2075+
2076+ if (!is_5312())
2077+ return;
2078+
2079+ /* Detect memory size */
2080+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2081+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2082+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2083+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2084+ + (bank1AC ? (1 << (bank1AC+1)) : 0);
2085+ memsize <<= 20;
2086+ add_memory_region(0, memsize, BOOT_MEM_RAM);
2087+
2088+ devid = ar231x_read_reg(AR531X_REV);
2089+ devid >>= AR531X_REV_WMAC_MIN_S;
2090+ devid &= AR531X_REV_CHIP;
2091+ ar231x_board.devid = (u16) devid;
2092+ ar231x_gpiodev = &ar5312_gpiodev;
2093+}
2094+
2095+void __init
2096+ar5312_plat_setup(void)
2097+{
2098+ if (!is_5312())
2099+ return;
2100+
2101+ /* Clear any lingering AHB errors */
2102+ ar231x_read_reg(AR531X_PROCADDR);
2103+ ar231x_read_reg(AR531X_DMAADDR);
2104+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2105+
2106+ _machine_restart = ar5312_restart;
2107+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2108+}
2109+
2110--- /dev/null
2111+++ b/arch/mips/ar231x/ar2315.c
2112@@ -0,0 +1,658 @@
2113+/*
2114+ * This file is subject to the terms and conditions of the GNU General Public
2115+ * License. See the file "COPYING" in the main directory of this archive
2116+ * for more details.
2117+ *
2118+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2119+ * Copyright (C) 2006 FON Technology, SL.
2120+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2121+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2122+ */
2123+
2124+/*
2125+ * Platform devices for Atheros SoCs
2126+ */
2127+
2128+#include <linux/autoconf.h>
2129+#include <linux/init.h>
2130+#include <linux/module.h>
2131+#include <linux/types.h>
2132+#include <linux/string.h>
2133+#include <linux/platform_device.h>
2134+#include <linux/kernel.h>
2135+#include <linux/reboot.h>
2136+#include <linux/delay.h>
2137+#include <linux/leds.h>
2138+#include <asm/bootinfo.h>
2139+#include <asm/reboot.h>
2140+#include <asm/time.h>
2141+#include <asm/irq.h>
2142+#include <asm/io.h>
2143+#include <asm/gpio.h>
2144+
2145+#include <ar231x_platform.h>
2146+#include <ar2315_regs.h>
2147+#include <ar231x.h>
2148+#include "devices.h"
2149+#include "ar2315.h"
2150+
2151+static u32 gpiointmask = 0, gpiointval = 0;
2152+
2153+static inline void ar2315_gpio_irq(void)
2154+{
2155+ u32 pend;
2156+ int bit = -1;
2157+
2158+ /* only do one gpio interrupt at a time */
2159+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2160+
2161+ if (pend) {
2162+ bit = fls(pend) - 1;
2163+ pend &= ~(1 << bit);
2164+ gpiointval ^= (1 << bit);
2165+ }
2166+
2167+ if (!pend)
2168+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2169+
2170+ /* Enable interrupt with edge detection */
2171+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2172+ return;
2173+
2174+ if (bit >= 0)
2175+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2176+}
2177+
2178+
2179+/*
2180+ * Called when an interrupt is received, this function
2181+ * determines exactly which interrupt it was, and it
2182+ * invokes the appropriate handler.
2183+ *
2184+ * Implicitly, we also define interrupt priority by
2185+ * choosing which to dispatch first.
2186+ */
2187+static asmlinkage void
2188+ar2315_irq_dispatch(void)
2189+{
2190+ int pending = read_c0_status() & read_c0_cause();
2191+
2192+ if (pending & CAUSEF_IP3)
2193+ do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2194+ else if (pending & CAUSEF_IP4)
2195+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
2196+ else if (pending & CAUSEF_IP2) {
2197+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2198+
2199+ if (misc_intr & AR2315_ISR_SPI)
2200+ do_IRQ(AR531X_MISC_IRQ_SPI);
2201+ else if (misc_intr & AR2315_ISR_TIMER)
2202+ do_IRQ(AR531X_MISC_IRQ_TIMER);
2203+ else if (misc_intr & AR2315_ISR_AHB)
2204+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2205+ else if (misc_intr & AR2315_ISR_GPIO)
2206+ ar2315_gpio_irq();
2207+ else if (misc_intr & AR2315_ISR_UART0)
2208+ do_IRQ(AR531X_MISC_IRQ_UART0);
2209+ else if (misc_intr & AR2315_ISR_WD)
2210+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2211+ else
2212+ do_IRQ(AR531X_MISC_IRQ_NONE);
2213+ } else if (pending & CAUSEF_IP7)
2214+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
2215+}
2216+
2217+static void ar2315_set_gpiointmask(int gpio, int level)
2218+{
2219+ u32 reg;
2220+
2221+ reg = ar231x_read_reg(AR2315_GPIO_INT);
2222+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2223+ reg |= gpio | AR2315_GPIO_INT_LVL(level);
2224+ ar231x_write_reg(AR2315_GPIO_INT, reg);
2225+}
2226+
2227+static void ar2315_gpio_intr_enable(unsigned int irq)
2228+{
2229+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2230+
2231+ /* Enable interrupt with edge detection */
2232+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2233+ return;
2234+
2235+ gpiointmask |= (1 << gpio);
2236+ ar2315_set_gpiointmask(gpio, 3);
2237+}
2238+
2239+static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
2240+{
2241+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2242+
2243+ /* reconfigure GPIO line as input */
2244+ ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2245+ ar2315_gpio_intr_enable(irq);
2246+ return 0;
2247+}
2248+
2249+static void ar2315_gpio_intr_disable(unsigned int irq)
2250+{
2251+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2252+
2253+ /* Disable interrupt */
2254+ gpiointmask &= ~(1 << gpio);
2255+ ar2315_set_gpiointmask(gpio, 0);
2256+}
2257+
2258+static void
2259+ar2315_gpio_intr_end(unsigned int irq)
2260+{
2261+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2262+ ar2315_gpio_intr_enable(irq);
2263+}
2264+
2265+static struct irq_chip ar2315_gpio_intr_controller = {
2266+ .typename = "AR2315-GPIO",
2267+ .startup = ar2315_gpio_intr_startup,
2268+ .ack = ar2315_gpio_intr_disable,
2269+ .mask_ack = ar2315_gpio_intr_disable,
2270+ .mask = ar2315_gpio_intr_disable,
2271+ .unmask = ar2315_gpio_intr_enable,
2272+ .end = ar2315_gpio_intr_end,
2273+};
2274+
2275+static void
2276+ar2315_misc_intr_enable(unsigned int irq)
2277+{
2278+ unsigned int imr;
2279+
2280+ imr = ar231x_read_reg(AR2315_IMR);
2281+ switch(irq) {
2282+ case AR531X_MISC_IRQ_SPI:
2283+ imr |= AR2315_ISR_SPI;
2284+ break;
2285+ case AR531X_MISC_IRQ_TIMER:
2286+ imr |= AR2315_ISR_TIMER;
2287+ break;
2288+ case AR531X_MISC_IRQ_AHB_PROC:
2289+ imr |= AR2315_ISR_AHB;
2290+ break;
2291+ case AR531X_MISC_IRQ_GPIO:
2292+ imr |= AR2315_ISR_GPIO;
2293+ break;
2294+ case AR531X_MISC_IRQ_UART0:
2295+ imr |= AR2315_ISR_UART0;
2296+ break;
2297+ case AR531X_MISC_IRQ_WATCHDOG:
2298+ imr |= AR2315_ISR_WD;
2299+ break;
2300+ default:
2301+ break;
2302+ }
2303+ ar231x_write_reg(AR2315_IMR, imr);
2304+}
2305+
2306+static void
2307+ar2315_misc_intr_disable(unsigned int irq)
2308+{
2309+ unsigned int imr;
2310+
2311+ imr = ar231x_read_reg(AR2315_IMR);
2312+ switch(irq) {
2313+ case AR531X_MISC_IRQ_SPI:
2314+ imr &= ~AR2315_ISR_SPI;
2315+ break;
2316+ case AR531X_MISC_IRQ_TIMER:
2317+ imr &= ~AR2315_ISR_TIMER;
2318+ break;
2319+ case AR531X_MISC_IRQ_AHB_PROC:
2320+ imr &= ~AR2315_ISR_AHB;
2321+ break;
2322+ case AR531X_MISC_IRQ_GPIO:
2323+ imr &= ~AR2315_ISR_GPIO;
2324+ break;
2325+ case AR531X_MISC_IRQ_UART0:
2326+ imr &= ~AR2315_ISR_UART0;
2327+ break;
2328+ case AR531X_MISC_IRQ_WATCHDOG:
2329+ imr &= ~AR2315_ISR_WD;
2330+ break;
2331+ default:
2332+ break;
2333+ }
2334+ ar231x_write_reg(AR2315_IMR, imr);
2335+}
2336+
2337+static void
2338+ar2315_misc_intr_end(unsigned int irq)
2339+{
2340+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2341+ ar2315_misc_intr_enable(irq);
2342+}
2343+
2344+
2345+static struct irq_chip ar2315_misc_intr_controller = {
2346+ .typename = "AR2315-MISC",
2347+ .ack = ar2315_misc_intr_disable,
2348+ .mask_ack = ar2315_misc_intr_disable,
2349+ .mask = ar2315_misc_intr_disable,
2350+ .unmask = ar2315_misc_intr_enable,
2351+ .end = ar2315_misc_intr_end,
2352+};
2353+
2354+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2355+{
2356+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2357+ ar231x_read_reg(AR2315_AHB_ERR1);
2358+
2359+ printk(KERN_ERR "AHB fatal error\n");
2360+ machine_restart("AHB error"); /* Catastrophic failure */
2361+
2362+ return IRQ_HANDLED;
2363+}
2364+
2365+static struct irqaction ar2315_ahb_proc_interrupt = {
2366+ .handler = ar2315_ahb_proc_handler,
2367+ .flags = IRQF_DISABLED,
2368+ .name = "ar2315_ahb_proc_interrupt",
2369+};
2370+
2371+static struct irqaction cascade = {
2372+ .handler = no_action,
2373+ .flags = IRQF_DISABLED,
2374+ .name = "cascade",
2375+};
2376+
2377+void
2378+ar2315_irq_init(void)
2379+{
2380+ int i;
2381+
2382+ if (!is_2315())
2383+ return;
2384+
2385+ ar231x_irq_dispatch = ar2315_irq_dispatch;
2386+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2387+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2388+ int irq = AR531X_MISC_IRQ_BASE + i;
2389+ set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller,
2390+ handle_level_irq);
2391+ }
2392+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2393+ int irq = AR531X_GPIO_IRQ_BASE + i;
2394+ set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2395+ handle_level_irq);
2396+ }
2397+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2398+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2399+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2400+}
2401+
2402+const struct ar231x_gpiodev ar2315_gpiodev;
2403+
2404+static u32
2405+ar2315_gpio_get_output(void)
2406+{
2407+ u32 reg;
2408+ reg = ar231x_read_reg(AR2315_GPIO_CR);
2409+ reg &= ar2315_gpiodev.valid_mask;
2410+ return reg;
2411+}
2412+
2413+static u32
2414+ar2315_gpio_set_output(u32 mask, u32 val)
2415+{
2416+ u32 reg;
2417+
2418+ reg = ar231x_read_reg(AR2315_GPIO_CR);
2419+ reg &= ~mask;
2420+ reg |= val;
2421+ ar231x_write_reg(AR2315_GPIO_CR, reg);
2422+ return reg;
2423+}
2424+
2425+static u32
2426+ar2315_gpio_get(void)
2427+{
2428+ u32 reg;
2429+ reg = ar231x_read_reg(AR2315_GPIO_DI);
2430+ reg &= ar2315_gpiodev.valid_mask;
2431+ return reg;
2432+}
2433+
2434+static u32
2435+ar2315_gpio_set(u32 mask, u32 value)
2436+{
2437+ u32 reg;
2438+ reg = ar231x_read_reg(AR2315_GPIO_DO);
2439+ reg &= ~mask;
2440+ reg |= value;
2441+ ar231x_write_reg(AR2315_GPIO_DO, reg);
2442+ return reg;
2443+}
2444+
2445+const struct ar231x_gpiodev ar2315_gpiodev = {
2446+ .valid_mask = (1 << 22) - 1,
2447+ .get_output = ar2315_gpio_get_output,
2448+ .set_output = ar2315_gpio_set_output,
2449+ .get = ar2315_gpio_get,
2450+ .set = ar2315_gpio_set,
2451+};
2452+
2453+static struct ar231x_eth ar2315_eth_data = {
2454+ .reset_base = AR2315_RESET,
2455+ .reset_mac = AR2315_RESET_ENET0,
2456+ .reset_phy = AR2315_RESET_EPHY0,
2457+ .phy_base = AR2315_ENET0,
2458+ .config = &ar231x_board,
2459+};
2460+
2461+static struct resource ar2315_spiflash_res[] = {
2462+ {
2463+ .name = "flash_base",
2464+ .flags = IORESOURCE_MEM,
2465+ .start = KSEG1ADDR(AR2315_SPI_READ),
2466+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2467+ },
2468+ {
2469+ .name = "flash_regs",
2470+ .flags = IORESOURCE_MEM,
2471+ .start = 0x11300000,
2472+ .end = 0x11300012,
2473+ },
2474+};
2475+
2476+static struct platform_device ar2315_spiflash = {
2477+ .id = 0,
2478+ .name = "spiflash",
2479+ .resource = ar2315_spiflash_res,
2480+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2481+};
2482+
2483+static struct platform_device ar2315_wdt = {
2484+ .id = 0,
2485+ .name = "ar2315_wdt",
2486+};
2487+
2488+#define SPI_FLASH_CTL 0x00
2489+#define SPI_FLASH_OPCODE 0x04
2490+#define SPI_FLASH_DATA 0x08
2491+
2492+static inline u32
2493+spiflash_read_reg(int reg)
2494+{
2495+ return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg);
2496+}
2497+
2498+static inline void
2499+spiflash_write_reg(int reg, u32 data)
2500+{
2501+ ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data);
2502+}
2503+
2504+static u32
2505+spiflash_wait_status(void)
2506+{
2507+ u32 reg;
2508+
2509+ do {
2510+ reg = spiflash_read_reg(SPI_FLASH_CTL);
2511+ } while (reg & SPI_CTL_BUSY);
2512+
2513+ return reg;
2514+}
2515+
2516+static u8
2517+spiflash_probe(void)
2518+{
2519+ u32 reg;
2520+
2521+ reg = spiflash_wait_status();
2522+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2523+ reg |= (1 << 4) | 4 | SPI_CTL_START;
2524+
2525+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2526+ spiflash_write_reg(SPI_FLASH_CTL, reg);
2527+
2528+ reg = spiflash_wait_status();
2529+ reg = spiflash_read_reg(SPI_FLASH_DATA);
2530+ reg &= 0xff;
2531+
2532+ return (u8) reg;
2533+}
2534+
2535+
2536+#define STM_8MBIT_SIGNATURE 0x13
2537+#define STM_16MBIT_SIGNATURE 0x14
2538+#define STM_32MBIT_SIGNATURE 0x15
2539+#define STM_64MBIT_SIGNATURE 0x16
2540+#define STM_128MBIT_SIGNATURE 0x17
2541+
2542+static u8 __init *
2543+ar2315_flash_limit(void)
2544+{
2545+ u32 flash_size = 0;
2546+
2547+ /* probe the flash chip size */
2548+ switch(spiflash_probe()) {
2549+ case STM_8MBIT_SIGNATURE:
2550+ flash_size = 0x00100000;
2551+ break;
2552+ case STM_16MBIT_SIGNATURE:
2553+ flash_size = 0x00200000;
2554+ break;
2555+ case STM_32MBIT_SIGNATURE:
2556+ flash_size = 0x00400000;
2557+ break;
2558+ case STM_64MBIT_SIGNATURE:
2559+ flash_size = 0x00800000;
2560+ break;
2561+ case STM_128MBIT_SIGNATURE:
2562+ flash_size = 0x01000000;
2563+ break;
2564+ }
2565+
2566+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2567+ flash_size - 1;
2568+ return (u8 *) ar2315_spiflash_res[0].end + 1;
2569+}
2570+
2571+#ifdef CONFIG_LEDS_GPIO
2572+static struct gpio_led ar2315_leds[6];
2573+static struct gpio_led_platform_data ar2315_led_data = {
2574+ .leds = (void *) ar2315_leds,
2575+};
2576+
2577+static struct platform_device ar2315_gpio_leds = {
2578+ .name = "leds-gpio",
2579+ .id = -1,
2580+ .dev = {
2581+ .platform_data = (void *) &ar2315_led_data,
2582+ }
2583+};
2584+
2585+static void __init
2586+ar2315_init_gpio(void)
2587+{
2588+ static char led_names[6][6];
2589+ int i, led = 0;
2590+
2591+ ar2315_led_data.num_leds = 0;
2592+ for(i = 1; i < 8; i++)
2593+ {
2594+ if((i == AR2315_RESET_GPIO) ||
2595+ (i == ar231x_board.config->resetConfigGpio))
2596+ continue;
2597+
2598+ if(i == ar231x_board.config->sysLedGpio)
2599+ strcpy(led_names[led], "wlan");
2600+ else
2601+ sprintf(led_names[led], "gpio%d", i);
2602+
2603+ ar2315_leds[led].name = led_names[led];
2604+ ar2315_leds[led].gpio = i;
2605+ ar2315_leds[led].active_low = 0;
2606+ led++;
2607+ }
2608+ ar2315_led_data.num_leds = led;
2609+ platform_device_register(&ar2315_gpio_leds);
2610+}
2611+#else
2612+static inline void ar2315_init_gpio(void)
2613+{
2614+}
2615+#endif
2616+
2617+int __init
2618+ar2315_init_devices(void)
2619+{
2620+ if (!is_2315())
2621+ return 0;
2622+
2623+ /* Find board configuration */
2624+ ar231x_find_config(ar2315_flash_limit());
2625+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2626+
2627+ ar2315_init_gpio();
2628+ platform_device_register(&ar2315_wdt);
2629+ platform_device_register(&ar2315_spiflash);
2630+ ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS,
2631+ &ar2315_eth_data);
2632+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2633+
2634+ return 0;
2635+}
2636+
2637+static void
2638+ar2315_restart(char *command)
2639+{
2640+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2641+
2642+ local_irq_disable();
2643+
2644+ /* try reset the system via reset control */
2645+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2646+
2647+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2648+ * give it some time to attempt a gpio based hardware reset
2649+ * (atheros reference design workaround) */
2650+ gpio_direction_output(AR2315_RESET_GPIO, 0);
2651+ mdelay(100);
2652+
2653+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2654+ * workaround. Attempt to jump to the mips reset location -
2655+ * the boot loader itself might be able to recover the system */
2656+ mips_reset_vec();
2657+}
2658+
2659+
2660+/*
2661+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2662+ * to determine the predevisor value.
2663+ */
2664+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2665+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2666+
2667+static unsigned int __init
2668+ar2315_sys_clk(unsigned int clockCtl)
2669+{
2670+ unsigned int pllcCtrl,cpuDiv;
2671+ unsigned int pllcOut,refdiv,fdiv,divby2;
2672+ unsigned int clkDiv;
2673+
2674+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2675+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2676+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2677+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2678+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2679+ divby2 += 1;
2680+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2681+
2682+
2683+ /* clkm input selected */
2684+ switch(clockCtl & CPUCLK_CLK_SEL_M) {
2685+ case 0:
2686+ case 1:
2687+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2688+ break;
2689+ case 2:
2690+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2691+ break;
2692+ default:
2693+ pllcOut = 40000000;
2694+ clkDiv = 1;
2695+ break;
2696+ }
2697+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2698+ cpuDiv = cpuDiv * 2 ?: 1;
2699+ return (pllcOut/(clkDiv * cpuDiv));
2700+}
2701+
2702+static inline unsigned int
2703+ar2315_cpu_frequency(void)
2704+{
2705+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2706+}
2707+
2708+static inline unsigned int
2709+ar2315_apb_frequency(void)
2710+{
2711+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2712+}
2713+
2714+void __init
2715+ar2315_time_init(void)
2716+{
2717+ if (!is_2315())
2718+ return;
2719+
2720+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2721+}
2722+
2723+void __init
2724+ar2315_prom_init(void)
2725+{
2726+ u32 memsize, memcfg, devid;
2727+
2728+ if (!is_2315())
2729+ return;
2730+
2731+ memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2732+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2733+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2734+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2735+ memsize <<= 3;
2736+ add_memory_region(0, memsize, BOOT_MEM_RAM);
2737+
2738+ /* Detect the hardware based on the device ID */
2739+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2740+ switch(devid) {
2741+ case 0x90:
2742+ case 0x91:
2743+ ar231x_devtype = DEV_TYPE_AR2317;
2744+ break;
2745+ default:
2746+ ar231x_devtype = DEV_TYPE_AR2315;
2747+ break;
2748+ }
2749+ ar231x_gpiodev = &ar2315_gpiodev;
2750+ ar231x_board.devid = devid;
2751+}
2752+
2753+void __init
2754+ar2315_plat_setup(void)
2755+{
2756+ u32 config;
2757+
2758+ if (!is_2315())
2759+ return;
2760+
2761+ /* Clear any lingering AHB errors */
2762+ config = read_c0_config();
2763+ write_c0_config(config & ~0x3);
2764+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2765+ ar231x_read_reg(AR2315_AHB_ERR1);
2766+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2767+
2768+ _machine_restart = ar2315_restart;
2769+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2770+}
2771--- /dev/null
2772+++ b/arch/mips/ar231x/ar2315.h
2773@@ -0,0 +1,37 @@
2774+#ifndef __AR2315_H
2775+#define __AR2315_H
2776+
2777+#ifdef CONFIG_ATHEROS_AR2315
2778+
2779+extern void ar2315_irq_init(void);
2780+extern int ar2315_init_devices(void);
2781+extern void ar2315_prom_init(void);
2782+extern void ar2315_plat_setup(void);
2783+extern void ar2315_time_init(void);
2784+
2785+#else
2786+
2787+static inline void ar2315_irq_init(void)
2788+{
2789+}
2790+
2791+static inline int ar2315_init_devices(void)
2792+{
2793+ return 0;
2794+}
2795+
2796+static inline void ar2315_prom_init(void)
2797+{
2798+}
2799+
2800+static inline void ar2315_plat_setup(void)
2801+{
2802+}
2803+
2804+static inline void ar2315_time_init(void)
2805+{
2806+}
2807+
2808+#endif
2809+
2810+#endif
2811--- /dev/null
2812+++ b/arch/mips/ar231x/ar5312.h
2813@@ -0,0 +1,38 @@
2814+#ifndef __AR5312_H
2815+#define __AR5312_H
2816+
2817+#ifdef CONFIG_ATHEROS_AR5312
2818+
2819+extern void ar5312_irq_init(void);
2820+extern int ar5312_init_devices(void);
2821+extern void ar5312_prom_init(void);
2822+extern void ar5312_plat_setup(void);
2823+extern void ar5312_time_init(void);
2824+extern void ar5312_time_init(void);
2825+
2826+#else
2827+
2828+static inline void ar5312_irq_init(void)
2829+{
2830+}
2831+
2832+static inline int ar5312_init_devices(void)
2833+{
2834+ return 0;
2835+}
2836+
2837+static inline void ar5312_prom_init(void)
2838+{
2839+}
2840+
2841+static inline void ar5312_plat_setup(void)
2842+{
2843+}
2844+
2845+static inline void ar5312_time_init(void)
2846+{
2847+}
2848+
2849+#endif
2850+
2851+#endif
2852--- /dev/null
2853+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2854@@ -0,0 +1,54 @@
2855+#ifndef __AR531X_H
2856+#define __AR531X_H
2857+
2858+#define AR531X_MISC_IRQ_BASE 0x20
2859+#define AR531X_GPIO_IRQ_BASE 0x30
2860+
2861+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2862+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2863+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2864+
2865+/* Miscellaneous interrupts, which share IP6 */
2866+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2867+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2868+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2869+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2870+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2871+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2872+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2873+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2874+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2875+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2876+#define AR531X_MISC_IRQ_COUNT 10
2877+
2878+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2879+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2880+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2881+#define AR531X_GPIO_IRQ_COUNT 22
2882+
2883+static inline u32
2884+ar231x_read_reg(u32 reg)
2885+{
2886+ return __raw_readl((u32 *) KSEG1ADDR(reg));
2887+}
2888+
2889+static inline void
2890+ar231x_write_reg(u32 reg, u32 val)
2891+{
2892+ __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2893+}
2894+
2895+static inline u32
2896+ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2897+{
2898+ u32 ret;
2899+
2900+ ret = ar231x_read_reg(reg);
2901+ ret &= ~mask;
2902+ ret |= val;
2903+ ar231x_write_reg(reg, ret);
2904+
2905+ return ret;
2906+}
2907+
2908+#endif
2909--- /dev/null
2910+++ b/arch/mips/ar231x/devices.h
2911@@ -0,0 +1,37 @@
2912+#ifndef __AR231X_DEVICES_H
2913+#define __AR231X_DEVICES_H
2914+
2915+enum {
2916+ /* handled by ar5312.c */
2917+ DEV_TYPE_AR2312,
2918+ DEV_TYPE_AR2313,
2919+ DEV_TYPE_AR5312,
2920+
2921+ /* handled by ar2315.c */
2922+ DEV_TYPE_AR2315,
2923+ DEV_TYPE_AR2316,
2924+ DEV_TYPE_AR2317,
2925+
2926+ DEV_TYPE_UNKNOWN
2927+};
2928+
2929+extern int ar231x_devtype;
2930+extern struct ar231x_board_config ar231x_board;
2931+extern asmlinkage void (*ar231x_irq_dispatch)(void);
2932+
2933+extern int ar231x_find_config(u8 *flash_limit);
2934+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2935+extern int ar231x_add_wmac(int nr, u32 base, int irq);
2936+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2937+
2938+static inline bool is_2315(void)
2939+{
2940+ return (current_cpu_data.cputype == CPU_4KEC);
2941+}
2942+
2943+static inline bool is_5312(void)
2944+{
2945+ return !is_2315();
2946+}
2947+
2948+#endif
2949--- /dev/null
2950+++ b/arch/mips/ar231x/devices.c
2951@@ -0,0 +1,175 @@
2952+#include <linux/kernel.h>
2953+#include <linux/init.h>
2954+#include <linux/serial.h>
2955+#include <linux/serial_core.h>
2956+#include <linux/serial_8250.h>
2957+#include <linux/platform_device.h>
2958+#include <ar231x_platform.h>
2959+#include <ar231x.h>
2960+#include "devices.h"
2961+#include "ar5312.h"
2962+#include "ar2315.h"
2963+
2964+struct ar231x_board_config ar231x_board;
2965+int ar231x_devtype = DEV_TYPE_UNKNOWN;
2966+const struct ar231x_gpiodev *ar231x_gpiodev;
2967+EXPORT_SYMBOL(ar231x_gpiodev);
2968+
2969+static struct resource ar231x_eth0_res[] = {
2970+ {
2971+ .name = "eth0_membase",
2972+ .flags = IORESOURCE_MEM,
2973+ },
2974+ {
2975+ .name = "eth0_irq",
2976+ .flags = IORESOURCE_IRQ,
2977+ }
2978+};
2979+
2980+static struct resource ar231x_eth1_res[] = {
2981+ {
2982+ .name = "eth1_membase",
2983+ .flags = IORESOURCE_MEM,
2984+ },
2985+ {
2986+ .name = "eth1_irq",
2987+ .flags = IORESOURCE_IRQ,
2988+ }
2989+};
2990+
2991+static struct platform_device ar231x_eth[] = {
2992+ {
2993+ .id = 0,
2994+ .name = "ar231x-eth",
2995+ .resource = ar231x_eth0_res,
2996+ .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2997+ },
2998+ {
2999+ .id = 1,
3000+ .name = "ar231x-eth",
3001+ .resource = ar231x_eth1_res,
3002+ .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3003+ }
3004+};
3005+
3006+static struct resource ar231x_wmac0_res[] = {
3007+ {
3008+ .name = "wmac0_membase",
3009+ .flags = IORESOURCE_MEM,
3010+ },
3011+ {
3012+ .name = "wmac0_irq",
3013+ .flags = IORESOURCE_IRQ,
3014+ }
3015+};
3016+
3017+static struct resource ar231x_wmac1_res[] = {
3018+ {
3019+ .name = "wmac1_membase",
3020+ .flags = IORESOURCE_MEM,
3021+ },
3022+ {
3023+ .name = "wmac1_irq",
3024+ .flags = IORESOURCE_IRQ,
3025+ }
3026+};
3027+
3028+
3029+static struct platform_device ar231x_wmac[] = {
3030+ {
3031+ .id = 0,
3032+ .name = "ar231x-wmac",
3033+ .resource = ar231x_wmac0_res,
3034+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3035+ .dev.platform_data = &ar231x_board,
3036+ },
3037+ {
3038+ .id = 1,
3039+ .name = "ar231x-wmac",
3040+ .resource = ar231x_wmac1_res,
3041+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3042+ .dev.platform_data = &ar231x_board,
3043+ },
3044+};
3045+
3046+static const char *devtype_strings[] = {
3047+ [DEV_TYPE_AR5312] = "Atheros AR5312",
3048+ [DEV_TYPE_AR2312] = "Atheros AR2312",
3049+ [DEV_TYPE_AR2313] = "Atheros AR2313",
3050+ [DEV_TYPE_AR2315] = "Atheros AR2315",
3051+ [DEV_TYPE_AR2316] = "Atheros AR2316",
3052+ [DEV_TYPE_AR2317] = "Atheros AR2317",
3053+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3054+};
3055+
3056+const char *get_system_type(void)
3057+{
3058+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3059+ !devtype_strings[ar231x_devtype])
3060+ return devtype_strings[DEV_TYPE_UNKNOWN];
3061+ return devtype_strings[ar231x_devtype];
3062+}
3063+
3064+
3065+int __init
3066+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3067+{
3068+ struct resource *res;
3069+
3070+ ar231x_eth[nr].dev.platform_data = pdata;
3071+ res = &ar231x_eth[nr].resource[0];
3072+ res->start = base;
3073+ res->end = base + 0x2000 - 1;
3074+ res++;
3075+ res->start = irq;
3076+ res->end = irq;
3077+ return platform_device_register(&ar231x_eth[nr]);
3078+}
3079+
3080+void __init
3081+ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3082+{
3083+ struct uart_port s;
3084+
3085+ memset(&s, 0, sizeof(s));
3086+
3087+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3088+ s.iotype = UPIO_MEM;
3089+ s.irq = AR531X_MISC_IRQ_UART0;
3090+ s.regshift = 2;
3091+ s.mapbase = mapbase;
3092+ s.uartclk = uartclk;
3093+ s.membase = (void __iomem *)s.mapbase;
3094+
3095+ early_serial_setup(&s);
3096+}
3097+
3098+int __init
3099+ar231x_add_wmac(int nr, u32 base, int irq)
3100+{
3101+ struct resource *res;
3102+
3103+ ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3104+ res = &ar231x_wmac[nr].resource[0];
3105+ res->start = base;
3106+ res->end = base + 0x10000 - 1;
3107+ res++;
3108+ res->start = irq;
3109+ res->end = irq;
3110+ return platform_device_register(&ar231x_wmac[nr]);
3111+}
3112+
3113+static int __init ar231x_register_devices(void)
3114+{
3115+ static struct resource res = {
3116+ .start = 0xFFFFFFFF,
3117+ };
3118+
3119+ platform_device_register_simple("GPIODEV", 0, &res, 1);
3120+ ar5312_init_devices();
3121+ ar2315_init_devices();
3122+
3123+ return 0;
3124+}
3125+
3126+device_initcall(ar231x_register_devices);
3127

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