| 1 | --- a/drivers/net/b44.c |
| 2 | +++ b/drivers/net/b44.c |
| 3 | @@ -1,7 +1,9 @@ |
| 4 | /* b44.c: Broadcom 4400 device driver. |
| 5 | * |
| 6 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) |
| 7 | - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) |
| 8 | + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi) |
| 9 | + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) |
| 10 | + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org) |
| 11 | * |
| 12 | * Distribute under GPL. |
| 13 | */ |
| 14 | @@ -25,6 +27,39 @@ |
| 15 | |
| 16 | #include "b44.h" |
| 17 | |
| 18 | +#include <typedefs.h> |
| 19 | +#include <bcmdevs.h> |
| 20 | +#include <osl.h> |
| 21 | +#include <bcmnvram.h> |
| 22 | +#include <sbconfig.h> |
| 23 | +#include <sbchipc.h> |
| 24 | +#include <sflash.h> |
| 25 | + |
| 26 | +#ifdef CONFIG_BCM947XX |
| 27 | +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0) |
| 28 | + |
| 29 | +static inline void e_aton(char *str, char *dest) |
| 30 | +{ |
| 31 | + int i = 0; |
| 32 | + u16 *d = (u16 *) dest; |
| 33 | + |
| 34 | + if (str == NULL) { |
| 35 | + memset(dest, 0, 6); |
| 36 | + return; |
| 37 | + } |
| 38 | + |
| 39 | + for (;;) { |
| 40 | + dest[i++] = (char) simple_strtoul(str, NULL, 16); |
| 41 | + str += 2; |
| 42 | + if (!*str++ || i == 6) |
| 43 | + break; |
| 44 | + } |
| 45 | +} |
| 46 | + |
| 47 | +static int instance = 0; |
| 48 | +#endif |
| 49 | + |
| 50 | + |
| 51 | #define DRV_MODULE_NAME "b44" |
| 52 | #define PFX DRV_MODULE_NAME ": " |
| 53 | #define DRV_MODULE_VERSION "0.93" |
| 54 | @@ -75,7 +110,7 @@ static char version[] __devinitdata = |
| 55 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
| 56 | |
| 57 | MODULE_AUTHOR("David S. Miller (davem@redhat.com)"); |
| 58 | -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver"); |
| 59 | +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver"); |
| 60 | MODULE_LICENSE("GPL"); |
| 61 | MODULE_PARM(b44_debug, "i"); |
| 62 | MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value"); |
| 63 | @@ -89,6 +124,8 @@ static struct pci_device_id b44_pci_tbl[ |
| 64 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
| 65 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1, |
| 66 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
| 67 | + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713, |
| 68 | + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
| 69 | { } /* terminate list with empty entry */ |
| 70 | }; |
| 71 | |
| 72 | @@ -113,11 +150,13 @@ static int b44_wait_bit(struct b44 *bp, |
| 73 | udelay(10); |
| 74 | } |
| 75 | if (i == timeout) { |
| 76 | +#ifdef DEBUG |
| 77 | printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register " |
| 78 | "%lx to %s.\n", |
| 79 | bp->dev->name, |
| 80 | bit, reg, |
| 81 | (clear ? "clear" : "set")); |
| 82 | +#endif |
| 83 | return -ENODEV; |
| 84 | } |
| 85 | return 0; |
| 86 | @@ -236,6 +275,8 @@ static void ssb_core_reset(struct b44 *b |
| 87 | udelay(1); |
| 88 | } |
| 89 | |
| 90 | +static int b44_4713_instance; |
| 91 | + |
| 92 | static int ssb_core_unit(struct b44 *bp) |
| 93 | { |
| 94 | #if 0 |
| 95 | @@ -258,6 +299,9 @@ static int ssb_core_unit(struct b44 *bp) |
| 96 | break; |
| 97 | }; |
| 98 | #endif |
| 99 | + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) |
| 100 | + return b44_4713_instance++; |
| 101 | + else |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | @@ -267,6 +311,28 @@ static int ssb_is_core_up(struct b44 *bp |
| 106 | == SBTMSLOW_CLOCK); |
| 107 | } |
| 108 | |
| 109 | +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index) |
| 110 | +{ |
| 111 | + u32 val; |
| 112 | + |
| 113 | + bw32(B44_CAM_CTRL, (CAM_CTRL_READ | |
| 114 | + (index << CAM_CTRL_INDEX_SHIFT))); |
| 115 | + |
| 116 | + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); |
| 117 | + |
| 118 | + val = br32(B44_CAM_DATA_LO); |
| 119 | + |
| 120 | + data[2] = (val >> 24) & 0xFF; |
| 121 | + data[3] = (val >> 16) & 0xFF; |
| 122 | + data[4] = (val >> 8) & 0xFF; |
| 123 | + data[5] = (val >> 0) & 0xFF; |
| 124 | + |
| 125 | + val = br32(B44_CAM_DATA_HI); |
| 126 | + |
| 127 | + data[0] = (val >> 8) & 0xFF; |
| 128 | + data[1] = (val >> 0) & 0xFF; |
| 129 | +} |
| 130 | + |
| 131 | static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index) |
| 132 | { |
| 133 | u32 val; |
| 134 | @@ -287,7 +353,7 @@ static void __b44_cam_write(struct b44 * |
| 135 | |
| 136 | static inline void __b44_disable_ints(struct b44 *bp) |
| 137 | { |
| 138 | - bw32(B44_IMASK, 0); |
| 139 | + bw32(B44_IMASK, ISTAT_TO); /* leave the timeout interrupt active */ |
| 140 | } |
| 141 | |
| 142 | static void b44_disable_ints(struct b44 *bp) |
| 143 | @@ -303,14 +369,14 @@ static void b44_enable_ints(struct b44 * |
| 144 | bw32(B44_IMASK, bp->imask); |
| 145 | } |
| 146 | |
| 147 | -static int b44_readphy(struct b44 *bp, int reg, u32 *val) |
| 148 | +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val) |
| 149 | { |
| 150 | int err; |
| 151 | |
| 152 | bw32(B44_EMAC_ISTAT, EMAC_INT_MII); |
| 153 | bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START | |
| 154 | (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) | |
| 155 | - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | |
| 156 | + (phy_addr << MDIO_DATA_PMD_SHIFT) | |
| 157 | (reg << MDIO_DATA_RA_SHIFT) | |
| 158 | (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT))); |
| 159 | err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); |
| 160 | @@ -319,23 +385,42 @@ static int b44_readphy(struct b44 *bp, i |
| 161 | return err; |
| 162 | } |
| 163 | |
| 164 | -static int b44_writephy(struct b44 *bp, int reg, u32 val) |
| 165 | +static int b44_readphy(struct b44 *bp, int reg, u32 *val) |
| 166 | +{ |
| 167 | + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) |
| 168 | + return 0; |
| 169 | + |
| 170 | + return __b44_readphy(bp, bp->phy_addr, reg, val); |
| 171 | +} |
| 172 | + |
| 173 | +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val) |
| 174 | { |
| 175 | bw32(B44_EMAC_ISTAT, EMAC_INT_MII); |
| 176 | bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START | |
| 177 | (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) | |
| 178 | - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | |
| 179 | + (phy_addr << MDIO_DATA_PMD_SHIFT) | |
| 180 | (reg << MDIO_DATA_RA_SHIFT) | |
| 181 | (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) | |
| 182 | (val & MDIO_DATA_DATA))); |
| 183 | return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); |
| 184 | } |
| 185 | |
| 186 | +static int b44_writephy(struct b44 *bp, int reg, u32 val) |
| 187 | +{ |
| 188 | + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) |
| 189 | + return 0; |
| 190 | + |
| 191 | + return __b44_writephy(bp, bp->phy_addr, reg, val); |
| 192 | +} |
| 193 | + |
| 194 | static int b44_phy_reset(struct b44 *bp) |
| 195 | { |
| 196 | u32 val; |
| 197 | int err; |
| 198 | |
| 199 | + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) |
| 200 | + return 0; |
| 201 | + |
| 202 | err = b44_writephy(bp, MII_BMCR, BMCR_RESET); |
| 203 | if (err) |
| 204 | return err; |
| 205 | @@ -406,6 +491,23 @@ static int b44_setup_phy(struct b44 *bp) |
| 206 | u32 val; |
| 207 | int err; |
| 208 | |
| 209 | + |
| 210 | + /* |
| 211 | + * workaround for bad hardware design in Linksys WAP54G v1.0 |
| 212 | + * see https://dev.openwrt.org/ticket/146 |
| 213 | + * check and reset bit "isolate" |
| 214 | + */ |
| 215 | + if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) && |
| 216 | + (atoi(nvram_get("boardnum")) == 2) && |
| 217 | + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) && |
| 218 | + (val & BMCR_ISOLATE) && |
| 219 | + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) { |
| 220 | + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n"); |
| 221 | + } |
| 222 | + |
| 223 | + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) |
| 224 | + return 0; |
| 225 | + |
| 226 | if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0) |
| 227 | goto out; |
| 228 | if ((err = b44_writephy(bp, B44_MII_ALEDCTRL, |
| 229 | @@ -498,6 +600,19 @@ static void b44_check_phy(struct b44 *bp |
| 230 | { |
| 231 | u32 bmsr, aux; |
| 232 | |
| 233 | + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) { |
| 234 | + bp->flags |= B44_FLAG_100_BASE_T; |
| 235 | + bp->flags |= B44_FLAG_FULL_DUPLEX; |
| 236 | + if (!netif_carrier_ok(bp->dev)) { |
| 237 | + u32 val = br32(B44_TX_CTRL); |
| 238 | + val |= TX_CTRL_DUPLEX; |
| 239 | + bw32(B44_TX_CTRL, val); |
| 240 | + netif_carrier_on(bp->dev); |
| 241 | + b44_link_report(bp); |
| 242 | + } |
| 243 | + return; |
| 244 | + } |
| 245 | + |
| 246 | if (!b44_readphy(bp, MII_BMSR, &bmsr) && |
| 247 | !b44_readphy(bp, B44_MII_AUXCTRL, &aux) && |
| 248 | (bmsr != 0xffff)) { |
| 249 | @@ -765,6 +880,25 @@ static int b44_rx(struct b44 *bp, int bu |
| 250 | return received; |
| 251 | } |
| 252 | |
| 253 | + |
| 254 | +static inline void __b44_reset(struct b44 *bp) |
| 255 | +{ |
| 256 | + spin_lock_irq(&bp->lock); |
| 257 | + b44_halt(bp); |
| 258 | + b44_init_rings(bp); |
| 259 | + b44_init_hw(bp); |
| 260 | + spin_unlock_irq(&bp->lock); |
| 261 | + |
| 262 | + b44_enable_ints(bp); |
| 263 | + netif_wake_queue(bp->dev); |
| 264 | +} |
| 265 | + |
| 266 | +static inline void __b44_set_timeout(struct b44 *bp, int timeout) |
| 267 | +{ |
| 268 | + /* Set timeout for Rx to two seconds after the last Tx */ |
| 269 | + bw32(B44_GPTIMER, timeout ? 2 * 125000000 : 0); |
| 270 | +} |
| 271 | + |
| 272 | static int b44_poll(struct net_device *netdev, int *budget) |
| 273 | { |
| 274 | struct b44 *bp = netdev->priv; |
| 275 | @@ -772,13 +906,13 @@ static int b44_poll(struct net_device *n |
| 276 | |
| 277 | spin_lock_irq(&bp->lock); |
| 278 | |
| 279 | - if (bp->istat & (ISTAT_TX | ISTAT_TO)) { |
| 280 | + if (bp->istat & ISTAT_TX) { |
| 281 | /* spin_lock(&bp->tx_lock); */ |
| 282 | b44_tx(bp); |
| 283 | /* spin_unlock(&bp->tx_lock); */ |
| 284 | } |
| 285 | spin_unlock_irq(&bp->lock); |
| 286 | - |
| 287 | + |
| 288 | done = 1; |
| 289 | if (bp->istat & ISTAT_RX) { |
| 290 | int orig_budget = *budget; |
| 291 | @@ -796,24 +930,18 @@ static int b44_poll(struct net_device *n |
| 292 | done = 0; |
| 293 | } |
| 294 | |
| 295 | - if (bp->istat & ISTAT_ERRORS) { |
| 296 | - spin_lock_irq(&bp->lock); |
| 297 | - b44_halt(bp); |
| 298 | - b44_init_rings(bp); |
| 299 | - b44_init_hw(bp); |
| 300 | - netif_wake_queue(bp->dev); |
| 301 | - spin_unlock_irq(&bp->lock); |
| 302 | - done = 1; |
| 303 | - } |
| 304 | - |
| 305 | if (done) { |
| 306 | netif_rx_complete(netdev); |
| 307 | b44_enable_ints(bp); |
| 308 | } |
| 309 | |
| 310 | + if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX))) |
| 311 | + __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0); |
| 312 | + |
| 313 | return (done ? 0 : 1); |
| 314 | } |
| 315 | |
| 316 | + |
| 317 | static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 318 | { |
| 319 | struct net_device *dev = dev_id; |
| 320 | @@ -832,6 +960,18 @@ static irqreturn_t b44_interrupt(int irq |
| 321 | */ |
| 322 | istat &= imask; |
| 323 | if (istat) { |
| 324 | + /* Workaround for the WL-500g WAN port hang */ |
| 325 | + if (istat & (ISTAT_TO | ISTAT_ERRORS)) { |
| 326 | + /* |
| 327 | + * no rx before the watchdog timeout |
| 328 | + * reset the interface |
| 329 | + */ |
| 330 | + __b44_reset(bp); |
| 331 | + } |
| 332 | + |
| 333 | + if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX))) |
| 334 | + __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0); |
| 335 | + |
| 336 | handled = 1; |
| 337 | if (netif_rx_schedule_prep(dev)) { |
| 338 | /* NOTE: These writes are posted by the readback of |
| 339 | @@ -848,6 +988,7 @@ static irqreturn_t b44_interrupt(int irq |
| 340 | bw32(B44_ISTAT, istat); |
| 341 | br32(B44_ISTAT); |
| 342 | } |
| 343 | + |
| 344 | spin_unlock_irqrestore(&bp->lock, flags); |
| 345 | return IRQ_RETVAL(handled); |
| 346 | } |
| 347 | @@ -859,16 +1000,7 @@ static void b44_tx_timeout(struct net_de |
| 348 | printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", |
| 349 | dev->name); |
| 350 | |
| 351 | - spin_lock_irq(&bp->lock); |
| 352 | - |
| 353 | - b44_halt(bp); |
| 354 | - b44_init_rings(bp); |
| 355 | - b44_init_hw(bp); |
| 356 | - |
| 357 | - spin_unlock_irq(&bp->lock); |
| 358 | - |
| 359 | - b44_enable_ints(bp); |
| 360 | - |
| 361 | + __b44_reset(bp); |
| 362 | netif_wake_queue(dev); |
| 363 | } |
| 364 | |
| 365 | @@ -1092,6 +1224,8 @@ static void b44_clear_stats(struct b44 * |
| 366 | /* bp->lock is held. */ |
| 367 | static void b44_chip_reset(struct b44 *bp) |
| 368 | { |
| 369 | + unsigned int sb_clock; |
| 370 | + |
| 371 | if (ssb_is_core_up(bp)) { |
| 372 | bw32(B44_RCV_LAZY, 0); |
| 373 | bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE); |
| 374 | @@ -1105,9 +1239,10 @@ static void b44_chip_reset(struct b44 *b |
| 375 | bw32(B44_DMARX_CTRL, 0); |
| 376 | bp->rx_prod = bp->rx_cons = 0; |
| 377 | } else { |
| 378 | - ssb_pci_setup(bp, (bp->core_unit == 0 ? |
| 379 | - SBINTVEC_ENET0 : |
| 380 | - SBINTVEC_ENET1)); |
| 381 | + /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/ |
| 382 | + ssb_pci_setup(bp, (bp->core_unit == 0 ? |
| 383 | + SBINTVEC_ENET0 : |
| 384 | + SBINTVEC_ENET1)); |
| 385 | } |
| 386 | |
| 387 | ssb_core_reset(bp); |
| 388 | @@ -1115,6 +1250,11 @@ static void b44_chip_reset(struct b44 *b |
| 389 | b44_clear_stats(bp); |
| 390 | |
| 391 | /* Make PHY accessible. */ |
| 392 | + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) |
| 393 | + sb_clock = 100000000; /* 100 MHz */ |
| 394 | + else |
| 395 | + sb_clock = 62500000; /* 62.5 MHz */ |
| 396 | + |
| 397 | bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE | |
| 398 | (0x0d & MDIO_CTRL_MAXF_MASK))); |
| 399 | br32(B44_MDIO_CTRL); |
| 400 | @@ -1216,6 +1356,8 @@ static int b44_open(struct net_device *d |
| 401 | struct b44 *bp = dev->priv; |
| 402 | int err; |
| 403 | |
| 404 | + netif_carrier_off(dev); |
| 405 | + |
| 406 | err = b44_alloc_consistent(bp); |
| 407 | if (err) |
| 408 | return err; |
| 409 | @@ -1236,9 +1378,10 @@ static int b44_open(struct net_device *d |
| 410 | bp->timer.expires = jiffies + HZ; |
| 411 | bp->timer.data = (unsigned long) bp; |
| 412 | bp->timer.function = b44_timer; |
| 413 | - add_timer(&bp->timer); |
| 414 | + b44_timer((unsigned long) bp); |
| 415 | |
| 416 | b44_enable_ints(bp); |
| 417 | + netif_start_queue(dev); |
| 418 | |
| 419 | return 0; |
| 420 | |
| 421 | @@ -1638,7 +1781,7 @@ static int b44_ioctl(struct net_device * |
| 422 | u32 mii_regval; |
| 423 | |
| 424 | spin_lock_irq(&bp->lock); |
| 425 | - err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval); |
| 426 | + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval); |
| 427 | spin_unlock_irq(&bp->lock); |
| 428 | |
| 429 | data->val_out = mii_regval; |
| 430 | @@ -1651,7 +1794,7 @@ static int b44_ioctl(struct net_device * |
| 431 | return -EPERM; |
| 432 | |
| 433 | spin_lock_irq(&bp->lock); |
| 434 | - err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in); |
| 435 | + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); |
| 436 | spin_unlock_irq(&bp->lock); |
| 437 | |
| 438 | return err; |
| 439 | @@ -1678,21 +1821,52 @@ static int b44_read_eeprom(struct b44 *b |
| 440 | static int __devinit b44_get_invariants(struct b44 *bp) |
| 441 | { |
| 442 | u8 eeprom[128]; |
| 443 | + u8 buf[32]; |
| 444 | int err; |
| 445 | + unsigned long flags; |
| 446 | |
| 447 | - err = b44_read_eeprom(bp, &eeprom[0]); |
| 448 | - if (err) |
| 449 | - goto out; |
| 450 | - |
| 451 | - bp->dev->dev_addr[0] = eeprom[79]; |
| 452 | - bp->dev->dev_addr[1] = eeprom[78]; |
| 453 | - bp->dev->dev_addr[2] = eeprom[81]; |
| 454 | - bp->dev->dev_addr[3] = eeprom[80]; |
| 455 | - bp->dev->dev_addr[4] = eeprom[83]; |
| 456 | - bp->dev->dev_addr[5] = eeprom[82]; |
| 457 | - |
| 458 | - bp->phy_addr = eeprom[90] & 0x1f; |
| 459 | - bp->mdc_port = (eeprom[90] >> 14) & 0x1; |
| 460 | + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) { |
| 461 | +#ifdef CONFIG_BCM947XX |
| 462 | + sprintf(buf, "et%dmacaddr", instance - 1); |
| 463 | + e_aton(nvram_get(buf), bp->dev->dev_addr); |
| 464 | + |
| 465 | + sprintf(buf, "et%dphyaddr", instance - 1); |
| 466 | + bp->phy_addr = B44_PHY_ADDR_NO_PHY; |
| 467 | +#else |
| 468 | + /* |
| 469 | + * BCM47xx boards don't have a EEPROM. The MAC is stored in |
| 470 | + * a NVRAM area somewhere in the flash memory. As we don't |
| 471 | + * know the location and/or the format of the NVRAM area |
| 472 | + * here, we simply rely on the bootloader to write the |
| 473 | + * MAC into the CAM. |
| 474 | + */ |
| 475 | + spin_lock_irqsave(&bp->lock, flags); |
| 476 | + __b44_cam_read(bp, bp->dev->dev_addr, 0); |
| 477 | + spin_unlock_irqrestore(&bp->lock, flags); |
| 478 | + |
| 479 | + /* |
| 480 | + * BCM47xx boards don't have a PHY. Usually there is a switch |
| 481 | + * chip with multiple PHYs connected to the PHY port. |
| 482 | + */ |
| 483 | + bp->phy_addr = B44_PHY_ADDR_NO_PHY; |
| 484 | +#endif |
| 485 | + bp->dma_offset = 0; |
| 486 | + } else { |
| 487 | + err = b44_read_eeprom(bp, &eeprom[0]); |
| 488 | + if (err) |
| 489 | + return err; |
| 490 | + |
| 491 | + bp->dev->dev_addr[0] = eeprom[79]; |
| 492 | + bp->dev->dev_addr[1] = eeprom[78]; |
| 493 | + bp->dev->dev_addr[2] = eeprom[81]; |
| 494 | + bp->dev->dev_addr[3] = eeprom[80]; |
| 495 | + bp->dev->dev_addr[4] = eeprom[83]; |
| 496 | + bp->dev->dev_addr[5] = eeprom[82]; |
| 497 | + |
| 498 | + bp->phy_addr = eeprom[90] & 0x1f; |
| 499 | + bp->dma_offset = SB_PCI_DMA; |
| 500 | + bp->mdc_port = (eeprom[90] >> 14) & 0x1; |
| 501 | + } |
| 502 | |
| 503 | /* With this, plus the rx_header prepended to the data by the |
| 504 | * hardware, we'll land the ethernet header on a 2-byte boundary. |
| 505 | @@ -1702,13 +1876,12 @@ static int __devinit b44_get_invariants( |
| 506 | bp->imask = IMASK_DEF; |
| 507 | |
| 508 | bp->core_unit = ssb_core_unit(bp); |
| 509 | - bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0); |
| 510 | |
| 511 | /* XXX - really required? |
| 512 | bp->flags |= B44_FLAG_BUGGY_TXPTR; |
| 513 | */ |
| 514 | -out: |
| 515 | - return err; |
| 516 | + |
| 517 | + return 0; |
| 518 | } |
| 519 | |
| 520 | static int __devinit b44_init_one(struct pci_dev *pdev, |
| 521 | @@ -1720,6 +1893,10 @@ static int __devinit b44_init_one(struct |
| 522 | struct b44 *bp; |
| 523 | int err, i; |
| 524 | |
| 525 | +#ifdef CONFIG_BCM947XX |
| 526 | + instance++; |
| 527 | +#endif |
| 528 | + |
| 529 | if (b44_version_printed++ == 0) |
| 530 | printk(KERN_INFO "%s", version); |
| 531 | |
| 532 | @@ -1834,11 +2011,17 @@ static int __devinit b44_init_one(struct |
| 533 | */ |
| 534 | b44_chip_reset(bp); |
| 535 | |
| 536 | - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); |
| 537 | + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name, |
| 538 | + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400"); |
| 539 | for (i = 0; i < 6; i++) |
| 540 | printk("%2.2x%c", dev->dev_addr[i], |
| 541 | i == 5 ? '\n' : ':'); |
| 542 | |
| 543 | + /* Initialize phy */ |
| 544 | + spin_lock_irq(&bp->lock); |
| 545 | + b44_chip_reset(bp); |
| 546 | + spin_unlock_irq(&bp->lock); |
| 547 | + |
| 548 | return 0; |
| 549 | |
| 550 | err_out_iounmap: |
| 551 | --- a/drivers/net/b44.h |
| 552 | +++ b/drivers/net/b44.h |
| 553 | @@ -229,8 +229,6 @@ |
| 554 | #define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */ |
| 555 | #define SBIPSFLAG_ISHIFT4 24 |
| 556 | #define B44_SBTPSFLAG 0x0F18UL /* SB Target Port OCP Slave Flag */ |
| 557 | -#define SBTPS_NUM0_MASK 0x0000003f |
| 558 | -#define SBTPS_F0EN0 0x00000040 |
| 559 | #define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */ |
| 560 | #define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */ |
| 561 | #define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */ |
| 562 | @@ -461,6 +459,8 @@ struct ring_info { |
| 563 | }; |
| 564 | |
| 565 | #define B44_MCAST_TABLE_SIZE 32 |
| 566 | +#define B44_PHY_ADDR_NO_PHY 30 |
| 567 | +#define B44_MDC_RATIO 5000000 |
| 568 | |
| 569 | /* SW copy of device statistics, kept up to date by periodic timer |
| 570 | * which probes HW values. Must have same relative layout as HW |
| 571 | --- a/include/linux/pci_ids.h |
| 572 | +++ b/include/linux/pci_ids.h |
| 573 | @@ -1765,6 +1765,7 @@ |
| 574 | #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e |
| 575 | #define PCI_DEVICE_ID_BCM4401 0x4401 |
| 576 | #define PCI_DEVICE_ID_BCM4401B0 0x4402 |
| 577 | +#define PCI_DEVICE_ID_BCM4713 0x4713 |
| 578 | |
| 579 | #define PCI_VENDOR_ID_ENE 0x1524 |
| 580 | #define PCI_DEVICE_ID_ENE_1211 0x1211 |
| 581 | |
