| 1 | --- a/arch/mips/au1000/common/au1xxx_irqmap.c |
| 2 | +++ b/arch/mips/au1000/common/au1xxx_irqmap.c |
| 3 | @@ -172,14 +172,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { |
| 4 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 5 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 6 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 7 | - { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
| 8 | - { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 9 | - { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 10 | - { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
| 11 | - { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
| 12 | - { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 13 | - { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 14 | - { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
| 15 | + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
| 16 | + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 17 | + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 18 | + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
| 19 | + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
| 20 | + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 21 | + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 22 | + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
| 23 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, |
| 24 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, |
| 25 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
| 26 | @@ -200,14 +200,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { |
| 27 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 28 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 29 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 30 | - { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
| 31 | - { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 32 | - { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 33 | - { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
| 34 | - { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
| 35 | - { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 36 | - { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 37 | - { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
| 38 | + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
| 39 | + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 40 | + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 41 | + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
| 42 | + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
| 43 | + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
| 44 | + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
| 45 | + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
| 46 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, |
| 47 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, |
| 48 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, |
| 49 | --- a/arch/mips/au1000/common/cputable.c |
| 50 | +++ b/arch/mips/au1000/common/cputable.c |
| 51 | @@ -39,7 +39,8 @@ struct cpu_spec cpu_specs[] = { |
| 52 | { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, |
| 53 | { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, |
| 54 | { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, |
| 55 | - { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 }, |
| 56 | + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 }, |
| 57 | + { 0xffffffff, 0x04030201, "Au1200 AC", 0, 0 }, |
| 58 | { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, |
| 59 | }; |
| 60 | |
| 61 | --- a/arch/mips/au1000/common/dbdma.c |
| 62 | +++ b/arch/mips/au1000/common/dbdma.c |
| 63 | @@ -41,6 +41,8 @@ |
| 64 | #include <asm/au1xxx_dbdma.h> |
| 65 | #include <asm/system.h> |
| 66 | |
| 67 | +#include <linux/module.h> |
| 68 | + |
| 69 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
| 70 | |
| 71 | /* |
| 72 | @@ -60,37 +62,10 @@ static spinlock_t au1xxx_dbdma_spin_lock |
| 73 | */ |
| 74 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) |
| 75 | |
| 76 | -static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
| 77 | -static int dbdma_initialized; |
| 78 | +static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
| 79 | +static int dbdma_initialized=0; |
| 80 | static void au1xxx_dbdma_init(void); |
| 81 | |
| 82 | -typedef struct dbdma_device_table { |
| 83 | - u32 dev_id; |
| 84 | - u32 dev_flags; |
| 85 | - u32 dev_tsize; |
| 86 | - u32 dev_devwidth; |
| 87 | - u32 dev_physaddr; /* If FIFO */ |
| 88 | - u32 dev_intlevel; |
| 89 | - u32 dev_intpolarity; |
| 90 | -} dbdev_tab_t; |
| 91 | - |
| 92 | -typedef struct dbdma_chan_config { |
| 93 | - u32 chan_flags; |
| 94 | - u32 chan_index; |
| 95 | - dbdev_tab_t *chan_src; |
| 96 | - dbdev_tab_t *chan_dest; |
| 97 | - au1x_dma_chan_t *chan_ptr; |
| 98 | - au1x_ddma_desc_t *chan_desc_base; |
| 99 | - au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; |
| 100 | - void *chan_callparam; |
| 101 | - void (*chan_callback)(int, void *, struct pt_regs *); |
| 102 | -} chan_tab_t; |
| 103 | - |
| 104 | -#define DEV_FLAGS_INUSE (1 << 0) |
| 105 | -#define DEV_FLAGS_ANYUSE (1 << 1) |
| 106 | -#define DEV_FLAGS_OUT (1 << 2) |
| 107 | -#define DEV_FLAGS_IN (1 << 3) |
| 108 | - |
| 109 | static dbdev_tab_t dbdev_tab[] = { |
| 110 | #ifdef CONFIG_SOC_AU1550 |
| 111 | /* UARTS */ |
| 112 | @@ -156,13 +131,13 @@ static dbdev_tab_t dbdev_tab[] = { |
| 113 | { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 114 | { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 115 | |
| 116 | - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, |
| 117 | - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 118 | - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, |
| 119 | - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 120 | + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, |
| 121 | + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, |
| 122 | + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, |
| 123 | + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, |
| 124 | |
| 125 | - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, |
| 126 | - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 127 | + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, |
| 128 | + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, |
| 129 | |
| 130 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, |
| 131 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, |
| 132 | @@ -172,9 +147,9 @@ static dbdev_tab_t dbdev_tab[] = { |
| 133 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, |
| 134 | { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 135 | |
| 136 | - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 137 | - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 138 | - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 139 | + { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, |
| 140 | + { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, |
| 141 | + { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, |
| 142 | { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 143 | |
| 144 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
| 145 | @@ -183,6 +158,24 @@ static dbdev_tab_t dbdev_tab[] = { |
| 146 | |
| 147 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 148 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
| 149 | + |
| 150 | + /* Provide 16 user definable device types */ |
| 151 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 152 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 153 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 154 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 155 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 156 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 157 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 158 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 159 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 160 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 161 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 162 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 163 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 164 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 165 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 166 | + { 0, 0, 0, 0, 0, 0, 0 }, |
| 167 | }; |
| 168 | |
| 169 | #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) |
| 170 | @@ -202,6 +195,30 @@ find_dbdev_id (u32 id) |
| 171 | return NULL; |
| 172 | } |
| 173 | |
| 174 | +u32 |
| 175 | +au1xxx_ddma_add_device(dbdev_tab_t *dev) |
| 176 | +{ |
| 177 | + u32 ret = 0; |
| 178 | + dbdev_tab_t *p=NULL; |
| 179 | + static u16 new_id=0x1000; |
| 180 | + |
| 181 | + p = find_dbdev_id(0); |
| 182 | + if ( NULL != p ) |
| 183 | + { |
| 184 | + memcpy(p, dev, sizeof(dbdev_tab_t)); |
| 185 | + p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); |
| 186 | + ret = p->dev_id; |
| 187 | + new_id++; |
| 188 | +#if 0 |
| 189 | + printk("add_device: id:%x flags:%x padd:%x\n", |
| 190 | + p->dev_id, p->dev_flags, p->dev_physaddr ); |
| 191 | +#endif |
| 192 | + } |
| 193 | + |
| 194 | + return ret; |
| 195 | +} |
| 196 | +EXPORT_SYMBOL(au1xxx_ddma_add_device); |
| 197 | + |
| 198 | /* Allocate a channel and return a non-zero descriptor if successful. |
| 199 | */ |
| 200 | u32 |
| 201 | @@ -214,7 +231,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 202 | int i; |
| 203 | dbdev_tab_t *stp, *dtp; |
| 204 | chan_tab_t *ctp; |
| 205 | - volatile au1x_dma_chan_t *cp; |
| 206 | + au1x_dma_chan_t *cp; |
| 207 | |
| 208 | /* We do the intialization on the first channel allocation. |
| 209 | * We have to wait because of the interrupt handler initialization |
| 210 | @@ -224,9 +241,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 211 | au1xxx_dbdma_init(); |
| 212 | dbdma_initialized = 1; |
| 213 | |
| 214 | - if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS)) |
| 215 | - return 0; |
| 216 | - |
| 217 | if ((stp = find_dbdev_id(srcid)) == NULL) return 0; |
| 218 | if ((dtp = find_dbdev_id(destid)) == NULL) return 0; |
| 219 | |
| 220 | @@ -268,9 +282,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 221 | /* If kmalloc fails, it is caught below same |
| 222 | * as a channel not available. |
| 223 | */ |
| 224 | - ctp = (chan_tab_t *)kmalloc(sizeof(chan_tab_t), GFP_KERNEL); |
| 225 | + ctp = (chan_tab_t *) |
| 226 | + kmalloc(sizeof(chan_tab_t), GFP_KERNEL); |
| 227 | chan_tab_ptr[i] = ctp; |
| 228 | - ctp->chan_index = chan = i; |
| 229 | break; |
| 230 | } |
| 231 | } |
| 232 | @@ -278,10 +292,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 233 | |
| 234 | if (ctp != NULL) { |
| 235 | memset(ctp, 0, sizeof(chan_tab_t)); |
| 236 | + ctp->chan_index = chan = i; |
| 237 | dcp = DDMA_CHANNEL_BASE; |
| 238 | dcp += (0x0100 * chan); |
| 239 | ctp->chan_ptr = (au1x_dma_chan_t *)dcp; |
| 240 | - cp = (volatile au1x_dma_chan_t *)dcp; |
| 241 | + cp = (au1x_dma_chan_t *)dcp; |
| 242 | ctp->chan_src = stp; |
| 243 | ctp->chan_dest = dtp; |
| 244 | ctp->chan_callback = callback; |
| 245 | @@ -298,6 +313,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 246 | i |= DDMA_CFG_DED; |
| 247 | if (dtp->dev_intpolarity) |
| 248 | i |= DDMA_CFG_DP; |
| 249 | + if ((stp->dev_flags & DEV_FLAGS_SYNC) || |
| 250 | + (dtp->dev_flags & DEV_FLAGS_SYNC)) |
| 251 | + i |= DDMA_CFG_SYNC; |
| 252 | cp->ddma_cfg = i; |
| 253 | au_sync(); |
| 254 | |
| 255 | @@ -308,14 +326,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d |
| 256 | rv = (u32)(&chan_tab_ptr[chan]); |
| 257 | } |
| 258 | else { |
| 259 | - /* Release devices. |
| 260 | - */ |
| 261 | + /* Release devices */ |
| 262 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
| 263 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; |
| 264 | } |
| 265 | } |
| 266 | return rv; |
| 267 | } |
| 268 | +EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); |
| 269 | |
| 270 | /* Set the device width if source or destination is a FIFO. |
| 271 | * Should be 8, 16, or 32 bits. |
| 272 | @@ -343,6 +361,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, in |
| 273 | |
| 274 | return rv; |
| 275 | } |
| 276 | +EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); |
| 277 | |
| 278 | /* Allocate a descriptor ring, initializing as much as possible. |
| 279 | */ |
| 280 | @@ -369,7 +388,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 281 | * and if we try that first we are likely to not waste larger |
| 282 | * slabs of memory. |
| 283 | */ |
| 284 | - desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); |
| 285 | + desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), |
| 286 | + GFP_KERNEL|GFP_DMA); |
| 287 | if (desc_base == 0) |
| 288 | return 0; |
| 289 | |
| 290 | @@ -380,7 +400,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 291 | kfree((const void *)desc_base); |
| 292 | i = entries * sizeof(au1x_ddma_desc_t); |
| 293 | i += (sizeof(au1x_ddma_desc_t) - 1); |
| 294 | - if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) |
| 295 | + if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0) |
| 296 | return 0; |
| 297 | |
| 298 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); |
| 299 | @@ -460,9 +480,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 300 | /* If source input is fifo, set static address. |
| 301 | */ |
| 302 | if (stp->dev_flags & DEV_FLAGS_IN) { |
| 303 | - src0 = stp->dev_physaddr; |
| 304 | - src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
| 305 | + if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) |
| 306 | + src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); |
| 307 | + else |
| 308 | + src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
| 309 | + |
| 310 | } |
| 311 | + if (stp->dev_physaddr) |
| 312 | + src0 = stp->dev_physaddr; |
| 313 | |
| 314 | /* Set up dest1. For now, assume no stride and increment. |
| 315 | * A channel attribute update can change this later. |
| 316 | @@ -486,10 +511,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 317 | /* If destination output is fifo, set static address. |
| 318 | */ |
| 319 | if (dtp->dev_flags & DEV_FLAGS_OUT) { |
| 320 | - dest0 = dtp->dev_physaddr; |
| 321 | + if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE ) |
| 322 | + dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); |
| 323 | + else |
| 324 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); |
| 325 | } |
| 326 | + if (dtp->dev_physaddr) |
| 327 | + dest0 = dtp->dev_physaddr; |
| 328 | |
| 329 | +#if 0 |
| 330 | + printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", |
| 331 | + dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 ); |
| 332 | +#endif |
| 333 | for (i=0; i<entries; i++) { |
| 334 | dp->dscr_cmd0 = cmd0; |
| 335 | dp->dscr_cmd1 = cmd1; |
| 336 | @@ -498,6 +531,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 337 | dp->dscr_dest0 = dest0; |
| 338 | dp->dscr_dest1 = dest1; |
| 339 | dp->dscr_stat = 0; |
| 340 | + dp->sw_context = dp->sw_status = 0; |
| 341 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); |
| 342 | dp++; |
| 343 | } |
| 344 | @@ -510,13 +544,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int |
| 345 | |
| 346 | return (u32)(ctp->chan_desc_base); |
| 347 | } |
| 348 | +EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); |
| 349 | |
| 350 | /* Put a source buffer into the DMA ring. |
| 351 | * This updates the source pointer and byte count. Normally used |
| 352 | * for memory to fifo transfers. |
| 353 | */ |
| 354 | u32 |
| 355 | -au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) |
| 356 | +_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) |
| 357 | { |
| 358 | chan_tab_t *ctp; |
| 359 | au1x_ddma_desc_t *dp; |
| 360 | @@ -543,24 +578,40 @@ au1xxx_dbdma_put_source(u32 chanid, void |
| 361 | */ |
| 362 | dp->dscr_source0 = virt_to_phys(buf); |
| 363 | dp->dscr_cmd1 = nbytes; |
| 364 | - dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
| 365 | - ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ |
| 366 | - |
| 367 | + /* Check flags */ |
| 368 | + if (flags & DDMA_FLAGS_IE) |
| 369 | + dp->dscr_cmd0 |= DSCR_CMD0_IE; |
| 370 | + if (flags & DDMA_FLAGS_NOIE) |
| 371 | + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; |
| 372 | /* Get next descriptor pointer. |
| 373 | */ |
| 374 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
| 375 | |
| 376 | + /* |
| 377 | + * There is an errata on the Au1200/Au1550 parts that could result |
| 378 | + * in "stale" data being DMA'd. It has to do with the snoop logic on |
| 379 | + * the dache eviction buffer. NONCOHERENT_IO is on by default for |
| 380 | + * these parts. If it is fixedin the future, these dma_cache_inv will |
| 381 | + * just be nothing more than empty macros. See io.h. |
| 382 | + * */ |
| 383 | + dma_cache_wback_inv(buf,nbytes); |
| 384 | + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
| 385 | + au_sync(); |
| 386 | + dma_cache_wback_inv(dp, sizeof(dp)); |
| 387 | + ctp->chan_ptr->ddma_dbell = 0; |
| 388 | + |
| 389 | /* return something not zero. |
| 390 | */ |
| 391 | return nbytes; |
| 392 | } |
| 393 | +EXPORT_SYMBOL(_au1xxx_dbdma_put_source); |
| 394 | |
| 395 | /* Put a destination buffer into the DMA ring. |
| 396 | * This updates the destination pointer and byte count. Normally used |
| 397 | * to place an empty buffer into the ring for fifo to memory transfers. |
| 398 | */ |
| 399 | u32 |
| 400 | -au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) |
| 401 | +_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) |
| 402 | { |
| 403 | chan_tab_t *ctp; |
| 404 | au1x_ddma_desc_t *dp; |
| 405 | @@ -582,11 +633,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void * |
| 406 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
| 407 | return 0; |
| 408 | |
| 409 | - /* Load up buffer address and byte count. |
| 410 | - */ |
| 411 | + /* Load up buffer address and byte count */ |
| 412 | + |
| 413 | + /* Check flags */ |
| 414 | + if (flags & DDMA_FLAGS_IE) |
| 415 | + dp->dscr_cmd0 |= DSCR_CMD0_IE; |
| 416 | + if (flags & DDMA_FLAGS_NOIE) |
| 417 | + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; |
| 418 | + |
| 419 | dp->dscr_dest0 = virt_to_phys(buf); |
| 420 | dp->dscr_cmd1 = nbytes; |
| 421 | +#if 0 |
| 422 | + printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", |
| 423 | + dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, |
| 424 | + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 ); |
| 425 | +#endif |
| 426 | + /* |
| 427 | + * There is an errata on the Au1200/Au1550 parts that could result in |
| 428 | + * "stale" data being DMA'd. It has to do with the snoop logic on the |
| 429 | + * dache eviction buffer. NONCOHERENT_IO is on by default for these |
| 430 | + * parts. If it is fixedin the future, these dma_cache_inv will just |
| 431 | + * be nothing more than empty macros. See io.h. |
| 432 | + * */ |
| 433 | + dma_cache_inv(buf,nbytes); |
| 434 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
| 435 | + au_sync(); |
| 436 | + dma_cache_wback_inv(dp, sizeof(dp)); |
| 437 | + ctp->chan_ptr->ddma_dbell = 0; |
| 438 | |
| 439 | /* Get next descriptor pointer. |
| 440 | */ |
| 441 | @@ -596,6 +669,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void * |
| 442 | */ |
| 443 | return nbytes; |
| 444 | } |
| 445 | +EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); |
| 446 | |
| 447 | /* Get a destination buffer into the DMA ring. |
| 448 | * Normally used to get a full buffer from the ring during fifo |
| 449 | @@ -645,7 +719,7 @@ void |
| 450 | au1xxx_dbdma_stop(u32 chanid) |
| 451 | { |
| 452 | chan_tab_t *ctp; |
| 453 | - volatile au1x_dma_chan_t *cp; |
| 454 | + au1x_dma_chan_t *cp; |
| 455 | int halt_timeout = 0; |
| 456 | |
| 457 | ctp = *((chan_tab_t **)chanid); |
| 458 | @@ -665,6 +739,7 @@ au1xxx_dbdma_stop(u32 chanid) |
| 459 | cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); |
| 460 | au_sync(); |
| 461 | } |
| 462 | +EXPORT_SYMBOL(au1xxx_dbdma_stop); |
| 463 | |
| 464 | /* Start using the current descriptor pointer. If the dbdma encounters |
| 465 | * a not valid descriptor, it will stop. In this case, we can just |
| 466 | @@ -674,17 +749,17 @@ void |
| 467 | au1xxx_dbdma_start(u32 chanid) |
| 468 | { |
| 469 | chan_tab_t *ctp; |
| 470 | - volatile au1x_dma_chan_t *cp; |
| 471 | + au1x_dma_chan_t *cp; |
| 472 | |
| 473 | ctp = *((chan_tab_t **)chanid); |
| 474 | - |
| 475 | cp = ctp->chan_ptr; |
| 476 | cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); |
| 477 | cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ |
| 478 | au_sync(); |
| 479 | - cp->ddma_dbell = 0xffffffff; /* Make it go */ |
| 480 | + cp->ddma_dbell = 0; |
| 481 | au_sync(); |
| 482 | } |
| 483 | +EXPORT_SYMBOL(au1xxx_dbdma_start); |
| 484 | |
| 485 | void |
| 486 | au1xxx_dbdma_reset(u32 chanid) |
| 487 | @@ -703,15 +778,21 @@ au1xxx_dbdma_reset(u32 chanid) |
| 488 | |
| 489 | do { |
| 490 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; |
| 491 | + /* reset our SW status -- this is used to determine |
| 492 | + * if a descriptor is in use by upper level SW. Since |
| 493 | + * posting can reset 'V' bit. |
| 494 | + */ |
| 495 | + dp->sw_status = 0; |
| 496 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
| 497 | } while (dp != ctp->chan_desc_base); |
| 498 | } |
| 499 | +EXPORT_SYMBOL(au1xxx_dbdma_reset); |
| 500 | |
| 501 | u32 |
| 502 | au1xxx_get_dma_residue(u32 chanid) |
| 503 | { |
| 504 | chan_tab_t *ctp; |
| 505 | - volatile au1x_dma_chan_t *cp; |
| 506 | + au1x_dma_chan_t *cp; |
| 507 | u32 rv; |
| 508 | |
| 509 | ctp = *((chan_tab_t **)chanid); |
| 510 | @@ -746,15 +827,16 @@ au1xxx_dbdma_chan_free(u32 chanid) |
| 511 | |
| 512 | kfree(ctp); |
| 513 | } |
| 514 | +EXPORT_SYMBOL(au1xxx_dbdma_chan_free); |
| 515 | |
| 516 | static void |
| 517 | dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 518 | { |
| 519 | - u32 intstat; |
| 520 | + u32 intstat, flags; |
| 521 | u32 chan_index; |
| 522 | chan_tab_t *ctp; |
| 523 | au1x_ddma_desc_t *dp; |
| 524 | - volatile au1x_dma_chan_t *cp; |
| 525 | + au1x_dma_chan_t *cp; |
| 526 | |
| 527 | intstat = dbdma_gptr->ddma_intstat; |
| 528 | au_sync(); |
| 529 | @@ -773,18 +855,26 @@ dbdma_interrupt(int irq, void *dev_id, s |
| 530 | (ctp->chan_callback)(irq, ctp->chan_callparam, regs); |
| 531 | |
| 532 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
| 533 | - |
| 534 | } |
| 535 | |
| 536 | -static void |
| 537 | -au1xxx_dbdma_init(void) |
| 538 | +static void au1xxx_dbdma_init(void) |
| 539 | { |
| 540 | + int irq_nr; |
| 541 | + |
| 542 | dbdma_gptr->ddma_config = 0; |
| 543 | dbdma_gptr->ddma_throttle = 0; |
| 544 | dbdma_gptr->ddma_inten = 0xffff; |
| 545 | au_sync(); |
| 546 | |
| 547 | - if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, |
| 548 | +#if defined(CONFIG_SOC_AU1550) |
| 549 | + irq_nr = AU1550_DDMA_INT; |
| 550 | +#elif defined(CONFIG_SOC_AU1200) |
| 551 | + irq_nr = AU1200_DDMA_INT; |
| 552 | +#else |
| 553 | + #error Unknown Au1x00 SOC |
| 554 | +#endif |
| 555 | + |
| 556 | + if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT, |
| 557 | "Au1xxx dbdma", (void *)dbdma_gptr)) |
| 558 | printk("Can't get 1550 dbdma irq"); |
| 559 | } |
| 560 | @@ -795,7 +885,8 @@ au1xxx_dbdma_dump(u32 chanid) |
| 561 | chan_tab_t *ctp; |
| 562 | au1x_ddma_desc_t *dp; |
| 563 | dbdev_tab_t *stp, *dtp; |
| 564 | - volatile au1x_dma_chan_t *cp; |
| 565 | + au1x_dma_chan_t *cp; |
| 566 | + u32 i = 0; |
| 567 | |
| 568 | ctp = *((chan_tab_t **)chanid); |
| 569 | stp = ctp->chan_src; |
| 570 | @@ -820,15 +911,64 @@ au1xxx_dbdma_dump(u32 chanid) |
| 571 | dp = ctp->chan_desc_base; |
| 572 | |
| 573 | do { |
| 574 | - printk("dp %08x, cmd0 %08x, cmd1 %08x\n", |
| 575 | - (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); |
| 576 | - printk("src0 %08x, src1 %08x, dest0 %08x\n", |
| 577 | - dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); |
| 578 | - printk("dest1 %08x, stat %08x, nxtptr %08x\n", |
| 579 | - dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); |
| 580 | + printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", |
| 581 | + i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); |
| 582 | + printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", |
| 583 | + dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); |
| 584 | + printk("stat %08x, nxtptr %08x\n", |
| 585 | + dp->dscr_stat, dp->dscr_nxtptr); |
| 586 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
| 587 | } while (dp != ctp->chan_desc_base); |
| 588 | } |
| 589 | |
| 590 | +/* Put a descriptor into the DMA ring. |
| 591 | + * This updates the source/destination pointers and byte count. |
| 592 | + */ |
| 593 | +u32 |
| 594 | +au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) |
| 595 | +{ |
| 596 | + chan_tab_t *ctp; |
| 597 | + au1x_ddma_desc_t *dp; |
| 598 | + u32 nbytes=0; |
| 599 | + |
| 600 | + /* I guess we could check this to be within the |
| 601 | + * range of the table...... |
| 602 | + */ |
| 603 | + ctp = *((chan_tab_t **)chanid); |
| 604 | + |
| 605 | + /* We should have multiple callers for a particular channel, |
| 606 | + * an interrupt doesn't affect this pointer nor the descriptor, |
| 607 | + * so no locking should be needed. |
| 608 | + */ |
| 609 | + dp = ctp->put_ptr; |
| 610 | + |
| 611 | + /* If the descriptor is valid, we are way ahead of the DMA |
| 612 | + * engine, so just return an error condition. |
| 613 | + */ |
| 614 | + if (dp->dscr_cmd0 & DSCR_CMD0_V) |
| 615 | + return 0; |
| 616 | + |
| 617 | + /* Load up buffer addresses and byte count. |
| 618 | + */ |
| 619 | + dp->dscr_dest0 = dscr->dscr_dest0; |
| 620 | + dp->dscr_source0 = dscr->dscr_source0; |
| 621 | + dp->dscr_dest1 = dscr->dscr_dest1; |
| 622 | + dp->dscr_source1 = dscr->dscr_source1; |
| 623 | + dp->dscr_cmd1 = dscr->dscr_cmd1; |
| 624 | + nbytes = dscr->dscr_cmd1; |
| 625 | + /* Allow the caller to specifiy if an interrupt is generated */ |
| 626 | + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; |
| 627 | + dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; |
| 628 | + ctp->chan_ptr->ddma_dbell = 0; |
| 629 | + |
| 630 | + /* Get next descriptor pointer. |
| 631 | + */ |
| 632 | + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
| 633 | + |
| 634 | + /* return something not zero. |
| 635 | + */ |
| 636 | + return nbytes; |
| 637 | +} |
| 638 | + |
| 639 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |
| 640 | |
| 641 | --- /dev/null |
| 642 | +++ b/arch/mips/au1000/common/gpio.c |
| 643 | @@ -0,0 +1,118 @@ |
| 644 | +/* |
| 645 | + * This program is free software; you can redistribute it and/or modify it |
| 646 | + * under the terms of the GNU General Public License as published by the |
| 647 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 648 | + * option) any later version. |
| 649 | + * |
| 650 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 651 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 652 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 653 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 654 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 655 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 656 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 657 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 658 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 659 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 660 | + * |
| 661 | + * You should have received a copy of the GNU General Public License along |
| 662 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 663 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 664 | + */ |
| 665 | + |
| 666 | +#include <asm/au1000.h> |
| 667 | +#include <asm/au1xxx_gpio.h> |
| 668 | + |
| 669 | +#define gpio1 sys |
| 670 | +#if !defined(CONFIG_SOC_AU1000) |
| 671 | +static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE; |
| 672 | + |
| 673 | +#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 |
| 674 | + |
| 675 | +int au1xxx_gpio2_read(int signal) |
| 676 | +{ |
| 677 | + signal -= 200; |
| 678 | +/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */ |
| 679 | + return ((gpio2->pinstate >> signal) & 0x01); |
| 680 | +} |
| 681 | + |
| 682 | +void au1xxx_gpio2_write(int signal, int value) |
| 683 | +{ |
| 684 | + signal -= 200; |
| 685 | + |
| 686 | + gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | |
| 687 | + (value << signal); |
| 688 | +} |
| 689 | + |
| 690 | +void au1xxx_gpio2_tristate(int signal) |
| 691 | +{ |
| 692 | + signal -= 200; |
| 693 | + gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */ |
| 694 | +} |
| 695 | +#endif |
| 696 | + |
| 697 | +int au1xxx_gpio1_read(int signal) |
| 698 | +{ |
| 699 | +/* gpio1->trioutclr |= (0x01 << signal); */ |
| 700 | + return ((gpio1->pinstaterd >> signal) & 0x01); |
| 701 | +} |
| 702 | + |
| 703 | +void au1xxx_gpio1_write(int signal, int value) |
| 704 | +{ |
| 705 | + if(value) |
| 706 | + gpio1->outputset = (0x01 << signal); |
| 707 | + else |
| 708 | + gpio1->outputclr = (0x01 << signal); /* Output a Zero */ |
| 709 | +} |
| 710 | + |
| 711 | +void au1xxx_gpio1_tristate(int signal) |
| 712 | +{ |
| 713 | + gpio1->trioutclr = (0x01 << signal); /* Tristate signal */ |
| 714 | +} |
| 715 | + |
| 716 | + |
| 717 | +int au1xxx_gpio_read(int signal) |
| 718 | +{ |
| 719 | + if(signal >= 200) |
| 720 | +#if defined(CONFIG_SOC_AU1000) |
| 721 | + return 0; |
| 722 | +#else |
| 723 | + return au1xxx_gpio2_read(signal); |
| 724 | +#endif |
| 725 | + else |
| 726 | + return au1xxx_gpio1_read(signal); |
| 727 | +} |
| 728 | + |
| 729 | +void au1xxx_gpio_write(int signal, int value) |
| 730 | +{ |
| 731 | + if(signal >= 200) |
| 732 | +#if defined(CONFIG_SOC_AU1000) |
| 733 | + ; |
| 734 | +#else |
| 735 | + au1xxx_gpio2_write(signal, value); |
| 736 | +#endif |
| 737 | + else |
| 738 | + au1xxx_gpio1_write(signal, value); |
| 739 | +} |
| 740 | + |
| 741 | +void au1xxx_gpio_tristate(int signal) |
| 742 | +{ |
| 743 | + if(signal >= 200) |
| 744 | +#if defined(CONFIG_SOC_AU1000) |
| 745 | + ; |
| 746 | +#else |
| 747 | + au1xxx_gpio2_tristate(signal); |
| 748 | +#endif |
| 749 | + else |
| 750 | + au1xxx_gpio1_tristate(signal); |
| 751 | +} |
| 752 | + |
| 753 | +void au1xxx_gpio1_set_inputs(void) |
| 754 | +{ |
| 755 | + gpio1->pininputen = 0; |
| 756 | +} |
| 757 | + |
| 758 | +EXPORT_SYMBOL(au1xxx_gpio1_set_inputs); |
| 759 | +EXPORT_SYMBOL(au1xxx_gpio_tristate); |
| 760 | +EXPORT_SYMBOL(au1xxx_gpio_write); |
| 761 | +EXPORT_SYMBOL(au1xxx_gpio_read); |
| 762 | --- a/arch/mips/au1000/common/irq.c |
| 763 | +++ b/arch/mips/au1000/common/irq.c |
| 764 | @@ -303,8 +303,30 @@ static struct hw_interrupt_type level_ir |
| 765 | }; |
| 766 | |
| 767 | #ifdef CONFIG_PM |
| 768 | -void startup_match20_interrupt(void) |
| 769 | +void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *)) |
| 770 | { |
| 771 | + static struct irqaction action; |
| 772 | + /* This is a big problem.... since we didn't use request_irq |
| 773 | + when kernel/irq.c calls probe_irq_xxx this interrupt will |
| 774 | + be probed for usage. This will end up disabling the device :( |
| 775 | + |
| 776 | + Give it a bogus "action" pointer -- this will keep it from |
| 777 | + getting auto-probed! |
| 778 | + |
| 779 | + By setting the status to match that of request_irq() we |
| 780 | + can avoid it. --cgray |
| 781 | + */ |
| 782 | + action.dev_id = handler; |
| 783 | + action.flags = 0; |
| 784 | + action.mask = 0; |
| 785 | + action.name = "Au1xxx TOY"; |
| 786 | + action.handler = handler; |
| 787 | + action.next = NULL; |
| 788 | + |
| 789 | + irq_desc[AU1000_TOY_MATCH2_INT].action = &action; |
| 790 | + irq_desc[AU1000_TOY_MATCH2_INT].status |
| 791 | + &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); |
| 792 | + |
| 793 | local_enable_irq(AU1000_TOY_MATCH2_INT); |
| 794 | } |
| 795 | #endif |
| 796 | @@ -508,6 +530,7 @@ void intc0_req0_irqdispatch(struct pt_re |
| 797 | |
| 798 | if (!intc0_req0) return; |
| 799 | |
| 800 | +#ifdef AU1000_USB_DEV_REQ_INT |
| 801 | /* |
| 802 | * Because of the tight timing of SETUP token to reply |
| 803 | * transactions, the USB devices-side packet complete |
| 804 | @@ -518,6 +541,7 @@ void intc0_req0_irqdispatch(struct pt_re |
| 805 | do_IRQ(AU1000_USB_DEV_REQ_INT, regs); |
| 806 | return; |
| 807 | } |
| 808 | +#endif |
| 809 | |
| 810 | irq = au_ffs(intc0_req0) - 1; |
| 811 | intc0_req0 &= ~(1<<irq); |
| 812 | @@ -536,17 +560,7 @@ void intc0_req1_irqdispatch(struct pt_re |
| 813 | |
| 814 | irq = au_ffs(intc0_req1) - 1; |
| 815 | intc0_req1 &= ~(1<<irq); |
| 816 | -#ifdef CONFIG_PM |
| 817 | - if (irq == AU1000_TOY_MATCH2_INT) { |
| 818 | - mask_and_ack_rise_edge_irq(irq); |
| 819 | - counter0_irq(irq, NULL, regs); |
| 820 | - local_enable_irq(irq); |
| 821 | - } |
| 822 | - else |
| 823 | -#endif |
| 824 | - { |
| 825 | - do_IRQ(irq, regs); |
| 826 | - } |
| 827 | + do_IRQ(irq, regs); |
| 828 | } |
| 829 | |
| 830 | |
| 831 | --- a/arch/mips/au1000/common/Makefile |
| 832 | +++ b/arch/mips/au1000/common/Makefile |
| 833 | @@ -19,9 +19,9 @@ O_TARGET := au1000.o |
| 834 | export-objs = prom.o clocks.o power.o usbdev.o |
| 835 | |
| 836 | obj-y := prom.o int-handler.o irq.o puts.o time.o reset.o cputable.o \ |
| 837 | - au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o |
| 838 | + au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o gpio.o |
| 839 | |
| 840 | -export-objs += dma.o dbdma.o |
| 841 | +export-objs += dma.o dbdma.o gpio.o |
| 842 | |
| 843 | obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o |
| 844 | obj-$(CONFIG_KGDB) += dbg_io.o |
| 845 | --- a/arch/mips/au1000/common/pci_fixup.c |
| 846 | +++ b/arch/mips/au1000/common/pci_fixup.c |
| 847 | @@ -75,9 +75,13 @@ void __init pcibios_fixup(void) |
| 848 | |
| 849 | #ifdef CONFIG_NONCOHERENT_IO |
| 850 | /* |
| 851 | - * Set the NC bit in controller for pre-AC silicon |
| 852 | + * Set the NC bit in controller for Au1500 pre-AC silicon |
| 853 | */ |
| 854 | - au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG); |
| 855 | + u32 prid = read_c0_prid(); |
| 856 | + if ( (prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { |
| 857 | + au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG); |
| 858 | + printk("Non-coherent PCI accesses enabled\n"); |
| 859 | + } |
| 860 | printk("Non-coherent PCI accesses enabled\n"); |
| 861 | #endif |
| 862 | |
| 863 | --- a/arch/mips/au1000/common/pci_ops.c |
| 864 | +++ b/arch/mips/au1000/common/pci_ops.c |
| 865 | @@ -162,6 +162,7 @@ unsigned long last_entryLo0, last_entryL |
| 866 | static int config_access(unsigned char access_type, struct pci_dev *dev, |
| 867 | unsigned char where, u32 * data) |
| 868 | { |
| 869 | + int error = PCIBIOS_SUCCESSFUL; |
| 870 | #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 ) |
| 871 | unsigned char bus = dev->bus->number; |
| 872 | unsigned int dev_fn = dev->devfn; |
| 873 | @@ -170,7 +171,6 @@ static int config_access(unsigned char a |
| 874 | unsigned long offset, status; |
| 875 | unsigned long cfg_base; |
| 876 | unsigned long flags; |
| 877 | - int error = PCIBIOS_SUCCESSFUL; |
| 878 | unsigned long entryLo0, entryLo1; |
| 879 | |
| 880 | if (device > 19) { |
| 881 | @@ -205,9 +205,8 @@ static int config_access(unsigned char a |
| 882 | last_entryLo0 = last_entryLo1 = 0xffffffff; |
| 883 | } |
| 884 | |
| 885 | - /* Since the Au1xxx doesn't do the idsel timing exactly to spec, |
| 886 | - * many board vendors implement their own off-chip idsel, so call |
| 887 | - * it now. If it doesn't succeed, may as well bail out at this point. |
| 888 | + /* Allow board vendors to implement their own off-chip idsel. |
| 889 | + * If it doesn't succeed, may as well bail out at this point. |
| 890 | */ |
| 891 | if (board_pci_idsel) { |
| 892 | if (board_pci_idsel(device, 1) == 0) { |
| 893 | @@ -271,8 +270,11 @@ static int config_access(unsigned char a |
| 894 | } |
| 895 | |
| 896 | local_irq_restore(flags); |
| 897 | - return error; |
| 898 | +#else |
| 899 | + /* Fake out Config space access with no responder */ |
| 900 | + *data = 0xFFFFFFFF; |
| 901 | #endif |
| 902 | + return error; |
| 903 | } |
| 904 | #endif |
| 905 | |
| 906 | --- a/arch/mips/au1000/common/power.c |
| 907 | +++ b/arch/mips/au1000/common/power.c |
| 908 | @@ -50,7 +50,6 @@ |
| 909 | |
| 910 | static void calibrate_delay(void); |
| 911 | |
| 912 | -extern void set_au1x00_speed(unsigned int new_freq); |
| 913 | extern unsigned int get_au1x00_speed(void); |
| 914 | extern unsigned long get_au1x00_uart_baud_base(void); |
| 915 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); |
| 916 | @@ -116,6 +115,7 @@ save_core_regs(void) |
| 917 | sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); |
| 918 | sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); |
| 919 | |
| 920 | +#ifndef CONFIG_SOC_AU1200 |
| 921 | /* Shutdown USB host/device. |
| 922 | */ |
| 923 | sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); |
| 924 | @@ -127,6 +127,7 @@ save_core_regs(void) |
| 925 | |
| 926 | sleep_usbdev_enable = au_readl(USBD_ENABLE); |
| 927 | au_writel(0, USBD_ENABLE); au_sync(); |
| 928 | +#endif |
| 929 | |
| 930 | /* Save interrupt controller state. |
| 931 | */ |
| 932 | @@ -212,14 +213,12 @@ void wakeup_from_suspend(void) |
| 933 | int au_sleep(void) |
| 934 | { |
| 935 | unsigned long wakeup, flags; |
| 936 | - extern void save_and_sleep(void); |
| 937 | + extern unsigned int save_and_sleep(void); |
| 938 | |
| 939 | spin_lock_irqsave(&pm_lock,flags); |
| 940 | |
| 941 | save_core_regs(); |
| 942 | |
| 943 | - flush_cache_all(); |
| 944 | - |
| 945 | /** The code below is all system dependent and we should probably |
| 946 | ** have a function call out of here to set this up. You need |
| 947 | ** to configure the GPIO or timer interrupts that will bring |
| 948 | @@ -227,27 +226,26 @@ int au_sleep(void) |
| 949 | ** For testing, the TOY counter wakeup is useful. |
| 950 | **/ |
| 951 | |
| 952 | -#if 0 |
| 953 | +#if 1 |
| 954 | au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); |
| 955 | |
| 956 | /* gpio 6 can cause a wake up event */ |
| 957 | wakeup = au_readl(SYS_WAKEMSK); |
| 958 | wakeup &= ~(1 << 8); /* turn off match20 wakeup */ |
| 959 | - wakeup |= 1 << 6; /* turn on gpio 6 wakeup */ |
| 960 | + wakeup = 1 << 5; /* turn on gpio 6 wakeup */ |
| 961 | #else |
| 962 | - /* For testing, allow match20 to wake us up. |
| 963 | - */ |
| 964 | + /* For testing, allow match20 to wake us up. */ |
| 965 | #ifdef SLEEP_TEST_TIMEOUT |
| 966 | wakeup_counter0_set(sleep_ticks); |
| 967 | #endif |
| 968 | wakeup = 1 << 8; /* turn on match20 wakeup */ |
| 969 | wakeup = 0; |
| 970 | #endif |
| 971 | - au_writel(1, SYS_WAKESRC); /* clear cause */ |
| 972 | + au_writel(0, SYS_WAKESRC); /* clear cause */ |
| 973 | au_sync(); |
| 974 | au_writel(wakeup, SYS_WAKEMSK); |
| 975 | au_sync(); |
| 976 | - |
| 977 | + DPRINTK("Entering sleep!\n"); |
| 978 | save_and_sleep(); |
| 979 | |
| 980 | /* after a wakeup, the cpu vectors back to 0x1fc00000 so |
| 981 | @@ -255,6 +253,7 @@ int au_sleep(void) |
| 982 | */ |
| 983 | restore_core_regs(); |
| 984 | spin_unlock_irqrestore(&pm_lock, flags); |
| 985 | + DPRINTK("Leaving sleep!\n"); |
| 986 | return 0; |
| 987 | } |
| 988 | |
| 989 | @@ -285,7 +284,6 @@ static int pm_do_sleep(ctl_table * ctl, |
| 990 | |
| 991 | if (retval) |
| 992 | return retval; |
| 993 | - |
| 994 | au_sleep(); |
| 995 | retval = pm_send_all(PM_RESUME, (void *) 0); |
| 996 | } |
| 997 | @@ -296,7 +294,6 @@ static int pm_do_suspend(ctl_table * ctl |
| 998 | void *buffer, size_t * len) |
| 999 | { |
| 1000 | int retval = 0; |
| 1001 | - void au1k_wait(void); |
| 1002 | |
| 1003 | if (!write) { |
| 1004 | *len = 0; |
| 1005 | @@ -305,119 +302,9 @@ static int pm_do_suspend(ctl_table * ctl |
| 1006 | if (retval) |
| 1007 | return retval; |
| 1008 | suspend_mode = 1; |
| 1009 | - au1k_wait(); |
| 1010 | - retval = pm_send_all(PM_RESUME, (void *) 0); |
| 1011 | - } |
| 1012 | - return retval; |
| 1013 | -} |
| 1014 | |
| 1015 | - |
| 1016 | -static int pm_do_freq(ctl_table * ctl, int write, struct file *file, |
| 1017 | - void *buffer, size_t * len) |
| 1018 | -{ |
| 1019 | - int retval = 0, i; |
| 1020 | - unsigned long val, pll; |
| 1021 | -#define TMPBUFLEN 64 |
| 1022 | -#define MAX_CPU_FREQ 396 |
| 1023 | - char buf[TMPBUFLEN], *p; |
| 1024 | - unsigned long flags, intc0_mask, intc1_mask; |
| 1025 | - unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk, |
| 1026 | - old_refresh; |
| 1027 | - unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; |
| 1028 | - |
| 1029 | - spin_lock_irqsave(&pm_lock, flags); |
| 1030 | - if (!write) { |
| 1031 | - *len = 0; |
| 1032 | - } else { |
| 1033 | - /* Parse the new frequency */ |
| 1034 | - if (*len > TMPBUFLEN - 1) { |
| 1035 | - spin_unlock_irqrestore(&pm_lock, flags); |
| 1036 | - return -EFAULT; |
| 1037 | - } |
| 1038 | - if (copy_from_user(buf, buffer, *len)) { |
| 1039 | - spin_unlock_irqrestore(&pm_lock, flags); |
| 1040 | - return -EFAULT; |
| 1041 | - } |
| 1042 | - buf[*len] = 0; |
| 1043 | - p = buf; |
| 1044 | - val = simple_strtoul(p, &p, 0); |
| 1045 | - if (val > MAX_CPU_FREQ) { |
| 1046 | - spin_unlock_irqrestore(&pm_lock, flags); |
| 1047 | - return -EFAULT; |
| 1048 | - } |
| 1049 | - |
| 1050 | - pll = val / 12; |
| 1051 | - if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ |
| 1052 | - /* revisit this for higher speed cpus */ |
| 1053 | - spin_unlock_irqrestore(&pm_lock, flags); |
| 1054 | - return -EFAULT; |
| 1055 | - } |
| 1056 | - |
| 1057 | - old_baud_base = get_au1x00_uart_baud_base(); |
| 1058 | - old_cpu_freq = get_au1x00_speed(); |
| 1059 | - |
| 1060 | - new_cpu_freq = pll * 12 * 1000000; |
| 1061 | - new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); |
| 1062 | - set_au1x00_speed(new_cpu_freq); |
| 1063 | - set_au1x00_uart_baud_base(new_baud_base); |
| 1064 | - |
| 1065 | - old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; |
| 1066 | - new_refresh = |
| 1067 | - ((old_refresh * new_cpu_freq) / |
| 1068 | - old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff); |
| 1069 | - |
| 1070 | - au_writel(pll, SYS_CPUPLL); |
| 1071 | - au_sync_delay(1); |
| 1072 | - au_writel(new_refresh, MEM_SDREFCFG); |
| 1073 | - au_sync_delay(1); |
| 1074 | - |
| 1075 | - for (i = 0; i < 4; i++) { |
| 1076 | - if (au_readl |
| 1077 | - (UART_BASE + UART_MOD_CNTRL + |
| 1078 | - i * 0x00100000) == 3) { |
| 1079 | - old_clk = |
| 1080 | - au_readl(UART_BASE + UART_CLK + |
| 1081 | - i * 0x00100000); |
| 1082 | - // baud_rate = baud_base/clk |
| 1083 | - baud_rate = old_baud_base / old_clk; |
| 1084 | - /* we won't get an exact baud rate and the error |
| 1085 | - * could be significant enough that our new |
| 1086 | - * calculation will result in a clock that will |
| 1087 | - * give us a baud rate that's too far off from |
| 1088 | - * what we really want. |
| 1089 | - */ |
| 1090 | - if (baud_rate > 100000) |
| 1091 | - baud_rate = 115200; |
| 1092 | - else if (baud_rate > 50000) |
| 1093 | - baud_rate = 57600; |
| 1094 | - else if (baud_rate > 30000) |
| 1095 | - baud_rate = 38400; |
| 1096 | - else if (baud_rate > 17000) |
| 1097 | - baud_rate = 19200; |
| 1098 | - else |
| 1099 | - (baud_rate = 9600); |
| 1100 | - // new_clk = new_baud_base/baud_rate |
| 1101 | - new_clk = new_baud_base / baud_rate; |
| 1102 | - au_writel(new_clk, |
| 1103 | - UART_BASE + UART_CLK + |
| 1104 | - i * 0x00100000); |
| 1105 | - au_sync_delay(10); |
| 1106 | - } |
| 1107 | - } |
| 1108 | + retval = pm_send_all(PM_RESUME, (void *) 0); |
| 1109 | } |
| 1110 | - |
| 1111 | - |
| 1112 | - /* We don't want _any_ interrupts other than |
| 1113 | - * match20. Otherwise our calibrate_delay() |
| 1114 | - * calculation will be off, potentially a lot. |
| 1115 | - */ |
| 1116 | - intc0_mask = save_local_and_disable(0); |
| 1117 | - intc1_mask = save_local_and_disable(1); |
| 1118 | - local_enable_irq(AU1000_TOY_MATCH2_INT); |
| 1119 | - spin_unlock_irqrestore(&pm_lock, flags); |
| 1120 | - calibrate_delay(); |
| 1121 | - restore_local_and_enable(0, intc0_mask); |
| 1122 | - restore_local_and_enable(1, intc1_mask); |
| 1123 | return retval; |
| 1124 | } |
| 1125 | |
| 1126 | @@ -425,7 +312,6 @@ static int pm_do_freq(ctl_table * ctl, i |
| 1127 | static struct ctl_table pm_table[] = { |
| 1128 | {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend}, |
| 1129 | {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep}, |
| 1130 | - {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq}, |
| 1131 | {0} |
| 1132 | }; |
| 1133 | |
| 1134 | --- a/arch/mips/au1000/common/reset.c |
| 1135 | +++ b/arch/mips/au1000/common/reset.c |
| 1136 | @@ -37,8 +37,6 @@ |
| 1137 | #include <asm/system.h> |
| 1138 | #include <asm/au1000.h> |
| 1139 | |
| 1140 | -extern int au_sleep(void); |
| 1141 | - |
| 1142 | void au1000_restart(char *command) |
| 1143 | { |
| 1144 | /* Set all integrated peripherals to disabled states */ |
| 1145 | @@ -144,6 +142,26 @@ void au1000_restart(char *command) |
| 1146 | au_writel(0x00, 0xb1900064); /* sys_auxpll */ |
| 1147 | au_writel(0x00, 0xb1900100); /* sys_pininputen */ |
| 1148 | break; |
| 1149 | + case 0x04000000: /* Au1200 */ |
| 1150 | + au_writel(0x00, 0xb400300c); /* ddma */ |
| 1151 | + au_writel(0x00, 0xb1a00004); /* psc 0 */ |
| 1152 | + au_writel(0x00, 0xb1b00004); /* psc 1 */ |
| 1153 | + au_writel(0x00d02000, 0xb4020004); /* ehci, ohci, udc, otg */ |
| 1154 | + au_writel(0x00, 0xb5000004); /* lcd */ |
| 1155 | + au_writel(0x00, 0xb060000c); /* sd0 */ |
| 1156 | + au_writel(0x00, 0xb068000c); /* sd1 */ |
| 1157 | + au_writel(0x00, 0xb1100100); /* swcnt */ |
| 1158 | + au_writel(0x00, 0xb0300000); /* aes */ |
| 1159 | + au_writel(0x00, 0xb4004000); /* cim */ |
| 1160 | + au_writel(0x00, 0xb1100100); /* uart0_enable */ |
| 1161 | + au_writel(0x00, 0xb1200100); /* uart1_enable */ |
| 1162 | + au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */ |
| 1163 | + au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */ |
| 1164 | + au_writel(0x00, 0xb1900028); /* sys_clksrc */ |
| 1165 | + au_writel(0x10, 0xb1900060); /* sys_cpupll */ |
| 1166 | + au_writel(0x00, 0xb1900064); /* sys_auxpll */ |
| 1167 | + au_writel(0x00, 0xb1900100); /* sys_pininputen */ |
| 1168 | + break; |
| 1169 | |
| 1170 | default: |
| 1171 | break; |
| 1172 | @@ -163,32 +181,23 @@ void au1000_restart(char *command) |
| 1173 | |
| 1174 | void au1000_halt(void) |
| 1175 | { |
| 1176 | -#if defined(CONFIG_MIPS_PB1550) |
| 1177 | - /* power off system */ |
| 1178 | - printk("\n** Powering off Pb1550\n"); |
| 1179 | - au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C); |
| 1180 | - au_sync(); |
| 1181 | - while(1); /* should not get here */ |
| 1182 | -#endif |
| 1183 | - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); |
| 1184 | -#ifdef CONFIG_MIPS_MIRAGE |
| 1185 | - au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); |
| 1186 | -#endif |
| 1187 | -#ifdef CONFIG_PM |
| 1188 | - au_sleep(); |
| 1189 | - |
| 1190 | - /* should not get here */ |
| 1191 | - printk(KERN_ERR "Unable to put cpu in sleep mode\n"); |
| 1192 | - while(1); |
| 1193 | -#else |
| 1194 | - while (1) |
| 1195 | + /* Use WAIT in a low-power infinite spin loop */ |
| 1196 | + while (1) { |
| 1197 | __asm__(".set\tmips3\n\t" |
| 1198 | "wait\n\t" |
| 1199 | ".set\tmips0"); |
| 1200 | -#endif |
| 1201 | + } |
| 1202 | } |
| 1203 | |
| 1204 | void au1000_power_off(void) |
| 1205 | { |
| 1206 | + extern void board_power_off (void); |
| 1207 | + |
| 1208 | + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); |
| 1209 | + |
| 1210 | + /* Give board a chance to power-off */ |
| 1211 | + board_power_off(); |
| 1212 | + |
| 1213 | + /* If board can't power-off, spin forever */ |
| 1214 | au1000_halt(); |
| 1215 | } |
| 1216 | --- a/arch/mips/au1000/common/setup.c |
| 1217 | +++ b/arch/mips/au1000/common/setup.c |
| 1218 | @@ -174,6 +174,40 @@ void __init au1x00_setup(void) |
| 1219 | initrd_end = (unsigned long)&__rd_end; |
| 1220 | #endif |
| 1221 | |
| 1222 | +#if defined(CONFIG_SOC_AU1200) |
| 1223 | +#ifdef CONFIG_USB_EHCI_HCD |
| 1224 | + if ((argptr = strstr(argptr, "usb_ehci=")) == NULL) { |
| 1225 | + char usb_args[80]; |
| 1226 | + argptr = prom_getcmdline(); |
| 1227 | + memset(usb_args, 0, sizeof(usb_args)); |
| 1228 | + sprintf(usb_args, " usb_ehci=base:0x%x,len:0x%x,irq:%d", |
| 1229 | + USB_EHCI_BASE, USB_EHCI_LEN, AU1000_USB_HOST_INT); |
| 1230 | + strcat(argptr, usb_args); |
| 1231 | + } |
| 1232 | +#ifdef CONFIG_USB_AMD5536UDC |
| 1233 | + /* enable EHC + OHC + UDC clocks, memory and bus mastering */ |
| 1234 | +/* au_writel( 0x00DF207F, USB_MSR_BASE + 4); */ |
| 1235 | + au_writel( 0xC0DF207F, USB_MSR_BASE + 4); // incl. prefetch |
| 1236 | +#else |
| 1237 | + /* enable EHC + OHC clocks, memory and bus mastering */ |
| 1238 | +/* au_writel( 0x00DB200F, USB_MSR_BASE + 4); */ |
| 1239 | + au_writel( 0xC0DB200F, USB_MSR_BASE + 4); /* incl. prefetch */ |
| 1240 | +#endif |
| 1241 | + udelay(1000); |
| 1242 | + |
| 1243 | +#else /* CONFIG_USB_EHCI_HCD */ |
| 1244 | + |
| 1245 | +#ifdef CONFIG_USB_AMD5536UDC |
| 1246 | +#ifndef CONFIG_USB_OHCI |
| 1247 | + /* enable UDC clocks, memory and bus mastering */ |
| 1248 | +/* au_writel( 0x00DC2070, USB_MSR_BASE + 4); */ |
| 1249 | + au_writel( 0xC0DC2070, USB_MSR_BASE + 4); // incl. prefetch |
| 1250 | + udelay(1000); |
| 1251 | +#endif |
| 1252 | +#endif |
| 1253 | +#endif /* CONFIG_USB_EHCI_HCD */ |
| 1254 | +#endif /* CONFIG_SOC_AU1200 */ |
| 1255 | + |
| 1256 | #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) |
| 1257 | #ifdef CONFIG_USB_OHCI |
| 1258 | if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { |
| 1259 | @@ -187,19 +221,38 @@ void __init au1x00_setup(void) |
| 1260 | #endif |
| 1261 | |
| 1262 | #ifdef CONFIG_USB_OHCI |
| 1263 | - // enable host controller and wait for reset done |
| 1264 | +#if defined(CONFIG_SOC_AU1200) |
| 1265 | +#ifndef CONFIG_USB_EHCI_HCD |
| 1266 | +#ifdef CONFIG_USB_AMD5536UDC |
| 1267 | + /* enable OHC + UDC clocks, memory and bus mastering */ |
| 1268 | +/* au_writel( 0x00DD2073, USB_MSR_BASE + 4); */ |
| 1269 | + au_writel( 0xC0DD2073, USB_MSR_BASE + 4); // incl. prefetch |
| 1270 | +#else |
| 1271 | + /* enable OHC clocks, memory and bus mastering */ |
| 1272 | + au_writel( 0x00D12003, USB_MSR_BASE + 4); |
| 1273 | +#endif |
| 1274 | + udelay(1000); |
| 1275 | +printk("DEBUG: Reading Au1200 USB2 reg 0x%x\n", au_readl(USB_MSR_BASE + 4)); |
| 1276 | +#endif |
| 1277 | +#else |
| 1278 | + /* Au1000, Au1500, Au1100, Au1550 */ |
| 1279 | + /* enable host controller and wait for reset done */ |
| 1280 | au_writel(0x08, USB_HOST_CONFIG); |
| 1281 | udelay(1000); |
| 1282 | au_writel(0x0E, USB_HOST_CONFIG); |
| 1283 | udelay(1000); |
| 1284 | - au_readl(USB_HOST_CONFIG); // throw away first read |
| 1285 | + au_readl(USB_HOST_CONFIG); /* throw away first read */ |
| 1286 | while (!(au_readl(USB_HOST_CONFIG) & 0x10)) |
| 1287 | au_readl(USB_HOST_CONFIG); |
| 1288 | +#endif /* CONFIG_SOC_AU1200 */ |
| 1289 | #endif |
| 1290 | -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) |
| 1291 | +#else |
| 1292 | + |
| 1293 | +#endif /* defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) */ |
| 1294 | + |
| 1295 | |
| 1296 | #ifdef CONFIG_FB |
| 1297 | - // Needed if PCI video card in use |
| 1298 | + /* Needed if PCI video card in use */ |
| 1299 | conswitchp = &dummy_con; |
| 1300 | #endif |
| 1301 | |
| 1302 | @@ -209,8 +262,7 @@ void __init au1x00_setup(void) |
| 1303 | #endif |
| 1304 | |
| 1305 | #ifdef CONFIG_BLK_DEV_IDE |
| 1306 | - /* Board setup takes precedence for unique devices. |
| 1307 | - */ |
| 1308 | + /* Board setup takes precedence for unique devices. */ |
| 1309 | if ((ide_ops == NULL) || (ide_ops == &no_ide_ops)) |
| 1310 | ide_ops = &std_ide_ops; |
| 1311 | #endif |
| 1312 | --- a/arch/mips/au1000/common/sleeper.S |
| 1313 | +++ b/arch/mips/au1000/common/sleeper.S |
| 1314 | @@ -15,17 +15,48 @@ |
| 1315 | #include <asm/addrspace.h> |
| 1316 | #include <asm/regdef.h> |
| 1317 | #include <asm/stackframe.h> |
| 1318 | +#include <asm/au1000.h> |
| 1319 | + |
| 1320 | +/* |
| 1321 | + * Note: This file is *not* conditional on CONFIG_PM since Alchemy sleep |
| 1322 | + * need not be tied to any particular power management scheme. |
| 1323 | + */ |
| 1324 | + |
| 1325 | + .extern ___flush_cache_all |
| 1326 | |
| 1327 | .text |
| 1328 | - .set macro |
| 1329 | - .set noat |
| 1330 | .align 5 |
| 1331 | |
| 1332 | -/* Save all of the processor general registers and go to sleep. |
| 1333 | - * A wakeup condition will get us back here to restore the registers. |
| 1334 | +/* |
| 1335 | + * Save the processor general registers and go to sleep. A wakeup |
| 1336 | + * condition will get us back here to restore the registers. |
| 1337 | */ |
| 1338 | -LEAF(save_and_sleep) |
| 1339 | |
| 1340 | +/* still need to fix alignment issues here */ |
| 1341 | +save_and_sleep_frmsz = 48 |
| 1342 | +NESTED(save_and_sleep, save_and_sleep_frmsz, ra) |
| 1343 | + .set noreorder |
| 1344 | + .set nomacro |
| 1345 | + .set noat |
| 1346 | + subu sp, save_and_sleep_frmsz |
| 1347 | + sw ra, save_and_sleep_frmsz-4(sp) |
| 1348 | + sw s0, save_and_sleep_frmsz-8(sp) |
| 1349 | + sw s1, save_and_sleep_frmsz-12(sp) |
| 1350 | + sw s2, save_and_sleep_frmsz-16(sp) |
| 1351 | + sw s3, save_and_sleep_frmsz-20(sp) |
| 1352 | + sw s4, save_and_sleep_frmsz-24(sp) |
| 1353 | + sw s5, save_and_sleep_frmsz-28(sp) |
| 1354 | + sw s6, save_and_sleep_frmsz-32(sp) |
| 1355 | + sw s7, save_and_sleep_frmsz-36(sp) |
| 1356 | + sw s8, save_and_sleep_frmsz-40(sp) |
| 1357 | + sw gp, save_and_sleep_frmsz-44(sp) |
| 1358 | + |
| 1359 | + /* We only need to save the registers that the calling function |
| 1360 | + * hasn't saved for us. 0 is always zero. 8 - 15, 24 and 25 are |
| 1361 | + * temporaries and can be used without saving. 26 and 27 are reserved |
| 1362 | + * for interrupt/trap handling and expected to change. 29 is the |
| 1363 | + * stack pointer which is handled as a special case here. |
| 1364 | + */ |
| 1365 | subu sp, PT_SIZE |
| 1366 | sw $1, PT_R1(sp) |
| 1367 | sw $2, PT_R2(sp) |
| 1368 | @@ -34,14 +65,6 @@ LEAF(save_and_sleep) |
| 1369 | sw $5, PT_R5(sp) |
| 1370 | sw $6, PT_R6(sp) |
| 1371 | sw $7, PT_R7(sp) |
| 1372 | - sw $8, PT_R8(sp) |
| 1373 | - sw $9, PT_R9(sp) |
| 1374 | - sw $10, PT_R10(sp) |
| 1375 | - sw $11, PT_R11(sp) |
| 1376 | - sw $12, PT_R12(sp) |
| 1377 | - sw $13, PT_R13(sp) |
| 1378 | - sw $14, PT_R14(sp) |
| 1379 | - sw $15, PT_R15(sp) |
| 1380 | sw $16, PT_R16(sp) |
| 1381 | sw $17, PT_R17(sp) |
| 1382 | sw $18, PT_R18(sp) |
| 1383 | @@ -50,32 +73,47 @@ LEAF(save_and_sleep) |
| 1384 | sw $21, PT_R21(sp) |
| 1385 | sw $22, PT_R22(sp) |
| 1386 | sw $23, PT_R23(sp) |
| 1387 | - sw $24, PT_R24(sp) |
| 1388 | - sw $25, PT_R25(sp) |
| 1389 | - sw $26, PT_R26(sp) |
| 1390 | - sw $27, PT_R27(sp) |
| 1391 | sw $28, PT_R28(sp) |
| 1392 | - sw $29, PT_R29(sp) |
| 1393 | sw $30, PT_R30(sp) |
| 1394 | sw $31, PT_R31(sp) |
| 1395 | +#define PT_C0STATUS PT_LO |
| 1396 | +#define PT_CONTEXT PT_HI |
| 1397 | +#define PT_PAGEMASK PT_EPC |
| 1398 | +#define PT_CONFIG PT_BVADDR |
| 1399 | mfc0 k0, CP0_STATUS |
| 1400 | - sw k0, 0x20(sp) |
| 1401 | + sw k0, PT_C0STATUS(sp) // 0x20 |
| 1402 | mfc0 k0, CP0_CONTEXT |
| 1403 | - sw k0, 0x1c(sp) |
| 1404 | + sw k0, PT_CONTEXT(sp) // 0x1c |
| 1405 | mfc0 k0, CP0_PAGEMASK |
| 1406 | - sw k0, 0x18(sp) |
| 1407 | + sw k0, PT_PAGEMASK(sp) // 0x18 |
| 1408 | mfc0 k0, CP0_CONFIG |
| 1409 | - sw k0, 0x14(sp) |
| 1410 | + sw k0, PT_CONFIG(sp) // 0x14 |
| 1411 | + |
| 1412 | + .set macro |
| 1413 | + .set at |
| 1414 | + |
| 1415 | + li t0, SYS_SLPPWR |
| 1416 | + sw zero, 0(t0) /* Get the processor ready to sleep */ |
| 1417 | + sync |
| 1418 | |
| 1419 | /* Now set up the scratch registers so the boot rom will |
| 1420 | * return to this point upon wakeup. |
| 1421 | + * sys_scratch0 : SP |
| 1422 | + * sys_scratch1 : RA |
| 1423 | + */ |
| 1424 | + li t0, SYS_SCRATCH0 |
| 1425 | + li t1, SYS_SCRATCH1 |
| 1426 | + sw sp, 0(t0) |
| 1427 | + la k0, resume_from_sleep |
| 1428 | + sw k0, 0(t1) |
| 1429 | + |
| 1430 | +/* |
| 1431 | + * Flush DCACHE to make sure context is in memory |
| 1432 | */ |
| 1433 | - la k0, 1f |
| 1434 | - lui k1, 0xb190 |
| 1435 | - ori k1, 0x18 |
| 1436 | - sw sp, 0(k1) |
| 1437 | - ori k1, 0x1c |
| 1438 | - sw k0, 0(k1) |
| 1439 | + la t1,___flush_cache_all /* _flush_cache_all is a function pointer */ |
| 1440 | + lw t0,0(t1) |
| 1441 | + jal t0 |
| 1442 | + nop |
| 1443 | |
| 1444 | /* Put SDRAM into self refresh. Preload instructions into cache, |
| 1445 | * issue a precharge, then auto refresh, then sleep commands to it. |
| 1446 | @@ -88,30 +126,65 @@ LEAF(save_and_sleep) |
| 1447 | cache 0x14, 96(t0) |
| 1448 | .set mips0 |
| 1449 | |
| 1450 | + /* Put SDRAM to sleep */ |
| 1451 | sdsleep: |
| 1452 | - lui k0, 0xb400 |
| 1453 | - sw zero, 0x001c(k0) /* Precharge */ |
| 1454 | - sw zero, 0x0020(k0) /* Auto refresh */ |
| 1455 | - sw zero, 0x0030(k0) /* SDRAM sleep */ |
| 1456 | + li a0, MEM_PHYS_ADDR |
| 1457 | + or a0, a0, 0xA0000000 |
| 1458 | +#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500) |
| 1459 | + lw k0, MEM_SDMODE0(a0) |
| 1460 | + sw zero, MEM_SDPRECMD(a0) /* Precharge */ |
| 1461 | + sw zero, MEM_SDAUTOREF(a0) /* Auto Refresh */ |
| 1462 | + sw zero, MEM_SDSLEEP(a0) /* Sleep */ |
| 1463 | sync |
| 1464 | - |
| 1465 | - lui k1, 0xb190 |
| 1466 | - sw zero, 0x0078(k1) /* get ready to sleep */ |
| 1467 | +#endif |
| 1468 | +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
| 1469 | + sw zero, MEM_SDPRECMD(a0) /* Precharge */ |
| 1470 | + sw zero, MEM_SDSREF(a0) |
| 1471 | + |
| 1472 | + #lw t0, MEM_SDSTAT(a0) |
| 1473 | + #and t0, t0, 0x01000000 |
| 1474 | + li t0, 0x01000000 |
| 1475 | +refresh_not_set: |
| 1476 | + lw t1, MEM_SDSTAT(a0) |
| 1477 | + and t2, t1, t0 |
| 1478 | + beq zero, t2, refresh_not_set |
| 1479 | + nop |
| 1480 | + |
| 1481 | + li t0, ~0x30000000 |
| 1482 | + lw t1, MEM_SDCONFIGA(a0) |
| 1483 | + and t1, t0, t1 |
| 1484 | + sw t1, MEM_SDCONFIGA(a0) |
| 1485 | sync |
| 1486 | - sw zero, 0x007c(k1) /* Put processor to sleep */ |
| 1487 | +#endif |
| 1488 | + |
| 1489 | + li t0, SYS_SLEEP |
| 1490 | + sw zero, 0(t0) /* Put processor to sleep */ |
| 1491 | sync |
| 1492 | + nop |
| 1493 | + nop |
| 1494 | + nop |
| 1495 | + nop |
| 1496 | + nop |
| 1497 | + nop |
| 1498 | + nop |
| 1499 | + nop |
| 1500 | + |
| 1501 | |
| 1502 | /* This is where we return upon wakeup. |
| 1503 | * Reload all of the registers and return. |
| 1504 | */ |
| 1505 | -1: nop |
| 1506 | - lw k0, 0x20(sp) |
| 1507 | +resume_from_sleep: |
| 1508 | + nop |
| 1509 | + .set nomacro |
| 1510 | + .set noat |
| 1511 | + |
| 1512 | + lw k0, PT_C0STATUS(sp) // 0x20 |
| 1513 | mtc0 k0, CP0_STATUS |
| 1514 | - lw k0, 0x1c(sp) |
| 1515 | + lw k0, PT_CONTEXT(sp) // 0x1c |
| 1516 | mtc0 k0, CP0_CONTEXT |
| 1517 | - lw k0, 0x18(sp) |
| 1518 | + lw k0, PT_PAGEMASK(sp) // 0x18 |
| 1519 | mtc0 k0, CP0_PAGEMASK |
| 1520 | - lw k0, 0x14(sp) |
| 1521 | + lw k0, PT_CONFIG(sp) // 0x14 |
| 1522 | mtc0 k0, CP0_CONFIG |
| 1523 | lw $1, PT_R1(sp) |
| 1524 | lw $2, PT_R2(sp) |
| 1525 | @@ -120,14 +193,6 @@ sdsleep: |
| 1526 | lw $5, PT_R5(sp) |
| 1527 | lw $6, PT_R6(sp) |
| 1528 | lw $7, PT_R7(sp) |
| 1529 | - lw $8, PT_R8(sp) |
| 1530 | - lw $9, PT_R9(sp) |
| 1531 | - lw $10, PT_R10(sp) |
| 1532 | - lw $11, PT_R11(sp) |
| 1533 | - lw $12, PT_R12(sp) |
| 1534 | - lw $13, PT_R13(sp) |
| 1535 | - lw $14, PT_R14(sp) |
| 1536 | - lw $15, PT_R15(sp) |
| 1537 | lw $16, PT_R16(sp) |
| 1538 | lw $17, PT_R17(sp) |
| 1539 | lw $18, PT_R18(sp) |
| 1540 | @@ -136,15 +201,36 @@ sdsleep: |
| 1541 | lw $21, PT_R21(sp) |
| 1542 | lw $22, PT_R22(sp) |
| 1543 | lw $23, PT_R23(sp) |
| 1544 | - lw $24, PT_R24(sp) |
| 1545 | - lw $25, PT_R25(sp) |
| 1546 | - lw $26, PT_R26(sp) |
| 1547 | - lw $27, PT_R27(sp) |
| 1548 | lw $28, PT_R28(sp) |
| 1549 | - lw $29, PT_R29(sp) |
| 1550 | lw $30, PT_R30(sp) |
| 1551 | lw $31, PT_R31(sp) |
| 1552 | + |
| 1553 | + .set macro |
| 1554 | + .set at |
| 1555 | + |
| 1556 | + /* clear the wake source, but save it as the return value of the function */ |
| 1557 | + li t0, SYS_WAKESRC |
| 1558 | + lw v0, 0(t0) |
| 1559 | + sw v0, PT_R2(sp) |
| 1560 | + sw zero, 0(t0) |
| 1561 | + |
| 1562 | addiu sp, PT_SIZE |
| 1563 | |
| 1564 | + lw gp, save_and_sleep_frmsz-44(sp) |
| 1565 | + lw s8, save_and_sleep_frmsz-40(sp) |
| 1566 | + lw s7, save_and_sleep_frmsz-36(sp) |
| 1567 | + lw s6, save_and_sleep_frmsz-32(sp) |
| 1568 | + lw s5, save_and_sleep_frmsz-28(sp) |
| 1569 | + lw s4, save_and_sleep_frmsz-24(sp) |
| 1570 | + lw s3, save_and_sleep_frmsz-20(sp) |
| 1571 | + lw s2, save_and_sleep_frmsz-16(sp) |
| 1572 | + lw s1, save_and_sleep_frmsz-12(sp) |
| 1573 | + lw s0, save_and_sleep_frmsz-8(sp) |
| 1574 | + lw ra, save_and_sleep_frmsz-4(sp) |
| 1575 | + |
| 1576 | + addu sp, save_and_sleep_frmsz |
| 1577 | jr ra |
| 1578 | + nop |
| 1579 | + .set reorder |
| 1580 | END(save_and_sleep) |
| 1581 | + |
| 1582 | --- a/arch/mips/au1000/common/time.c |
| 1583 | +++ b/arch/mips/au1000/common/time.c |
| 1584 | @@ -50,7 +50,6 @@ |
| 1585 | #include <linux/mc146818rtc.h> |
| 1586 | #include <linux/timex.h> |
| 1587 | |
| 1588 | -extern void startup_match20_interrupt(void); |
| 1589 | extern void do_softirq(void); |
| 1590 | extern volatile unsigned long wall_jiffies; |
| 1591 | unsigned long missed_heart_beats = 0; |
| 1592 | @@ -59,14 +58,14 @@ static unsigned long r4k_offset; /* Amou |
| 1593 | static unsigned long r4k_cur; /* What counter should be at next timer irq */ |
| 1594 | extern rwlock_t xtime_lock; |
| 1595 | int no_au1xxx_32khz; |
| 1596 | -void (*au1k_wait_ptr)(void); |
| 1597 | +extern int allow_au1k_wait; /* default off for CP0 Counter */ |
| 1598 | |
| 1599 | /* Cycle counter value at the previous timer interrupt.. */ |
| 1600 | static unsigned int timerhi = 0, timerlo = 0; |
| 1601 | |
| 1602 | #ifdef CONFIG_PM |
| 1603 | #define MATCH20_INC 328 |
| 1604 | -extern void startup_match20_interrupt(void); |
| 1605 | +extern void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *)); |
| 1606 | static unsigned long last_pc0, last_match20; |
| 1607 | #endif |
| 1608 | |
| 1609 | @@ -385,7 +384,6 @@ void __init au1xxx_timer_setup(void) |
| 1610 | { |
| 1611 | unsigned int est_freq; |
| 1612 | extern unsigned long (*do_gettimeoffset)(void); |
| 1613 | - extern void au1k_wait(void); |
| 1614 | |
| 1615 | printk("calculating r4koff... "); |
| 1616 | r4k_offset = cal_r4koff(); |
| 1617 | @@ -437,9 +435,6 @@ void __init au1xxx_timer_setup(void) |
| 1618 | au_writel(0, SYS_TOYWRITE); |
| 1619 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); |
| 1620 | |
| 1621 | - au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK); |
| 1622 | - au_writel(~0, SYS_WAKESRC); |
| 1623 | - au_sync(); |
| 1624 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); |
| 1625 | |
| 1626 | /* setup match20 to interrupt once every 10ms */ |
| 1627 | @@ -447,13 +442,13 @@ void __init au1xxx_timer_setup(void) |
| 1628 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); |
| 1629 | au_sync(); |
| 1630 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); |
| 1631 | - startup_match20_interrupt(); |
| 1632 | + startup_match20_interrupt(counter0_irq); |
| 1633 | |
| 1634 | do_gettimeoffset = do_fast_pm_gettimeoffset; |
| 1635 | |
| 1636 | /* We can use the real 'wait' instruction. |
| 1637 | */ |
| 1638 | - au1k_wait_ptr = au1k_wait; |
| 1639 | + allow_au1k_wait = 1; |
| 1640 | } |
| 1641 | |
| 1642 | #else |
| 1643 | --- a/arch/mips/au1000/db1x00/board_setup.c |
| 1644 | +++ b/arch/mips/au1000/db1x00/board_setup.c |
| 1645 | @@ -46,10 +46,22 @@ |
| 1646 | #include <asm/au1000.h> |
| 1647 | #include <asm/db1x00.h> |
| 1648 | |
| 1649 | -extern struct rtc_ops no_rtc_ops; |
| 1650 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) && defined(CONFIG_MIPS_DB1550) |
| 1651 | +#include <asm/au1xxx_dbdma.h> |
| 1652 | +extern struct ide_ops *ide_ops; |
| 1653 | +extern struct ide_ops au1xxx_ide_ops; |
| 1654 | +extern u32 au1xxx_ide_virtbase; |
| 1655 | +extern u64 au1xxx_ide_physbase; |
| 1656 | +extern int au1xxx_ide_irq; |
| 1657 | + |
| 1658 | +/* Ddma */ |
| 1659 | +chan_tab_t *ide_read_ch, *ide_write_ch; |
| 1660 | +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma |
| 1661 | + |
| 1662 | +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }; |
| 1663 | +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */ |
| 1664 | |
| 1665 | -/* not correct for db1550 */ |
| 1666 | -static BCSR * const bcsr = (BCSR *)0xAE000000; |
| 1667 | +extern struct rtc_ops no_rtc_ops; |
| 1668 | |
| 1669 | void board_reset (void) |
| 1670 | { |
| 1671 | @@ -57,6 +69,13 @@ void board_reset (void) |
| 1672 | au_writel(0x00000000, 0xAE00001C); |
| 1673 | } |
| 1674 | |
| 1675 | +void board_power_off (void) |
| 1676 | +{ |
| 1677 | +#ifdef CONFIG_MIPS_MIRAGE |
| 1678 | + au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); |
| 1679 | +#endif |
| 1680 | +} |
| 1681 | + |
| 1682 | void __init board_setup(void) |
| 1683 | { |
| 1684 | u32 pin_func; |
| 1685 | @@ -108,8 +127,42 @@ void __init board_setup(void) |
| 1686 | au_writel(0x02000200, GPIO2_OUTPUT); |
| 1687 | #endif |
| 1688 | |
| 1689 | +#if defined(CONFIG_AU1XXX_SMC91111) |
| 1690 | +#define CPLD_CONTROL (0xAF00000C) |
| 1691 | + { |
| 1692 | + extern uint32_t au1xxx_smc91111_base; |
| 1693 | + extern unsigned int au1xxx_smc91111_irq; |
| 1694 | + extern int au1xxx_smc91111_nowait; |
| 1695 | + |
| 1696 | + au1xxx_smc91111_base = 0xAC000300; |
| 1697 | + au1xxx_smc91111_irq = AU1000_GPIO_8; |
| 1698 | + au1xxx_smc91111_nowait = 1; |
| 1699 | + |
| 1700 | + /* set up the Static Bus timing - only 396Mhz */ |
| 1701 | + bcsr->resets |= 0x7; |
| 1702 | + au_writel(0x00010003, MEM_STCFG0); |
| 1703 | + au_writel(0x000c00c0, MEM_STCFG2); |
| 1704 | + au_writel(0x85E1900D, MEM_STTIME2); |
| 1705 | + } |
| 1706 | +#endif /* end CONFIG_SMC91111 */ |
| 1707 | au_sync(); |
| 1708 | |
| 1709 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) && defined(CONFIG_MIPS_DB1550) |
| 1710 | + /* |
| 1711 | + * Iniz IDE parameters |
| 1712 | + */ |
| 1713 | + ide_ops = &au1xxx_ide_ops; |
| 1714 | + au1xxx_ide_irq = DAUGHTER_CARD_IRQ; |
| 1715 | + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR; |
| 1716 | + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR); |
| 1717 | + |
| 1718 | + /* |
| 1719 | + * change PIO or PIO+Ddma |
| 1720 | + * check the GPIO-6 pin condition. db1550:s6_dot |
| 1721 | + */ |
| 1722 | + switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 6)) ? 1 : 0; |
| 1723 | +#endif |
| 1724 | + |
| 1725 | #ifdef CONFIG_MIPS_DB1000 |
| 1726 | printk("AMD Alchemy Au1000/Db1000 Board\n"); |
| 1727 | #endif |
| 1728 | --- a/arch/mips/au1000/db1x00/irqmap.c |
| 1729 | +++ b/arch/mips/au1000/db1x00/irqmap.c |
| 1730 | @@ -53,6 +53,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { |
| 1731 | #ifdef CONFIG_MIPS_DB1550 |
| 1732 | { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 IRQ# |
| 1733 | { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 1 IRQ# |
| 1734 | + { AU1000_GPIO_8, INTC_INT_LOW_LEVEL, 0 }, // Daughtercard IRQ# |
| 1735 | #else |
| 1736 | { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 Fully_Interted# |
| 1737 | { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 STSCHG# |
| 1738 | --- a/arch/mips/au1000/db1x00/Makefile |
| 1739 | +++ b/arch/mips/au1000/db1x00/Makefile |
| 1740 | @@ -17,4 +17,11 @@ O_TARGET := db1x00.o |
| 1741 | obj-y := init.o board_setup.o irqmap.o |
| 1742 | obj-$(CONFIG_WM97XX_COMODULE) += mirage_ts.o |
| 1743 | |
| 1744 | +ifdef CONFIG_MIPS_DB1100 |
| 1745 | +ifdef CONFIG_MMC |
| 1746 | +obj-y += mmc_support.o |
| 1747 | +export-objs += mmc_support.o |
| 1748 | +endif |
| 1749 | +endif |
| 1750 | + |
| 1751 | include $(TOPDIR)/Rules.make |
| 1752 | --- /dev/null |
| 1753 | +++ b/arch/mips/au1000/db1x00/mmc_support.c |
| 1754 | @@ -0,0 +1,126 @@ |
| 1755 | +/* |
| 1756 | + * BRIEF MODULE DESCRIPTION |
| 1757 | + * |
| 1758 | + * MMC support routines for DB1100. |
| 1759 | + * |
| 1760 | + * |
| 1761 | + * Copyright (c) 2003-2004 Embedded Edge, LLC. |
| 1762 | + * Author: Embedded Edge, LLC. |
| 1763 | + * Contact: dan@embeddededge.com |
| 1764 | + * |
| 1765 | + * This program is free software; you can redistribute it and/or modify it |
| 1766 | + * under the terms of the GNU General Public License as published by the |
| 1767 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 1768 | + * option) any later version. |
| 1769 | + * |
| 1770 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 1771 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 1772 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 1773 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 1774 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 1775 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 1776 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 1777 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 1778 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 1779 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 1780 | + * |
| 1781 | + * You should have received a copy of the GNU General Public License along |
| 1782 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 1783 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 1784 | + * |
| 1785 | + */ |
| 1786 | + |
| 1787 | + |
| 1788 | +#include <linux/config.h> |
| 1789 | +#include <linux/kernel.h> |
| 1790 | +#include <linux/module.h> |
| 1791 | +#include <linux/init.h> |
| 1792 | + |
| 1793 | +#include <asm/irq.h> |
| 1794 | +#include <asm/au1000.h> |
| 1795 | +#include <asm/au1100_mmc.h> |
| 1796 | +#include <asm/db1x00.h> |
| 1797 | + |
| 1798 | + |
| 1799 | +/* SD/MMC controller support functions */ |
| 1800 | + |
| 1801 | +/* |
| 1802 | + * Detect card. |
| 1803 | + */ |
| 1804 | +void mmc_card_inserted(int _n_, int *_res_) |
| 1805 | +{ |
| 1806 | + u32 gpios = au_readl(SYS_PINSTATERD); |
| 1807 | + u32 emptybit = (_n_) ? (1<<20) : (1<<19); |
| 1808 | + *_res_ = ((gpios & emptybit) == 0); |
| 1809 | +} |
| 1810 | + |
| 1811 | +/* |
| 1812 | + * Check card write protection. |
| 1813 | + */ |
| 1814 | +void mmc_card_writable(int _n_, int *_res_) |
| 1815 | +{ |
| 1816 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 1817 | + unsigned long mmc_wp, board_specific; |
| 1818 | + |
| 1819 | + if (_n_) { |
| 1820 | + mmc_wp = BCSR_BOARD_SD1_WP; |
| 1821 | + } else { |
| 1822 | + mmc_wp = BCSR_BOARD_SD0_WP; |
| 1823 | + } |
| 1824 | + |
| 1825 | + board_specific = au_readl((unsigned long)(&bcsr->specific)); |
| 1826 | + |
| 1827 | + if (!(board_specific & mmc_wp)) {/* low means card writable */ |
| 1828 | + *_res_ = 1; |
| 1829 | + } else { |
| 1830 | + *_res_ = 0; |
| 1831 | + } |
| 1832 | +} |
| 1833 | + |
| 1834 | +/* |
| 1835 | + * Apply power to card slot. |
| 1836 | + */ |
| 1837 | +void mmc_power_on(int _n_) |
| 1838 | +{ |
| 1839 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 1840 | + unsigned long mmc_pwr, board_specific; |
| 1841 | + |
| 1842 | + if (_n_) { |
| 1843 | + mmc_pwr = BCSR_BOARD_SD1_PWR; |
| 1844 | + } else { |
| 1845 | + mmc_pwr = BCSR_BOARD_SD0_PWR; |
| 1846 | + } |
| 1847 | + |
| 1848 | + board_specific = au_readl((unsigned long)(&bcsr->specific)); |
| 1849 | + board_specific |= mmc_pwr; |
| 1850 | + |
| 1851 | + au_writel(board_specific, (int)(&bcsr->specific)); |
| 1852 | + au_sync_delay(1); |
| 1853 | +} |
| 1854 | + |
| 1855 | +/* |
| 1856 | + * Remove power from card slot. |
| 1857 | + */ |
| 1858 | +void mmc_power_off(int _n_) |
| 1859 | +{ |
| 1860 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 1861 | + unsigned long mmc_pwr, board_specific; |
| 1862 | + |
| 1863 | + if (_n_) { |
| 1864 | + mmc_pwr = BCSR_BOARD_SD1_PWR; |
| 1865 | + } else { |
| 1866 | + mmc_pwr = BCSR_BOARD_SD0_PWR; |
| 1867 | + } |
| 1868 | + |
| 1869 | + board_specific = au_readl((unsigned long)(&bcsr->specific)); |
| 1870 | + board_specific &= ~mmc_pwr; |
| 1871 | + |
| 1872 | + au_writel(board_specific, (int)(&bcsr->specific)); |
| 1873 | + au_sync_delay(1); |
| 1874 | +} |
| 1875 | + |
| 1876 | +EXPORT_SYMBOL(mmc_card_inserted); |
| 1877 | +EXPORT_SYMBOL(mmc_card_writable); |
| 1878 | +EXPORT_SYMBOL(mmc_power_on); |
| 1879 | +EXPORT_SYMBOL(mmc_power_off); |
| 1880 | + |
| 1881 | --- /dev/null |
| 1882 | +++ b/arch/mips/au1000/ficmmp/au1200_ibutton.c |
| 1883 | @@ -0,0 +1,270 @@ |
| 1884 | +/* ---------------------------------------------------------------------- |
| 1885 | + * mtwilson_keys.c |
| 1886 | + * |
| 1887 | + * Copyright (C) 2003 Intrinsyc Software Inc. |
| 1888 | + * |
| 1889 | + * Intel Personal Media Player buttons |
| 1890 | + * |
| 1891 | + * This program is free software; you can redistribute it and/or modify |
| 1892 | + * it under the terms of the GNU General Public License version 2 as |
| 1893 | + * published by the Free Software Foundation. |
| 1894 | + * |
| 1895 | + * May 02, 2003 : Initial version [FB] |
| 1896 | + * |
| 1897 | + ------------------------------------------------------------------------*/ |
| 1898 | + |
| 1899 | +#include <linux/config.h> |
| 1900 | +#include <linux/module.h> |
| 1901 | +#include <linux/kernel.h> |
| 1902 | +#include <linux/init.h> |
| 1903 | +#include <linux/fs.h> |
| 1904 | +#include <linux/sched.h> |
| 1905 | +#include <linux/miscdevice.h> |
| 1906 | +#include <linux/errno.h> |
| 1907 | +#include <linux/poll.h> |
| 1908 | +#include <linux/delay.h> |
| 1909 | +#include <linux/input.h> |
| 1910 | + |
| 1911 | +#include <asm/au1000.h> |
| 1912 | +#include <asm/uaccess.h> |
| 1913 | +#include <asm/au1xxx_gpio.h> |
| 1914 | +#include <asm/irq.h> |
| 1915 | +#include <asm/keyboard.h> |
| 1916 | +#include <linux/time.h> |
| 1917 | + |
| 1918 | +#define DRIVER_VERSION "V1.0" |
| 1919 | +#define DRIVER_AUTHOR "FIC" |
| 1920 | +#define DRIVER_DESC "FIC Travis Media Player Button Driver" |
| 1921 | +#define DRIVER_NAME "Au1200Button" |
| 1922 | + |
| 1923 | +#define BUTTON_MAIN (1<<1) |
| 1924 | +#define BUTTON_SELECT (1<<6) |
| 1925 | +#define BUTTON_GUIDE (1<<12) |
| 1926 | +#define BUTTON_DOWN (1<<17) |
| 1927 | +#define BUTTON_LEFT (1<<19) |
| 1928 | +#define BUTTON_RIGHT (1<<26) |
| 1929 | +#define BUTTON_UP (1<<28) |
| 1930 | + |
| 1931 | +#define BUTTON_MASK (\ |
| 1932 | + BUTTON_MAIN \ |
| 1933 | + | BUTTON_SELECT \ |
| 1934 | + | BUTTON_GUIDE \ |
| 1935 | + | BUTTON_DOWN \ |
| 1936 | + | BUTTON_LEFT \ |
| 1937 | + | BUTTON_RIGHT \ |
| 1938 | + | BUTTON_UP \ |
| 1939 | + ) |
| 1940 | + |
| 1941 | +#define BUTTON_INVERT (\ |
| 1942 | + BUTTON_MAIN \ |
| 1943 | + | 0 \ |
| 1944 | + | BUTTON_GUIDE \ |
| 1945 | + | 0 \ |
| 1946 | + | 0 \ |
| 1947 | + | 0 \ |
| 1948 | + | 0 \ |
| 1949 | + ) |
| 1950 | + |
| 1951 | +char button_map[32]={0,KEY_S,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0}; |
| 1952 | +//char button_map[32]={0,0,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0}; |
| 1953 | + |
| 1954 | +//char button_map[32]={0,KEY_TAB,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0}; |
| 1955 | +//char button_map[32]={0,0,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0}; |
| 1956 | + |
| 1957 | +#define BUTTON_COUNT (sizeof (button_map) / sizeof (button_map[0])) |
| 1958 | + |
| 1959 | +struct input_dev dev; |
| 1960 | +struct timeval cur_tv; |
| 1961 | + |
| 1962 | +static unsigned int old_tv_usec = 0; |
| 1963 | + |
| 1964 | +static unsigned int read_button_state(void) |
| 1965 | +{ |
| 1966 | + unsigned int state; |
| 1967 | + |
| 1968 | + state = au_readl(SYS_PINSTATERD) & BUTTON_MASK; /* get gpio status */ |
| 1969 | + |
| 1970 | + state ^= BUTTON_INVERT; /* invert main & guide button */ |
| 1971 | + |
| 1972 | + /* printk("au1200_ibutton.c: button state [0x%X]\r\n",state); */ |
| 1973 | + return state; |
| 1974 | +} |
| 1975 | + |
| 1976 | +//This function returns 0 if the allowed microseconds have elapsed since the last call to ths function, otherwise it returns 1 to indicate a bounce condition |
| 1977 | +static unsigned int bounce() |
| 1978 | +{ |
| 1979 | + |
| 1980 | + unsigned int elapsed_time; |
| 1981 | + |
| 1982 | + do_gettimeofday (&cur_tv); |
| 1983 | + |
| 1984 | + if (!old_tv_usec) { |
| 1985 | + old_tv_usec = cur_tv.tv_usec; |
| 1986 | + return 0; |
| 1987 | + } |
| 1988 | + |
| 1989 | + if(cur_tv.tv_usec > old_tv_usec) { |
| 1990 | + /* If there hasn't been rollover */ |
| 1991 | + elapsed_time = ((cur_tv.tv_usec - old_tv_usec)); |
| 1992 | + } |
| 1993 | + else { |
| 1994 | + /* Accounting for rollover */ |
| 1995 | + elapsed_time = ((1000000 - old_tv_usec + cur_tv.tv_usec)); |
| 1996 | + } |
| 1997 | + |
| 1998 | + if (elapsed_time > 250000) { |
| 1999 | + old_tv_usec = 0; /* reset the bounce time */ |
| 2000 | + return 0; |
| 2001 | + } |
| 2002 | + |
| 2003 | + return 1; |
| 2004 | +} |
| 2005 | + |
| 2006 | +/* button interrupt handler */ |
| 2007 | +static void button_interrupt(int irq, void *dev, struct pt_regs *regs) |
| 2008 | +{ |
| 2009 | + |
| 2010 | + unsigned int i,bit_mask, key_choice; |
| 2011 | + u32 button_state; |
| 2012 | + |
| 2013 | + /* Report state to upper level */ |
| 2014 | + |
| 2015 | + button_state = read_button_state() & BUTTON_MASK; /* get new gpio status */ |
| 2016 | + |
| 2017 | + /* Return if this is a repeated (bouncing) event */ |
| 2018 | + if(bounce()) |
| 2019 | + return; |
| 2020 | + |
| 2021 | + /* we want to make keystrokes */ |
| 2022 | + for( i=0; i< BUTTON_COUNT; i++) { |
| 2023 | + bit_mask = 1<<i; |
| 2024 | + if (button_state & bit_mask) { |
| 2025 | + key_choice = button_map[i]; |
| 2026 | + /* toggle key down */ |
| 2027 | + input_report_key(dev, key_choice, 1); |
| 2028 | + /* toggle key up */ |
| 2029 | + input_report_key(dev, key_choice, 0); |
| 2030 | + printk("ibutton gpio %d stat %x scan code %d\r\n", |
| 2031 | + i, button_state, key_choice); |
| 2032 | + /* Only report the first key event; it doesn't make |
| 2033 | + * sense for two keys to be pressed at the same time, |
| 2034 | + * and causes problems with the directional keys |
| 2035 | + * return; |
| 2036 | + */ |
| 2037 | + } |
| 2038 | + } |
| 2039 | +} |
| 2040 | + |
| 2041 | +static int |
| 2042 | +button_translate(unsigned char scancode, unsigned char *keycode, char raw_mode) |
| 2043 | +{ |
| 2044 | + static int prev_scancode; |
| 2045 | + |
| 2046 | + printk( "ibutton.c: translate: scancode=%x raw_mode=%x\n", |
| 2047 | + scancode, raw_mode); |
| 2048 | + |
| 2049 | + if (scancode == 0xe0 || scancode == 0xe1) { |
| 2050 | + prev_scancode = scancode; |
| 2051 | + return 0; |
| 2052 | + } |
| 2053 | + |
| 2054 | + if (scancode == 0x00 || scancode == 0xff) { |
| 2055 | + prev_scancode = 0; |
| 2056 | + return 0; |
| 2057 | + } |
| 2058 | + |
| 2059 | + *keycode = scancode; |
| 2060 | + |
| 2061 | + return 1; |
| 2062 | +} |
| 2063 | + |
| 2064 | +/* init button hardware */ |
| 2065 | +static int button_hw_init(void) |
| 2066 | +{ |
| 2067 | + unsigned int ipinfunc=0; |
| 2068 | + |
| 2069 | + printk("au1200_ibutton.c: Initializing buttons hardware\n"); |
| 2070 | + |
| 2071 | + // initialize GPIO pin function assignments |
| 2072 | + |
| 2073 | + ipinfunc = au_readl(SYS_PINFUNC); |
| 2074 | + |
| 2075 | + ipinfunc &= ~(SYS_PINFUNC_DMA | SYS_PINFUNC_S0A | SYS_PINFUNC_S0B); |
| 2076 | + au_writel( ipinfunc ,SYS_PINFUNC); |
| 2077 | + |
| 2078 | + ipinfunc |= (SYS_PINFUNC_S0C); |
| 2079 | + au_writel( ipinfunc ,SYS_PINFUNC); |
| 2080 | + |
| 2081 | + return 0; |
| 2082 | +} |
| 2083 | + |
| 2084 | +/* button driver init */ |
| 2085 | +static int __init button_init(void) |
| 2086 | +{ |
| 2087 | + int ret, i; |
| 2088 | + unsigned int flag=0; |
| 2089 | + |
| 2090 | + printk("au1200_ibutton.c: button_init()\r\n"); |
| 2091 | + |
| 2092 | + button_hw_init(); |
| 2093 | + |
| 2094 | + /* register all button irq handler */ |
| 2095 | + |
| 2096 | + for(i=0; i< sizeof(button_map)/sizeof(button_map[0]); i++) |
| 2097 | + { |
| 2098 | + /* register irq <-- gpio 1 ,6 ,12 , 17 ,19 , 26 ,28 */ |
| 2099 | + if(button_map[i] != 0) |
| 2100 | + { |
| 2101 | + ret = request_irq(AU1000_GPIO_0 + i , |
| 2102 | + &button_interrupt , SA_INTERRUPT , |
| 2103 | + DRIVER_NAME , &dev); |
| 2104 | + if(ret) flag |= 1<<i; |
| 2105 | + } |
| 2106 | + } |
| 2107 | + |
| 2108 | + printk("au1200_ibutton.c: request_irq,ret:0x%x\r\n",ret); |
| 2109 | + |
| 2110 | + if (ret) { |
| 2111 | + printk("au1200_ibutton.c: request_irq:%X failed\r\n",flag); |
| 2112 | + return ret; |
| 2113 | + } |
| 2114 | + |
| 2115 | + dev.name = DRIVER_NAME; |
| 2116 | + dev.evbit[0] = BIT(EV_KEY) | BIT(EV_REP); |
| 2117 | + |
| 2118 | + for (i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++) |
| 2119 | + { |
| 2120 | + dev.keybit[LONG(button_map[i])] |= BIT(button_map[i]); |
| 2121 | + } |
| 2122 | + |
| 2123 | + input_register_device(&dev); |
| 2124 | + |
| 2125 | + /* ready to receive interrupts */ |
| 2126 | + |
| 2127 | + return 0; |
| 2128 | +} |
| 2129 | + |
| 2130 | +/* button driver exit */ |
| 2131 | +static void __exit button_exit(void) |
| 2132 | +{ |
| 2133 | + int i; |
| 2134 | + |
| 2135 | + for(i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++) |
| 2136 | + { |
| 2137 | + if(button_map[i] != 0) |
| 2138 | + { |
| 2139 | + free_irq( AU1000_GPIO_0 + i, &dev); |
| 2140 | + } |
| 2141 | + } |
| 2142 | + |
| 2143 | + input_unregister_device(&dev); |
| 2144 | + |
| 2145 | + printk("au1200_ibutton.c: button_exit()\r\n"); |
| 2146 | +} |
| 2147 | + |
| 2148 | +module_init(button_init); |
| 2149 | +module_exit(button_exit); |
| 2150 | + |
| 2151 | +MODULE_AUTHOR( DRIVER_AUTHOR ); |
| 2152 | +MODULE_DESCRIPTION( DRIVER_DESC ); |
| 2153 | +MODULE_LICENSE("GPL"); |
| 2154 | --- /dev/null |
| 2155 | +++ b/arch/mips/au1000/ficmmp/au1xxx_dock.c |
| 2156 | @@ -0,0 +1,261 @@ |
| 2157 | +/* |
| 2158 | + * Copyright (C) 2003 Metrowerks, All Rights Reserved. |
| 2159 | + * |
| 2160 | + * This program is free software; you can redistribute it and/or modify |
| 2161 | + * it under the terms of the GNU General Public License version 2 as |
| 2162 | + * published by the Free Software Foundation. |
| 2163 | + */ |
| 2164 | + |
| 2165 | +#include <linux/config.h> |
| 2166 | +#include <linux/module.h> |
| 2167 | +#include <linux/init.h> |
| 2168 | +#include <linux/fs.h> |
| 2169 | +#include <linux/sched.h> |
| 2170 | +#include <linux/miscdevice.h> |
| 2171 | +#include <linux/errno.h> |
| 2172 | +#include <linux/poll.h> |
| 2173 | +#include <asm/au1000.h> |
| 2174 | +#include <asm/uaccess.h> |
| 2175 | +#include <asm/au1xxx_gpio.h> |
| 2176 | + |
| 2177 | + |
| 2178 | +#if defined(CONFIG_MIPS_FICMMP) |
| 2179 | + #define DOCK_GPIO 215 |
| 2180 | +#else |
| 2181 | + #error Unsupported Au1xxx Platform |
| 2182 | +#endif |
| 2183 | + |
| 2184 | +#define MAKE_FLAG 0x20 |
| 2185 | + |
| 2186 | +#undef DEBUG |
| 2187 | + |
| 2188 | +#define DEBUG 0 |
| 2189 | +//#define DEBUG 1 |
| 2190 | + |
| 2191 | +#if DEBUG |
| 2192 | +#define DPRINTK(format, args...) printk(__FUNCTION__ ": " format, ## args) |
| 2193 | +#else |
| 2194 | +#define DPRINTK(format, args...) do { } while (0) |
| 2195 | +#endif |
| 2196 | + |
| 2197 | +/* Please note that this driver is based on a timer and is not interrupt |
| 2198 | + * driven. If you are going to make use of this driver, you will need to have |
| 2199 | + * your application open the dock listing from the /dev directory first. |
| 2200 | + */ |
| 2201 | + |
| 2202 | +struct au1xxx_dock { |
| 2203 | + struct fasync_struct *fasync; |
| 2204 | + wait_queue_head_t read_wait; |
| 2205 | + int open_count; |
| 2206 | + unsigned int debounce; |
| 2207 | + unsigned int current; |
| 2208 | + unsigned int last; |
| 2209 | +}; |
| 2210 | + |
| 2211 | +static struct au1xxx_dock dock_info; |
| 2212 | + |
| 2213 | + |
| 2214 | +static void dock_timer_periodic(void *data); |
| 2215 | + |
| 2216 | +static struct tq_struct dock_task = { |
| 2217 | + routine: dock_timer_periodic, |
| 2218 | + data: NULL |
| 2219 | +}; |
| 2220 | + |
| 2221 | +static int cleanup_flag = 0; |
| 2222 | +static DECLARE_WAIT_QUEUE_HEAD(cleanup_wait_queue); |
| 2223 | + |
| 2224 | + |
| 2225 | +static unsigned int read_dock_state(void) |
| 2226 | +{ |
| 2227 | + u32 state; |
| 2228 | + |
| 2229 | + state = au1xxx_gpio_read(DOCK_GPIO); |
| 2230 | + |
| 2231 | + /* printk( "Current Dock State: %d\n", state ); */ |
| 2232 | + |
| 2233 | + return state; |
| 2234 | +} |
| 2235 | + |
| 2236 | + |
| 2237 | +static void dock_timer_periodic(void *data) |
| 2238 | +{ |
| 2239 | + struct au1xxx_dock *dock = (struct au1xxx_dock *)data; |
| 2240 | + unsigned long dock_state; |
| 2241 | + |
| 2242 | + /* If cleanup wants us to die */ |
| 2243 | + if (cleanup_flag) { |
| 2244 | + /* now cleanup_module can return */ |
| 2245 | + wake_up(&cleanup_wait_queue); |
| 2246 | + } else { |
| 2247 | + /* put ourselves back in the task queue */ |
| 2248 | + queue_task(&dock_task, &tq_timer); |
| 2249 | + } |
| 2250 | + |
| 2251 | + /* read current dock */ |
| 2252 | + dock_state = read_dock_state(); |
| 2253 | + |
| 2254 | + /* if dock states hasn't changed */ |
| 2255 | + /* save time and be done. */ |
| 2256 | + if (dock_state == dock->current) { |
| 2257 | + return; |
| 2258 | + } |
| 2259 | + |
| 2260 | + if (dock_state == dock->debounce) { |
| 2261 | + dock->current = dock_state; |
| 2262 | + } else { |
| 2263 | + dock->debounce = dock_state; |
| 2264 | + } |
| 2265 | + if (dock->current != dock->last) { |
| 2266 | + if (waitqueue_active(&dock->read_wait)) { |
| 2267 | + wake_up_interruptible(&dock->read_wait); |
| 2268 | + } |
| 2269 | + } |
| 2270 | +} |
| 2271 | + |
| 2272 | + |
| 2273 | +static ssize_t au1xxx_dock_read(struct file *filp, char *buffer, size_t count, loff_t *ppos) |
| 2274 | +{ |
| 2275 | + struct au1xxx_dock *dock = filp->private_data; |
| 2276 | + char event[3]; |
| 2277 | + int last; |
| 2278 | + int cur; |
| 2279 | + int err; |
| 2280 | + |
| 2281 | +try_again: |
| 2282 | + |
| 2283 | + while (dock->current == dock->last) { |
| 2284 | + if (filp->f_flags & O_NONBLOCK) { |
| 2285 | + return -EAGAIN; |
| 2286 | + } |
| 2287 | + interruptible_sleep_on(&dock->read_wait); |
| 2288 | + if (signal_pending(current)) { |
| 2289 | + return -ERESTARTSYS; |
| 2290 | + } |
| 2291 | + } |
| 2292 | + |
| 2293 | + cur = dock->current; |
| 2294 | + last = dock->last; |
| 2295 | + |
| 2296 | + if(cur != last) |
| 2297 | + { |
| 2298 | + event[0] = cur ? 'D' : 'U'; |
| 2299 | + event[1] = '\r'; |
| 2300 | + event[2] = '\n'; |
| 2301 | + } |
| 2302 | + else |
| 2303 | + goto try_again; |
| 2304 | + |
| 2305 | + dock->last = cur; |
| 2306 | + err = copy_to_user(buffer, &event, 3); |
| 2307 | + if (err) { |
| 2308 | + return err; |
| 2309 | + } |
| 2310 | + |
| 2311 | + return 3; |
| 2312 | +} |
| 2313 | + |
| 2314 | + |
| 2315 | +static int au1xxx_dock_open(struct inode *inode, struct file *filp) |
| 2316 | +{ |
| 2317 | + struct au1xxx_dock *dock = &dock_info; |
| 2318 | + |
| 2319 | + MOD_INC_USE_COUNT; |
| 2320 | + |
| 2321 | + filp->private_data = dock; |
| 2322 | + |
| 2323 | + if (dock->open_count++ == 0) { |
| 2324 | + dock_task.data = dock; |
| 2325 | + cleanup_flag = 0; |
| 2326 | + queue_task(&dock_task, &tq_timer); |
| 2327 | + } |
| 2328 | + |
| 2329 | + return 0; |
| 2330 | +} |
| 2331 | + |
| 2332 | + |
| 2333 | +static unsigned int au1xxx_dock_poll(struct file *filp, poll_table *wait) |
| 2334 | +{ |
| 2335 | + struct au1xxx_dock *dock = filp->private_data; |
| 2336 | + int ret = 0; |
| 2337 | + |
| 2338 | + DPRINTK("start\n"); |
| 2339 | + poll_wait(filp, &dock->read_wait, wait); |
| 2340 | + if (dock->current != dock->last) { |
| 2341 | + ret = POLLIN | POLLRDNORM; |
| 2342 | + } |
| 2343 | + return ret; |
| 2344 | +} |
| 2345 | + |
| 2346 | + |
| 2347 | +static int au1xxx_dock_release(struct inode *inode, struct file *filp) |
| 2348 | +{ |
| 2349 | + struct au1xxx_dock *dock = filp->private_data; |
| 2350 | + |
| 2351 | + DPRINTK("start\n"); |
| 2352 | + |
| 2353 | + if (--dock->open_count == 0) { |
| 2354 | + cleanup_flag = 1; |
| 2355 | + sleep_on(&cleanup_wait_queue); |
| 2356 | + } |
| 2357 | + MOD_DEC_USE_COUNT; |
| 2358 | + |
| 2359 | + return 0; |
| 2360 | +} |
| 2361 | + |
| 2362 | + |
| 2363 | + |
| 2364 | +static struct file_operations au1xxx_dock_fops = { |
| 2365 | + owner: THIS_MODULE, |
| 2366 | + read: au1xxx_dock_read, |
| 2367 | + poll: au1xxx_dock_poll, |
| 2368 | + open: au1xxx_dock_open, |
| 2369 | + release: au1xxx_dock_release, |
| 2370 | +}; |
| 2371 | + |
| 2372 | +/* |
| 2373 | + * The au1xxx dock is a misc device: |
| 2374 | + * Major 10 char |
| 2375 | + * Minor 22 /dev/dock |
| 2376 | + * |
| 2377 | + * This is /dev/misc/dock if devfs is used. |
| 2378 | + */ |
| 2379 | + |
| 2380 | +static struct miscdevice au1xxx_dock_dev = { |
| 2381 | + minor: 23, |
| 2382 | + name: "dock", |
| 2383 | + fops: &au1xxx_dock_fops, |
| 2384 | +}; |
| 2385 | + |
| 2386 | +static int __init au1xxx_dock_init(void) |
| 2387 | +{ |
| 2388 | + struct au1xxx_dock *dock = &dock_info; |
| 2389 | + int ret; |
| 2390 | + |
| 2391 | + DPRINTK("Initializing dock driver\n"); |
| 2392 | + dock->open_count = 0; |
| 2393 | + cleanup_flag = 0; |
| 2394 | + init_waitqueue_head(&dock->read_wait); |
| 2395 | + |
| 2396 | + |
| 2397 | + /* yamon configures GPIO pins for the dock |
| 2398 | + * no initialization needed |
| 2399 | + */ |
| 2400 | + |
| 2401 | + ret = misc_register(&au1xxx_dock_dev); |
| 2402 | + |
| 2403 | + DPRINTK("dock driver fully initialized.\n"); |
| 2404 | + |
| 2405 | + return ret; |
| 2406 | +} |
| 2407 | + |
| 2408 | + |
| 2409 | +static void __exit au1xxx_dock_exit(void) |
| 2410 | +{ |
| 2411 | + DPRINTK("unloading dock driver\n"); |
| 2412 | + misc_deregister(&au1xxx_dock_dev); |
| 2413 | +} |
| 2414 | + |
| 2415 | + |
| 2416 | +module_init(au1xxx_dock_init); |
| 2417 | +module_exit(au1xxx_dock_exit); |
| 2418 | --- /dev/null |
| 2419 | +++ b/arch/mips/au1000/ficmmp/board_setup.c |
| 2420 | @@ -0,0 +1,226 @@ |
| 2421 | +/* |
| 2422 | + * |
| 2423 | + * BRIEF MODULE DESCRIPTION |
| 2424 | + * Alchemy Pb1200 board setup. |
| 2425 | + * |
| 2426 | + * This program is free software; you can redistribute it and/or modify it |
| 2427 | + * under the terms of the GNU General Public License as published by the |
| 2428 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 2429 | + * option) any later version. |
| 2430 | + * |
| 2431 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 2432 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 2433 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 2434 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 2435 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 2436 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 2437 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 2438 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 2439 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 2440 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 2441 | + * |
| 2442 | + * You should have received a copy of the GNU General Public License along |
| 2443 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 2444 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 2445 | + */ |
| 2446 | +#include <linux/config.h> |
| 2447 | +#include <linux/init.h> |
| 2448 | +#include <linux/sched.h> |
| 2449 | +#include <linux/ioport.h> |
| 2450 | +#include <linux/mm.h> |
| 2451 | +#include <linux/console.h> |
| 2452 | +#include <linux/mc146818rtc.h> |
| 2453 | +#include <linux/delay.h> |
| 2454 | +#include <linux/ide.h> |
| 2455 | + |
| 2456 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 2457 | +#include <linux/ide.h> |
| 2458 | +#endif |
| 2459 | + |
| 2460 | +#include <asm/cpu.h> |
| 2461 | +#include <asm/bootinfo.h> |
| 2462 | +#include <asm/irq.h> |
| 2463 | +#include <asm/keyboard.h> |
| 2464 | +#include <asm/mipsregs.h> |
| 2465 | +#include <asm/reboot.h> |
| 2466 | +#include <asm/pgtable.h> |
| 2467 | +#include <asm/au1000.h> |
| 2468 | +#include <asm/ficmmp.h> |
| 2469 | +#include <asm/au1xxx_dbdma.h> |
| 2470 | +#include <asm/au1xxx_gpio.h> |
| 2471 | + |
| 2472 | +extern struct rtc_ops no_rtc_ops; |
| 2473 | + |
| 2474 | +/* value currently in the board configuration register */ |
| 2475 | +u16 ficmmp_config = 0; |
| 2476 | + |
| 2477 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 2478 | +extern struct ide_ops *ide_ops; |
| 2479 | +extern struct ide_ops au1xxx_ide_ops; |
| 2480 | +extern u32 au1xxx_ide_virtbase; |
| 2481 | +extern u64 au1xxx_ide_physbase; |
| 2482 | +extern int au1xxx_ide_irq; |
| 2483 | + |
| 2484 | +u32 led_base_addr; |
| 2485 | +/* Ddma */ |
| 2486 | +chan_tab_t *ide_read_ch, *ide_write_ch; |
| 2487 | +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma |
| 2488 | + |
| 2489 | +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }; |
| 2490 | +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */ |
| 2491 | + |
| 2492 | +void board_reset (void) |
| 2493 | +{ |
| 2494 | + au_writel(0, 0xAD80001C); |
| 2495 | +} |
| 2496 | + |
| 2497 | +void board_power_off (void) |
| 2498 | +{ |
| 2499 | +} |
| 2500 | + |
| 2501 | +void __init board_setup(void) |
| 2502 | +{ |
| 2503 | + char *argptr = NULL; |
| 2504 | + u32 pin_func; |
| 2505 | + rtc_ops = &no_rtc_ops; |
| 2506 | + |
| 2507 | + ficmmp_config_init(); //Initialize FIC control register |
| 2508 | + |
| 2509 | +#if 0 |
| 2510 | + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, |
| 2511 | + * but it is board specific code, so put it here. |
| 2512 | + */ |
| 2513 | + pin_func = au_readl(SYS_PINFUNC); |
| 2514 | + au_sync(); |
| 2515 | + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; |
| 2516 | + au_writel(pin_func, SYS_PINFUNC); |
| 2517 | + |
| 2518 | + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ |
| 2519 | + au_sync(); |
| 2520 | +#endif |
| 2521 | + |
| 2522 | +#if defined( CONFIG_I2C_ALGO_AU1550 ) |
| 2523 | + { |
| 2524 | + u32 freq0, clksrc; |
| 2525 | + |
| 2526 | + /* Select SMBUS in CPLD */ |
| 2527 | + /* bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); */ |
| 2528 | + |
| 2529 | + pin_func = au_readl(SYS_PINFUNC); |
| 2530 | + au_sync(); |
| 2531 | + pin_func &= ~(3<<17 | 1<<4); |
| 2532 | + /* Set GPIOs correctly */ |
| 2533 | + pin_func |= 2<<17; |
| 2534 | + au_writel(pin_func, SYS_PINFUNC); |
| 2535 | + au_sync(); |
| 2536 | + |
| 2537 | + /* The i2c driver depends on 50Mhz clock */ |
| 2538 | + freq0 = au_readl(SYS_FREQCTRL0); |
| 2539 | + au_sync(); |
| 2540 | + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); |
| 2541 | + freq0 |= (3<<SYS_FC_FRDIV1_BIT); |
| 2542 | + /* 396Mhz / (3+1)*2 == 49.5Mhz */ |
| 2543 | + au_writel(freq0, SYS_FREQCTRL0); |
| 2544 | + au_sync(); |
| 2545 | + freq0 |= SYS_FC_FE1; |
| 2546 | + au_writel(freq0, SYS_FREQCTRL0); |
| 2547 | + au_sync(); |
| 2548 | + |
| 2549 | + clksrc = au_readl(SYS_CLKSRC); |
| 2550 | + au_sync(); |
| 2551 | + clksrc &= ~0x01f00000; |
| 2552 | + /* bit 22 is EXTCLK0 for PSC0 */ |
| 2553 | + clksrc |= (0x3 << 22); |
| 2554 | + au_writel(clksrc, SYS_CLKSRC); |
| 2555 | + au_sync(); |
| 2556 | + } |
| 2557 | +#endif |
| 2558 | + |
| 2559 | +#ifdef CONFIG_FB_AU1200 |
| 2560 | + argptr = prom_getcmdline(); |
| 2561 | + strcat(argptr, " video=au1200fb:"); |
| 2562 | +#endif |
| 2563 | + |
| 2564 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 2565 | + /* |
| 2566 | + * Iniz IDE parameters |
| 2567 | + */ |
| 2568 | + ide_ops = &au1xxx_ide_ops; |
| 2569 | + au1xxx_ide_irq = FICMMP_IDE_INT; |
| 2570 | + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR; |
| 2571 | + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR); |
| 2572 | + switch4ddma = 0; |
| 2573 | + /* |
| 2574 | + ide_ops = &au1xxx_ide_ops; |
| 2575 | + au1xxx_ide_irq = FICMMP_IDE_INT; |
| 2576 | + au1xxx_ide_base = KSEG1ADDR(AU1XXX_ATA_BASE); |
| 2577 | + */ |
| 2578 | + au1xxx_gpio_write(9, 1); |
| 2579 | + printk("B4001010: %X\n", *((u32*)0xB4001010)); |
| 2580 | + printk("B4001014: %X\n", *((u32*)0xB4001014)); |
| 2581 | + printk("B4001018: %X\n", *((u32*)0xB4001018)); |
| 2582 | + printk("B1900100: %X\n", *((u32*)0xB1900100)); |
| 2583 | + |
| 2584 | +#if 0 |
| 2585 | + ficmmp_config_clear(FICMMP_CONFIG_IDERST); |
| 2586 | + mdelay(100); |
| 2587 | + ficmmp_config_set(FICMMP_CONFIG_IDERST); |
| 2588 | + mdelay(100); |
| 2589 | +#endif |
| 2590 | + /* |
| 2591 | + * change PIO or PIO+Ddma |
| 2592 | + * check the GPIO-5 pin condition. pb1200:s18_dot |
| 2593 | + */ |
| 2594 | +/* switch4ddma = 0; //(au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; */ |
| 2595 | +#endif |
| 2596 | + |
| 2597 | + /* The Pb1200 development board uses external MUX for PSC0 to |
| 2598 | + support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI |
| 2599 | + */ |
| 2600 | +#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550) |
| 2601 | + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\ |
| 2602 | + Refer to Pb1200 documentation. |
| 2603 | +#elif defined( CONFIG_AU1550_PSC_SPI ) |
| 2604 | + //bcsr->resets |= BCSR_RESETS_PCS0MUX; |
| 2605 | +#elif defined( CONFIG_I2C_ALGO_AU1550 ) |
| 2606 | + //bcsr->resets &= (~BCSR_RESETS_PCS0MUX); |
| 2607 | +#endif |
| 2608 | + au_sync(); |
| 2609 | + |
| 2610 | + printk("FIC Multimedia Player Board\n"); |
| 2611 | + au1xxx_gpio_tristate(5); |
| 2612 | + printk("B1900100: %X\n", *((volatile u32*)0xB1900100)); |
| 2613 | + printk("B190002C: %X\n", *((volatile u32*)0xB190002C)); |
| 2614 | +} |
| 2615 | + |
| 2616 | +int |
| 2617 | +board_au1200fb_panel (void) |
| 2618 | +{ |
| 2619 | + au1xxx_gpio_tristate(6); |
| 2620 | + |
| 2621 | + if (au1xxx_gpio_read(12) == 0) |
| 2622 | + return 9; /* FS453_640x480 (Composite/S-Video) */ |
| 2623 | + else |
| 2624 | + return 7; /* Sharp 320x240 TFT */ |
| 2625 | +} |
| 2626 | + |
| 2627 | +int |
| 2628 | +board_au1200fb_panel_init (void) |
| 2629 | +{ |
| 2630 | + /*Enable data buffers*/ |
| 2631 | + ficmmp_config_clear(FICMMP_CONFIG_LCMDATAOUT); |
| 2632 | + /*Take LCD out of reset*/ |
| 2633 | + ficmmp_config_set(FICMMP_CONFIG_LCMPWREN | FICMMP_CONFIG_LCMEN); |
| 2634 | + return 0; |
| 2635 | +} |
| 2636 | + |
| 2637 | +int |
| 2638 | +board_au1200fb_panel_shutdown (void) |
| 2639 | +{ |
| 2640 | + /*Disable data buffers*/ |
| 2641 | + ficmmp_config_set(FICMMP_CONFIG_LCMDATAOUT); |
| 2642 | + /*Put LCD in reset, remove power*/ |
| 2643 | + ficmmp_config_clear(FICMMP_CONFIG_LCMEN | FICMMP_CONFIG_LCMPWREN); |
| 2644 | + return 0; |
| 2645 | +} |
| 2646 | + |
| 2647 | --- /dev/null |
| 2648 | +++ b/arch/mips/au1000/ficmmp/init.c |
| 2649 | @@ -0,0 +1,76 @@ |
| 2650 | +/* |
| 2651 | + * |
| 2652 | + * BRIEF MODULE DESCRIPTION |
| 2653 | + * PB1200 board setup |
| 2654 | + * |
| 2655 | + * This program is free software; you can redistribute it and/or modify it |
| 2656 | + * under the terms of the GNU General Public License as published by the |
| 2657 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 2658 | + * option) any later version. |
| 2659 | + * |
| 2660 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 2661 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 2662 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 2663 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 2664 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 2665 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 2666 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 2667 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 2668 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 2669 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 2670 | + * |
| 2671 | + * You should have received a copy of the GNU General Public License along |
| 2672 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 2673 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 2674 | + */ |
| 2675 | + |
| 2676 | +#include <linux/init.h> |
| 2677 | +#include <linux/mm.h> |
| 2678 | +#include <linux/sched.h> |
| 2679 | +#include <linux/bootmem.h> |
| 2680 | +#include <asm/addrspace.h> |
| 2681 | +#include <asm/bootinfo.h> |
| 2682 | +#include <linux/config.h> |
| 2683 | +#include <linux/string.h> |
| 2684 | +#include <linux/kernel.h> |
| 2685 | +#include <linux/sched.h> |
| 2686 | + |
| 2687 | +int prom_argc; |
| 2688 | +char **prom_argv, **prom_envp; |
| 2689 | +extern void __init prom_init_cmdline(void); |
| 2690 | +extern char *prom_getenv(char *envname); |
| 2691 | + |
| 2692 | +const char *get_system_type(void) |
| 2693 | +{ |
| 2694 | + return "FIC Multimedia Player (Au1200)"; |
| 2695 | +} |
| 2696 | + |
| 2697 | +u32 mae_memsize = 0; |
| 2698 | + |
| 2699 | +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) |
| 2700 | +{ |
| 2701 | + unsigned char *memsize_str; |
| 2702 | + unsigned long memsize; |
| 2703 | + |
| 2704 | + prom_argc = argc; |
| 2705 | + prom_argv = argv; |
| 2706 | + prom_envp = envp; |
| 2707 | + |
| 2708 | + mips_machgroup = MACH_GROUP_ALCHEMY; |
| 2709 | + mips_machtype = MACH_PB1000; /* set the platform # */ |
| 2710 | + prom_init_cmdline(); |
| 2711 | + |
| 2712 | + memsize_str = prom_getenv("memsize"); |
| 2713 | + if (!memsize_str) { |
| 2714 | + memsize = 0x08000000; |
| 2715 | + } else { |
| 2716 | + memsize = simple_strtol(memsize_str, NULL, 0); |
| 2717 | + } |
| 2718 | + |
| 2719 | + /* reserved 32MB for MAE driver */ |
| 2720 | + memsize -= (32 * 1024 * 1024); |
| 2721 | + add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 2722 | + mae_memsize = memsize; /* for drivers/char/au1xxx_mae.c */ |
| 2723 | + return 0; |
| 2724 | +} |
| 2725 | + |
| 2726 | --- /dev/null |
| 2727 | +++ b/arch/mips/au1000/ficmmp/irqmap.c |
| 2728 | @@ -0,0 +1,61 @@ |
| 2729 | +/* |
| 2730 | + * BRIEF MODULE DESCRIPTION |
| 2731 | + * Au1xxx irq map table |
| 2732 | + * |
| 2733 | + * This program is free software; you can redistribute it and/or modify it |
| 2734 | + * under the terms of the GNU General Public License as published by the |
| 2735 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 2736 | + * option) any later version. |
| 2737 | + * |
| 2738 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 2739 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 2740 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 2741 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 2742 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 2743 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 2744 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 2745 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 2746 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 2747 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 2748 | + * |
| 2749 | + * You should have received a copy of the GNU General Public License along |
| 2750 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 2751 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 2752 | + */ |
| 2753 | +#include <linux/errno.h> |
| 2754 | +#include <linux/init.h> |
| 2755 | +#include <linux/irq.h> |
| 2756 | +#include <linux/kernel_stat.h> |
| 2757 | +#include <linux/module.h> |
| 2758 | +#include <linux/signal.h> |
| 2759 | +#include <linux/sched.h> |
| 2760 | +#include <linux/types.h> |
| 2761 | +#include <linux/interrupt.h> |
| 2762 | +#include <linux/ioport.h> |
| 2763 | +#include <linux/timex.h> |
| 2764 | +#include <linux/slab.h> |
| 2765 | +#include <linux/random.h> |
| 2766 | +#include <linux/delay.h> |
| 2767 | + |
| 2768 | +#include <asm/bitops.h> |
| 2769 | +#include <asm/bootinfo.h> |
| 2770 | +#include <asm/io.h> |
| 2771 | +#include <asm/mipsregs.h> |
| 2772 | +#include <asm/system.h> |
| 2773 | +#include <asm/au1000.h> |
| 2774 | +#include <asm/ficmmp.h> |
| 2775 | + |
| 2776 | +au1xxx_irq_map_t au1xxx_irq_map[] = { |
| 2777 | + { FICMMP_IDE_INT, INTC_INT_HIGH_LEVEL, 0 }, |
| 2778 | + { AU1XXX_SMC91111_IRQ, INTC_INT_HIGH_LEVEL, 0 }, |
| 2779 | + { AU1000_GPIO_1 , INTC_INT_FALL_EDGE, 0 }, // main button |
| 2780 | + { AU1000_GPIO_6 , INTC_INT_RISE_EDGE, 0 }, // select button |
| 2781 | + { AU1000_GPIO_12, INTC_INT_FALL_EDGE, 0 }, // guide button |
| 2782 | + { AU1000_GPIO_17, INTC_INT_RISE_EDGE, 0 }, // down button |
| 2783 | + { AU1000_GPIO_19, INTC_INT_RISE_EDGE, 0 }, // left button |
| 2784 | + { AU1000_GPIO_26, INTC_INT_RISE_EDGE, 0 }, // right button |
| 2785 | + { AU1000_GPIO_28, INTC_INT_RISE_EDGE, 0 }, // up button |
| 2786 | +}; |
| 2787 | + |
| 2788 | +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); |
| 2789 | + |
| 2790 | --- /dev/null |
| 2791 | +++ b/arch/mips/au1000/ficmmp/Makefile |
| 2792 | @@ -0,0 +1,25 @@ |
| 2793 | +# |
| 2794 | +# Copyright 2000 MontaVista Software Inc. |
| 2795 | +# Author: MontaVista Software, Inc. |
| 2796 | +# ppopov@mvista.com or source@mvista.com |
| 2797 | +# |
| 2798 | +# Makefile for the Alchemy Semiconductor FIC board. |
| 2799 | +# |
| 2800 | +# Note! Dependencies are done automagically by 'make dep', which also |
| 2801 | +# removes any old dependencies. DON'T put your own dependencies here |
| 2802 | +# unless it's something special (ie not a .c file). |
| 2803 | +# |
| 2804 | + |
| 2805 | +USE_STANDARD_AS_RULE := true |
| 2806 | + |
| 2807 | +O_TARGET := ficmmp.o |
| 2808 | + |
| 2809 | +obj-y := init.o board_setup.o irqmap.o au1200_ibutton.o au1xxx_dock.o |
| 2810 | + |
| 2811 | +ifdef CONFIG_MMC |
| 2812 | +obj-y += mmc_support.o |
| 2813 | +export-objs +=mmc_support.o |
| 2814 | +endif |
| 2815 | + |
| 2816 | + |
| 2817 | +include $(TOPDIR)/Rules.make |
| 2818 | --- a/arch/mips/au1000/hydrogen3/board_setup.c |
| 2819 | +++ b/arch/mips/au1000/hydrogen3/board_setup.c |
| 2820 | @@ -51,12 +51,19 @@ void board_reset (void) |
| 2821 | { |
| 2822 | } |
| 2823 | |
| 2824 | +void board_power_off (void) |
| 2825 | +{ |
| 2826 | +} |
| 2827 | + |
| 2828 | void __init board_setup(void) |
| 2829 | { |
| 2830 | u32 pin_func; |
| 2831 | |
| 2832 | rtc_ops = &no_rtc_ops; |
| 2833 | |
| 2834 | + /* Set GPIO14 high to make CD/DAT1 high for MMC to work */ |
| 2835 | + au_writel(1<<14, SYS_OUTPUTSET); |
| 2836 | + |
| 2837 | #ifdef CONFIG_AU1X00_USB_DEVICE |
| 2838 | // 2nd USB port is USB device |
| 2839 | pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); |
| 2840 | --- /dev/null |
| 2841 | +++ b/arch/mips/au1000/hydrogen3/buttons.c |
| 2842 | @@ -0,0 +1,308 @@ |
| 2843 | +/* |
| 2844 | + * Copyright (C) 2003 Metrowerks, All Rights Reserved. |
| 2845 | + * |
| 2846 | + * This program is free software; you can redistribute it and/or modify |
| 2847 | + * it under the terms of the GNU General Public License version 2 as |
| 2848 | + * published by the Free Software Foundation. |
| 2849 | + */ |
| 2850 | + |
| 2851 | +#include <linux/config.h> |
| 2852 | +#include <linux/module.h> |
| 2853 | +#include <linux/init.h> |
| 2854 | +#include <linux/fs.h> |
| 2855 | +#include <linux/sched.h> |
| 2856 | +#include <linux/miscdevice.h> |
| 2857 | +#include <linux/errno.h> |
| 2858 | +#include <linux/poll.h> |
| 2859 | +#include <asm/au1000.h> |
| 2860 | +#include <asm/uaccess.h> |
| 2861 | + |
| 2862 | +#define BUTTON_SELECT (1<<1) |
| 2863 | +#define BUTTON_1 (1<<2) |
| 2864 | +#define BUTTON_2 (1<<3) |
| 2865 | +#define BUTTON_ONOFF (1<<6) |
| 2866 | +#define BUTTON_3 (1<<7) |
| 2867 | +#define BUTTON_4 (1<<8) |
| 2868 | +#define BUTTON_LEFT (1<<9) |
| 2869 | +#define BUTTON_DOWN (1<<10) |
| 2870 | +#define BUTTON_RIGHT (1<<11) |
| 2871 | +#define BUTTON_UP (1<<12) |
| 2872 | + |
| 2873 | +#define BUTTON_MASK (\ |
| 2874 | + BUTTON_SELECT \ |
| 2875 | + | BUTTON_1 \ |
| 2876 | + | BUTTON_2 \ |
| 2877 | + | BUTTON_ONOFF \ |
| 2878 | + | BUTTON_3 \ |
| 2879 | + | BUTTON_4 \ |
| 2880 | + | BUTTON_LEFT \ |
| 2881 | + | BUTTON_DOWN \ |
| 2882 | + | BUTTON_RIGHT \ |
| 2883 | + | BUTTON_UP \ |
| 2884 | + ) |
| 2885 | + |
| 2886 | +#define BUTTON_INVERT (\ |
| 2887 | + BUTTON_SELECT \ |
| 2888 | + | BUTTON_1 \ |
| 2889 | + | BUTTON_2 \ |
| 2890 | + | BUTTON_3 \ |
| 2891 | + | BUTTON_4 \ |
| 2892 | + | BUTTON_LEFT \ |
| 2893 | + | BUTTON_DOWN \ |
| 2894 | + | BUTTON_RIGHT \ |
| 2895 | + | BUTTON_UP \ |
| 2896 | + ) |
| 2897 | + |
| 2898 | + |
| 2899 | + |
| 2900 | +#define MAKE_FLAG 0x20 |
| 2901 | + |
| 2902 | +#undef DEBUG |
| 2903 | + |
| 2904 | +#define DEBUG 0 |
| 2905 | +//#define DEBUG 1 |
| 2906 | + |
| 2907 | +#if DEBUG |
| 2908 | +#define DPRINTK(format, args...) printk(__FUNCTION__ ": " format, ## args) |
| 2909 | +#else |
| 2910 | +#define DPRINTK(format, args...) do { } while (0) |
| 2911 | +#endif |
| 2912 | + |
| 2913 | +/* Please note that this driver is based on a timer and is not interrupt |
| 2914 | + * driven. If you are going to make use of this driver, you will need to have |
| 2915 | + * your application open the buttons listing from the /dev directory first. |
| 2916 | + */ |
| 2917 | + |
| 2918 | +struct hydrogen3_buttons { |
| 2919 | + struct fasync_struct *fasync; |
| 2920 | + wait_queue_head_t read_wait; |
| 2921 | + int open_count; |
| 2922 | + unsigned int debounce; |
| 2923 | + unsigned int current; |
| 2924 | + unsigned int last; |
| 2925 | +}; |
| 2926 | + |
| 2927 | +static struct hydrogen3_buttons buttons_info; |
| 2928 | + |
| 2929 | + |
| 2930 | +static void button_timer_periodic(void *data); |
| 2931 | + |
| 2932 | +static struct tq_struct button_task = { |
| 2933 | + routine: button_timer_periodic, |
| 2934 | + data: NULL |
| 2935 | +}; |
| 2936 | + |
| 2937 | +static int cleanup_flag = 0; |
| 2938 | +static DECLARE_WAIT_QUEUE_HEAD(cleanup_wait_queue); |
| 2939 | + |
| 2940 | + |
| 2941 | +static unsigned int read_button_state(void) |
| 2942 | +{ |
| 2943 | + unsigned long state; |
| 2944 | + |
| 2945 | + state = inl(SYS_PINSTATERD) & BUTTON_MASK; |
| 2946 | + state ^= BUTTON_INVERT; |
| 2947 | + |
| 2948 | + DPRINTK( "Current Button State: %d\n", state ); |
| 2949 | + |
| 2950 | + return state; |
| 2951 | +} |
| 2952 | + |
| 2953 | + |
| 2954 | +static void button_timer_periodic(void *data) |
| 2955 | +{ |
| 2956 | + struct hydrogen3_buttons *buttons = (struct hydrogen3_buttons *)data; |
| 2957 | + unsigned long button_state; |
| 2958 | + |
| 2959 | + // If cleanup wants us to die |
| 2960 | + if (cleanup_flag) { |
| 2961 | + wake_up(&cleanup_wait_queue); // now cleanup_module can return |
| 2962 | + } else { |
| 2963 | + queue_task(&button_task, &tq_timer); // put ourselves back in the task queue |
| 2964 | + } |
| 2965 | + |
| 2966 | + // read current buttons |
| 2967 | + button_state = read_button_state(); |
| 2968 | + |
| 2969 | + // if no buttons are down and nothing to do then |
| 2970 | + // save time and be done. |
| 2971 | + if ((button_state == 0) && (buttons->current == 0)) { |
| 2972 | + return; |
| 2973 | + } |
| 2974 | + |
| 2975 | + if (button_state == buttons->debounce) { |
| 2976 | + buttons->current = button_state; |
| 2977 | + } else { |
| 2978 | + buttons->debounce = button_state; |
| 2979 | + } |
| 2980 | +// printk("0x%04x\n", button_state); |
| 2981 | + if (buttons->current != buttons->last) { |
| 2982 | + if (waitqueue_active(&buttons->read_wait)) { |
| 2983 | + wake_up_interruptible(&buttons->read_wait); |
| 2984 | + } |
| 2985 | + } |
| 2986 | +} |
| 2987 | + |
| 2988 | + |
| 2989 | +static ssize_t hydrogen3_buttons_read(struct file *filp, char *buffer, size_t count, loff_t *ppos) |
| 2990 | +{ |
| 2991 | + struct hydrogen3_buttons *buttons = filp->private_data; |
| 2992 | + char events[16]; |
| 2993 | + int index; |
| 2994 | + int last; |
| 2995 | + int cur; |
| 2996 | + int bit; |
| 2997 | + int bit_mask; |
| 2998 | + int err; |
| 2999 | + |
| 3000 | + DPRINTK("start\n"); |
| 3001 | + |
| 3002 | +try_again: |
| 3003 | + |
| 3004 | + while (buttons->current == buttons->last) { |
| 3005 | + if (filp->f_flags & O_NONBLOCK) { |
| 3006 | + return -EAGAIN; |
| 3007 | + } |
| 3008 | + interruptible_sleep_on(&buttons->read_wait); |
| 3009 | + if (signal_pending(current)) { |
| 3010 | + return -ERESTARTSYS; |
| 3011 | + } |
| 3012 | + } |
| 3013 | + |
| 3014 | + cur = buttons->current; |
| 3015 | + last = buttons->last; |
| 3016 | + |
| 3017 | + index = 0; |
| 3018 | + bit_mask = 1; |
| 3019 | + for (bit = 0; (bit < 16) && count; bit++) { |
| 3020 | + if ((cur ^ last) & bit_mask) { |
| 3021 | + if (cur & bit_mask) { |
| 3022 | + events[index] = (bit | MAKE_FLAG) + 'A'; |
| 3023 | + last |= bit_mask; |
| 3024 | + } else { |
| 3025 | + events[index] = bit + 'A'; |
| 3026 | + last &= ~bit_mask; |
| 3027 | + } |
| 3028 | + index++; |
| 3029 | + count--; |
| 3030 | + } |
| 3031 | + bit_mask <<= 1; |
| 3032 | + } |
| 3033 | + buttons->last = last; |
| 3034 | + |
| 3035 | + if (index == 0) { |
| 3036 | + goto try_again; |
| 3037 | + } |
| 3038 | + |
| 3039 | + err = copy_to_user(buffer, events, index); |
| 3040 | + if (err) { |
| 3041 | + return err; |
| 3042 | + } |
| 3043 | + |
| 3044 | + return index; |
| 3045 | +} |
| 3046 | + |
| 3047 | + |
| 3048 | +static int hydrogen3_buttons_open(struct inode *inode, struct file *filp) |
| 3049 | +{ |
| 3050 | + struct hydrogen3_buttons *buttons = &buttons_info; |
| 3051 | + |
| 3052 | + DPRINTK("start\n"); |
| 3053 | + MOD_INC_USE_COUNT; |
| 3054 | + |
| 3055 | + filp->private_data = buttons; |
| 3056 | + |
| 3057 | + if (buttons->open_count++ == 0) { |
| 3058 | + button_task.data = buttons; |
| 3059 | + cleanup_flag = 0; |
| 3060 | + queue_task(&button_task, &tq_timer); |
| 3061 | + } |
| 3062 | + |
| 3063 | + return 0; |
| 3064 | +} |
| 3065 | + |
| 3066 | + |
| 3067 | +static unsigned int hydrogen3_buttons_poll(struct file *filp, poll_table *wait) |
| 3068 | +{ |
| 3069 | + struct hydrogen3_buttons *buttons = filp->private_data; |
| 3070 | + int ret = 0; |
| 3071 | + |
| 3072 | + DPRINTK("start\n"); |
| 3073 | + poll_wait(filp, &buttons->read_wait, wait); |
| 3074 | + if (buttons->current != buttons->last) { |
| 3075 | + ret = POLLIN | POLLRDNORM; |
| 3076 | + } |
| 3077 | + return ret; |
| 3078 | +} |
| 3079 | + |
| 3080 | + |
| 3081 | +static int hydrogen3_buttons_release(struct inode *inode, struct file *filp) |
| 3082 | +{ |
| 3083 | + struct hydrogen3_buttons *buttons = filp->private_data; |
| 3084 | + |
| 3085 | + DPRINTK("start\n"); |
| 3086 | + |
| 3087 | + if (--buttons->open_count == 0) { |
| 3088 | + cleanup_flag = 1; |
| 3089 | + sleep_on(&cleanup_wait_queue); |
| 3090 | + } |
| 3091 | + MOD_DEC_USE_COUNT; |
| 3092 | + |
| 3093 | + return 0; |
| 3094 | +} |
| 3095 | + |
| 3096 | + |
| 3097 | + |
| 3098 | +static struct file_operations hydrogen3_buttons_fops = { |
| 3099 | + owner: THIS_MODULE, |
| 3100 | + read: hydrogen3_buttons_read, |
| 3101 | + poll: hydrogen3_buttons_poll, |
| 3102 | + open: hydrogen3_buttons_open, |
| 3103 | + release: hydrogen3_buttons_release, |
| 3104 | +}; |
| 3105 | + |
| 3106 | +/* |
| 3107 | + * The hydrogen3 buttons is a misc device: |
| 3108 | + * Major 10 char |
| 3109 | + * Minor 22 /dev/buttons |
| 3110 | + * |
| 3111 | + * This is /dev/misc/buttons if devfs is used. |
| 3112 | + */ |
| 3113 | + |
| 3114 | +static struct miscdevice hydrogen3_buttons_dev = { |
| 3115 | + minor: 22, |
| 3116 | + name: "buttons", |
| 3117 | + fops: &hydrogen3_buttons_fops, |
| 3118 | +}; |
| 3119 | + |
| 3120 | +static int __init hydrogen3_buttons_init(void) |
| 3121 | +{ |
| 3122 | + struct hydrogen3_buttons *buttons = &buttons_info; |
| 3123 | + int ret; |
| 3124 | + |
| 3125 | + DPRINTK("Initializing buttons driver\n"); |
| 3126 | + buttons->open_count = 0; |
| 3127 | + cleanup_flag = 0; |
| 3128 | + init_waitqueue_head(&buttons->read_wait); |
| 3129 | + |
| 3130 | + |
| 3131 | + // yamon configures GPIO pins for the buttons |
| 3132 | + // no initialization needed |
| 3133 | + |
| 3134 | + ret = misc_register(&hydrogen3_buttons_dev); |
| 3135 | + |
| 3136 | + DPRINTK("Buttons driver fully initialized.\n"); |
| 3137 | + |
| 3138 | + return ret; |
| 3139 | +} |
| 3140 | + |
| 3141 | + |
| 3142 | +static void __exit hydrogen3_buttons_exit(void) |
| 3143 | +{ |
| 3144 | + DPRINTK("unloading buttons driver\n"); |
| 3145 | + misc_deregister(&hydrogen3_buttons_dev); |
| 3146 | +} |
| 3147 | + |
| 3148 | + |
| 3149 | +module_init(hydrogen3_buttons_init); |
| 3150 | +module_exit(hydrogen3_buttons_exit); |
| 3151 | --- a/arch/mips/au1000/hydrogen3/Makefile |
| 3152 | +++ b/arch/mips/au1000/hydrogen3/Makefile |
| 3153 | @@ -14,6 +14,11 @@ USE_STANDARD_AS_RULE := true |
| 3154 | |
| 3155 | O_TARGET := hydrogen3.o |
| 3156 | |
| 3157 | -obj-y := init.o board_setup.o irqmap.o |
| 3158 | +obj-y := init.o board_setup.o irqmap.o buttons.o |
| 3159 | + |
| 3160 | +ifdef CONFIG_MMC |
| 3161 | +obj-y += mmc_support.o |
| 3162 | +export-objs +=mmc_support.o |
| 3163 | +endif |
| 3164 | |
| 3165 | include $(TOPDIR)/Rules.make |
| 3166 | --- /dev/null |
| 3167 | +++ b/arch/mips/au1000/hydrogen3/mmc_support.c |
| 3168 | @@ -0,0 +1,89 @@ |
| 3169 | +/* |
| 3170 | + * BRIEF MODULE DESCRIPTION |
| 3171 | + * |
| 3172 | + * MMC support routines for Hydrogen3. |
| 3173 | + * |
| 3174 | + * |
| 3175 | + * Copyright (c) 2003-2004 Embedded Edge, LLC. |
| 3176 | + * Author: Embedded Edge, LLC. |
| 3177 | + * Contact: dan@embeddededge.com |
| 3178 | + * |
| 3179 | + * This program is free software; you can redistribute it and/or modify it |
| 3180 | + * under the terms of the GNU General Public License as published by the |
| 3181 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3182 | + * option) any later version. |
| 3183 | + * |
| 3184 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3185 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3186 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3187 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3188 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3189 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3190 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3191 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3192 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3193 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3194 | + * |
| 3195 | + * You should have received a copy of the GNU General Public License along |
| 3196 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3197 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 3198 | + * |
| 3199 | + */ |
| 3200 | + |
| 3201 | + |
| 3202 | +#include <linux/config.h> |
| 3203 | +#include <linux/kernel.h> |
| 3204 | +#include <linux/module.h> |
| 3205 | +#include <linux/init.h> |
| 3206 | + |
| 3207 | +#include <asm/irq.h> |
| 3208 | +#include <asm/au1000.h> |
| 3209 | +#include <asm/au1100_mmc.h> |
| 3210 | + |
| 3211 | +#define GPIO_17_WP 0x20000 |
| 3212 | + |
| 3213 | +/* SD/MMC controller support functions */ |
| 3214 | + |
| 3215 | +/* |
| 3216 | + * Detect card. |
| 3217 | + */ |
| 3218 | +void mmc_card_inserted(int _n_, int *_res_) |
| 3219 | +{ |
| 3220 | + u32 gpios = au_readl(SYS_PINSTATERD); |
| 3221 | + u32 emptybit = (1<<16); |
| 3222 | + *_res_ = ((gpios & emptybit) == 0); |
| 3223 | +} |
| 3224 | + |
| 3225 | +/* |
| 3226 | + * Check card write protection. |
| 3227 | + */ |
| 3228 | +void mmc_card_writable(int _n_, int *_res_) |
| 3229 | +{ |
| 3230 | + unsigned long mmc_wp, board_specific; |
| 3231 | + board_specific = au_readl(SYS_OUTPUTSET); |
| 3232 | + mmc_wp=GPIO_17_WP; |
| 3233 | + if (!(board_specific & mmc_wp)) {/* low means card writable */ |
| 3234 | + *_res_ = 1; |
| 3235 | + } else { |
| 3236 | + *_res_ = 0; |
| 3237 | + } |
| 3238 | +} |
| 3239 | +/* |
| 3240 | + * Apply power to card slot. |
| 3241 | + */ |
| 3242 | +void mmc_power_on(int _n_) |
| 3243 | +{ |
| 3244 | +} |
| 3245 | + |
| 3246 | +/* |
| 3247 | + * Remove power from card slot. |
| 3248 | + */ |
| 3249 | +void mmc_power_off(int _n_) |
| 3250 | +{ |
| 3251 | +} |
| 3252 | + |
| 3253 | +EXPORT_SYMBOL(mmc_card_inserted); |
| 3254 | +EXPORT_SYMBOL(mmc_card_writable); |
| 3255 | +EXPORT_SYMBOL(mmc_power_on); |
| 3256 | +EXPORT_SYMBOL(mmc_power_off); |
| 3257 | + |
| 3258 | --- a/arch/mips/au1000/mtx-1/board_setup.c |
| 3259 | +++ b/arch/mips/au1000/mtx-1/board_setup.c |
| 3260 | @@ -48,6 +48,12 @@ |
| 3261 | |
| 3262 | extern struct rtc_ops no_rtc_ops; |
| 3263 | |
| 3264 | +void board_reset (void) |
| 3265 | +{ |
| 3266 | + /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ |
| 3267 | + au_writel(0x00000000, 0xAE00001C); |
| 3268 | +} |
| 3269 | + |
| 3270 | void __init board_setup(void) |
| 3271 | { |
| 3272 | rtc_ops = &no_rtc_ops; |
| 3273 | --- a/arch/mips/au1000/mtx-1/irqmap.c |
| 3274 | +++ b/arch/mips/au1000/mtx-1/irqmap.c |
| 3275 | @@ -72,10 +72,10 @@ au1xxx_pci_irqmap(struct pci_dev *dev, u |
| 3276 | * A B C D |
| 3277 | */ |
| 3278 | { |
| 3279 | - {INTA, INTB, INTC, INTD}, /* IDSEL 0 */ |
| 3280 | - {INTA, INTB, INTC, INTD}, /* IDSEL 1 */ |
| 3281 | - {INTA, INTB, INTC, INTD}, /* IDSEL 2 */ |
| 3282 | - {INTA, INTB, INTC, INTD}, /* IDSEL 3 */ |
| 3283 | + {INTA, INTB, INTX, INTX}, /* IDSEL 0 */ |
| 3284 | + {INTB, INTA, INTX, INTX}, /* IDSEL 1 */ |
| 3285 | + {INTC, INTD, INTX, INTX}, /* IDSEL 2 */ |
| 3286 | + {INTD, INTC, INTX, INTX}, /* IDSEL 3 */ |
| 3287 | }; |
| 3288 | const long min_idsel = 0, max_idsel = 3, irqs_per_slot = 4; |
| 3289 | return PCI_IRQ_TABLE_LOOKUP; |
| 3290 | --- a/arch/mips/au1000/pb1000/board_setup.c |
| 3291 | +++ b/arch/mips/au1000/pb1000/board_setup.c |
| 3292 | @@ -58,6 +58,10 @@ void board_reset (void) |
| 3293 | { |
| 3294 | } |
| 3295 | |
| 3296 | +void board_power_off (void) |
| 3297 | +{ |
| 3298 | +} |
| 3299 | + |
| 3300 | void __init board_setup(void) |
| 3301 | { |
| 3302 | u32 pin_func, static_cfg0; |
| 3303 | --- a/arch/mips/au1000/pb1100/board_setup.c |
| 3304 | +++ b/arch/mips/au1000/pb1100/board_setup.c |
| 3305 | @@ -62,6 +62,10 @@ void board_reset (void) |
| 3306 | au_writel(0x00000000, 0xAE00001C); |
| 3307 | } |
| 3308 | |
| 3309 | +void board_power_off (void) |
| 3310 | +{ |
| 3311 | +} |
| 3312 | + |
| 3313 | void __init board_setup(void) |
| 3314 | { |
| 3315 | u32 pin_func; |
| 3316 | --- a/arch/mips/au1000/pb1100/Makefile |
| 3317 | +++ b/arch/mips/au1000/pb1100/Makefile |
| 3318 | @@ -16,4 +16,10 @@ O_TARGET := pb1100.o |
| 3319 | |
| 3320 | obj-y := init.o board_setup.o irqmap.o |
| 3321 | |
| 3322 | + |
| 3323 | +ifdef CONFIG_MMC |
| 3324 | +obj-y += mmc_support.o |
| 3325 | +export-objs += mmc_support.o |
| 3326 | +endif |
| 3327 | + |
| 3328 | include $(TOPDIR)/Rules.make |
| 3329 | --- /dev/null |
| 3330 | +++ b/arch/mips/au1000/pb1100/mmc_support.c |
| 3331 | @@ -0,0 +1,126 @@ |
| 3332 | +/* |
| 3333 | + * BRIEF MODULE DESCRIPTION |
| 3334 | + * |
| 3335 | + * MMC support routines for PB1100. |
| 3336 | + * |
| 3337 | + * |
| 3338 | + * Copyright (c) 2003-2004 Embedded Edge, LLC. |
| 3339 | + * Author: Embedded Edge, LLC. |
| 3340 | + * Contact: dan@embeddededge.com |
| 3341 | + * |
| 3342 | + * This program is free software; you can redistribute it and/or modify it |
| 3343 | + * under the terms of the GNU General Public License as published by the |
| 3344 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3345 | + * option) any later version. |
| 3346 | + * |
| 3347 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3348 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3349 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3350 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3351 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3352 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3353 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3354 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3355 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3356 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3357 | + * |
| 3358 | + * You should have received a copy of the GNU General Public License along |
| 3359 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3360 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 3361 | + * |
| 3362 | + */ |
| 3363 | + |
| 3364 | + |
| 3365 | +#include <linux/config.h> |
| 3366 | +#include <linux/kernel.h> |
| 3367 | +#include <linux/module.h> |
| 3368 | +#include <linux/init.h> |
| 3369 | + |
| 3370 | +#include <asm/irq.h> |
| 3371 | +#include <asm/au1000.h> |
| 3372 | +#include <asm/au1100_mmc.h> |
| 3373 | +#include <asm/pb1100.h> |
| 3374 | + |
| 3375 | + |
| 3376 | +/* SD/MMC controller support functions */ |
| 3377 | + |
| 3378 | +/* |
| 3379 | + * Detect card. |
| 3380 | + */ |
| 3381 | +void mmc_card_inserted(int _n_, int *_res_) |
| 3382 | +{ |
| 3383 | + u32 gpios = au_readl(SYS_PINSTATERD); |
| 3384 | + u32 emptybit = (_n_) ? (1<<15) : (1<<14); |
| 3385 | + *_res_ = ((gpios & emptybit) == 0); |
| 3386 | +} |
| 3387 | + |
| 3388 | +/* |
| 3389 | + * Check card write protection. |
| 3390 | + */ |
| 3391 | +void mmc_card_writable(int _n_, int *_res_) |
| 3392 | +{ |
| 3393 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3394 | + unsigned long mmc_wp, board_specific; |
| 3395 | + |
| 3396 | + if (_n_) { |
| 3397 | + mmc_wp = BCSR_PCMCIA_SD1_WP; |
| 3398 | + } else { |
| 3399 | + mmc_wp = BCSR_PCMCIA_SD0_WP; |
| 3400 | + } |
| 3401 | + |
| 3402 | + board_specific = au_readl((unsigned long)(&bcsr->pcmcia)); |
| 3403 | + |
| 3404 | + if (!(board_specific & mmc_wp)) {/* low means card writable */ |
| 3405 | + *_res_ = 1; |
| 3406 | + } else { |
| 3407 | + *_res_ = 0; |
| 3408 | + } |
| 3409 | +} |
| 3410 | + |
| 3411 | +/* |
| 3412 | + * Apply power to card slot. |
| 3413 | + */ |
| 3414 | +void mmc_power_on(int _n_) |
| 3415 | +{ |
| 3416 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3417 | + unsigned long mmc_pwr, board_specific; |
| 3418 | + |
| 3419 | + if (_n_) { |
| 3420 | + mmc_pwr = BCSR_PCMCIA_SD1_PWR; |
| 3421 | + } else { |
| 3422 | + mmc_pwr = BCSR_PCMCIA_SD0_PWR; |
| 3423 | + } |
| 3424 | + |
| 3425 | + board_specific = au_readl((unsigned long)(&bcsr->pcmcia)); |
| 3426 | + board_specific |= mmc_pwr; |
| 3427 | + |
| 3428 | + au_writel(board_specific, (int)(&bcsr->pcmcia)); |
| 3429 | + au_sync_delay(1); |
| 3430 | +} |
| 3431 | + |
| 3432 | +/* |
| 3433 | + * Remove power from card slot. |
| 3434 | + */ |
| 3435 | +void mmc_power_off(int _n_) |
| 3436 | +{ |
| 3437 | + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3438 | + unsigned long mmc_pwr, board_specific; |
| 3439 | + |
| 3440 | + if (_n_) { |
| 3441 | + mmc_pwr = BCSR_PCMCIA_SD1_PWR; |
| 3442 | + } else { |
| 3443 | + mmc_pwr = BCSR_PCMCIA_SD0_PWR; |
| 3444 | + } |
| 3445 | + |
| 3446 | + board_specific = au_readl((unsigned long)(&bcsr->pcmcia)); |
| 3447 | + board_specific &= ~mmc_pwr; |
| 3448 | + |
| 3449 | + au_writel(board_specific, (int)(&bcsr->pcmcia)); |
| 3450 | + au_sync_delay(1); |
| 3451 | +} |
| 3452 | + |
| 3453 | +EXPORT_SYMBOL(mmc_card_inserted); |
| 3454 | +EXPORT_SYMBOL(mmc_card_writable); |
| 3455 | +EXPORT_SYMBOL(mmc_power_on); |
| 3456 | +EXPORT_SYMBOL(mmc_power_off); |
| 3457 | + |
| 3458 | --- /dev/null |
| 3459 | +++ b/arch/mips/au1000/pb1200/board_setup.c |
| 3460 | @@ -0,0 +1,221 @@ |
| 3461 | +/* |
| 3462 | + * |
| 3463 | + * BRIEF MODULE DESCRIPTION |
| 3464 | + * Alchemy Pb1200 board setup. |
| 3465 | + * |
| 3466 | + * This program is free software; you can redistribute it and/or modify it |
| 3467 | + * under the terms of the GNU General Public License as published by the |
| 3468 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3469 | + * option) any later version. |
| 3470 | + * |
| 3471 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3472 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3473 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3474 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3475 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3476 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3477 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3478 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3479 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3480 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3481 | + * |
| 3482 | + * You should have received a copy of the GNU General Public License along |
| 3483 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3484 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 3485 | + */ |
| 3486 | +#include <linux/config.h> |
| 3487 | +#include <linux/init.h> |
| 3488 | +#include <linux/sched.h> |
| 3489 | +#include <linux/ioport.h> |
| 3490 | +#include <linux/mm.h> |
| 3491 | +#include <linux/console.h> |
| 3492 | +#include <linux/mc146818rtc.h> |
| 3493 | +#include <linux/delay.h> |
| 3494 | + |
| 3495 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 3496 | +#include <linux/ide.h> |
| 3497 | +#endif |
| 3498 | + |
| 3499 | +#include <asm/cpu.h> |
| 3500 | +#include <asm/bootinfo.h> |
| 3501 | +#include <asm/irq.h> |
| 3502 | +#include <asm/keyboard.h> |
| 3503 | +#include <asm/mipsregs.h> |
| 3504 | +#include <asm/reboot.h> |
| 3505 | +#include <asm/pgtable.h> |
| 3506 | +#include <asm/au1000.h> |
| 3507 | +#include <asm/au1xxx_dbdma.h> |
| 3508 | + |
| 3509 | +#ifdef CONFIG_MIPS_PB1200 |
| 3510 | +#include <asm/pb1200.h> |
| 3511 | +#endif |
| 3512 | + |
| 3513 | +#ifdef CONFIG_MIPS_DB1200 |
| 3514 | +#include <asm/db1200.h> |
| 3515 | +#define PB1200_ETH_INT DB1200_ETH_INT |
| 3516 | +#define PB1200_IDE_INT DB1200_IDE_INT |
| 3517 | +#endif |
| 3518 | + |
| 3519 | +extern struct rtc_ops no_rtc_ops; |
| 3520 | + |
| 3521 | +extern void _board_init_irq(void); |
| 3522 | +extern void (*board_init_irq)(void); |
| 3523 | + |
| 3524 | +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX |
| 3525 | +extern struct ide_ops *ide_ops; |
| 3526 | +extern struct ide_ops au1xxx_ide_ops; |
| 3527 | +extern u32 au1xxx_ide_virtbase; |
| 3528 | +extern u64 au1xxx_ide_physbase; |
| 3529 | +extern int au1xxx_ide_irq; |
| 3530 | + |
| 3531 | +u32 led_base_addr; |
| 3532 | +/* Ddma */ |
| 3533 | +chan_tab_t *ide_read_ch, *ide_write_ch; |
| 3534 | +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma |
| 3535 | + |
| 3536 | +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }; |
| 3537 | +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */ |
| 3538 | + |
| 3539 | +void board_reset (void) |
| 3540 | +{ |
| 3541 | + bcsr->resets = 0; |
| 3542 | +} |
| 3543 | + |
| 3544 | +void board_power_off (void) |
| 3545 | +{ |
| 3546 | + bcsr->resets = 0xC000; |
| 3547 | +} |
| 3548 | + |
| 3549 | +void __init board_setup(void) |
| 3550 | +{ |
| 3551 | + char *argptr = NULL; |
| 3552 | + u32 pin_func; |
| 3553 | + rtc_ops = &no_rtc_ops; |
| 3554 | + |
| 3555 | +#if 0 |
| 3556 | + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, |
| 3557 | + * but it is board specific code, so put it here. |
| 3558 | + */ |
| 3559 | + pin_func = au_readl(SYS_PINFUNC); |
| 3560 | + au_sync(); |
| 3561 | + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; |
| 3562 | + au_writel(pin_func, SYS_PINFUNC); |
| 3563 | + |
| 3564 | + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ |
| 3565 | + au_sync(); |
| 3566 | +#endif |
| 3567 | + |
| 3568 | +#if defined( CONFIG_I2C_ALGO_AU1550 ) |
| 3569 | + { |
| 3570 | + u32 freq0, clksrc; |
| 3571 | + |
| 3572 | + /* Select SMBUS in CPLD */ |
| 3573 | + bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); |
| 3574 | + |
| 3575 | + pin_func = au_readl(SYS_PINFUNC); |
| 3576 | + au_sync(); |
| 3577 | + pin_func &= ~(3<<17 | 1<<4); |
| 3578 | + /* Set GPIOs correctly */ |
| 3579 | + pin_func |= 2<<17; |
| 3580 | + au_writel(pin_func, SYS_PINFUNC); |
| 3581 | + au_sync(); |
| 3582 | + |
| 3583 | + /* The i2c driver depends on 50Mhz clock */ |
| 3584 | + freq0 = au_readl(SYS_FREQCTRL0); |
| 3585 | + au_sync(); |
| 3586 | + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); |
| 3587 | + freq0 |= (3<<SYS_FC_FRDIV1_BIT); |
| 3588 | + /* 396Mhz / (3+1)*2 == 49.5Mhz */ |
| 3589 | + au_writel(freq0, SYS_FREQCTRL0); |
| 3590 | + au_sync(); |
| 3591 | + freq0 |= SYS_FC_FE1; |
| 3592 | + au_writel(freq0, SYS_FREQCTRL0); |
| 3593 | + au_sync(); |
| 3594 | + |
| 3595 | + clksrc = au_readl(SYS_CLKSRC); |
| 3596 | + au_sync(); |
| 3597 | + clksrc &= ~0x01f00000; |
| 3598 | + /* bit 22 is EXTCLK0 for PSC0 */ |
| 3599 | + clksrc |= (0x3 << 22); |
| 3600 | + au_writel(clksrc, SYS_CLKSRC); |
| 3601 | + au_sync(); |
| 3602 | + } |
| 3603 | +#endif |
| 3604 | + |
| 3605 | +#ifdef CONFIG_FB_AU1200 |
| 3606 | + argptr = prom_getcmdline(); |
| 3607 | + strcat(argptr, " video=au1200fb:"); |
| 3608 | +#endif |
| 3609 | + |
| 3610 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 3611 | + /* |
| 3612 | + * Iniz IDE parameters |
| 3613 | + */ |
| 3614 | + ide_ops = &au1xxx_ide_ops; |
| 3615 | + au1xxx_ide_irq = PB1200_IDE_INT; |
| 3616 | + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR; |
| 3617 | + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR); |
| 3618 | + /* |
| 3619 | + * change PIO or PIO+Ddma |
| 3620 | + * check the GPIO-5 pin condition. pb1200:s18_dot */ |
| 3621 | + switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; |
| 3622 | +#endif |
| 3623 | + |
| 3624 | + /* The Pb1200 development board uses external MUX for PSC0 to |
| 3625 | + support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI |
| 3626 | + */ |
| 3627 | +#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550) |
| 3628 | + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\ |
| 3629 | + Refer to Pb1200/Db1200 documentation. |
| 3630 | +#elif defined( CONFIG_AU1550_PSC_SPI ) |
| 3631 | + bcsr->resets |= BCSR_RESETS_PCS0MUX; |
| 3632 | +#elif defined( CONFIG_I2C_ALGO_AU1550 ) |
| 3633 | + bcsr->resets &= (~BCSR_RESETS_PCS0MUX); |
| 3634 | +#endif |
| 3635 | + au_sync(); |
| 3636 | + |
| 3637 | +#ifdef CONFIG_MIPS_PB1200 |
| 3638 | + printk("AMD Alchemy Pb1200 Board\n"); |
| 3639 | +#endif |
| 3640 | +#ifdef CONFIG_MIPS_DB1200 |
| 3641 | + printk("AMD Alchemy Db1200 Board\n"); |
| 3642 | +#endif |
| 3643 | + |
| 3644 | + /* Setup Pb1200 External Interrupt Controller */ |
| 3645 | + { |
| 3646 | + extern void (*board_init_irq)(void); |
| 3647 | + extern void _board_init_irq(void); |
| 3648 | + board_init_irq = _board_init_irq; |
| 3649 | + } |
| 3650 | +} |
| 3651 | + |
| 3652 | +int |
| 3653 | +board_au1200fb_panel (void) |
| 3654 | +{ |
| 3655 | + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3656 | + int p; |
| 3657 | + |
| 3658 | + p = bcsr->switches; |
| 3659 | + p >>= 8; |
| 3660 | + p &= 0x0F; |
| 3661 | + return p; |
| 3662 | +} |
| 3663 | + |
| 3664 | +int |
| 3665 | +board_au1200fb_panel_init (void) |
| 3666 | +{ |
| 3667 | + /* Apply power */ |
| 3668 | + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3669 | + bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); |
| 3670 | + return 0; |
| 3671 | +} |
| 3672 | + |
| 3673 | +int |
| 3674 | +board_au1200fb_panel_shutdown (void) |
| 3675 | +{ |
| 3676 | + /* Remove power */ |
| 3677 | + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 3678 | + bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); |
| 3679 | + return 0; |
| 3680 | +} |
| 3681 | + |
| 3682 | --- /dev/null |
| 3683 | +++ b/arch/mips/au1000/pb1200/init.c |
| 3684 | @@ -0,0 +1,72 @@ |
| 3685 | +/* |
| 3686 | + * |
| 3687 | + * BRIEF MODULE DESCRIPTION |
| 3688 | + * PB1200 board setup |
| 3689 | + * |
| 3690 | + * This program is free software; you can redistribute it and/or modify it |
| 3691 | + * under the terms of the GNU General Public License as published by the |
| 3692 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3693 | + * option) any later version. |
| 3694 | + * |
| 3695 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3696 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3697 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3698 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3699 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3700 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3701 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3702 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3703 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3704 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3705 | + * |
| 3706 | + * You should have received a copy of the GNU General Public License along |
| 3707 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3708 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 3709 | + */ |
| 3710 | + |
| 3711 | +#include <linux/init.h> |
| 3712 | +#include <linux/mm.h> |
| 3713 | +#include <linux/sched.h> |
| 3714 | +#include <linux/bootmem.h> |
| 3715 | +#include <asm/addrspace.h> |
| 3716 | +#include <asm/bootinfo.h> |
| 3717 | +#include <linux/config.h> |
| 3718 | +#include <linux/string.h> |
| 3719 | +#include <linux/kernel.h> |
| 3720 | +#include <linux/sched.h> |
| 3721 | + |
| 3722 | +int prom_argc; |
| 3723 | +char **prom_argv, **prom_envp; |
| 3724 | +extern void __init prom_init_cmdline(void); |
| 3725 | +extern char *prom_getenv(char *envname); |
| 3726 | + |
| 3727 | +const char *get_system_type(void) |
| 3728 | +{ |
| 3729 | + return "AMD Alchemy Au1200/Pb1200"; |
| 3730 | +} |
| 3731 | + |
| 3732 | +u32 mae_memsize = 0; |
| 3733 | + |
| 3734 | +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) |
| 3735 | +{ |
| 3736 | + unsigned char *memsize_str; |
| 3737 | + unsigned long memsize; |
| 3738 | + |
| 3739 | + prom_argc = argc; |
| 3740 | + prom_argv = argv; |
| 3741 | + prom_envp = envp; |
| 3742 | + |
| 3743 | + mips_machgroup = MACH_GROUP_ALCHEMY; |
| 3744 | + mips_machtype = MACH_PB1000; /* set the platform # */ |
| 3745 | + prom_init_cmdline(); |
| 3746 | + |
| 3747 | + memsize_str = prom_getenv("memsize"); |
| 3748 | + if (!memsize_str) { |
| 3749 | + memsize = 0x08000000; |
| 3750 | + } else { |
| 3751 | + memsize = simple_strtol(memsize_str, NULL, 0); |
| 3752 | + } |
| 3753 | + add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 3754 | + return 0; |
| 3755 | +} |
| 3756 | + |
| 3757 | --- /dev/null |
| 3758 | +++ b/arch/mips/au1000/pb1200/irqmap.c |
| 3759 | @@ -0,0 +1,180 @@ |
| 3760 | +/* |
| 3761 | + * BRIEF MODULE DESCRIPTION |
| 3762 | + * Au1xxx irq map table |
| 3763 | + * |
| 3764 | + * This program is free software; you can redistribute it and/or modify it |
| 3765 | + * under the terms of the GNU General Public License as published by the |
| 3766 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3767 | + * option) any later version. |
| 3768 | + * |
| 3769 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3770 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3771 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3772 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3773 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3774 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3775 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3776 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3777 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3778 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3779 | + * |
| 3780 | + * You should have received a copy of the GNU General Public License along |
| 3781 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3782 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 3783 | + */ |
| 3784 | +#include <linux/errno.h> |
| 3785 | +#include <linux/init.h> |
| 3786 | +#include <linux/irq.h> |
| 3787 | +#include <linux/kernel_stat.h> |
| 3788 | +#include <linux/module.h> |
| 3789 | +#include <linux/signal.h> |
| 3790 | +#include <linux/sched.h> |
| 3791 | +#include <linux/types.h> |
| 3792 | +#include <linux/interrupt.h> |
| 3793 | +#include <linux/ioport.h> |
| 3794 | +#include <linux/timex.h> |
| 3795 | +#include <linux/slab.h> |
| 3796 | +#include <linux/random.h> |
| 3797 | +#include <linux/delay.h> |
| 3798 | + |
| 3799 | +#include <asm/bitops.h> |
| 3800 | +#include <asm/bootinfo.h> |
| 3801 | +#include <asm/io.h> |
| 3802 | +#include <asm/mipsregs.h> |
| 3803 | +#include <asm/system.h> |
| 3804 | +#include <asm/au1000.h> |
| 3805 | + |
| 3806 | +#ifdef CONFIG_MIPS_PB1200 |
| 3807 | +#include <asm/pb1200.h> |
| 3808 | +#endif |
| 3809 | + |
| 3810 | +#ifdef CONFIG_MIPS_DB1200 |
| 3811 | +#include <asm/db1200.h> |
| 3812 | +#define PB1200_INT_BEGIN DB1200_INT_BEGIN |
| 3813 | +#define PB1200_INT_END DB1200_INT_END |
| 3814 | +#endif |
| 3815 | + |
| 3816 | +au1xxx_irq_map_t au1xxx_irq_map[] = { |
| 3817 | + { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade |
| 3818 | +}; |
| 3819 | + |
| 3820 | +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); |
| 3821 | + |
| 3822 | +/* |
| 3823 | + * Support for External interrupts on the PbAu1200 Development platform. |
| 3824 | + */ |
| 3825 | +static volatile int pb1200_cascade_en=0; |
| 3826 | + |
| 3827 | +void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs) |
| 3828 | +{ |
| 3829 | + unsigned short bisr = bcsr->int_status; |
| 3830 | + int extirq_nr = 0; |
| 3831 | + |
| 3832 | + /* Clear all the edge interrupts. This has no effect on level */ |
| 3833 | + bcsr->int_status = bisr; |
| 3834 | + for( ; bisr; bisr &= (bisr-1) ) |
| 3835 | + { |
| 3836 | + extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr); |
| 3837 | + /* Ack and dispatch IRQ */ |
| 3838 | + do_IRQ(extirq_nr,regs); |
| 3839 | + } |
| 3840 | +} |
| 3841 | + |
| 3842 | +inline void pb1200_enable_irq(unsigned int irq_nr) |
| 3843 | +{ |
| 3844 | + bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN); |
| 3845 | + bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN); |
| 3846 | +} |
| 3847 | + |
| 3848 | +inline void pb1200_disable_irq(unsigned int irq_nr) |
| 3849 | +{ |
| 3850 | + bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN); |
| 3851 | + bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN); |
| 3852 | +} |
| 3853 | + |
| 3854 | +static unsigned int pb1200_startup_irq( unsigned int irq_nr ) |
| 3855 | +{ |
| 3856 | + if (++pb1200_cascade_en == 1) |
| 3857 | + { |
| 3858 | + request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, |
| 3859 | + 0, "Pb1200 Cascade", &pb1200_cascade_handler ); |
| 3860 | +#ifdef CONFIG_MIPS_PB1200 |
| 3861 | + /* We have a problem with CPLD rev3. Enable a workaround */ |
| 3862 | + if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3) |
| 3863 | + { |
| 3864 | + printk("\nWARNING!!!\n"); |
| 3865 | + printk("\nWARNING!!!\n"); |
| 3866 | + printk("\nWARNING!!!\n"); |
| 3867 | + printk("\nWARNING!!!\n"); |
| 3868 | + printk("\nWARNING!!!\n"); |
| 3869 | + printk("\nWARNING!!!\n"); |
| 3870 | + printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n"); |
| 3871 | + printk("updated to latest revision. This software will not\n"); |
| 3872 | + printk("work on anything less than CPLD rev4\n"); |
| 3873 | + printk("\nWARNING!!!\n"); |
| 3874 | + printk("\nWARNING!!!\n"); |
| 3875 | + printk("\nWARNING!!!\n"); |
| 3876 | + printk("\nWARNING!!!\n"); |
| 3877 | + printk("\nWARNING!!!\n"); |
| 3878 | + printk("\nWARNING!!!\n"); |
| 3879 | + while(1); |
| 3880 | + } |
| 3881 | +#endif |
| 3882 | + } |
| 3883 | + pb1200_enable_irq(irq_nr); |
| 3884 | + return 0; |
| 3885 | +} |
| 3886 | + |
| 3887 | +static void pb1200_shutdown_irq( unsigned int irq_nr ) |
| 3888 | +{ |
| 3889 | + pb1200_disable_irq(irq_nr); |
| 3890 | + if (--pb1200_cascade_en == 0) |
| 3891 | + { |
| 3892 | + free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); |
| 3893 | + } |
| 3894 | + return; |
| 3895 | +} |
| 3896 | + |
| 3897 | +static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr) |
| 3898 | +{ |
| 3899 | + pb1200_disable_irq( irq_nr ); |
| 3900 | +} |
| 3901 | + |
| 3902 | +static void pb1200_end_irq(unsigned int irq_nr) |
| 3903 | +{ |
| 3904 | + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { |
| 3905 | + pb1200_enable_irq(irq_nr); |
| 3906 | + } |
| 3907 | +} |
| 3908 | + |
| 3909 | +static struct hw_interrupt_type external_irq_type = |
| 3910 | +{ |
| 3911 | +#ifdef CONFIG_MIPS_PB1200 |
| 3912 | + "Pb1200 Ext", |
| 3913 | +#endif |
| 3914 | +#ifdef CONFIG_MIPS_DB1200 |
| 3915 | + "Db1200 Ext", |
| 3916 | +#endif |
| 3917 | + pb1200_startup_irq, |
| 3918 | + pb1200_shutdown_irq, |
| 3919 | + pb1200_enable_irq, |
| 3920 | + pb1200_disable_irq, |
| 3921 | + pb1200_mask_and_ack_irq, |
| 3922 | + pb1200_end_irq, |
| 3923 | + NULL |
| 3924 | +}; |
| 3925 | + |
| 3926 | +void _board_init_irq(void) |
| 3927 | +{ |
| 3928 | + int irq_nr; |
| 3929 | + |
| 3930 | + for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) |
| 3931 | + { |
| 3932 | + irq_desc[irq_nr].handler = &external_irq_type; |
| 3933 | + pb1200_disable_irq(irq_nr); |
| 3934 | + } |
| 3935 | + |
| 3936 | + /* GPIO_7 can not be hooked here, so it is hooked upon first |
| 3937 | + request of any source attached to the cascade */ |
| 3938 | +} |
| 3939 | + |
| 3940 | --- /dev/null |
| 3941 | +++ b/arch/mips/au1000/pb1200/Makefile |
| 3942 | @@ -0,0 +1,25 @@ |
| 3943 | +# |
| 3944 | +# Copyright 2000 MontaVista Software Inc. |
| 3945 | +# Author: MontaVista Software, Inc. |
| 3946 | +# ppopov@mvista.com or source@mvista.com |
| 3947 | +# |
| 3948 | +# Makefile for the Alchemy Semiconductor PB1000 board. |
| 3949 | +# |
| 3950 | +# Note! Dependencies are done automagically by 'make dep', which also |
| 3951 | +# removes any old dependencies. DON'T put your own dependencies here |
| 3952 | +# unless it's something special (ie not a .c file). |
| 3953 | +# |
| 3954 | + |
| 3955 | +USE_STANDARD_AS_RULE := true |
| 3956 | + |
| 3957 | +O_TARGET := pb1200.o |
| 3958 | + |
| 3959 | +obj-y := init.o board_setup.o irqmap.o |
| 3960 | + |
| 3961 | +ifdef CONFIG_MMC |
| 3962 | +obj-y += mmc_support.o |
| 3963 | +export-objs +=mmc_support.o |
| 3964 | +endif |
| 3965 | + |
| 3966 | + |
| 3967 | +include $(TOPDIR)/Rules.make |
| 3968 | --- /dev/null |
| 3969 | +++ b/arch/mips/au1000/pb1200/mmc_support.c |
| 3970 | @@ -0,0 +1,141 @@ |
| 3971 | +/* |
| 3972 | + * BRIEF MODULE DESCRIPTION |
| 3973 | + * |
| 3974 | + * MMC support routines for PB1200. |
| 3975 | + * |
| 3976 | + * |
| 3977 | + * Copyright (c) 2003-2004 Embedded Edge, LLC. |
| 3978 | + * Author: Embedded Edge, LLC. |
| 3979 | + * Contact: dan@embeddededge.com |
| 3980 | + * |
| 3981 | + * This program is free software; you can redistribute it and/or modify it |
| 3982 | + * under the terms of the GNU General Public License as published by the |
| 3983 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 3984 | + * option) any later version. |
| 3985 | + * |
| 3986 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 3987 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 3988 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 3989 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 3990 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 3991 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 3992 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 3993 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 3994 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 3995 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 3996 | + * |
| 3997 | + * You should have received a copy of the GNU General Public License along |
| 3998 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 3999 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 4000 | + * |
| 4001 | + */ |
| 4002 | + |
| 4003 | + |
| 4004 | +#include <linux/config.h> |
| 4005 | +#include <linux/kernel.h> |
| 4006 | +#include <linux/module.h> |
| 4007 | +#include <linux/init.h> |
| 4008 | + |
| 4009 | +#include <asm/irq.h> |
| 4010 | +#include <asm/au1000.h> |
| 4011 | +#include <asm/au1100_mmc.h> |
| 4012 | + |
| 4013 | +#ifdef CONFIG_MIPS_PB1200 |
| 4014 | +#include <asm/pb1200.h> |
| 4015 | +#endif |
| 4016 | + |
| 4017 | +#ifdef CONFIG_MIPS_DB1200 |
| 4018 | +/* NOTE: DB1200 only has SD0 pinned out and usable */ |
| 4019 | +#include <asm/db1200.h> |
| 4020 | +#endif |
| 4021 | + |
| 4022 | +/* SD/MMC controller support functions */ |
| 4023 | + |
| 4024 | +/* |
| 4025 | + * Detect card. |
| 4026 | + */ |
| 4027 | +void mmc_card_inserted(int socket, int *result) |
| 4028 | +{ |
| 4029 | + u16 mask; |
| 4030 | + |
| 4031 | + if (socket) |
| 4032 | +#ifdef CONFIG_MIPS_DB1200 |
| 4033 | + mask = 0; |
| 4034 | +#else |
| 4035 | + mask = BCSR_INT_SD1INSERT; |
| 4036 | +#endif |
| 4037 | + else |
| 4038 | + mask = BCSR_INT_SD0INSERT; |
| 4039 | + |
| 4040 | + *result = ((bcsr->sig_status & mask) != 0); |
| 4041 | +} |
| 4042 | + |
| 4043 | +/* |
| 4044 | + * Check card write protection. |
| 4045 | + */ |
| 4046 | +void mmc_card_writable(int socket, int *result) |
| 4047 | +{ |
| 4048 | + u16 mask; |
| 4049 | + |
| 4050 | + if (socket) |
| 4051 | +#ifdef CONFIG_MIPS_DB1200 |
| 4052 | + mask = 0; |
| 4053 | +#else |
| 4054 | + mask = BCSR_STATUS_SD1WP; |
| 4055 | +#endif |
| 4056 | + else |
| 4057 | + mask = BCSR_STATUS_SD0WP; |
| 4058 | + |
| 4059 | + /* low means card writable */ |
| 4060 | + if (!(bcsr->status & mask)) { |
| 4061 | + *result = 1; |
| 4062 | + } else { |
| 4063 | + *result = 0; |
| 4064 | + } |
| 4065 | +} |
| 4066 | + |
| 4067 | +/* |
| 4068 | + * Apply power to card slot. |
| 4069 | + */ |
| 4070 | +void mmc_power_on(int socket) |
| 4071 | +{ |
| 4072 | + u16 mask; |
| 4073 | + |
| 4074 | + if (socket) |
| 4075 | +#ifdef CONFIG_MIPS_DB1200 |
| 4076 | + mask = 0; |
| 4077 | +#else |
| 4078 | + mask = BCSR_BOARD_SD1PWR; |
| 4079 | +#endif |
| 4080 | + else |
| 4081 | + mask = BCSR_BOARD_SD0PWR; |
| 4082 | + |
| 4083 | + bcsr->board |= mask; |
| 4084 | + au_sync_delay(1); |
| 4085 | +} |
| 4086 | + |
| 4087 | +/* |
| 4088 | + * Remove power from card slot. |
| 4089 | + */ |
| 4090 | +void mmc_power_off(int socket) |
| 4091 | +{ |
| 4092 | + u16 mask; |
| 4093 | + |
| 4094 | + if (socket) |
| 4095 | +#ifdef CONFIG_MIPS_DB1200 |
| 4096 | + mask = 0; |
| 4097 | +#else |
| 4098 | + mask = BCSR_BOARD_SD1PWR; |
| 4099 | +#endif |
| 4100 | + else |
| 4101 | + mask = BCSR_BOARD_SD0PWR; |
| 4102 | + |
| 4103 | + bcsr->board &= ~mask; |
| 4104 | + au_sync_delay(1); |
| 4105 | +} |
| 4106 | + |
| 4107 | +EXPORT_SYMBOL(mmc_card_inserted); |
| 4108 | +EXPORT_SYMBOL(mmc_card_writable); |
| 4109 | +EXPORT_SYMBOL(mmc_power_on); |
| 4110 | +EXPORT_SYMBOL(mmc_power_off); |
| 4111 | + |
| 4112 | --- a/arch/mips/au1000/pb1500/board_setup.c |
| 4113 | +++ b/arch/mips/au1000/pb1500/board_setup.c |
| 4114 | @@ -62,6 +62,10 @@ void board_reset (void) |
| 4115 | au_writel(0x00000000, 0xAE00001C); |
| 4116 | } |
| 4117 | |
| 4118 | +void board_power_off (void) |
| 4119 | +{ |
| 4120 | +} |
| 4121 | + |
| 4122 | void __init board_setup(void) |
| 4123 | { |
| 4124 | u32 pin_func; |
| 4125 | --- a/arch/mips/au1000/pb1550/board_setup.c |
| 4126 | +++ b/arch/mips/au1000/pb1550/board_setup.c |
| 4127 | @@ -48,12 +48,31 @@ |
| 4128 | |
| 4129 | extern struct rtc_ops no_rtc_ops; |
| 4130 | |
| 4131 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 4132 | +extern struct ide_ops *ide_ops; |
| 4133 | +extern struct ide_ops au1xxx_ide_ops; |
| 4134 | +extern u32 au1xxx_ide_virtbase; |
| 4135 | +extern u64 au1xxx_ide_physbase; |
| 4136 | +extern unsigned int au1xxx_ide_irq; |
| 4137 | + |
| 4138 | +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma |
| 4139 | +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */ |
| 4140 | + |
| 4141 | void board_reset (void) |
| 4142 | { |
| 4143 | /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ |
| 4144 | au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); |
| 4145 | } |
| 4146 | |
| 4147 | +void board_power_off (void) |
| 4148 | +{ |
| 4149 | + /* power off system */ |
| 4150 | + printk("\n** Powering off Pb1550\n"); |
| 4151 | + au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C); |
| 4152 | + au_sync(); |
| 4153 | + while(1); /* should not get here */ |
| 4154 | +} |
| 4155 | + |
| 4156 | void __init board_setup(void) |
| 4157 | { |
| 4158 | u32 pin_func; |
| 4159 | @@ -78,5 +97,36 @@ void __init board_setup(void) |
| 4160 | au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ |
| 4161 | au_sync(); |
| 4162 | |
| 4163 | +#if defined(CONFIG_AU1XXX_SMC91111) |
| 4164 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 4165 | +#error "Resource conflict occured. Disable either Ethernet or IDE daughter card." |
| 4166 | +#else |
| 4167 | +#define CPLD_CONTROL (0xAF00000C) |
| 4168 | + { |
| 4169 | + /* set up the Static Bus timing */ |
| 4170 | + /* only 396Mhz */ |
| 4171 | + /* reset the DC */ |
| 4172 | + au_writew(au_readw(CPLD_CONTROL) | 0x0f, CPLD_CONTROL); |
| 4173 | + au_writel(0x00010003, MEM_STCFG0); |
| 4174 | + au_writel(0x000c00c0, MEM_STCFG2); |
| 4175 | + au_writel(0x85E1900D, MEM_STTIME2); |
| 4176 | + } |
| 4177 | +#endif |
| 4178 | +#endif /* end CONFIG_SMC91111 */ |
| 4179 | + |
| 4180 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) |
| 4181 | + /* |
| 4182 | + * Iniz IDE parameters |
| 4183 | + */ |
| 4184 | + ide_ops = &au1xxx_ide_ops; |
| 4185 | + au1xxx_ide_irq = DAUGHTER_CARD_IRQ;; |
| 4186 | + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR; |
| 4187 | + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR); |
| 4188 | + /* |
| 4189 | + * change PIO or PIO+Ddma |
| 4190 | + * check the GPIO-6 pin condition. pb1550:s15_dot |
| 4191 | + */ |
| 4192 | + switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 6)) ? 1 : 0; |
| 4193 | +#endif |
| 4194 | printk("AMD Alchemy Pb1550 Board\n"); |
| 4195 | } |
| 4196 | --- a/arch/mips/au1000/pb1550/irqmap.c |
| 4197 | +++ b/arch/mips/au1000/pb1550/irqmap.c |
| 4198 | @@ -50,6 +50,9 @@ |
| 4199 | au1xxx_irq_map_t au1xxx_irq_map[] = { |
| 4200 | { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, |
| 4201 | { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, |
| 4202 | +#ifdef CONFIG_AU1XXX_SMC91111 |
| 4203 | + { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, |
| 4204 | +#endif |
| 4205 | }; |
| 4206 | |
| 4207 | int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); |
| 4208 | --- a/arch/mips/config-shared.in |
| 4209 | +++ b/arch/mips/config-shared.in |
| 4210 | @@ -21,16 +21,19 @@ mainmenu_option next_comment |
| 4211 | comment 'Machine selection' |
| 4212 | dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL |
| 4213 | dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32 |
| 4214 | +dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32 |
| 4215 | dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32 |
| 4216 | dep_bool 'Support for Alchemy Db1000 board' CONFIG_MIPS_DB1000 $CONFIG_MIPS32 |
| 4217 | dep_bool 'Support for Alchemy Db1100 board' CONFIG_MIPS_DB1100 $CONFIG_MIPS32 |
| 4218 | dep_bool 'Support for Alchemy Db1500 board' CONFIG_MIPS_DB1500 $CONFIG_MIPS32 |
| 4219 | dep_bool 'Support for Alchemy Db1550 board' CONFIG_MIPS_DB1550 $CONFIG_MIPS32 |
| 4220 | +dep_bool 'Support for Alchemy Db1200 board' CONFIG_MIPS_DB1200 $CONFIG_MIPS32 |
| 4221 | dep_bool 'Support for Alchemy PB1000 board' CONFIG_MIPS_PB1000 $CONFIG_MIPS32 |
| 4222 | dep_bool 'Support for Alchemy PB1100 board' CONFIG_MIPS_PB1100 $CONFIG_MIPS32 |
| 4223 | dep_bool 'Support for Alchemy PB1500 board' CONFIG_MIPS_PB1500 $CONFIG_MIPS32 |
| 4224 | -dep_bool 'Support for Alchemy Hydrogen3 board' CONFIG_MIPS_HYDROGEN3 $CONFIG_MIPS32 |
| 4225 | dep_bool 'Support for Alchemy PB1550 board' CONFIG_MIPS_PB1550 $CONFIG_MIPS32 |
| 4226 | +dep_bool 'Support for Alchemy PB1200 board' CONFIG_MIPS_PB1200 $CONFIG_MIPS32 |
| 4227 | +dep_bool 'Support for Alchemy Hydrogen3 board' CONFIG_MIPS_HYDROGEN3 $CONFIG_MIPS32 |
| 4228 | dep_bool 'Support for MyCable XXS1500 board' CONFIG_MIPS_XXS1500 $CONFIG_MIPS32 |
| 4229 | dep_bool 'Support for 4G Systems MTX-1 board' CONFIG_MIPS_MTX1 $CONFIG_MIPS32 |
| 4230 | dep_bool 'Support for Cogent CSB250 board' CONFIG_COGENT_CSB250 $CONFIG_MIPS32 |
| 4231 | @@ -249,6 +252,12 @@ if [ "$CONFIG_MIPS_MIRAGE" = "y" ]; then |
| 4232 | define_bool CONFIG_PC_KEYB y |
| 4233 | define_bool CONFIG_NONCOHERENT_IO y |
| 4234 | fi |
| 4235 | +if [ "$CONFIG_MIPS_FICMMP" = "y" ]; then |
| 4236 | + define_bool CONFIG_SOC_AU1X00 y |
| 4237 | + define_bool CONFIG_SOC_AU1200 y |
| 4238 | + define_bool CONFIG_NONCOHERENT_IO y |
| 4239 | + define_bool CONFIG_PC_KEYB y |
| 4240 | +fi |
| 4241 | if [ "$CONFIG_MIPS_BOSPORUS" = "y" ]; then |
| 4242 | define_bool CONFIG_SOC_AU1X00 y |
| 4243 | define_bool CONFIG_SOC_AU1500 y |
| 4244 | @@ -263,6 +272,12 @@ if [ "$CONFIG_MIPS_PB1000" = "y" ]; then |
| 4245 | define_bool CONFIG_SWAP_IO_SPACE_W y |
| 4246 | define_bool CONFIG_SWAP_IO_SPACE_L y |
| 4247 | fi |
| 4248 | +if [ "$CONFIG_MIPS_PB1500" = "y" ]; then |
| 4249 | + define_bool CONFIG_SOC_AU1X00 y |
| 4250 | + define_bool CONFIG_SOC_AU1500 y |
| 4251 | + define_bool CONFIG_NONCOHERENT_IO y |
| 4252 | + define_bool CONFIG_PC_KEYB y |
| 4253 | +fi |
| 4254 | if [ "$CONFIG_MIPS_PB1100" = "y" ]; then |
| 4255 | define_bool CONFIG_SOC_AU1X00 y |
| 4256 | define_bool CONFIG_SOC_AU1100 y |
| 4257 | @@ -271,9 +286,15 @@ if [ "$CONFIG_MIPS_PB1100" = "y" ]; then |
| 4258 | define_bool CONFIG_SWAP_IO_SPACE_W y |
| 4259 | define_bool CONFIG_SWAP_IO_SPACE_L y |
| 4260 | fi |
| 4261 | -if [ "$CONFIG_MIPS_PB1500" = "y" ]; then |
| 4262 | +if [ "$CONFIG_MIPS_PB1550" = "y" ]; then |
| 4263 | define_bool CONFIG_SOC_AU1X00 y |
| 4264 | - define_bool CONFIG_SOC_AU1500 y |
| 4265 | + define_bool CONFIG_SOC_AU1550 y |
| 4266 | + define_bool CONFIG_NONCOHERENT_IO n |
| 4267 | + define_bool CONFIG_PC_KEYB y |
| 4268 | +fi |
| 4269 | +if [ "$CONFIG_MIPS_PB1200" = "y" ]; then |
| 4270 | + define_bool CONFIG_SOC_AU1X00 y |
| 4271 | + define_bool CONFIG_SOC_AU1200 y |
| 4272 | define_bool CONFIG_NONCOHERENT_IO y |
| 4273 | define_bool CONFIG_PC_KEYB y |
| 4274 | fi |
| 4275 | @@ -290,18 +311,24 @@ if [ "$CONFIG_MIPS_DB1500" = "y" ]; then |
| 4276 | define_bool CONFIG_NONCOHERENT_IO y |
| 4277 | define_bool CONFIG_PC_KEYB y |
| 4278 | fi |
| 4279 | +if [ "$CONFIG_MIPS_DB1100" = "y" ]; then |
| 4280 | + define_bool CONFIG_SOC_AU1X00 y |
| 4281 | + define_bool CONFIG_SOC_AU1100 y |
| 4282 | + define_bool CONFIG_NONCOHERENT_IO y |
| 4283 | + define_bool CONFIG_PC_KEYB y |
| 4284 | + define_bool CONFIG_SWAP_IO_SPACE y |
| 4285 | +fi |
| 4286 | if [ "$CONFIG_MIPS_DB1550" = "y" ]; then |
| 4287 | define_bool CONFIG_SOC_AU1X00 y |
| 4288 | define_bool CONFIG_SOC_AU1550 y |
| 4289 | define_bool CONFIG_NONCOHERENT_IO y |
| 4290 | define_bool CONFIG_PC_KEYB y |
| 4291 | fi |
| 4292 | -if [ "$CONFIG_MIPS_DB1100" = "y" ]; then |
| 4293 | +if [ "$CONFIG_MIPS_DB1200" = "y" ]; then |
| 4294 | define_bool CONFIG_SOC_AU1X00 y |
| 4295 | - define_bool CONFIG_SOC_AU1100 y |
| 4296 | + define_bool CONFIG_SOC_AU1200 y |
| 4297 | define_bool CONFIG_NONCOHERENT_IO y |
| 4298 | define_bool CONFIG_PC_KEYB y |
| 4299 | - define_bool CONFIG_SWAP_IO_SPACE y |
| 4300 | fi |
| 4301 | if [ "$CONFIG_MIPS_HYDROGEN3" = "y" ]; then |
| 4302 | define_bool CONFIG_SOC_AU1X00 y |
| 4303 | @@ -327,12 +354,6 @@ if [ "$CONFIG_COGENT_CSB250" = "y" ]; th |
| 4304 | define_bool CONFIG_NONCOHERENT_IO y |
| 4305 | define_bool CONFIG_PC_KEYB y |
| 4306 | fi |
| 4307 | -if [ "$CONFIG_MIPS_PB1550" = "y" ]; then |
| 4308 | - define_bool CONFIG_SOC_AU1X00 y |
| 4309 | - define_bool CONFIG_SOC_AU1550 y |
| 4310 | - define_bool CONFIG_NONCOHERENT_IO n |
| 4311 | - define_bool CONFIG_PC_KEYB y |
| 4312 | -fi |
| 4313 | if [ "$CONFIG_MIPS_COBALT" = "y" ]; then |
| 4314 | define_bool CONFIG_BOOT_ELF32 y |
| 4315 | define_bool CONFIG_COBALT_LCD y |
| 4316 | @@ -729,6 +750,13 @@ if [ "$CONFIG_ACER_PICA_61" = "y" -o \ |
| 4317 | "$CONFIG_MIPS_PB1000" = "y" -o \ |
| 4318 | "$CONFIG_MIPS_PB1100" = "y" -o \ |
| 4319 | "$CONFIG_MIPS_PB1500" = "y" -o \ |
| 4320 | + "$CONFIG_MIPS_PB1550" = "y" -o \ |
| 4321 | + "$CONFIG_MIPS_PB1200" = "y" -o \ |
| 4322 | + "$CONFIG_MIPS_DB1000" = "y" -o \ |
| 4323 | + "$CONFIG_MIPS_DB1100" = "y" -o \ |
| 4324 | + "$CONFIG_MIPS_DB1500" = "y" -o \ |
| 4325 | + "$CONFIG_MIPS_DB1550" = "y" -o \ |
| 4326 | + "$CONFIG_MIPS_DB1200" = "y" -o \ |
| 4327 | "$CONFIG_NEC_OSPREY" = "y" -o \ |
| 4328 | "$CONFIG_NEC_EAGLE" = "y" -o \ |
| 4329 | "$CONFIG_NINO" = "y" -o \ |
| 4330 | --- a/arch/mips/defconfig |
| 4331 | +++ b/arch/mips/defconfig |
| 4332 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 4333 | # CONFIG_MIPS_PB1000 is not set |
| 4334 | # CONFIG_MIPS_PB1100 is not set |
| 4335 | # CONFIG_MIPS_PB1500 is not set |
| 4336 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4337 | # CONFIG_MIPS_PB1550 is not set |
| 4338 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4339 | # CONFIG_MIPS_XXS1500 is not set |
| 4340 | # CONFIG_MIPS_MTX1 is not set |
| 4341 | # CONFIG_COGENT_CSB250 is not set |
| 4342 | @@ -235,11 +235,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 4343 | # |
| 4344 | # CONFIG_IPX is not set |
| 4345 | # CONFIG_ATALK is not set |
| 4346 | - |
| 4347 | -# |
| 4348 | -# Appletalk devices |
| 4349 | -# |
| 4350 | -# CONFIG_DEV_APPLETALK is not set |
| 4351 | # CONFIG_DECNET is not set |
| 4352 | # CONFIG_BRIDGE is not set |
| 4353 | # CONFIG_X25 is not set |
| 4354 | @@ -319,9 +314,11 @@ CONFIG_SGIWD93_SCSI=y |
| 4355 | # CONFIG_SCSI_MEGARAID is not set |
| 4356 | # CONFIG_SCSI_MEGARAID2 is not set |
| 4357 | # CONFIG_SCSI_SATA is not set |
| 4358 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 4359 | # CONFIG_SCSI_SATA_SVW is not set |
| 4360 | # CONFIG_SCSI_ATA_PIIX is not set |
| 4361 | # CONFIG_SCSI_SATA_NV is not set |
| 4362 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 4363 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 4364 | # CONFIG_SCSI_SATA_SX4 is not set |
| 4365 | # CONFIG_SCSI_SATA_SIL is not set |
| 4366 | @@ -465,7 +462,6 @@ CONFIG_VT_CONSOLE=y |
| 4367 | # CONFIG_SERIAL is not set |
| 4368 | # CONFIG_SERIAL_EXTENDED is not set |
| 4369 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 4370 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4371 | CONFIG_UNIX98_PTYS=y |
| 4372 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4373 | |
| 4374 | --- a/arch/mips/defconfig-atlas |
| 4375 | +++ b/arch/mips/defconfig-atlas |
| 4376 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 4377 | # CONFIG_MIPS_PB1000 is not set |
| 4378 | # CONFIG_MIPS_PB1100 is not set |
| 4379 | # CONFIG_MIPS_PB1500 is not set |
| 4380 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4381 | # CONFIG_MIPS_PB1550 is not set |
| 4382 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4383 | # CONFIG_MIPS_XXS1500 is not set |
| 4384 | # CONFIG_MIPS_MTX1 is not set |
| 4385 | # CONFIG_COGENT_CSB250 is not set |
| 4386 | @@ -235,11 +235,6 @@ CONFIG_IP_PNP=y |
| 4387 | # |
| 4388 | # CONFIG_IPX is not set |
| 4389 | # CONFIG_ATALK is not set |
| 4390 | - |
| 4391 | -# |
| 4392 | -# Appletalk devices |
| 4393 | -# |
| 4394 | -# CONFIG_DEV_APPLETALK is not set |
| 4395 | # CONFIG_DECNET is not set |
| 4396 | # CONFIG_BRIDGE is not set |
| 4397 | # CONFIG_X25 is not set |
| 4398 | @@ -317,9 +312,11 @@ CONFIG_SD_EXTRA_DEVS=40 |
| 4399 | # CONFIG_SCSI_MEGARAID is not set |
| 4400 | # CONFIG_SCSI_MEGARAID2 is not set |
| 4401 | # CONFIG_SCSI_SATA is not set |
| 4402 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 4403 | # CONFIG_SCSI_SATA_SVW is not set |
| 4404 | # CONFIG_SCSI_ATA_PIIX is not set |
| 4405 | # CONFIG_SCSI_SATA_NV is not set |
| 4406 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 4407 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 4408 | # CONFIG_SCSI_SATA_SX4 is not set |
| 4409 | # CONFIG_SCSI_SATA_SIL is not set |
| 4410 | @@ -528,7 +525,6 @@ CONFIG_SERIAL=y |
| 4411 | CONFIG_SERIAL_CONSOLE=y |
| 4412 | # CONFIG_SERIAL_EXTENDED is not set |
| 4413 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 4414 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4415 | CONFIG_UNIX98_PTYS=y |
| 4416 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4417 | |
| 4418 | --- a/arch/mips/defconfig-bosporus |
| 4419 | +++ b/arch/mips/defconfig-bosporus |
| 4420 | @@ -30,8 +30,8 @@ CONFIG_MIPS_BOSPORUS=y |
| 4421 | # CONFIG_MIPS_PB1000 is not set |
| 4422 | # CONFIG_MIPS_PB1100 is not set |
| 4423 | # CONFIG_MIPS_PB1500 is not set |
| 4424 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4425 | # CONFIG_MIPS_PB1550 is not set |
| 4426 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4427 | # CONFIG_MIPS_XXS1500 is not set |
| 4428 | # CONFIG_MIPS_MTX1 is not set |
| 4429 | # CONFIG_COGENT_CSB250 is not set |
| 4430 | @@ -208,9 +208,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 4431 | CONFIG_MTD_BOSPORUS=y |
| 4432 | # CONFIG_MTD_XXS1500 is not set |
| 4433 | # CONFIG_MTD_MTX1 is not set |
| 4434 | -# CONFIG_MTD_DB1X00 is not set |
| 4435 | # CONFIG_MTD_PB1550 is not set |
| 4436 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 4437 | # CONFIG_MTD_MIRAGE is not set |
| 4438 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 4439 | # CONFIG_MTD_OCELOT is not set |
| 4440 | @@ -229,7 +227,6 @@ CONFIG_MTD_BOSPORUS=y |
| 4441 | # |
| 4442 | # Disk-On-Chip Device Drivers |
| 4443 | # |
| 4444 | -# CONFIG_MTD_DOC1000 is not set |
| 4445 | # CONFIG_MTD_DOC2000 is not set |
| 4446 | # CONFIG_MTD_DOC2001 is not set |
| 4447 | # CONFIG_MTD_DOCPROBE is not set |
| 4448 | @@ -373,11 +370,6 @@ CONFIG_IP_NF_MANGLE=m |
| 4449 | # |
| 4450 | # CONFIG_IPX is not set |
| 4451 | # CONFIG_ATALK is not set |
| 4452 | - |
| 4453 | -# |
| 4454 | -# Appletalk devices |
| 4455 | -# |
| 4456 | -# CONFIG_DEV_APPLETALK is not set |
| 4457 | # CONFIG_DECNET is not set |
| 4458 | # CONFIG_BRIDGE is not set |
| 4459 | # CONFIG_X25 is not set |
| 4460 | @@ -457,9 +449,11 @@ CONFIG_SCSI_CONSTANTS=y |
| 4461 | # CONFIG_SCSI_MEGARAID is not set |
| 4462 | # CONFIG_SCSI_MEGARAID2 is not set |
| 4463 | # CONFIG_SCSI_SATA is not set |
| 4464 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 4465 | # CONFIG_SCSI_SATA_SVW is not set |
| 4466 | # CONFIG_SCSI_ATA_PIIX is not set |
| 4467 | # CONFIG_SCSI_SATA_NV is not set |
| 4468 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 4469 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 4470 | # CONFIG_SCSI_SATA_SX4 is not set |
| 4471 | # CONFIG_SCSI_SATA_SIL is not set |
| 4472 | @@ -681,7 +675,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 4473 | # CONFIG_AU1X00_USB_TTY is not set |
| 4474 | # CONFIG_AU1X00_USB_RAW is not set |
| 4475 | # CONFIG_TXX927_SERIAL is not set |
| 4476 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4477 | CONFIG_UNIX98_PTYS=y |
| 4478 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4479 | |
| 4480 | --- a/arch/mips/defconfig-capcella |
| 4481 | +++ b/arch/mips/defconfig-capcella |
| 4482 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 4483 | # CONFIG_MIPS_PB1000 is not set |
| 4484 | # CONFIG_MIPS_PB1100 is not set |
| 4485 | # CONFIG_MIPS_PB1500 is not set |
| 4486 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4487 | # CONFIG_MIPS_PB1550 is not set |
| 4488 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4489 | # CONFIG_MIPS_XXS1500 is not set |
| 4490 | # CONFIG_MIPS_MTX1 is not set |
| 4491 | # CONFIG_COGENT_CSB250 is not set |
| 4492 | @@ -228,11 +228,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 4493 | # |
| 4494 | # CONFIG_IPX is not set |
| 4495 | # CONFIG_ATALK is not set |
| 4496 | - |
| 4497 | -# |
| 4498 | -# Appletalk devices |
| 4499 | -# |
| 4500 | -# CONFIG_DEV_APPLETALK is not set |
| 4501 | # CONFIG_DECNET is not set |
| 4502 | # CONFIG_BRIDGE is not set |
| 4503 | # CONFIG_X25 is not set |
| 4504 | @@ -472,7 +467,6 @@ CONFIG_SERIAL=y |
| 4505 | CONFIG_SERIAL_CONSOLE=y |
| 4506 | # CONFIG_SERIAL_EXTENDED is not set |
| 4507 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 4508 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4509 | # CONFIG_VR41XX_KIU is not set |
| 4510 | CONFIG_UNIX98_PTYS=y |
| 4511 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4512 | --- a/arch/mips/defconfig-cobalt |
| 4513 | +++ b/arch/mips/defconfig-cobalt |
| 4514 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 4515 | # CONFIG_MIPS_PB1000 is not set |
| 4516 | # CONFIG_MIPS_PB1100 is not set |
| 4517 | # CONFIG_MIPS_PB1500 is not set |
| 4518 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4519 | # CONFIG_MIPS_PB1550 is not set |
| 4520 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4521 | # CONFIG_MIPS_XXS1500 is not set |
| 4522 | # CONFIG_MIPS_MTX1 is not set |
| 4523 | # CONFIG_COGENT_CSB250 is not set |
| 4524 | @@ -222,11 +222,6 @@ CONFIG_INET=y |
| 4525 | # |
| 4526 | # CONFIG_IPX is not set |
| 4527 | # CONFIG_ATALK is not set |
| 4528 | - |
| 4529 | -# |
| 4530 | -# Appletalk devices |
| 4531 | -# |
| 4532 | -# CONFIG_DEV_APPLETALK is not set |
| 4533 | # CONFIG_DECNET is not set |
| 4534 | # CONFIG_BRIDGE is not set |
| 4535 | # CONFIG_X25 is not set |
| 4536 | @@ -505,7 +500,6 @@ CONFIG_SERIAL=y |
| 4537 | CONFIG_SERIAL_CONSOLE=y |
| 4538 | # CONFIG_SERIAL_EXTENDED is not set |
| 4539 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 4540 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4541 | CONFIG_UNIX98_PTYS=y |
| 4542 | CONFIG_UNIX98_PTY_COUNT=16 |
| 4543 | |
| 4544 | --- a/arch/mips/defconfig-csb250 |
| 4545 | +++ b/arch/mips/defconfig-csb250 |
| 4546 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 4547 | # CONFIG_MIPS_PB1000 is not set |
| 4548 | # CONFIG_MIPS_PB1100 is not set |
| 4549 | # CONFIG_MIPS_PB1500 is not set |
| 4550 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4551 | # CONFIG_MIPS_PB1550 is not set |
| 4552 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4553 | # CONFIG_MIPS_XXS1500 is not set |
| 4554 | # CONFIG_MIPS_MTX1 is not set |
| 4555 | CONFIG_COGENT_CSB250=y |
| 4556 | @@ -268,11 +268,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 4557 | # |
| 4558 | # CONFIG_IPX is not set |
| 4559 | # CONFIG_ATALK is not set |
| 4560 | - |
| 4561 | -# |
| 4562 | -# Appletalk devices |
| 4563 | -# |
| 4564 | -# CONFIG_DEV_APPLETALK is not set |
| 4565 | # CONFIG_DECNET is not set |
| 4566 | # CONFIG_BRIDGE is not set |
| 4567 | # CONFIG_X25 is not set |
| 4568 | @@ -556,7 +551,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 4569 | # CONFIG_AU1X00_USB_TTY is not set |
| 4570 | # CONFIG_AU1X00_USB_RAW is not set |
| 4571 | # CONFIG_TXX927_SERIAL is not set |
| 4572 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4573 | CONFIG_UNIX98_PTYS=y |
| 4574 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4575 | |
| 4576 | --- a/arch/mips/defconfig-db1000 |
| 4577 | +++ b/arch/mips/defconfig-db1000 |
| 4578 | @@ -30,8 +30,8 @@ CONFIG_MIPS_DB1000=y |
| 4579 | # CONFIG_MIPS_PB1000 is not set |
| 4580 | # CONFIG_MIPS_PB1100 is not set |
| 4581 | # CONFIG_MIPS_PB1500 is not set |
| 4582 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4583 | # CONFIG_MIPS_PB1550 is not set |
| 4584 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4585 | # CONFIG_MIPS_XXS1500 is not set |
| 4586 | # CONFIG_MIPS_MTX1 is not set |
| 4587 | # CONFIG_COGENT_CSB250 is not set |
| 4588 | @@ -214,11 +214,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 4589 | # CONFIG_MTD_BOSPORUS is not set |
| 4590 | # CONFIG_MTD_XXS1500 is not set |
| 4591 | # CONFIG_MTD_MTX1 is not set |
| 4592 | -CONFIG_MTD_DB1X00=y |
| 4593 | -CONFIG_MTD_DB1X00_BOOT=y |
| 4594 | -CONFIG_MTD_DB1X00_USER=y |
| 4595 | # CONFIG_MTD_PB1550 is not set |
| 4596 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 4597 | # CONFIG_MTD_MIRAGE is not set |
| 4598 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 4599 | # CONFIG_MTD_OCELOT is not set |
| 4600 | @@ -237,7 +233,6 @@ CONFIG_MTD_DB1X00_USER=y |
| 4601 | # |
| 4602 | # Disk-On-Chip Device Drivers |
| 4603 | # |
| 4604 | -# CONFIG_MTD_DOC1000 is not set |
| 4605 | # CONFIG_MTD_DOC2000 is not set |
| 4606 | # CONFIG_MTD_DOC2001 is not set |
| 4607 | # CONFIG_MTD_DOCPROBE is not set |
| 4608 | @@ -342,11 +337,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 4609 | # |
| 4610 | # CONFIG_IPX is not set |
| 4611 | # CONFIG_ATALK is not set |
| 4612 | - |
| 4613 | -# |
| 4614 | -# Appletalk devices |
| 4615 | -# |
| 4616 | -# CONFIG_DEV_APPLETALK is not set |
| 4617 | # CONFIG_DECNET is not set |
| 4618 | # CONFIG_BRIDGE is not set |
| 4619 | # CONFIG_X25 is not set |
| 4620 | @@ -636,7 +626,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 4621 | # CONFIG_AU1X00_USB_TTY is not set |
| 4622 | # CONFIG_AU1X00_USB_RAW is not set |
| 4623 | # CONFIG_TXX927_SERIAL is not set |
| 4624 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4625 | CONFIG_UNIX98_PTYS=y |
| 4626 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4627 | |
| 4628 | --- a/arch/mips/defconfig-db1100 |
| 4629 | +++ b/arch/mips/defconfig-db1100 |
| 4630 | @@ -30,8 +30,8 @@ CONFIG_MIPS_DB1100=y |
| 4631 | # CONFIG_MIPS_PB1000 is not set |
| 4632 | # CONFIG_MIPS_PB1100 is not set |
| 4633 | # CONFIG_MIPS_PB1500 is not set |
| 4634 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 4635 | # CONFIG_MIPS_PB1550 is not set |
| 4636 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4637 | # CONFIG_MIPS_XXS1500 is not set |
| 4638 | # CONFIG_MIPS_MTX1 is not set |
| 4639 | # CONFIG_COGENT_CSB250 is not set |
| 4640 | @@ -214,11 +214,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 4641 | # CONFIG_MTD_BOSPORUS is not set |
| 4642 | # CONFIG_MTD_XXS1500 is not set |
| 4643 | # CONFIG_MTD_MTX1 is not set |
| 4644 | -CONFIG_MTD_DB1X00=y |
| 4645 | -# CONFIG_MTD_DB1X00_BOOT is not set |
| 4646 | -CONFIG_MTD_DB1X00_USER=y |
| 4647 | # CONFIG_MTD_PB1550 is not set |
| 4648 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 4649 | # CONFIG_MTD_MIRAGE is not set |
| 4650 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 4651 | # CONFIG_MTD_OCELOT is not set |
| 4652 | @@ -237,7 +233,6 @@ CONFIG_MTD_DB1X00_USER=y |
| 4653 | # |
| 4654 | # Disk-On-Chip Device Drivers |
| 4655 | # |
| 4656 | -# CONFIG_MTD_DOC1000 is not set |
| 4657 | # CONFIG_MTD_DOC2000 is not set |
| 4658 | # CONFIG_MTD_DOC2001 is not set |
| 4659 | # CONFIG_MTD_DOCPROBE is not set |
| 4660 | @@ -342,11 +337,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 4661 | # |
| 4662 | # CONFIG_IPX is not set |
| 4663 | # CONFIG_ATALK is not set |
| 4664 | - |
| 4665 | -# |
| 4666 | -# Appletalk devices |
| 4667 | -# |
| 4668 | -# CONFIG_DEV_APPLETALK is not set |
| 4669 | # CONFIG_DECNET is not set |
| 4670 | # CONFIG_BRIDGE is not set |
| 4671 | # CONFIG_X25 is not set |
| 4672 | @@ -636,7 +626,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 4673 | # CONFIG_AU1X00_USB_TTY is not set |
| 4674 | # CONFIG_AU1X00_USB_RAW is not set |
| 4675 | # CONFIG_TXX927_SERIAL is not set |
| 4676 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 4677 | CONFIG_UNIX98_PTYS=y |
| 4678 | CONFIG_UNIX98_PTY_COUNT=256 |
| 4679 | |
| 4680 | @@ -884,6 +873,7 @@ CONFIG_DUMMY_CONSOLE=y |
| 4681 | # CONFIG_FB_PM2 is not set |
| 4682 | # CONFIG_FB_PM3 is not set |
| 4683 | # CONFIG_FB_CYBER2000 is not set |
| 4684 | +CONFIG_FB_AU1100=y |
| 4685 | # CONFIG_FB_MATROX is not set |
| 4686 | # CONFIG_FB_ATY is not set |
| 4687 | # CONFIG_FB_RADEON is not set |
| 4688 | @@ -895,7 +885,6 @@ CONFIG_DUMMY_CONSOLE=y |
| 4689 | # CONFIG_FB_VOODOO1 is not set |
| 4690 | # CONFIG_FB_TRIDENT is not set |
| 4691 | # CONFIG_FB_E1356 is not set |
| 4692 | -CONFIG_FB_AU1100=y |
| 4693 | # CONFIG_FB_IT8181 is not set |
| 4694 | # CONFIG_FB_VIRTUAL is not set |
| 4695 | CONFIG_FBCON_ADVANCED=y |
| 4696 | --- /dev/null |
| 4697 | +++ b/arch/mips/defconfig-db1200 |
| 4698 | @@ -0,0 +1,1032 @@ |
| 4699 | +# |
| 4700 | +# Automatically generated make config: don't edit |
| 4701 | +# |
| 4702 | +CONFIG_MIPS=y |
| 4703 | +CONFIG_MIPS32=y |
| 4704 | +# CONFIG_MIPS64 is not set |
| 4705 | + |
| 4706 | +# |
| 4707 | +# Code maturity level options |
| 4708 | +# |
| 4709 | +CONFIG_EXPERIMENTAL=y |
| 4710 | + |
| 4711 | +# |
| 4712 | +# Loadable module support |
| 4713 | +# |
| 4714 | +CONFIG_MODULES=y |
| 4715 | +# CONFIG_MODVERSIONS is not set |
| 4716 | +CONFIG_KMOD=y |
| 4717 | + |
| 4718 | +# |
| 4719 | +# Machine selection |
| 4720 | +# |
| 4721 | +# CONFIG_ACER_PICA_61 is not set |
| 4722 | +# CONFIG_MIPS_BOSPORUS is not set |
| 4723 | +# CONFIG_MIPS_MIRAGE is not set |
| 4724 | +# CONFIG_MIPS_DB1000 is not set |
| 4725 | +# CONFIG_MIPS_DB1100 is not set |
| 4726 | +# CONFIG_MIPS_DB1500 is not set |
| 4727 | +# CONFIG_MIPS_DB1550 is not set |
| 4728 | +# CONFIG_MIPS_PB1000 is not set |
| 4729 | +# CONFIG_MIPS_PB1100 is not set |
| 4730 | +# CONFIG_MIPS_PB1500 is not set |
| 4731 | +# CONFIG_MIPS_PB1550 is not set |
| 4732 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 4733 | +# CONFIG_MIPS_XXS1500 is not set |
| 4734 | +# CONFIG_MIPS_MTX1 is not set |
| 4735 | +# CONFIG_COGENT_CSB250 is not set |
| 4736 | +# CONFIG_BAGET_MIPS is not set |
| 4737 | +# CONFIG_CASIO_E55 is not set |
| 4738 | +# CONFIG_MIPS_COBALT is not set |
| 4739 | +# CONFIG_DECSTATION is not set |
| 4740 | +# CONFIG_MIPS_EV64120 is not set |
| 4741 | +# CONFIG_MIPS_EV96100 is not set |
| 4742 | +# CONFIG_MIPS_IVR is not set |
| 4743 | +# CONFIG_HP_LASERJET is not set |
| 4744 | +# CONFIG_IBM_WORKPAD is not set |
| 4745 | +# CONFIG_LASAT is not set |
| 4746 | +# CONFIG_MIPS_ITE8172 is not set |
| 4747 | +# CONFIG_MIPS_ATLAS is not set |
| 4748 | +# CONFIG_MIPS_MAGNUM_4000 is not set |
| 4749 | +# CONFIG_MIPS_MALTA is not set |
| 4750 | +# CONFIG_MIPS_SEAD is not set |
| 4751 | +# CONFIG_MOMENCO_OCELOT is not set |
| 4752 | +# CONFIG_MOMENCO_OCELOT_G is not set |
| 4753 | +# CONFIG_MOMENCO_OCELOT_C is not set |
| 4754 | +# CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 4755 | +# CONFIG_PMC_BIG_SUR is not set |
| 4756 | +# CONFIG_PMC_STRETCH is not set |
| 4757 | +# CONFIG_PMC_YOSEMITE is not set |
| 4758 | +# CONFIG_DDB5074 is not set |
| 4759 | +# CONFIG_DDB5476 is not set |
| 4760 | +# CONFIG_DDB5477 is not set |
| 4761 | +# CONFIG_NEC_OSPREY is not set |
| 4762 | +# CONFIG_NEC_EAGLE is not set |
| 4763 | +# CONFIG_OLIVETTI_M700 is not set |
| 4764 | +# CONFIG_NINO is not set |
| 4765 | +# CONFIG_SGI_IP22 is not set |
| 4766 | +# CONFIG_SGI_IP27 is not set |
| 4767 | +# CONFIG_SIBYTE_SB1xxx_SOC is not set |
| 4768 | +# CONFIG_SNI_RM200_PCI is not set |
| 4769 | +# CONFIG_TANBAC_TB0226 is not set |
| 4770 | +# CONFIG_TANBAC_TB0229 is not set |
| 4771 | +# CONFIG_TOSHIBA_JMR3927 is not set |
| 4772 | +# CONFIG_TOSHIBA_RBTX4927 is not set |
| 4773 | +# CONFIG_VICTOR_MPC30X is not set |
| 4774 | +# CONFIG_ZAO_CAPCELLA is not set |
| 4775 | +# CONFIG_HIGHMEM is not set |
| 4776 | +CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 4777 | +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 4778 | +# CONFIG_MIPS_AU1000 is not set |
| 4779 | + |
| 4780 | +# |
| 4781 | +# CPU selection |
| 4782 | +# |
| 4783 | +CONFIG_CPU_MIPS32=y |
| 4784 | +# CONFIG_CPU_MIPS64 is not set |
| 4785 | +# CONFIG_CPU_R3000 is not set |
| 4786 | +# CONFIG_CPU_TX39XX is not set |
| 4787 | +# CONFIG_CPU_VR41XX is not set |
| 4788 | +# CONFIG_CPU_R4300 is not set |
| 4789 | +# CONFIG_CPU_R4X00 is not set |
| 4790 | +# CONFIG_CPU_TX49XX is not set |
| 4791 | +# CONFIG_CPU_R5000 is not set |
| 4792 | +# CONFIG_CPU_R5432 is not set |
| 4793 | +# CONFIG_CPU_R6000 is not set |
| 4794 | +# CONFIG_CPU_NEVADA is not set |
| 4795 | +# CONFIG_CPU_R8000 is not set |
| 4796 | +# CONFIG_CPU_R10000 is not set |
| 4797 | +# CONFIG_CPU_RM7000 is not set |
| 4798 | +# CONFIG_CPU_RM9000 is not set |
| 4799 | +# CONFIG_CPU_SB1 is not set |
| 4800 | +CONFIG_PAGE_SIZE_4KB=y |
| 4801 | +# CONFIG_PAGE_SIZE_16KB is not set |
| 4802 | +# CONFIG_PAGE_SIZE_64KB is not set |
| 4803 | +CONFIG_CPU_HAS_PREFETCH=y |
| 4804 | +# CONFIG_VTAG_ICACHE is not set |
| 4805 | +CONFIG_64BIT_PHYS_ADDR=y |
| 4806 | +# CONFIG_CPU_ADVANCED is not set |
| 4807 | +CONFIG_CPU_HAS_LLSC=y |
| 4808 | +# CONFIG_CPU_HAS_LLDSCD is not set |
| 4809 | +# CONFIG_CPU_HAS_WB is not set |
| 4810 | +CONFIG_CPU_HAS_SYNC=y |
| 4811 | + |
| 4812 | +# |
| 4813 | +# General setup |
| 4814 | +# |
| 4815 | +CONFIG_CPU_LITTLE_ENDIAN=y |
| 4816 | +# CONFIG_BUILD_ELF64 is not set |
| 4817 | +CONFIG_NET=y |
| 4818 | +CONFIG_PCI=y |
| 4819 | +CONFIG_PCI_NEW=y |
| 4820 | +CONFIG_PCI_AUTO=y |
| 4821 | +# CONFIG_PCI_NAMES is not set |
| 4822 | +# CONFIG_ISA is not set |
| 4823 | +# CONFIG_TC is not set |
| 4824 | +# CONFIG_MCA is not set |
| 4825 | +# CONFIG_SBUS is not set |
| 4826 | +CONFIG_HOTPLUG=y |
| 4827 | + |
| 4828 | +# |
| 4829 | +# PCMCIA/CardBus support |
| 4830 | +# |
| 4831 | +CONFIG_PCMCIA=m |
| 4832 | +# CONFIG_CARDBUS is not set |
| 4833 | +# CONFIG_TCIC is not set |
| 4834 | +# CONFIG_I82092 is not set |
| 4835 | +# CONFIG_I82365 is not set |
| 4836 | + |
| 4837 | +# |
| 4838 | +# PCI Hotplug Support |
| 4839 | +# |
| 4840 | +# CONFIG_HOTPLUG_PCI is not set |
| 4841 | +# CONFIG_HOTPLUG_PCI_COMPAQ is not set |
| 4842 | +# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set |
| 4843 | +# CONFIG_HOTPLUG_PCI_SHPC is not set |
| 4844 | +# CONFIG_HOTPLUG_PCI_SHPC_POLL_EVENT_MODE is not set |
| 4845 | +# CONFIG_HOTPLUG_PCI_PCIE is not set |
| 4846 | +# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set |
| 4847 | +CONFIG_SYSVIPC=y |
| 4848 | +# CONFIG_BSD_PROCESS_ACCT is not set |
| 4849 | +CONFIG_SYSCTL=y |
| 4850 | +CONFIG_KCORE_ELF=y |
| 4851 | +# CONFIG_KCORE_AOUT is not set |
| 4852 | +# CONFIG_BINFMT_AOUT is not set |
| 4853 | +CONFIG_BINFMT_ELF=y |
| 4854 | +# CONFIG_MIPS32_COMPAT is not set |
| 4855 | +# CONFIG_MIPS32_O32 is not set |
| 4856 | +# CONFIG_MIPS32_N32 is not set |
| 4857 | +# CONFIG_BINFMT_ELF32 is not set |
| 4858 | +# CONFIG_BINFMT_MISC is not set |
| 4859 | +# CONFIG_OOM_KILLER is not set |
| 4860 | +CONFIG_CMDLINE_BOOL=y |
| 4861 | +CONFIG_CMDLINE="mem=96M" |
| 4862 | + |
| 4863 | +# |
| 4864 | +# Memory Technology Devices (MTD) |
| 4865 | +# |
| 4866 | +# CONFIG_MTD is not set |
| 4867 | + |
| 4868 | +# |
| 4869 | +# Parallel port support |
| 4870 | +# |
| 4871 | +# CONFIG_PARPORT is not set |
| 4872 | + |
| 4873 | +# |
| 4874 | +# Plug and Play configuration |
| 4875 | +# |
| 4876 | +# CONFIG_PNP is not set |
| 4877 | +# CONFIG_ISAPNP is not set |
| 4878 | + |
| 4879 | +# |
| 4880 | +# Block devices |
| 4881 | +# |
| 4882 | +# CONFIG_BLK_DEV_FD is not set |
| 4883 | +# CONFIG_BLK_DEV_XD is not set |
| 4884 | +# CONFIG_PARIDE is not set |
| 4885 | +# CONFIG_BLK_CPQ_DA is not set |
| 4886 | +# CONFIG_BLK_CPQ_CISS_DA is not set |
| 4887 | +# CONFIG_CISS_SCSI_TAPE is not set |
| 4888 | +# CONFIG_CISS_MONITOR_THREAD is not set |
| 4889 | +# CONFIG_BLK_DEV_DAC960 is not set |
| 4890 | +# CONFIG_BLK_DEV_UMEM is not set |
| 4891 | +# CONFIG_BLK_DEV_SX8 is not set |
| 4892 | +CONFIG_BLK_DEV_LOOP=y |
| 4893 | +# CONFIG_BLK_DEV_NBD is not set |
| 4894 | +# CONFIG_BLK_DEV_RAM is not set |
| 4895 | +# CONFIG_BLK_DEV_INITRD is not set |
| 4896 | +# CONFIG_BLK_STATS is not set |
| 4897 | + |
| 4898 | +# |
| 4899 | +# Multi-device support (RAID and LVM) |
| 4900 | +# |
| 4901 | +# CONFIG_MD is not set |
| 4902 | +# CONFIG_BLK_DEV_MD is not set |
| 4903 | +# CONFIG_MD_LINEAR is not set |
| 4904 | +# CONFIG_MD_RAID0 is not set |
| 4905 | +# CONFIG_MD_RAID1 is not set |
| 4906 | +# CONFIG_MD_RAID5 is not set |
| 4907 | +# CONFIG_MD_MULTIPATH is not set |
| 4908 | +# CONFIG_BLK_DEV_LVM is not set |
| 4909 | + |
| 4910 | +# |
| 4911 | +# Networking options |
| 4912 | +# |
| 4913 | +CONFIG_PACKET=y |
| 4914 | +# CONFIG_PACKET_MMAP is not set |
| 4915 | +# CONFIG_NETLINK_DEV is not set |
| 4916 | +CONFIG_NETFILTER=y |
| 4917 | +# CONFIG_NETFILTER_DEBUG is not set |
| 4918 | +CONFIG_FILTER=y |
| 4919 | +CONFIG_UNIX=y |
| 4920 | +CONFIG_INET=y |
| 4921 | +CONFIG_IP_MULTICAST=y |
| 4922 | +# CONFIG_IP_ADVANCED_ROUTER is not set |
| 4923 | +CONFIG_IP_PNP=y |
| 4924 | +# CONFIG_IP_PNP_DHCP is not set |
| 4925 | +CONFIG_IP_PNP_BOOTP=y |
| 4926 | +# CONFIG_IP_PNP_RARP is not set |
| 4927 | +# CONFIG_NET_IPIP is not set |
| 4928 | +# CONFIG_NET_IPGRE is not set |
| 4929 | +# CONFIG_IP_MROUTE is not set |
| 4930 | +# CONFIG_ARPD is not set |
| 4931 | +# CONFIG_INET_ECN is not set |
| 4932 | +# CONFIG_SYN_COOKIES is not set |
| 4933 | + |
| 4934 | +# |
| 4935 | +# IP: Netfilter Configuration |
| 4936 | +# |
| 4937 | +# CONFIG_IP_NF_CONNTRACK is not set |
| 4938 | +# CONFIG_IP_NF_QUEUE is not set |
| 4939 | +# CONFIG_IP_NF_IPTABLES is not set |
| 4940 | +# CONFIG_IP_NF_ARPTABLES is not set |
| 4941 | +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set |
| 4942 | +# CONFIG_IP_NF_COMPAT_IPFWADM is not set |
| 4943 | + |
| 4944 | +# |
| 4945 | +# IP: Virtual Server Configuration |
| 4946 | +# |
| 4947 | +# CONFIG_IP_VS is not set |
| 4948 | +# CONFIG_IPV6 is not set |
| 4949 | +# CONFIG_KHTTPD is not set |
| 4950 | + |
| 4951 | +# |
| 4952 | +# SCTP Configuration (EXPERIMENTAL) |
| 4953 | +# |
| 4954 | +# CONFIG_IP_SCTP is not set |
| 4955 | +# CONFIG_ATM is not set |
| 4956 | +# CONFIG_VLAN_8021Q is not set |
| 4957 | + |
| 4958 | +# |
| 4959 | +# |
| 4960 | +# |
| 4961 | +# CONFIG_IPX is not set |
| 4962 | +# CONFIG_ATALK is not set |
| 4963 | +# CONFIG_DECNET is not set |
| 4964 | +# CONFIG_BRIDGE is not set |
| 4965 | +# CONFIG_X25 is not set |
| 4966 | +# CONFIG_LAPB is not set |
| 4967 | +# CONFIG_LLC is not set |
| 4968 | +# CONFIG_NET_DIVERT is not set |
| 4969 | +# CONFIG_ECONET is not set |
| 4970 | +# CONFIG_WAN_ROUTER is not set |
| 4971 | +# CONFIG_NET_FASTROUTE is not set |
| 4972 | +# CONFIG_NET_HW_FLOWCONTROL is not set |
| 4973 | + |
| 4974 | +# |
| 4975 | +# QoS and/or fair queueing |
| 4976 | +# |
| 4977 | +# CONFIG_NET_SCHED is not set |
| 4978 | + |
| 4979 | +# |
| 4980 | +# Network testing |
| 4981 | +# |
| 4982 | +# CONFIG_NET_PKTGEN is not set |
| 4983 | + |
| 4984 | +# |
| 4985 | +# Telephony Support |
| 4986 | +# |
| 4987 | +# CONFIG_PHONE is not set |
| 4988 | +# CONFIG_PHONE_IXJ is not set |
| 4989 | +# CONFIG_PHONE_IXJ_PCMCIA is not set |
| 4990 | + |
| 4991 | +# |
| 4992 | +# ATA/IDE/MFM/RLL support |
| 4993 | +# |
| 4994 | +CONFIG_IDE=y |
| 4995 | + |
| 4996 | +# |
| 4997 | +# IDE, ATA and ATAPI Block devices |
| 4998 | +# |
| 4999 | +CONFIG_BLK_DEV_IDE=y |
| 5000 | + |
| 5001 | +# |
| 5002 | +# Please see Documentation/ide.txt for help/info on IDE drives |
| 5003 | +# |
| 5004 | +# CONFIG_BLK_DEV_HD_IDE is not set |
| 5005 | +# CONFIG_BLK_DEV_HD is not set |
| 5006 | +# CONFIG_BLK_DEV_IDE_SATA is not set |
| 5007 | +CONFIG_BLK_DEV_IDEDISK=y |
| 5008 | +CONFIG_IDEDISK_MULTI_MODE=y |
| 5009 | +CONFIG_IDEDISK_STROKE=y |
| 5010 | +CONFIG_BLK_DEV_IDECS=m |
| 5011 | +# CONFIG_BLK_DEV_DELKIN is not set |
| 5012 | +# CONFIG_BLK_DEV_IDECD is not set |
| 5013 | +# CONFIG_BLK_DEV_IDETAPE is not set |
| 5014 | +# CONFIG_BLK_DEV_IDEFLOPPY is not set |
| 5015 | +# CONFIG_BLK_DEV_IDESCSI is not set |
| 5016 | +# CONFIG_IDE_TASK_IOCTL is not set |
| 5017 | + |
| 5018 | +# |
| 5019 | +# IDE chipset support/bugfixes |
| 5020 | +# |
| 5021 | +# CONFIG_BLK_DEV_CMD640 is not set |
| 5022 | +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set |
| 5023 | +# CONFIG_BLK_DEV_ISAPNP is not set |
| 5024 | +# CONFIG_BLK_DEV_IDEPCI is not set |
| 5025 | +# CONFIG_IDE_CHIPSETS is not set |
| 5026 | +# CONFIG_IDEDMA_AUTO is not set |
| 5027 | +# CONFIG_DMA_NONPCI is not set |
| 5028 | +# CONFIG_BLK_DEV_ATARAID is not set |
| 5029 | +# CONFIG_BLK_DEV_ATARAID_PDC is not set |
| 5030 | +# CONFIG_BLK_DEV_ATARAID_HPT is not set |
| 5031 | +# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set |
| 5032 | +# CONFIG_BLK_DEV_ATARAID_SII is not set |
| 5033 | + |
| 5034 | +# |
| 5035 | +# SCSI support |
| 5036 | +# |
| 5037 | +CONFIG_SCSI=y |
| 5038 | + |
| 5039 | +# |
| 5040 | +# SCSI support type (disk, tape, CD-ROM) |
| 5041 | +# |
| 5042 | +CONFIG_BLK_DEV_SD=y |
| 5043 | +CONFIG_SD_EXTRA_DEVS=40 |
| 5044 | +CONFIG_CHR_DEV_ST=y |
| 5045 | +# CONFIG_CHR_DEV_OSST is not set |
| 5046 | +CONFIG_BLK_DEV_SR=y |
| 5047 | +# CONFIG_BLK_DEV_SR_VENDOR is not set |
| 5048 | +CONFIG_SR_EXTRA_DEVS=2 |
| 5049 | +# CONFIG_CHR_DEV_SG is not set |
| 5050 | + |
| 5051 | +# |
| 5052 | +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs |
| 5053 | +# |
| 5054 | +# CONFIG_SCSI_DEBUG_QUEUES is not set |
| 5055 | +# CONFIG_SCSI_MULTI_LUN is not set |
| 5056 | +CONFIG_SCSI_CONSTANTS=y |
| 5057 | +# CONFIG_SCSI_LOGGING is not set |
| 5058 | + |
| 5059 | +# |
| 5060 | +# SCSI low-level drivers |
| 5061 | +# |
| 5062 | +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 5063 | +# CONFIG_SCSI_7000FASST is not set |
| 5064 | +# CONFIG_SCSI_ACARD is not set |
| 5065 | +# CONFIG_SCSI_AHA152X is not set |
| 5066 | +# CONFIG_SCSI_AHA1542 is not set |
| 5067 | +# CONFIG_SCSI_AHA1740 is not set |
| 5068 | +# CONFIG_SCSI_AACRAID is not set |
| 5069 | +# CONFIG_SCSI_AIC7XXX is not set |
| 5070 | +# CONFIG_SCSI_AIC79XX is not set |
| 5071 | +# CONFIG_SCSI_AIC7XXX_OLD is not set |
| 5072 | +# CONFIG_SCSI_DPT_I2O is not set |
| 5073 | +# CONFIG_SCSI_ADVANSYS is not set |
| 5074 | +# CONFIG_SCSI_IN2000 is not set |
| 5075 | +# CONFIG_SCSI_AM53C974 is not set |
| 5076 | +# CONFIG_SCSI_MEGARAID is not set |
| 5077 | +# CONFIG_SCSI_MEGARAID2 is not set |
| 5078 | +# CONFIG_SCSI_SATA is not set |
| 5079 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 5080 | +# CONFIG_SCSI_SATA_SVW is not set |
| 5081 | +# CONFIG_SCSI_ATA_PIIX is not set |
| 5082 | +# CONFIG_SCSI_SATA_NV is not set |
| 5083 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 5084 | +# CONFIG_SCSI_SATA_PROMISE is not set |
| 5085 | +# CONFIG_SCSI_SATA_SX4 is not set |
| 5086 | +# CONFIG_SCSI_SATA_SIL is not set |
| 5087 | +# CONFIG_SCSI_SATA_SIS is not set |
| 5088 | +# CONFIG_SCSI_SATA_ULI is not set |
| 5089 | +# CONFIG_SCSI_SATA_VIA is not set |
| 5090 | +# CONFIG_SCSI_SATA_VITESSE is not set |
| 5091 | +# CONFIG_SCSI_BUSLOGIC is not set |
| 5092 | +# CONFIG_SCSI_CPQFCTS is not set |
| 5093 | +# CONFIG_SCSI_DMX3191D is not set |
| 5094 | +# CONFIG_SCSI_DTC3280 is not set |
| 5095 | +# CONFIG_SCSI_EATA is not set |
| 5096 | +# CONFIG_SCSI_EATA_DMA is not set |
| 5097 | +# CONFIG_SCSI_EATA_PIO is not set |
| 5098 | +# CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 5099 | +# CONFIG_SCSI_GDTH is not set |
| 5100 | +# CONFIG_SCSI_GENERIC_NCR5380 is not set |
| 5101 | +# CONFIG_SCSI_INITIO is not set |
| 5102 | +# CONFIG_SCSI_INIA100 is not set |
| 5103 | +# CONFIG_SCSI_NCR53C406A is not set |
| 5104 | +# CONFIG_SCSI_NCR53C7xx is not set |
| 5105 | +# CONFIG_SCSI_SYM53C8XX_2 is not set |
| 5106 | +# CONFIG_SCSI_NCR53C8XX is not set |
| 5107 | +# CONFIG_SCSI_SYM53C8XX is not set |
| 5108 | +# CONFIG_SCSI_PAS16 is not set |
| 5109 | +# CONFIG_SCSI_PCI2000 is not set |
| 5110 | +# CONFIG_SCSI_PCI2220I is not set |
| 5111 | +# CONFIG_SCSI_PSI240I is not set |
| 5112 | +# CONFIG_SCSI_QLOGIC_FAS is not set |
| 5113 | +# CONFIG_SCSI_QLOGIC_ISP is not set |
| 5114 | +# CONFIG_SCSI_QLOGIC_FC is not set |
| 5115 | +# CONFIG_SCSI_QLOGIC_1280 is not set |
| 5116 | +# CONFIG_SCSI_SIM710 is not set |
| 5117 | +# CONFIG_SCSI_SYM53C416 is not set |
| 5118 | +# CONFIG_SCSI_DC390T is not set |
| 5119 | +# CONFIG_SCSI_T128 is not set |
| 5120 | +# CONFIG_SCSI_U14_34F is not set |
| 5121 | +# CONFIG_SCSI_NSP32 is not set |
| 5122 | +# CONFIG_SCSI_DEBUG is not set |
| 5123 | + |
| 5124 | +# |
| 5125 | +# PCMCIA SCSI adapter support |
| 5126 | +# |
| 5127 | +# CONFIG_SCSI_PCMCIA is not set |
| 5128 | + |
| 5129 | +# |
| 5130 | +# Fusion MPT device support |
| 5131 | +# |
| 5132 | +# CONFIG_FUSION is not set |
| 5133 | +# CONFIG_FUSION_BOOT is not set |
| 5134 | +# CONFIG_FUSION_ISENSE is not set |
| 5135 | +# CONFIG_FUSION_CTL is not set |
| 5136 | +# CONFIG_FUSION_LAN is not set |
| 5137 | + |
| 5138 | +# |
| 5139 | +# IEEE 1394 (FireWire) support (EXPERIMENTAL) |
| 5140 | +# |
| 5141 | +# CONFIG_IEEE1394 is not set |
| 5142 | + |
| 5143 | +# |
| 5144 | +# I2O device support |
| 5145 | +# |
| 5146 | +# CONFIG_I2O is not set |
| 5147 | +# CONFIG_I2O_PCI is not set |
| 5148 | +# CONFIG_I2O_BLOCK is not set |
| 5149 | +# CONFIG_I2O_LAN is not set |
| 5150 | +# CONFIG_I2O_SCSI is not set |
| 5151 | +# CONFIG_I2O_PROC is not set |
| 5152 | + |
| 5153 | +# |
| 5154 | +# Network device support |
| 5155 | +# |
| 5156 | +CONFIG_NETDEVICES=y |
| 5157 | + |
| 5158 | +# |
| 5159 | +# ARCnet devices |
| 5160 | +# |
| 5161 | +# CONFIG_ARCNET is not set |
| 5162 | +# CONFIG_DUMMY is not set |
| 5163 | +# CONFIG_BONDING is not set |
| 5164 | +# CONFIG_EQUALIZER is not set |
| 5165 | +# CONFIG_TUN is not set |
| 5166 | +# CONFIG_ETHERTAP is not set |
| 5167 | + |
| 5168 | +# |
| 5169 | +# Ethernet (10 or 100Mbit) |
| 5170 | +# |
| 5171 | +CONFIG_NET_ETHERNET=y |
| 5172 | +# CONFIG_SUNLANCE is not set |
| 5173 | +# CONFIG_HAPPYMEAL is not set |
| 5174 | +# CONFIG_SUNBMAC is not set |
| 5175 | +# CONFIG_SUNQE is not set |
| 5176 | +# CONFIG_SUNGEM is not set |
| 5177 | +# CONFIG_NET_VENDOR_3COM is not set |
| 5178 | +# CONFIG_LANCE is not set |
| 5179 | +# CONFIG_NET_VENDOR_SMC is not set |
| 5180 | +# CONFIG_NET_VENDOR_RACAL is not set |
| 5181 | +# CONFIG_HP100 is not set |
| 5182 | +# CONFIG_NET_ISA is not set |
| 5183 | +# CONFIG_NET_PCI is not set |
| 5184 | +# CONFIG_NET_POCKET is not set |
| 5185 | + |
| 5186 | +# |
| 5187 | +# Ethernet (1000 Mbit) |
| 5188 | +# |
| 5189 | +# CONFIG_ACENIC is not set |
| 5190 | +# CONFIG_DL2K is not set |
| 5191 | +# CONFIG_E1000 is not set |
| 5192 | +# CONFIG_MYRI_SBUS is not set |
| 5193 | +# CONFIG_NS83820 is not set |
| 5194 | +# CONFIG_HAMACHI is not set |
| 5195 | +# CONFIG_YELLOWFIN is not set |
| 5196 | +# CONFIG_R8169 is not set |
| 5197 | +# CONFIG_SK98LIN is not set |
| 5198 | +# CONFIG_TIGON3 is not set |
| 5199 | +# CONFIG_FDDI is not set |
| 5200 | +# CONFIG_HIPPI is not set |
| 5201 | +# CONFIG_PLIP is not set |
| 5202 | +# CONFIG_PPP is not set |
| 5203 | +# CONFIG_SLIP is not set |
| 5204 | + |
| 5205 | +# |
| 5206 | +# Wireless LAN (non-hamradio) |
| 5207 | +# |
| 5208 | +# CONFIG_NET_RADIO is not set |
| 5209 | + |
| 5210 | +# |
| 5211 | +# Token Ring devices |
| 5212 | +# |
| 5213 | +# CONFIG_TR is not set |
| 5214 | +# CONFIG_NET_FC is not set |
| 5215 | +# CONFIG_RCPCI is not set |
| 5216 | +# CONFIG_SHAPER is not set |
| 5217 | + |
| 5218 | +# |
| 5219 | +# Wan interfaces |
| 5220 | +# |
| 5221 | +# CONFIG_WAN is not set |
| 5222 | + |
| 5223 | +# |
| 5224 | +# PCMCIA network device support |
| 5225 | +# |
| 5226 | +# CONFIG_NET_PCMCIA is not set |
| 5227 | + |
| 5228 | +# |
| 5229 | +# Amateur Radio support |
| 5230 | +# |
| 5231 | +# CONFIG_HAMRADIO is not set |
| 5232 | + |
| 5233 | +# |
| 5234 | +# IrDA (infrared) support |
| 5235 | +# |
| 5236 | +# CONFIG_IRDA is not set |
| 5237 | + |
| 5238 | +# |
| 5239 | +# ISDN subsystem |
| 5240 | +# |
| 5241 | +# CONFIG_ISDN is not set |
| 5242 | + |
| 5243 | +# |
| 5244 | +# Input core support |
| 5245 | +# |
| 5246 | +CONFIG_INPUT=y |
| 5247 | +CONFIG_INPUT_KEYBDEV=y |
| 5248 | +CONFIG_INPUT_MOUSEDEV=y |
| 5249 | +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 5250 | +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 5251 | +# CONFIG_INPUT_JOYDEV is not set |
| 5252 | +CONFIG_INPUT_EVDEV=y |
| 5253 | +# CONFIG_INPUT_UINPUT is not set |
| 5254 | + |
| 5255 | +# |
| 5256 | +# Character devices |
| 5257 | +# |
| 5258 | +CONFIG_VT=y |
| 5259 | +# CONFIG_VT_CONSOLE is not set |
| 5260 | +# CONFIG_SERIAL is not set |
| 5261 | +# CONFIG_SERIAL_EXTENDED is not set |
| 5262 | +CONFIG_SERIAL_NONSTANDARD=y |
| 5263 | +# CONFIG_COMPUTONE is not set |
| 5264 | +# CONFIG_ROCKETPORT is not set |
| 5265 | +# CONFIG_CYCLADES is not set |
| 5266 | +# CONFIG_DIGIEPCA is not set |
| 5267 | +# CONFIG_DIGI is not set |
| 5268 | +# CONFIG_ESPSERIAL is not set |
| 5269 | +# CONFIG_MOXA_INTELLIO is not set |
| 5270 | +# CONFIG_MOXA_SMARTIO is not set |
| 5271 | +# CONFIG_ISI is not set |
| 5272 | +# CONFIG_SYNCLINK is not set |
| 5273 | +# CONFIG_SYNCLINKMP is not set |
| 5274 | +# CONFIG_N_HDLC is not set |
| 5275 | +# CONFIG_RISCOM8 is not set |
| 5276 | +# CONFIG_SPECIALIX is not set |
| 5277 | +# CONFIG_SX is not set |
| 5278 | +# CONFIG_RIO is not set |
| 5279 | +# CONFIG_STALDRV is not set |
| 5280 | +# CONFIG_SERIAL_TX3912 is not set |
| 5281 | +# CONFIG_SERIAL_TX3912_CONSOLE is not set |
| 5282 | +# CONFIG_SERIAL_TXX9 is not set |
| 5283 | +# CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 5284 | +# CONFIG_TXX927_SERIAL is not set |
| 5285 | +CONFIG_UNIX98_PTYS=y |
| 5286 | +CONFIG_UNIX98_PTY_COUNT=256 |
| 5287 | + |
| 5288 | +# |
| 5289 | +# I2C support |
| 5290 | +# |
| 5291 | +# CONFIG_I2C is not set |
| 5292 | + |
| 5293 | +# |
| 5294 | +# Mice |
| 5295 | +# |
| 5296 | +# CONFIG_BUSMOUSE is not set |
| 5297 | +# CONFIG_MOUSE is not set |
| 5298 | + |
| 5299 | +# |
| 5300 | +# Joysticks |
| 5301 | +# |
| 5302 | +# CONFIG_INPUT_GAMEPORT is not set |
| 5303 | +# CONFIG_INPUT_NS558 is not set |
| 5304 | +# CONFIG_INPUT_LIGHTNING is not set |
| 5305 | +# CONFIG_INPUT_PCIGAME is not set |
| 5306 | +# CONFIG_INPUT_CS461X is not set |
| 5307 | +# CONFIG_INPUT_EMU10K1 is not set |
| 5308 | +# CONFIG_INPUT_SERIO is not set |
| 5309 | +# CONFIG_INPUT_SERPORT is not set |
| 5310 | + |
| 5311 | +# |
| 5312 | +# Joysticks |
| 5313 | +# |
| 5314 | +# CONFIG_INPUT_ANALOG is not set |
| 5315 | +# CONFIG_INPUT_A3D is not set |
| 5316 | +# CONFIG_INPUT_ADI is not set |
| 5317 | +# CONFIG_INPUT_COBRA is not set |
| 5318 | +# CONFIG_INPUT_GF2K is not set |
| 5319 | +# CONFIG_INPUT_GRIP is not set |
| 5320 | +# CONFIG_INPUT_INTERACT is not set |
| 5321 | +# CONFIG_INPUT_TMDC is not set |
| 5322 | +# CONFIG_INPUT_SIDEWINDER is not set |
| 5323 | +# CONFIG_INPUT_IFORCE_USB is not set |
| 5324 | +# CONFIG_INPUT_IFORCE_232 is not set |
| 5325 | +# CONFIG_INPUT_WARRIOR is not set |
| 5326 | +# CONFIG_INPUT_MAGELLAN is not set |
| 5327 | +# CONFIG_INPUT_SPACEORB is not set |
| 5328 | +# CONFIG_INPUT_SPACEBALL is not set |
| 5329 | +# CONFIG_INPUT_STINGER is not set |
| 5330 | +# CONFIG_INPUT_DB9 is not set |
| 5331 | +# CONFIG_INPUT_GAMECON is not set |
| 5332 | +# CONFIG_INPUT_TURBOGRAFX is not set |
| 5333 | +# CONFIG_QIC02_TAPE is not set |
| 5334 | +# CONFIG_IPMI_HANDLER is not set |
| 5335 | +# CONFIG_IPMI_PANIC_EVENT is not set |
| 5336 | +# CONFIG_IPMI_DEVICE_INTERFACE is not set |
| 5337 | +# CONFIG_IPMI_KCS is not set |
| 5338 | +# CONFIG_IPMI_WATCHDOG is not set |
| 5339 | + |
| 5340 | +# |
| 5341 | +# Watchdog Cards |
| 5342 | +# |
| 5343 | +# CONFIG_WATCHDOG is not set |
| 5344 | +# CONFIG_SCx200 is not set |
| 5345 | +# CONFIG_SCx200_GPIO is not set |
| 5346 | +# CONFIG_AMD_PM768 is not set |
| 5347 | +# CONFIG_NVRAM is not set |
| 5348 | +# CONFIG_RTC is not set |
| 5349 | +# CONFIG_DTLK is not set |
| 5350 | +# CONFIG_R3964 is not set |
| 5351 | +# CONFIG_APPLICOM is not set |
| 5352 | + |
| 5353 | +# |
| 5354 | +# Ftape, the floppy tape device driver |
| 5355 | +# |
| 5356 | +# CONFIG_FTAPE is not set |
| 5357 | +# CONFIG_AGP is not set |
| 5358 | + |
| 5359 | +# |
| 5360 | +# Direct Rendering Manager (XFree86 DRI support) |
| 5361 | +# |
| 5362 | +# CONFIG_DRM is not set |
| 5363 | + |
| 5364 | +# |
| 5365 | +# PCMCIA character devices |
| 5366 | +# |
| 5367 | +# CONFIG_PCMCIA_SERIAL_CS is not set |
| 5368 | +# CONFIG_SYNCLINK_CS is not set |
| 5369 | + |
| 5370 | +# |
| 5371 | +# File systems |
| 5372 | +# |
| 5373 | +# CONFIG_QUOTA is not set |
| 5374 | +# CONFIG_QFMT_V2 is not set |
| 5375 | +CONFIG_AUTOFS_FS=y |
| 5376 | +# CONFIG_AUTOFS4_FS is not set |
| 5377 | +# CONFIG_REISERFS_FS is not set |
| 5378 | +# CONFIG_REISERFS_CHECK is not set |
| 5379 | +# CONFIG_REISERFS_PROC_INFO is not set |
| 5380 | +# CONFIG_ADFS_FS is not set |
| 5381 | +# CONFIG_ADFS_FS_RW is not set |
| 5382 | +# CONFIG_AFFS_FS is not set |
| 5383 | +# CONFIG_HFS_FS is not set |
| 5384 | +# CONFIG_HFSPLUS_FS is not set |
| 5385 | +# CONFIG_BEFS_FS is not set |
| 5386 | +# CONFIG_BEFS_DEBUG is not set |
| 5387 | +# CONFIG_BFS_FS is not set |
| 5388 | +CONFIG_EXT3_FS=y |
| 5389 | +CONFIG_JBD=y |
| 5390 | +# CONFIG_JBD_DEBUG is not set |
| 5391 | +CONFIG_FAT_FS=y |
| 5392 | +CONFIG_MSDOS_FS=y |
| 5393 | +# CONFIG_UMSDOS_FS is not set |
| 5394 | +CONFIG_VFAT_FS=y |
| 5395 | +# CONFIG_EFS_FS is not set |
| 5396 | +# CONFIG_JFFS_FS is not set |
| 5397 | +# CONFIG_JFFS2_FS is not set |
| 5398 | +# CONFIG_CRAMFS is not set |
| 5399 | +CONFIG_TMPFS=y |
| 5400 | +CONFIG_RAMFS=y |
| 5401 | +# CONFIG_ISO9660_FS is not set |
| 5402 | +# CONFIG_JOLIET is not set |
| 5403 | +# CONFIG_ZISOFS is not set |
| 5404 | +# CONFIG_JFS_FS is not set |
| 5405 | +# CONFIG_JFS_DEBUG is not set |
| 5406 | +# CONFIG_JFS_STATISTICS is not set |
| 5407 | +# CONFIG_MINIX_FS is not set |
| 5408 | +# CONFIG_VXFS_FS is not set |
| 5409 | +# CONFIG_NTFS_FS is not set |
| 5410 | +# CONFIG_NTFS_RW is not set |
| 5411 | +# CONFIG_HPFS_FS is not set |
| 5412 | +CONFIG_PROC_FS=y |
| 5413 | +# CONFIG_DEVFS_FS is not set |
| 5414 | +# CONFIG_DEVFS_MOUNT is not set |
| 5415 | +# CONFIG_DEVFS_DEBUG is not set |
| 5416 | +CONFIG_DEVPTS_FS=y |
| 5417 | +# CONFIG_QNX4FS_FS is not set |
| 5418 | +# CONFIG_QNX4FS_RW is not set |
| 5419 | +# CONFIG_ROMFS_FS is not set |
| 5420 | +CONFIG_EXT2_FS=y |
| 5421 | +# CONFIG_SYSV_FS is not set |
| 5422 | +# CONFIG_UDF_FS is not set |
| 5423 | +# CONFIG_UDF_RW is not set |
| 5424 | +# CONFIG_UFS_FS is not set |
| 5425 | +# CONFIG_UFS_FS_WRITE is not set |
| 5426 | +# CONFIG_XFS_FS is not set |
| 5427 | +# CONFIG_XFS_QUOTA is not set |
| 5428 | +# CONFIG_XFS_RT is not set |
| 5429 | +# CONFIG_XFS_TRACE is not set |
| 5430 | +# CONFIG_XFS_DEBUG is not set |
| 5431 | + |
| 5432 | +# |
| 5433 | +# Network File Systems |
| 5434 | +# |
| 5435 | +# CONFIG_CODA_FS is not set |
| 5436 | +# CONFIG_INTERMEZZO_FS is not set |
| 5437 | +CONFIG_NFS_FS=y |
| 5438 | +CONFIG_NFS_V3=y |
| 5439 | +# CONFIG_NFS_DIRECTIO is not set |
| 5440 | +CONFIG_ROOT_NFS=y |
| 5441 | +# CONFIG_NFSD is not set |
| 5442 | +# CONFIG_NFSD_V3 is not set |
| 5443 | +# CONFIG_NFSD_TCP is not set |
| 5444 | +CONFIG_SUNRPC=y |
| 5445 | +CONFIG_LOCKD=y |
| 5446 | +CONFIG_LOCKD_V4=y |
| 5447 | +# CONFIG_SMB_FS is not set |
| 5448 | +# CONFIG_NCP_FS is not set |
| 5449 | +# CONFIG_NCPFS_PACKET_SIGNING is not set |
| 5450 | +# CONFIG_NCPFS_IOCTL_LOCKING is not set |
| 5451 | +# CONFIG_NCPFS_STRONG is not set |
| 5452 | +# CONFIG_NCPFS_NFS_NS is not set |
| 5453 | +# CONFIG_NCPFS_OS2_NS is not set |
| 5454 | +# CONFIG_NCPFS_SMALLDOS is not set |
| 5455 | +# CONFIG_NCPFS_NLS is not set |
| 5456 | +# CONFIG_NCPFS_EXTRAS is not set |
| 5457 | +# CONFIG_ZISOFS_FS is not set |
| 5458 | + |
| 5459 | +# |
| 5460 | +# Partition Types |
| 5461 | +# |
| 5462 | +# CONFIG_PARTITION_ADVANCED is not set |
| 5463 | +CONFIG_MSDOS_PARTITION=y |
| 5464 | +# CONFIG_SMB_NLS is not set |
| 5465 | +CONFIG_NLS=y |
| 5466 | + |
| 5467 | +# |
| 5468 | +# Native Language Support |
| 5469 | +# |
| 5470 | +CONFIG_NLS_DEFAULT="iso8859-1" |
| 5471 | +# CONFIG_NLS_CODEPAGE_437 is not set |
| 5472 | +# CONFIG_NLS_CODEPAGE_737 is not set |
| 5473 | +# CONFIG_NLS_CODEPAGE_775 is not set |
| 5474 | +# CONFIG_NLS_CODEPAGE_850 is not set |
| 5475 | +# CONFIG_NLS_CODEPAGE_852 is not set |
| 5476 | +# CONFIG_NLS_CODEPAGE_855 is not set |
| 5477 | +# CONFIG_NLS_CODEPAGE_857 is not set |
| 5478 | +# CONFIG_NLS_CODEPAGE_860 is not set |
| 5479 | +# CONFIG_NLS_CODEPAGE_861 is not set |
| 5480 | +# CONFIG_NLS_CODEPAGE_862 is not set |
| 5481 | +# CONFIG_NLS_CODEPAGE_863 is not set |
| 5482 | +# CONFIG_NLS_CODEPAGE_864 is not set |
| 5483 | +# CONFIG_NLS_CODEPAGE_865 is not set |
| 5484 | +# CONFIG_NLS_CODEPAGE_866 is not set |
| 5485 | +# CONFIG_NLS_CODEPAGE_869 is not set |
| 5486 | +# CONFIG_NLS_CODEPAGE_936 is not set |
| 5487 | +# CONFIG_NLS_CODEPAGE_950 is not set |
| 5488 | +# CONFIG_NLS_CODEPAGE_932 is not set |
| 5489 | +# CONFIG_NLS_CODEPAGE_949 is not set |
| 5490 | +# CONFIG_NLS_CODEPAGE_874 is not set |
| 5491 | +# CONFIG_NLS_ISO8859_8 is not set |
| 5492 | +# CONFIG_NLS_CODEPAGE_1250 is not set |
| 5493 | +# CONFIG_NLS_CODEPAGE_1251 is not set |
| 5494 | +# CONFIG_NLS_ISO8859_1 is not set |
| 5495 | +# CONFIG_NLS_ISO8859_2 is not set |
| 5496 | +# CONFIG_NLS_ISO8859_3 is not set |
| 5497 | +# CONFIG_NLS_ISO8859_4 is not set |
| 5498 | +# CONFIG_NLS_ISO8859_5 is not set |
| 5499 | +# CONFIG_NLS_ISO8859_6 is not set |
| 5500 | +# CONFIG_NLS_ISO8859_7 is not set |
| 5501 | +# CONFIG_NLS_ISO8859_9 is not set |
| 5502 | +# CONFIG_NLS_ISO8859_13 is not set |
| 5503 | +# CONFIG_NLS_ISO8859_14 is not set |
| 5504 | +# CONFIG_NLS_ISO8859_15 is not set |
| 5505 | +# CONFIG_NLS_KOI8_R is not set |
| 5506 | +# CONFIG_NLS_KOI8_U is not set |
| 5507 | +# CONFIG_NLS_UTF8 is not set |
| 5508 | + |
| 5509 | +# |
| 5510 | +# Multimedia devices |
| 5511 | +# |
| 5512 | +# CONFIG_VIDEO_DEV is not set |
| 5513 | + |
| 5514 | +# |
| 5515 | +# Console drivers |
| 5516 | +# |
| 5517 | +# CONFIG_VGA_CONSOLE is not set |
| 5518 | +# CONFIG_MDA_CONSOLE is not set |
| 5519 | + |
| 5520 | +# |
| 5521 | +# Frame-buffer support |
| 5522 | +# |
| 5523 | +CONFIG_FB=y |
| 5524 | +CONFIG_DUMMY_CONSOLE=y |
| 5525 | +# CONFIG_FB_RIVA is not set |
| 5526 | +# CONFIG_FB_CLGEN is not set |
| 5527 | +# CONFIG_FB_PM2 is not set |
| 5528 | +# CONFIG_FB_PM3 is not set |
| 5529 | +# CONFIG_FB_CYBER2000 is not set |
| 5530 | +# CONFIG_FB_MATROX is not set |
| 5531 | +# CONFIG_FB_ATY is not set |
| 5532 | +# CONFIG_FB_RADEON is not set |
| 5533 | +# CONFIG_FB_ATY128 is not set |
| 5534 | +# CONFIG_FB_INTEL is not set |
| 5535 | +# CONFIG_FB_SIS is not set |
| 5536 | +# CONFIG_FB_NEOMAGIC is not set |
| 5537 | +# CONFIG_FB_3DFX is not set |
| 5538 | +# CONFIG_FB_VOODOO1 is not set |
| 5539 | +# CONFIG_FB_TRIDENT is not set |
| 5540 | +# CONFIG_FB_E1356 is not set |
| 5541 | +# CONFIG_FB_IT8181 is not set |
| 5542 | +# CONFIG_FB_VIRTUAL is not set |
| 5543 | +CONFIG_FBCON_ADVANCED=y |
| 5544 | +# CONFIG_FBCON_MFB is not set |
| 5545 | +# CONFIG_FBCON_CFB2 is not set |
| 5546 | +# CONFIG_FBCON_CFB4 is not set |
| 5547 | +# CONFIG_FBCON_CFB8 is not set |
| 5548 | +CONFIG_FBCON_CFB16=y |
| 5549 | +# CONFIG_FBCON_CFB24 is not set |
| 5550 | +CONFIG_FBCON_CFB32=y |
| 5551 | +# CONFIG_FBCON_AFB is not set |
| 5552 | +# CONFIG_FBCON_ILBM is not set |
| 5553 | +# CONFIG_FBCON_IPLAN2P2 is not set |
| 5554 | +# CONFIG_FBCON_IPLAN2P4 is not set |
| 5555 | +# CONFIG_FBCON_IPLAN2P8 is not set |
| 5556 | +# CONFIG_FBCON_MAC is not set |
| 5557 | +# CONFIG_FBCON_VGA_PLANES is not set |
| 5558 | +# CONFIG_FBCON_VGA is not set |
| 5559 | +# CONFIG_FBCON_HGA is not set |
| 5560 | +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set |
| 5561 | +CONFIG_FBCON_FONTS=y |
| 5562 | +CONFIG_FONT_8x8=y |
| 5563 | +CONFIG_FONT_8x16=y |
| 5564 | +# CONFIG_FONT_SUN8x16 is not set |
| 5565 | +# CONFIG_FONT_SUN12x22 is not set |
| 5566 | +# CONFIG_FONT_6x11 is not set |
| 5567 | +# CONFIG_FONT_PEARL_8x8 is not set |
| 5568 | +# CONFIG_FONT_ACORN_8x8 is not set |
| 5569 | + |
| 5570 | +# |
| 5571 | +# Sound |
| 5572 | +# |
| 5573 | +CONFIG_SOUND=y |
| 5574 | +# CONFIG_SOUND_ALI5455 is not set |
| 5575 | +# CONFIG_SOUND_BT878 is not set |
| 5576 | +# CONFIG_SOUND_CMPCI is not set |
| 5577 | +# CONFIG_SOUND_EMU10K1 is not set |
| 5578 | +# CONFIG_MIDI_EMU10K1 is not set |
| 5579 | +# CONFIG_SOUND_FUSION is not set |
| 5580 | +# CONFIG_SOUND_CS4281 is not set |
| 5581 | +# CONFIG_SOUND_ES1370 is not set |
| 5582 | +# CONFIG_SOUND_ES1371 is not set |
| 5583 | +# CONFIG_SOUND_ESSSOLO1 is not set |
| 5584 | +# CONFIG_SOUND_MAESTRO is not set |
| 5585 | +# CONFIG_SOUND_MAESTRO3 is not set |
| 5586 | +# CONFIG_SOUND_FORTE is not set |
| 5587 | +# CONFIG_SOUND_ICH is not set |
| 5588 | +# CONFIG_SOUND_RME96XX is not set |
| 5589 | +# CONFIG_SOUND_SONICVIBES is not set |
| 5590 | +# CONFIG_SOUND_TRIDENT is not set |
| 5591 | +# CONFIG_SOUND_MSNDCLAS is not set |
| 5592 | +# CONFIG_SOUND_MSNDPIN is not set |
| 5593 | +# CONFIG_SOUND_VIA82CXXX is not set |
| 5594 | +# CONFIG_MIDI_VIA82CXXX is not set |
| 5595 | +# CONFIG_SOUND_OSS is not set |
| 5596 | +# CONFIG_SOUND_TVMIXER is not set |
| 5597 | +# CONFIG_SOUND_AD1980 is not set |
| 5598 | +# CONFIG_SOUND_WM97XX is not set |
| 5599 | + |
| 5600 | +# |
| 5601 | +# USB support |
| 5602 | +# |
| 5603 | +CONFIG_USB=y |
| 5604 | +# CONFIG_USB_DEBUG is not set |
| 5605 | + |
| 5606 | +# |
| 5607 | +# Miscellaneous USB options |
| 5608 | +# |
| 5609 | +CONFIG_USB_DEVICEFS=y |
| 5610 | +# CONFIG_USB_BANDWIDTH is not set |
| 5611 | + |
| 5612 | +# |
| 5613 | +# USB Host Controller Drivers |
| 5614 | +# |
| 5615 | +# CONFIG_USB_EHCI_HCD is not set |
| 5616 | +# CONFIG_USB_UHCI is not set |
| 5617 | +# CONFIG_USB_UHCI_ALT is not set |
| 5618 | +CONFIG_USB_OHCI=y |
| 5619 | + |
| 5620 | +# |
| 5621 | +# USB Device Class drivers |
| 5622 | +# |
| 5623 | +# CONFIG_USB_AUDIO is not set |
| 5624 | +# CONFIG_USB_EMI26 is not set |
| 5625 | +# CONFIG_USB_BLUETOOTH is not set |
| 5626 | +# CONFIG_USB_MIDI is not set |
| 5627 | +CONFIG_USB_STORAGE=y |
| 5628 | +# CONFIG_USB_STORAGE_DEBUG is not set |
| 5629 | +# CONFIG_USB_STORAGE_DATAFAB is not set |
| 5630 | +# CONFIG_USB_STORAGE_FREECOM is not set |
| 5631 | +# CONFIG_USB_STORAGE_ISD200 is not set |
| 5632 | +# CONFIG_USB_STORAGE_DPCM is not set |
| 5633 | +# CONFIG_USB_STORAGE_HP8200e is not set |
| 5634 | +# CONFIG_USB_STORAGE_SDDR09 is not set |
| 5635 | +# CONFIG_USB_STORAGE_SDDR55 is not set |
| 5636 | +# CONFIG_USB_STORAGE_JUMPSHOT is not set |
| 5637 | +# CONFIG_USB_ACM is not set |
| 5638 | +# CONFIG_USB_PRINTER is not set |
| 5639 | + |
| 5640 | +# |
| 5641 | +# USB Human Interface Devices (HID) |
| 5642 | +# |
| 5643 | +CONFIG_USB_HID=y |
| 5644 | +CONFIG_USB_HIDINPUT=y |
| 5645 | +CONFIG_USB_HIDDEV=y |
| 5646 | +# CONFIG_USB_AIPTEK is not set |
| 5647 | +# CONFIG_USB_WACOM is not set |
| 5648 | +# CONFIG_USB_KBTAB is not set |
| 5649 | +# CONFIG_USB_POWERMATE is not set |
| 5650 | + |
| 5651 | +# |
| 5652 | +# USB Imaging devices |
| 5653 | +# |
| 5654 | +# CONFIG_USB_DC2XX is not set |
| 5655 | +# CONFIG_USB_MDC800 is not set |
| 5656 | +# CONFIG_USB_SCANNER is not set |
| 5657 | +# CONFIG_USB_MICROTEK is not set |
| 5658 | +# CONFIG_USB_HPUSBSCSI is not set |
| 5659 | + |
| 5660 | +# |
| 5661 | +# USB Multimedia devices |
| 5662 | +# |
| 5663 | + |
| 5664 | +# |
| 5665 | +# Video4Linux support is needed for USB Multimedia device support |
| 5666 | +# |
| 5667 | + |
| 5668 | +# |
| 5669 | +# USB Network adaptors |
| 5670 | +# |
| 5671 | +# CONFIG_USB_PEGASUS is not set |
| 5672 | +# CONFIG_USB_RTL8150 is not set |
| 5673 | +# CONFIG_USB_KAWETH is not set |
| 5674 | +# CONFIG_USB_CATC is not set |
| 5675 | +# CONFIG_USB_CDCETHER is not set |
| 5676 | +# CONFIG_USB_USBNET is not set |
| 5677 | + |
| 5678 | +# |
| 5679 | +# USB port drivers |
| 5680 | +# |
| 5681 | +# CONFIG_USB_USS720 is not set |
| 5682 | + |
| 5683 | +# |
| 5684 | +# USB Serial Converter support |
| 5685 | +# |
| 5686 | +# CONFIG_USB_SERIAL is not set |
| 5687 | + |
| 5688 | +# |
| 5689 | +# USB Miscellaneous drivers |
| 5690 | +# |
| 5691 | +# CONFIG_USB_RIO500 is not set |
| 5692 | +# CONFIG_USB_AUERSWALD is not set |
| 5693 | +# CONFIG_USB_TIGL is not set |
| 5694 | +# CONFIG_USB_BRLVGER is not set |
| 5695 | +# CONFIG_USB_LCD is not set |
| 5696 | + |
| 5697 | +# |
| 5698 | +# Support for USB gadgets |
| 5699 | +# |
| 5700 | +# CONFIG_USB_GADGET is not set |
| 5701 | + |
| 5702 | +# |
| 5703 | +# Bluetooth support |
| 5704 | +# |
| 5705 | +# CONFIG_BLUEZ is not set |
| 5706 | + |
| 5707 | +# |
| 5708 | +# Kernel hacking |
| 5709 | +# |
| 5710 | +CONFIG_CROSSCOMPILE=y |
| 5711 | +# CONFIG_RUNTIME_DEBUG is not set |
| 5712 | +# CONFIG_KGDB is not set |
| 5713 | +# CONFIG_GDB_CONSOLE is not set |
| 5714 | +# CONFIG_DEBUG_INFO is not set |
| 5715 | +# CONFIG_MAGIC_SYSRQ is not set |
| 5716 | +# CONFIG_MIPS_UNCACHED is not set |
| 5717 | +CONFIG_LOG_BUF_SHIFT=0 |
| 5718 | + |
| 5719 | +# |
| 5720 | +# Cryptographic options |
| 5721 | +# |
| 5722 | +# CONFIG_CRYPTO is not set |
| 5723 | + |
| 5724 | +# |
| 5725 | +# Library routines |
| 5726 | +# |
| 5727 | +# CONFIG_CRC32 is not set |
| 5728 | +CONFIG_ZLIB_INFLATE=m |
| 5729 | +CONFIG_ZLIB_DEFLATE=m |
| 5730 | +# CONFIG_FW_LOADER is not set |
| 5731 | --- a/arch/mips/defconfig-db1500 |
| 5732 | +++ b/arch/mips/defconfig-db1500 |
| 5733 | @@ -30,8 +30,8 @@ CONFIG_MIPS_DB1500=y |
| 5734 | # CONFIG_MIPS_PB1000 is not set |
| 5735 | # CONFIG_MIPS_PB1100 is not set |
| 5736 | # CONFIG_MIPS_PB1500 is not set |
| 5737 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5738 | # CONFIG_MIPS_PB1550 is not set |
| 5739 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5740 | # CONFIG_MIPS_XXS1500 is not set |
| 5741 | # CONFIG_MIPS_MTX1 is not set |
| 5742 | # CONFIG_COGENT_CSB250 is not set |
| 5743 | @@ -267,11 +267,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5744 | # |
| 5745 | # CONFIG_IPX is not set |
| 5746 | # CONFIG_ATALK is not set |
| 5747 | - |
| 5748 | -# |
| 5749 | -# Appletalk devices |
| 5750 | -# |
| 5751 | -# CONFIG_DEV_APPLETALK is not set |
| 5752 | # CONFIG_DECNET is not set |
| 5753 | # CONFIG_BRIDGE is not set |
| 5754 | # CONFIG_X25 is not set |
| 5755 | @@ -555,7 +550,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 5756 | # CONFIG_AU1X00_USB_TTY is not set |
| 5757 | # CONFIG_AU1X00_USB_RAW is not set |
| 5758 | # CONFIG_TXX927_SERIAL is not set |
| 5759 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5760 | CONFIG_UNIX98_PTYS=y |
| 5761 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5762 | |
| 5763 | --- a/arch/mips/defconfig-db1550 |
| 5764 | +++ b/arch/mips/defconfig-db1550 |
| 5765 | @@ -30,8 +30,8 @@ CONFIG_MIPS_DB1550=y |
| 5766 | # CONFIG_MIPS_PB1000 is not set |
| 5767 | # CONFIG_MIPS_PB1100 is not set |
| 5768 | # CONFIG_MIPS_PB1500 is not set |
| 5769 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5770 | # CONFIG_MIPS_PB1550 is not set |
| 5771 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5772 | # CONFIG_MIPS_XXS1500 is not set |
| 5773 | # CONFIG_MIPS_MTX1 is not set |
| 5774 | # CONFIG_COGENT_CSB250 is not set |
| 5775 | @@ -213,11 +213,9 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 5776 | # CONFIG_MTD_BOSPORUS is not set |
| 5777 | # CONFIG_MTD_XXS1500 is not set |
| 5778 | # CONFIG_MTD_MTX1 is not set |
| 5779 | -# CONFIG_MTD_DB1X00 is not set |
| 5780 | CONFIG_MTD_PB1550=y |
| 5781 | CONFIG_MTD_PB1550_BOOT=y |
| 5782 | CONFIG_MTD_PB1550_USER=y |
| 5783 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 5784 | # CONFIG_MTD_MIRAGE is not set |
| 5785 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 5786 | # CONFIG_MTD_OCELOT is not set |
| 5787 | @@ -236,7 +234,6 @@ CONFIG_MTD_PB1550_USER=y |
| 5788 | # |
| 5789 | # Disk-On-Chip Device Drivers |
| 5790 | # |
| 5791 | -# CONFIG_MTD_DOC1000 is not set |
| 5792 | # CONFIG_MTD_DOC2000 is not set |
| 5793 | # CONFIG_MTD_DOC2001 is not set |
| 5794 | # CONFIG_MTD_DOCPROBE is not set |
| 5795 | @@ -343,11 +340,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5796 | # |
| 5797 | # CONFIG_IPX is not set |
| 5798 | # CONFIG_ATALK is not set |
| 5799 | - |
| 5800 | -# |
| 5801 | -# Appletalk devices |
| 5802 | -# |
| 5803 | -# CONFIG_DEV_APPLETALK is not set |
| 5804 | # CONFIG_DECNET is not set |
| 5805 | # CONFIG_BRIDGE is not set |
| 5806 | # CONFIG_X25 is not set |
| 5807 | @@ -633,7 +625,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 5808 | # CONFIG_AU1X00_USB_TTY is not set |
| 5809 | # CONFIG_AU1X00_USB_RAW is not set |
| 5810 | # CONFIG_TXX927_SERIAL is not set |
| 5811 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5812 | CONFIG_UNIX98_PTYS=y |
| 5813 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5814 | |
| 5815 | --- a/arch/mips/defconfig-ddb5476 |
| 5816 | +++ b/arch/mips/defconfig-ddb5476 |
| 5817 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 5818 | # CONFIG_MIPS_PB1000 is not set |
| 5819 | # CONFIG_MIPS_PB1100 is not set |
| 5820 | # CONFIG_MIPS_PB1500 is not set |
| 5821 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5822 | # CONFIG_MIPS_PB1550 is not set |
| 5823 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5824 | # CONFIG_MIPS_XXS1500 is not set |
| 5825 | # CONFIG_MIPS_MTX1 is not set |
| 5826 | # CONFIG_COGENT_CSB250 is not set |
| 5827 | @@ -226,11 +226,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5828 | # |
| 5829 | # CONFIG_IPX is not set |
| 5830 | # CONFIG_ATALK is not set |
| 5831 | - |
| 5832 | -# |
| 5833 | -# Appletalk devices |
| 5834 | -# |
| 5835 | -# CONFIG_DEV_APPLETALK is not set |
| 5836 | # CONFIG_DECNET is not set |
| 5837 | # CONFIG_BRIDGE is not set |
| 5838 | # CONFIG_X25 is not set |
| 5839 | @@ -517,7 +512,6 @@ CONFIG_SERIAL=y |
| 5840 | CONFIG_SERIAL_CONSOLE=y |
| 5841 | # CONFIG_SERIAL_EXTENDED is not set |
| 5842 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 5843 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5844 | CONFIG_UNIX98_PTYS=y |
| 5845 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5846 | |
| 5847 | --- a/arch/mips/defconfig-ddb5477 |
| 5848 | +++ b/arch/mips/defconfig-ddb5477 |
| 5849 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 5850 | # CONFIG_MIPS_PB1000 is not set |
| 5851 | # CONFIG_MIPS_PB1100 is not set |
| 5852 | # CONFIG_MIPS_PB1500 is not set |
| 5853 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5854 | # CONFIG_MIPS_PB1550 is not set |
| 5855 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5856 | # CONFIG_MIPS_XXS1500 is not set |
| 5857 | # CONFIG_MIPS_MTX1 is not set |
| 5858 | # CONFIG_COGENT_CSB250 is not set |
| 5859 | @@ -226,11 +226,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5860 | # |
| 5861 | # CONFIG_IPX is not set |
| 5862 | # CONFIG_ATALK is not set |
| 5863 | - |
| 5864 | -# |
| 5865 | -# Appletalk devices |
| 5866 | -# |
| 5867 | -# CONFIG_DEV_APPLETALK is not set |
| 5868 | # CONFIG_DECNET is not set |
| 5869 | # CONFIG_BRIDGE is not set |
| 5870 | # CONFIG_X25 is not set |
| 5871 | @@ -434,7 +429,6 @@ CONFIG_SERIAL=y |
| 5872 | CONFIG_SERIAL_CONSOLE=y |
| 5873 | # CONFIG_SERIAL_EXTENDED is not set |
| 5874 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 5875 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5876 | CONFIG_UNIX98_PTYS=y |
| 5877 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5878 | |
| 5879 | --- a/arch/mips/defconfig-decstation |
| 5880 | +++ b/arch/mips/defconfig-decstation |
| 5881 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 5882 | # CONFIG_MIPS_PB1000 is not set |
| 5883 | # CONFIG_MIPS_PB1100 is not set |
| 5884 | # CONFIG_MIPS_PB1500 is not set |
| 5885 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5886 | # CONFIG_MIPS_PB1550 is not set |
| 5887 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5888 | # CONFIG_MIPS_XXS1500 is not set |
| 5889 | # CONFIG_MIPS_MTX1 is not set |
| 5890 | # CONFIG_COGENT_CSB250 is not set |
| 5891 | @@ -223,11 +223,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5892 | # |
| 5893 | # CONFIG_IPX is not set |
| 5894 | # CONFIG_ATALK is not set |
| 5895 | - |
| 5896 | -# |
| 5897 | -# Appletalk devices |
| 5898 | -# |
| 5899 | -# CONFIG_DEV_APPLETALK is not set |
| 5900 | # CONFIG_DECNET is not set |
| 5901 | # CONFIG_BRIDGE is not set |
| 5902 | # CONFIG_X25 is not set |
| 5903 | @@ -306,9 +301,11 @@ CONFIG_SCSI_DECNCR=y |
| 5904 | # CONFIG_SCSI_MEGARAID is not set |
| 5905 | # CONFIG_SCSI_MEGARAID2 is not set |
| 5906 | # CONFIG_SCSI_SATA is not set |
| 5907 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 5908 | # CONFIG_SCSI_SATA_SVW is not set |
| 5909 | # CONFIG_SCSI_ATA_PIIX is not set |
| 5910 | # CONFIG_SCSI_SATA_NV is not set |
| 5911 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 5912 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 5913 | # CONFIG_SCSI_SATA_SX4 is not set |
| 5914 | # CONFIG_SCSI_SATA_SIL is not set |
| 5915 | @@ -477,7 +474,6 @@ CONFIG_SERIAL_DEC=y |
| 5916 | CONFIG_SERIAL_DEC_CONSOLE=y |
| 5917 | CONFIG_DZ=y |
| 5918 | CONFIG_ZS=y |
| 5919 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5920 | CONFIG_UNIX98_PTYS=y |
| 5921 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5922 | |
| 5923 | --- a/arch/mips/defconfig-e55 |
| 5924 | +++ b/arch/mips/defconfig-e55 |
| 5925 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 5926 | # CONFIG_MIPS_PB1000 is not set |
| 5927 | # CONFIG_MIPS_PB1100 is not set |
| 5928 | # CONFIG_MIPS_PB1500 is not set |
| 5929 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5930 | # CONFIG_MIPS_PB1550 is not set |
| 5931 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5932 | # CONFIG_MIPS_XXS1500 is not set |
| 5933 | # CONFIG_MIPS_MTX1 is not set |
| 5934 | # CONFIG_COGENT_CSB250 is not set |
| 5935 | @@ -222,11 +222,6 @@ CONFIG_IP_MULTICAST=y |
| 5936 | # |
| 5937 | # CONFIG_IPX is not set |
| 5938 | # CONFIG_ATALK is not set |
| 5939 | - |
| 5940 | -# |
| 5941 | -# Appletalk devices |
| 5942 | -# |
| 5943 | -# CONFIG_DEV_APPLETALK is not set |
| 5944 | # CONFIG_DECNET is not set |
| 5945 | # CONFIG_BRIDGE is not set |
| 5946 | # CONFIG_X25 is not set |
| 5947 | @@ -426,7 +421,6 @@ CONFIG_SERIAL_MANY_PORTS=y |
| 5948 | # CONFIG_SERIAL_MULTIPORT is not set |
| 5949 | # CONFIG_HUB6 is not set |
| 5950 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 5951 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 5952 | # CONFIG_VR41XX_KIU is not set |
| 5953 | CONFIG_UNIX98_PTYS=y |
| 5954 | CONFIG_UNIX98_PTY_COUNT=256 |
| 5955 | --- a/arch/mips/defconfig-eagle |
| 5956 | +++ b/arch/mips/defconfig-eagle |
| 5957 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 5958 | # CONFIG_MIPS_PB1000 is not set |
| 5959 | # CONFIG_MIPS_PB1100 is not set |
| 5960 | # CONFIG_MIPS_PB1500 is not set |
| 5961 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 5962 | # CONFIG_MIPS_PB1550 is not set |
| 5963 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 5964 | # CONFIG_MIPS_XXS1500 is not set |
| 5965 | # CONFIG_MIPS_MTX1 is not set |
| 5966 | # CONFIG_COGENT_CSB250 is not set |
| 5967 | @@ -208,8 +208,8 @@ CONFIG_MTD_CFI_INTELEXT=y |
| 5968 | # Mapping drivers for chip access |
| 5969 | # |
| 5970 | CONFIG_MTD_PHYSMAP=y |
| 5971 | -CONFIG_MTD_PHYSMAP_START=1c000000 |
| 5972 | -CONFIG_MTD_PHYSMAP_LEN=2000000 |
| 5973 | +CONFIG_MTD_PHYSMAP_START=0x1c000000 |
| 5974 | +CONFIG_MTD_PHYSMAP_LEN=0x2000000 |
| 5975 | CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 5976 | # CONFIG_MTD_PB1000 is not set |
| 5977 | # CONFIG_MTD_PB1500 is not set |
| 5978 | @@ -217,9 +217,7 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 5979 | # CONFIG_MTD_BOSPORUS is not set |
| 5980 | # CONFIG_MTD_XXS1500 is not set |
| 5981 | # CONFIG_MTD_MTX1 is not set |
| 5982 | -# CONFIG_MTD_DB1X00 is not set |
| 5983 | # CONFIG_MTD_PB1550 is not set |
| 5984 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 5985 | # CONFIG_MTD_MIRAGE is not set |
| 5986 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 5987 | # CONFIG_MTD_OCELOT is not set |
| 5988 | @@ -238,7 +236,6 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 5989 | # |
| 5990 | # Disk-On-Chip Device Drivers |
| 5991 | # |
| 5992 | -# CONFIG_MTD_DOC1000 is not set |
| 5993 | # CONFIG_MTD_DOC2000 is not set |
| 5994 | # CONFIG_MTD_DOC2001 is not set |
| 5995 | # CONFIG_MTD_DOCPROBE is not set |
| 5996 | @@ -327,11 +324,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 5997 | # |
| 5998 | # CONFIG_IPX is not set |
| 5999 | # CONFIG_ATALK is not set |
| 6000 | - |
| 6001 | -# |
| 6002 | -# Appletalk devices |
| 6003 | -# |
| 6004 | -# CONFIG_DEV_APPLETALK is not set |
| 6005 | # CONFIG_DECNET is not set |
| 6006 | # CONFIG_BRIDGE is not set |
| 6007 | # CONFIG_X25 is not set |
| 6008 | @@ -587,7 +579,6 @@ CONFIG_SERIAL=y |
| 6009 | CONFIG_SERIAL_CONSOLE=y |
| 6010 | # CONFIG_SERIAL_EXTENDED is not set |
| 6011 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 6012 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 6013 | # CONFIG_VR41XX_KIU is not set |
| 6014 | CONFIG_UNIX98_PTYS=y |
| 6015 | CONFIG_UNIX98_PTY_COUNT=256 |
| 6016 | --- a/arch/mips/defconfig-ev64120 |
| 6017 | +++ b/arch/mips/defconfig-ev64120 |
| 6018 | @@ -30,8 +30,8 @@ CONFIG_MODULES=y |
| 6019 | # CONFIG_MIPS_PB1000 is not set |
| 6020 | # CONFIG_MIPS_PB1100 is not set |
| 6021 | # CONFIG_MIPS_PB1500 is not set |
| 6022 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 6023 | # CONFIG_MIPS_PB1550 is not set |
| 6024 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 6025 | # CONFIG_MIPS_XXS1500 is not set |
| 6026 | # CONFIG_MIPS_MTX1 is not set |
| 6027 | # CONFIG_COGENT_CSB250 is not set |
| 6028 | @@ -230,11 +230,6 @@ CONFIG_IP_PNP=y |
| 6029 | # |
| 6030 | # CONFIG_IPX is not set |
| 6031 | # CONFIG_ATALK is not set |
| 6032 | - |
| 6033 | -# |
| 6034 | -# Appletalk devices |
| 6035 | -# |
| 6036 | -# CONFIG_DEV_APPLETALK is not set |
| 6037 | # CONFIG_DECNET is not set |
| 6038 | # CONFIG_BRIDGE is not set |
| 6039 | # CONFIG_X25 is not set |
| 6040 | @@ -443,7 +438,6 @@ CONFIG_SERIAL=y |
| 6041 | # CONFIG_SERIAL_CONSOLE is not set |
| 6042 | # CONFIG_SERIAL_EXTENDED is not set |
| 6043 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 6044 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 6045 | CONFIG_UNIX98_PTYS=y |
| 6046 | CONFIG_UNIX98_PTY_COUNT=256 |
| 6047 | |
| 6048 | --- a/arch/mips/defconfig-ev96100 |
| 6049 | +++ b/arch/mips/defconfig-ev96100 |
| 6050 | @@ -30,8 +30,8 @@ CONFIG_MODULES=y |
| 6051 | # CONFIG_MIPS_PB1000 is not set |
| 6052 | # CONFIG_MIPS_PB1100 is not set |
| 6053 | # CONFIG_MIPS_PB1500 is not set |
| 6054 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 6055 | # CONFIG_MIPS_PB1550 is not set |
| 6056 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 6057 | # CONFIG_MIPS_XXS1500 is not set |
| 6058 | # CONFIG_MIPS_MTX1 is not set |
| 6059 | # CONFIG_COGENT_CSB250 is not set |
| 6060 | @@ -232,11 +232,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 6061 | # |
| 6062 | # CONFIG_IPX is not set |
| 6063 | # CONFIG_ATALK is not set |
| 6064 | - |
| 6065 | -# |
| 6066 | -# Appletalk devices |
| 6067 | -# |
| 6068 | -# CONFIG_DEV_APPLETALK is not set |
| 6069 | # CONFIG_DECNET is not set |
| 6070 | # CONFIG_BRIDGE is not set |
| 6071 | # CONFIG_X25 is not set |
| 6072 | @@ -441,7 +436,6 @@ CONFIG_SERIAL=y |
| 6073 | CONFIG_SERIAL_CONSOLE=y |
| 6074 | # CONFIG_SERIAL_EXTENDED is not set |
| 6075 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 6076 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 6077 | CONFIG_UNIX98_PTYS=y |
| 6078 | CONFIG_UNIX98_PTY_COUNT=256 |
| 6079 | |
| 6080 | --- /dev/null |
| 6081 | +++ b/arch/mips/defconfig-ficmmp |
| 6082 | @@ -0,0 +1,862 @@ |
| 6083 | +# |
| 6084 | +# Automatically generated make config: don't edit |
| 6085 | +# |
| 6086 | +CONFIG_MIPS=y |
| 6087 | +CONFIG_MIPS32=y |
| 6088 | +# CONFIG_MIPS64 is not set |
| 6089 | + |
| 6090 | +# |
| 6091 | +# Code maturity level options |
| 6092 | +# |
| 6093 | +CONFIG_EXPERIMENTAL=y |
| 6094 | + |
| 6095 | +# |
| 6096 | +# Loadable module support |
| 6097 | +# |
| 6098 | +CONFIG_MODULES=y |
| 6099 | +# CONFIG_MODVERSIONS is not set |
| 6100 | +CONFIG_KMOD=y |
| 6101 | + |
| 6102 | +# |
| 6103 | +# Machine selection |
| 6104 | +# |
| 6105 | +# CONFIG_ACER_PICA_61 is not set |
| 6106 | +# CONFIG_MIPS_BOSPORUS is not set |
| 6107 | +# CONFIG_MIPS_MIRAGE is not set |
| 6108 | +# CONFIG_MIPS_DB1000 is not set |
| 6109 | +# CONFIG_MIPS_DB1100 is not set |
| 6110 | +# CONFIG_MIPS_DB1500 is not set |
| 6111 | +# CONFIG_MIPS_DB1550 is not set |
| 6112 | +# CONFIG_MIPS_PB1000 is not set |
| 6113 | +# CONFIG_MIPS_PB1100 is not set |
| 6114 | +# CONFIG_MIPS_PB1500 is not set |
| 6115 | +# CONFIG_MIPS_PB1550 is not set |
| 6116 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 6117 | +# CONFIG_MIPS_XXS1500 is not set |
| 6118 | +# CONFIG_MIPS_MTX1 is not set |
| 6119 | +# CONFIG_COGENT_CSB250 is not set |
| 6120 | +# CONFIG_BAGET_MIPS is not set |
| 6121 | +# CONFIG_CASIO_E55 is not set |
| 6122 | +# CONFIG_MIPS_COBALT is not set |
| 6123 | +# CONFIG_DECSTATION is not set |
| 6124 | +# CONFIG_MIPS_EV64120 is not set |
| 6125 | +# CONFIG_MIPS_EV96100 is not set |
| 6126 | +# CONFIG_MIPS_IVR is not set |
| 6127 | +# CONFIG_HP_LASERJET is not set |
| 6128 | +# CONFIG_IBM_WORKPAD is not set |
| 6129 | +# CONFIG_LASAT is not set |
| 6130 | +# CONFIG_MIPS_ITE8172 is not set |
| 6131 | +# CONFIG_MIPS_ATLAS is not set |
| 6132 | +# CONFIG_MIPS_MAGNUM_4000 is not set |
| 6133 | +# CONFIG_MIPS_MALTA is not set |
| 6134 | +# CONFIG_MIPS_SEAD is not set |
| 6135 | +# CONFIG_MOMENCO_OCELOT is not set |
| 6136 | +# CONFIG_MOMENCO_OCELOT_G is not set |
| 6137 | +# CONFIG_MOMENCO_OCELOT_C is not set |
| 6138 | +# CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 6139 | +# CONFIG_PMC_BIG_SUR is not set |
| 6140 | +# CONFIG_PMC_STRETCH is not set |
| 6141 | +# CONFIG_PMC_YOSEMITE is not set |
| 6142 | +# CONFIG_DDB5074 is not set |
| 6143 | +# CONFIG_DDB5476 is not set |
| 6144 | +# CONFIG_DDB5477 is not set |
| 6145 | +# CONFIG_NEC_OSPREY is not set |
| 6146 | +# CONFIG_NEC_EAGLE is not set |
| 6147 | +# CONFIG_OLIVETTI_M700 is not set |
| 6148 | +# CONFIG_NINO is not set |
| 6149 | +# CONFIG_SGI_IP22 is not set |
| 6150 | +# CONFIG_SGI_IP27 is not set |
| 6151 | +# CONFIG_SIBYTE_SB1xxx_SOC is not set |
| 6152 | +# CONFIG_SNI_RM200_PCI is not set |
| 6153 | +# CONFIG_TANBAC_TB0226 is not set |
| 6154 | +# CONFIG_TANBAC_TB0229 is not set |
| 6155 | +# CONFIG_TOSHIBA_JMR3927 is not set |
| 6156 | +# CONFIG_TOSHIBA_RBTX4927 is not set |
| 6157 | +# CONFIG_VICTOR_MPC30X is not set |
| 6158 | +# CONFIG_ZAO_CAPCELLA is not set |
| 6159 | +# CONFIG_HIGHMEM is not set |
| 6160 | +CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 6161 | +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 6162 | +# CONFIG_MIPS_AU1000 is not set |
| 6163 | + |
| 6164 | +# |
| 6165 | +# CPU selection |
| 6166 | +# |
| 6167 | +CONFIG_CPU_MIPS32=y |
| 6168 | +# CONFIG_CPU_MIPS64 is not set |
| 6169 | +# CONFIG_CPU_R3000 is not set |
| 6170 | +# CONFIG_CPU_TX39XX is not set |
| 6171 | +# CONFIG_CPU_VR41XX is not set |
| 6172 | +# CONFIG_CPU_R4300 is not set |
| 6173 | +# CONFIG_CPU_R4X00 is not set |
| 6174 | +# CONFIG_CPU_TX49XX is not set |
| 6175 | +# CONFIG_CPU_R5000 is not set |
| 6176 | +# CONFIG_CPU_R5432 is not set |
| 6177 | +# CONFIG_CPU_R6000 is not set |
| 6178 | +# CONFIG_CPU_NEVADA is not set |
| 6179 | +# CONFIG_CPU_R8000 is not set |
| 6180 | +# CONFIG_CPU_R10000 is not set |
| 6181 | +# CONFIG_CPU_RM7000 is not set |
| 6182 | +# CONFIG_CPU_RM9000 is not set |
| 6183 | +# CONFIG_CPU_SB1 is not set |
| 6184 | +CONFIG_PAGE_SIZE_4KB=y |
| 6185 | +# CONFIG_PAGE_SIZE_16KB is not set |
| 6186 | +# CONFIG_PAGE_SIZE_64KB is not set |
| 6187 | +CONFIG_CPU_HAS_PREFETCH=y |
| 6188 | +# CONFIG_VTAG_ICACHE is not set |
| 6189 | +CONFIG_64BIT_PHYS_ADDR=y |
| 6190 | +# CONFIG_CPU_ADVANCED is not set |
| 6191 | +CONFIG_CPU_HAS_LLSC=y |
| 6192 | +# CONFIG_CPU_HAS_LLDSCD is not set |
| 6193 | +# CONFIG_CPU_HAS_WB is not set |
| 6194 | +CONFIG_CPU_HAS_SYNC=y |
| 6195 | + |
| 6196 | +# |
| 6197 | +# General setup |
| 6198 | +# |
| 6199 | +CONFIG_CPU_LITTLE_ENDIAN=y |
| 6200 | +# CONFIG_BUILD_ELF64 is not set |
| 6201 | +CONFIG_NET=y |
| 6202 | +# CONFIG_PCI is not set |
| 6203 | +# CONFIG_PCI_NEW is not set |
| 6204 | +CONFIG_PCI_AUTO=y |
| 6205 | +# CONFIG_ISA is not set |
| 6206 | +# CONFIG_TC is not set |
| 6207 | +# CONFIG_MCA is not set |
| 6208 | +# CONFIG_SBUS is not set |
| 6209 | +# CONFIG_HOTPLUG is not set |
| 6210 | +# CONFIG_PCMCIA is not set |
| 6211 | +# CONFIG_HOTPLUG_PCI is not set |
| 6212 | +CONFIG_SYSVIPC=y |
| 6213 | +# CONFIG_BSD_PROCESS_ACCT is not set |
| 6214 | +CONFIG_SYSCTL=y |
| 6215 | +CONFIG_KCORE_ELF=y |
| 6216 | +# CONFIG_KCORE_AOUT is not set |
| 6217 | +# CONFIG_BINFMT_AOUT is not set |
| 6218 | +CONFIG_BINFMT_ELF=y |
| 6219 | +# CONFIG_MIPS32_COMPAT is not set |
| 6220 | +# CONFIG_MIPS32_O32 is not set |
| 6221 | +# CONFIG_MIPS32_N32 is not set |
| 6222 | +# CONFIG_BINFMT_ELF32 is not set |
| 6223 | +# CONFIG_BINFMT_MISC is not set |
| 6224 | +# CONFIG_OOM_KILLER is not set |
| 6225 | +CONFIG_CMDLINE_BOOL=y |
| 6226 | +CONFIG_CMDLINE="ide3=dma mem=96M root=/dev/hda2 rootflags=data=journal" |
| 6227 | + |
| 6228 | +# |
| 6229 | +# Memory Technology Devices (MTD) |
| 6230 | +# |
| 6231 | +# CONFIG_MTD is not set |
| 6232 | + |
| 6233 | +# |
| 6234 | +# Parallel port support |
| 6235 | +# |
| 6236 | +# CONFIG_PARPORT is not set |
| 6237 | + |
| 6238 | +# |
| 6239 | +# Plug and Play configuration |
| 6240 | +# |
| 6241 | +# CONFIG_PNP is not set |
| 6242 | +# CONFIG_ISAPNP is not set |
| 6243 | + |
| 6244 | +# |
| 6245 | +# Block devices |
| 6246 | +# |
| 6247 | +# CONFIG_BLK_DEV_FD is not set |
| 6248 | +# CONFIG_BLK_DEV_XD is not set |
| 6249 | +# CONFIG_PARIDE is not set |
| 6250 | +# CONFIG_BLK_CPQ_DA is not set |
| 6251 | +# CONFIG_BLK_CPQ_CISS_DA is not set |
| 6252 | +# CONFIG_CISS_SCSI_TAPE is not set |
| 6253 | +# CONFIG_CISS_MONITOR_THREAD is not set |
| 6254 | +# CONFIG_BLK_DEV_DAC960 is not set |
| 6255 | +# CONFIG_BLK_DEV_UMEM is not set |
| 6256 | +# CONFIG_BLK_DEV_SX8 is not set |
| 6257 | +CONFIG_BLK_DEV_LOOP=y |
| 6258 | +# CONFIG_BLK_DEV_NBD is not set |
| 6259 | +# CONFIG_BLK_DEV_RAM is not set |
| 6260 | +# CONFIG_BLK_DEV_INITRD is not set |
| 6261 | +# CONFIG_BLK_STATS is not set |
| 6262 | + |
| 6263 | +# |
| 6264 | +# Multi-device support (RAID and LVM) |
| 6265 | +# |
| 6266 | +# CONFIG_MD is not set |
| 6267 | +# CONFIG_BLK_DEV_MD is not set |
| 6268 | +# CONFIG_MD_LINEAR is not set |
| 6269 | +# CONFIG_MD_RAID0 is not set |
| 6270 | +# CONFIG_MD_RAID1 is not set |
| 6271 | +# CONFIG_MD_RAID5 is not set |
| 6272 | +# CONFIG_MD_MULTIPATH is not set |
| 6273 | +# CONFIG_BLK_DEV_LVM is not set |
| 6274 | + |
| 6275 | +# |
| 6276 | +# Networking options |
| 6277 | +# |
| 6278 | +CONFIG_PACKET=y |
| 6279 | +# CONFIG_PACKET_MMAP is not set |
| 6280 | +# CONFIG_NETLINK_DEV is not set |
| 6281 | +CONFIG_NETFILTER=y |
| 6282 | +# CONFIG_NETFILTER_DEBUG is not set |
| 6283 | +CONFIG_FILTER=y |
| 6284 | +CONFIG_UNIX=y |
| 6285 | +CONFIG_INET=y |
| 6286 | +CONFIG_IP_MULTICAST=y |
| 6287 | +# CONFIG_IP_ADVANCED_ROUTER is not set |
| 6288 | +# CONFIG_IP_PNP is not set |
| 6289 | +# CONFIG_NET_IPIP is not set |
| 6290 | +# CONFIG_NET_IPGRE is not set |
| 6291 | +# CONFIG_IP_MROUTE is not set |
| 6292 | +# CONFIG_ARPD is not set |
| 6293 | +# CONFIG_INET_ECN is not set |
| 6294 | +# CONFIG_SYN_COOKIES is not set |
| 6295 | + |
| 6296 | +# |
| 6297 | +# IP: Netfilter Configuration |
| 6298 | +# |
| 6299 | +# CONFIG_IP_NF_CONNTRACK is not set |
| 6300 | +# CONFIG_IP_NF_QUEUE is not set |
| 6301 | +# CONFIG_IP_NF_IPTABLES is not set |
| 6302 | +# CONFIG_IP_NF_ARPTABLES is not set |
| 6303 | +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set |
| 6304 | +# CONFIG_IP_NF_COMPAT_IPFWADM is not set |
| 6305 | + |
| 6306 | +# |
| 6307 | +# IP: Virtual Server Configuration |
| 6308 | +# |
| 6309 | +# CONFIG_IP_VS is not set |
| 6310 | +# CONFIG_IPV6 is not set |
| 6311 | +# CONFIG_KHTTPD is not set |
| 6312 | + |
| 6313 | +# |
| 6314 | +# SCTP Configuration (EXPERIMENTAL) |
| 6315 | +# |
| 6316 | +# CONFIG_IP_SCTP is not set |
| 6317 | +# CONFIG_ATM is not set |
| 6318 | +# CONFIG_VLAN_8021Q is not set |
| 6319 | + |
| 6320 | +# |
| 6321 | +# |
| 6322 | +# |
| 6323 | +# CONFIG_IPX is not set |
| 6324 | +# CONFIG_ATALK is not set |
| 6325 | +# CONFIG_DECNET is not set |
| 6326 | +# CONFIG_BRIDGE is not set |
| 6327 | +# CONFIG_X25 is not set |
| 6328 | +# CONFIG_LAPB is not set |
| 6329 | +# CONFIG_LLC is not set |
| 6330 | +# CONFIG_NET_DIVERT is not set |
| 6331 | +# CONFIG_ECONET is not set |
| 6332 | +# CONFIG_WAN_ROUTER is not set |
| 6333 | +# CONFIG_NET_FASTROUTE is not set |
| 6334 | +# CONFIG_NET_HW_FLOWCONTROL is not set |
| 6335 | + |
| 6336 | +# |
| 6337 | +# QoS and/or fair queueing |
| 6338 | +# |
| 6339 | +# CONFIG_NET_SCHED is not set |
| 6340 | + |
| 6341 | +# |
| 6342 | +# Network testing |
| 6343 | +# |
| 6344 | +# CONFIG_NET_PKTGEN is not set |
| 6345 | + |
| 6346 | +# |
| 6347 | +# Telephony Support |
| 6348 | +# |
| 6349 | +# CONFIG_PHONE is not set |
| 6350 | +# CONFIG_PHONE_IXJ is not set |
| 6351 | +# CONFIG_PHONE_IXJ_PCMCIA is not set |
| 6352 | + |
| 6353 | +# |
| 6354 | +# ATA/IDE/MFM/RLL support |
| 6355 | +# |
| 6356 | +CONFIG_IDE=y |
| 6357 | + |
| 6358 | +# |
| 6359 | +# IDE, ATA and ATAPI Block devices |
| 6360 | +# |
| 6361 | +CONFIG_BLK_DEV_IDE=y |
| 6362 | + |
| 6363 | +# |
| 6364 | +# Please see Documentation/ide.txt for help/info on IDE drives |
| 6365 | +# |
| 6366 | +CONFIG_BLK_DEV_HD_IDE=y |
| 6367 | +CONFIG_BLK_DEV_HD=y |
| 6368 | +# CONFIG_BLK_DEV_IDE_SATA is not set |
| 6369 | +CONFIG_BLK_DEV_IDEDISK=y |
| 6370 | +CONFIG_IDEDISK_MULTI_MODE=y |
| 6371 | +CONFIG_IDEDISK_STROKE=y |
| 6372 | +# CONFIG_BLK_DEV_IDECS is not set |
| 6373 | +# CONFIG_BLK_DEV_DELKIN is not set |
| 6374 | +# CONFIG_BLK_DEV_IDECD is not set |
| 6375 | +# CONFIG_BLK_DEV_IDETAPE is not set |
| 6376 | +# CONFIG_BLK_DEV_IDEFLOPPY is not set |
| 6377 | +# CONFIG_BLK_DEV_IDESCSI is not set |
| 6378 | +# CONFIG_IDE_TASK_IOCTL is not set |
| 6379 | + |
| 6380 | +# |
| 6381 | +# IDE chipset support/bugfixes |
| 6382 | +# |
| 6383 | +# CONFIG_BLK_DEV_CMD640 is not set |
| 6384 | +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set |
| 6385 | +# CONFIG_BLK_DEV_ISAPNP is not set |
| 6386 | +# CONFIG_IDE_CHIPSETS is not set |
| 6387 | +# CONFIG_IDEDMA_AUTO is not set |
| 6388 | +# CONFIG_DMA_NONPCI is not set |
| 6389 | +# CONFIG_BLK_DEV_ATARAID is not set |
| 6390 | +# CONFIG_BLK_DEV_ATARAID_PDC is not set |
| 6391 | +# CONFIG_BLK_DEV_ATARAID_HPT is not set |
| 6392 | +# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set |
| 6393 | +# CONFIG_BLK_DEV_ATARAID_SII is not set |
| 6394 | + |
| 6395 | +# |
| 6396 | +# SCSI support |
| 6397 | +# |
| 6398 | +CONFIG_SCSI=y |
| 6399 | + |
| 6400 | +# |
| 6401 | +# SCSI support type (disk, tape, CD-ROM) |
| 6402 | +# |
| 6403 | +CONFIG_BLK_DEV_SD=y |
| 6404 | +CONFIG_SD_EXTRA_DEVS=40 |
| 6405 | +CONFIG_CHR_DEV_ST=y |
| 6406 | +# CONFIG_CHR_DEV_OSST is not set |
| 6407 | +CONFIG_BLK_DEV_SR=y |
| 6408 | +# CONFIG_BLK_DEV_SR_VENDOR is not set |
| 6409 | +CONFIG_SR_EXTRA_DEVS=2 |
| 6410 | +# CONFIG_CHR_DEV_SG is not set |
| 6411 | + |
| 6412 | +# |
| 6413 | +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs |
| 6414 | +# |
| 6415 | +# CONFIG_SCSI_DEBUG_QUEUES is not set |
| 6416 | +# CONFIG_SCSI_MULTI_LUN is not set |
| 6417 | +CONFIG_SCSI_CONSTANTS=y |
| 6418 | +# CONFIG_SCSI_LOGGING is not set |
| 6419 | + |
| 6420 | +# |
| 6421 | +# SCSI low-level drivers |
| 6422 | +# |
| 6423 | +# CONFIG_SCSI_7000FASST is not set |
| 6424 | +# CONFIG_SCSI_ACARD is not set |
| 6425 | +# CONFIG_SCSI_AHA152X is not set |
| 6426 | +# CONFIG_SCSI_AHA1542 is not set |
| 6427 | +# CONFIG_SCSI_AHA1740 is not set |
| 6428 | +# CONFIG_SCSI_AACRAID is not set |
| 6429 | +# CONFIG_SCSI_AIC7XXX is not set |
| 6430 | +# CONFIG_SCSI_AIC79XX is not set |
| 6431 | +# CONFIG_SCSI_AIC7XXX_OLD is not set |
| 6432 | +# CONFIG_SCSI_DPT_I2O is not set |
| 6433 | +# CONFIG_SCSI_ADVANSYS is not set |
| 6434 | +# CONFIG_SCSI_IN2000 is not set |
| 6435 | +# CONFIG_SCSI_AM53C974 is not set |
| 6436 | +# CONFIG_SCSI_MEGARAID is not set |
| 6437 | +# CONFIG_SCSI_MEGARAID2 is not set |
| 6438 | +# CONFIG_SCSI_SATA is not set |
| 6439 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 6440 | +# CONFIG_SCSI_SATA_SVW is not set |
| 6441 | +# CONFIG_SCSI_ATA_PIIX is not set |
| 6442 | +# CONFIG_SCSI_SATA_NV is not set |
| 6443 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 6444 | +# CONFIG_SCSI_SATA_PROMISE is not set |
| 6445 | +# CONFIG_SCSI_SATA_SX4 is not set |
| 6446 | +# CONFIG_SCSI_SATA_SIL is not set |
| 6447 | +# CONFIG_SCSI_SATA_SIS is not set |
| 6448 | +# CONFIG_SCSI_SATA_ULI is not set |
| 6449 | +# CONFIG_SCSI_SATA_VIA is not set |
| 6450 | +# CONFIG_SCSI_SATA_VITESSE is not set |
| 6451 | +# CONFIG_SCSI_BUSLOGIC is not set |
| 6452 | +# CONFIG_SCSI_DMX3191D is not set |
| 6453 | +# CONFIG_SCSI_DTC3280 is not set |
| 6454 | +# CONFIG_SCSI_EATA is not set |
| 6455 | +# CONFIG_SCSI_EATA_DMA is not set |
| 6456 | +# CONFIG_SCSI_EATA_PIO is not set |
| 6457 | +# CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 6458 | +# CONFIG_SCSI_GDTH is not set |
| 6459 | +# CONFIG_SCSI_GENERIC_NCR5380 is not set |
| 6460 | +# CONFIG_SCSI_INITIO is not set |
| 6461 | +# CONFIG_SCSI_INIA100 is not set |
| 6462 | +# CONFIG_SCSI_NCR53C406A is not set |
| 6463 | +# CONFIG_SCSI_NCR53C7xx is not set |
| 6464 | +# CONFIG_SCSI_PAS16 is not set |
| 6465 | +# CONFIG_SCSI_PCI2000 is not set |
| 6466 | +# CONFIG_SCSI_PCI2220I is not set |
| 6467 | +# CONFIG_SCSI_PSI240I is not set |
| 6468 | +# CONFIG_SCSI_QLOGIC_FAS is not set |
| 6469 | +# CONFIG_SCSI_SIM710 is not set |
| 6470 | +# CONFIG_SCSI_SYM53C416 is not set |
| 6471 | +# CONFIG_SCSI_T128 is not set |
| 6472 | +# CONFIG_SCSI_U14_34F is not set |
| 6473 | +# CONFIG_SCSI_NSP32 is not set |
| 6474 | +# CONFIG_SCSI_DEBUG is not set |
| 6475 | + |
| 6476 | +# |
| 6477 | +# Fusion MPT device support |
| 6478 | +# |
| 6479 | +# CONFIG_FUSION is not set |
| 6480 | +# CONFIG_FUSION_BOOT is not set |
| 6481 | +# CONFIG_FUSION_ISENSE is not set |
| 6482 | +# CONFIG_FUSION_CTL is not set |
| 6483 | +# CONFIG_FUSION_LAN is not set |
| 6484 | + |
| 6485 | +# |
| 6486 | +# Network device support |
| 6487 | +# |
| 6488 | +CONFIG_NETDEVICES=y |
| 6489 | + |
| 6490 | +# |
| 6491 | +# ARCnet devices |
| 6492 | +# |
| 6493 | +# CONFIG_ARCNET is not set |
| 6494 | +# CONFIG_DUMMY is not set |
| 6495 | +# CONFIG_BONDING is not set |
| 6496 | +# CONFIG_EQUALIZER is not set |
| 6497 | +# CONFIG_TUN is not set |
| 6498 | +# CONFIG_ETHERTAP is not set |
| 6499 | + |
| 6500 | +# |
| 6501 | +# Ethernet (10 or 100Mbit) |
| 6502 | +# |
| 6503 | +CONFIG_NET_ETHERNET=y |
| 6504 | +# CONFIG_SUNLANCE is not set |
| 6505 | +# CONFIG_SUNBMAC is not set |
| 6506 | +# CONFIG_SUNQE is not set |
| 6507 | +# CONFIG_SUNGEM is not set |
| 6508 | +# CONFIG_NET_VENDOR_3COM is not set |
| 6509 | +# CONFIG_LANCE is not set |
| 6510 | +# CONFIG_NET_VENDOR_SMC is not set |
| 6511 | +# CONFIG_NET_VENDOR_RACAL is not set |
| 6512 | +# CONFIG_NET_ISA is not set |
| 6513 | +# CONFIG_NET_PCI is not set |
| 6514 | +# CONFIG_NET_POCKET is not set |
| 6515 | + |
| 6516 | +# |
| 6517 | +# Ethernet (1000 Mbit) |
| 6518 | +# |
| 6519 | +# CONFIG_ACENIC is not set |
| 6520 | +# CONFIG_DL2K is not set |
| 6521 | +# CONFIG_E1000 is not set |
| 6522 | +# CONFIG_MYRI_SBUS is not set |
| 6523 | +# CONFIG_NS83820 is not set |
| 6524 | +# CONFIG_HAMACHI is not set |
| 6525 | +# CONFIG_YELLOWFIN is not set |
| 6526 | +# CONFIG_R8169 is not set |
| 6527 | +# CONFIG_SK98LIN is not set |
| 6528 | +# CONFIG_TIGON3 is not set |
| 6529 | +# CONFIG_FDDI is not set |
| 6530 | +# CONFIG_HIPPI is not set |
| 6531 | +# CONFIG_PLIP is not set |
| 6532 | +# CONFIG_PPP is not set |
| 6533 | +# CONFIG_SLIP is not set |
| 6534 | + |
| 6535 | +# |
| 6536 | +# Wireless LAN (non-hamradio) |
| 6537 | +# |
| 6538 | +# CONFIG_NET_RADIO is not set |
| 6539 | + |
| 6540 | +# |
| 6541 | +# Token Ring devices |
| 6542 | +# |
| 6543 | +# CONFIG_TR is not set |
| 6544 | +# CONFIG_NET_FC is not set |
| 6545 | +# CONFIG_RCPCI is not set |
| 6546 | +# CONFIG_SHAPER is not set |
| 6547 | + |
| 6548 | +# |
| 6549 | +# Wan interfaces |
| 6550 | +# |
| 6551 | +# CONFIG_WAN is not set |
| 6552 | + |
| 6553 | +# |
| 6554 | +# Amateur Radio support |
| 6555 | +# |
| 6556 | +# CONFIG_HAMRADIO is not set |
| 6557 | + |
| 6558 | +# |
| 6559 | +# IrDA (infrared) support |
| 6560 | +# |
| 6561 | +# CONFIG_IRDA is not set |
| 6562 | + |
| 6563 | +# |
| 6564 | +# ISDN subsystem |
| 6565 | +# |
| 6566 | +# CONFIG_ISDN is not set |
| 6567 | + |
| 6568 | +# |
| 6569 | +# Input core support |
| 6570 | +# |
| 6571 | +CONFIG_INPUT=y |
| 6572 | +CONFIG_INPUT_KEYBDEV=y |
| 6573 | +CONFIG_INPUT_MOUSEDEV=y |
| 6574 | +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 6575 | +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 6576 | +# CONFIG_INPUT_JOYDEV is not set |
| 6577 | +CONFIG_INPUT_EVDEV=y |
| 6578 | +# CONFIG_INPUT_UINPUT is not set |
| 6579 | + |
| 6580 | +# |
| 6581 | +# Character devices |
| 6582 | +# |
| 6583 | +CONFIG_VT=y |
| 6584 | +CONFIG_VT_CONSOLE=y |
| 6585 | +# CONFIG_SERIAL is not set |
| 6586 | +# CONFIG_SERIAL_EXTENDED is not set |
| 6587 | +CONFIG_SERIAL_NONSTANDARD=y |
| 6588 | +# CONFIG_COMPUTONE is not set |
| 6589 | +# CONFIG_ROCKETPORT is not set |
| 6590 | +# CONFIG_CYCLADES is not set |
| 6591 | +# CONFIG_DIGIEPCA is not set |
| 6592 | +# CONFIG_DIGI is not set |
| 6593 | +# CONFIG_ESPSERIAL is not set |
| 6594 | +# CONFIG_MOXA_INTELLIO is not set |
| 6595 | +# CONFIG_MOXA_SMARTIO is not set |
| 6596 | +# CONFIG_ISI is not set |
| 6597 | +# CONFIG_SYNCLINK is not set |
| 6598 | +# CONFIG_SYNCLINKMP is not set |
| 6599 | +# CONFIG_N_HDLC is not set |
| 6600 | +# CONFIG_RISCOM8 is not set |
| 6601 | +# CONFIG_SPECIALIX is not set |
| 6602 | +# CONFIG_SX is not set |
| 6603 | +# CONFIG_RIO is not set |
| 6604 | +# CONFIG_STALDRV is not set |
| 6605 | +# CONFIG_SERIAL_TX3912 is not set |
| 6606 | +# CONFIG_SERIAL_TX3912_CONSOLE is not set |
| 6607 | +# CONFIG_SERIAL_TXX9 is not set |
| 6608 | +# CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 6609 | +# CONFIG_TXX927_SERIAL is not set |
| 6610 | +CONFIG_UNIX98_PTYS=y |
| 6611 | +CONFIG_UNIX98_PTY_COUNT=256 |
| 6612 | + |
| 6613 | +# |
| 6614 | +# I2C support |
| 6615 | +# |
| 6616 | +CONFIG_I2C=y |
| 6617 | +# CONFIG_I2C_ALGOBIT is not set |
| 6618 | +# CONFIG_SCx200_ACB is not set |
| 6619 | +# CONFIG_I2C_ALGOPCF is not set |
| 6620 | +# CONFIG_I2C_CHARDEV is not set |
| 6621 | +# CONFIG_I2C_PROC is not set |
| 6622 | + |
| 6623 | +# |
| 6624 | +# Mice |
| 6625 | +# |
| 6626 | +# CONFIG_BUSMOUSE is not set |
| 6627 | +# CONFIG_MOUSE is not set |
| 6628 | + |
| 6629 | +# |
| 6630 | +# Joysticks |
| 6631 | +# |
| 6632 | +# CONFIG_INPUT_GAMEPORT is not set |
| 6633 | +# CONFIG_INPUT_NS558 is not set |
| 6634 | +# CONFIG_INPUT_LIGHTNING is not set |
| 6635 | +# CONFIG_INPUT_PCIGAME is not set |
| 6636 | +# CONFIG_INPUT_CS461X is not set |
| 6637 | +# CONFIG_INPUT_EMU10K1 is not set |
| 6638 | +# CONFIG_INPUT_SERIO is not set |
| 6639 | +# CONFIG_INPUT_SERPORT is not set |
| 6640 | + |
| 6641 | +# |
| 6642 | +# Joysticks |
| 6643 | +# |
| 6644 | +# CONFIG_INPUT_ANALOG is not set |
| 6645 | +# CONFIG_INPUT_A3D is not set |
| 6646 | +# CONFIG_INPUT_ADI is not set |
| 6647 | +# CONFIG_INPUT_COBRA is not set |
| 6648 | +# CONFIG_INPUT_GF2K is not set |
| 6649 | +# CONFIG_INPUT_GRIP is not set |
| 6650 | +# CONFIG_INPUT_INTERACT is not set |
| 6651 | +# CONFIG_INPUT_TMDC is not set |
| 6652 | +# CONFIG_INPUT_SIDEWINDER is not set |
| 6653 | +# CONFIG_INPUT_IFORCE_USB is not set |
| 6654 | +# CONFIG_INPUT_IFORCE_232 is not set |
| 6655 | +# CONFIG_INPUT_WARRIOR is not set |
| 6656 | +# CONFIG_INPUT_MAGELLAN is not set |
| 6657 | +# CONFIG_INPUT_SPACEORB is not set |
| 6658 | +# CONFIG_INPUT_SPACEBALL is not set |
| 6659 | +# CONFIG_INPUT_STINGER is not set |
| 6660 | +# CONFIG_INPUT_DB9 is not set |
| 6661 | +# CONFIG_INPUT_GAMECON is not set |
| 6662 | +# CONFIG_INPUT_TURBOGRAFX is not set |
| 6663 | +# CONFIG_QIC02_TAPE is not set |
| 6664 | +# CONFIG_IPMI_HANDLER is not set |
| 6665 | +# CONFIG_IPMI_PANIC_EVENT is not set |
| 6666 | +# CONFIG_IPMI_DEVICE_INTERFACE is not set |
| 6667 | +# CONFIG_IPMI_KCS is not set |
| 6668 | +# CONFIG_IPMI_WATCHDOG is not set |
| 6669 | + |
| 6670 | +# |
| 6671 | +# Watchdog Cards |
| 6672 | +# |
| 6673 | +# CONFIG_WATCHDOG is not set |
| 6674 | +# CONFIG_SCx200 is not set |
| 6675 | +# CONFIG_SCx200_GPIO is not set |
| 6676 | +# CONFIG_AMD_PM768 is not set |
| 6677 | +# CONFIG_NVRAM is not set |
| 6678 | +# CONFIG_RTC is not set |
| 6679 | +# CONFIG_DTLK is not set |
| 6680 | +# CONFIG_R3964 is not set |
| 6681 | +# CONFIG_APPLICOM is not set |
| 6682 | + |
| 6683 | +# |
| 6684 | +# Ftape, the floppy tape device driver |
| 6685 | +# |
| 6686 | +# CONFIG_FTAPE is not set |
| 6687 | +# CONFIG_AGP is not set |
| 6688 | + |
| 6689 | +# |
| 6690 | +# Direct Rendering Manager (XFree86 DRI support) |
| 6691 | +# |
| 6692 | +# CONFIG_DRM is not set |
| 6693 | + |
| 6694 | +# |
| 6695 | +# File systems |
| 6696 | +# |
| 6697 | +# CONFIG_QUOTA is not set |
| 6698 | +# CONFIG_QFMT_V2 is not set |
| 6699 | +CONFIG_AUTOFS_FS=y |
| 6700 | +# CONFIG_AUTOFS4_FS is not set |
| 6701 | +# CONFIG_REISERFS_FS is not set |
| 6702 | +# CONFIG_REISERFS_CHECK is not set |
| 6703 | +# CONFIG_REISERFS_PROC_INFO is not set |
| 6704 | +# CONFIG_ADFS_FS is not set |
| 6705 | +# CONFIG_ADFS_FS_RW is not set |
| 6706 | +# CONFIG_AFFS_FS is not set |
| 6707 | +# CONFIG_HFS_FS is not set |
| 6708 | +# CONFIG_HFSPLUS_FS is not set |
| 6709 | +# CONFIG_BEFS_FS is not set |
| 6710 | +# CONFIG_BEFS_DEBUG is not set |
| 6711 | +# CONFIG_BFS_FS is not set |
| 6712 | +CONFIG_EXT3_FS=y |
| 6713 | +CONFIG_JBD=y |
| 6714 | +# CONFIG_JBD_DEBUG is not set |
| 6715 | +CONFIG_FAT_FS=y |
| 6716 | +CONFIG_MSDOS_FS=y |
| 6717 | +# CONFIG_UMSDOS_FS is not set |
| 6718 | +CONFIG_VFAT_FS=y |
| 6719 | +# CONFIG_EFS_FS is not set |
| 6720 | +# CONFIG_JFFS_FS is not set |
| 6721 | +# CONFIG_JFFS2_FS is not set |
| 6722 | +# CONFIG_CRAMFS is not set |
| 6723 | +# CONFIG_TMPFS is not set |
| 6724 | +CONFIG_RAMFS=y |
| 6725 | +# CONFIG_ISO9660_FS is not set |
| 6726 | +# CONFIG_JOLIET is not set |
| 6727 | +# CONFIG_ZISOFS is not set |
| 6728 | +# CONFIG_JFS_FS is not set |
| 6729 | +# CONFIG_JFS_DEBUG is not set |
| 6730 | +# CONFIG_JFS_STATISTICS is not set |
| 6731 | +# CONFIG_MINIX_FS is not set |
| 6732 | +# CONFIG_VXFS_FS is not set |
| 6733 | +# CONFIG_NTFS_FS is not set |
| 6734 | +# CONFIG_NTFS_RW is not set |
| 6735 | +# CONFIG_HPFS_FS is not set |
| 6736 | +CONFIG_PROC_FS=y |
| 6737 | +# CONFIG_DEVFS_FS is not set |
| 6738 | +# CONFIG_DEVFS_MOUNT is not set |
| 6739 | +# CONFIG_DEVFS_DEBUG is not set |
| 6740 | +CONFIG_DEVPTS_FS=y |
| 6741 | +# CONFIG_QNX4FS_FS is not set |
| 6742 | +# CONFIG_QNX4FS_RW is not set |
| 6743 | +# CONFIG_ROMFS_FS is not set |
| 6744 | +CONFIG_EXT2_FS=y |
| 6745 | +# CONFIG_SYSV_FS is not set |
| 6746 | +# CONFIG_UDF_FS is not set |
| 6747 | +# CONFIG_UDF_RW is not set |
| 6748 | +# CONFIG_UFS_FS is not set |
| 6749 | +# CONFIG_UFS_FS_WRITE is not set |
| 6750 | +# CONFIG_XFS_FS is not set |
| 6751 | +# CONFIG_XFS_QUOTA is not set |
| 6752 | +# CONFIG_XFS_RT is not set |
| 6753 | +# CONFIG_XFS_TRACE is not set |
| 6754 | +# CONFIG_XFS_DEBUG is not set |
| 6755 | + |
| 6756 | +# |
| 6757 | +# Network File Systems |
| 6758 | +# |
| 6759 | +# CONFIG_CODA_FS is not set |
| 6760 | +# CONFIG_INTERMEZZO_FS is not set |
| 6761 | +# CONFIG_NFS_FS is not set |
| 6762 | +# CONFIG_NFS_V3 is not set |
| 6763 | +# CONFIG_NFS_DIRECTIO is not set |
| 6764 | +# CONFIG_ROOT_NFS is not set |
| 6765 | +# CONFIG_NFSD is not set |
| 6766 | +# CONFIG_NFSD_V3 is not set |
| 6767 | +# CONFIG_NFSD_TCP is not set |
| 6768 | +# CONFIG_SUNRPC is not set |
| 6769 | +# CONFIG_LOCKD is not set |
| 6770 | +# CONFIG_SMB_FS is not set |
| 6771 | +# CONFIG_NCP_FS is not set |
| 6772 | +# CONFIG_NCPFS_PACKET_SIGNING is not set |
| 6773 | +# CONFIG_NCPFS_IOCTL_LOCKING is not set |
| 6774 | +# CONFIG_NCPFS_STRONG is not set |
| 6775 | +# CONFIG_NCPFS_NFS_NS is not set |
| 6776 | +# CONFIG_NCPFS_OS2_NS is not set |
| 6777 | +# CONFIG_NCPFS_SMALLDOS is not set |
| 6778 | +# CONFIG_NCPFS_NLS is not set |
| 6779 | +# CONFIG_NCPFS_EXTRAS is not set |
| 6780 | +# CONFIG_ZISOFS_FS is not set |
| 6781 | + |
| 6782 | +# |
| 6783 | +# Partition Types |
| 6784 | +# |
| 6785 | +# CONFIG_PARTITION_ADVANCED is not set |
| 6786 | +CONFIG_MSDOS_PARTITION=y |
| 6787 | +# CONFIG_SMB_NLS is not set |
| 6788 | +CONFIG_NLS=y |
| 6789 | + |
| 6790 | +# |
| 6791 | +# Native Language Support |
| 6792 | +# |
| 6793 | +CONFIG_NLS_DEFAULT="iso8859-1" |
| 6794 | +# CONFIG_NLS_CODEPAGE_437 is not set |
| 6795 | +# CONFIG_NLS_CODEPAGE_737 is not set |
| 6796 | +# CONFIG_NLS_CODEPAGE_775 is not set |
| 6797 | +# CONFIG_NLS_CODEPAGE_850 is not set |
| 6798 | +# CONFIG_NLS_CODEPAGE_852 is not set |
| 6799 | +# CONFIG_NLS_CODEPAGE_855 is not set |
| 6800 | +# CONFIG_NLS_CODEPAGE_857 is not set |
| 6801 | +# CONFIG_NLS_CODEPAGE_860 is not set |
| 6802 | +# CONFIG_NLS_CODEPAGE_861 is not set |
| 6803 | +# CONFIG_NLS_CODEPAGE_862 is not set |
| 6804 | +# CONFIG_NLS_CODEPAGE_863 is not set |
| 6805 | +# CONFIG_NLS_CODEPAGE_864 is not set |
| 6806 | +# CONFIG_NLS_CODEPAGE_865 is not set |
| 6807 | +# CONFIG_NLS_CODEPAGE_866 is not set |
| 6808 | +# CONFIG_NLS_CODEPAGE_869 is not set |
| 6809 | +# CONFIG_NLS_CODEPAGE_936 is not set |
| 6810 | +# CONFIG_NLS_CODEPAGE_950 is not set |
| 6811 | +# CONFIG_NLS_CODEPAGE_932 is not set |
| 6812 | +# CONFIG_NLS_CODEPAGE_949 is not set |
| 6813 | +# CONFIG_NLS_CODEPAGE_874 is not set |
| 6814 | +# CONFIG_NLS_ISO8859_8 is not set |
| 6815 | +# CONFIG_NLS_CODEPAGE_1250 is not set |
| 6816 | +# CONFIG_NLS_CODEPAGE_1251 is not set |
| 6817 | +# CONFIG_NLS_ISO8859_1 is not set |
| 6818 | +# CONFIG_NLS_ISO8859_2 is not set |
| 6819 | +# CONFIG_NLS_ISO8859_3 is not set |
| 6820 | +# CONFIG_NLS_ISO8859_4 is not set |
| 6821 | +# CONFIG_NLS_ISO8859_5 is not set |
| 6822 | +# CONFIG_NLS_ISO8859_6 is not set |
| 6823 | +# CONFIG_NLS_ISO8859_7 is not set |
| 6824 | +# CONFIG_NLS_ISO8859_9 is not set |
| 6825 | +# CONFIG_NLS_ISO8859_13 is not set |
| 6826 | +# CONFIG_NLS_ISO8859_14 is not set |
| 6827 | +# CONFIG_NLS_ISO8859_15 is not set |
| 6828 | +# CONFIG_NLS_KOI8_R is not set |
| 6829 | +# CONFIG_NLS_KOI8_U is not set |
| 6830 | +# CONFIG_NLS_UTF8 is not set |
| 6831 | + |
| 6832 | +# |
| 6833 | +# Multimedia devices |
| 6834 | +# |
| 6835 | +# CONFIG_VIDEO_DEV is not set |
| 6836 | + |
| 6837 | +# |
| 6838 | +# Console drivers |
| 6839 | +# |
| 6840 | +# CONFIG_VGA_CONSOLE is not set |
| 6841 | +# CONFIG_MDA_CONSOLE is not set |
| 6842 | + |
| 6843 | +# |
| 6844 | +# Frame-buffer support |
| 6845 | +# |
| 6846 | +CONFIG_FB=y |
| 6847 | +CONFIG_DUMMY_CONSOLE=y |
| 6848 | +# CONFIG_FB_CYBER2000 is not set |
| 6849 | +# CONFIG_FB_VIRTUAL is not set |
| 6850 | +CONFIG_FBCON_ADVANCED=y |
| 6851 | +# CONFIG_FBCON_MFB is not set |
| 6852 | +# CONFIG_FBCON_CFB2 is not set |
| 6853 | +# CONFIG_FBCON_CFB4 is not set |
| 6854 | +# CONFIG_FBCON_CFB8 is not set |
| 6855 | +CONFIG_FBCON_CFB16=y |
| 6856 | +# CONFIG_FBCON_CFB24 is not set |
| 6857 | +# CONFIG_FBCON_CFB32 is not set |
| 6858 | +# CONFIG_FBCON_AFB is not set |
| 6859 | +# CONFIG_FBCON_ILBM is not set |
| 6860 | +# CONFIG_FBCON_IPLAN2P2 is not set |
| 6861 | +# CONFIG_FBCON_IPLAN2P4 is not set |
| 6862 | +# CONFIG_FBCON_IPLAN2P8 is not set |
| 6863 | +# CONFIG_FBCON_MAC is not set |
| 6864 | +# CONFIG_FBCON_VGA_PLANES is not set |
| 6865 | +# CONFIG_FBCON_VGA is not set |
| 6866 | +# CONFIG_FBCON_HGA is not set |
| 6867 | +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set |
| 6868 | +CONFIG_FBCON_FONTS=y |
| 6869 | +CONFIG_FONT_8x8=y |
| 6870 | +CONFIG_FONT_8x16=y |
| 6871 | +# CONFIG_FONT_SUN8x16 is not set |
| 6872 | +# CONFIG_FONT_SUN12x22 is not set |
| 6873 | +# CONFIG_FONT_6x11 is not set |
| 6874 | +# CONFIG_FONT_PEARL_8x8 is not set |
| 6875 | +# CONFIG_FONT_ACORN_8x8 is not set |
| 6876 | + |
| 6877 | +# |
| 6878 | +# Sound |
| 6879 | +# |
| 6880 | +CONFIG_SOUND=y |
| 6881 | +# CONFIG_SOUND_ALI5455 is not set |
| 6882 | +# CONFIG_SOUND_BT878 is not set |
| 6883 | +# CONFIG_SOUND_CMPCI is not set |
| 6884 | +# CONFIG_SOUND_EMU10K1 is not set |
| 6885 | +# CONFIG_MIDI_EMU10K1 is not set |
| 6886 | +# CONFIG_SOUND_FUSION is not set |
| 6887 | +# CONFIG_SOUND_CS4281 is not set |
| 6888 | +# CONFIG_SOUND_ES1370 is not set |
| 6889 | +# CONFIG_SOUND_ES1371 is not set |
| 6890 | +# CONFIG_SOUND_ESSSOLO1 is not set |
| 6891 | +# CONFIG_SOUND_MAESTRO is not set |
| 6892 | +# CONFIG_SOUND_MAESTRO3 is not set |
| 6893 | +# CONFIG_SOUND_FORTE is not set |
| 6894 | +# CONFIG_SOUND_ICH is not set |
| 6895 | +# CONFIG_SOUND_RME96XX is not set |
| 6896 | +# CONFIG_SOUND_SONICVIBES is not set |
| 6897 | +# CONFIG_SOUND_TRIDENT is not set |
| 6898 | +# CONFIG_SOUND_MSNDCLAS is not set |
| 6899 | +# CONFIG_SOUND_MSNDPIN is not set |
| 6900 | +# CONFIG_SOUND_VIA82CXXX is not set |
| 6901 | +# CONFIG_MIDI_VIA82CXXX is not set |
| 6902 | +# CONFIG_SOUND_OSS is not set |
| 6903 | +# CONFIG_SOUND_TVMIXER is not set |
| 6904 | +# CONFIG_SOUND_AD1980 is not set |
| 6905 | +# CONFIG_SOUND_WM97XX is not set |
| 6906 | + |
| 6907 | +# |
| 6908 | +# USB support |
| 6909 | +# |
| 6910 | +# CONFIG_USB is not set |
| 6911 | + |
| 6912 | +# |
| 6913 | +# Support for USB gadgets |
| 6914 | +# |
| 6915 | +# CONFIG_USB_GADGET is not set |
| 6916 | + |
| 6917 | +# |
| 6918 | +# Bluetooth support |
| 6919 | +# |
| 6920 | +# CONFIG_BLUEZ is not set |
| 6921 | + |
| 6922 | +# |
| 6923 | +# Kernel hacking |
| 6924 | +# |
| 6925 | +CONFIG_CROSSCOMPILE=y |
| 6926 | +# CONFIG_RUNTIME_DEBUG is not set |
| 6927 | +# CONFIG_KGDB is not set |
| 6928 | +# CONFIG_GDB_CONSOLE is not set |
| 6929 | +# CONFIG_DEBUG_INFO is not set |
| 6930 | +# CONFIG_MAGIC_SYSRQ is not set |
| 6931 | +# CONFIG_MIPS_UNCACHED is not set |
| 6932 | +CONFIG_LOG_BUF_SHIFT=0 |
| 6933 | + |
| 6934 | +# |
| 6935 | +# Cryptographic options |
| 6936 | +# |
| 6937 | +# CONFIG_CRYPTO is not set |
| 6938 | + |
| 6939 | +# |
| 6940 | +# Library routines |
| 6941 | +# |
| 6942 | +# CONFIG_CRC32 is not set |
| 6943 | +CONFIG_ZLIB_INFLATE=m |
| 6944 | +CONFIG_ZLIB_DEFLATE=m |
| 6945 | --- a/arch/mips/defconfig-hp-lj |
| 6946 | +++ b/arch/mips/defconfig-hp-lj |
| 6947 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 6948 | # CONFIG_MIPS_PB1000 is not set |
| 6949 | # CONFIG_MIPS_PB1100 is not set |
| 6950 | # CONFIG_MIPS_PB1500 is not set |
| 6951 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 6952 | # CONFIG_MIPS_PB1550 is not set |
| 6953 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 6954 | # CONFIG_MIPS_XXS1500 is not set |
| 6955 | # CONFIG_MIPS_MTX1 is not set |
| 6956 | # CONFIG_COGENT_CSB250 is not set |
| 6957 | @@ -184,8 +184,8 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 6958 | # Mapping drivers for chip access |
| 6959 | # |
| 6960 | CONFIG_MTD_PHYSMAP=y |
| 6961 | -CONFIG_MTD_PHYSMAP_START=10040000 |
| 6962 | -CONFIG_MTD_PHYSMAP_LEN=00fc0000 |
| 6963 | +CONFIG_MTD_PHYSMAP_START=0x10040000 |
| 6964 | +CONFIG_MTD_PHYSMAP_LEN=0x00fc0000 |
| 6965 | CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 6966 | # CONFIG_MTD_PB1000 is not set |
| 6967 | # CONFIG_MTD_PB1500 is not set |
| 6968 | @@ -193,9 +193,7 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 6969 | # CONFIG_MTD_BOSPORUS is not set |
| 6970 | # CONFIG_MTD_XXS1500 is not set |
| 6971 | # CONFIG_MTD_MTX1 is not set |
| 6972 | -# CONFIG_MTD_DB1X00 is not set |
| 6973 | # CONFIG_MTD_PB1550 is not set |
| 6974 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 6975 | # CONFIG_MTD_MIRAGE is not set |
| 6976 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 6977 | # CONFIG_MTD_OCELOT is not set |
| 6978 | @@ -214,7 +212,6 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 6979 | # |
| 6980 | # Disk-On-Chip Device Drivers |
| 6981 | # |
| 6982 | -# CONFIG_MTD_DOC1000 is not set |
| 6983 | # CONFIG_MTD_DOC2000 is not set |
| 6984 | # CONFIG_MTD_DOC2001 is not set |
| 6985 | # CONFIG_MTD_DOCPROBE is not set |
| 6986 | @@ -304,11 +301,6 @@ CONFIG_IP_PNP_DHCP=y |
| 6987 | # |
| 6988 | # CONFIG_IPX is not set |
| 6989 | # CONFIG_ATALK is not set |
| 6990 | - |
| 6991 | -# |
| 6992 | -# Appletalk devices |
| 6993 | -# |
| 6994 | -# CONFIG_DEV_APPLETALK is not set |
| 6995 | # CONFIG_DECNET is not set |
| 6996 | # CONFIG_BRIDGE is not set |
| 6997 | # CONFIG_X25 is not set |
| 6998 | @@ -604,7 +596,6 @@ CONFIG_SERIAL=y |
| 6999 | CONFIG_SERIAL_CONSOLE=y |
| 7000 | # CONFIG_SERIAL_EXTENDED is not set |
| 7001 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7002 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7003 | # CONFIG_UNIX98_PTYS is not set |
| 7004 | |
| 7005 | # |
| 7006 | --- a/arch/mips/defconfig-hydrogen3 |
| 7007 | +++ b/arch/mips/defconfig-hydrogen3 |
| 7008 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7009 | # CONFIG_MIPS_PB1000 is not set |
| 7010 | # CONFIG_MIPS_PB1100 is not set |
| 7011 | # CONFIG_MIPS_PB1500 is not set |
| 7012 | -CONFIG_MIPS_HYDROGEN3=y |
| 7013 | # CONFIG_MIPS_PB1550 is not set |
| 7014 | +CONFIG_MIPS_HYDROGEN3=y |
| 7015 | # CONFIG_MIPS_XXS1500 is not set |
| 7016 | # CONFIG_MIPS_MTX1 is not set |
| 7017 | # CONFIG_COGENT_CSB250 is not set |
| 7018 | @@ -214,9 +214,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 7019 | # CONFIG_MTD_BOSPORUS is not set |
| 7020 | # CONFIG_MTD_XXS1500 is not set |
| 7021 | # CONFIG_MTD_MTX1 is not set |
| 7022 | -# CONFIG_MTD_DB1X00 is not set |
| 7023 | # CONFIG_MTD_PB1550 is not set |
| 7024 | -CONFIG_MTD_HYDROGEN3=y |
| 7025 | # CONFIG_MTD_MIRAGE is not set |
| 7026 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7027 | # CONFIG_MTD_OCELOT is not set |
| 7028 | @@ -235,7 +233,6 @@ CONFIG_MTD_HYDROGEN3=y |
| 7029 | # |
| 7030 | # Disk-On-Chip Device Drivers |
| 7031 | # |
| 7032 | -# CONFIG_MTD_DOC1000 is not set |
| 7033 | # CONFIG_MTD_DOC2000 is not set |
| 7034 | # CONFIG_MTD_DOC2001 is not set |
| 7035 | # CONFIG_MTD_DOCPROBE is not set |
| 7036 | @@ -340,11 +337,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7037 | # |
| 7038 | # CONFIG_IPX is not set |
| 7039 | # CONFIG_ATALK is not set |
| 7040 | - |
| 7041 | -# |
| 7042 | -# Appletalk devices |
| 7043 | -# |
| 7044 | -# CONFIG_DEV_APPLETALK is not set |
| 7045 | # CONFIG_DECNET is not set |
| 7046 | # CONFIG_BRIDGE is not set |
| 7047 | # CONFIG_X25 is not set |
| 7048 | @@ -590,7 +582,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 7049 | # CONFIG_AU1X00_USB_TTY is not set |
| 7050 | # CONFIG_AU1X00_USB_RAW is not set |
| 7051 | # CONFIG_TXX927_SERIAL is not set |
| 7052 | -CONFIG_MIPS_HYDROGEN3_BUTTONS=y |
| 7053 | CONFIG_UNIX98_PTYS=y |
| 7054 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7055 | |
| 7056 | @@ -838,6 +829,7 @@ CONFIG_DUMMY_CONSOLE=y |
| 7057 | # CONFIG_FB_PM2 is not set |
| 7058 | # CONFIG_FB_PM3 is not set |
| 7059 | # CONFIG_FB_CYBER2000 is not set |
| 7060 | +CONFIG_FB_AU1100=y |
| 7061 | # CONFIG_FB_MATROX is not set |
| 7062 | # CONFIG_FB_ATY is not set |
| 7063 | # CONFIG_FB_RADEON is not set |
| 7064 | @@ -849,7 +841,6 @@ CONFIG_DUMMY_CONSOLE=y |
| 7065 | # CONFIG_FB_VOODOO1 is not set |
| 7066 | # CONFIG_FB_TRIDENT is not set |
| 7067 | # CONFIG_FB_E1356 is not set |
| 7068 | -CONFIG_FB_AU1100=y |
| 7069 | # CONFIG_FB_IT8181 is not set |
| 7070 | # CONFIG_FB_VIRTUAL is not set |
| 7071 | CONFIG_FBCON_ADVANCED=y |
| 7072 | --- a/arch/mips/defconfig-ip22 |
| 7073 | +++ b/arch/mips/defconfig-ip22 |
| 7074 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7075 | # CONFIG_MIPS_PB1000 is not set |
| 7076 | # CONFIG_MIPS_PB1100 is not set |
| 7077 | # CONFIG_MIPS_PB1500 is not set |
| 7078 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7079 | # CONFIG_MIPS_PB1550 is not set |
| 7080 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7081 | # CONFIG_MIPS_XXS1500 is not set |
| 7082 | # CONFIG_MIPS_MTX1 is not set |
| 7083 | # CONFIG_COGENT_CSB250 is not set |
| 7084 | @@ -235,11 +235,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7085 | # |
| 7086 | # CONFIG_IPX is not set |
| 7087 | # CONFIG_ATALK is not set |
| 7088 | - |
| 7089 | -# |
| 7090 | -# Appletalk devices |
| 7091 | -# |
| 7092 | -# CONFIG_DEV_APPLETALK is not set |
| 7093 | # CONFIG_DECNET is not set |
| 7094 | # CONFIG_BRIDGE is not set |
| 7095 | # CONFIG_X25 is not set |
| 7096 | @@ -319,9 +314,11 @@ CONFIG_SGIWD93_SCSI=y |
| 7097 | # CONFIG_SCSI_MEGARAID is not set |
| 7098 | # CONFIG_SCSI_MEGARAID2 is not set |
| 7099 | # CONFIG_SCSI_SATA is not set |
| 7100 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 7101 | # CONFIG_SCSI_SATA_SVW is not set |
| 7102 | # CONFIG_SCSI_ATA_PIIX is not set |
| 7103 | # CONFIG_SCSI_SATA_NV is not set |
| 7104 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 7105 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 7106 | # CONFIG_SCSI_SATA_SX4 is not set |
| 7107 | # CONFIG_SCSI_SATA_SIL is not set |
| 7108 | @@ -465,7 +462,6 @@ CONFIG_VT_CONSOLE=y |
| 7109 | # CONFIG_SERIAL is not set |
| 7110 | # CONFIG_SERIAL_EXTENDED is not set |
| 7111 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7112 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7113 | CONFIG_UNIX98_PTYS=y |
| 7114 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7115 | |
| 7116 | --- a/arch/mips/defconfig-it8172 |
| 7117 | +++ b/arch/mips/defconfig-it8172 |
| 7118 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7119 | # CONFIG_MIPS_PB1000 is not set |
| 7120 | # CONFIG_MIPS_PB1100 is not set |
| 7121 | # CONFIG_MIPS_PB1500 is not set |
| 7122 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7123 | # CONFIG_MIPS_PB1550 is not set |
| 7124 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7125 | # CONFIG_MIPS_XXS1500 is not set |
| 7126 | # CONFIG_MIPS_MTX1 is not set |
| 7127 | # CONFIG_COGENT_CSB250 is not set |
| 7128 | @@ -186,8 +186,8 @@ CONFIG_MTD_CFI_INTELEXT=y |
| 7129 | # Mapping drivers for chip access |
| 7130 | # |
| 7131 | CONFIG_MTD_PHYSMAP=y |
| 7132 | -CONFIG_MTD_PHYSMAP_START=8000000 |
| 7133 | -CONFIG_MTD_PHYSMAP_LEN=2000000 |
| 7134 | +CONFIG_MTD_PHYSMAP_START=0x8000000 |
| 7135 | +CONFIG_MTD_PHYSMAP_LEN=0x2000000 |
| 7136 | CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 7137 | # CONFIG_MTD_PB1000 is not set |
| 7138 | # CONFIG_MTD_PB1500 is not set |
| 7139 | @@ -195,9 +195,7 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 7140 | # CONFIG_MTD_BOSPORUS is not set |
| 7141 | # CONFIG_MTD_XXS1500 is not set |
| 7142 | # CONFIG_MTD_MTX1 is not set |
| 7143 | -# CONFIG_MTD_DB1X00 is not set |
| 7144 | # CONFIG_MTD_PB1550 is not set |
| 7145 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7146 | # CONFIG_MTD_MIRAGE is not set |
| 7147 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7148 | # CONFIG_MTD_OCELOT is not set |
| 7149 | @@ -216,7 +214,6 @@ CONFIG_MTD_PHYSMAP_BUSWIDTH=4 |
| 7150 | # |
| 7151 | # Disk-On-Chip Device Drivers |
| 7152 | # |
| 7153 | -# CONFIG_MTD_DOC1000 is not set |
| 7154 | # CONFIG_MTD_DOC2000 is not set |
| 7155 | # CONFIG_MTD_DOC2001 is not set |
| 7156 | # CONFIG_MTD_DOCPROBE is not set |
| 7157 | @@ -304,11 +301,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7158 | # |
| 7159 | # CONFIG_IPX is not set |
| 7160 | # CONFIG_ATALK is not set |
| 7161 | - |
| 7162 | -# |
| 7163 | -# Appletalk devices |
| 7164 | -# |
| 7165 | -# CONFIG_DEV_APPLETALK is not set |
| 7166 | # CONFIG_DECNET is not set |
| 7167 | # CONFIG_BRIDGE is not set |
| 7168 | # CONFIG_X25 is not set |
| 7169 | @@ -592,7 +584,6 @@ CONFIG_SERIAL_CONSOLE=y |
| 7170 | CONFIG_PC_KEYB=y |
| 7171 | # CONFIG_IT8172_SCR0 is not set |
| 7172 | # CONFIG_IT8172_SCR1 is not set |
| 7173 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7174 | CONFIG_UNIX98_PTYS=y |
| 7175 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7176 | |
| 7177 | --- a/arch/mips/defconfig-ivr |
| 7178 | +++ b/arch/mips/defconfig-ivr |
| 7179 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7180 | # CONFIG_MIPS_PB1000 is not set |
| 7181 | # CONFIG_MIPS_PB1100 is not set |
| 7182 | # CONFIG_MIPS_PB1500 is not set |
| 7183 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7184 | # CONFIG_MIPS_PB1550 is not set |
| 7185 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7186 | # CONFIG_MIPS_XXS1500 is not set |
| 7187 | # CONFIG_MIPS_MTX1 is not set |
| 7188 | # CONFIG_COGENT_CSB250 is not set |
| 7189 | @@ -226,11 +226,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7190 | # |
| 7191 | # CONFIG_IPX is not set |
| 7192 | # CONFIG_ATALK is not set |
| 7193 | - |
| 7194 | -# |
| 7195 | -# Appletalk devices |
| 7196 | -# |
| 7197 | -# CONFIG_DEV_APPLETALK is not set |
| 7198 | # CONFIG_DECNET is not set |
| 7199 | # CONFIG_BRIDGE is not set |
| 7200 | # CONFIG_X25 is not set |
| 7201 | @@ -516,7 +511,6 @@ CONFIG_SERIAL_CONSOLE=y |
| 7202 | CONFIG_QTRONIX_KEYBOARD=y |
| 7203 | CONFIG_IT8172_CIR=y |
| 7204 | # CONFIG_IT8172_SCR0 is not set |
| 7205 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7206 | CONFIG_UNIX98_PTYS=y |
| 7207 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7208 | |
| 7209 | --- a/arch/mips/defconfig-jmr3927 |
| 7210 | +++ b/arch/mips/defconfig-jmr3927 |
| 7211 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 7212 | # CONFIG_MIPS_PB1000 is not set |
| 7213 | # CONFIG_MIPS_PB1100 is not set |
| 7214 | # CONFIG_MIPS_PB1500 is not set |
| 7215 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7216 | # CONFIG_MIPS_PB1550 is not set |
| 7217 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7218 | # CONFIG_MIPS_XXS1500 is not set |
| 7219 | # CONFIG_MIPS_MTX1 is not set |
| 7220 | # CONFIG_COGENT_CSB250 is not set |
| 7221 | @@ -225,11 +225,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7222 | # |
| 7223 | # CONFIG_IPX is not set |
| 7224 | # CONFIG_ATALK is not set |
| 7225 | - |
| 7226 | -# |
| 7227 | -# Appletalk devices |
| 7228 | -# |
| 7229 | -# CONFIG_DEV_APPLETALK is not set |
| 7230 | # CONFIG_DECNET is not set |
| 7231 | # CONFIG_BRIDGE is not set |
| 7232 | # CONFIG_X25 is not set |
| 7233 | @@ -454,7 +449,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 7234 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 7235 | CONFIG_TXX927_SERIAL=y |
| 7236 | CONFIG_TXX927_SERIAL_CONSOLE=y |
| 7237 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7238 | # CONFIG_UNIX98_PTYS is not set |
| 7239 | |
| 7240 | # |
| 7241 | --- a/arch/mips/defconfig-lasat |
| 7242 | +++ b/arch/mips/defconfig-lasat |
| 7243 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7244 | # CONFIG_MIPS_PB1000 is not set |
| 7245 | # CONFIG_MIPS_PB1100 is not set |
| 7246 | # CONFIG_MIPS_PB1500 is not set |
| 7247 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7248 | # CONFIG_MIPS_PB1550 is not set |
| 7249 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7250 | # CONFIG_MIPS_XXS1500 is not set |
| 7251 | # CONFIG_MIPS_MTX1 is not set |
| 7252 | # CONFIG_COGENT_CSB250 is not set |
| 7253 | @@ -198,9 +198,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 7254 | # CONFIG_MTD_BOSPORUS is not set |
| 7255 | # CONFIG_MTD_XXS1500 is not set |
| 7256 | # CONFIG_MTD_MTX1 is not set |
| 7257 | -# CONFIG_MTD_DB1X00 is not set |
| 7258 | # CONFIG_MTD_PB1550 is not set |
| 7259 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7260 | # CONFIG_MTD_MIRAGE is not set |
| 7261 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7262 | # CONFIG_MTD_OCELOT is not set |
| 7263 | @@ -219,7 +217,6 @@ CONFIG_MTD_LASAT=y |
| 7264 | # |
| 7265 | # Disk-On-Chip Device Drivers |
| 7266 | # |
| 7267 | -# CONFIG_MTD_DOC1000 is not set |
| 7268 | # CONFIG_MTD_DOC2000 is not set |
| 7269 | # CONFIG_MTD_DOC2001 is not set |
| 7270 | # CONFIG_MTD_DOCPROBE is not set |
| 7271 | @@ -303,11 +300,6 @@ CONFIG_INET=y |
| 7272 | # |
| 7273 | # CONFIG_IPX is not set |
| 7274 | # CONFIG_ATALK is not set |
| 7275 | - |
| 7276 | -# |
| 7277 | -# Appletalk devices |
| 7278 | -# |
| 7279 | -# CONFIG_DEV_APPLETALK is not set |
| 7280 | # CONFIG_DECNET is not set |
| 7281 | # CONFIG_BRIDGE is not set |
| 7282 | # CONFIG_X25 is not set |
| 7283 | @@ -584,7 +576,6 @@ CONFIG_SERIAL=y |
| 7284 | CONFIG_SERIAL_CONSOLE=y |
| 7285 | # CONFIG_SERIAL_EXTENDED is not set |
| 7286 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7287 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7288 | CONFIG_UNIX98_PTYS=y |
| 7289 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7290 | |
| 7291 | --- a/arch/mips/defconfig-malta |
| 7292 | +++ b/arch/mips/defconfig-malta |
| 7293 | @@ -22,16 +22,19 @@ CONFIG_KMOD=y |
| 7294 | # |
| 7295 | # CONFIG_ACER_PICA_61 is not set |
| 7296 | # CONFIG_MIPS_BOSPORUS is not set |
| 7297 | +# CONFIG_MIPS_FICMMP is not set |
| 7298 | # CONFIG_MIPS_MIRAGE is not set |
| 7299 | # CONFIG_MIPS_DB1000 is not set |
| 7300 | # CONFIG_MIPS_DB1100 is not set |
| 7301 | # CONFIG_MIPS_DB1500 is not set |
| 7302 | # CONFIG_MIPS_DB1550 is not set |
| 7303 | +# CONFIG_MIPS_DB1200 is not set |
| 7304 | # CONFIG_MIPS_PB1000 is not set |
| 7305 | # CONFIG_MIPS_PB1100 is not set |
| 7306 | # CONFIG_MIPS_PB1500 is not set |
| 7307 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7308 | # CONFIG_MIPS_PB1550 is not set |
| 7309 | +# CONFIG_MIPS_PB1200 is not set |
| 7310 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7311 | # CONFIG_MIPS_XXS1500 is not set |
| 7312 | # CONFIG_MIPS_MTX1 is not set |
| 7313 | # CONFIG_COGENT_CSB250 is not set |
| 7314 | @@ -237,11 +240,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7315 | # |
| 7316 | # CONFIG_IPX is not set |
| 7317 | # CONFIG_ATALK is not set |
| 7318 | - |
| 7319 | -# |
| 7320 | -# Appletalk devices |
| 7321 | -# |
| 7322 | -# CONFIG_DEV_APPLETALK is not set |
| 7323 | # CONFIG_DECNET is not set |
| 7324 | # CONFIG_BRIDGE is not set |
| 7325 | # CONFIG_X25 is not set |
| 7326 | @@ -273,8 +271,83 @@ CONFIG_IP_PNP_BOOTP=y |
| 7327 | # |
| 7328 | # ATA/IDE/MFM/RLL support |
| 7329 | # |
| 7330 | -# CONFIG_IDE is not set |
| 7331 | +CONFIG_IDE=y |
| 7332 | + |
| 7333 | +# |
| 7334 | +# IDE, ATA and ATAPI Block devices |
| 7335 | +# |
| 7336 | +CONFIG_BLK_DEV_IDE=y |
| 7337 | + |
| 7338 | +# |
| 7339 | +# Please see Documentation/ide.txt for help/info on IDE drives |
| 7340 | +# |
| 7341 | +# CONFIG_BLK_DEV_HD_IDE is not set |
| 7342 | # CONFIG_BLK_DEV_HD is not set |
| 7343 | +# CONFIG_BLK_DEV_IDE_SATA is not set |
| 7344 | +CONFIG_BLK_DEV_IDEDISK=y |
| 7345 | +# CONFIG_IDEDISK_MULTI_MODE is not set |
| 7346 | +# CONFIG_IDEDISK_STROKE is not set |
| 7347 | +# CONFIG_BLK_DEV_IDECS is not set |
| 7348 | +# CONFIG_BLK_DEV_DELKIN is not set |
| 7349 | +CONFIG_BLK_DEV_IDECD=y |
| 7350 | +CONFIG_BLK_DEV_IDETAPE=y |
| 7351 | +CONFIG_BLK_DEV_IDEFLOPPY=y |
| 7352 | +CONFIG_BLK_DEV_IDESCSI=y |
| 7353 | +# CONFIG_IDE_TASK_IOCTL is not set |
| 7354 | + |
| 7355 | +# |
| 7356 | +# IDE chipset support/bugfixes |
| 7357 | +# |
| 7358 | +# CONFIG_BLK_DEV_CMD640 is not set |
| 7359 | +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set |
| 7360 | +# CONFIG_BLK_DEV_ISAPNP is not set |
| 7361 | +CONFIG_BLK_DEV_IDEPCI=y |
| 7362 | +CONFIG_BLK_DEV_GENERIC=y |
| 7363 | +CONFIG_IDEPCI_SHARE_IRQ=y |
| 7364 | +CONFIG_BLK_DEV_IDEDMA_PCI=y |
| 7365 | +# CONFIG_BLK_DEV_OFFBOARD is not set |
| 7366 | +CONFIG_BLK_DEV_IDEDMA_FORCED=y |
| 7367 | +CONFIG_IDEDMA_PCI_AUTO=y |
| 7368 | +# CONFIG_IDEDMA_ONLYDISK is not set |
| 7369 | +CONFIG_BLK_DEV_IDEDMA=y |
| 7370 | +# CONFIG_IDEDMA_PCI_WIP is not set |
| 7371 | +# CONFIG_BLK_DEV_ADMA100 is not set |
| 7372 | +# CONFIG_BLK_DEV_AEC62XX is not set |
| 7373 | +# CONFIG_BLK_DEV_ALI15X3 is not set |
| 7374 | +# CONFIG_WDC_ALI15X3 is not set |
| 7375 | +# CONFIG_BLK_DEV_AMD74XX is not set |
| 7376 | +# CONFIG_AMD74XX_OVERRIDE is not set |
| 7377 | +# CONFIG_BLK_DEV_ATIIXP is not set |
| 7378 | +# CONFIG_BLK_DEV_CMD64X is not set |
| 7379 | +# CONFIG_BLK_DEV_TRIFLEX is not set |
| 7380 | +# CONFIG_BLK_DEV_CY82C693 is not set |
| 7381 | +# CONFIG_BLK_DEV_CS5530 is not set |
| 7382 | +# CONFIG_BLK_DEV_HPT34X is not set |
| 7383 | +# CONFIG_HPT34X_AUTODMA is not set |
| 7384 | +# CONFIG_BLK_DEV_HPT366 is not set |
| 7385 | +CONFIG_BLK_DEV_PIIX=y |
| 7386 | +# CONFIG_BLK_DEV_NS87415 is not set |
| 7387 | +# CONFIG_BLK_DEV_OPTI621 is not set |
| 7388 | +# CONFIG_BLK_DEV_PDC202XX_OLD is not set |
| 7389 | +# CONFIG_PDC202XX_BURST is not set |
| 7390 | +# CONFIG_BLK_DEV_PDC202XX_NEW is not set |
| 7391 | +# CONFIG_BLK_DEV_RZ1000 is not set |
| 7392 | +# CONFIG_BLK_DEV_SC1200 is not set |
| 7393 | +# CONFIG_BLK_DEV_SVWKS is not set |
| 7394 | +# CONFIG_BLK_DEV_SIIMAGE is not set |
| 7395 | +# CONFIG_BLK_DEV_SIS5513 is not set |
| 7396 | +# CONFIG_BLK_DEV_SLC90E66 is not set |
| 7397 | +# CONFIG_BLK_DEV_TRM290 is not set |
| 7398 | +# CONFIG_BLK_DEV_VIA82CXXX is not set |
| 7399 | +# CONFIG_IDE_CHIPSETS is not set |
| 7400 | +CONFIG_IDEDMA_AUTO=y |
| 7401 | +# CONFIG_IDEDMA_IVB is not set |
| 7402 | +# CONFIG_DMA_NONPCI is not set |
| 7403 | +# CONFIG_BLK_DEV_ATARAID is not set |
| 7404 | +# CONFIG_BLK_DEV_ATARAID_PDC is not set |
| 7405 | +# CONFIG_BLK_DEV_ATARAID_HPT is not set |
| 7406 | +# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set |
| 7407 | +# CONFIG_BLK_DEV_ATARAID_SII is not set |
| 7408 | |
| 7409 | # |
| 7410 | # SCSI support |
| 7411 | @@ -319,9 +392,11 @@ CONFIG_SD_EXTRA_DEVS=40 |
| 7412 | # CONFIG_SCSI_MEGARAID is not set |
| 7413 | # CONFIG_SCSI_MEGARAID2 is not set |
| 7414 | # CONFIG_SCSI_SATA is not set |
| 7415 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 7416 | # CONFIG_SCSI_SATA_SVW is not set |
| 7417 | # CONFIG_SCSI_ATA_PIIX is not set |
| 7418 | # CONFIG_SCSI_SATA_NV is not set |
| 7419 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 7420 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 7421 | # CONFIG_SCSI_SATA_SX4 is not set |
| 7422 | # CONFIG_SCSI_SATA_SIL is not set |
| 7423 | @@ -524,7 +599,6 @@ CONFIG_SERIAL=y |
| 7424 | CONFIG_SERIAL_CONSOLE=y |
| 7425 | # CONFIG_SERIAL_EXTENDED is not set |
| 7426 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7427 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7428 | CONFIG_UNIX98_PTYS=y |
| 7429 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7430 | |
| 7431 | --- a/arch/mips/defconfig-mirage |
| 7432 | +++ b/arch/mips/defconfig-mirage |
| 7433 | @@ -30,8 +30,8 @@ CONFIG_MIPS_MIRAGE=y |
| 7434 | # CONFIG_MIPS_PB1000 is not set |
| 7435 | # CONFIG_MIPS_PB1100 is not set |
| 7436 | # CONFIG_MIPS_PB1500 is not set |
| 7437 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7438 | # CONFIG_MIPS_PB1550 is not set |
| 7439 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7440 | # CONFIG_MIPS_XXS1500 is not set |
| 7441 | # CONFIG_MIPS_MTX1 is not set |
| 7442 | # CONFIG_COGENT_CSB250 is not set |
| 7443 | @@ -209,9 +209,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 7444 | # CONFIG_MTD_BOSPORUS is not set |
| 7445 | # CONFIG_MTD_XXS1500 is not set |
| 7446 | # CONFIG_MTD_MTX1 is not set |
| 7447 | -# CONFIG_MTD_DB1X00 is not set |
| 7448 | # CONFIG_MTD_PB1550 is not set |
| 7449 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7450 | CONFIG_MTD_MIRAGE=y |
| 7451 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7452 | # CONFIG_MTD_OCELOT is not set |
| 7453 | @@ -230,7 +228,6 @@ CONFIG_MTD_MIRAGE=y |
| 7454 | # |
| 7455 | # Disk-On-Chip Device Drivers |
| 7456 | # |
| 7457 | -# CONFIG_MTD_DOC1000 is not set |
| 7458 | # CONFIG_MTD_DOC2000 is not set |
| 7459 | # CONFIG_MTD_DOC2001 is not set |
| 7460 | # CONFIG_MTD_DOCPROBE is not set |
| 7461 | @@ -335,11 +332,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7462 | # |
| 7463 | # CONFIG_IPX is not set |
| 7464 | # CONFIG_ATALK is not set |
| 7465 | - |
| 7466 | -# |
| 7467 | -# Appletalk devices |
| 7468 | -# |
| 7469 | -# CONFIG_DEV_APPLETALK is not set |
| 7470 | # CONFIG_DECNET is not set |
| 7471 | # CONFIG_BRIDGE is not set |
| 7472 | # CONFIG_X25 is not set |
| 7473 | @@ -560,7 +552,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 7474 | # CONFIG_AU1X00_USB_TTY is not set |
| 7475 | # CONFIG_AU1X00_USB_RAW is not set |
| 7476 | # CONFIG_TXX927_SERIAL is not set |
| 7477 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7478 | CONFIG_UNIX98_PTYS=y |
| 7479 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7480 | |
| 7481 | --- a/arch/mips/defconfig-mpc30x |
| 7482 | +++ b/arch/mips/defconfig-mpc30x |
| 7483 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7484 | # CONFIG_MIPS_PB1000 is not set |
| 7485 | # CONFIG_MIPS_PB1100 is not set |
| 7486 | # CONFIG_MIPS_PB1500 is not set |
| 7487 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7488 | # CONFIG_MIPS_PB1550 is not set |
| 7489 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7490 | # CONFIG_MIPS_XXS1500 is not set |
| 7491 | # CONFIG_MIPS_MTX1 is not set |
| 7492 | # CONFIG_COGENT_CSB250 is not set |
| 7493 | @@ -228,11 +228,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7494 | # |
| 7495 | # CONFIG_IPX is not set |
| 7496 | # CONFIG_ATALK is not set |
| 7497 | - |
| 7498 | -# |
| 7499 | -# Appletalk devices |
| 7500 | -# |
| 7501 | -# CONFIG_DEV_APPLETALK is not set |
| 7502 | # CONFIG_DECNET is not set |
| 7503 | # CONFIG_BRIDGE is not set |
| 7504 | # CONFIG_X25 is not set |
| 7505 | @@ -400,7 +395,6 @@ CONFIG_SERIAL=y |
| 7506 | CONFIG_SERIAL_CONSOLE=y |
| 7507 | # CONFIG_SERIAL_EXTENDED is not set |
| 7508 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7509 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7510 | # CONFIG_VR41XX_KIU is not set |
| 7511 | CONFIG_UNIX98_PTYS=y |
| 7512 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7513 | --- a/arch/mips/defconfig-mtx-1 |
| 7514 | +++ b/arch/mips/defconfig-mtx-1 |
| 7515 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7516 | # CONFIG_MIPS_PB1000 is not set |
| 7517 | # CONFIG_MIPS_PB1100 is not set |
| 7518 | # CONFIG_MIPS_PB1500 is not set |
| 7519 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7520 | # CONFIG_MIPS_PB1550 is not set |
| 7521 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7522 | # CONFIG_MIPS_XXS1500 is not set |
| 7523 | CONFIG_MIPS_MTX1=y |
| 7524 | # CONFIG_COGENT_CSB250 is not set |
| 7525 | @@ -193,9 +193,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 7526 | # CONFIG_MTD_BOSPORUS is not set |
| 7527 | # CONFIG_MTD_XXS1500 is not set |
| 7528 | CONFIG_MTD_MTX1=y |
| 7529 | -# CONFIG_MTD_DB1X00 is not set |
| 7530 | # CONFIG_MTD_PB1550 is not set |
| 7531 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7532 | # CONFIG_MTD_MIRAGE is not set |
| 7533 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7534 | # CONFIG_MTD_OCELOT is not set |
| 7535 | @@ -214,7 +212,6 @@ CONFIG_MTD_MTX1=y |
| 7536 | # |
| 7537 | # Disk-On-Chip Device Drivers |
| 7538 | # |
| 7539 | -# CONFIG_MTD_DOC1000 is not set |
| 7540 | # CONFIG_MTD_DOC2000 is not set |
| 7541 | # CONFIG_MTD_DOC2001 is not set |
| 7542 | # CONFIG_MTD_DOCPROBE is not set |
| 7543 | @@ -371,11 +368,6 @@ CONFIG_VLAN_8021Q=m |
| 7544 | # |
| 7545 | # CONFIG_IPX is not set |
| 7546 | # CONFIG_ATALK is not set |
| 7547 | - |
| 7548 | -# |
| 7549 | -# Appletalk devices |
| 7550 | -# |
| 7551 | -# CONFIG_DEV_APPLETALK is not set |
| 7552 | # CONFIG_DECNET is not set |
| 7553 | CONFIG_BRIDGE=m |
| 7554 | # CONFIG_X25 is not set |
| 7555 | @@ -479,9 +471,11 @@ CONFIG_SR_EXTRA_DEVS=2 |
| 7556 | # CONFIG_SCSI_MEGARAID is not set |
| 7557 | # CONFIG_SCSI_MEGARAID2 is not set |
| 7558 | # CONFIG_SCSI_SATA is not set |
| 7559 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 7560 | # CONFIG_SCSI_SATA_SVW is not set |
| 7561 | # CONFIG_SCSI_ATA_PIIX is not set |
| 7562 | # CONFIG_SCSI_SATA_NV is not set |
| 7563 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 7564 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 7565 | # CONFIG_SCSI_SATA_SX4 is not set |
| 7566 | # CONFIG_SCSI_SATA_SIL is not set |
| 7567 | @@ -700,7 +694,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 7568 | # CONFIG_AU1X00_USB_TTY is not set |
| 7569 | # CONFIG_AU1X00_USB_RAW is not set |
| 7570 | # CONFIG_TXX927_SERIAL is not set |
| 7571 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7572 | CONFIG_UNIX98_PTYS=y |
| 7573 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7574 | |
| 7575 | --- a/arch/mips/defconfig-nino |
| 7576 | +++ b/arch/mips/defconfig-nino |
| 7577 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7578 | # CONFIG_MIPS_PB1000 is not set |
| 7579 | # CONFIG_MIPS_PB1100 is not set |
| 7580 | # CONFIG_MIPS_PB1500 is not set |
| 7581 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7582 | # CONFIG_MIPS_PB1550 is not set |
| 7583 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7584 | # CONFIG_MIPS_XXS1500 is not set |
| 7585 | # CONFIG_MIPS_MTX1 is not set |
| 7586 | # CONFIG_COGENT_CSB250 is not set |
| 7587 | @@ -226,11 +226,6 @@ CONFIG_INET=y |
| 7588 | # |
| 7589 | # CONFIG_IPX is not set |
| 7590 | # CONFIG_ATALK is not set |
| 7591 | - |
| 7592 | -# |
| 7593 | -# Appletalk devices |
| 7594 | -# |
| 7595 | -# CONFIG_DEV_APPLETALK is not set |
| 7596 | # CONFIG_DECNET is not set |
| 7597 | # CONFIG_BRIDGE is not set |
| 7598 | # CONFIG_X25 is not set |
| 7599 | @@ -339,7 +334,6 @@ CONFIG_SERIAL_TX3912_CONSOLE=y |
| 7600 | # CONFIG_SERIAL_TXX9 is not set |
| 7601 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 7602 | # CONFIG_TXX927_SERIAL is not set |
| 7603 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7604 | # CONFIG_UNIX98_PTYS is not set |
| 7605 | |
| 7606 | # |
| 7607 | --- a/arch/mips/defconfig-ocelot |
| 7608 | +++ b/arch/mips/defconfig-ocelot |
| 7609 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 7610 | # CONFIG_MIPS_PB1000 is not set |
| 7611 | # CONFIG_MIPS_PB1100 is not set |
| 7612 | # CONFIG_MIPS_PB1500 is not set |
| 7613 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7614 | # CONFIG_MIPS_PB1550 is not set |
| 7615 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7616 | # CONFIG_MIPS_XXS1500 is not set |
| 7617 | # CONFIG_MIPS_MTX1 is not set |
| 7618 | # CONFIG_COGENT_CSB250 is not set |
| 7619 | @@ -194,9 +194,7 @@ CONFIG_MTD_JEDEC=y |
| 7620 | # CONFIG_MTD_BOSPORUS is not set |
| 7621 | # CONFIG_MTD_XXS1500 is not set |
| 7622 | # CONFIG_MTD_MTX1 is not set |
| 7623 | -# CONFIG_MTD_DB1X00 is not set |
| 7624 | # CONFIG_MTD_PB1550 is not set |
| 7625 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7626 | # CONFIG_MTD_MIRAGE is not set |
| 7627 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7628 | CONFIG_MTD_OCELOT=y |
| 7629 | @@ -215,7 +213,6 @@ CONFIG_MTD_OCELOT=y |
| 7630 | # |
| 7631 | # Disk-On-Chip Device Drivers |
| 7632 | # |
| 7633 | -# CONFIG_MTD_DOC1000 is not set |
| 7634 | CONFIG_MTD_DOC2000=y |
| 7635 | # CONFIG_MTD_DOC2001 is not set |
| 7636 | CONFIG_MTD_DOCPROBE=y |
| 7637 | @@ -307,11 +304,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7638 | # |
| 7639 | # CONFIG_IPX is not set |
| 7640 | # CONFIG_ATALK is not set |
| 7641 | - |
| 7642 | -# |
| 7643 | -# Appletalk devices |
| 7644 | -# |
| 7645 | -# CONFIG_DEV_APPLETALK is not set |
| 7646 | # CONFIG_DECNET is not set |
| 7647 | # CONFIG_BRIDGE is not set |
| 7648 | # CONFIG_X25 is not set |
| 7649 | @@ -513,7 +505,6 @@ CONFIG_SERIAL=y |
| 7650 | CONFIG_SERIAL_CONSOLE=y |
| 7651 | # CONFIG_SERIAL_EXTENDED is not set |
| 7652 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7653 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7654 | CONFIG_UNIX98_PTYS=y |
| 7655 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7656 | |
| 7657 | --- a/arch/mips/defconfig-osprey |
| 7658 | +++ b/arch/mips/defconfig-osprey |
| 7659 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7660 | # CONFIG_MIPS_PB1000 is not set |
| 7661 | # CONFIG_MIPS_PB1100 is not set |
| 7662 | # CONFIG_MIPS_PB1500 is not set |
| 7663 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7664 | # CONFIG_MIPS_PB1550 is not set |
| 7665 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7666 | # CONFIG_MIPS_XXS1500 is not set |
| 7667 | # CONFIG_MIPS_MTX1 is not set |
| 7668 | # CONFIG_COGENT_CSB250 is not set |
| 7669 | @@ -227,11 +227,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7670 | # |
| 7671 | # CONFIG_IPX is not set |
| 7672 | # CONFIG_ATALK is not set |
| 7673 | - |
| 7674 | -# |
| 7675 | -# Appletalk devices |
| 7676 | -# |
| 7677 | -# CONFIG_DEV_APPLETALK is not set |
| 7678 | # CONFIG_DECNET is not set |
| 7679 | # CONFIG_BRIDGE is not set |
| 7680 | # CONFIG_X25 is not set |
| 7681 | @@ -388,7 +383,6 @@ CONFIG_SERIAL_MANY_PORTS=y |
| 7682 | # CONFIG_SERIAL_MULTIPORT is not set |
| 7683 | # CONFIG_HUB6 is not set |
| 7684 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 7685 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7686 | # CONFIG_VR41XX_KIU is not set |
| 7687 | CONFIG_UNIX98_PTYS=y |
| 7688 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7689 | --- a/arch/mips/defconfig-pb1000 |
| 7690 | +++ b/arch/mips/defconfig-pb1000 |
| 7691 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7692 | CONFIG_MIPS_PB1000=y |
| 7693 | # CONFIG_MIPS_PB1100 is not set |
| 7694 | # CONFIG_MIPS_PB1500 is not set |
| 7695 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7696 | # CONFIG_MIPS_PB1550 is not set |
| 7697 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7698 | # CONFIG_MIPS_XXS1500 is not set |
| 7699 | # CONFIG_MIPS_MTX1 is not set |
| 7700 | # CONFIG_COGENT_CSB250 is not set |
| 7701 | @@ -215,9 +215,7 @@ CONFIG_MTD_PB1000=y |
| 7702 | # CONFIG_MTD_BOSPORUS is not set |
| 7703 | # CONFIG_MTD_XXS1500 is not set |
| 7704 | # CONFIG_MTD_MTX1 is not set |
| 7705 | -# CONFIG_MTD_DB1X00 is not set |
| 7706 | # CONFIG_MTD_PB1550 is not set |
| 7707 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7708 | # CONFIG_MTD_MIRAGE is not set |
| 7709 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7710 | # CONFIG_MTD_OCELOT is not set |
| 7711 | @@ -236,7 +234,6 @@ CONFIG_MTD_PB1000=y |
| 7712 | # |
| 7713 | # Disk-On-Chip Device Drivers |
| 7714 | # |
| 7715 | -# CONFIG_MTD_DOC1000 is not set |
| 7716 | # CONFIG_MTD_DOC2000 is not set |
| 7717 | # CONFIG_MTD_DOC2001 is not set |
| 7718 | # CONFIG_MTD_DOCPROBE is not set |
| 7719 | @@ -324,11 +321,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7720 | # |
| 7721 | # CONFIG_IPX is not set |
| 7722 | # CONFIG_ATALK is not set |
| 7723 | - |
| 7724 | -# |
| 7725 | -# Appletalk devices |
| 7726 | -# |
| 7727 | -# CONFIG_DEV_APPLETALK is not set |
| 7728 | # CONFIG_DECNET is not set |
| 7729 | # CONFIG_BRIDGE is not set |
| 7730 | # CONFIG_X25 is not set |
| 7731 | @@ -622,7 +614,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 7732 | # CONFIG_AU1X00_USB_TTY is not set |
| 7733 | # CONFIG_AU1X00_USB_RAW is not set |
| 7734 | # CONFIG_TXX927_SERIAL is not set |
| 7735 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7736 | CONFIG_UNIX98_PTYS=y |
| 7737 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7738 | |
| 7739 | @@ -707,7 +698,7 @@ CONFIG_UNIX98_PTY_COUNT=256 |
| 7740 | # |
| 7741 | # CONFIG_PCMCIA_SERIAL_CS is not set |
| 7742 | # CONFIG_SYNCLINK_CS is not set |
| 7743 | -CONFIG_AU1X00_GPIO=m |
| 7744 | +CONFIG_AU1X00_GPIO=y |
| 7745 | # CONFIG_TS_AU1X00_ADS7846 is not set |
| 7746 | |
| 7747 | # |
| 7748 | --- a/arch/mips/defconfig-pb1100 |
| 7749 | +++ b/arch/mips/defconfig-pb1100 |
| 7750 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 7751 | # CONFIG_MIPS_PB1000 is not set |
| 7752 | CONFIG_MIPS_PB1100=y |
| 7753 | # CONFIG_MIPS_PB1500 is not set |
| 7754 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 7755 | # CONFIG_MIPS_PB1550 is not set |
| 7756 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7757 | # CONFIG_MIPS_XXS1500 is not set |
| 7758 | # CONFIG_MIPS_MTX1 is not set |
| 7759 | # CONFIG_COGENT_CSB250 is not set |
| 7760 | @@ -198,9 +198,7 @@ CONFIG_MTD_PB1100=y |
| 7761 | # CONFIG_MTD_MTX1 is not set |
| 7762 | CONFIG_MTD_PB1500_BOOT=y |
| 7763 | CONFIG_MTD_PB1500_USER=y |
| 7764 | -# CONFIG_MTD_DB1X00 is not set |
| 7765 | # CONFIG_MTD_PB1550 is not set |
| 7766 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 7767 | # CONFIG_MTD_MIRAGE is not set |
| 7768 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 7769 | # CONFIG_MTD_OCELOT is not set |
| 7770 | @@ -219,7 +217,6 @@ CONFIG_MTD_PB1500_USER=y |
| 7771 | # |
| 7772 | # Disk-On-Chip Device Drivers |
| 7773 | # |
| 7774 | -# CONFIG_MTD_DOC1000 is not set |
| 7775 | # CONFIG_MTD_DOC2000 is not set |
| 7776 | # CONFIG_MTD_DOC2001 is not set |
| 7777 | # CONFIG_MTD_DOCPROBE is not set |
| 7778 | @@ -324,11 +321,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 7779 | # |
| 7780 | # CONFIG_IPX is not set |
| 7781 | # CONFIG_ATALK is not set |
| 7782 | - |
| 7783 | -# |
| 7784 | -# Appletalk devices |
| 7785 | -# |
| 7786 | -# CONFIG_DEV_APPLETALK is not set |
| 7787 | # CONFIG_DECNET is not set |
| 7788 | # CONFIG_BRIDGE is not set |
| 7789 | # CONFIG_X25 is not set |
| 7790 | @@ -613,7 +605,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 7791 | # CONFIG_AU1X00_USB_TTY is not set |
| 7792 | # CONFIG_AU1X00_USB_RAW is not set |
| 7793 | # CONFIG_TXX927_SERIAL is not set |
| 7794 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 7795 | CONFIG_UNIX98_PTYS=y |
| 7796 | CONFIG_UNIX98_PTY_COUNT=256 |
| 7797 | |
| 7798 | @@ -859,6 +850,7 @@ CONFIG_DUMMY_CONSOLE=y |
| 7799 | # CONFIG_FB_PM2 is not set |
| 7800 | # CONFIG_FB_PM3 is not set |
| 7801 | # CONFIG_FB_CYBER2000 is not set |
| 7802 | +CONFIG_FB_AU1100=y |
| 7803 | # CONFIG_FB_MATROX is not set |
| 7804 | # CONFIG_FB_ATY is not set |
| 7805 | # CONFIG_FB_RADEON is not set |
| 7806 | @@ -870,7 +862,6 @@ CONFIG_DUMMY_CONSOLE=y |
| 7807 | # CONFIG_FB_VOODOO1 is not set |
| 7808 | # CONFIG_FB_TRIDENT is not set |
| 7809 | # CONFIG_FB_E1356 is not set |
| 7810 | -CONFIG_FB_AU1100=y |
| 7811 | # CONFIG_FB_IT8181 is not set |
| 7812 | # CONFIG_FB_VIRTUAL is not set |
| 7813 | CONFIG_FBCON_ADVANCED=y |
| 7814 | --- /dev/null |
| 7815 | +++ b/arch/mips/defconfig-pb1200 |
| 7816 | @@ -0,0 +1,1060 @@ |
| 7817 | +# |
| 7818 | +# Automatically generated make config: don't edit |
| 7819 | +# |
| 7820 | +CONFIG_MIPS=y |
| 7821 | +CONFIG_MIPS32=y |
| 7822 | +# CONFIG_MIPS64 is not set |
| 7823 | + |
| 7824 | +# |
| 7825 | +# Code maturity level options |
| 7826 | +# |
| 7827 | +CONFIG_EXPERIMENTAL=y |
| 7828 | + |
| 7829 | +# |
| 7830 | +# Loadable module support |
| 7831 | +# |
| 7832 | +CONFIG_MODULES=y |
| 7833 | +# CONFIG_MODVERSIONS is not set |
| 7834 | +CONFIG_KMOD=y |
| 7835 | + |
| 7836 | +# |
| 7837 | +# Machine selection |
| 7838 | +# |
| 7839 | +# CONFIG_ACER_PICA_61 is not set |
| 7840 | +# CONFIG_MIPS_BOSPORUS is not set |
| 7841 | +# CONFIG_MIPS_MIRAGE is not set |
| 7842 | +# CONFIG_MIPS_DB1000 is not set |
| 7843 | +# CONFIG_MIPS_DB1100 is not set |
| 7844 | +# CONFIG_MIPS_DB1500 is not set |
| 7845 | +# CONFIG_MIPS_DB1550 is not set |
| 7846 | +# CONFIG_MIPS_PB1000 is not set |
| 7847 | +# CONFIG_MIPS_PB1100 is not set |
| 7848 | +# CONFIG_MIPS_PB1500 is not set |
| 7849 | +# CONFIG_MIPS_PB1550 is not set |
| 7850 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 7851 | +# CONFIG_MIPS_XXS1500 is not set |
| 7852 | +# CONFIG_MIPS_MTX1 is not set |
| 7853 | +# CONFIG_COGENT_CSB250 is not set |
| 7854 | +# CONFIG_BAGET_MIPS is not set |
| 7855 | +# CONFIG_CASIO_E55 is not set |
| 7856 | +# CONFIG_MIPS_COBALT is not set |
| 7857 | +# CONFIG_DECSTATION is not set |
| 7858 | +# CONFIG_MIPS_EV64120 is not set |
| 7859 | +# CONFIG_MIPS_EV96100 is not set |
| 7860 | +# CONFIG_MIPS_IVR is not set |
| 7861 | +# CONFIG_HP_LASERJET is not set |
| 7862 | +# CONFIG_IBM_WORKPAD is not set |
| 7863 | +# CONFIG_LASAT is not set |
| 7864 | +# CONFIG_MIPS_ITE8172 is not set |
| 7865 | +# CONFIG_MIPS_ATLAS is not set |
| 7866 | +# CONFIG_MIPS_MAGNUM_4000 is not set |
| 7867 | +# CONFIG_MIPS_MALTA is not set |
| 7868 | +# CONFIG_MIPS_SEAD is not set |
| 7869 | +# CONFIG_MOMENCO_OCELOT is not set |
| 7870 | +# CONFIG_MOMENCO_OCELOT_G is not set |
| 7871 | +# CONFIG_MOMENCO_OCELOT_C is not set |
| 7872 | +# CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 7873 | +# CONFIG_PMC_BIG_SUR is not set |
| 7874 | +# CONFIG_PMC_STRETCH is not set |
| 7875 | +# CONFIG_PMC_YOSEMITE is not set |
| 7876 | +# CONFIG_DDB5074 is not set |
| 7877 | +# CONFIG_DDB5476 is not set |
| 7878 | +# CONFIG_DDB5477 is not set |
| 7879 | +# CONFIG_NEC_OSPREY is not set |
| 7880 | +# CONFIG_NEC_EAGLE is not set |
| 7881 | +# CONFIG_OLIVETTI_M700 is not set |
| 7882 | +# CONFIG_NINO is not set |
| 7883 | +# CONFIG_SGI_IP22 is not set |
| 7884 | +# CONFIG_SGI_IP27 is not set |
| 7885 | +# CONFIG_SIBYTE_SB1xxx_SOC is not set |
| 7886 | +# CONFIG_SNI_RM200_PCI is not set |
| 7887 | +# CONFIG_TANBAC_TB0226 is not set |
| 7888 | +# CONFIG_TANBAC_TB0229 is not set |
| 7889 | +# CONFIG_TOSHIBA_JMR3927 is not set |
| 7890 | +# CONFIG_TOSHIBA_RBTX4927 is not set |
| 7891 | +# CONFIG_VICTOR_MPC30X is not set |
| 7892 | +# CONFIG_ZAO_CAPCELLA is not set |
| 7893 | +# CONFIG_HIGHMEM is not set |
| 7894 | +CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 7895 | +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 7896 | +CONFIG_SOC_AU1X00=y |
| 7897 | +CONFIG_SOC_AU1200=y |
| 7898 | +CONFIG_NONCOHERENT_IO=y |
| 7899 | +CONFIG_PC_KEYB=y |
| 7900 | +# CONFIG_MIPS_AU1000 is not set |
| 7901 | + |
| 7902 | +# |
| 7903 | +# CPU selection |
| 7904 | +# |
| 7905 | +CONFIG_CPU_MIPS32=y |
| 7906 | +# CONFIG_CPU_MIPS64 is not set |
| 7907 | +# CONFIG_CPU_R3000 is not set |
| 7908 | +# CONFIG_CPU_TX39XX is not set |
| 7909 | +# CONFIG_CPU_VR41XX is not set |
| 7910 | +# CONFIG_CPU_R4300 is not set |
| 7911 | +# CONFIG_CPU_R4X00 is not set |
| 7912 | +# CONFIG_CPU_TX49XX is not set |
| 7913 | +# CONFIG_CPU_R5000 is not set |
| 7914 | +# CONFIG_CPU_R5432 is not set |
| 7915 | +# CONFIG_CPU_R6000 is not set |
| 7916 | +# CONFIG_CPU_NEVADA is not set |
| 7917 | +# CONFIG_CPU_R8000 is not set |
| 7918 | +# CONFIG_CPU_R10000 is not set |
| 7919 | +# CONFIG_CPU_RM7000 is not set |
| 7920 | +# CONFIG_CPU_RM9000 is not set |
| 7921 | +# CONFIG_CPU_SB1 is not set |
| 7922 | +CONFIG_PAGE_SIZE_4KB=y |
| 7923 | +# CONFIG_PAGE_SIZE_16KB is not set |
| 7924 | +# CONFIG_PAGE_SIZE_64KB is not set |
| 7925 | +CONFIG_CPU_HAS_PREFETCH=y |
| 7926 | +# CONFIG_VTAG_ICACHE is not set |
| 7927 | +CONFIG_64BIT_PHYS_ADDR=y |
| 7928 | +# CONFIG_CPU_ADVANCED is not set |
| 7929 | +CONFIG_CPU_HAS_LLSC=y |
| 7930 | +# CONFIG_CPU_HAS_LLDSCD is not set |
| 7931 | +# CONFIG_CPU_HAS_WB is not set |
| 7932 | +CONFIG_CPU_HAS_SYNC=y |
| 7933 | + |
| 7934 | +# |
| 7935 | +# General setup |
| 7936 | +# |
| 7937 | +CONFIG_CPU_LITTLE_ENDIAN=y |
| 7938 | +# CONFIG_BUILD_ELF64 is not set |
| 7939 | +CONFIG_NET=y |
| 7940 | +CONFIG_PCI=y |
| 7941 | +CONFIG_PCI_NEW=y |
| 7942 | +CONFIG_PCI_AUTO=y |
| 7943 | +# CONFIG_PCI_NAMES is not set |
| 7944 | +# CONFIG_ISA is not set |
| 7945 | +# CONFIG_TC is not set |
| 7946 | +# CONFIG_MCA is not set |
| 7947 | +# CONFIG_SBUS is not set |
| 7948 | +CONFIG_HOTPLUG=y |
| 7949 | + |
| 7950 | +# |
| 7951 | +# PCMCIA/CardBus support |
| 7952 | +# |
| 7953 | +CONFIG_PCMCIA=m |
| 7954 | +# CONFIG_CARDBUS is not set |
| 7955 | +# CONFIG_TCIC is not set |
| 7956 | +# CONFIG_I82092 is not set |
| 7957 | +# CONFIG_I82365 is not set |
| 7958 | +CONFIG_PCMCIA_AU1X00=m |
| 7959 | + |
| 7960 | +# |
| 7961 | +# PCI Hotplug Support |
| 7962 | +# |
| 7963 | +# CONFIG_HOTPLUG_PCI is not set |
| 7964 | +# CONFIG_HOTPLUG_PCI_COMPAQ is not set |
| 7965 | +# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set |
| 7966 | +# CONFIG_HOTPLUG_PCI_SHPC is not set |
| 7967 | +# CONFIG_HOTPLUG_PCI_SHPC_POLL_EVENT_MODE is not set |
| 7968 | +# CONFIG_HOTPLUG_PCI_PCIE is not set |
| 7969 | +# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set |
| 7970 | +CONFIG_SYSVIPC=y |
| 7971 | +# CONFIG_BSD_PROCESS_ACCT is not set |
| 7972 | +CONFIG_SYSCTL=y |
| 7973 | +CONFIG_KCORE_ELF=y |
| 7974 | +# CONFIG_KCORE_AOUT is not set |
| 7975 | +# CONFIG_BINFMT_AOUT is not set |
| 7976 | +CONFIG_BINFMT_ELF=y |
| 7977 | +# CONFIG_MIPS32_COMPAT is not set |
| 7978 | +# CONFIG_MIPS32_O32 is not set |
| 7979 | +# CONFIG_MIPS32_N32 is not set |
| 7980 | +# CONFIG_BINFMT_ELF32 is not set |
| 7981 | +# CONFIG_BINFMT_MISC is not set |
| 7982 | +# CONFIG_OOM_KILLER is not set |
| 7983 | +CONFIG_CMDLINE_BOOL=y |
| 7984 | +CONFIG_CMDLINE="mem=96M" |
| 7985 | +# CONFIG_PM is not set |
| 7986 | + |
| 7987 | +# |
| 7988 | +# Memory Technology Devices (MTD) |
| 7989 | +# |
| 7990 | +# CONFIG_MTD is not set |
| 7991 | + |
| 7992 | +# |
| 7993 | +# Parallel port support |
| 7994 | +# |
| 7995 | +# CONFIG_PARPORT is not set |
| 7996 | + |
| 7997 | +# |
| 7998 | +# Plug and Play configuration |
| 7999 | +# |
| 8000 | +# CONFIG_PNP is not set |
| 8001 | +# CONFIG_ISAPNP is not set |
| 8002 | + |
| 8003 | +# |
| 8004 | +# Block devices |
| 8005 | +# |
| 8006 | +# CONFIG_BLK_DEV_FD is not set |
| 8007 | +# CONFIG_BLK_DEV_XD is not set |
| 8008 | +# CONFIG_PARIDE is not set |
| 8009 | +# CONFIG_BLK_CPQ_DA is not set |
| 8010 | +# CONFIG_BLK_CPQ_CISS_DA is not set |
| 8011 | +# CONFIG_CISS_SCSI_TAPE is not set |
| 8012 | +# CONFIG_CISS_MONITOR_THREAD is not set |
| 8013 | +# CONFIG_BLK_DEV_DAC960 is not set |
| 8014 | +# CONFIG_BLK_DEV_UMEM is not set |
| 8015 | +# CONFIG_BLK_DEV_SX8 is not set |
| 8016 | +CONFIG_BLK_DEV_LOOP=y |
| 8017 | +# CONFIG_BLK_DEV_NBD is not set |
| 8018 | +# CONFIG_BLK_DEV_RAM is not set |
| 8019 | +# CONFIG_BLK_DEV_INITRD is not set |
| 8020 | +# CONFIG_BLK_STATS is not set |
| 8021 | + |
| 8022 | +# |
| 8023 | +# Multi-device support (RAID and LVM) |
| 8024 | +# |
| 8025 | +# CONFIG_MD is not set |
| 8026 | +# CONFIG_BLK_DEV_MD is not set |
| 8027 | +# CONFIG_MD_LINEAR is not set |
| 8028 | +# CONFIG_MD_RAID0 is not set |
| 8029 | +# CONFIG_MD_RAID1 is not set |
| 8030 | +# CONFIG_MD_RAID5 is not set |
| 8031 | +# CONFIG_MD_MULTIPATH is not set |
| 8032 | +# CONFIG_BLK_DEV_LVM is not set |
| 8033 | + |
| 8034 | +# |
| 8035 | +# Networking options |
| 8036 | +# |
| 8037 | +CONFIG_PACKET=y |
| 8038 | +# CONFIG_PACKET_MMAP is not set |
| 8039 | +# CONFIG_NETLINK_DEV is not set |
| 8040 | +CONFIG_NETFILTER=y |
| 8041 | +# CONFIG_NETFILTER_DEBUG is not set |
| 8042 | +CONFIG_FILTER=y |
| 8043 | +CONFIG_UNIX=y |
| 8044 | +CONFIG_INET=y |
| 8045 | +CONFIG_IP_MULTICAST=y |
| 8046 | +# CONFIG_IP_ADVANCED_ROUTER is not set |
| 8047 | +CONFIG_IP_PNP=y |
| 8048 | +# CONFIG_IP_PNP_DHCP is not set |
| 8049 | +CONFIG_IP_PNP_BOOTP=y |
| 8050 | +# CONFIG_IP_PNP_RARP is not set |
| 8051 | +# CONFIG_NET_IPIP is not set |
| 8052 | +# CONFIG_NET_IPGRE is not set |
| 8053 | +# CONFIG_IP_MROUTE is not set |
| 8054 | +# CONFIG_ARPD is not set |
| 8055 | +# CONFIG_INET_ECN is not set |
| 8056 | +# CONFIG_SYN_COOKIES is not set |
| 8057 | + |
| 8058 | +# |
| 8059 | +# IP: Netfilter Configuration |
| 8060 | +# |
| 8061 | +# CONFIG_IP_NF_CONNTRACK is not set |
| 8062 | +# CONFIG_IP_NF_QUEUE is not set |
| 8063 | +# CONFIG_IP_NF_IPTABLES is not set |
| 8064 | +# CONFIG_IP_NF_ARPTABLES is not set |
| 8065 | +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set |
| 8066 | +# CONFIG_IP_NF_COMPAT_IPFWADM is not set |
| 8067 | + |
| 8068 | +# |
| 8069 | +# IP: Virtual Server Configuration |
| 8070 | +# |
| 8071 | +# CONFIG_IP_VS is not set |
| 8072 | +# CONFIG_IPV6 is not set |
| 8073 | +# CONFIG_KHTTPD is not set |
| 8074 | + |
| 8075 | +# |
| 8076 | +# SCTP Configuration (EXPERIMENTAL) |
| 8077 | +# |
| 8078 | +# CONFIG_IP_SCTP is not set |
| 8079 | +# CONFIG_ATM is not set |
| 8080 | +# CONFIG_VLAN_8021Q is not set |
| 8081 | + |
| 8082 | +# |
| 8083 | +# |
| 8084 | +# |
| 8085 | +# CONFIG_IPX is not set |
| 8086 | +# CONFIG_ATALK is not set |
| 8087 | +# CONFIG_DECNET is not set |
| 8088 | +# CONFIG_BRIDGE is not set |
| 8089 | +# CONFIG_X25 is not set |
| 8090 | +# CONFIG_LAPB is not set |
| 8091 | +# CONFIG_LLC is not set |
| 8092 | +# CONFIG_NET_DIVERT is not set |
| 8093 | +# CONFIG_ECONET is not set |
| 8094 | +# CONFIG_WAN_ROUTER is not set |
| 8095 | +# CONFIG_NET_FASTROUTE is not set |
| 8096 | +# CONFIG_NET_HW_FLOWCONTROL is not set |
| 8097 | + |
| 8098 | +# |
| 8099 | +# QoS and/or fair queueing |
| 8100 | +# |
| 8101 | +# CONFIG_NET_SCHED is not set |
| 8102 | + |
| 8103 | +# |
| 8104 | +# Network testing |
| 8105 | +# |
| 8106 | +# CONFIG_NET_PKTGEN is not set |
| 8107 | + |
| 8108 | +# |
| 8109 | +# Telephony Support |
| 8110 | +# |
| 8111 | +# CONFIG_PHONE is not set |
| 8112 | +# CONFIG_PHONE_IXJ is not set |
| 8113 | +# CONFIG_PHONE_IXJ_PCMCIA is not set |
| 8114 | + |
| 8115 | +# |
| 8116 | +# ATA/IDE/MFM/RLL support |
| 8117 | +# |
| 8118 | +CONFIG_IDE=y |
| 8119 | + |
| 8120 | +# |
| 8121 | +# IDE, ATA and ATAPI Block devices |
| 8122 | +# |
| 8123 | +CONFIG_BLK_DEV_IDE=y |
| 8124 | + |
| 8125 | +# |
| 8126 | +# Please see Documentation/ide.txt for help/info on IDE drives |
| 8127 | +# |
| 8128 | +# CONFIG_BLK_DEV_HD_IDE is not set |
| 8129 | +# CONFIG_BLK_DEV_HD is not set |
| 8130 | +# CONFIG_BLK_DEV_IDE_SATA is not set |
| 8131 | +CONFIG_BLK_DEV_IDEDISK=y |
| 8132 | +CONFIG_IDEDISK_MULTI_MODE=y |
| 8133 | +CONFIG_IDEDISK_STROKE=y |
| 8134 | +CONFIG_BLK_DEV_IDECS=m |
| 8135 | +# CONFIG_BLK_DEV_DELKIN is not set |
| 8136 | +# CONFIG_BLK_DEV_IDECD is not set |
| 8137 | +# CONFIG_BLK_DEV_IDETAPE is not set |
| 8138 | +# CONFIG_BLK_DEV_IDEFLOPPY is not set |
| 8139 | +# CONFIG_BLK_DEV_IDESCSI is not set |
| 8140 | +# CONFIG_IDE_TASK_IOCTL is not set |
| 8141 | + |
| 8142 | +# |
| 8143 | +# IDE chipset support/bugfixes |
| 8144 | +# |
| 8145 | +# CONFIG_BLK_DEV_CMD640 is not set |
| 8146 | +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set |
| 8147 | +# CONFIG_BLK_DEV_ISAPNP is not set |
| 8148 | +# CONFIG_BLK_DEV_IDEPCI is not set |
| 8149 | +# CONFIG_IDE_CHIPSETS is not set |
| 8150 | +# CONFIG_IDEDMA_AUTO is not set |
| 8151 | +# CONFIG_DMA_NONPCI is not set |
| 8152 | +# CONFIG_BLK_DEV_ATARAID is not set |
| 8153 | +# CONFIG_BLK_DEV_ATARAID_PDC is not set |
| 8154 | +# CONFIG_BLK_DEV_ATARAID_HPT is not set |
| 8155 | +# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set |
| 8156 | +# CONFIG_BLK_DEV_ATARAID_SII is not set |
| 8157 | + |
| 8158 | +# |
| 8159 | +# SCSI support |
| 8160 | +# |
| 8161 | +CONFIG_SCSI=y |
| 8162 | + |
| 8163 | +# |
| 8164 | +# SCSI support type (disk, tape, CD-ROM) |
| 8165 | +# |
| 8166 | +CONFIG_BLK_DEV_SD=y |
| 8167 | +CONFIG_SD_EXTRA_DEVS=40 |
| 8168 | +CONFIG_CHR_DEV_ST=y |
| 8169 | +# CONFIG_CHR_DEV_OSST is not set |
| 8170 | +CONFIG_BLK_DEV_SR=y |
| 8171 | +# CONFIG_BLK_DEV_SR_VENDOR is not set |
| 8172 | +CONFIG_SR_EXTRA_DEVS=2 |
| 8173 | +# CONFIG_CHR_DEV_SG is not set |
| 8174 | + |
| 8175 | +# |
| 8176 | +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs |
| 8177 | +# |
| 8178 | +# CONFIG_SCSI_DEBUG_QUEUES is not set |
| 8179 | +# CONFIG_SCSI_MULTI_LUN is not set |
| 8180 | +CONFIG_SCSI_CONSTANTS=y |
| 8181 | +# CONFIG_SCSI_LOGGING is not set |
| 8182 | + |
| 8183 | +# |
| 8184 | +# SCSI low-level drivers |
| 8185 | +# |
| 8186 | +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 8187 | +# CONFIG_SCSI_7000FASST is not set |
| 8188 | +# CONFIG_SCSI_ACARD is not set |
| 8189 | +# CONFIG_SCSI_AHA152X is not set |
| 8190 | +# CONFIG_SCSI_AHA1542 is not set |
| 8191 | +# CONFIG_SCSI_AHA1740 is not set |
| 8192 | +# CONFIG_SCSI_AACRAID is not set |
| 8193 | +# CONFIG_SCSI_AIC7XXX is not set |
| 8194 | +# CONFIG_SCSI_AIC79XX is not set |
| 8195 | +# CONFIG_SCSI_AIC7XXX_OLD is not set |
| 8196 | +# CONFIG_SCSI_DPT_I2O is not set |
| 8197 | +# CONFIG_SCSI_ADVANSYS is not set |
| 8198 | +# CONFIG_SCSI_IN2000 is not set |
| 8199 | +# CONFIG_SCSI_AM53C974 is not set |
| 8200 | +# CONFIG_SCSI_MEGARAID is not set |
| 8201 | +# CONFIG_SCSI_MEGARAID2 is not set |
| 8202 | +# CONFIG_SCSI_SATA is not set |
| 8203 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 8204 | +# CONFIG_SCSI_SATA_SVW is not set |
| 8205 | +# CONFIG_SCSI_ATA_PIIX is not set |
| 8206 | +# CONFIG_SCSI_SATA_NV is not set |
| 8207 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 8208 | +# CONFIG_SCSI_SATA_PROMISE is not set |
| 8209 | +# CONFIG_SCSI_SATA_SX4 is not set |
| 8210 | +# CONFIG_SCSI_SATA_SIL is not set |
| 8211 | +# CONFIG_SCSI_SATA_SIS is not set |
| 8212 | +# CONFIG_SCSI_SATA_ULI is not set |
| 8213 | +# CONFIG_SCSI_SATA_VIA is not set |
| 8214 | +# CONFIG_SCSI_SATA_VITESSE is not set |
| 8215 | +# CONFIG_SCSI_BUSLOGIC is not set |
| 8216 | +# CONFIG_SCSI_CPQFCTS is not set |
| 8217 | +# CONFIG_SCSI_DMX3191D is not set |
| 8218 | +# CONFIG_SCSI_DTC3280 is not set |
| 8219 | +# CONFIG_SCSI_EATA is not set |
| 8220 | +# CONFIG_SCSI_EATA_DMA is not set |
| 8221 | +# CONFIG_SCSI_EATA_PIO is not set |
| 8222 | +# CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 8223 | +# CONFIG_SCSI_GDTH is not set |
| 8224 | +# CONFIG_SCSI_GENERIC_NCR5380 is not set |
| 8225 | +# CONFIG_SCSI_INITIO is not set |
| 8226 | +# CONFIG_SCSI_INIA100 is not set |
| 8227 | +# CONFIG_SCSI_NCR53C406A is not set |
| 8228 | +# CONFIG_SCSI_NCR53C7xx is not set |
| 8229 | +# CONFIG_SCSI_SYM53C8XX_2 is not set |
| 8230 | +# CONFIG_SCSI_NCR53C8XX is not set |
| 8231 | +# CONFIG_SCSI_SYM53C8XX is not set |
| 8232 | +# CONFIG_SCSI_PAS16 is not set |
| 8233 | +# CONFIG_SCSI_PCI2000 is not set |
| 8234 | +# CONFIG_SCSI_PCI2220I is not set |
| 8235 | +# CONFIG_SCSI_PSI240I is not set |
| 8236 | +# CONFIG_SCSI_QLOGIC_FAS is not set |
| 8237 | +# CONFIG_SCSI_QLOGIC_ISP is not set |
| 8238 | +# CONFIG_SCSI_QLOGIC_FC is not set |
| 8239 | +# CONFIG_SCSI_QLOGIC_1280 is not set |
| 8240 | +# CONFIG_SCSI_SIM710 is not set |
| 8241 | +# CONFIG_SCSI_SYM53C416 is not set |
| 8242 | +# CONFIG_SCSI_DC390T is not set |
| 8243 | +# CONFIG_SCSI_T128 is not set |
| 8244 | +# CONFIG_SCSI_U14_34F is not set |
| 8245 | +# CONFIG_SCSI_NSP32 is not set |
| 8246 | +# CONFIG_SCSI_DEBUG is not set |
| 8247 | + |
| 8248 | +# |
| 8249 | +# PCMCIA SCSI adapter support |
| 8250 | +# |
| 8251 | +# CONFIG_SCSI_PCMCIA is not set |
| 8252 | + |
| 8253 | +# |
| 8254 | +# Fusion MPT device support |
| 8255 | +# |
| 8256 | +# CONFIG_FUSION is not set |
| 8257 | +# CONFIG_FUSION_BOOT is not set |
| 8258 | +# CONFIG_FUSION_ISENSE is not set |
| 8259 | +# CONFIG_FUSION_CTL is not set |
| 8260 | +# CONFIG_FUSION_LAN is not set |
| 8261 | + |
| 8262 | +# |
| 8263 | +# IEEE 1394 (FireWire) support (EXPERIMENTAL) |
| 8264 | +# |
| 8265 | +# CONFIG_IEEE1394 is not set |
| 8266 | + |
| 8267 | +# |
| 8268 | +# I2O device support |
| 8269 | +# |
| 8270 | +# CONFIG_I2O is not set |
| 8271 | +# CONFIG_I2O_PCI is not set |
| 8272 | +# CONFIG_I2O_BLOCK is not set |
| 8273 | +# CONFIG_I2O_LAN is not set |
| 8274 | +# CONFIG_I2O_SCSI is not set |
| 8275 | +# CONFIG_I2O_PROC is not set |
| 8276 | + |
| 8277 | +# |
| 8278 | +# Network device support |
| 8279 | +# |
| 8280 | +CONFIG_NETDEVICES=y |
| 8281 | + |
| 8282 | +# |
| 8283 | +# ARCnet devices |
| 8284 | +# |
| 8285 | +# CONFIG_ARCNET is not set |
| 8286 | +# CONFIG_DUMMY is not set |
| 8287 | +# CONFIG_BONDING is not set |
| 8288 | +# CONFIG_EQUALIZER is not set |
| 8289 | +# CONFIG_TUN is not set |
| 8290 | +# CONFIG_ETHERTAP is not set |
| 8291 | + |
| 8292 | +# |
| 8293 | +# Ethernet (10 or 100Mbit) |
| 8294 | +# |
| 8295 | +CONFIG_NET_ETHERNET=y |
| 8296 | +# CONFIG_MIPS_AU1X00_ENET is not set |
| 8297 | +# CONFIG_SUNLANCE is not set |
| 8298 | +# CONFIG_HAPPYMEAL is not set |
| 8299 | +# CONFIG_SUNBMAC is not set |
| 8300 | +# CONFIG_SUNQE is not set |
| 8301 | +# CONFIG_SUNGEM is not set |
| 8302 | +# CONFIG_NET_VENDOR_3COM is not set |
| 8303 | +# CONFIG_LANCE is not set |
| 8304 | +# CONFIG_NET_VENDOR_SMC is not set |
| 8305 | +# CONFIG_NET_VENDOR_RACAL is not set |
| 8306 | +# CONFIG_HP100 is not set |
| 8307 | +# CONFIG_NET_ISA is not set |
| 8308 | +# CONFIG_NET_PCI is not set |
| 8309 | +# CONFIG_NET_POCKET is not set |
| 8310 | + |
| 8311 | +# |
| 8312 | +# Ethernet (1000 Mbit) |
| 8313 | +# |
| 8314 | +# CONFIG_ACENIC is not set |
| 8315 | +# CONFIG_DL2K is not set |
| 8316 | +# CONFIG_E1000 is not set |
| 8317 | +# CONFIG_MYRI_SBUS is not set |
| 8318 | +# CONFIG_NS83820 is not set |
| 8319 | +# CONFIG_HAMACHI is not set |
| 8320 | +# CONFIG_YELLOWFIN is not set |
| 8321 | +# CONFIG_R8169 is not set |
| 8322 | +# CONFIG_SK98LIN is not set |
| 8323 | +# CONFIG_TIGON3 is not set |
| 8324 | +# CONFIG_FDDI is not set |
| 8325 | +# CONFIG_HIPPI is not set |
| 8326 | +# CONFIG_PLIP is not set |
| 8327 | +CONFIG_PPP=m |
| 8328 | +CONFIG_PPP_MULTILINK=y |
| 8329 | +# CONFIG_PPP_FILTER is not set |
| 8330 | +CONFIG_PPP_ASYNC=m |
| 8331 | +# CONFIG_PPP_SYNC_TTY is not set |
| 8332 | +CONFIG_PPP_DEFLATE=m |
| 8333 | +# CONFIG_PPP_BSDCOMP is not set |
| 8334 | +CONFIG_PPPOE=m |
| 8335 | +# CONFIG_SLIP is not set |
| 8336 | + |
| 8337 | +# |
| 8338 | +# Wireless LAN (non-hamradio) |
| 8339 | +# |
| 8340 | +# CONFIG_NET_RADIO is not set |
| 8341 | + |
| 8342 | +# |
| 8343 | +# Token Ring devices |
| 8344 | +# |
| 8345 | +# CONFIG_TR is not set |
| 8346 | +# CONFIG_NET_FC is not set |
| 8347 | +# CONFIG_RCPCI is not set |
| 8348 | +# CONFIG_SHAPER is not set |
| 8349 | + |
| 8350 | +# |
| 8351 | +# Wan interfaces |
| 8352 | +# |
| 8353 | +# CONFIG_WAN is not set |
| 8354 | + |
| 8355 | +# |
| 8356 | +# PCMCIA network device support |
| 8357 | +# |
| 8358 | +# CONFIG_NET_PCMCIA is not set |
| 8359 | + |
| 8360 | +# |
| 8361 | +# Amateur Radio support |
| 8362 | +# |
| 8363 | +# CONFIG_HAMRADIO is not set |
| 8364 | + |
| 8365 | +# |
| 8366 | +# IrDA (infrared) support |
| 8367 | +# |
| 8368 | +# CONFIG_IRDA is not set |
| 8369 | + |
| 8370 | +# |
| 8371 | +# ISDN subsystem |
| 8372 | +# |
| 8373 | +# CONFIG_ISDN is not set |
| 8374 | + |
| 8375 | +# |
| 8376 | +# Input core support |
| 8377 | +# |
| 8378 | +CONFIG_INPUT=y |
| 8379 | +CONFIG_INPUT_KEYBDEV=y |
| 8380 | +CONFIG_INPUT_MOUSEDEV=y |
| 8381 | +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 8382 | +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 8383 | +# CONFIG_INPUT_JOYDEV is not set |
| 8384 | +CONFIG_INPUT_EVDEV=y |
| 8385 | +# CONFIG_INPUT_UINPUT is not set |
| 8386 | + |
| 8387 | +# |
| 8388 | +# Character devices |
| 8389 | +# |
| 8390 | +CONFIG_VT=y |
| 8391 | +# CONFIG_VT_CONSOLE is not set |
| 8392 | +# CONFIG_SERIAL is not set |
| 8393 | +# CONFIG_SERIAL_EXTENDED is not set |
| 8394 | +CONFIG_SERIAL_NONSTANDARD=y |
| 8395 | +# CONFIG_COMPUTONE is not set |
| 8396 | +# CONFIG_ROCKETPORT is not set |
| 8397 | +# CONFIG_CYCLADES is not set |
| 8398 | +# CONFIG_DIGIEPCA is not set |
| 8399 | +# CONFIG_DIGI is not set |
| 8400 | +# CONFIG_ESPSERIAL is not set |
| 8401 | +# CONFIG_MOXA_INTELLIO is not set |
| 8402 | +# CONFIG_MOXA_SMARTIO is not set |
| 8403 | +# CONFIG_ISI is not set |
| 8404 | +# CONFIG_SYNCLINK is not set |
| 8405 | +# CONFIG_SYNCLINKMP is not set |
| 8406 | +# CONFIG_N_HDLC is not set |
| 8407 | +# CONFIG_RISCOM8 is not set |
| 8408 | +# CONFIG_SPECIALIX is not set |
| 8409 | +# CONFIG_SX is not set |
| 8410 | +# CONFIG_RIO is not set |
| 8411 | +# CONFIG_STALDRV is not set |
| 8412 | +# CONFIG_SERIAL_TX3912 is not set |
| 8413 | +# CONFIG_SERIAL_TX3912_CONSOLE is not set |
| 8414 | +# CONFIG_SERIAL_TXX9 is not set |
| 8415 | +# CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 8416 | +CONFIG_AU1X00_UART=y |
| 8417 | +CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 8418 | +# CONFIG_AU1X00_USB_TTY is not set |
| 8419 | +# CONFIG_AU1X00_USB_RAW is not set |
| 8420 | +# CONFIG_TXX927_SERIAL is not set |
| 8421 | +CONFIG_UNIX98_PTYS=y |
| 8422 | +CONFIG_UNIX98_PTY_COUNT=256 |
| 8423 | + |
| 8424 | +# |
| 8425 | +# I2C support |
| 8426 | +# |
| 8427 | +CONFIG_I2C=y |
| 8428 | +# CONFIG_I2C_ALGOBIT is not set |
| 8429 | +# CONFIG_SCx200_ACB is not set |
| 8430 | +# CONFIG_I2C_ALGOPCF is not set |
| 8431 | +# CONFIG_I2C_CHARDEV is not set |
| 8432 | +CONFIG_I2C_PROC=y |
| 8433 | + |
| 8434 | +# |
| 8435 | +# Mice |
| 8436 | +# |
| 8437 | +# CONFIG_BUSMOUSE is not set |
| 8438 | +# CONFIG_MOUSE is not set |
| 8439 | + |
| 8440 | +# |
| 8441 | +# Joysticks |
| 8442 | +# |
| 8443 | +# CONFIG_INPUT_GAMEPORT is not set |
| 8444 | +# CONFIG_INPUT_NS558 is not set |
| 8445 | +# CONFIG_INPUT_LIGHTNING is not set |
| 8446 | +# CONFIG_INPUT_PCIGAME is not set |
| 8447 | +# CONFIG_INPUT_CS461X is not set |
| 8448 | +# CONFIG_INPUT_EMU10K1 is not set |
| 8449 | +# CONFIG_INPUT_SERIO is not set |
| 8450 | +# CONFIG_INPUT_SERPORT is not set |
| 8451 | + |
| 8452 | +# |
| 8453 | +# Joysticks |
| 8454 | +# |
| 8455 | +# CONFIG_INPUT_ANALOG is not set |
| 8456 | +# CONFIG_INPUT_A3D is not set |
| 8457 | +# CONFIG_INPUT_ADI is not set |
| 8458 | +# CONFIG_INPUT_COBRA is not set |
| 8459 | +# CONFIG_INPUT_GF2K is not set |
| 8460 | +# CONFIG_INPUT_GRIP is not set |
| 8461 | +# CONFIG_INPUT_INTERACT is not set |
| 8462 | +# CONFIG_INPUT_TMDC is not set |
| 8463 | +# CONFIG_INPUT_SIDEWINDER is not set |
| 8464 | +# CONFIG_INPUT_IFORCE_USB is not set |
| 8465 | +# CONFIG_INPUT_IFORCE_232 is not set |
| 8466 | +# CONFIG_INPUT_WARRIOR is not set |
| 8467 | +# CONFIG_INPUT_MAGELLAN is not set |
| 8468 | +# CONFIG_INPUT_SPACEORB is not set |
| 8469 | +# CONFIG_INPUT_SPACEBALL is not set |
| 8470 | +# CONFIG_INPUT_STINGER is not set |
| 8471 | +# CONFIG_INPUT_DB9 is not set |
| 8472 | +# CONFIG_INPUT_GAMECON is not set |
| 8473 | +# CONFIG_INPUT_TURBOGRAFX is not set |
| 8474 | +# CONFIG_QIC02_TAPE is not set |
| 8475 | +# CONFIG_IPMI_HANDLER is not set |
| 8476 | +# CONFIG_IPMI_PANIC_EVENT is not set |
| 8477 | +# CONFIG_IPMI_DEVICE_INTERFACE is not set |
| 8478 | +# CONFIG_IPMI_KCS is not set |
| 8479 | +# CONFIG_IPMI_WATCHDOG is not set |
| 8480 | + |
| 8481 | +# |
| 8482 | +# Watchdog Cards |
| 8483 | +# |
| 8484 | +# CONFIG_WATCHDOG is not set |
| 8485 | +# CONFIG_SCx200 is not set |
| 8486 | +# CONFIG_SCx200_GPIO is not set |
| 8487 | +# CONFIG_AMD_PM768 is not set |
| 8488 | +# CONFIG_NVRAM is not set |
| 8489 | +# CONFIG_RTC is not set |
| 8490 | +# CONFIG_DTLK is not set |
| 8491 | +# CONFIG_R3964 is not set |
| 8492 | +# CONFIG_APPLICOM is not set |
| 8493 | + |
| 8494 | +# |
| 8495 | +# Ftape, the floppy tape device driver |
| 8496 | +# |
| 8497 | +# CONFIG_FTAPE is not set |
| 8498 | +# CONFIG_AGP is not set |
| 8499 | + |
| 8500 | +# |
| 8501 | +# Direct Rendering Manager (XFree86 DRI support) |
| 8502 | +# |
| 8503 | +# CONFIG_DRM is not set |
| 8504 | + |
| 8505 | +# |
| 8506 | +# PCMCIA character devices |
| 8507 | +# |
| 8508 | +# CONFIG_PCMCIA_SERIAL_CS is not set |
| 8509 | +# CONFIG_SYNCLINK_CS is not set |
| 8510 | +# CONFIG_AU1X00_GPIO is not set |
| 8511 | +# CONFIG_TS_AU1X00_ADS7846 is not set |
| 8512 | + |
| 8513 | +# |
| 8514 | +# File systems |
| 8515 | +# |
| 8516 | +# CONFIG_QUOTA is not set |
| 8517 | +# CONFIG_QFMT_V2 is not set |
| 8518 | +CONFIG_AUTOFS_FS=y |
| 8519 | +# CONFIG_AUTOFS4_FS is not set |
| 8520 | +# CONFIG_REISERFS_FS is not set |
| 8521 | +# CONFIG_REISERFS_CHECK is not set |
| 8522 | +# CONFIG_REISERFS_PROC_INFO is not set |
| 8523 | +# CONFIG_ADFS_FS is not set |
| 8524 | +# CONFIG_ADFS_FS_RW is not set |
| 8525 | +# CONFIG_AFFS_FS is not set |
| 8526 | +# CONFIG_HFS_FS is not set |
| 8527 | +# CONFIG_HFSPLUS_FS is not set |
| 8528 | +# CONFIG_BEFS_FS is not set |
| 8529 | +# CONFIG_BEFS_DEBUG is not set |
| 8530 | +# CONFIG_BFS_FS is not set |
| 8531 | +CONFIG_EXT3_FS=y |
| 8532 | +CONFIG_JBD=y |
| 8533 | +# CONFIG_JBD_DEBUG is not set |
| 8534 | +CONFIG_FAT_FS=y |
| 8535 | +CONFIG_MSDOS_FS=y |
| 8536 | +# CONFIG_UMSDOS_FS is not set |
| 8537 | +CONFIG_VFAT_FS=y |
| 8538 | +# CONFIG_EFS_FS is not set |
| 8539 | +# CONFIG_JFFS_FS is not set |
| 8540 | +# CONFIG_JFFS2_FS is not set |
| 8541 | +# CONFIG_CRAMFS is not set |
| 8542 | +CONFIG_TMPFS=y |
| 8543 | +CONFIG_RAMFS=y |
| 8544 | +# CONFIG_ISO9660_FS is not set |
| 8545 | +# CONFIG_JOLIET is not set |
| 8546 | +# CONFIG_ZISOFS is not set |
| 8547 | +# CONFIG_JFS_FS is not set |
| 8548 | +# CONFIG_JFS_DEBUG is not set |
| 8549 | +# CONFIG_JFS_STATISTICS is not set |
| 8550 | +# CONFIG_MINIX_FS is not set |
| 8551 | +# CONFIG_VXFS_FS is not set |
| 8552 | +# CONFIG_NTFS_FS is not set |
| 8553 | +# CONFIG_NTFS_RW is not set |
| 8554 | +# CONFIG_HPFS_FS is not set |
| 8555 | +CONFIG_PROC_FS=y |
| 8556 | +# CONFIG_DEVFS_FS is not set |
| 8557 | +# CONFIG_DEVFS_MOUNT is not set |
| 8558 | +# CONFIG_DEVFS_DEBUG is not set |
| 8559 | +CONFIG_DEVPTS_FS=y |
| 8560 | +# CONFIG_QNX4FS_FS is not set |
| 8561 | +# CONFIG_QNX4FS_RW is not set |
| 8562 | +# CONFIG_ROMFS_FS is not set |
| 8563 | +CONFIG_EXT2_FS=y |
| 8564 | +# CONFIG_SYSV_FS is not set |
| 8565 | +# CONFIG_UDF_FS is not set |
| 8566 | +# CONFIG_UDF_RW is not set |
| 8567 | +# CONFIG_UFS_FS is not set |
| 8568 | +# CONFIG_UFS_FS_WRITE is not set |
| 8569 | +# CONFIG_XFS_FS is not set |
| 8570 | +# CONFIG_XFS_QUOTA is not set |
| 8571 | +# CONFIG_XFS_RT is not set |
| 8572 | +# CONFIG_XFS_TRACE is not set |
| 8573 | +# CONFIG_XFS_DEBUG is not set |
| 8574 | + |
| 8575 | +# |
| 8576 | +# Network File Systems |
| 8577 | +# |
| 8578 | +# CONFIG_CODA_FS is not set |
| 8579 | +# CONFIG_INTERMEZZO_FS is not set |
| 8580 | +CONFIG_NFS_FS=y |
| 8581 | +CONFIG_NFS_V3=y |
| 8582 | +# CONFIG_NFS_DIRECTIO is not set |
| 8583 | +CONFIG_ROOT_NFS=y |
| 8584 | +# CONFIG_NFSD is not set |
| 8585 | +# CONFIG_NFSD_V3 is not set |
| 8586 | +# CONFIG_NFSD_TCP is not set |
| 8587 | +CONFIG_SUNRPC=y |
| 8588 | +CONFIG_LOCKD=y |
| 8589 | +CONFIG_LOCKD_V4=y |
| 8590 | +# CONFIG_SMB_FS is not set |
| 8591 | +# CONFIG_NCP_FS is not set |
| 8592 | +# CONFIG_NCPFS_PACKET_SIGNING is not set |
| 8593 | +# CONFIG_NCPFS_IOCTL_LOCKING is not set |
| 8594 | +# CONFIG_NCPFS_STRONG is not set |
| 8595 | +# CONFIG_NCPFS_NFS_NS is not set |
| 8596 | +# CONFIG_NCPFS_OS2_NS is not set |
| 8597 | +# CONFIG_NCPFS_SMALLDOS is not set |
| 8598 | +# CONFIG_NCPFS_NLS is not set |
| 8599 | +# CONFIG_NCPFS_EXTRAS is not set |
| 8600 | +# CONFIG_ZISOFS_FS is not set |
| 8601 | + |
| 8602 | +# |
| 8603 | +# Partition Types |
| 8604 | +# |
| 8605 | +# CONFIG_PARTITION_ADVANCED is not set |
| 8606 | +CONFIG_MSDOS_PARTITION=y |
| 8607 | +# CONFIG_SMB_NLS is not set |
| 8608 | +CONFIG_NLS=y |
| 8609 | + |
| 8610 | +# |
| 8611 | +# Native Language Support |
| 8612 | +# |
| 8613 | +CONFIG_NLS_DEFAULT="iso8859-1" |
| 8614 | +# CONFIG_NLS_CODEPAGE_437 is not set |
| 8615 | +# CONFIG_NLS_CODEPAGE_737 is not set |
| 8616 | +# CONFIG_NLS_CODEPAGE_775 is not set |
| 8617 | +# CONFIG_NLS_CODEPAGE_850 is not set |
| 8618 | +# CONFIG_NLS_CODEPAGE_852 is not set |
| 8619 | +# CONFIG_NLS_CODEPAGE_855 is not set |
| 8620 | +# CONFIG_NLS_CODEPAGE_857 is not set |
| 8621 | +# CONFIG_NLS_CODEPAGE_860 is not set |
| 8622 | +# CONFIG_NLS_CODEPAGE_861 is not set |
| 8623 | +# CONFIG_NLS_CODEPAGE_862 is not set |
| 8624 | +# CONFIG_NLS_CODEPAGE_863 is not set |
| 8625 | +# CONFIG_NLS_CODEPAGE_864 is not set |
| 8626 | +# CONFIG_NLS_CODEPAGE_865 is not set |
| 8627 | +# CONFIG_NLS_CODEPAGE_866 is not set |
| 8628 | +# CONFIG_NLS_CODEPAGE_869 is not set |
| 8629 | +# CONFIG_NLS_CODEPAGE_936 is not set |
| 8630 | +# CONFIG_NLS_CODEPAGE_950 is not set |
| 8631 | +# CONFIG_NLS_CODEPAGE_932 is not set |
| 8632 | +# CONFIG_NLS_CODEPAGE_949 is not set |
| 8633 | +# CONFIG_NLS_CODEPAGE_874 is not set |
| 8634 | +# CONFIG_NLS_ISO8859_8 is not set |
| 8635 | +# CONFIG_NLS_CODEPAGE_1250 is not set |
| 8636 | +# CONFIG_NLS_CODEPAGE_1251 is not set |
| 8637 | +# CONFIG_NLS_ISO8859_1 is not set |
| 8638 | +# CONFIG_NLS_ISO8859_2 is not set |
| 8639 | +# CONFIG_NLS_ISO8859_3 is not set |
| 8640 | +# CONFIG_NLS_ISO8859_4 is not set |
| 8641 | +# CONFIG_NLS_ISO8859_5 is not set |
| 8642 | +# CONFIG_NLS_ISO8859_6 is not set |
| 8643 | +# CONFIG_NLS_ISO8859_7 is not set |
| 8644 | +# CONFIG_NLS_ISO8859_9 is not set |
| 8645 | +# CONFIG_NLS_ISO8859_13 is not set |
| 8646 | +# CONFIG_NLS_ISO8859_14 is not set |
| 8647 | +# CONFIG_NLS_ISO8859_15 is not set |
| 8648 | +# CONFIG_NLS_KOI8_R is not set |
| 8649 | +# CONFIG_NLS_KOI8_U is not set |
| 8650 | +# CONFIG_NLS_UTF8 is not set |
| 8651 | + |
| 8652 | +# |
| 8653 | +# Multimedia devices |
| 8654 | +# |
| 8655 | +# CONFIG_VIDEO_DEV is not set |
| 8656 | + |
| 8657 | +# |
| 8658 | +# Console drivers |
| 8659 | +# |
| 8660 | +# CONFIG_VGA_CONSOLE is not set |
| 8661 | +# CONFIG_MDA_CONSOLE is not set |
| 8662 | + |
| 8663 | +# |
| 8664 | +# Frame-buffer support |
| 8665 | +# |
| 8666 | +CONFIG_FB=y |
| 8667 | +CONFIG_DUMMY_CONSOLE=y |
| 8668 | +# CONFIG_FB_RIVA is not set |
| 8669 | +# CONFIG_FB_CLGEN is not set |
| 8670 | +# CONFIG_FB_PM2 is not set |
| 8671 | +# CONFIG_FB_PM3 is not set |
| 8672 | +# CONFIG_FB_CYBER2000 is not set |
| 8673 | +# CONFIG_FB_MATROX is not set |
| 8674 | +# CONFIG_FB_ATY is not set |
| 8675 | +# CONFIG_FB_RADEON is not set |
| 8676 | +# CONFIG_FB_ATY128 is not set |
| 8677 | +# CONFIG_FB_INTEL is not set |
| 8678 | +# CONFIG_FB_SIS is not set |
| 8679 | +# CONFIG_FB_NEOMAGIC is not set |
| 8680 | +# CONFIG_FB_3DFX is not set |
| 8681 | +# CONFIG_FB_VOODOO1 is not set |
| 8682 | +# CONFIG_FB_TRIDENT is not set |
| 8683 | +# CONFIG_FB_E1356 is not set |
| 8684 | +# CONFIG_FB_IT8181 is not set |
| 8685 | +# CONFIG_FB_VIRTUAL is not set |
| 8686 | +CONFIG_FBCON_ADVANCED=y |
| 8687 | +# CONFIG_FBCON_MFB is not set |
| 8688 | +# CONFIG_FBCON_CFB2 is not set |
| 8689 | +# CONFIG_FBCON_CFB4 is not set |
| 8690 | +# CONFIG_FBCON_CFB8 is not set |
| 8691 | +CONFIG_FBCON_CFB16=y |
| 8692 | +# CONFIG_FBCON_CFB24 is not set |
| 8693 | +CONFIG_FBCON_CFB32=y |
| 8694 | +# CONFIG_FBCON_AFB is not set |
| 8695 | +# CONFIG_FBCON_ILBM is not set |
| 8696 | +# CONFIG_FBCON_IPLAN2P2 is not set |
| 8697 | +# CONFIG_FBCON_IPLAN2P4 is not set |
| 8698 | +# CONFIG_FBCON_IPLAN2P8 is not set |
| 8699 | +# CONFIG_FBCON_MAC is not set |
| 8700 | +# CONFIG_FBCON_VGA_PLANES is not set |
| 8701 | +# CONFIG_FBCON_VGA is not set |
| 8702 | +# CONFIG_FBCON_HGA is not set |
| 8703 | +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set |
| 8704 | +CONFIG_FBCON_FONTS=y |
| 8705 | +CONFIG_FONT_8x8=y |
| 8706 | +CONFIG_FONT_8x16=y |
| 8707 | +# CONFIG_FONT_SUN8x16 is not set |
| 8708 | +# CONFIG_FONT_SUN12x22 is not set |
| 8709 | +# CONFIG_FONT_6x11 is not set |
| 8710 | +# CONFIG_FONT_PEARL_8x8 is not set |
| 8711 | +# CONFIG_FONT_ACORN_8x8 is not set |
| 8712 | + |
| 8713 | +# |
| 8714 | +# Sound |
| 8715 | +# |
| 8716 | +CONFIG_SOUND=y |
| 8717 | +# CONFIG_SOUND_ALI5455 is not set |
| 8718 | +# CONFIG_SOUND_BT878 is not set |
| 8719 | +# CONFIG_SOUND_CMPCI is not set |
| 8720 | +# CONFIG_SOUND_EMU10K1 is not set |
| 8721 | +# CONFIG_MIDI_EMU10K1 is not set |
| 8722 | +# CONFIG_SOUND_FUSION is not set |
| 8723 | +# CONFIG_SOUND_CS4281 is not set |
| 8724 | +# CONFIG_SOUND_ES1370 is not set |
| 8725 | +# CONFIG_SOUND_ES1371 is not set |
| 8726 | +# CONFIG_SOUND_ESSSOLO1 is not set |
| 8727 | +# CONFIG_SOUND_MAESTRO is not set |
| 8728 | +# CONFIG_SOUND_MAESTRO3 is not set |
| 8729 | +# CONFIG_SOUND_FORTE is not set |
| 8730 | +# CONFIG_SOUND_ICH is not set |
| 8731 | +# CONFIG_SOUND_RME96XX is not set |
| 8732 | +# CONFIG_SOUND_SONICVIBES is not set |
| 8733 | +# CONFIG_SOUND_AU1X00 is not set |
| 8734 | +CONFIG_SOUND_AU1550_PSC=y |
| 8735 | +# CONFIG_SOUND_AU1550_I2S is not set |
| 8736 | +# CONFIG_SOUND_TRIDENT is not set |
| 8737 | +# CONFIG_SOUND_MSNDCLAS is not set |
| 8738 | +# CONFIG_SOUND_MSNDPIN is not set |
| 8739 | +# CONFIG_SOUND_VIA82CXXX is not set |
| 8740 | +# CONFIG_MIDI_VIA82CXXX is not set |
| 8741 | +# CONFIG_SOUND_OSS is not set |
| 8742 | +# CONFIG_SOUND_TVMIXER is not set |
| 8743 | +# CONFIG_SOUND_AD1980 is not set |
| 8744 | +# CONFIG_SOUND_WM97XX is not set |
| 8745 | + |
| 8746 | +# |
| 8747 | +# USB support |
| 8748 | +# |
| 8749 | +CONFIG_USB=y |
| 8750 | +# CONFIG_USB_DEBUG is not set |
| 8751 | + |
| 8752 | +# |
| 8753 | +# Miscellaneous USB options |
| 8754 | +# |
| 8755 | +CONFIG_USB_DEVICEFS=y |
| 8756 | +# CONFIG_USB_BANDWIDTH is not set |
| 8757 | + |
| 8758 | +# |
| 8759 | +# USB Host Controller Drivers |
| 8760 | +# |
| 8761 | +# CONFIG_USB_EHCI_HCD is not set |
| 8762 | +# CONFIG_USB_UHCI is not set |
| 8763 | +# CONFIG_USB_UHCI_ALT is not set |
| 8764 | +CONFIG_USB_OHCI=y |
| 8765 | + |
| 8766 | +# |
| 8767 | +# USB Device Class drivers |
| 8768 | +# |
| 8769 | +# CONFIG_USB_AUDIO is not set |
| 8770 | +# CONFIG_USB_EMI26 is not set |
| 8771 | +# CONFIG_USB_BLUETOOTH is not set |
| 8772 | +# CONFIG_USB_MIDI is not set |
| 8773 | +CONFIG_USB_STORAGE=y |
| 8774 | +# CONFIG_USB_STORAGE_DEBUG is not set |
| 8775 | +# CONFIG_USB_STORAGE_DATAFAB is not set |
| 8776 | +# CONFIG_USB_STORAGE_FREECOM is not set |
| 8777 | +# CONFIG_USB_STORAGE_ISD200 is not set |
| 8778 | +# CONFIG_USB_STORAGE_DPCM is not set |
| 8779 | +# CONFIG_USB_STORAGE_HP8200e is not set |
| 8780 | +# CONFIG_USB_STORAGE_SDDR09 is not set |
| 8781 | +# CONFIG_USB_STORAGE_SDDR55 is not set |
| 8782 | +# CONFIG_USB_STORAGE_JUMPSHOT is not set |
| 8783 | +# CONFIG_USB_ACM is not set |
| 8784 | +# CONFIG_USB_PRINTER is not set |
| 8785 | + |
| 8786 | +# |
| 8787 | +# USB Human Interface Devices (HID) |
| 8788 | +# |
| 8789 | +CONFIG_USB_HID=y |
| 8790 | +CONFIG_USB_HIDINPUT=y |
| 8791 | +CONFIG_USB_HIDDEV=y |
| 8792 | +# CONFIG_USB_AIPTEK is not set |
| 8793 | +# CONFIG_USB_WACOM is not set |
| 8794 | +# CONFIG_USB_KBTAB is not set |
| 8795 | +# CONFIG_USB_POWERMATE is not set |
| 8796 | + |
| 8797 | +# |
| 8798 | +# USB Imaging devices |
| 8799 | +# |
| 8800 | +# CONFIG_USB_DC2XX is not set |
| 8801 | +# CONFIG_USB_MDC800 is not set |
| 8802 | +# CONFIG_USB_SCANNER is not set |
| 8803 | +# CONFIG_USB_MICROTEK is not set |
| 8804 | +# CONFIG_USB_HPUSBSCSI is not set |
| 8805 | + |
| 8806 | +# |
| 8807 | +# USB Multimedia devices |
| 8808 | +# |
| 8809 | + |
| 8810 | +# |
| 8811 | +# Video4Linux support is needed for USB Multimedia device support |
| 8812 | +# |
| 8813 | + |
| 8814 | +# |
| 8815 | +# USB Network adaptors |
| 8816 | +# |
| 8817 | +# CONFIG_USB_PEGASUS is not set |
| 8818 | +# CONFIG_USB_RTL8150 is not set |
| 8819 | +# CONFIG_USB_KAWETH is not set |
| 8820 | +# CONFIG_USB_CATC is not set |
| 8821 | +# CONFIG_USB_CDCETHER is not set |
| 8822 | +# CONFIG_USB_USBNET is not set |
| 8823 | + |
| 8824 | +# |
| 8825 | +# USB port drivers |
| 8826 | +# |
| 8827 | +# CONFIG_USB_USS720 is not set |
| 8828 | + |
| 8829 | +# |
| 8830 | +# USB Serial Converter support |
| 8831 | +# |
| 8832 | +# CONFIG_USB_SERIAL is not set |
| 8833 | + |
| 8834 | +# |
| 8835 | +# USB Miscellaneous drivers |
| 8836 | +# |
| 8837 | +# CONFIG_USB_RIO500 is not set |
| 8838 | +# CONFIG_USB_AUERSWALD is not set |
| 8839 | +# CONFIG_USB_TIGL is not set |
| 8840 | +# CONFIG_USB_BRLVGER is not set |
| 8841 | +# CONFIG_USB_LCD is not set |
| 8842 | + |
| 8843 | +# |
| 8844 | +# Support for USB gadgets |
| 8845 | +# |
| 8846 | +# CONFIG_USB_GADGET is not set |
| 8847 | + |
| 8848 | +# |
| 8849 | +# Bluetooth support |
| 8850 | +# |
| 8851 | +# CONFIG_BLUEZ is not set |
| 8852 | + |
| 8853 | +# |
| 8854 | +# Kernel hacking |
| 8855 | +# |
| 8856 | +CONFIG_CROSSCOMPILE=y |
| 8857 | +# CONFIG_RUNTIME_DEBUG is not set |
| 8858 | +# CONFIG_KGDB is not set |
| 8859 | +# CONFIG_GDB_CONSOLE is not set |
| 8860 | +# CONFIG_DEBUG_INFO is not set |
| 8861 | +# CONFIG_MAGIC_SYSRQ is not set |
| 8862 | +# CONFIG_MIPS_UNCACHED is not set |
| 8863 | +CONFIG_LOG_BUF_SHIFT=0 |
| 8864 | + |
| 8865 | +# |
| 8866 | +# Cryptographic options |
| 8867 | +# |
| 8868 | +# CONFIG_CRYPTO is not set |
| 8869 | + |
| 8870 | +# |
| 8871 | +# Library routines |
| 8872 | +# |
| 8873 | +# CONFIG_CRC32 is not set |
| 8874 | +CONFIG_ZLIB_INFLATE=m |
| 8875 | +CONFIG_ZLIB_DEFLATE=m |
| 8876 | +# CONFIG_FW_LOADER is not set |
| 8877 | --- a/arch/mips/defconfig-pb1500 |
| 8878 | +++ b/arch/mips/defconfig-pb1500 |
| 8879 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 8880 | # CONFIG_MIPS_PB1000 is not set |
| 8881 | # CONFIG_MIPS_PB1100 is not set |
| 8882 | CONFIG_MIPS_PB1500=y |
| 8883 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 8884 | # CONFIG_MIPS_PB1550 is not set |
| 8885 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 8886 | # CONFIG_MIPS_XXS1500 is not set |
| 8887 | # CONFIG_MIPS_MTX1 is not set |
| 8888 | # CONFIG_COGENT_CSB250 is not set |
| 8889 | @@ -215,9 +215,7 @@ CONFIG_MTD_PB1500=y |
| 8890 | # CONFIG_MTD_MTX1 is not set |
| 8891 | CONFIG_MTD_PB1500_BOOT=y |
| 8892 | # CONFIG_MTD_PB1500_USER is not set |
| 8893 | -# CONFIG_MTD_DB1X00 is not set |
| 8894 | # CONFIG_MTD_PB1550 is not set |
| 8895 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 8896 | # CONFIG_MTD_MIRAGE is not set |
| 8897 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 8898 | # CONFIG_MTD_OCELOT is not set |
| 8899 | @@ -236,7 +234,6 @@ CONFIG_MTD_PB1500_BOOT=y |
| 8900 | # |
| 8901 | # Disk-On-Chip Device Drivers |
| 8902 | # |
| 8903 | -# CONFIG_MTD_DOC1000 is not set |
| 8904 | # CONFIG_MTD_DOC2000 is not set |
| 8905 | # CONFIG_MTD_DOC2001 is not set |
| 8906 | # CONFIG_MTD_DOCPROBE is not set |
| 8907 | @@ -341,11 +338,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 8908 | # |
| 8909 | # CONFIG_IPX is not set |
| 8910 | # CONFIG_ATALK is not set |
| 8911 | - |
| 8912 | -# |
| 8913 | -# Appletalk devices |
| 8914 | -# |
| 8915 | -# CONFIG_DEV_APPLETALK is not set |
| 8916 | # CONFIG_DECNET is not set |
| 8917 | # CONFIG_BRIDGE is not set |
| 8918 | # CONFIG_X25 is not set |
| 8919 | @@ -675,7 +667,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 8920 | # CONFIG_AU1X00_USB_TTY is not set |
| 8921 | # CONFIG_AU1X00_USB_RAW is not set |
| 8922 | # CONFIG_TXX927_SERIAL is not set |
| 8923 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 8924 | CONFIG_UNIX98_PTYS=y |
| 8925 | CONFIG_UNIX98_PTY_COUNT=256 |
| 8926 | |
| 8927 | --- a/arch/mips/defconfig-pb1550 |
| 8928 | +++ b/arch/mips/defconfig-pb1550 |
| 8929 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 8930 | # CONFIG_MIPS_PB1000 is not set |
| 8931 | # CONFIG_MIPS_PB1100 is not set |
| 8932 | # CONFIG_MIPS_PB1500 is not set |
| 8933 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 8934 | CONFIG_MIPS_PB1550=y |
| 8935 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 8936 | # CONFIG_MIPS_XXS1500 is not set |
| 8937 | # CONFIG_MIPS_MTX1 is not set |
| 8938 | # CONFIG_COGENT_CSB250 is not set |
| 8939 | @@ -213,11 +213,9 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 8940 | # CONFIG_MTD_BOSPORUS is not set |
| 8941 | # CONFIG_MTD_XXS1500 is not set |
| 8942 | # CONFIG_MTD_MTX1 is not set |
| 8943 | -# CONFIG_MTD_DB1X00 is not set |
| 8944 | CONFIG_MTD_PB1550=y |
| 8945 | CONFIG_MTD_PB1550_BOOT=y |
| 8946 | CONFIG_MTD_PB1550_USER=y |
| 8947 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 8948 | # CONFIG_MTD_MIRAGE is not set |
| 8949 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 8950 | # CONFIG_MTD_OCELOT is not set |
| 8951 | @@ -236,7 +234,6 @@ CONFIG_MTD_PB1550_USER=y |
| 8952 | # |
| 8953 | # Disk-On-Chip Device Drivers |
| 8954 | # |
| 8955 | -# CONFIG_MTD_DOC1000 is not set |
| 8956 | # CONFIG_MTD_DOC2000 is not set |
| 8957 | # CONFIG_MTD_DOC2001 is not set |
| 8958 | # CONFIG_MTD_DOCPROBE is not set |
| 8959 | @@ -343,11 +340,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 8960 | # |
| 8961 | # CONFIG_IPX is not set |
| 8962 | # CONFIG_ATALK is not set |
| 8963 | - |
| 8964 | -# |
| 8965 | -# Appletalk devices |
| 8966 | -# |
| 8967 | -# CONFIG_DEV_APPLETALK is not set |
| 8968 | # CONFIG_DECNET is not set |
| 8969 | # CONFIG_BRIDGE is not set |
| 8970 | # CONFIG_X25 is not set |
| 8971 | @@ -633,7 +625,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 8972 | # CONFIG_AU1X00_USB_TTY is not set |
| 8973 | # CONFIG_AU1X00_USB_RAW is not set |
| 8974 | # CONFIG_TXX927_SERIAL is not set |
| 8975 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 8976 | CONFIG_UNIX98_PTYS=y |
| 8977 | CONFIG_UNIX98_PTY_COUNT=256 |
| 8978 | |
| 8979 | --- a/arch/mips/defconfig-rbtx4927 |
| 8980 | +++ b/arch/mips/defconfig-rbtx4927 |
| 8981 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 8982 | # CONFIG_MIPS_PB1000 is not set |
| 8983 | # CONFIG_MIPS_PB1100 is not set |
| 8984 | # CONFIG_MIPS_PB1500 is not set |
| 8985 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 8986 | # CONFIG_MIPS_PB1550 is not set |
| 8987 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 8988 | # CONFIG_MIPS_XXS1500 is not set |
| 8989 | # CONFIG_MIPS_MTX1 is not set |
| 8990 | # CONFIG_COGENT_CSB250 is not set |
| 8991 | @@ -223,11 +223,6 @@ CONFIG_IP_PNP_DHCP=y |
| 8992 | # |
| 8993 | # CONFIG_IPX is not set |
| 8994 | # CONFIG_ATALK is not set |
| 8995 | - |
| 8996 | -# |
| 8997 | -# Appletalk devices |
| 8998 | -# |
| 8999 | -# CONFIG_DEV_APPLETALK is not set |
| 9000 | # CONFIG_DECNET is not set |
| 9001 | # CONFIG_BRIDGE is not set |
| 9002 | # CONFIG_X25 is not set |
| 9003 | @@ -466,7 +461,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 9004 | CONFIG_SERIAL_TXX9=y |
| 9005 | CONFIG_SERIAL_TXX9_CONSOLE=y |
| 9006 | # CONFIG_TXX927_SERIAL is not set |
| 9007 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9008 | # CONFIG_UNIX98_PTYS is not set |
| 9009 | |
| 9010 | # |
| 9011 | --- a/arch/mips/defconfig-rm200 |
| 9012 | +++ b/arch/mips/defconfig-rm200 |
| 9013 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9014 | # CONFIG_MIPS_PB1000 is not set |
| 9015 | # CONFIG_MIPS_PB1100 is not set |
| 9016 | # CONFIG_MIPS_PB1500 is not set |
| 9017 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9018 | # CONFIG_MIPS_PB1550 is not set |
| 9019 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9020 | # CONFIG_MIPS_XXS1500 is not set |
| 9021 | # CONFIG_MIPS_MTX1 is not set |
| 9022 | # CONFIG_COGENT_CSB250 is not set |
| 9023 | @@ -229,11 +229,6 @@ CONFIG_INET=y |
| 9024 | # |
| 9025 | # CONFIG_IPX is not set |
| 9026 | # CONFIG_ATALK is not set |
| 9027 | - |
| 9028 | -# |
| 9029 | -# Appletalk devices |
| 9030 | -# |
| 9031 | -# CONFIG_DEV_APPLETALK is not set |
| 9032 | # CONFIG_DECNET is not set |
| 9033 | # CONFIG_BRIDGE is not set |
| 9034 | # CONFIG_X25 is not set |
| 9035 | @@ -340,7 +335,6 @@ CONFIG_VT_CONSOLE=y |
| 9036 | # CONFIG_SERIAL is not set |
| 9037 | # CONFIG_SERIAL_EXTENDED is not set |
| 9038 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 9039 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9040 | CONFIG_UNIX98_PTYS=y |
| 9041 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9042 | |
| 9043 | --- a/arch/mips/defconfig-sb1250-swarm |
| 9044 | +++ b/arch/mips/defconfig-sb1250-swarm |
| 9045 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9046 | # CONFIG_MIPS_PB1000 is not set |
| 9047 | # CONFIG_MIPS_PB1100 is not set |
| 9048 | # CONFIG_MIPS_PB1500 is not set |
| 9049 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9050 | # CONFIG_MIPS_PB1550 is not set |
| 9051 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9052 | # CONFIG_MIPS_XXS1500 is not set |
| 9053 | # CONFIG_MIPS_MTX1 is not set |
| 9054 | # CONFIG_COGENT_CSB250 is not set |
| 9055 | @@ -90,6 +90,7 @@ CONFIG_SIBYTE_CFE=y |
| 9056 | # CONFIG_SIBYTE_TBPROF is not set |
| 9057 | CONFIG_SIBYTE_GENBUS_IDE=y |
| 9058 | CONFIG_SMP_CAPABLE=y |
| 9059 | +CONFIG_MIPS_RTC=y |
| 9060 | # CONFIG_SNI_RM200_PCI is not set |
| 9061 | # CONFIG_TANBAC_TB0226 is not set |
| 9062 | # CONFIG_TANBAC_TB0229 is not set |
| 9063 | @@ -253,11 +254,6 @@ CONFIG_INET=y |
| 9064 | # |
| 9065 | # CONFIG_IPX is not set |
| 9066 | # CONFIG_ATALK is not set |
| 9067 | - |
| 9068 | -# |
| 9069 | -# Appletalk devices |
| 9070 | -# |
| 9071 | -# CONFIG_DEV_APPLETALK is not set |
| 9072 | # CONFIG_DECNET is not set |
| 9073 | # CONFIG_BRIDGE is not set |
| 9074 | # CONFIG_X25 is not set |
| 9075 | @@ -469,7 +465,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 9076 | CONFIG_SIBYTE_SB1250_DUART=y |
| 9077 | CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y |
| 9078 | CONFIG_SERIAL_CONSOLE=y |
| 9079 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9080 | CONFIG_UNIX98_PTYS=y |
| 9081 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9082 | |
| 9083 | --- a/arch/mips/defconfig-sead |
| 9084 | +++ b/arch/mips/defconfig-sead |
| 9085 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 9086 | # CONFIG_MIPS_PB1000 is not set |
| 9087 | # CONFIG_MIPS_PB1100 is not set |
| 9088 | # CONFIG_MIPS_PB1500 is not set |
| 9089 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9090 | # CONFIG_MIPS_PB1550 is not set |
| 9091 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9092 | # CONFIG_MIPS_XXS1500 is not set |
| 9093 | # CONFIG_MIPS_MTX1 is not set |
| 9094 | # CONFIG_COGENT_CSB250 is not set |
| 9095 | @@ -244,7 +244,6 @@ CONFIG_SERIAL=y |
| 9096 | CONFIG_SERIAL_CONSOLE=y |
| 9097 | # CONFIG_SERIAL_EXTENDED is not set |
| 9098 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 9099 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9100 | # CONFIG_UNIX98_PTYS is not set |
| 9101 | |
| 9102 | # |
| 9103 | --- a/arch/mips/defconfig-stretch |
| 9104 | +++ b/arch/mips/defconfig-stretch |
| 9105 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9106 | # CONFIG_MIPS_PB1000 is not set |
| 9107 | # CONFIG_MIPS_PB1100 is not set |
| 9108 | # CONFIG_MIPS_PB1500 is not set |
| 9109 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9110 | # CONFIG_MIPS_PB1550 is not set |
| 9111 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9112 | # CONFIG_MIPS_XXS1500 is not set |
| 9113 | # CONFIG_MIPS_MTX1 is not set |
| 9114 | # CONFIG_COGENT_CSB250 is not set |
| 9115 | @@ -240,11 +240,6 @@ CONFIG_IP_PNP_DHCP=y |
| 9116 | # |
| 9117 | # CONFIG_IPX is not set |
| 9118 | # CONFIG_ATALK is not set |
| 9119 | - |
| 9120 | -# |
| 9121 | -# Appletalk devices |
| 9122 | -# |
| 9123 | -# CONFIG_DEV_APPLETALK is not set |
| 9124 | # CONFIG_DECNET is not set |
| 9125 | # CONFIG_BRIDGE is not set |
| 9126 | # CONFIG_X25 is not set |
| 9127 | @@ -324,9 +319,11 @@ CONFIG_CHR_DEV_SG=y |
| 9128 | # CONFIG_SCSI_MEGARAID is not set |
| 9129 | # CONFIG_SCSI_MEGARAID2 is not set |
| 9130 | # CONFIG_SCSI_SATA is not set |
| 9131 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 9132 | # CONFIG_SCSI_SATA_SVW is not set |
| 9133 | # CONFIG_SCSI_ATA_PIIX is not set |
| 9134 | # CONFIG_SCSI_SATA_NV is not set |
| 9135 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 9136 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 9137 | # CONFIG_SCSI_SATA_SX4 is not set |
| 9138 | # CONFIG_SCSI_SATA_SIL is not set |
| 9139 | @@ -516,7 +513,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 9140 | # CONFIG_SERIAL_TXX9 is not set |
| 9141 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 9142 | # CONFIG_TXX927_SERIAL is not set |
| 9143 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9144 | CONFIG_UNIX98_PTYS=y |
| 9145 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9146 | |
| 9147 | --- a/arch/mips/defconfig-tb0226 |
| 9148 | +++ b/arch/mips/defconfig-tb0226 |
| 9149 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9150 | # CONFIG_MIPS_PB1000 is not set |
| 9151 | # CONFIG_MIPS_PB1100 is not set |
| 9152 | # CONFIG_MIPS_PB1500 is not set |
| 9153 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9154 | # CONFIG_MIPS_PB1550 is not set |
| 9155 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9156 | # CONFIG_MIPS_XXS1500 is not set |
| 9157 | # CONFIG_MIPS_MTX1 is not set |
| 9158 | # CONFIG_COGENT_CSB250 is not set |
| 9159 | @@ -228,11 +228,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 9160 | # |
| 9161 | # CONFIG_IPX is not set |
| 9162 | # CONFIG_ATALK is not set |
| 9163 | - |
| 9164 | -# |
| 9165 | -# Appletalk devices |
| 9166 | -# |
| 9167 | -# CONFIG_DEV_APPLETALK is not set |
| 9168 | # CONFIG_DECNET is not set |
| 9169 | # CONFIG_BRIDGE is not set |
| 9170 | # CONFIG_X25 is not set |
| 9171 | @@ -312,9 +307,11 @@ CONFIG_SCSI_CONSTANTS=y |
| 9172 | # CONFIG_SCSI_MEGARAID is not set |
| 9173 | # CONFIG_SCSI_MEGARAID2 is not set |
| 9174 | # CONFIG_SCSI_SATA is not set |
| 9175 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 9176 | # CONFIG_SCSI_SATA_SVW is not set |
| 9177 | # CONFIG_SCSI_ATA_PIIX is not set |
| 9178 | # CONFIG_SCSI_SATA_NV is not set |
| 9179 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 9180 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 9181 | # CONFIG_SCSI_SATA_SX4 is not set |
| 9182 | # CONFIG_SCSI_SATA_SIL is not set |
| 9183 | @@ -518,7 +515,6 @@ CONFIG_SERIAL=y |
| 9184 | CONFIG_SERIAL_CONSOLE=y |
| 9185 | # CONFIG_SERIAL_EXTENDED is not set |
| 9186 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 9187 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9188 | # CONFIG_VR41XX_KIU is not set |
| 9189 | CONFIG_UNIX98_PTYS=y |
| 9190 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9191 | --- a/arch/mips/defconfig-tb0229 |
| 9192 | +++ b/arch/mips/defconfig-tb0229 |
| 9193 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9194 | # CONFIG_MIPS_PB1000 is not set |
| 9195 | # CONFIG_MIPS_PB1100 is not set |
| 9196 | # CONFIG_MIPS_PB1500 is not set |
| 9197 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9198 | # CONFIG_MIPS_PB1550 is not set |
| 9199 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9200 | # CONFIG_MIPS_XXS1500 is not set |
| 9201 | # CONFIG_MIPS_MTX1 is not set |
| 9202 | # CONFIG_COGENT_CSB250 is not set |
| 9203 | @@ -230,11 +230,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 9204 | # |
| 9205 | # CONFIG_IPX is not set |
| 9206 | # CONFIG_ATALK is not set |
| 9207 | - |
| 9208 | -# |
| 9209 | -# Appletalk devices |
| 9210 | -# |
| 9211 | -# CONFIG_DEV_APPLETALK is not set |
| 9212 | # CONFIG_DECNET is not set |
| 9213 | # CONFIG_BRIDGE is not set |
| 9214 | # CONFIG_X25 is not set |
| 9215 | @@ -445,7 +440,6 @@ CONFIG_SERIAL=y |
| 9216 | CONFIG_SERIAL_CONSOLE=y |
| 9217 | # CONFIG_SERIAL_EXTENDED is not set |
| 9218 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 9219 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9220 | # CONFIG_VR41XX_KIU is not set |
| 9221 | CONFIG_UNIX98_PTYS=y |
| 9222 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9223 | --- a/arch/mips/defconfig-ti1500 |
| 9224 | +++ b/arch/mips/defconfig-ti1500 |
| 9225 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9226 | # CONFIG_MIPS_PB1000 is not set |
| 9227 | # CONFIG_MIPS_PB1100 is not set |
| 9228 | # CONFIG_MIPS_PB1500 is not set |
| 9229 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9230 | # CONFIG_MIPS_PB1550 is not set |
| 9231 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9232 | CONFIG_MIPS_XXS1500=y |
| 9233 | # CONFIG_MIPS_MTX1 is not set |
| 9234 | # CONFIG_COGENT_CSB250 is not set |
| 9235 | @@ -213,9 +213,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 9236 | # CONFIG_MTD_BOSPORUS is not set |
| 9237 | CONFIG_MTD_XXS1500=y |
| 9238 | # CONFIG_MTD_MTX1 is not set |
| 9239 | -# CONFIG_MTD_DB1X00 is not set |
| 9240 | # CONFIG_MTD_PB1550 is not set |
| 9241 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 9242 | # CONFIG_MTD_MIRAGE is not set |
| 9243 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 9244 | # CONFIG_MTD_OCELOT is not set |
| 9245 | @@ -234,7 +232,6 @@ CONFIG_MTD_XXS1500=y |
| 9246 | # |
| 9247 | # Disk-On-Chip Device Drivers |
| 9248 | # |
| 9249 | -# CONFIG_MTD_DOC1000 is not set |
| 9250 | # CONFIG_MTD_DOC2000 is not set |
| 9251 | # CONFIG_MTD_DOC2001 is not set |
| 9252 | # CONFIG_MTD_DOCPROBE is not set |
| 9253 | @@ -339,11 +336,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 9254 | # |
| 9255 | # CONFIG_IPX is not set |
| 9256 | # CONFIG_ATALK is not set |
| 9257 | - |
| 9258 | -# |
| 9259 | -# Appletalk devices |
| 9260 | -# |
| 9261 | -# CONFIG_DEV_APPLETALK is not set |
| 9262 | # CONFIG_DECNET is not set |
| 9263 | # CONFIG_BRIDGE is not set |
| 9264 | # CONFIG_X25 is not set |
| 9265 | @@ -600,7 +592,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 9266 | # CONFIG_AU1X00_USB_TTY is not set |
| 9267 | # CONFIG_AU1X00_USB_RAW is not set |
| 9268 | # CONFIG_TXX927_SERIAL is not set |
| 9269 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9270 | CONFIG_UNIX98_PTYS=y |
| 9271 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9272 | |
| 9273 | --- a/arch/mips/defconfig-workpad |
| 9274 | +++ b/arch/mips/defconfig-workpad |
| 9275 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9276 | # CONFIG_MIPS_PB1000 is not set |
| 9277 | # CONFIG_MIPS_PB1100 is not set |
| 9278 | # CONFIG_MIPS_PB1500 is not set |
| 9279 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9280 | # CONFIG_MIPS_PB1550 is not set |
| 9281 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9282 | # CONFIG_MIPS_XXS1500 is not set |
| 9283 | # CONFIG_MIPS_MTX1 is not set |
| 9284 | # CONFIG_COGENT_CSB250 is not set |
| 9285 | @@ -222,11 +222,6 @@ CONFIG_IP_MULTICAST=y |
| 9286 | # |
| 9287 | # CONFIG_IPX is not set |
| 9288 | # CONFIG_ATALK is not set |
| 9289 | - |
| 9290 | -# |
| 9291 | -# Appletalk devices |
| 9292 | -# |
| 9293 | -# CONFIG_DEV_APPLETALK is not set |
| 9294 | # CONFIG_DECNET is not set |
| 9295 | # CONFIG_BRIDGE is not set |
| 9296 | # CONFIG_X25 is not set |
| 9297 | @@ -426,7 +421,6 @@ CONFIG_SERIAL_MANY_PORTS=y |
| 9298 | # CONFIG_SERIAL_MULTIPORT is not set |
| 9299 | # CONFIG_HUB6 is not set |
| 9300 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 9301 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9302 | # CONFIG_VR41XX_KIU is not set |
| 9303 | CONFIG_UNIX98_PTYS=y |
| 9304 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9305 | --- a/arch/mips/defconfig-xxs1500 |
| 9306 | +++ b/arch/mips/defconfig-xxs1500 |
| 9307 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9308 | # CONFIG_MIPS_PB1000 is not set |
| 9309 | # CONFIG_MIPS_PB1100 is not set |
| 9310 | # CONFIG_MIPS_PB1500 is not set |
| 9311 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9312 | # CONFIG_MIPS_PB1550 is not set |
| 9313 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9314 | CONFIG_MIPS_XXS1500=y |
| 9315 | # CONFIG_MIPS_MTX1 is not set |
| 9316 | # CONFIG_COGENT_CSB250 is not set |
| 9317 | @@ -213,9 +213,7 @@ CONFIG_MTD_CFI_AMDSTD=y |
| 9318 | # CONFIG_MTD_BOSPORUS is not set |
| 9319 | CONFIG_MTD_XXS1500=y |
| 9320 | # CONFIG_MTD_MTX1 is not set |
| 9321 | -# CONFIG_MTD_DB1X00 is not set |
| 9322 | # CONFIG_MTD_PB1550 is not set |
| 9323 | -# CONFIG_MTD_HYDROGEN3 is not set |
| 9324 | # CONFIG_MTD_MIRAGE is not set |
| 9325 | # CONFIG_MTD_CSTM_MIPS_IXX is not set |
| 9326 | # CONFIG_MTD_OCELOT is not set |
| 9327 | @@ -234,7 +232,6 @@ CONFIG_MTD_XXS1500=y |
| 9328 | # |
| 9329 | # Disk-On-Chip Device Drivers |
| 9330 | # |
| 9331 | -# CONFIG_MTD_DOC1000 is not set |
| 9332 | # CONFIG_MTD_DOC2000 is not set |
| 9333 | # CONFIG_MTD_DOC2001 is not set |
| 9334 | # CONFIG_MTD_DOCPROBE is not set |
| 9335 | @@ -339,11 +336,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 9336 | # |
| 9337 | # CONFIG_IPX is not set |
| 9338 | # CONFIG_ATALK is not set |
| 9339 | - |
| 9340 | -# |
| 9341 | -# Appletalk devices |
| 9342 | -# |
| 9343 | -# CONFIG_DEV_APPLETALK is not set |
| 9344 | # CONFIG_DECNET is not set |
| 9345 | # CONFIG_BRIDGE is not set |
| 9346 | # CONFIG_X25 is not set |
| 9347 | @@ -671,7 +663,6 @@ CONFIG_AU1X00_SERIAL_CONSOLE=y |
| 9348 | # CONFIG_AU1X00_USB_TTY is not set |
| 9349 | # CONFIG_AU1X00_USB_RAW is not set |
| 9350 | # CONFIG_TXX927_SERIAL is not set |
| 9351 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9352 | CONFIG_UNIX98_PTYS=y |
| 9353 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9354 | |
| 9355 | --- a/arch/mips/defconfig-yosemite |
| 9356 | +++ b/arch/mips/defconfig-yosemite |
| 9357 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 9358 | # CONFIG_MIPS_PB1000 is not set |
| 9359 | # CONFIG_MIPS_PB1100 is not set |
| 9360 | # CONFIG_MIPS_PB1500 is not set |
| 9361 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 9362 | # CONFIG_MIPS_PB1550 is not set |
| 9363 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 9364 | # CONFIG_MIPS_XXS1500 is not set |
| 9365 | # CONFIG_MIPS_MTX1 is not set |
| 9366 | # CONFIG_COGENT_CSB250 is not set |
| 9367 | @@ -227,11 +227,6 @@ CONFIG_IP_PNP_DHCP=y |
| 9368 | # |
| 9369 | # CONFIG_IPX is not set |
| 9370 | # CONFIG_ATALK is not set |
| 9371 | - |
| 9372 | -# |
| 9373 | -# Appletalk devices |
| 9374 | -# |
| 9375 | -# CONFIG_DEV_APPLETALK is not set |
| 9376 | # CONFIG_DECNET is not set |
| 9377 | # CONFIG_BRIDGE is not set |
| 9378 | # CONFIG_X25 is not set |
| 9379 | @@ -310,9 +305,11 @@ CONFIG_CHR_DEV_SG=y |
| 9380 | # CONFIG_SCSI_MEGARAID is not set |
| 9381 | # CONFIG_SCSI_MEGARAID2 is not set |
| 9382 | # CONFIG_SCSI_SATA is not set |
| 9383 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 9384 | # CONFIG_SCSI_SATA_SVW is not set |
| 9385 | # CONFIG_SCSI_ATA_PIIX is not set |
| 9386 | # CONFIG_SCSI_SATA_NV is not set |
| 9387 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 9388 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 9389 | # CONFIG_SCSI_SATA_SX4 is not set |
| 9390 | # CONFIG_SCSI_SATA_SIL is not set |
| 9391 | @@ -477,7 +474,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 9392 | # CONFIG_SERIAL_TXX9 is not set |
| 9393 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 9394 | # CONFIG_TXX927_SERIAL is not set |
| 9395 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 9396 | CONFIG_UNIX98_PTYS=y |
| 9397 | CONFIG_UNIX98_PTY_COUNT=256 |
| 9398 | |
| 9399 | --- a/arch/mips/kernel/cpu-probe.c |
| 9400 | +++ b/arch/mips/kernel/cpu-probe.c |
| 9401 | @@ -34,21 +34,16 @@ static void r4k_wait(void) |
| 9402 | ".set\tmips0"); |
| 9403 | } |
| 9404 | |
| 9405 | -/* The Au1xxx wait is available only if we run CONFIG_PM and |
| 9406 | - * the timer setup found we had a 32KHz counter available. |
| 9407 | - * There are still problems with functions that may call au1k_wait |
| 9408 | - * directly, but that will be discovered pretty quickly. |
| 9409 | - */ |
| 9410 | -extern void (*au1k_wait_ptr)(void); |
| 9411 | -void au1k_wait(void) |
| 9412 | +/* The Au1xxx wait is available only if using 32khz counter or |
| 9413 | + * external timer source, but specifically not CP0 Counter. */ |
| 9414 | +int allow_au1k_wait; |
| 9415 | + |
| 9416 | +static void au1k_wait(void) |
| 9417 | { |
| 9418 | -#ifdef CONFIG_PM |
| 9419 | - unsigned long addr; |
| 9420 | /* using the wait instruction makes CP0 counter unusable */ |
| 9421 | - __asm__("la %0,au1k_wait\n\t" |
| 9422 | - ".set mips3\n\t" |
| 9423 | - "cache 0x14,0(%0)\n\t" |
| 9424 | - "cache 0x14,32(%0)\n\t" |
| 9425 | + __asm__(".set mips3\n\t" |
| 9426 | + "cache 0x14, 0(%0)\n\t" |
| 9427 | + "cache 0x14, 32(%0)\n\t" |
| 9428 | "sync\n\t" |
| 9429 | "nop\n\t" |
| 9430 | "wait\n\t" |
| 9431 | @@ -57,11 +52,7 @@ void au1k_wait(void) |
| 9432 | "nop\n\t" |
| 9433 | "nop\n\t" |
| 9434 | ".set mips0\n\t" |
| 9435 | - : : "r" (addr)); |
| 9436 | -#else |
| 9437 | - __asm__("nop\n\t" |
| 9438 | - "nop"); |
| 9439 | -#endif |
| 9440 | + : : "r" (au1k_wait)); |
| 9441 | } |
| 9442 | |
| 9443 | static inline void check_wait(void) |
| 9444 | @@ -100,20 +91,17 @@ static inline void check_wait(void) |
| 9445 | cpu_wait = r4k_wait; |
| 9446 | printk(" available.\n"); |
| 9447 | break; |
| 9448 | -#ifdef CONFIG_PM |
| 9449 | case CPU_AU1000: |
| 9450 | case CPU_AU1100: |
| 9451 | case CPU_AU1500: |
| 9452 | case CPU_AU1550: |
| 9453 | - if (au1k_wait_ptr != NULL) { |
| 9454 | - cpu_wait = au1k_wait_ptr; |
| 9455 | + case CPU_AU1200: |
| 9456 | + if (allow_au1k_wait) { |
| 9457 | + cpu_wait = au1k_wait; |
| 9458 | printk(" available.\n"); |
| 9459 | - } |
| 9460 | - else { |
| 9461 | + } else |
| 9462 | printk(" unavailable.\n"); |
| 9463 | - } |
| 9464 | break; |
| 9465 | -#endif |
| 9466 | default: |
| 9467 | printk(" unavailable.\n"); |
| 9468 | break; |
| 9469 | --- a/arch/mips/kernel/head.S |
| 9470 | +++ b/arch/mips/kernel/head.S |
| 9471 | @@ -43,9 +43,9 @@ |
| 9472 | |
| 9473 | /* Cache Error */ |
| 9474 | LEAF(except_vec2_generic) |
| 9475 | + .set push |
| 9476 | .set noreorder |
| 9477 | .set noat |
| 9478 | - .set mips0 |
| 9479 | /* |
| 9480 | * This is a very bad place to be. Our cache error |
| 9481 | * detection has triggered. If we have write-back data |
| 9482 | @@ -64,10 +64,9 @@ |
| 9483 | |
| 9484 | j cache_parity_error |
| 9485 | nop |
| 9486 | + .set pop |
| 9487 | END(except_vec2_generic) |
| 9488 | |
| 9489 | - .set at |
| 9490 | - |
| 9491 | /* |
| 9492 | * Special interrupt vector for embedded MIPS. This is a |
| 9493 | * dedicated interrupt vector which reduces interrupt processing |
| 9494 | @@ -76,8 +75,11 @@ |
| 9495 | * size! |
| 9496 | */ |
| 9497 | NESTED(except_vec4, 0, sp) |
| 9498 | + .set push |
| 9499 | + .set noreorder |
| 9500 | 1: j 1b /* Dummy, will be replaced */ |
| 9501 | nop |
| 9502 | + .set pop |
| 9503 | END(except_vec4) |
| 9504 | |
| 9505 | /* |
| 9506 | @@ -87,8 +89,11 @@ |
| 9507 | * unconditional jump to this vector. |
| 9508 | */ |
| 9509 | NESTED(except_vec_ejtag_debug, 0, sp) |
| 9510 | + .set push |
| 9511 | + .set noreorder |
| 9512 | j ejtag_debug_handler |
| 9513 | nop |
| 9514 | + .set pop |
| 9515 | END(except_vec_ejtag_debug) |
| 9516 | |
| 9517 | __FINIT |
| 9518 | @@ -97,6 +102,7 @@ |
| 9519 | * EJTAG debug exception handler. |
| 9520 | */ |
| 9521 | NESTED(ejtag_debug_handler, PT_SIZE, sp) |
| 9522 | + .set push |
| 9523 | .set noat |
| 9524 | .set noreorder |
| 9525 | mtc0 k0, CP0_DESAVE |
| 9526 | @@ -120,7 +126,7 @@ ejtag_return: |
| 9527 | deret |
| 9528 | .set mips0 |
| 9529 | nop |
| 9530 | - .set at |
| 9531 | + .set pop |
| 9532 | END(ejtag_debug_handler) |
| 9533 | |
| 9534 | __INIT |
| 9535 | @@ -132,13 +138,17 @@ ejtag_return: |
| 9536 | * unconditional jump to this vector. |
| 9537 | */ |
| 9538 | NESTED(except_vec_nmi, 0, sp) |
| 9539 | + .set push |
| 9540 | + .set noreorder |
| 9541 | j nmi_handler |
| 9542 | nop |
| 9543 | + .set pop |
| 9544 | END(except_vec_nmi) |
| 9545 | |
| 9546 | __FINIT |
| 9547 | |
| 9548 | NESTED(nmi_handler, PT_SIZE, sp) |
| 9549 | + .set push |
| 9550 | .set noat |
| 9551 | .set noreorder |
| 9552 | .set mips3 |
| 9553 | @@ -147,8 +157,7 @@ ejtag_return: |
| 9554 | move a0, sp |
| 9555 | RESTORE_ALL |
| 9556 | eret |
| 9557 | - .set at |
| 9558 | - .set mips0 |
| 9559 | + .set pop |
| 9560 | END(nmi_handler) |
| 9561 | |
| 9562 | __INIT |
| 9563 | @@ -157,7 +166,20 @@ ejtag_return: |
| 9564 | * Kernel entry point |
| 9565 | */ |
| 9566 | NESTED(kernel_entry, 16, sp) |
| 9567 | + .set push |
| 9568 | + /* |
| 9569 | + * For the moment disable interrupts and mark the kernel mode. |
| 9570 | + * A full initialization of the CPU's status register is done |
| 9571 | + * later in per_cpu_trap_init(). |
| 9572 | + */ |
| 9573 | + mfc0 t0, CP0_STATUS |
| 9574 | + or t0, ST0_CU0|0x1f |
| 9575 | + xor t0, 0x1f |
| 9576 | + mtc0 t0, CP0_STATUS |
| 9577 | + |
| 9578 | .set noreorder |
| 9579 | + sll zero,3 # ehb |
| 9580 | + .set reorder |
| 9581 | |
| 9582 | /* |
| 9583 | * The firmware/bootloader passes argc/argp/envp |
| 9584 | @@ -170,8 +192,8 @@ ejtag_return: |
| 9585 | la t1, (_end - 4) |
| 9586 | 1: |
| 9587 | addiu t0, 4 |
| 9588 | + sw zero, (t0) |
| 9589 | bne t0, t1, 1b |
| 9590 | - sw zero, (t0) |
| 9591 | |
| 9592 | /* |
| 9593 | * Stack for kernel and init, current variable |
| 9594 | @@ -182,7 +204,7 @@ ejtag_return: |
| 9595 | sw t0, kernelsp |
| 9596 | |
| 9597 | jal init_arch |
| 9598 | - nop |
| 9599 | + .set pop |
| 9600 | END(kernel_entry) |
| 9601 | |
| 9602 | |
| 9603 | @@ -193,17 +215,26 @@ ejtag_return: |
| 9604 | * function after setting up the stack and gp registers. |
| 9605 | */ |
| 9606 | LEAF(smp_bootstrap) |
| 9607 | - .set push |
| 9608 | - .set noreorder |
| 9609 | - mtc0 zero, CP0_WIRED |
| 9610 | - CLI |
| 9611 | + .set push |
| 9612 | + /* |
| 9613 | + * For the moment disable interrupts and bootstrap exception |
| 9614 | + * vectors and mark the kernel mode. A full initialization of |
| 9615 | + * the CPU's status register is done later in |
| 9616 | + * per_cpu_trap_init(). |
| 9617 | + */ |
| 9618 | mfc0 t0, CP0_STATUS |
| 9619 | - li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_UX) |
| 9620 | - and t0, t1 |
| 9621 | - or t0, (ST0_CU0); |
| 9622 | + or t0, ST0_CU0|ST0_BEV|0x1f |
| 9623 | + xor t0, ST0_BEV|0x1f |
| 9624 | + mtc0 t0, CP0_STATUS |
| 9625 | + |
| 9626 | + .set noreorder |
| 9627 | + sll zero,3 # ehb |
| 9628 | + .set reorder |
| 9629 | + |
| 9630 | + mtc0 zero, CP0_WIRED |
| 9631 | + |
| 9632 | jal start_secondary |
| 9633 | - mtc0 t0, CP0_STATUS |
| 9634 | - .set pop |
| 9635 | + .set pop |
| 9636 | END(smp_bootstrap) |
| 9637 | #endif |
| 9638 | |
| 9639 | --- a/arch/mips/kernel/process.c |
| 9640 | +++ b/arch/mips/kernel/process.c |
| 9641 | @@ -128,6 +128,26 @@ int dump_fpu(struct pt_regs *regs, elf_f |
| 9642 | return 1; |
| 9643 | } |
| 9644 | |
| 9645 | +void dump_regs(elf_greg_t *gp, struct pt_regs *regs) |
| 9646 | +{ |
| 9647 | + int i; |
| 9648 | + |
| 9649 | + for (i = 0; i < EF_REG0; i++) |
| 9650 | + gp[i] = 0; |
| 9651 | + gp[EF_REG0] = 0; |
| 9652 | + for (i = 1; i <= 31; i++) |
| 9653 | + gp[EF_REG0 + i] = regs->regs[i]; |
| 9654 | + gp[EF_REG26] = 0; |
| 9655 | + gp[EF_REG27] = 0; |
| 9656 | + gp[EF_LO] = regs->lo; |
| 9657 | + gp[EF_HI] = regs->hi; |
| 9658 | + gp[EF_CP0_EPC] = regs->cp0_epc; |
| 9659 | + gp[EF_CP0_BADVADDR] = regs->cp0_badvaddr; |
| 9660 | + gp[EF_CP0_STATUS] = regs->cp0_status; |
| 9661 | + gp[EF_CP0_CAUSE] = regs->cp0_cause; |
| 9662 | + gp[EF_UNUSED0] = 0; |
| 9663 | +} |
| 9664 | + |
| 9665 | /* |
| 9666 | * Create a kernel thread |
| 9667 | */ |
| 9668 | --- a/arch/mips/kernel/scall_o32.S |
| 9669 | +++ b/arch/mips/kernel/scall_o32.S |
| 9670 | @@ -121,15 +121,14 @@ reschedule: |
| 9671 | |
| 9672 | trace_a_syscall: |
| 9673 | SAVE_STATIC |
| 9674 | - sw t2, PT_R1(sp) |
| 9675 | + move s0, t2 |
| 9676 | jal syscall_trace |
| 9677 | - lw t2, PT_R1(sp) |
| 9678 | |
| 9679 | lw a0, PT_R4(sp) # Restore argument registers |
| 9680 | lw a1, PT_R5(sp) |
| 9681 | lw a2, PT_R6(sp) |
| 9682 | lw a3, PT_R7(sp) |
| 9683 | - jalr t2 |
| 9684 | + jalr s0 |
| 9685 | |
| 9686 | li t0, -EMAXERRNO - 1 # error? |
| 9687 | sltu t0, t0, v0 |
| 9688 | --- a/arch/mips/kernel/setup.c |
| 9689 | +++ b/arch/mips/kernel/setup.c |
| 9690 | @@ -5,7 +5,7 @@ |
| 9691 | * |
| 9692 | * Copyright (C) 1995 Linus Torvalds |
| 9693 | * Copyright (C) 1995 Waldorf Electronics |
| 9694 | - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle |
| 9695 | + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 01, 05 Ralf Baechle |
| 9696 | * Copyright (C) 1996 Stoned Elipot |
| 9697 | * Copyright (C) 2000, 2001, 2002 Maciej W. Rozycki |
| 9698 | */ |
| 9699 | @@ -71,6 +71,8 @@ extern void * __rd_start, * __rd_end; |
| 9700 | extern struct rtc_ops no_rtc_ops; |
| 9701 | struct rtc_ops *rtc_ops; |
| 9702 | |
| 9703 | +EXPORT_SYMBOL(rtc_ops); |
| 9704 | + |
| 9705 | #ifdef CONFIG_PC_KEYB |
| 9706 | struct kbd_ops *kbd_ops; |
| 9707 | #endif |
| 9708 | @@ -132,10 +134,6 @@ init_arch(int argc, char **argv, char ** |
| 9709 | */ |
| 9710 | load_mmu(); |
| 9711 | |
| 9712 | - /* Disable coprocessors and set FPU for 16/32 FPR register model */ |
| 9713 | - clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR); |
| 9714 | - set_c0_status(ST0_CU0); |
| 9715 | - |
| 9716 | start_kernel(); |
| 9717 | } |
| 9718 | |
| 9719 | --- a/arch/mips/kernel/traps.c |
| 9720 | +++ b/arch/mips/kernel/traps.c |
| 9721 | @@ -452,9 +452,10 @@ static inline void simulate_ll(struct pt |
| 9722 | } |
| 9723 | ll_task = current; |
| 9724 | |
| 9725 | + compute_return_epc(regs); |
| 9726 | + |
| 9727 | regs->regs[(opcode & RT) >> 16] = value; |
| 9728 | |
| 9729 | - compute_return_epc(regs); |
| 9730 | return; |
| 9731 | |
| 9732 | sig: |
| 9733 | @@ -485,8 +486,8 @@ static inline void simulate_sc(struct pt |
| 9734 | goto sig; |
| 9735 | } |
| 9736 | if (ll_bit == 0 || ll_task != current) { |
| 9737 | - regs->regs[reg] = 0; |
| 9738 | compute_return_epc(regs); |
| 9739 | + regs->regs[reg] = 0; |
| 9740 | return; |
| 9741 | } |
| 9742 | |
| 9743 | @@ -495,9 +496,9 @@ static inline void simulate_sc(struct pt |
| 9744 | goto sig; |
| 9745 | } |
| 9746 | |
| 9747 | + compute_return_epc(regs); |
| 9748 | regs->regs[reg] = 1; |
| 9749 | |
| 9750 | - compute_return_epc(regs); |
| 9751 | return; |
| 9752 | |
| 9753 | sig: |
| 9754 | @@ -887,12 +888,18 @@ extern asmlinkage int fpu_emulator_resto |
| 9755 | void __init per_cpu_trap_init(void) |
| 9756 | { |
| 9757 | unsigned int cpu = smp_processor_id(); |
| 9758 | + unsigned int status_set = ST0_CU0; |
| 9759 | |
| 9760 | - /* Some firmware leaves the BEV flag set, clear it. */ |
| 9761 | - clear_c0_status(ST0_CU3|ST0_CU2|ST0_CU1|ST0_BEV|ST0_KX|ST0_SX|ST0_UX); |
| 9762 | - |
| 9763 | + /* |
| 9764 | + * Disable coprocessors and 64-bit addressing and set FPU for |
| 9765 | + * the 16/32 FPR register model. Reset the BEV flag that some |
| 9766 | + * firmware may have left set and the TS bit (for IP27). Set |
| 9767 | + * XX for ISA IV code to work. |
| 9768 | + */ |
| 9769 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) |
| 9770 | - set_c0_status(ST0_XX); |
| 9771 | + status_set |= ST0_XX; |
| 9772 | + change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
| 9773 | + status_set); |
| 9774 | |
| 9775 | /* |
| 9776 | * Some MIPS CPUs have a dedicated interrupt vector which reduces the |
| 9777 | @@ -902,7 +909,7 @@ void __init per_cpu_trap_init(void) |
| 9778 | set_c0_cause(CAUSEF_IV); |
| 9779 | |
| 9780 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; |
| 9781 | - write_c0_context(cpu << 23); |
| 9782 | + TLBMISS_HANDLER_SETUP(); |
| 9783 | |
| 9784 | atomic_inc(&init_mm.mm_count); |
| 9785 | current->active_mm = &init_mm; |
| 9786 | @@ -918,8 +925,6 @@ void __init trap_init(void) |
| 9787 | extern char except_vec4; |
| 9788 | unsigned long i; |
| 9789 | |
| 9790 | - per_cpu_trap_init(); |
| 9791 | - |
| 9792 | /* Copy the generic exception handler code to it's final destination. */ |
| 9793 | memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80); |
| 9794 | |
| 9795 | @@ -1020,10 +1025,5 @@ void __init trap_init(void) |
| 9796 | |
| 9797 | flush_icache_range(KSEG0, KSEG0 + 0x400); |
| 9798 | |
| 9799 | - atomic_inc(&init_mm.mm_count); /* XXX UP? */ |
| 9800 | - current->active_mm = &init_mm; |
| 9801 | - |
| 9802 | - /* XXX Must be done for all CPUs */ |
| 9803 | - current_cpu_data.asid_cache = ASID_FIRST_VERSION; |
| 9804 | - TLBMISS_HANDLER_SETUP(); |
| 9805 | + per_cpu_trap_init(); |
| 9806 | } |
| 9807 | --- a/arch/mips/lib/rtc-no.c |
| 9808 | +++ b/arch/mips/lib/rtc-no.c |
| 9809 | @@ -6,10 +6,9 @@ |
| 9810 | * Stub RTC routines to keep Linux from crashing on machine which don't |
| 9811 | * have a RTC chip. |
| 9812 | * |
| 9813 | - * Copyright (C) 1998, 2001 by Ralf Baechle |
| 9814 | + * Copyright (C) 1998, 2001, 2005 by Ralf Baechle |
| 9815 | */ |
| 9816 | #include <linux/kernel.h> |
| 9817 | -#include <linux/module.h> |
| 9818 | #include <linux/mc146818rtc.h> |
| 9819 | |
| 9820 | static unsigned int shouldnt_happen(void) |
| 9821 | @@ -29,5 +28,3 @@ struct rtc_ops no_rtc_ops = { |
| 9822 | .rtc_write_data = (void *) &shouldnt_happen, |
| 9823 | .rtc_bcd_mode = (void *) &shouldnt_happen |
| 9824 | }; |
| 9825 | - |
| 9826 | -EXPORT_SYMBOL(rtc_ops); |
| 9827 | --- a/arch/mips/lib/rtc-std.c |
| 9828 | +++ b/arch/mips/lib/rtc-std.c |
| 9829 | @@ -5,9 +5,8 @@ |
| 9830 | * |
| 9831 | * RTC routines for PC style attached Dallas chip. |
| 9832 | * |
| 9833 | - * Copyright (C) 1998, 2001 by Ralf Baechle |
| 9834 | + * Copyright (C) 1998, 2001, 05 by Ralf Baechle |
| 9835 | */ |
| 9836 | -#include <linux/module.h> |
| 9837 | #include <linux/mc146818rtc.h> |
| 9838 | #include <asm/io.h> |
| 9839 | |
| 9840 | @@ -33,5 +32,3 @@ struct rtc_ops std_rtc_ops = { |
| 9841 | &std_rtc_write_data, |
| 9842 | &std_rtc_bcd_mode |
| 9843 | }; |
| 9844 | - |
| 9845 | -EXPORT_SYMBOL(rtc_ops); |
| 9846 | --- a/arch/mips/Makefile |
| 9847 | +++ b/arch/mips/Makefile |
| 9848 | @@ -209,7 +209,7 @@ LOADADDR := 0x80080000 |
| 9849 | endif |
| 9850 | |
| 9851 | # |
| 9852 | -# Au1000 (Alchemy Semi PB1000) eval board |
| 9853 | +# Au1x AMD Alchemy eval boards |
| 9854 | # |
| 9855 | ifdef CONFIG_MIPS_PB1000 |
| 9856 | LIBS += arch/mips/au1000/pb1000/pb1000.o \ |
| 9857 | @@ -218,9 +218,6 @@ SUBDIRS += arch/mips/au1000/pb1000 arch |
| 9858 | LOADADDR := 0x80100000 |
| 9859 | endif |
| 9860 | |
| 9861 | -# |
| 9862 | -# Au1100 (Alchemy Semi PB1100) eval board |
| 9863 | -# |
| 9864 | ifdef CONFIG_MIPS_PB1100 |
| 9865 | LIBS += arch/mips/au1000/pb1100/pb1100.o \ |
| 9866 | arch/mips/au1000/common/au1000.o |
| 9867 | @@ -228,9 +225,6 @@ SUBDIRS += arch/mips/au1000/pb1100 |
| 9868 | LOADADDR += 0x80100000 |
| 9869 | endif |
| 9870 | |
| 9871 | -# |
| 9872 | -# Au1500 (Alchemy Semi PB1500) eval board |
| 9873 | -# |
| 9874 | ifdef CONFIG_MIPS_PB1500 |
| 9875 | LIBS += arch/mips/au1000/pb1500/pb1500.o \ |
| 9876 | arch/mips/au1000/common/au1000.o |
| 9877 | @@ -238,9 +232,6 @@ SUBDIRS += arch/mips/au1000/pb1500 arch |
| 9878 | LOADADDR := 0x80100000 |
| 9879 | endif |
| 9880 | |
| 9881 | -# |
| 9882 | -# Au1x00 (AMD/Alchemy) eval boards |
| 9883 | -# |
| 9884 | ifdef CONFIG_MIPS_DB1000 |
| 9885 | LIBS += arch/mips/au1000/db1x00/db1x00.o \ |
| 9886 | arch/mips/au1000/common/au1000.o |
| 9887 | @@ -311,6 +302,27 @@ SUBDIRS += arch/mips/au1000/pb1550 |
| 9888 | LOADADDR += 0x80100000 |
| 9889 | endif |
| 9890 | |
| 9891 | +ifdef CONFIG_MIPS_PB1200 |
| 9892 | +LIBS += arch/mips/au1000/pb1200/pb1200.o \ |
| 9893 | + arch/mips/au1000/common/au1000.o |
| 9894 | +SUBDIRS += arch/mips/au1000/pb1200 arch/mips/au1000/common |
| 9895 | +LOADADDR += 0x80100000 |
| 9896 | +endif |
| 9897 | + |
| 9898 | +ifdef CONFIG_MIPS_DB1200 |
| 9899 | +LIBS += arch/mips/au1000/pb1200/pb1200.o \ |
| 9900 | + arch/mips/au1000/common/au1000.o |
| 9901 | +SUBDIRS += arch/mips/au1000/pb1200 arch/mips/au1000/common |
| 9902 | +LOADADDR += 0x80100000 |
| 9903 | +endif |
| 9904 | + |
| 9905 | +ifdef CONFIG_MIPS_FICMMP |
| 9906 | +LIBS += arch/mips/au1000/ficmmp/ficmmp.o \ |
| 9907 | + arch/mips/au1000/common/au1000.o |
| 9908 | +SUBDIRS += arch/mips/au1000/ficmmp arch/mips/au1000/common |
| 9909 | +LOADADDR += 0x80100000 |
| 9910 | +endif |
| 9911 | + |
| 9912 | |
| 9913 | # |
| 9914 | # Cogent CSB250 |
| 9915 | --- a/arch/mips/mm/cerr-sb1.c |
| 9916 | +++ b/arch/mips/mm/cerr-sb1.c |
| 9917 | @@ -252,14 +252,14 @@ static const uint8_t parity[256] = { |
| 9918 | |
| 9919 | /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ |
| 9920 | static const uint64_t mask_72_64[8] = { |
| 9921 | - 0x0738C808099264FFL, |
| 9922 | - 0x38C808099264FF07L, |
| 9923 | - 0xC808099264FF0738L, |
| 9924 | - 0x08099264FF0738C8L, |
| 9925 | - 0x099264FF0738C808L, |
| 9926 | - 0x9264FF0738C80809L, |
| 9927 | - 0x64FF0738C8080992L, |
| 9928 | - 0xFF0738C808099264L |
| 9929 | + 0x0738C808099264FFULL, |
| 9930 | + 0x38C808099264FF07ULL, |
| 9931 | + 0xC808099264FF0738ULL, |
| 9932 | + 0x08099264FF0738C8ULL, |
| 9933 | + 0x099264FF0738C808ULL, |
| 9934 | + 0x9264FF0738C80809ULL, |
| 9935 | + 0x64FF0738C8080992ULL, |
| 9936 | + 0xFF0738C808099264ULL |
| 9937 | }; |
| 9938 | |
| 9939 | /* Calculate the parity on a range of bits */ |
| 9940 | @@ -331,9 +331,9 @@ static uint32_t extract_ic(unsigned shor |
| 9941 | ((lru >> 4) & 0x3), |
| 9942 | ((lru >> 6) & 0x3)); |
| 9943 | } |
| 9944 | - va = (taglo & 0xC0000FFFFFFFE000) | addr; |
| 9945 | + va = (taglo & 0xC0000FFFFFFFE000ULL) | addr; |
| 9946 | if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) |
| 9947 | - va |= 0x3FFFF00000000000; |
| 9948 | + va |= 0x3FFFF00000000000ULL; |
| 9949 | valid = ((taghi >> 29) & 1); |
| 9950 | if (valid) { |
| 9951 | tlo_tmp = taglo & 0xfff3ff; |
| 9952 | @@ -474,7 +474,7 @@ static uint32_t extract_dc(unsigned shor |
| 9953 | : "r" ((way << 13) | addr)); |
| 9954 | |
| 9955 | taglo = ((unsigned long long)taglohi << 32) | taglolo; |
| 9956 | - pa = (taglo & 0xFFFFFFE000) | addr; |
| 9957 | + pa = (taglo & 0xFFFFFFE000ULL) | addr; |
| 9958 | if (way == 0) { |
| 9959 | lru = (taghi >> 14) & 0xff; |
| 9960 | prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", |
| 9961 | --- a/arch/mips/mm/c-r4k.c |
| 9962 | +++ b/arch/mips/mm/c-r4k.c |
| 9963 | @@ -867,9 +867,16 @@ static void __init probe_pcache(void) |
| 9964 | * normally they'd suffer from aliases but magic in the hardware deals |
| 9965 | * with that for us so we don't need to take care ourselves. |
| 9966 | */ |
| 9967 | - if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) |
| 9968 | - if (c->dcache.waysize > PAGE_SIZE) |
| 9969 | - c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 9970 | + switch (c->cputype) { |
| 9971 | + case CPU_R10000: |
| 9972 | + case CPU_R12000: |
| 9973 | + break; |
| 9974 | + case CPU_24K: |
| 9975 | + if (!(read_c0_config7() & (1 << 16))) |
| 9976 | + default: |
| 9977 | + if (c->dcache.waysize > PAGE_SIZE) |
| 9978 | + c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 9979 | + } |
| 9980 | |
| 9981 | switch (c->cputype) { |
| 9982 | case CPU_20KC: |
| 9983 | @@ -1069,9 +1076,6 @@ void __init ld_mmu_r4xx0(void) |
| 9984 | probe_pcache(); |
| 9985 | setup_scache(); |
| 9986 | |
| 9987 | - if (c->dcache.sets * c->dcache.ways > PAGE_SIZE) |
| 9988 | - c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 9989 | - |
| 9990 | r4k_blast_dcache_page_setup(); |
| 9991 | r4k_blast_dcache_page_indexed_setup(); |
| 9992 | r4k_blast_dcache_setup(); |
| 9993 | --- a/arch/mips/mm/tlbex-mips32.S |
| 9994 | +++ b/arch/mips/mm/tlbex-mips32.S |
| 9995 | @@ -196,7 +196,7 @@ |
| 9996 | .set noat; \ |
| 9997 | SAVE_ALL; \ |
| 9998 | mfc0 a2, CP0_BADVADDR; \ |
| 9999 | - STI; \ |
| 10000 | + KMODE; \ |
| 10001 | .set at; \ |
| 10002 | move a0, sp; \ |
| 10003 | jal do_page_fault; \ |
| 10004 | --- a/arch/mips/mm/tlbex-r4k.S |
| 10005 | +++ b/arch/mips/mm/tlbex-r4k.S |
| 10006 | @@ -184,13 +184,10 @@ |
| 10007 | P_MTC0 k0, CP0_ENTRYLO0 # load it |
| 10008 | PTE_SRL k1, k1, 6 # convert to entrylo1 |
| 10009 | P_MTC0 k1, CP0_ENTRYLO1 # load it |
| 10010 | - b 1f |
| 10011 | - rm9000_tlb_hazard |
| 10012 | + mtc0_tlbw_hazard |
| 10013 | tlbwr # write random tlb entry |
| 10014 | -1: |
| 10015 | - nop |
| 10016 | - rm9000_tlb_hazard |
| 10017 | - eret # return from trap |
| 10018 | + tlbw_eret_hazard |
| 10019 | + eret |
| 10020 | END(except_vec0_r4000) |
| 10021 | |
| 10022 | /* TLB refill, EXL == 0, R4600 version */ |
| 10023 | @@ -468,13 +465,9 @@ invalid_tlbl: |
| 10024 | PTE_PRESENT(k0, k1, nopage_tlbl) |
| 10025 | PTE_MAKEVALID(k0, k1) |
| 10026 | PTE_RELOAD(k1, k0) |
| 10027 | - rm9000_tlb_hazard |
| 10028 | - nop |
| 10029 | - b 1f |
| 10030 | - tlbwi |
| 10031 | -1: |
| 10032 | - nop |
| 10033 | - rm9000_tlb_hazard |
| 10034 | + mtc0_tlbw_hazard |
| 10035 | + tlbwi |
| 10036 | + tlbw_eret_hazard |
| 10037 | .set mips3 |
| 10038 | eret |
| 10039 | .set mips0 |
| 10040 | @@ -496,13 +489,9 @@ nopage_tlbl: |
| 10041 | PTE_WRITABLE(k0, k1, nopage_tlbs) |
| 10042 | PTE_MAKEWRITE(k0, k1) |
| 10043 | PTE_RELOAD(k1, k0) |
| 10044 | - rm9000_tlb_hazard |
| 10045 | - nop |
| 10046 | - b 1f |
| 10047 | - tlbwi |
| 10048 | -1: |
| 10049 | - nop |
| 10050 | - rm9000_tlb_hazard |
| 10051 | + mtc0_tlbw_hazard |
| 10052 | + tlbwi |
| 10053 | + tlbw_eret_hazard |
| 10054 | .set mips3 |
| 10055 | eret |
| 10056 | .set mips0 |
| 10057 | @@ -529,13 +518,9 @@ nopage_tlbs: |
| 10058 | |
| 10059 | /* Now reload the entry into the tlb. */ |
| 10060 | PTE_RELOAD(k1, k0) |
| 10061 | - rm9000_tlb_hazard |
| 10062 | - nop |
| 10063 | - b 1f |
| 10064 | - tlbwi |
| 10065 | -1: |
| 10066 | - rm9000_tlb_hazard |
| 10067 | - nop |
| 10068 | + mtc0_tlbw_hazard |
| 10069 | + tlbwi |
| 10070 | + tlbw_eret_hazard |
| 10071 | .set mips3 |
| 10072 | eret |
| 10073 | .set mips0 |
| 10074 | --- a/arch/mips/mm/tlb-r4k.c |
| 10075 | +++ b/arch/mips/mm/tlb-r4k.c |
| 10076 | @@ -3,17 +3,12 @@ |
| 10077 | * License. See the file "COPYING" in the main directory of this archive |
| 10078 | * for more details. |
| 10079 | * |
| 10080 | - * r4xx0.c: R4000 processor variant specific MMU/Cache routines. |
| 10081 | - * |
| 10082 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) |
| 10083 | * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org |
| 10084 | - * |
| 10085 | - * To do: |
| 10086 | - * |
| 10087 | - * - this code is a overbloated pig |
| 10088 | - * - many of the bug workarounds are not efficient at all, but at |
| 10089 | - * least they are functional ... |
| 10090 | + * Carsten Langgaard, carstenl@mips.com |
| 10091 | + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. |
| 10092 | */ |
| 10093 | +#include <linux/config.h> |
| 10094 | #include <linux/init.h> |
| 10095 | #include <linux/sched.h> |
| 10096 | #include <linux/mm.h> |
| 10097 | @@ -25,9 +20,6 @@ |
| 10098 | #include <asm/pgtable.h> |
| 10099 | #include <asm/system.h> |
| 10100 | |
| 10101 | -#undef DEBUG_TLB |
| 10102 | -#undef DEBUG_TLBUPDATE |
| 10103 | - |
| 10104 | extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600; |
| 10105 | |
| 10106 | /* CP0 hazard avoidance. */ |
| 10107 | @@ -41,33 +33,23 @@ void local_flush_tlb_all(void) |
| 10108 | unsigned long old_ctx; |
| 10109 | int entry; |
| 10110 | |
| 10111 | -#ifdef DEBUG_TLB |
| 10112 | - printk("[tlball]"); |
| 10113 | -#endif |
| 10114 | - |
| 10115 | local_irq_save(flags); |
| 10116 | /* Save old context and create impossible VPN2 value */ |
| 10117 | old_ctx = read_c0_entryhi(); |
| 10118 | write_c0_entrylo0(0); |
| 10119 | write_c0_entrylo1(0); |
| 10120 | - BARRIER; |
| 10121 | |
| 10122 | entry = read_c0_wired(); |
| 10123 | |
| 10124 | /* Blast 'em all away. */ |
| 10125 | while (entry < current_cpu_data.tlbsize) { |
| 10126 | - /* |
| 10127 | - * Make sure all entries differ. If they're not different |
| 10128 | - * MIPS32 will take revenge ... |
| 10129 | - */ |
| 10130 | write_c0_entryhi(KSEG0 + entry*0x2000); |
| 10131 | write_c0_index(entry); |
| 10132 | - BARRIER; |
| 10133 | + mtc0_tlbw_hazard(); |
| 10134 | tlb_write_indexed(); |
| 10135 | - BARRIER; |
| 10136 | entry++; |
| 10137 | } |
| 10138 | - BARRIER; |
| 10139 | + tlbw_use_hazard(); |
| 10140 | write_c0_entryhi(old_ctx); |
| 10141 | local_irq_restore(flags); |
| 10142 | } |
| 10143 | @@ -76,12 +58,8 @@ void local_flush_tlb_mm(struct mm_struct |
| 10144 | { |
| 10145 | int cpu = smp_processor_id(); |
| 10146 | |
| 10147 | - if (cpu_context(cpu, mm) != 0) { |
| 10148 | -#ifdef DEBUG_TLB |
| 10149 | - printk("[tlbmm<%d>]", cpu_context(cpu, mm)); |
| 10150 | -#endif |
| 10151 | + if (cpu_context(cpu, mm) != 0) |
| 10152 | drop_mmu_context(mm,cpu); |
| 10153 | - } |
| 10154 | } |
| 10155 | |
| 10156 | void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, |
| 10157 | @@ -93,10 +71,6 @@ void local_flush_tlb_range(struct mm_str |
| 10158 | unsigned long flags; |
| 10159 | int size; |
| 10160 | |
| 10161 | -#ifdef DEBUG_TLB |
| 10162 | - printk("[tlbrange<%02x,%08lx,%08lx>]", |
| 10163 | - cpu_asid(cpu, mm), start, end); |
| 10164 | -#endif |
| 10165 | local_irq_save(flags); |
| 10166 | size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
| 10167 | size = (size + 1) >> 1; |
| 10168 | @@ -112,7 +86,7 @@ void local_flush_tlb_range(struct mm_str |
| 10169 | |
| 10170 | write_c0_entryhi(start | newpid); |
| 10171 | start += (PAGE_SIZE << 1); |
| 10172 | - BARRIER; |
| 10173 | + mtc0_tlbw_hazard(); |
| 10174 | tlb_probe(); |
| 10175 | BARRIER; |
| 10176 | idx = read_c0_index(); |
| 10177 | @@ -122,10 +96,10 @@ void local_flush_tlb_range(struct mm_str |
| 10178 | continue; |
| 10179 | /* Make sure all entries differ. */ |
| 10180 | write_c0_entryhi(KSEG0 + idx*0x2000); |
| 10181 | - BARRIER; |
| 10182 | + mtc0_tlbw_hazard(); |
| 10183 | tlb_write_indexed(); |
| 10184 | - BARRIER; |
| 10185 | } |
| 10186 | + tlbw_use_hazard(); |
| 10187 | write_c0_entryhi(oldpid); |
| 10188 | } else { |
| 10189 | drop_mmu_context(mm, cpu); |
| 10190 | @@ -138,34 +112,30 @@ void local_flush_tlb_page(struct vm_area |
| 10191 | { |
| 10192 | int cpu = smp_processor_id(); |
| 10193 | |
| 10194 | - if (!vma || cpu_context(cpu, vma->vm_mm) != 0) { |
| 10195 | + if (cpu_context(cpu, vma->vm_mm) != 0) { |
| 10196 | unsigned long flags; |
| 10197 | - int oldpid, newpid, idx; |
| 10198 | + unsigned long oldpid, newpid, idx; |
| 10199 | |
| 10200 | -#ifdef DEBUG_TLB |
| 10201 | - printk("[tlbpage<%d,%08lx>]", cpu_context(cpu, vma->vm_mm), |
| 10202 | - page); |
| 10203 | -#endif |
| 10204 | newpid = cpu_asid(cpu, vma->vm_mm); |
| 10205 | page &= (PAGE_MASK << 1); |
| 10206 | local_irq_save(flags); |
| 10207 | oldpid = read_c0_entryhi(); |
| 10208 | write_c0_entryhi(page | newpid); |
| 10209 | - BARRIER; |
| 10210 | + mtc0_tlbw_hazard(); |
| 10211 | tlb_probe(); |
| 10212 | BARRIER; |
| 10213 | idx = read_c0_index(); |
| 10214 | write_c0_entrylo0(0); |
| 10215 | write_c0_entrylo1(0); |
| 10216 | - if(idx < 0) |
| 10217 | + if (idx < 0) |
| 10218 | goto finish; |
| 10219 | /* Make sure all entries differ. */ |
| 10220 | write_c0_entryhi(KSEG0+idx*0x2000); |
| 10221 | - BARRIER; |
| 10222 | + mtc0_tlbw_hazard(); |
| 10223 | tlb_write_indexed(); |
| 10224 | + tlbw_use_hazard(); |
| 10225 | |
| 10226 | finish: |
| 10227 | - BARRIER; |
| 10228 | write_c0_entryhi(oldpid); |
| 10229 | local_irq_restore(flags); |
| 10230 | } |
| 10231 | @@ -185,7 +155,7 @@ void local_flush_tlb_one(unsigned long p |
| 10232 | |
| 10233 | local_irq_save(flags); |
| 10234 | write_c0_entryhi(page); |
| 10235 | - BARRIER; |
| 10236 | + mtc0_tlbw_hazard(); |
| 10237 | tlb_probe(); |
| 10238 | BARRIER; |
| 10239 | idx = read_c0_index(); |
| 10240 | @@ -194,18 +164,19 @@ void local_flush_tlb_one(unsigned long p |
| 10241 | if (idx >= 0) { |
| 10242 | /* Make sure all entries differ. */ |
| 10243 | write_c0_entryhi(KSEG0+idx*0x2000); |
| 10244 | + mtc0_tlbw_hazard(); |
| 10245 | tlb_write_indexed(); |
| 10246 | + tlbw_use_hazard(); |
| 10247 | } |
| 10248 | - BARRIER; |
| 10249 | write_c0_entryhi(oldpid); |
| 10250 | + |
| 10251 | local_irq_restore(flags); |
| 10252 | } |
| 10253 | |
| 10254 | EXPORT_SYMBOL(local_flush_tlb_one); |
| 10255 | |
| 10256 | -/* We will need multiple versions of update_mmu_cache(), one that just |
| 10257 | - * updates the TLB with the new pte(s), and another which also checks |
| 10258 | - * for the R4k "end of page" hardware bug and does the needy. |
| 10259 | +/* |
| 10260 | + * Updates the TLB with the new pte(s). |
| 10261 | */ |
| 10262 | void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) |
| 10263 | { |
| 10264 | @@ -223,25 +194,16 @@ void __update_tlb(struct vm_area_struct |
| 10265 | |
| 10266 | pid = read_c0_entryhi() & ASID_MASK; |
| 10267 | |
| 10268 | -#ifdef DEBUG_TLB |
| 10269 | - if ((pid != cpu_asid(cpu, vma->vm_mm)) || |
| 10270 | - (cpu_context(vma->vm_mm) == 0)) { |
| 10271 | - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d " |
| 10272 | - "tlbpid=%d\n", (int) (cpu_asid(cpu, vma->vm_mm)), pid); |
| 10273 | - } |
| 10274 | -#endif |
| 10275 | - |
| 10276 | local_irq_save(flags); |
| 10277 | address &= (PAGE_MASK << 1); |
| 10278 | write_c0_entryhi(address | pid); |
| 10279 | pgdp = pgd_offset(vma->vm_mm, address); |
| 10280 | - BARRIER; |
| 10281 | + mtc0_tlbw_hazard(); |
| 10282 | tlb_probe(); |
| 10283 | BARRIER; |
| 10284 | pmdp = pmd_offset(pgdp, address); |
| 10285 | idx = read_c0_index(); |
| 10286 | ptep = pte_offset(pmdp, address); |
| 10287 | - BARRIER; |
| 10288 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
| 10289 | write_c0_entrylo0(ptep->pte_high); |
| 10290 | ptep++; |
| 10291 | @@ -251,15 +213,13 @@ void __update_tlb(struct vm_area_struct |
| 10292 | write_c0_entrylo1(pte_val(*ptep) >> 6); |
| 10293 | #endif |
| 10294 | write_c0_entryhi(address | pid); |
| 10295 | - BARRIER; |
| 10296 | - if (idx < 0) { |
| 10297 | + mtc0_tlbw_hazard(); |
| 10298 | + if (idx < 0) |
| 10299 | tlb_write_random(); |
| 10300 | - } else { |
| 10301 | + else |
| 10302 | tlb_write_indexed(); |
| 10303 | - } |
| 10304 | - BARRIER; |
| 10305 | + tlbw_use_hazard(); |
| 10306 | write_c0_entryhi(pid); |
| 10307 | - BARRIER; |
| 10308 | local_irq_restore(flags); |
| 10309 | } |
| 10310 | |
| 10311 | @@ -279,24 +239,26 @@ static void r4k_update_mmu_cache_hwbug(s |
| 10312 | asid = read_c0_entryhi() & ASID_MASK; |
| 10313 | write_c0_entryhi(address | asid); |
| 10314 | pgdp = pgd_offset(vma->vm_mm, address); |
| 10315 | + mtc0_tlbw_hazard(); |
| 10316 | tlb_probe(); |
| 10317 | + BARRIER; |
| 10318 | pmdp = pmd_offset(pgdp, address); |
| 10319 | idx = read_c0_index(); |
| 10320 | ptep = pte_offset(pmdp, address); |
| 10321 | write_c0_entrylo0(pte_val(*ptep++) >> 6); |
| 10322 | write_c0_entrylo1(pte_val(*ptep) >> 6); |
| 10323 | - BARRIER; |
| 10324 | + mtc0_tlbw_hazard(); |
| 10325 | if (idx < 0) |
| 10326 | tlb_write_random(); |
| 10327 | else |
| 10328 | tlb_write_indexed(); |
| 10329 | - BARRIER; |
| 10330 | + tlbw_use_hazard(); |
| 10331 | local_irq_restore(flags); |
| 10332 | } |
| 10333 | #endif |
| 10334 | |
| 10335 | void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
| 10336 | - unsigned long entryhi, unsigned long pagemask) |
| 10337 | + unsigned long entryhi, unsigned long pagemask) |
| 10338 | { |
| 10339 | unsigned long flags; |
| 10340 | unsigned long wired; |
| 10341 | @@ -315,9 +277,9 @@ void __init add_wired_entry(unsigned lon |
| 10342 | write_c0_entryhi(entryhi); |
| 10343 | write_c0_entrylo0(entrylo0); |
| 10344 | write_c0_entrylo1(entrylo1); |
| 10345 | - BARRIER; |
| 10346 | + mtc0_tlbw_hazard(); |
| 10347 | tlb_write_indexed(); |
| 10348 | - BARRIER; |
| 10349 | + tlbw_use_hazard(); |
| 10350 | |
| 10351 | write_c0_entryhi(old_ctx); |
| 10352 | BARRIER; |
| 10353 | @@ -355,17 +317,15 @@ __init int add_temporary_entry(unsigned |
| 10354 | } |
| 10355 | |
| 10356 | write_c0_index(temp_tlb_entry); |
| 10357 | - BARRIER; |
| 10358 | write_c0_pagemask(pagemask); |
| 10359 | write_c0_entryhi(entryhi); |
| 10360 | write_c0_entrylo0(entrylo0); |
| 10361 | write_c0_entrylo1(entrylo1); |
| 10362 | - BARRIER; |
| 10363 | + mtc0_tlbw_hazard(); |
| 10364 | tlb_write_indexed(); |
| 10365 | - BARRIER; |
| 10366 | + tlbw_use_hazard(); |
| 10367 | |
| 10368 | write_c0_entryhi(old_ctx); |
| 10369 | - BARRIER; |
| 10370 | write_c0_pagemask(old_pagemask); |
| 10371 | out: |
| 10372 | local_irq_restore(flags); |
| 10373 | @@ -375,7 +335,7 @@ out: |
| 10374 | static void __init probe_tlb(unsigned long config) |
| 10375 | { |
| 10376 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 10377 | - unsigned int reg; |
| 10378 | + unsigned int config1; |
| 10379 | |
| 10380 | /* |
| 10381 | * If this isn't a MIPS32 / MIPS64 compliant CPU. Config 1 register |
| 10382 | @@ -385,16 +345,16 @@ static void __init probe_tlb(unsigned lo |
| 10383 | if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) |
| 10384 | return; |
| 10385 | |
| 10386 | - reg = read_c0_config1(); |
| 10387 | + config1 = read_c0_config1(); |
| 10388 | if (!((config >> 7) & 3)) |
| 10389 | panic("No TLB present"); |
| 10390 | |
| 10391 | - c->tlbsize = ((reg >> 25) & 0x3f) + 1; |
| 10392 | + c->tlbsize = ((config1 >> 25) & 0x3f) + 1; |
| 10393 | } |
| 10394 | |
| 10395 | void __init r4k_tlb_init(void) |
| 10396 | { |
| 10397 | - u32 config = read_c0_config(); |
| 10398 | + unsigned int config = read_c0_config(); |
| 10399 | |
| 10400 | /* |
| 10401 | * You should never change this register: |
| 10402 | --- a/arch/mips64/defconfig |
| 10403 | +++ b/arch/mips64/defconfig |
| 10404 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10405 | # CONFIG_MIPS_PB1000 is not set |
| 10406 | # CONFIG_MIPS_PB1100 is not set |
| 10407 | # CONFIG_MIPS_PB1500 is not set |
| 10408 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10409 | # CONFIG_MIPS_PB1550 is not set |
| 10410 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10411 | # CONFIG_MIPS_XXS1500 is not set |
| 10412 | # CONFIG_MIPS_MTX1 is not set |
| 10413 | # CONFIG_COGENT_CSB250 is not set |
| 10414 | @@ -470,9 +470,11 @@ CONFIG_SCSI_LOGGING=y |
| 10415 | # CONFIG_SCSI_MEGARAID is not set |
| 10416 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10417 | # CONFIG_SCSI_SATA is not set |
| 10418 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10419 | # CONFIG_SCSI_SATA_SVW is not set |
| 10420 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10421 | # CONFIG_SCSI_SATA_NV is not set |
| 10422 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10423 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10424 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10425 | # CONFIG_SCSI_SATA_SIL is not set |
| 10426 | @@ -658,7 +660,6 @@ CONFIG_SERIAL=y |
| 10427 | CONFIG_SERIAL_CONSOLE=y |
| 10428 | # CONFIG_SERIAL_EXTENDED is not set |
| 10429 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 10430 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10431 | CONFIG_UNIX98_PTYS=y |
| 10432 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10433 | |
| 10434 | --- a/arch/mips64/defconfig-atlas |
| 10435 | +++ b/arch/mips64/defconfig-atlas |
| 10436 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 10437 | # CONFIG_MIPS_PB1000 is not set |
| 10438 | # CONFIG_MIPS_PB1100 is not set |
| 10439 | # CONFIG_MIPS_PB1500 is not set |
| 10440 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10441 | # CONFIG_MIPS_PB1550 is not set |
| 10442 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10443 | # CONFIG_MIPS_XXS1500 is not set |
| 10444 | # CONFIG_MIPS_MTX1 is not set |
| 10445 | # CONFIG_COGENT_CSB250 is not set |
| 10446 | @@ -232,11 +232,6 @@ CONFIG_IP_PNP=y |
| 10447 | # |
| 10448 | # CONFIG_IPX is not set |
| 10449 | # CONFIG_ATALK is not set |
| 10450 | - |
| 10451 | -# |
| 10452 | -# Appletalk devices |
| 10453 | -# |
| 10454 | -# CONFIG_DEV_APPLETALK is not set |
| 10455 | # CONFIG_DECNET is not set |
| 10456 | # CONFIG_BRIDGE is not set |
| 10457 | # CONFIG_X25 is not set |
| 10458 | @@ -314,9 +309,11 @@ CONFIG_SD_EXTRA_DEVS=40 |
| 10459 | # CONFIG_SCSI_MEGARAID is not set |
| 10460 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10461 | # CONFIG_SCSI_SATA is not set |
| 10462 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10463 | # CONFIG_SCSI_SATA_SVW is not set |
| 10464 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10465 | # CONFIG_SCSI_SATA_NV is not set |
| 10466 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10467 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10468 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10469 | # CONFIG_SCSI_SATA_SIL is not set |
| 10470 | @@ -474,7 +471,6 @@ CONFIG_SERIAL=y |
| 10471 | CONFIG_SERIAL_CONSOLE=y |
| 10472 | # CONFIG_SERIAL_EXTENDED is not set |
| 10473 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 10474 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10475 | CONFIG_UNIX98_PTYS=y |
| 10476 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10477 | |
| 10478 | --- a/arch/mips64/defconfig-decstation |
| 10479 | +++ b/arch/mips64/defconfig-decstation |
| 10480 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 10481 | # CONFIG_MIPS_PB1000 is not set |
| 10482 | # CONFIG_MIPS_PB1100 is not set |
| 10483 | # CONFIG_MIPS_PB1500 is not set |
| 10484 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10485 | # CONFIG_MIPS_PB1550 is not set |
| 10486 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10487 | # CONFIG_MIPS_XXS1500 is not set |
| 10488 | # CONFIG_MIPS_MTX1 is not set |
| 10489 | # CONFIG_COGENT_CSB250 is not set |
| 10490 | @@ -224,11 +224,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 10491 | # |
| 10492 | # CONFIG_IPX is not set |
| 10493 | # CONFIG_ATALK is not set |
| 10494 | - |
| 10495 | -# |
| 10496 | -# Appletalk devices |
| 10497 | -# |
| 10498 | -# CONFIG_DEV_APPLETALK is not set |
| 10499 | # CONFIG_DECNET is not set |
| 10500 | # CONFIG_BRIDGE is not set |
| 10501 | # CONFIG_X25 is not set |
| 10502 | @@ -307,9 +302,11 @@ CONFIG_SCSI_DECNCR=y |
| 10503 | # CONFIG_SCSI_MEGARAID is not set |
| 10504 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10505 | # CONFIG_SCSI_SATA is not set |
| 10506 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10507 | # CONFIG_SCSI_SATA_SVW is not set |
| 10508 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10509 | # CONFIG_SCSI_SATA_NV is not set |
| 10510 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10511 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10512 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10513 | # CONFIG_SCSI_SATA_SIL is not set |
| 10514 | @@ -477,7 +474,6 @@ CONFIG_SERIAL_DEC=y |
| 10515 | CONFIG_SERIAL_DEC_CONSOLE=y |
| 10516 | # CONFIG_DZ is not set |
| 10517 | CONFIG_ZS=y |
| 10518 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10519 | CONFIG_UNIX98_PTYS=y |
| 10520 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10521 | |
| 10522 | --- a/arch/mips64/defconfig-ip22 |
| 10523 | +++ b/arch/mips64/defconfig-ip22 |
| 10524 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10525 | # CONFIG_MIPS_PB1000 is not set |
| 10526 | # CONFIG_MIPS_PB1100 is not set |
| 10527 | # CONFIG_MIPS_PB1500 is not set |
| 10528 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10529 | # CONFIG_MIPS_PB1550 is not set |
| 10530 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10531 | # CONFIG_MIPS_XXS1500 is not set |
| 10532 | # CONFIG_MIPS_MTX1 is not set |
| 10533 | # CONFIG_COGENT_CSB250 is not set |
| 10534 | @@ -235,11 +235,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 10535 | # |
| 10536 | # CONFIG_IPX is not set |
| 10537 | # CONFIG_ATALK is not set |
| 10538 | - |
| 10539 | -# |
| 10540 | -# Appletalk devices |
| 10541 | -# |
| 10542 | -# CONFIG_DEV_APPLETALK is not set |
| 10543 | # CONFIG_DECNET is not set |
| 10544 | # CONFIG_BRIDGE is not set |
| 10545 | # CONFIG_X25 is not set |
| 10546 | @@ -319,9 +314,11 @@ CONFIG_SGIWD93_SCSI=y |
| 10547 | # CONFIG_SCSI_MEGARAID is not set |
| 10548 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10549 | # CONFIG_SCSI_SATA is not set |
| 10550 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10551 | # CONFIG_SCSI_SATA_SVW is not set |
| 10552 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10553 | # CONFIG_SCSI_SATA_NV is not set |
| 10554 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10555 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10556 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10557 | # CONFIG_SCSI_SATA_SIL is not set |
| 10558 | @@ -488,7 +485,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 10559 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 10560 | # CONFIG_TXX927_SERIAL is not set |
| 10561 | CONFIG_IP22_SERIAL=y |
| 10562 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10563 | CONFIG_UNIX98_PTYS=y |
| 10564 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10565 | |
| 10566 | --- a/arch/mips64/defconfig-ip27 |
| 10567 | +++ b/arch/mips64/defconfig-ip27 |
| 10568 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10569 | # CONFIG_MIPS_PB1000 is not set |
| 10570 | # CONFIG_MIPS_PB1100 is not set |
| 10571 | # CONFIG_MIPS_PB1500 is not set |
| 10572 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10573 | # CONFIG_MIPS_PB1550 is not set |
| 10574 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10575 | # CONFIG_MIPS_XXS1500 is not set |
| 10576 | # CONFIG_MIPS_MTX1 is not set |
| 10577 | # CONFIG_COGENT_CSB250 is not set |
| 10578 | @@ -470,9 +470,11 @@ CONFIG_SCSI_LOGGING=y |
| 10579 | # CONFIG_SCSI_MEGARAID is not set |
| 10580 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10581 | # CONFIG_SCSI_SATA is not set |
| 10582 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10583 | # CONFIG_SCSI_SATA_SVW is not set |
| 10584 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10585 | # CONFIG_SCSI_SATA_NV is not set |
| 10586 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10587 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10588 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10589 | # CONFIG_SCSI_SATA_SIL is not set |
| 10590 | @@ -658,7 +660,6 @@ CONFIG_SERIAL=y |
| 10591 | CONFIG_SERIAL_CONSOLE=y |
| 10592 | # CONFIG_SERIAL_EXTENDED is not set |
| 10593 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 10594 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10595 | CONFIG_UNIX98_PTYS=y |
| 10596 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10597 | |
| 10598 | --- a/arch/mips64/defconfig-jaguar |
| 10599 | +++ b/arch/mips64/defconfig-jaguar |
| 10600 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10601 | # CONFIG_MIPS_PB1000 is not set |
| 10602 | # CONFIG_MIPS_PB1100 is not set |
| 10603 | # CONFIG_MIPS_PB1500 is not set |
| 10604 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10605 | # CONFIG_MIPS_PB1550 is not set |
| 10606 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10607 | # CONFIG_MIPS_XXS1500 is not set |
| 10608 | # CONFIG_MIPS_MTX1 is not set |
| 10609 | # CONFIG_COGENT_CSB250 is not set |
| 10610 | @@ -227,11 +227,6 @@ CONFIG_IP_PNP_DHCP=y |
| 10611 | # |
| 10612 | # CONFIG_IPX is not set |
| 10613 | # CONFIG_ATALK is not set |
| 10614 | - |
| 10615 | -# |
| 10616 | -# Appletalk devices |
| 10617 | -# |
| 10618 | -# CONFIG_DEV_APPLETALK is not set |
| 10619 | # CONFIG_DECNET is not set |
| 10620 | # CONFIG_BRIDGE is not set |
| 10621 | # CONFIG_X25 is not set |
| 10622 | @@ -403,7 +398,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 10623 | # CONFIG_SERIAL_TXX9 is not set |
| 10624 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 10625 | # CONFIG_TXX927_SERIAL is not set |
| 10626 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10627 | CONFIG_UNIX98_PTYS=y |
| 10628 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10629 | |
| 10630 | --- a/arch/mips64/defconfig-malta |
| 10631 | +++ b/arch/mips64/defconfig-malta |
| 10632 | @@ -22,16 +22,19 @@ CONFIG_KMOD=y |
| 10633 | # |
| 10634 | # CONFIG_ACER_PICA_61 is not set |
| 10635 | # CONFIG_MIPS_BOSPORUS is not set |
| 10636 | +# CONFIG_MIPS_FICMMP is not set |
| 10637 | # CONFIG_MIPS_MIRAGE is not set |
| 10638 | # CONFIG_MIPS_DB1000 is not set |
| 10639 | # CONFIG_MIPS_DB1100 is not set |
| 10640 | # CONFIG_MIPS_DB1500 is not set |
| 10641 | # CONFIG_MIPS_DB1550 is not set |
| 10642 | +# CONFIG_MIPS_DB1200 is not set |
| 10643 | # CONFIG_MIPS_PB1000 is not set |
| 10644 | # CONFIG_MIPS_PB1100 is not set |
| 10645 | # CONFIG_MIPS_PB1500 is not set |
| 10646 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10647 | # CONFIG_MIPS_PB1550 is not set |
| 10648 | +# CONFIG_MIPS_PB1200 is not set |
| 10649 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10650 | # CONFIG_MIPS_XXS1500 is not set |
| 10651 | # CONFIG_MIPS_MTX1 is not set |
| 10652 | # CONFIG_COGENT_CSB250 is not set |
| 10653 | @@ -146,9 +149,9 @@ CONFIG_KCORE_ELF=y |
| 10654 | CONFIG_BINFMT_ELF=y |
| 10655 | CONFIG_MIPS32_COMPAT=y |
| 10656 | CONFIG_MIPS32_O32=y |
| 10657 | -# CONFIG_MIPS32_N32 is not set |
| 10658 | +CONFIG_MIPS32_N32=y |
| 10659 | CONFIG_BINFMT_ELF32=y |
| 10660 | -# CONFIG_BINFMT_MISC is not set |
| 10661 | +CONFIG_BINFMT_MISC=y |
| 10662 | # CONFIG_OOM_KILLER is not set |
| 10663 | # CONFIG_CMDLINE_BOOL is not set |
| 10664 | |
| 10665 | @@ -235,11 +238,6 @@ CONFIG_IP_PNP_BOOTP=y |
| 10666 | # |
| 10667 | # CONFIG_IPX is not set |
| 10668 | # CONFIG_ATALK is not set |
| 10669 | - |
| 10670 | -# |
| 10671 | -# Appletalk devices |
| 10672 | -# |
| 10673 | -# CONFIG_DEV_APPLETALK is not set |
| 10674 | # CONFIG_DECNET is not set |
| 10675 | # CONFIG_BRIDGE is not set |
| 10676 | # CONFIG_X25 is not set |
| 10677 | @@ -271,8 +269,83 @@ CONFIG_IP_PNP_BOOTP=y |
| 10678 | # |
| 10679 | # ATA/IDE/MFM/RLL support |
| 10680 | # |
| 10681 | -# CONFIG_IDE is not set |
| 10682 | +CONFIG_IDE=y |
| 10683 | + |
| 10684 | +# |
| 10685 | +# IDE, ATA and ATAPI Block devices |
| 10686 | +# |
| 10687 | +CONFIG_BLK_DEV_IDE=y |
| 10688 | + |
| 10689 | +# |
| 10690 | +# Please see Documentation/ide.txt for help/info on IDE drives |
| 10691 | +# |
| 10692 | +# CONFIG_BLK_DEV_HD_IDE is not set |
| 10693 | # CONFIG_BLK_DEV_HD is not set |
| 10694 | +# CONFIG_BLK_DEV_IDE_SATA is not set |
| 10695 | +CONFIG_BLK_DEV_IDEDISK=y |
| 10696 | +# CONFIG_IDEDISK_MULTI_MODE is not set |
| 10697 | +# CONFIG_IDEDISK_STROKE is not set |
| 10698 | +# CONFIG_BLK_DEV_IDECS is not set |
| 10699 | +# CONFIG_BLK_DEV_DELKIN is not set |
| 10700 | +CONFIG_BLK_DEV_IDECD=y |
| 10701 | +CONFIG_BLK_DEV_IDETAPE=y |
| 10702 | +CONFIG_BLK_DEV_IDEFLOPPY=y |
| 10703 | +# CONFIG_BLK_DEV_IDESCSI is not set |
| 10704 | +# CONFIG_IDE_TASK_IOCTL is not set |
| 10705 | + |
| 10706 | +# |
| 10707 | +# IDE chipset support/bugfixes |
| 10708 | +# |
| 10709 | +# CONFIG_BLK_DEV_CMD640 is not set |
| 10710 | +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set |
| 10711 | +# CONFIG_BLK_DEV_ISAPNP is not set |
| 10712 | +CONFIG_BLK_DEV_IDEPCI=y |
| 10713 | +CONFIG_BLK_DEV_GENERIC=y |
| 10714 | +CONFIG_IDEPCI_SHARE_IRQ=y |
| 10715 | +CONFIG_BLK_DEV_IDEDMA_PCI=y |
| 10716 | +# CONFIG_BLK_DEV_OFFBOARD is not set |
| 10717 | +CONFIG_BLK_DEV_IDEDMA_FORCED=y |
| 10718 | +CONFIG_IDEDMA_PCI_AUTO=y |
| 10719 | +# CONFIG_IDEDMA_ONLYDISK is not set |
| 10720 | +CONFIG_BLK_DEV_IDEDMA=y |
| 10721 | +# CONFIG_IDEDMA_PCI_WIP is not set |
| 10722 | +# CONFIG_BLK_DEV_ADMA100 is not set |
| 10723 | +# CONFIG_BLK_DEV_AEC62XX is not set |
| 10724 | +# CONFIG_BLK_DEV_ALI15X3 is not set |
| 10725 | +# CONFIG_WDC_ALI15X3 is not set |
| 10726 | +# CONFIG_BLK_DEV_AMD74XX is not set |
| 10727 | +# CONFIG_AMD74XX_OVERRIDE is not set |
| 10728 | +# CONFIG_BLK_DEV_ATIIXP is not set |
| 10729 | +# CONFIG_BLK_DEV_CMD64X is not set |
| 10730 | +# CONFIG_BLK_DEV_TRIFLEX is not set |
| 10731 | +# CONFIG_BLK_DEV_CY82C693 is not set |
| 10732 | +# CONFIG_BLK_DEV_CS5530 is not set |
| 10733 | +# CONFIG_BLK_DEV_HPT34X is not set |
| 10734 | +# CONFIG_HPT34X_AUTODMA is not set |
| 10735 | +# CONFIG_BLK_DEV_HPT366 is not set |
| 10736 | +CONFIG_BLK_DEV_PIIX=y |
| 10737 | +# CONFIG_BLK_DEV_NS87415 is not set |
| 10738 | +# CONFIG_BLK_DEV_OPTI621 is not set |
| 10739 | +# CONFIG_BLK_DEV_PDC202XX_OLD is not set |
| 10740 | +# CONFIG_PDC202XX_BURST is not set |
| 10741 | +# CONFIG_BLK_DEV_PDC202XX_NEW is not set |
| 10742 | +# CONFIG_BLK_DEV_RZ1000 is not set |
| 10743 | +# CONFIG_BLK_DEV_SC1200 is not set |
| 10744 | +# CONFIG_BLK_DEV_SVWKS is not set |
| 10745 | +# CONFIG_BLK_DEV_SIIMAGE is not set |
| 10746 | +# CONFIG_BLK_DEV_SIS5513 is not set |
| 10747 | +# CONFIG_BLK_DEV_SLC90E66 is not set |
| 10748 | +# CONFIG_BLK_DEV_TRM290 is not set |
| 10749 | +# CONFIG_BLK_DEV_VIA82CXXX is not set |
| 10750 | +# CONFIG_IDE_CHIPSETS is not set |
| 10751 | +CONFIG_IDEDMA_AUTO=y |
| 10752 | +# CONFIG_IDEDMA_IVB is not set |
| 10753 | +# CONFIG_DMA_NONPCI is not set |
| 10754 | +# CONFIG_BLK_DEV_ATARAID is not set |
| 10755 | +# CONFIG_BLK_DEV_ATARAID_PDC is not set |
| 10756 | +# CONFIG_BLK_DEV_ATARAID_HPT is not set |
| 10757 | +# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set |
| 10758 | +# CONFIG_BLK_DEV_ATARAID_SII is not set |
| 10759 | |
| 10760 | # |
| 10761 | # SCSI support |
| 10762 | @@ -317,9 +390,11 @@ CONFIG_SD_EXTRA_DEVS=40 |
| 10763 | # CONFIG_SCSI_MEGARAID is not set |
| 10764 | # CONFIG_SCSI_MEGARAID2 is not set |
| 10765 | # CONFIG_SCSI_SATA is not set |
| 10766 | +# CONFIG_SCSI_SATA_AHCI is not set |
| 10767 | # CONFIG_SCSI_SATA_SVW is not set |
| 10768 | # CONFIG_SCSI_ATA_PIIX is not set |
| 10769 | # CONFIG_SCSI_SATA_NV is not set |
| 10770 | +# CONFIG_SCSI_SATA_QSTOR is not set |
| 10771 | # CONFIG_SCSI_SATA_PROMISE is not set |
| 10772 | # CONFIG_SCSI_SATA_SX4 is not set |
| 10773 | # CONFIG_SCSI_SATA_SIL is not set |
| 10774 | @@ -477,7 +552,6 @@ CONFIG_SERIAL=y |
| 10775 | CONFIG_SERIAL_CONSOLE=y |
| 10776 | # CONFIG_SERIAL_EXTENDED is not set |
| 10777 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 10778 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10779 | CONFIG_UNIX98_PTYS=y |
| 10780 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10781 | |
| 10782 | --- a/arch/mips64/defconfig-ocelotc |
| 10783 | +++ b/arch/mips64/defconfig-ocelotc |
| 10784 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10785 | # CONFIG_MIPS_PB1000 is not set |
| 10786 | # CONFIG_MIPS_PB1100 is not set |
| 10787 | # CONFIG_MIPS_PB1500 is not set |
| 10788 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10789 | # CONFIG_MIPS_PB1550 is not set |
| 10790 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10791 | # CONFIG_MIPS_XXS1500 is not set |
| 10792 | # CONFIG_MIPS_MTX1 is not set |
| 10793 | # CONFIG_COGENT_CSB250 is not set |
| 10794 | @@ -231,11 +231,6 @@ CONFIG_IP_PNP_DHCP=y |
| 10795 | # |
| 10796 | # CONFIG_IPX is not set |
| 10797 | # CONFIG_ATALK is not set |
| 10798 | - |
| 10799 | -# |
| 10800 | -# Appletalk devices |
| 10801 | -# |
| 10802 | -# CONFIG_DEV_APPLETALK is not set |
| 10803 | # CONFIG_DECNET is not set |
| 10804 | # CONFIG_BRIDGE is not set |
| 10805 | # CONFIG_X25 is not set |
| 10806 | @@ -453,7 +448,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 10807 | # CONFIG_SERIAL_TXX9 is not set |
| 10808 | # CONFIG_SERIAL_TXX9_CONSOLE is not set |
| 10809 | # CONFIG_TXX927_SERIAL is not set |
| 10810 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10811 | CONFIG_UNIX98_PTYS=y |
| 10812 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10813 | |
| 10814 | --- a/arch/mips64/defconfig-sb1250-swarm |
| 10815 | +++ b/arch/mips64/defconfig-sb1250-swarm |
| 10816 | @@ -30,8 +30,8 @@ CONFIG_KMOD=y |
| 10817 | # CONFIG_MIPS_PB1000 is not set |
| 10818 | # CONFIG_MIPS_PB1100 is not set |
| 10819 | # CONFIG_MIPS_PB1500 is not set |
| 10820 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10821 | # CONFIG_MIPS_PB1550 is not set |
| 10822 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10823 | # CONFIG_MIPS_XXS1500 is not set |
| 10824 | # CONFIG_MIPS_MTX1 is not set |
| 10825 | # CONFIG_COGENT_CSB250 is not set |
| 10826 | @@ -90,6 +90,7 @@ CONFIG_SIBYTE_CFE=y |
| 10827 | # CONFIG_SIBYTE_TBPROF is not set |
| 10828 | CONFIG_SIBYTE_GENBUS_IDE=y |
| 10829 | CONFIG_SMP_CAPABLE=y |
| 10830 | +CONFIG_MIPS_RTC=y |
| 10831 | # CONFIG_SNI_RM200_PCI is not set |
| 10832 | # CONFIG_TANBAC_TB0226 is not set |
| 10833 | # CONFIG_TANBAC_TB0229 is not set |
| 10834 | @@ -253,11 +254,6 @@ CONFIG_INET=y |
| 10835 | # |
| 10836 | # CONFIG_IPX is not set |
| 10837 | # CONFIG_ATALK is not set |
| 10838 | - |
| 10839 | -# |
| 10840 | -# Appletalk devices |
| 10841 | -# |
| 10842 | -# CONFIG_DEV_APPLETALK is not set |
| 10843 | # CONFIG_DECNET is not set |
| 10844 | # CONFIG_BRIDGE is not set |
| 10845 | # CONFIG_X25 is not set |
| 10846 | @@ -432,7 +428,6 @@ CONFIG_SERIAL_NONSTANDARD=y |
| 10847 | CONFIG_SIBYTE_SB1250_DUART=y |
| 10848 | CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y |
| 10849 | CONFIG_SERIAL_CONSOLE=y |
| 10850 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10851 | CONFIG_UNIX98_PTYS=y |
| 10852 | CONFIG_UNIX98_PTY_COUNT=256 |
| 10853 | |
| 10854 | --- a/arch/mips64/defconfig-sead |
| 10855 | +++ b/arch/mips64/defconfig-sead |
| 10856 | @@ -28,8 +28,8 @@ CONFIG_EXPERIMENTAL=y |
| 10857 | # CONFIG_MIPS_PB1000 is not set |
| 10858 | # CONFIG_MIPS_PB1100 is not set |
| 10859 | # CONFIG_MIPS_PB1500 is not set |
| 10860 | -# CONFIG_MIPS_HYDROGEN3 is not set |
| 10861 | # CONFIG_MIPS_PB1550 is not set |
| 10862 | +# CONFIG_MIPS_HYDROGEN3 is not set |
| 10863 | # CONFIG_MIPS_XXS1500 is not set |
| 10864 | # CONFIG_MIPS_MTX1 is not set |
| 10865 | # CONFIG_COGENT_CSB250 is not set |
| 10866 | @@ -242,7 +242,6 @@ CONFIG_SERIAL=y |
| 10867 | CONFIG_SERIAL_CONSOLE=y |
| 10868 | # CONFIG_SERIAL_EXTENDED is not set |
| 10869 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 10870 | -# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set |
| 10871 | # CONFIG_UNIX98_PTYS is not set |
| 10872 | |
| 10873 | # |
| 10874 | --- a/arch/mips64/kernel/binfmt_elfn32.c |
| 10875 | +++ b/arch/mips64/kernel/binfmt_elfn32.c |
| 10876 | @@ -116,4 +116,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux- |
| 10877 | #undef MODULE_DESCRIPTION |
| 10878 | #undef MODULE_AUTHOR |
| 10879 | |
| 10880 | +#undef TASK_SIZE |
| 10881 | +#define TASK_SIZE TASK_SIZE32 |
| 10882 | + |
| 10883 | #include "../../../fs/binfmt_elf.c" |
| 10884 | --- a/arch/mips64/kernel/binfmt_elfo32.c |
| 10885 | +++ b/arch/mips64/kernel/binfmt_elfo32.c |
| 10886 | @@ -137,4 +137,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux- |
| 10887 | #undef MODULE_DESCRIPTION |
| 10888 | #undef MODULE_AUTHOR |
| 10889 | |
| 10890 | +#undef TASK_SIZE |
| 10891 | +#define TASK_SIZE TASK_SIZE32 |
| 10892 | + |
| 10893 | #include "../../../fs/binfmt_elf.c" |
| 10894 | --- a/arch/mips64/kernel/head.S |
| 10895 | +++ b/arch/mips64/kernel/head.S |
| 10896 | @@ -91,6 +91,21 @@ EXPORT(_stext) |
| 10897 | __INIT |
| 10898 | |
| 10899 | NESTED(kernel_entry, 16, sp) # kernel entry point |
| 10900 | + .set push |
| 10901 | + /* |
| 10902 | + * For the moment disable interrupts, mark the kernel mode and |
| 10903 | + * set ST0_KX so that the CPU does not spit fire when using |
| 10904 | + * 64-bit addresses. A full initialization of the CPU's status |
| 10905 | + * register is done later in per_cpu_trap_init(). |
| 10906 | + */ |
| 10907 | + mfc0 t0, CP0_STATUS |
| 10908 | + or t0, ST0_CU0|ST0_KX|0x1f |
| 10909 | + xor t0, 0x1f |
| 10910 | + mtc0 t0, CP0_STATUS |
| 10911 | + |
| 10912 | + .set noreorder |
| 10913 | + sll zero,3 # ehb |
| 10914 | + .set reorder |
| 10915 | |
| 10916 | ori sp, 0xf # align stack on 16 byte. |
| 10917 | xori sp, 0xf |
| 10918 | @@ -103,8 +118,6 @@ NESTED(kernel_entry, 16, sp) # kernel |
| 10919 | |
| 10920 | ARC64_TWIDDLE_PC |
| 10921 | |
| 10922 | - CLI # disable interrupts |
| 10923 | - |
| 10924 | /* |
| 10925 | * The firmware/bootloader passes argc/argp/envp |
| 10926 | * to us as arguments. But clear bss first because |
| 10927 | @@ -125,6 +138,7 @@ NESTED(kernel_entry, 16, sp) # kernel |
| 10928 | dsubu sp, 4*SZREG # init stack pointer |
| 10929 | |
| 10930 | j init_arch |
| 10931 | + .set pop |
| 10932 | END(kernel_entry) |
| 10933 | |
| 10934 | #ifdef CONFIG_SMP |
| 10935 | @@ -133,6 +147,23 @@ NESTED(kernel_entry, 16, sp) # kernel |
| 10936 | * function after setting up the stack and gp registers. |
| 10937 | */ |
| 10938 | NESTED(smp_bootstrap, 16, sp) |
| 10939 | + .set push |
| 10940 | + /* |
| 10941 | + * For the moment disable interrupts and bootstrap exception |
| 10942 | + * vectors, mark the kernel mode and set ST0_KX so that the CPU |
| 10943 | + * does not spit fire when using 64-bit addresses. A full |
| 10944 | + * initialization of the CPU's status register is done later in |
| 10945 | + * per_cpu_trap_init(). |
| 10946 | + */ |
| 10947 | + mfc0 t0, CP0_STATUS |
| 10948 | + or t0, ST0_CU0|ST0_BEV|ST0_KX|0x1f |
| 10949 | + xor t0, ST0_BEV|0x1f |
| 10950 | + mtc0 t0, CP0_STATUS |
| 10951 | + |
| 10952 | + .set noreorder |
| 10953 | + sll zero,3 # ehb |
| 10954 | + .set reorder |
| 10955 | + |
| 10956 | #ifdef CONFIG_SGI_IP27 |
| 10957 | GET_NASID_ASM t1 |
| 10958 | dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \ |
| 10959 | @@ -146,19 +177,8 @@ NESTED(smp_bootstrap, 16, sp) |
| 10960 | ARC64_TWIDDLE_PC |
| 10961 | #endif /* CONFIG_SGI_IP27 */ |
| 10962 | |
| 10963 | - CLI |
| 10964 | - |
| 10965 | - /* |
| 10966 | - * For the moment set ST0_KU so the CPU will not spit fire when |
| 10967 | - * executing 64-bit instructions. The full initialization of the |
| 10968 | - * CPU's status register is done later in per_cpu_trap_init(). |
| 10969 | - */ |
| 10970 | - mfc0 t0, CP0_STATUS |
| 10971 | - or t0, ST0_KX |
| 10972 | - mtc0 t0, CP0_STATUS |
| 10973 | - |
| 10974 | jal start_secondary # XXX: IP27: cboot |
| 10975 | - |
| 10976 | + .set pop |
| 10977 | END(smp_bootstrap) |
| 10978 | #endif /* CONFIG_SMP */ |
| 10979 | |
| 10980 | --- a/arch/mips64/kernel/ioctl32.c |
| 10981 | +++ b/arch/mips64/kernel/ioctl32.c |
| 10982 | @@ -2352,7 +2352,7 @@ static struct ioctl32_list ioctl32_handl |
| 10983 | IOCTL32_HANDLER(AUTOFS_IOC_SETTIMEOUT32, ioc_settimeout), |
| 10984 | IOCTL32_DEFAULT(AUTOFS_IOC_EXPIRE), |
| 10985 | IOCTL32_DEFAULT(AUTOFS_IOC_EXPIRE_MULTI), |
| 10986 | - IOCTL32_DEFAULT(AUTOFS_IOC_PROTSUBVER), |
| 10987 | + IOCTL32_DEFAULT(AUTOFS_IOC_PROTOSUBVER), |
| 10988 | IOCTL32_DEFAULT(AUTOFS_IOC_ASKREGHOST), |
| 10989 | IOCTL32_DEFAULT(AUTOFS_IOC_TOGGLEREGHOST), |
| 10990 | IOCTL32_DEFAULT(AUTOFS_IOC_ASKUMOUNT), |
| 10991 | --- a/arch/mips64/kernel/linux32.c |
| 10992 | +++ b/arch/mips64/kernel/linux32.c |
| 10993 | @@ -1101,6 +1101,7 @@ do_readv_writev32(int type, struct file |
| 10994 | * specially as they have atomicity guarantees and can handle |
| 10995 | * iovec's natively |
| 10996 | */ |
| 10997 | + inode = file->f_dentry->d_inode; |
| 10998 | if (inode->i_sock) { |
| 10999 | int err; |
| 11000 | err = sock_readv_writev(type, inode, file, iov, count, tot_len); |
| 11001 | @@ -1187,72 +1188,19 @@ bad_file: |
| 11002 | lseek back to original location. They fail just like lseek does on |
| 11003 | non-seekable files. */ |
| 11004 | |
| 11005 | -asmlinkage ssize_t sys32_pread(unsigned int fd, char * buf, |
| 11006 | - size_t count, u32 unused, u64 a4, u64 a5) |
| 11007 | +asmlinkage ssize_t sys32_pread(unsigned int fd, char *buf, |
| 11008 | + size_t count, u32 unused, u64 a4, u64 a5) |
| 11009 | { |
| 11010 | - ssize_t ret; |
| 11011 | - struct file * file; |
| 11012 | - ssize_t (*read)(struct file *, char *, size_t, loff_t *); |
| 11013 | - loff_t pos; |
| 11014 | - |
| 11015 | - ret = -EBADF; |
| 11016 | - file = fget(fd); |
| 11017 | - if (!file) |
| 11018 | - goto bad_file; |
| 11019 | - if (!(file->f_mode & FMODE_READ)) |
| 11020 | - goto out; |
| 11021 | - pos = merge_64(a4, a5); |
| 11022 | - ret = locks_verify_area(FLOCK_VERIFY_READ, file->f_dentry->d_inode, |
| 11023 | - file, pos, count); |
| 11024 | - if (ret) |
| 11025 | - goto out; |
| 11026 | - ret = -EINVAL; |
| 11027 | - if (!file->f_op || !(read = file->f_op->read)) |
| 11028 | - goto out; |
| 11029 | - if (pos < 0) |
| 11030 | - goto out; |
| 11031 | - ret = read(file, buf, count, &pos); |
| 11032 | - if (ret > 0) |
| 11033 | - dnotify_parent(file->f_dentry, DN_ACCESS); |
| 11034 | -out: |
| 11035 | - fput(file); |
| 11036 | -bad_file: |
| 11037 | - return ret; |
| 11038 | + return sys_pread(fd, buf, count, merge_64(a4, a5)); |
| 11039 | } |
| 11040 | |
| 11041 | asmlinkage ssize_t sys32_pwrite(unsigned int fd, const char * buf, |
| 11042 | size_t count, u32 unused, u64 a4, u64 a5) |
| 11043 | { |
| 11044 | - ssize_t ret; |
| 11045 | - struct file * file; |
| 11046 | - ssize_t (*write)(struct file *, const char *, size_t, loff_t *); |
| 11047 | - loff_t pos; |
| 11048 | + return sys_pwrite(fd, buf, count, merge_64(a4, a5)); |
| 11049 | +} |
| 11050 | |
| 11051 | - ret = -EBADF; |
| 11052 | - file = fget(fd); |
| 11053 | - if (!file) |
| 11054 | - goto bad_file; |
| 11055 | - if (!(file->f_mode & FMODE_WRITE)) |
| 11056 | - goto out; |
| 11057 | - pos = merge_64(a4, a5); |
| 11058 | - ret = locks_verify_area(FLOCK_VERIFY_WRITE, file->f_dentry->d_inode, |
| 11059 | - file, pos, count); |
| 11060 | - if (ret) |
| 11061 | - goto out; |
| 11062 | - ret = -EINVAL; |
| 11063 | - if (!file->f_op || !(write = file->f_op->write)) |
| 11064 | - goto out; |
| 11065 | - if (pos < 0) |
| 11066 | - goto out; |
| 11067 | |
| 11068 | - ret = write(file, buf, count, &pos); |
| 11069 | - if (ret > 0) |
| 11070 | - dnotify_parent(file->f_dentry, DN_MODIFY); |
| 11071 | -out: |
| 11072 | - fput(file); |
| 11073 | -bad_file: |
| 11074 | - return ret; |
| 11075 | -} |
| 11076 | /* |
| 11077 | * Ooo, nasty. We need here to frob 32-bit unsigned longs to |
| 11078 | * 64-bit unsigned longs. |
| 11079 | --- a/arch/mips64/kernel/process.c |
| 11080 | +++ b/arch/mips64/kernel/process.c |
| 11081 | @@ -125,6 +125,25 @@ int dump_fpu(struct pt_regs *regs, elf_f |
| 11082 | return 1; |
| 11083 | } |
| 11084 | |
| 11085 | +void dump_regs(elf_greg_t *gp, struct pt_regs *regs) |
| 11086 | +{ |
| 11087 | + int i; |
| 11088 | + |
| 11089 | + for (i = 0; i < EF_REG0; i++) |
| 11090 | + gp[i] = 0; |
| 11091 | + gp[EF_REG0] = 0; |
| 11092 | + for (i = 1; i <= 31; i++) |
| 11093 | + gp[EF_REG0 + i] = regs->regs[i]; |
| 11094 | + gp[EF_REG26] = 0; |
| 11095 | + gp[EF_REG27] = 0; |
| 11096 | + gp[EF_LO] = regs->lo; |
| 11097 | + gp[EF_HI] = regs->hi; |
| 11098 | + gp[EF_CP0_EPC] = regs->cp0_epc; |
| 11099 | + gp[EF_CP0_BADVADDR] = regs->cp0_badvaddr; |
| 11100 | + gp[EF_CP0_STATUS] = regs->cp0_status; |
| 11101 | + gp[EF_CP0_CAUSE] = regs->cp0_cause; |
| 11102 | +} |
| 11103 | + |
| 11104 | /* |
| 11105 | * Create a kernel thread |
| 11106 | */ |
| 11107 | --- a/arch/mips64/kernel/scall_64.S |
| 11108 | +++ b/arch/mips64/kernel/scall_64.S |
| 11109 | @@ -102,15 +102,14 @@ _64_reschedule: |
| 11110 | |
| 11111 | trace_a_syscall: |
| 11112 | SAVE_STATIC |
| 11113 | - sd t2,PT_R1(sp) |
| 11114 | + move s0, t2 |
| 11115 | jal syscall_trace |
| 11116 | - ld t2,PT_R1(sp) |
| 11117 | |
| 11118 | ld a0, PT_R4(sp) # Restore argument registers |
| 11119 | ld a1, PT_R5(sp) |
| 11120 | ld a2, PT_R6(sp) |
| 11121 | ld a3, PT_R7(sp) |
| 11122 | - jalr t2 |
| 11123 | + jalr s0 |
| 11124 | |
| 11125 | li t0, -EMAXERRNO - 1 # error? |
| 11126 | sltu t0, t0, v0 |
| 11127 | --- a/arch/mips64/kernel/scall_n32.S |
| 11128 | +++ b/arch/mips64/kernel/scall_n32.S |
| 11129 | @@ -106,15 +106,14 @@ n32_reschedule: |
| 11130 | |
| 11131 | trace_a_syscall: |
| 11132 | SAVE_STATIC |
| 11133 | - sd t2,PT_R1(sp) |
| 11134 | + move s0, t2 |
| 11135 | jal syscall_trace |
| 11136 | - ld t2,PT_R1(sp) |
| 11137 | |
| 11138 | ld a0, PT_R4(sp) # Restore argument registers |
| 11139 | ld a1, PT_R5(sp) |
| 11140 | ld a2, PT_R6(sp) |
| 11141 | ld a3, PT_R7(sp) |
| 11142 | - jalr t2 |
| 11143 | + jalr s0 |
| 11144 | |
| 11145 | li t0, -EMAXERRNO - 1 # error? |
| 11146 | sltu t0, t0, v0 |
| 11147 | --- a/arch/mips64/kernel/scall_o32.S |
| 11148 | +++ b/arch/mips64/kernel/scall_o32.S |
| 11149 | @@ -118,9 +118,8 @@ trace_a_syscall: |
| 11150 | sd a6, PT_R10(sp) |
| 11151 | sd a7, PT_R11(sp) |
| 11152 | |
| 11153 | - sd t2,PT_R1(sp) |
| 11154 | + move s0, t2 |
| 11155 | jal syscall_trace |
| 11156 | - ld t2,PT_R1(sp) |
| 11157 | |
| 11158 | ld a0, PT_R4(sp) # Restore argument registers |
| 11159 | ld a1, PT_R5(sp) |
| 11160 | @@ -129,7 +128,7 @@ trace_a_syscall: |
| 11161 | ld a4, PT_R8(sp) |
| 11162 | ld a5, PT_R9(sp) |
| 11163 | |
| 11164 | - jalr t2 |
| 11165 | + jalr s0 |
| 11166 | |
| 11167 | li t0, -EMAXERRNO - 1 # error? |
| 11168 | sltu t0, t0, v0 |
| 11169 | @@ -576,6 +575,8 @@ out: jr ra |
| 11170 | sys_call_table: |
| 11171 | syscalltable |
| 11172 | |
| 11173 | + .purgem sys |
| 11174 | + |
| 11175 | .macro sys function, nargs |
| 11176 | .byte \nargs |
| 11177 | .endm |
| 11178 | --- a/arch/mips64/kernel/setup.c |
| 11179 | +++ b/arch/mips64/kernel/setup.c |
| 11180 | @@ -129,14 +129,6 @@ asmlinkage void __init init_arch(int arg |
| 11181 | */ |
| 11182 | load_mmu(); |
| 11183 | |
| 11184 | - /* |
| 11185 | - * On IP27, I am seeing the TS bit set when the kernel is loaded. |
| 11186 | - * Maybe because the kernel is in ckseg0 and not xkphys? Clear it |
| 11187 | - * anyway ... |
| 11188 | - */ |
| 11189 | - clear_c0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3); |
| 11190 | - set_c0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR); |
| 11191 | - |
| 11192 | start_kernel(); |
| 11193 | } |
| 11194 | |
| 11195 | --- a/arch/mips64/kernel/signal_n32.c |
| 11196 | +++ b/arch/mips64/kernel/signal_n32.c |
| 11197 | @@ -68,7 +68,7 @@ struct rt_sigframe_n32 { |
| 11198 | }; |
| 11199 | |
| 11200 | extern asmlinkage int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc); |
| 11201 | -extern int inline setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc); |
| 11202 | +extern int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc); |
| 11203 | |
| 11204 | asmlinkage void sysn32_rt_sigreturn(abi64_no_regargs, struct pt_regs regs) |
| 11205 | { |
| 11206 | --- a/arch/mips64/kernel/traps.c |
| 11207 | +++ b/arch/mips64/kernel/traps.c |
| 11208 | @@ -462,9 +462,10 @@ static inline void simulate_ll(struct pt |
| 11209 | } |
| 11210 | ll_task = current; |
| 11211 | |
| 11212 | + compute_return_epc(regs); |
| 11213 | + |
| 11214 | regs->regs[(opcode & RT) >> 16] = value; |
| 11215 | |
| 11216 | - compute_return_epc(regs); |
| 11217 | return; |
| 11218 | |
| 11219 | sig: |
| 11220 | @@ -495,8 +496,8 @@ static inline void simulate_sc(struct pt |
| 11221 | goto sig; |
| 11222 | } |
| 11223 | if (ll_bit == 0 || ll_task != current) { |
| 11224 | - regs->regs[reg] = 0; |
| 11225 | compute_return_epc(regs); |
| 11226 | + regs->regs[reg] = 0; |
| 11227 | return; |
| 11228 | } |
| 11229 | |
| 11230 | @@ -505,9 +506,9 @@ static inline void simulate_sc(struct pt |
| 11231 | goto sig; |
| 11232 | } |
| 11233 | |
| 11234 | + compute_return_epc(regs); |
| 11235 | regs->regs[reg] = 1; |
| 11236 | |
| 11237 | - compute_return_epc(regs); |
| 11238 | return; |
| 11239 | |
| 11240 | sig: |
| 11241 | @@ -809,13 +810,18 @@ extern asmlinkage int fpu_emulator_resto |
| 11242 | void __init per_cpu_trap_init(void) |
| 11243 | { |
| 11244 | unsigned int cpu = smp_processor_id(); |
| 11245 | + unsigned int status_set = ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
| 11246 | |
| 11247 | - /* Some firmware leaves the BEV flag set, clear it. */ |
| 11248 | - clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); |
| 11249 | - set_c0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX); |
| 11250 | - |
| 11251 | + /* |
| 11252 | + * Disable coprocessors, enable 64-bit addressing and set FPU |
| 11253 | + * for the 32/32 FPR register model. Reset the BEV flag that |
| 11254 | + * some firmware may have left set and the TS bit (for IP27). |
| 11255 | + * Set XX for ISA IV code to work. |
| 11256 | + */ |
| 11257 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) |
| 11258 | - set_c0_status(ST0_XX); |
| 11259 | + status_set |= ST0_XX; |
| 11260 | + change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
| 11261 | + status_set); |
| 11262 | |
| 11263 | /* |
| 11264 | * Some MIPS CPUs have a dedicated interrupt vector which reduces the |
| 11265 | @@ -825,13 +831,11 @@ void __init per_cpu_trap_init(void) |
| 11266 | set_c0_cause(CAUSEF_IV); |
| 11267 | |
| 11268 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; |
| 11269 | - write_c0_context(((long)(&pgd_current[cpu])) << 23); |
| 11270 | - write_c0_wired(0); |
| 11271 | + TLBMISS_HANDLER_SETUP(); |
| 11272 | |
| 11273 | atomic_inc(&init_mm.mm_count); |
| 11274 | current->active_mm = &init_mm; |
| 11275 | - if (current->mm) |
| 11276 | - BUG(); |
| 11277 | + BUG_ON(current->mm); |
| 11278 | enter_lazy_tlb(&init_mm, current, cpu); |
| 11279 | } |
| 11280 | |
| 11281 | @@ -842,8 +846,6 @@ void __init trap_init(void) |
| 11282 | extern char except_vec4; |
| 11283 | unsigned long i; |
| 11284 | |
| 11285 | - per_cpu_trap_init(); |
| 11286 | - |
| 11287 | /* Copy the generic exception handlers to their final destination. */ |
| 11288 | memcpy((void *) KSEG0 , &except_vec0_generic, 0x80); |
| 11289 | memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); |
| 11290 | @@ -933,6 +935,5 @@ void __init trap_init(void) |
| 11291 | |
| 11292 | flush_icache_range(KSEG0, KSEG0 + 0x400); |
| 11293 | |
| 11294 | - atomic_inc(&init_mm.mm_count); /* XXX UP? */ |
| 11295 | - current->active_mm = &init_mm; |
| 11296 | + per_cpu_trap_init(); |
| 11297 | } |
| 11298 | --- a/arch/mips64/mm/cerr-sb1.c |
| 11299 | +++ b/arch/mips64/mm/cerr-sb1.c |
| 11300 | @@ -252,14 +252,14 @@ static const uint8_t parity[256] = { |
| 11301 | |
| 11302 | /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ |
| 11303 | static const uint64_t mask_72_64[8] = { |
| 11304 | - 0x0738C808099264FFL, |
| 11305 | - 0x38C808099264FF07L, |
| 11306 | - 0xC808099264FF0738L, |
| 11307 | - 0x08099264FF0738C8L, |
| 11308 | - 0x099264FF0738C808L, |
| 11309 | - 0x9264FF0738C80809L, |
| 11310 | - 0x64FF0738C8080992L, |
| 11311 | - 0xFF0738C808099264L |
| 11312 | + 0x0738C808099264FFULL, |
| 11313 | + 0x38C808099264FF07ULL, |
| 11314 | + 0xC808099264FF0738ULL, |
| 11315 | + 0x08099264FF0738C8ULL, |
| 11316 | + 0x099264FF0738C808ULL, |
| 11317 | + 0x9264FF0738C80809ULL, |
| 11318 | + 0x64FF0738C8080992ULL, |
| 11319 | + 0xFF0738C808099264ULL |
| 11320 | }; |
| 11321 | |
| 11322 | /* Calculate the parity on a range of bits */ |
| 11323 | @@ -331,9 +331,9 @@ static uint32_t extract_ic(unsigned shor |
| 11324 | ((lru >> 4) & 0x3), |
| 11325 | ((lru >> 6) & 0x3)); |
| 11326 | } |
| 11327 | - va = (taglo & 0xC0000FFFFFFFE000) | addr; |
| 11328 | + va = (taglo & 0xC0000FFFFFFFE000ULL) | addr; |
| 11329 | if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) |
| 11330 | - va |= 0x3FFFF00000000000; |
| 11331 | + va |= 0x3FFFF00000000000ULL; |
| 11332 | valid = ((taghi >> 29) & 1); |
| 11333 | if (valid) { |
| 11334 | tlo_tmp = taglo & 0xfff3ff; |
| 11335 | @@ -474,7 +474,7 @@ static uint32_t extract_dc(unsigned shor |
| 11336 | : "r" ((way << 13) | addr)); |
| 11337 | |
| 11338 | taglo = ((unsigned long long)taglohi << 32) | taglolo; |
| 11339 | - pa = (taglo & 0xFFFFFFE000) | addr; |
| 11340 | + pa = (taglo & 0xFFFFFFE000ULL) | addr; |
| 11341 | if (way == 0) { |
| 11342 | lru = (taghi >> 14) & 0xff; |
| 11343 | prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", |
| 11344 | --- a/arch/mips64/mm/c-r4k.c |
| 11345 | +++ b/arch/mips64/mm/c-r4k.c |
| 11346 | @@ -867,9 +867,16 @@ static void __init probe_pcache(void) |
| 11347 | * normally they'd suffer from aliases but magic in the hardware deals |
| 11348 | * with that for us so we don't need to take care ourselves. |
| 11349 | */ |
| 11350 | - if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) |
| 11351 | - if (c->dcache.waysize > PAGE_SIZE) |
| 11352 | - c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 11353 | + switch (c->cputype) { |
| 11354 | + case CPU_R10000: |
| 11355 | + case CPU_R12000: |
| 11356 | + break; |
| 11357 | + case CPU_24K: |
| 11358 | + if (!(read_c0_config7() & (1 << 16))) |
| 11359 | + default: |
| 11360 | + if (c->dcache.waysize > PAGE_SIZE) |
| 11361 | + c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 11362 | + } |
| 11363 | |
| 11364 | switch (c->cputype) { |
| 11365 | case CPU_20KC: |
| 11366 | @@ -1070,9 +1077,6 @@ void __init ld_mmu_r4xx0(void) |
| 11367 | setup_scache(); |
| 11368 | coherency_setup(); |
| 11369 | |
| 11370 | - if (c->dcache.sets * c->dcache.ways > PAGE_SIZE) |
| 11371 | - c->dcache.flags |= MIPS_CACHE_ALIASES; |
| 11372 | - |
| 11373 | r4k_blast_dcache_page_setup(); |
| 11374 | r4k_blast_dcache_page_indexed_setup(); |
| 11375 | r4k_blast_dcache_setup(); |
| 11376 | --- a/arch/mips64/mm/tlbex-r4k.S |
| 11377 | +++ b/arch/mips64/mm/tlbex-r4k.S |
| 11378 | @@ -125,6 +125,33 @@ LEAF(except_vec1_r4k) |
| 11379 | nop |
| 11380 | END(except_vec1_r4k) |
| 11381 | |
| 11382 | + __FINIT |
| 11383 | + |
| 11384 | + .align 5 |
| 11385 | +LEAF(handle_vec1_r4k) |
| 11386 | + .set noat |
| 11387 | + LOAD_PTE2 k1 k0 9f |
| 11388 | + ld k0, 0(k1) # get even pte |
| 11389 | + ld k1, 8(k1) # get odd pte |
| 11390 | + PTE_RELOAD k0 k1 |
| 11391 | + mtc0_tlbw_hazard |
| 11392 | + tlbwr |
| 11393 | + tlbw_eret_hazard |
| 11394 | + eret |
| 11395 | + |
| 11396 | +9: # handle the vmalloc range |
| 11397 | + LOAD_KPTE2 k1 k0 invalid_vmalloc_address |
| 11398 | + ld k0, 0(k1) # get even pte |
| 11399 | + ld k1, 8(k1) # get odd pte |
| 11400 | + PTE_RELOAD k0 k1 |
| 11401 | + mtc0_tlbw_hazard |
| 11402 | + tlbwr |
| 11403 | + tlbw_eret_hazard |
| 11404 | + eret |
| 11405 | +END(handle_vec1_r4k) |
| 11406 | + |
| 11407 | + __INIT |
| 11408 | + |
| 11409 | LEAF(except_vec1_sb1) |
| 11410 | #if BCM1250_M3_WAR |
| 11411 | dmfc0 k0, CP0_BADVADDR |
| 11412 | @@ -134,28 +161,24 @@ LEAF(except_vec1_sb1) |
| 11413 | bnez k0, 1f |
| 11414 | #endif |
| 11415 | .set noat |
| 11416 | - dla k0, handle_vec1_r4k |
| 11417 | + dla k0, handle_vec1_sb1 |
| 11418 | jr k0 |
| 11419 | nop |
| 11420 | |
| 11421 | 1: eret |
| 11422 | - nop |
| 11423 | END(except_vec1_sb1) |
| 11424 | |
| 11425 | __FINIT |
| 11426 | |
| 11427 | .align 5 |
| 11428 | -LEAF(handle_vec1_r4k) |
| 11429 | +LEAF(handle_vec1_sb1) |
| 11430 | .set noat |
| 11431 | LOAD_PTE2 k1 k0 9f |
| 11432 | ld k0, 0(k1) # get even pte |
| 11433 | ld k1, 8(k1) # get odd pte |
| 11434 | PTE_RELOAD k0 k1 |
| 11435 | - rm9000_tlb_hazard |
| 11436 | - b 1f |
| 11437 | - tlbwr |
| 11438 | -1: nop |
| 11439 | - rm9000_tlb_hazard |
| 11440 | + mtc0_tlbw_hazard |
| 11441 | + tlbwr |
| 11442 | eret |
| 11443 | |
| 11444 | 9: # handle the vmalloc range |
| 11445 | @@ -163,13 +186,10 @@ LEAF(handle_vec1_r4k) |
| 11446 | ld k0, 0(k1) # get even pte |
| 11447 | ld k1, 8(k1) # get odd pte |
| 11448 | PTE_RELOAD k0 k1 |
| 11449 | - rm9000_tlb_hazard |
| 11450 | - b 1f |
| 11451 | - tlbwr |
| 11452 | -1: nop |
| 11453 | - rm9000_tlb_hazard |
| 11454 | + mtc0_tlbw_hazard |
| 11455 | + tlbwr |
| 11456 | eret |
| 11457 | -END(handle_vec1_r4k) |
| 11458 | +END(handle_vec1_sb1) |
| 11459 | |
| 11460 | |
| 11461 | __INIT |
| 11462 | @@ -195,10 +215,8 @@ LEAF(handle_vec1_r10k) |
| 11463 | ld k0, 0(k1) # get even pte |
| 11464 | ld k1, 8(k1) # get odd pte |
| 11465 | PTE_RELOAD k0 k1 |
| 11466 | - rm9000_tlb_hazard |
| 11467 | - nop |
| 11468 | + mtc0_tlbw_hazard |
| 11469 | tlbwr |
| 11470 | - rm9000_tlb_hazard |
| 11471 | eret |
| 11472 | |
| 11473 | 9: # handle the vmalloc range |
| 11474 | @@ -206,10 +224,8 @@ LEAF(handle_vec1_r10k) |
| 11475 | ld k0, 0(k1) # get even pte |
| 11476 | ld k1, 8(k1) # get odd pte |
| 11477 | PTE_RELOAD k0 k1 |
| 11478 | - rm9000_tlb_hazard |
| 11479 | - nop |
| 11480 | + mtc0_tlbw_hazard |
| 11481 | tlbwr |
| 11482 | - rm9000_tlb_hazard |
| 11483 | eret |
| 11484 | END(handle_vec1_r10k) |
| 11485 | |
| 11486 | --- a/arch/mips64/mm/tlb-r4k.c |
| 11487 | +++ b/arch/mips64/mm/tlb-r4k.c |
| 11488 | @@ -1,24 +1,12 @@ |
| 11489 | /* |
| 11490 | - * Carsten Langgaard, carstenl@mips.com |
| 11491 | - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. |
| 11492 | - * |
| 11493 | - * This program is free software; you can distribute it and/or modify it |
| 11494 | - * under the terms of the GNU General Public License (Version 2) as |
| 11495 | - * published by the Free Software Foundation. |
| 11496 | - * |
| 11497 | - * This program is distributed in the hope it will be useful, but WITHOUT |
| 11498 | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11499 | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 11500 | + * This file is subject to the terms and conditions of the GNU General Public |
| 11501 | + * License. See the file "COPYING" in the main directory of this archive |
| 11502 | * for more details. |
| 11503 | * |
| 11504 | - * You should have received a copy of the GNU General Public License along |
| 11505 | - * with this program; if not, write to the Free Software Foundation, Inc., |
| 11506 | - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 11507 | - * |
| 11508 | - * MIPS64 CPU variant specific MMU routines. |
| 11509 | - * These routine are not optimized in any way, they are done in a generic way |
| 11510 | - * so they can be used on all MIPS64 compliant CPUs, and also done in an |
| 11511 | - * attempt not to break anything for the R4xx0 style CPUs. |
| 11512 | + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) |
| 11513 | + * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org |
| 11514 | + * Carsten Langgaard, carstenl@mips.com |
| 11515 | + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. |
| 11516 | */ |
| 11517 | #include <linux/init.h> |
| 11518 | #include <linux/sched.h> |
| 11519 | @@ -30,9 +18,6 @@ |
| 11520 | #include <asm/pgtable.h> |
| 11521 | #include <asm/system.h> |
| 11522 | |
| 11523 | -#undef DEBUG_TLB |
| 11524 | -#undef DEBUG_TLBUPDATE |
| 11525 | - |
| 11526 | extern void except_vec1_r4k(void); |
| 11527 | |
| 11528 | /* CP0 hazard avoidance. */ |
| 11529 | @@ -46,31 +31,23 @@ void local_flush_tlb_all(void) |
| 11530 | unsigned long old_ctx; |
| 11531 | int entry; |
| 11532 | |
| 11533 | -#ifdef DEBUG_TLB |
| 11534 | - printk("[tlball]"); |
| 11535 | -#endif |
| 11536 | - |
| 11537 | local_irq_save(flags); |
| 11538 | /* Save old context and create impossible VPN2 value */ |
| 11539 | old_ctx = read_c0_entryhi(); |
| 11540 | - write_c0_entryhi(XKPHYS); |
| 11541 | write_c0_entrylo0(0); |
| 11542 | write_c0_entrylo1(0); |
| 11543 | - BARRIER; |
| 11544 | |
| 11545 | entry = read_c0_wired(); |
| 11546 | |
| 11547 | /* Blast 'em all away. */ |
| 11548 | - while(entry < current_cpu_data.tlbsize) { |
| 11549 | - /* Make sure all entries differ. */ |
| 11550 | - write_c0_entryhi(XKPHYS+entry*0x2000); |
| 11551 | + while (entry < current_cpu_data.tlbsize) { |
| 11552 | + write_c0_entryhi(XKPHYS + entry*0x2000); |
| 11553 | write_c0_index(entry); |
| 11554 | - BARRIER; |
| 11555 | + mtc0_tlbw_hazard(); |
| 11556 | tlb_write_indexed(); |
| 11557 | - BARRIER; |
| 11558 | entry++; |
| 11559 | } |
| 11560 | - BARRIER; |
| 11561 | + tlbw_use_hazard(); |
| 11562 | write_c0_entryhi(old_ctx); |
| 11563 | local_irq_restore(flags); |
| 11564 | } |
| 11565 | @@ -79,12 +56,8 @@ void local_flush_tlb_mm(struct mm_struct |
| 11566 | { |
| 11567 | int cpu = smp_processor_id(); |
| 11568 | |
| 11569 | - if (cpu_context(cpu, mm) != 0) { |
| 11570 | -#ifdef DEBUG_TLB |
| 11571 | - printk("[tlbmm<%d>]", mm->context); |
| 11572 | -#endif |
| 11573 | + if (cpu_context(cpu, mm) != 0) |
| 11574 | drop_mmu_context(mm,cpu); |
| 11575 | - } |
| 11576 | } |
| 11577 | |
| 11578 | void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, |
| 11579 | @@ -96,10 +69,6 @@ void local_flush_tlb_range(struct mm_str |
| 11580 | unsigned long flags; |
| 11581 | int size; |
| 11582 | |
| 11583 | -#ifdef DEBUG_TLB |
| 11584 | - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & ASID_MASK), |
| 11585 | - start, end); |
| 11586 | -#endif |
| 11587 | local_irq_save(flags); |
| 11588 | size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
| 11589 | size = (size + 1) >> 1; |
| 11590 | @@ -110,25 +79,25 @@ void local_flush_tlb_range(struct mm_str |
| 11591 | start &= (PAGE_MASK << 1); |
| 11592 | end += ((PAGE_SIZE << 1) - 1); |
| 11593 | end &= (PAGE_MASK << 1); |
| 11594 | - while(start < end) { |
| 11595 | + while (start < end) { |
| 11596 | int idx; |
| 11597 | |
| 11598 | write_c0_entryhi(start | newpid); |
| 11599 | start += (PAGE_SIZE << 1); |
| 11600 | - BARRIER; |
| 11601 | + mtc0_tlbw_hazard(); |
| 11602 | tlb_probe(); |
| 11603 | BARRIER; |
| 11604 | idx = read_c0_index(); |
| 11605 | write_c0_entrylo0(0); |
| 11606 | write_c0_entrylo1(0); |
| 11607 | - if(idx < 0) |
| 11608 | + if (idx < 0) |
| 11609 | continue; |
| 11610 | /* Make sure all entries differ. */ |
| 11611 | write_c0_entryhi(XKPHYS+idx*0x2000); |
| 11612 | - BARRIER; |
| 11613 | + mtc0_tlbw_hazard(); |
| 11614 | tlb_write_indexed(); |
| 11615 | - BARRIER; |
| 11616 | } |
| 11617 | + tlbw_use_hazard(); |
| 11618 | write_c0_entryhi(oldpid); |
| 11619 | } else { |
| 11620 | drop_mmu_context(mm, cpu); |
| 11621 | @@ -145,28 +114,26 @@ void local_flush_tlb_page(struct vm_area |
| 11622 | unsigned long flags; |
| 11623 | unsigned long oldpid, newpid, idx; |
| 11624 | |
| 11625 | -#ifdef DEBUG_TLB |
| 11626 | - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); |
| 11627 | -#endif |
| 11628 | newpid = cpu_asid(cpu, vma->vm_mm); |
| 11629 | page &= (PAGE_MASK << 1); |
| 11630 | local_irq_save(flags); |
| 11631 | oldpid = read_c0_entryhi(); |
| 11632 | write_c0_entryhi(page | newpid); |
| 11633 | - BARRIER; |
| 11634 | + mtc0_tlbw_hazard(); |
| 11635 | tlb_probe(); |
| 11636 | BARRIER; |
| 11637 | idx = read_c0_index(); |
| 11638 | write_c0_entrylo0(0); |
| 11639 | write_c0_entrylo1(0); |
| 11640 | - if(idx < 0) |
| 11641 | + if (idx < 0) |
| 11642 | goto finish; |
| 11643 | /* Make sure all entries differ. */ |
| 11644 | write_c0_entryhi(XKPHYS+idx*0x2000); |
| 11645 | - BARRIER; |
| 11646 | + mtc0_tlbw_hazard(); |
| 11647 | tlb_write_indexed(); |
| 11648 | + tlbw_use_hazard(); |
| 11649 | + |
| 11650 | finish: |
| 11651 | - BARRIER; |
| 11652 | write_c0_entryhi(oldpid); |
| 11653 | local_irq_restore(flags); |
| 11654 | } |
| 11655 | @@ -186,7 +153,7 @@ void local_flush_tlb_one(unsigned long p |
| 11656 | |
| 11657 | local_irq_save(flags); |
| 11658 | write_c0_entryhi(page); |
| 11659 | - BARRIER; |
| 11660 | + mtc0_tlbw_hazard(); |
| 11661 | tlb_probe(); |
| 11662 | BARRIER; |
| 11663 | idx = read_c0_index(); |
| 11664 | @@ -195,10 +162,12 @@ void local_flush_tlb_one(unsigned long p |
| 11665 | if (idx >= 0) { |
| 11666 | /* Make sure all entries differ. */ |
| 11667 | write_c0_entryhi(KSEG0+idx*0x2000); |
| 11668 | + mtc0_tlbw_hazard(); |
| 11669 | tlb_write_indexed(); |
| 11670 | + tlbw_use_hazard(); |
| 11671 | } |
| 11672 | - BARRIER; |
| 11673 | write_c0_entryhi(oldpid); |
| 11674 | + |
| 11675 | local_irq_restore(flags); |
| 11676 | } |
| 11677 | |
| 11678 | @@ -208,7 +177,6 @@ void local_flush_tlb_one(unsigned long p |
| 11679 | void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) |
| 11680 | { |
| 11681 | unsigned long flags; |
| 11682 | - unsigned int asid; |
| 11683 | pgd_t *pgdp; |
| 11684 | pmd_t *pmdp; |
| 11685 | pte_t *ptep; |
| 11686 | @@ -222,70 +190,58 @@ void __update_tlb(struct vm_area_struct |
| 11687 | |
| 11688 | pid = read_c0_entryhi() & ASID_MASK; |
| 11689 | |
| 11690 | -#ifdef DEBUG_TLB |
| 11691 | - if ((pid != (cpu_asid(smp_processor_id(), vma->vm_mm))) || |
| 11692 | - (cpu_context(smp_processor_id(), vma->vm_mm) == 0)) { |
| 11693 | - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d" |
| 11694 | - "tlbpid=%d\n", (int) (cpu_context(smp_processor_id(), |
| 11695 | - vma->vm_mm) & ASID_MASK), pid); |
| 11696 | - } |
| 11697 | -#endif |
| 11698 | - |
| 11699 | local_irq_save(flags); |
| 11700 | address &= (PAGE_MASK << 1); |
| 11701 | - write_c0_entryhi(address | (pid)); |
| 11702 | + write_c0_entryhi(address | pid); |
| 11703 | pgdp = pgd_offset(vma->vm_mm, address); |
| 11704 | - BARRIER; |
| 11705 | + mtc0_tlbw_hazard(); |
| 11706 | tlb_probe(); |
| 11707 | BARRIER; |
| 11708 | pmdp = pmd_offset(pgdp, address); |
| 11709 | idx = read_c0_index(); |
| 11710 | ptep = pte_offset(pmdp, address); |
| 11711 | - BARRIER; |
| 11712 | write_c0_entrylo0(pte_val(*ptep++) >> 6); |
| 11713 | write_c0_entrylo1(pte_val(*ptep) >> 6); |
| 11714 | - write_c0_entryhi(address | (pid)); |
| 11715 | - BARRIER; |
| 11716 | - if(idx < 0) { |
| 11717 | + write_c0_entryhi(address | pid); |
| 11718 | + mtc0_tlbw_hazard(); |
| 11719 | + if (idx < 0) |
| 11720 | tlb_write_random(); |
| 11721 | - } else { |
| 11722 | + else |
| 11723 | tlb_write_indexed(); |
| 11724 | - } |
| 11725 | - BARRIER; |
| 11726 | + tlbw_use_hazard(); |
| 11727 | write_c0_entryhi(pid); |
| 11728 | - BARRIER; |
| 11729 | local_irq_restore(flags); |
| 11730 | } |
| 11731 | |
| 11732 | -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
| 11733 | - unsigned long entryhi, unsigned long pagemask) |
| 11734 | +void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
| 11735 | + unsigned long entryhi, unsigned long pagemask) |
| 11736 | { |
| 11737 | - unsigned long flags; |
| 11738 | - unsigned long wired; |
| 11739 | - unsigned long old_pagemask; |
| 11740 | - unsigned long old_ctx; |
| 11741 | - |
| 11742 | - local_irq_save(flags); |
| 11743 | - /* Save old context and create impossible VPN2 value */ |
| 11744 | - old_ctx = (read_c0_entryhi() & ASID_MASK); |
| 11745 | - old_pagemask = read_c0_pagemask(); |
| 11746 | - wired = read_c0_wired(); |
| 11747 | - write_c0_wired(wired + 1); |
| 11748 | - write_c0_index(wired); |
| 11749 | - BARRIER; |
| 11750 | - write_c0_pagemask(pagemask); |
| 11751 | - write_c0_entryhi(entryhi); |
| 11752 | - write_c0_entrylo0(entrylo0); |
| 11753 | - write_c0_entrylo1(entrylo1); |
| 11754 | - BARRIER; |
| 11755 | - tlb_write_indexed(); |
| 11756 | - BARRIER; |
| 11757 | - |
| 11758 | - write_c0_entryhi(old_ctx); |
| 11759 | - BARRIER; |
| 11760 | - write_c0_pagemask(old_pagemask); |
| 11761 | - local_flush_tlb_all(); |
| 11762 | - local_irq_restore(flags); |
| 11763 | + unsigned long flags; |
| 11764 | + unsigned long wired; |
| 11765 | + unsigned long old_pagemask; |
| 11766 | + unsigned long old_ctx; |
| 11767 | + |
| 11768 | + local_irq_save(flags); |
| 11769 | + /* Save old context and create impossible VPN2 value */ |
| 11770 | + old_ctx = read_c0_entryhi() & ASID_MASK; |
| 11771 | + old_pagemask = read_c0_pagemask(); |
| 11772 | + wired = read_c0_wired(); |
| 11773 | + write_c0_wired(wired + 1); |
| 11774 | + write_c0_index(wired); |
| 11775 | + BARRIER; |
| 11776 | + write_c0_pagemask(pagemask); |
| 11777 | + write_c0_entryhi(entryhi); |
| 11778 | + write_c0_entrylo0(entrylo0); |
| 11779 | + write_c0_entrylo1(entrylo1); |
| 11780 | + mtc0_tlbw_hazard(); |
| 11781 | + tlb_write_indexed(); |
| 11782 | + tlbw_use_hazard(); |
| 11783 | + |
| 11784 | + write_c0_entryhi(old_ctx); |
| 11785 | + BARRIER; |
| 11786 | + write_c0_pagemask(old_pagemask); |
| 11787 | + local_flush_tlb_all(); |
| 11788 | + local_irq_restore(flags); |
| 11789 | } |
| 11790 | |
| 11791 | /* |
| 11792 | @@ -317,17 +273,15 @@ __init int add_temporary_entry(unsigned |
| 11793 | } |
| 11794 | |
| 11795 | write_c0_index(temp_tlb_entry); |
| 11796 | - BARRIER; |
| 11797 | write_c0_pagemask(pagemask); |
| 11798 | write_c0_entryhi(entryhi); |
| 11799 | write_c0_entrylo0(entrylo0); |
| 11800 | write_c0_entrylo1(entrylo1); |
| 11801 | - BARRIER; |
| 11802 | + mtc0_tlbw_hazard(); |
| 11803 | tlb_write_indexed(); |
| 11804 | - BARRIER; |
| 11805 | + tlbw_use_hazard(); |
| 11806 | |
| 11807 | write_c0_entryhi(old_ctx); |
| 11808 | - BARRIER; |
| 11809 | write_c0_pagemask(old_pagemask); |
| 11810 | out: |
| 11811 | local_irq_restore(flags); |
| 11812 | @@ -348,15 +302,23 @@ static void __init probe_tlb(unsigned lo |
| 11813 | return; |
| 11814 | |
| 11815 | config1 = read_c0_config1(); |
| 11816 | - if (!((config1 >> 7) & 3)) |
| 11817 | - panic("No MMU present"); |
| 11818 | + if (!((config >> 7) & 3)) |
| 11819 | + panic("No TLB present"); |
| 11820 | |
| 11821 | c->tlbsize = ((config1 >> 25) & 0x3f) + 1; |
| 11822 | } |
| 11823 | |
| 11824 | void __init r4k_tlb_init(void) |
| 11825 | { |
| 11826 | - unsigned long config = read_c0_config(); |
| 11827 | + unsigned int config = read_c0_config(); |
| 11828 | + |
| 11829 | + /* |
| 11830 | + * You should never change this register: |
| 11831 | + * - On R4600 1.7 the tlbp never hits for pages smaller than |
| 11832 | + * the value in the c0_pagemask register. |
| 11833 | + * - The entire mm handling assumes the c0_pagemask register to |
| 11834 | + * be set for 4kb pages. |
| 11835 | + */ |
| 11836 | probe_tlb(config); |
| 11837 | write_c0_pagemask(PM_DEFAULT_MASK); |
| 11838 | write_c0_wired(0); |
| 11839 | --- a/drivers/char/au1000_gpio.c |
| 11840 | +++ b/drivers/char/au1000_gpio.c |
| 11841 | @@ -246,7 +246,7 @@ static struct file_operations au1000gpio |
| 11842 | |
| 11843 | static struct miscdevice au1000gpio_miscdev = |
| 11844 | { |
| 11845 | - GPIO_MINOR, |
| 11846 | + MISC_DYNAMIC_MINOR, |
| 11847 | "au1000_gpio", |
| 11848 | &au1000gpio_fops |
| 11849 | }; |
| 11850 | --- /dev/null |
| 11851 | +++ b/drivers/char/au1550_psc_spi.c |
| 11852 | @@ -0,0 +1,466 @@ |
| 11853 | +/* |
| 11854 | + * Driver for Alchemy Au1550 SPI on the PSC. |
| 11855 | + * |
| 11856 | + * Copyright 2004 Embedded Edge, LLC. |
| 11857 | + * dan@embeddededge.com |
| 11858 | + * |
| 11859 | + * This program is free software; you can redistribute it and/or modify it |
| 11860 | + * under the terms of the GNU General Public License as published by the |
| 11861 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 11862 | + * option) any later version. |
| 11863 | + * |
| 11864 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 11865 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 11866 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 11867 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 11868 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 11869 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 11870 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 11871 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 11872 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 11873 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 11874 | + * |
| 11875 | + * You should have received a copy of the GNU General Public License along |
| 11876 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 11877 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 11878 | + */ |
| 11879 | + |
| 11880 | +#include <linux/module.h> |
| 11881 | +#include <linux/config.h> |
| 11882 | +#include <linux/types.h> |
| 11883 | +#include <linux/kernel.h> |
| 11884 | +#include <linux/miscdevice.h> |
| 11885 | +#include <linux/init.h> |
| 11886 | +#include <asm/uaccess.h> |
| 11887 | +#include <asm/io.h> |
| 11888 | +#include <asm/au1000.h> |
| 11889 | +#include <asm/au1550_spi.h> |
| 11890 | +#include <asm/au1xxx_psc.h> |
| 11891 | + |
| 11892 | +#ifdef CONFIG_MIPS_PB1550 |
| 11893 | +#include <asm/pb1550.h> |
| 11894 | +#endif |
| 11895 | + |
| 11896 | +#ifdef CONFIG_MIPS_DB1550 |
| 11897 | +#include <asm/db1x00.h> |
| 11898 | +#endif |
| 11899 | + |
| 11900 | +#ifdef CONFIG_MIPS_PB1200 |
| 11901 | +#include <asm/pb1200.h> |
| 11902 | +#endif |
| 11903 | + |
| 11904 | +/* This is just a simple programmed I/O SPI interface on the PSC of the 1550. |
| 11905 | + * We support open, close, write, and ioctl. The SPI is a full duplex |
| 11906 | + * interface, you can't read without writing. So, the write system call |
| 11907 | + * copies the bytes out to the SPI, and whatever is returned is placed |
| 11908 | + * in the same buffer. Kinda weird, maybe we'll change it, but for now |
| 11909 | + * it works OK. |
| 11910 | + * I didn't implement any DMA yet, and it's a debate about the necessity. |
| 11911 | + * The SPI clocks are usually quite fast, so data is sent/received as |
| 11912 | + * quickly as you can stuff the FIFO. The overhead of DMA and interrupts |
| 11913 | + * are usually far greater than the data transfer itself. If, however, |
| 11914 | + * we find applications that move large amounts of data, we may choose |
| 11915 | + * use the overhead of buffering and DMA to do the work. |
| 11916 | + */ |
| 11917 | + |
| 11918 | +/* The maximum clock rate specified in the manual is 2mHz. |
| 11919 | +*/ |
| 11920 | +#define MAX_BAUD_RATE (2 * 1000000) |
| 11921 | +#define PSC_INTCLK_RATE (32 * 1000000) |
| 11922 | + |
| 11923 | +static int inuse; |
| 11924 | + |
| 11925 | +/* We have to know what the user requested for the data length |
| 11926 | + * so we know how to stuff the fifo. The FIFO is 32 bits wide, |
| 11927 | + * and we have to load it with the bits to go in a single transfer. |
| 11928 | + */ |
| 11929 | +static uint spi_datalen; |
| 11930 | + |
| 11931 | +static int |
| 11932 | +au1550spi_master_done( int ms ) |
| 11933 | +{ |
| 11934 | + int timeout=ms; |
| 11935 | + volatile psc_spi_t *sp; |
| 11936 | + |
| 11937 | + sp = (volatile psc_spi_t *)SPI_PSC_BASE; |
| 11938 | + |
| 11939 | + /* Loop until MD is set or timeout has expired */ |
| 11940 | + while(!(sp->psc_spievent & PSC_SPIEVNT_MD) && timeout--) udelay(1000); |
| 11941 | + |
| 11942 | + if ( !timeout ) |
| 11943 | + return 0; |
| 11944 | + else |
| 11945 | + sp->psc_spievent |= PSC_SPIEVNT_MD; |
| 11946 | + |
| 11947 | + return 1; |
| 11948 | +} |
| 11949 | + |
| 11950 | +static int |
| 11951 | +au1550spi_open(struct inode *inode, struct file *file) |
| 11952 | +{ |
| 11953 | + if (inuse) |
| 11954 | + return -EBUSY; |
| 11955 | + |
| 11956 | + inuse = 1; |
| 11957 | + |
| 11958 | + MOD_INC_USE_COUNT; |
| 11959 | + |
| 11960 | + return 0; |
| 11961 | +} |
| 11962 | + |
| 11963 | +static ssize_t |
| 11964 | +au1550spi_write(struct file *fp, const char *bp, size_t count, loff_t *ppos) |
| 11965 | +{ |
| 11966 | + int bytelen, i; |
| 11967 | + size_t rcount, retval; |
| 11968 | + unsigned char sb, *rp, *wp; |
| 11969 | + uint fifoword, pcr, stat; |
| 11970 | + volatile psc_spi_t *sp; |
| 11971 | + |
| 11972 | + /* Get the number of bytes per transfer. |
| 11973 | + */ |
| 11974 | + bytelen = ((spi_datalen - 1) / 8) + 1; |
| 11975 | + |
| 11976 | + /* User needs to send us multiple of this count. |
| 11977 | + */ |
| 11978 | + if ((count % bytelen) != 0) |
| 11979 | + return -EINVAL; |
| 11980 | + |
| 11981 | + rp = wp = (unsigned char *)bp; |
| 11982 | + retval = rcount = count; |
| 11983 | + |
| 11984 | + /* Reset the FIFO. |
| 11985 | + */ |
| 11986 | + sp = (volatile psc_spi_t *)SPI_PSC_BASE; |
| 11987 | + sp->psc_spipcr = (PSC_SPIPCR_RC | PSC_SPIPCR_TC); |
| 11988 | + au_sync(); |
| 11989 | + do { |
| 11990 | + pcr = sp->psc_spipcr; |
| 11991 | + au_sync(); |
| 11992 | + } while (pcr != 0); |
| 11993 | + |
| 11994 | + /* Prime the transmit FIFO. |
| 11995 | + */ |
| 11996 | + while (count > 0) { |
| 11997 | + fifoword = 0; |
| 11998 | + for (i=0; i<bytelen; i++) { |
| 11999 | + fifoword <<= 8; |
| 12000 | + if (get_user(sb, wp) < 0) |
| 12001 | + return -EFAULT; |
| 12002 | + fifoword |= sb; |
| 12003 | + wp++; |
| 12004 | + } |
| 12005 | + count -= bytelen; |
| 12006 | + if (count <= 0) |
| 12007 | + fifoword |= PSC_SPITXRX_LC; |
| 12008 | + sp->psc_spitxrx = fifoword; |
| 12009 | + au_sync(); |
| 12010 | + stat = sp->psc_spistat; |
| 12011 | + au_sync(); |
| 12012 | + if (stat & PSC_SPISTAT_TF) |
| 12013 | + break; |
| 12014 | + } |
| 12015 | + |
| 12016 | + /* Start the transfer. |
| 12017 | + */ |
| 12018 | + sp->psc_spipcr = PSC_SPIPCR_MS; |
| 12019 | + au_sync(); |
| 12020 | + |
| 12021 | + /* Now, just keep the transmit fifo full and empty the receive. |
| 12022 | + */ |
| 12023 | + while (count > 0) { |
| 12024 | + stat = sp->psc_spistat; |
| 12025 | + au_sync(); |
| 12026 | + while ((stat & PSC_SPISTAT_RE) == 0) { |
| 12027 | + fifoword = sp->psc_spitxrx; |
| 12028 | + au_sync(); |
| 12029 | + for (i=0; i<bytelen; i++) { |
| 12030 | + sb = fifoword & 0xff; |
| 12031 | + if (put_user(sb, rp) < 0) |
| 12032 | + return -EFAULT; |
| 12033 | + fifoword >>= 8; |
| 12034 | + rp++; |
| 12035 | + } |
| 12036 | + rcount -= bytelen; |
| 12037 | + stat = sp->psc_spistat; |
| 12038 | + au_sync(); |
| 12039 | + } |
| 12040 | + if ((stat & PSC_SPISTAT_TF) == 0) { |
| 12041 | + fifoword = 0; |
| 12042 | + for (i=0; i<bytelen; i++) { |
| 12043 | + fifoword <<= 8; |
| 12044 | + if (get_user(sb, wp) < 0) |
| 12045 | + return -EFAULT; |
| 12046 | + fifoword |= sb; |
| 12047 | + wp++; |
| 12048 | + } |
| 12049 | + count -= bytelen; |
| 12050 | + if (count <= 0) |
| 12051 | + fifoword |= PSC_SPITXRX_LC; |
| 12052 | + sp->psc_spitxrx = fifoword; |
| 12053 | + au_sync(); |
| 12054 | + } |
| 12055 | + } |
| 12056 | + |
| 12057 | + /* All of the bytes for transmit have been written. Hang |
| 12058 | + * out waiting for any residual bytes that are yet to be |
| 12059 | + * read from the fifo. |
| 12060 | + */ |
| 12061 | + while (rcount > 0) { |
| 12062 | + stat = sp->psc_spistat; |
| 12063 | + au_sync(); |
| 12064 | + if ((stat & PSC_SPISTAT_RE) == 0) { |
| 12065 | + fifoword = sp->psc_spitxrx; |
| 12066 | + au_sync(); |
| 12067 | + for (i=0; i<bytelen; i++) { |
| 12068 | + sb = fifoword & 0xff; |
| 12069 | + if (put_user(sb, rp) < 0) |
| 12070 | + return -EFAULT; |
| 12071 | + fifoword >>= 8; |
| 12072 | + rp++; |
| 12073 | + } |
| 12074 | + rcount -= bytelen; |
| 12075 | + } |
| 12076 | + } |
| 12077 | + |
| 12078 | + /* Wait for MasterDone event. 30ms timeout */ |
| 12079 | + if (!au1550spi_master_done(30) ) retval = -EFAULT; |
| 12080 | + return retval; |
| 12081 | +} |
| 12082 | + |
| 12083 | +static int |
| 12084 | +au1550spi_release(struct inode *inode, struct file *file) |
| 12085 | +{ |
| 12086 | + MOD_DEC_USE_COUNT; |
| 12087 | + |
| 12088 | + inuse = 0; |
| 12089 | + |
| 12090 | + return 0; |
| 12091 | +} |
| 12092 | + |
| 12093 | +/* Set the baud rate closest to the request, then return the actual |
| 12094 | + * value we are using. |
| 12095 | + */ |
| 12096 | +static uint |
| 12097 | +set_baud_rate(uint baud) |
| 12098 | +{ |
| 12099 | + uint rate, tmpclk, brg, ctl, stat; |
| 12100 | + volatile psc_spi_t *sp; |
| 12101 | + |
| 12102 | + /* For starters, the input clock is divided by two. |
| 12103 | + */ |
| 12104 | + tmpclk = PSC_INTCLK_RATE/2; |
| 12105 | + |
| 12106 | + rate = tmpclk / baud; |
| 12107 | + |
| 12108 | + /* The dividers work as follows: |
| 12109 | + * baud = tmpclk / (2 * (brg + 1)) |
| 12110 | + */ |
| 12111 | + brg = (rate/2) - 1; |
| 12112 | + |
| 12113 | + /* Test BRG to ensure it will fit into the 6 bits allocated. |
| 12114 | + */ |
| 12115 | + |
| 12116 | + /* Make sure the device is disabled while we make the change. |
| 12117 | + */ |
| 12118 | + sp = (volatile psc_spi_t *)SPI_PSC_BASE; |
| 12119 | + ctl = sp->psc_spicfg; |
| 12120 | + au_sync(); |
| 12121 | + sp->psc_spicfg = ctl & ~PSC_SPICFG_DE_ENABLE; |
| 12122 | + au_sync(); |
| 12123 | + ctl = PSC_SPICFG_CLR_BAUD(ctl); |
| 12124 | + ctl |= PSC_SPICFG_SET_BAUD(brg); |
| 12125 | + sp->psc_spicfg = ctl; |
| 12126 | + au_sync(); |
| 12127 | + |
| 12128 | + /* If the device was running prior to getting here, wait for |
| 12129 | + * it to restart. |
| 12130 | + */ |
| 12131 | + if (ctl & PSC_SPICFG_DE_ENABLE) { |
| 12132 | + do { |
| 12133 | + stat = sp->psc_spistat; |
| 12134 | + au_sync(); |
| 12135 | + } while ((stat & PSC_SPISTAT_DR) == 0); |
| 12136 | + } |
| 12137 | + |
| 12138 | + /* Return the actual value. |
| 12139 | + */ |
| 12140 | + rate = tmpclk / (2 * (brg + 1)); |
| 12141 | + |
| 12142 | + return(rate); |
| 12143 | +} |
| 12144 | + |
| 12145 | +static uint |
| 12146 | +set_word_len(uint len) |
| 12147 | +{ |
| 12148 | + uint ctl, stat; |
| 12149 | + volatile psc_spi_t *sp; |
| 12150 | + |
| 12151 | + if ((len < 4) || (len > 24)) |
| 12152 | + return -EINVAL; |
| 12153 | + |
| 12154 | + /* Make sure the device is disabled while we make the change. |
| 12155 | + */ |
| 12156 | + sp = (volatile psc_spi_t *)SPI_PSC_BASE; |
| 12157 | + ctl = sp->psc_spicfg; |
| 12158 | + au_sync(); |
| 12159 | + sp->psc_spicfg = ctl & ~PSC_SPICFG_DE_ENABLE; |
| 12160 | + au_sync(); |
| 12161 | + ctl = PSC_SPICFG_CLR_LEN(ctl); |
| 12162 | + ctl |= PSC_SPICFG_SET_LEN(len); |
| 12163 | + sp->psc_spicfg = ctl; |
| 12164 | + au_sync(); |
| 12165 | + |
| 12166 | + /* If the device was running prior to getting here, wait for |
| 12167 | + * it to restart. |
| 12168 | + */ |
| 12169 | + if (ctl & PSC_SPICFG_DE_ENABLE) { |
| 12170 | + do { |
| 12171 | + stat = sp->psc_spistat; |
| 12172 | + au_sync(); |
| 12173 | + } while ((stat & PSC_SPISTAT_DR) == 0); |
| 12174 | + } |
| 12175 | + |
| 12176 | + return 0; |
| 12177 | +} |
| 12178 | + |
| 12179 | +static int |
| 12180 | +au1550spi_ioctl(struct inode *inode, struct file *file, |
| 12181 | + unsigned int cmd, unsigned long arg) |
| 12182 | +{ |
| 12183 | + int status; |
| 12184 | + u32 val; |
| 12185 | + |
| 12186 | + status = 0; |
| 12187 | + |
| 12188 | + switch(cmd) { |
| 12189 | + case AU1550SPI_WORD_LEN: |
| 12190 | + status = set_word_len(arg); |
| 12191 | + break; |
| 12192 | + |
| 12193 | + case AU1550SPI_SET_BAUD: |
| 12194 | + if (get_user(val, (u32 *)arg)) |
| 12195 | + return -EFAULT; |
| 12196 | + |
| 12197 | + val = set_baud_rate(val); |
| 12198 | + if (put_user(val, (u32 *)arg)) |
| 12199 | + return -EFAULT; |
| 12200 | + break; |
| 12201 | + |
| 12202 | + default: |
| 12203 | + status = -ENOIOCTLCMD; |
| 12204 | + |
| 12205 | + } |
| 12206 | + |
| 12207 | + return status; |
| 12208 | +} |
| 12209 | + |
| 12210 | + |
| 12211 | +static struct file_operations au1550spi_fops = |
| 12212 | +{ |
| 12213 | + owner: THIS_MODULE, |
| 12214 | + write: au1550spi_write, |
| 12215 | + ioctl: au1550spi_ioctl, |
| 12216 | + open: au1550spi_open, |
| 12217 | + release: au1550spi_release, |
| 12218 | +}; |
| 12219 | + |
| 12220 | + |
| 12221 | +static struct miscdevice au1550spi_miscdev = |
| 12222 | +{ |
| 12223 | + MISC_DYNAMIC_MINOR, |
| 12224 | + "au1550_spi", |
| 12225 | + &au1550spi_fops |
| 12226 | +}; |
| 12227 | + |
| 12228 | + |
| 12229 | +int __init |
| 12230 | +au1550spi_init(void) |
| 12231 | +{ |
| 12232 | + uint clk, rate, stat; |
| 12233 | + volatile psc_spi_t *sp; |
| 12234 | + |
| 12235 | + /* Wire up Freq3 as a clock for the SPI. The PSC does |
| 12236 | + * factor of 2 divisor, so run a higher rate so we can |
| 12237 | + * get some granularity to the clock speeds. |
| 12238 | + * We can't do this in board set up because the frequency |
| 12239 | + * is computed too late. |
| 12240 | + */ |
| 12241 | + rate = get_au1x00_speed(); |
| 12242 | + rate /= PSC_INTCLK_RATE; |
| 12243 | + |
| 12244 | + /* The FRDIV in the frequency control is (FRDIV + 1) * 2 |
| 12245 | + */ |
| 12246 | + rate /=2; |
| 12247 | + rate--; |
| 12248 | + clk = au_readl(SYS_FREQCTRL1); |
| 12249 | + au_sync(); |
| 12250 | + clk &= ~SYS_FC_FRDIV3_MASK; |
| 12251 | + clk |= (rate << SYS_FC_FRDIV3_BIT); |
| 12252 | + clk |= SYS_FC_FE3; |
| 12253 | + au_writel(clk, SYS_FREQCTRL1); |
| 12254 | + au_sync(); |
| 12255 | + |
| 12256 | + /* Set up the clock source routing to get Freq3 to PSC0_intclk. |
| 12257 | + */ |
| 12258 | + clk = au_readl(SYS_CLKSRC); |
| 12259 | + au_sync(); |
| 12260 | + clk &= ~0x03e0; |
| 12261 | + clk |= (5 << 7); |
| 12262 | + au_writel(clk, SYS_CLKSRC); |
| 12263 | + au_sync(); |
| 12264 | + |
| 12265 | + /* Set up GPIO pin function to drive PSC0_SYNC1, which is |
| 12266 | + * the SPI Select. |
| 12267 | + */ |
| 12268 | + clk = au_readl(SYS_PINFUNC); |
| 12269 | + au_sync(); |
| 12270 | + clk |= 1; |
| 12271 | + au_writel(clk, SYS_PINFUNC); |
| 12272 | + au_sync(); |
| 12273 | + |
| 12274 | + /* Now, set up the PSC for SPI PIO mode. |
| 12275 | + */ |
| 12276 | + sp = (volatile psc_spi_t *)SPI_PSC_BASE; |
| 12277 | + sp->psc_ctrl = PSC_CTRL_DISABLE; |
| 12278 | + au_sync(); |
| 12279 | + sp->psc_sel = PSC_SEL_PS_SPIMODE; |
| 12280 | + sp->psc_spicfg = 0; |
| 12281 | + au_sync(); |
| 12282 | + sp->psc_ctrl = PSC_CTRL_ENABLE; |
| 12283 | + au_sync(); |
| 12284 | + do { |
| 12285 | + stat = sp->psc_spistat; |
| 12286 | + au_sync(); |
| 12287 | + } while ((stat & PSC_SPISTAT_SR) == 0); |
| 12288 | + |
| 12289 | + sp->psc_spicfg = (PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8 | |
| 12290 | + PSC_SPICFG_DD_DISABLE | PSC_SPICFG_MO); |
| 12291 | + sp->psc_spicfg |= PSC_SPICFG_SET_LEN(8); |
| 12292 | + spi_datalen = 8; |
| 12293 | + sp->psc_spimsk = PSC_SPIMSK_ALLMASK; |
| 12294 | + au_sync(); |
| 12295 | + |
| 12296 | + set_baud_rate(1000000); |
| 12297 | + |
| 12298 | + sp->psc_spicfg |= PSC_SPICFG_DE_ENABLE; |
| 12299 | + do { |
| 12300 | + stat = sp->psc_spistat; |
| 12301 | + au_sync(); |
| 12302 | + } while ((stat & PSC_SPISTAT_DR) == 0); |
| 12303 | + |
| 12304 | + misc_register(&au1550spi_miscdev); |
| 12305 | + printk("Au1550 SPI driver\n"); |
| 12306 | + return 0; |
| 12307 | +} |
| 12308 | + |
| 12309 | + |
| 12310 | +void __exit |
| 12311 | +au1550spi_exit(void) |
| 12312 | +{ |
| 12313 | + misc_deregister(&au1550spi_miscdev); |
| 12314 | +} |
| 12315 | + |
| 12316 | + |
| 12317 | +module_init(au1550spi_init); |
| 12318 | +module_exit(au1550spi_exit); |
| 12319 | --- a/drivers/char/Config.in |
| 12320 | +++ b/drivers/char/Config.in |
| 12321 | @@ -322,14 +322,11 @@ fi |
| 12322 | if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then |
| 12323 | bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8 |
| 12324 | fi |
| 12325 | -if [ "$CONFIG_MIPS" = "y" -a "$CONFIG_NEW_TIME_C" = "y" ]; then |
| 12326 | - tristate 'Generic MIPS RTC Support' CONFIG_MIPS_RTC |
| 12327 | -fi |
| 12328 | if [ "$CONFIG_SGI_IP22" = "y" ]; then |
| 12329 | - bool 'SGI DS1286 RTC support' CONFIG_SGI_DS1286 |
| 12330 | + tristate 'Dallas DS1286 RTC support' CONFIG_DS1286 |
| 12331 | fi |
| 12332 | if [ "$CONFIG_SGI_IP27" = "y" ]; then |
| 12333 | - bool 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC |
| 12334 | + tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC |
| 12335 | fi |
| 12336 | if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then |
| 12337 | tristate 'Dallas DS1742 RTC support' CONFIG_DS1742 |
| 12338 | @@ -392,6 +389,11 @@ if [ "$CONFIG_DRM" = "y" ]; then |
| 12339 | source drivers/char/drm/Config.in |
| 12340 | fi |
| 12341 | fi |
| 12342 | + |
| 12343 | +if [ "$CONFIG_X86" = "y" ]; then |
| 12344 | + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE |
| 12345 | +fi |
| 12346 | + |
| 12347 | endmenu |
| 12348 | |
| 12349 | if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then |
| 12350 | @@ -400,6 +402,7 @@ fi |
| 12351 | if [ "$CONFIG_SOC_AU1X00" = "y" ]; then |
| 12352 | tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO |
| 12353 | tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846 |
| 12354 | + #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI |
| 12355 | fi |
| 12356 | if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then |
| 12357 | tristate ' ITE GPIO' CONFIG_ITE_GPIO |
| 12358 | --- a/drivers/char/decserial.c |
| 12359 | +++ b/drivers/char/decserial.c |
| 12360 | @@ -3,95 +3,105 @@ |
| 12361 | * choose the right serial device at boot time |
| 12362 | * |
| 12363 | * triemer 6-SEP-1998 |
| 12364 | - * sercons.c is designed to allow the three different kinds |
| 12365 | + * sercons.c is designed to allow the three different kinds |
| 12366 | * of serial devices under the decstation world to co-exist |
| 12367 | - * in the same kernel. The idea here is to abstract |
| 12368 | + * in the same kernel. The idea here is to abstract |
| 12369 | * the pieces of the drivers that are common to this file |
| 12370 | * so that they do not clash at compile time and runtime. |
| 12371 | * |
| 12372 | * HK 16-SEP-1998 v0.002 |
| 12373 | * removed the PROM console as this is not a real serial |
| 12374 | * device. Added support for PROM console in drivers/char/tty_io.c |
| 12375 | - * instead. Although it may work to enable more than one |
| 12376 | + * instead. Although it may work to enable more than one |
| 12377 | * console device I strongly recommend to use only one. |
| 12378 | + * |
| 12379 | + * Copyright (C) 2004 Maciej W. Rozycki |
| 12380 | */ |
| 12381 | |
| 12382 | #include <linux/config.h> |
| 12383 | +#include <linux/errno.h> |
| 12384 | #include <linux/init.h> |
| 12385 | + |
| 12386 | #include <asm/dec/machtype.h> |
| 12387 | +#include <asm/dec/serial.h> |
| 12388 | + |
| 12389 | +extern int register_zs_hook(unsigned int channel, |
| 12390 | + struct dec_serial_hook *hook); |
| 12391 | +extern int unregister_zs_hook(unsigned int channel); |
| 12392 | + |
| 12393 | +extern int register_dz_hook(unsigned int channel, |
| 12394 | + struct dec_serial_hook *hook); |
| 12395 | +extern int unregister_dz_hook(unsigned int channel); |
| 12396 | |
| 12397 | +int register_dec_serial_hook(unsigned int channel, |
| 12398 | + struct dec_serial_hook *hook) |
| 12399 | +{ |
| 12400 | #ifdef CONFIG_ZS |
| 12401 | -extern int zs_init(void); |
| 12402 | + if (IOASIC) |
| 12403 | + return register_zs_hook(channel, hook); |
| 12404 | #endif |
| 12405 | - |
| 12406 | #ifdef CONFIG_DZ |
| 12407 | -extern int dz_init(void); |
| 12408 | + if (!IOASIC) |
| 12409 | + return register_dz_hook(channel, hook); |
| 12410 | #endif |
| 12411 | + return 0; |
| 12412 | +} |
| 12413 | |
| 12414 | -#ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 12415 | - |
| 12416 | +int unregister_dec_serial_hook(unsigned int channel) |
| 12417 | +{ |
| 12418 | #ifdef CONFIG_ZS |
| 12419 | -extern void zs_serial_console_init(void); |
| 12420 | + if (IOASIC) |
| 12421 | + return unregister_zs_hook(channel); |
| 12422 | #endif |
| 12423 | - |
| 12424 | #ifdef CONFIG_DZ |
| 12425 | -extern void dz_serial_console_init(void); |
| 12426 | -#endif |
| 12427 | - |
| 12428 | + if (!IOASIC) |
| 12429 | + return unregister_dz_hook(channel); |
| 12430 | #endif |
| 12431 | + return 0; |
| 12432 | +} |
| 12433 | |
| 12434 | -/* rs_init - starts up the serial interface - |
| 12435 | - handle normal case of starting up the serial interface */ |
| 12436 | |
| 12437 | -#ifdef CONFIG_SERIAL_DEC |
| 12438 | +extern int zs_init(void); |
| 12439 | +extern int dz_init(void); |
| 12440 | |
| 12441 | +/* |
| 12442 | + * rs_init - starts up the serial interface - |
| 12443 | + * handle normal case of starting up the serial interface |
| 12444 | + */ |
| 12445 | int __init rs_init(void) |
| 12446 | { |
| 12447 | - |
| 12448 | -#if defined(CONFIG_ZS) && defined(CONFIG_DZ) |
| 12449 | - if (IOASIC) |
| 12450 | - return zs_init(); |
| 12451 | - else |
| 12452 | - return dz_init(); |
| 12453 | -#else |
| 12454 | - |
| 12455 | #ifdef CONFIG_ZS |
| 12456 | - return zs_init(); |
| 12457 | + if (IOASIC) |
| 12458 | + return zs_init(); |
| 12459 | #endif |
| 12460 | - |
| 12461 | #ifdef CONFIG_DZ |
| 12462 | - return dz_init(); |
| 12463 | -#endif |
| 12464 | - |
| 12465 | + if (!IOASIC) |
| 12466 | + return dz_init(); |
| 12467 | #endif |
| 12468 | + return -ENXIO; |
| 12469 | } |
| 12470 | |
| 12471 | __initcall(rs_init); |
| 12472 | |
| 12473 | -#endif |
| 12474 | |
| 12475 | #ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 12476 | |
| 12477 | -/* dec_serial_console_init handles the special case of starting |
| 12478 | - * up the console on the serial port |
| 12479 | +extern void zs_serial_console_init(void); |
| 12480 | +extern void dz_serial_console_init(void); |
| 12481 | + |
| 12482 | +/* |
| 12483 | + * dec_serial_console_init handles the special case of starting |
| 12484 | + * up the console on the serial port |
| 12485 | */ |
| 12486 | void __init dec_serial_console_init(void) |
| 12487 | { |
| 12488 | -#if defined(CONFIG_ZS) && defined(CONFIG_DZ) |
| 12489 | - if (IOASIC) |
| 12490 | - zs_serial_console_init(); |
| 12491 | - else |
| 12492 | - dz_serial_console_init(); |
| 12493 | -#else |
| 12494 | - |
| 12495 | #ifdef CONFIG_ZS |
| 12496 | - zs_serial_console_init(); |
| 12497 | + if (IOASIC) |
| 12498 | + zs_serial_console_init(); |
| 12499 | #endif |
| 12500 | - |
| 12501 | #ifdef CONFIG_DZ |
| 12502 | - dz_serial_console_init(); |
| 12503 | -#endif |
| 12504 | - |
| 12505 | + if (!IOASIC) |
| 12506 | + dz_serial_console_init(); |
| 12507 | #endif |
| 12508 | } |
| 12509 | |
| 12510 | --- a/drivers/char/ds1286.c |
| 12511 | +++ b/drivers/char/ds1286.c |
| 12512 | @@ -1,6 +1,10 @@ |
| 12513 | /* |
| 12514 | * DS1286 Real Time Clock interface for Linux |
| 12515 | * |
| 12516 | + * Copyright (C) 2003 TimeSys Corp. |
| 12517 | + * S. James Hill (James.Hill@timesys.com) |
| 12518 | + * (sjhill@realitydiluted.com) |
| 12519 | + * |
| 12520 | * Copyright (C) 1998, 1999, 2000 Ralf Baechle |
| 12521 | * |
| 12522 | * Based on code written by Paul Gortmaker. |
| 12523 | @@ -29,6 +33,7 @@ |
| 12524 | #include <linux/types.h> |
| 12525 | #include <linux/errno.h> |
| 12526 | #include <linux/miscdevice.h> |
| 12527 | +#include <linux/module.h> |
| 12528 | #include <linux/slab.h> |
| 12529 | #include <linux/ioport.h> |
| 12530 | #include <linux/fcntl.h> |
| 12531 | @@ -95,6 +100,12 @@ static ssize_t ds1286_read(struct file * |
| 12532 | return -EIO; |
| 12533 | } |
| 12534 | |
| 12535 | +void rtc_ds1286_wait(void) |
| 12536 | +{ |
| 12537 | + unsigned char sec = CMOS_READ(RTC_SECONDS); |
| 12538 | + while (sec == CMOS_READ(RTC_SECONDS)); |
| 12539 | +} |
| 12540 | + |
| 12541 | static int ds1286_ioctl(struct inode *inode, struct file *file, |
| 12542 | unsigned int cmd, unsigned long arg) |
| 12543 | { |
| 12544 | @@ -249,23 +260,22 @@ static int ds1286_open(struct inode *ino |
| 12545 | { |
| 12546 | spin_lock_irq(&ds1286_lock); |
| 12547 | |
| 12548 | - if (ds1286_status & RTC_IS_OPEN) |
| 12549 | - goto out_busy; |
| 12550 | + if (ds1286_status & RTC_IS_OPEN) { |
| 12551 | + spin_unlock_irq(&ds1286_lock); |
| 12552 | + return -EBUSY; |
| 12553 | + } |
| 12554 | |
| 12555 | ds1286_status |= RTC_IS_OPEN; |
| 12556 | |
| 12557 | - spin_lock_irq(&ds1286_lock); |
| 12558 | + spin_unlock_irq(&ds1286_lock); |
| 12559 | return 0; |
| 12560 | - |
| 12561 | -out_busy: |
| 12562 | - spin_lock_irq(&ds1286_lock); |
| 12563 | - return -EBUSY; |
| 12564 | } |
| 12565 | |
| 12566 | static int ds1286_release(struct inode *inode, struct file *file) |
| 12567 | { |
| 12568 | + spin_lock_irq(&ds1286_lock); |
| 12569 | ds1286_status &= ~RTC_IS_OPEN; |
| 12570 | - |
| 12571 | + spin_unlock_irq(&ds1286_lock); |
| 12572 | return 0; |
| 12573 | } |
| 12574 | |
| 12575 | @@ -276,32 +286,6 @@ static unsigned int ds1286_poll(struct f |
| 12576 | return 0; |
| 12577 | } |
| 12578 | |
| 12579 | -/* |
| 12580 | - * The various file operations we support. |
| 12581 | - */ |
| 12582 | - |
| 12583 | -static struct file_operations ds1286_fops = { |
| 12584 | - .llseek = no_llseek, |
| 12585 | - .read = ds1286_read, |
| 12586 | - .poll = ds1286_poll, |
| 12587 | - .ioctl = ds1286_ioctl, |
| 12588 | - .open = ds1286_open, |
| 12589 | - .release = ds1286_release, |
| 12590 | -}; |
| 12591 | - |
| 12592 | -static struct miscdevice ds1286_dev= |
| 12593 | -{ |
| 12594 | - .minor = RTC_MINOR, |
| 12595 | - .name = "rtc", |
| 12596 | - .fops = &ds1286_fops, |
| 12597 | -}; |
| 12598 | - |
| 12599 | -int __init ds1286_init(void) |
| 12600 | -{ |
| 12601 | - printk(KERN_INFO "DS1286 Real Time Clock Driver v%s\n", DS1286_VERSION); |
| 12602 | - return misc_register(&ds1286_dev); |
| 12603 | -} |
| 12604 | - |
| 12605 | static char *days[] = { |
| 12606 | "***", "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" |
| 12607 | }; |
| 12608 | @@ -528,3 +512,38 @@ void ds1286_get_alm_time(struct rtc_time |
| 12609 | BCD_TO_BIN(alm_tm->tm_hour); |
| 12610 | alm_tm->tm_sec = 0; |
| 12611 | } |
| 12612 | + |
| 12613 | +static struct file_operations ds1286_fops = { |
| 12614 | + .owner = THIS_MODULE, |
| 12615 | + .llseek = no_llseek, |
| 12616 | + .read = ds1286_read, |
| 12617 | + .poll = ds1286_poll, |
| 12618 | + .ioctl = ds1286_ioctl, |
| 12619 | + .open = ds1286_open, |
| 12620 | + .release = ds1286_release, |
| 12621 | +}; |
| 12622 | + |
| 12623 | +static struct miscdevice ds1286_dev = |
| 12624 | +{ |
| 12625 | + .minor = RTC_MINOR, |
| 12626 | + .name = "rtc", |
| 12627 | + .fops = &ds1286_fops, |
| 12628 | +}; |
| 12629 | + |
| 12630 | +static int __init ds1286_init(void) |
| 12631 | +{ |
| 12632 | + printk(KERN_INFO "DS1286 Real Time Clock Driver v%s\n", DS1286_VERSION); |
| 12633 | + return misc_register(&ds1286_dev); |
| 12634 | +} |
| 12635 | + |
| 12636 | +static void __exit ds1286_exit(void) |
| 12637 | +{ |
| 12638 | + misc_deregister(&ds1286_dev); |
| 12639 | +} |
| 12640 | + |
| 12641 | +module_init(ds1286_init); |
| 12642 | +module_exit(ds1286_exit); |
| 12643 | +EXPORT_NO_SYMBOLS; |
| 12644 | + |
| 12645 | +MODULE_AUTHOR("Ralf Baechle"); |
| 12646 | +MODULE_LICENSE("GPL"); |
| 12647 | --- a/drivers/char/ds1742.c |
| 12648 | +++ b/drivers/char/ds1742.c |
| 12649 | @@ -142,6 +142,7 @@ static int rtc_ds1742_set_time(unsigned |
| 12650 | CMOS_WRITE(RTC_WRITE, RTC_CONTROL); |
| 12651 | |
| 12652 | /* convert */ |
| 12653 | + memset(&tm, 0, sizeof(struct rtc_time)); |
| 12654 | to_tm(t, &tm); |
| 12655 | |
| 12656 | /* check each field one by one */ |
| 12657 | @@ -216,6 +217,7 @@ static int get_ds1742_status(char *buf) |
| 12658 | unsigned long curr_time; |
| 12659 | |
| 12660 | curr_time = rtc_ds1742_get_time(); |
| 12661 | + memset(&tm, 0, sizeof(struct rtc_time)); |
| 12662 | to_tm(curr_time, &tm); |
| 12663 | |
| 12664 | p = buf; |
| 12665 | @@ -251,8 +253,8 @@ static int ds1742_read_proc(char *page, |
| 12666 | |
| 12667 | void rtc_ds1742_wait(void) |
| 12668 | { |
| 12669 | - while (CMOS_READ(RTC_SECONDS) & 1); |
| 12670 | - while (!(CMOS_READ(RTC_SECONDS) & 1)); |
| 12671 | + unsigned char sec = CMOS_READ(RTC_SECONDS); |
| 12672 | + while (sec == CMOS_READ(RTC_SECONDS)); |
| 12673 | } |
| 12674 | |
| 12675 | static int ds1742_ioctl(struct inode *inode, struct file *file, |
| 12676 | @@ -264,6 +266,7 @@ static int ds1742_ioctl(struct inode *in |
| 12677 | switch (cmd) { |
| 12678 | case RTC_RD_TIME: /* Read the time/date from RTC */ |
| 12679 | curr_time = rtc_ds1742_get_time(); |
| 12680 | + memset(&rtc_tm, 0, sizeof(struct rtc_time)); |
| 12681 | to_tm(curr_time, &rtc_tm); |
| 12682 | rtc_tm.tm_year -= 1900; |
| 12683 | return copy_to_user((void *) arg, &rtc_tm, sizeof(rtc_tm)) ? |
| 12684 | --- a/drivers/char/dummy_keyb.c |
| 12685 | +++ b/drivers/char/dummy_keyb.c |
| 12686 | @@ -141,3 +141,7 @@ void __init kbd_init_hw(void) |
| 12687 | { |
| 12688 | printk("Dummy keyboard driver installed.\n"); |
| 12689 | } |
| 12690 | +#ifdef CONFIG_MAGIC_SYSRQ |
| 12691 | +unsigned char kbd_sysrq_key; |
| 12692 | +unsigned char kbd_sysrq_xlate[128]; |
| 12693 | +#endif |
| 12694 | --- a/drivers/char/dz.c |
| 12695 | +++ b/drivers/char/dz.c |
| 12696 | @@ -1,11 +1,13 @@ |
| 12697 | /* |
| 12698 | - * dz.c: Serial port driver for DECStations equiped |
| 12699 | + * dz.c: Serial port driver for DECstations equipped |
| 12700 | * with the DZ chipset. |
| 12701 | * |
| 12702 | * Copyright (C) 1998 Olivier A. D. Lebaillif |
| 12703 | * |
| 12704 | * Email: olivier.lebaillif@ifrsys.com |
| 12705 | * |
| 12706 | + * Copyright (C) 2004 Maciej W. Rozycki |
| 12707 | + * |
| 12708 | * [31-AUG-98] triemer |
| 12709 | * Changed IRQ to use Harald's dec internals interrupts.h |
| 12710 | * removed base_addr code - moving address assignment to setup.c |
| 12711 | @@ -24,6 +26,7 @@ |
| 12712 | #undef DEBUG_DZ |
| 12713 | |
| 12714 | #include <linux/config.h> |
| 12715 | +#include <linux/delay.h> |
| 12716 | #include <linux/version.h> |
| 12717 | #include <linux/kernel.h> |
| 12718 | #include <linux/sched.h> |
| 12719 | @@ -54,33 +57,56 @@ |
| 12720 | #include <asm/system.h> |
| 12721 | #include <asm/uaccess.h> |
| 12722 | |
| 12723 | -#define CONSOLE_LINE (3) /* for definition of struct console */ |
| 12724 | +#ifdef CONFIG_MAGIC_SYSRQ |
| 12725 | +#include <linux/sysrq.h> |
| 12726 | +#endif |
| 12727 | |
| 12728 | #include "dz.h" |
| 12729 | |
| 12730 | -#define DZ_INTR_DEBUG 1 |
| 12731 | - |
| 12732 | DECLARE_TASK_QUEUE(tq_serial); |
| 12733 | |
| 12734 | -static struct dz_serial *lines[4]; |
| 12735 | -static unsigned char tmp_buffer[256]; |
| 12736 | +static struct dz_serial multi[DZ_NB_PORT]; /* Four serial lines in the DZ chip */ |
| 12737 | +static struct tty_driver serial_driver, callout_driver; |
| 12738 | + |
| 12739 | +static struct tty_struct *serial_table[DZ_NB_PORT]; |
| 12740 | +static struct termios *serial_termios[DZ_NB_PORT]; |
| 12741 | +static struct termios *serial_termios_locked[DZ_NB_PORT]; |
| 12742 | + |
| 12743 | +static int serial_refcount; |
| 12744 | |
| 12745 | -#ifdef DEBUG_DZ |
| 12746 | /* |
| 12747 | - * debugging code to send out chars via prom |
| 12748 | + * tmp_buf is used as a temporary buffer by serial_write. We need to |
| 12749 | + * lock it in case the copy_from_user blocks while swapping in a page, |
| 12750 | + * and some other program tries to do a serial write at the same time. |
| 12751 | + * Since the lock will only come under contention when the system is |
| 12752 | + * swapping and available memory is low, it makes sense to share one |
| 12753 | + * buffer across all the serial ports, since it significantly saves |
| 12754 | + * memory if large numbers of serial ports are open. |
| 12755 | */ |
| 12756 | -static void debug_console(const char *s, int count) |
| 12757 | -{ |
| 12758 | - unsigned i; |
| 12759 | +static unsigned char *tmp_buf; |
| 12760 | +static DECLARE_MUTEX(tmp_buf_sem); |
| 12761 | |
| 12762 | - for (i = 0; i < count; i++) { |
| 12763 | - if (*s == 10) |
| 12764 | - prom_printf("%c", 13); |
| 12765 | - prom_printf("%c", *s++); |
| 12766 | - } |
| 12767 | -} |
| 12768 | +static char *dz_name __initdata = "DECstation DZ serial driver version "; |
| 12769 | +static char *dz_version __initdata = "1.03"; |
| 12770 | + |
| 12771 | +static struct dz_serial *lines[DZ_NB_PORT]; |
| 12772 | +static unsigned char tmp_buffer[256]; |
| 12773 | + |
| 12774 | +#ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 12775 | +static struct console dz_sercons; |
| 12776 | +#endif |
| 12777 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 12778 | + !defined(MODULE) |
| 12779 | +static unsigned long break_pressed; /* break, really ... */ |
| 12780 | #endif |
| 12781 | |
| 12782 | +static void change_speed (struct dz_serial *); |
| 12783 | + |
| 12784 | +static int baud_table[] = { |
| 12785 | + 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, |
| 12786 | + 9600, 0 |
| 12787 | +}; |
| 12788 | + |
| 12789 | /* |
| 12790 | * ------------------------------------------------------------ |
| 12791 | * dz_in () and dz_out () |
| 12792 | @@ -94,15 +120,16 @@ static inline unsigned short dz_in(struc |
| 12793 | { |
| 12794 | volatile unsigned short *addr = |
| 12795 | (volatile unsigned short *) (info->port + offset); |
| 12796 | + |
| 12797 | return *addr; |
| 12798 | } |
| 12799 | |
| 12800 | static inline void dz_out(struct dz_serial *info, unsigned offset, |
| 12801 | unsigned short value) |
| 12802 | { |
| 12803 | - |
| 12804 | volatile unsigned short *addr = |
| 12805 | (volatile unsigned short *) (info->port + offset); |
| 12806 | + |
| 12807 | *addr = value; |
| 12808 | } |
| 12809 | |
| 12810 | @@ -143,25 +170,24 @@ static void dz_start(struct tty_struct * |
| 12811 | |
| 12812 | tmp |= mask; /* set the TX flag */ |
| 12813 | dz_out(info, DZ_TCR, tmp); |
| 12814 | - |
| 12815 | } |
| 12816 | |
| 12817 | /* |
| 12818 | * ------------------------------------------------------------ |
| 12819 | - * Here starts the interrupt handling routines. All of the |
| 12820 | - * following subroutines are declared as inline and are folded |
| 12821 | - * into dz_interrupt. They were separated out for readability's |
| 12822 | - * sake. |
| 12823 | * |
| 12824 | - * Note: rs_interrupt() is a "fast" interrupt, which means that it |
| 12825 | + * Here starts the interrupt handling routines. All of the following |
| 12826 | + * subroutines are declared as inline and are folded into |
| 12827 | + * dz_interrupt(). They were separated out for readability's sake. |
| 12828 | + * |
| 12829 | + * Note: dz_interrupt() is a "fast" interrupt, which means that it |
| 12830 | * runs with interrupts turned off. People who may want to modify |
| 12831 | - * rs_interrupt() should try to keep the interrupt handler as fast as |
| 12832 | + * dz_interrupt() should try to keep the interrupt handler as fast as |
| 12833 | * possible. After you are done making modifications, it is not a bad |
| 12834 | * idea to do: |
| 12835 | * |
| 12836 | * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer dz.c |
| 12837 | * |
| 12838 | - * and look at the resulting assemble code in serial.s. |
| 12839 | + * and look at the resulting assemble code in dz.s. |
| 12840 | * |
| 12841 | * ------------------------------------------------------------ |
| 12842 | */ |
| 12843 | @@ -188,101 +214,97 @@ static inline void dz_sched_event(struct |
| 12844 | * This routine deals with inputs from any lines. |
| 12845 | * ------------------------------------------------------------ |
| 12846 | */ |
| 12847 | -static inline void receive_chars(struct dz_serial *info_in) |
| 12848 | +static inline void receive_chars(struct dz_serial *info_in, |
| 12849 | + struct pt_regs *regs) |
| 12850 | { |
| 12851 | - |
| 12852 | struct dz_serial *info; |
| 12853 | - struct tty_struct *tty = 0; |
| 12854 | + struct tty_struct *tty; |
| 12855 | struct async_icount *icount; |
| 12856 | - int ignore = 0; |
| 12857 | - unsigned short status, tmp; |
| 12858 | - unsigned char ch; |
| 12859 | - |
| 12860 | - /* this code is going to be a problem... |
| 12861 | - the call to tty_flip_buffer is going to need |
| 12862 | - to be rethought... |
| 12863 | - */ |
| 12864 | - do { |
| 12865 | - status = dz_in(info_in, DZ_RBUF); |
| 12866 | - info = lines[LINE(status)]; |
| 12867 | + int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 }; |
| 12868 | + unsigned short status; |
| 12869 | + unsigned char ch, flag; |
| 12870 | + int i; |
| 12871 | |
| 12872 | - /* punt so we don't get duplicate characters */ |
| 12873 | - if (!(status & DZ_DVAL)) |
| 12874 | - goto ignore_char; |
| 12875 | - |
| 12876 | - ch = UCHAR(status); /* grab the char */ |
| 12877 | - |
| 12878 | -#if 0 |
| 12879 | - if (info->is_console) { |
| 12880 | - if (ch == 0) |
| 12881 | - return; /* it's a break ... */ |
| 12882 | - } |
| 12883 | -#endif |
| 12884 | + while ((status = dz_in(info_in, DZ_RBUF)) & DZ_DVAL) { |
| 12885 | + info = lines[LINE(status)]; |
| 12886 | + tty = info->tty; /* point to the proper dev */ |
| 12887 | |
| 12888 | - tty = info->tty; /* now tty points to the proper dev */ |
| 12889 | - icount = &info->icount; |
| 12890 | + ch = UCHAR(status); /* grab the char */ |
| 12891 | |
| 12892 | - if (!tty) |
| 12893 | - break; |
| 12894 | - if (tty->flip.count >= TTY_FLIPBUF_SIZE) |
| 12895 | - break; |
| 12896 | + if (!tty && (!info->hook || !info->hook->rx_char)) |
| 12897 | + continue; |
| 12898 | |
| 12899 | - *tty->flip.char_buf_ptr = ch; |
| 12900 | - *tty->flip.flag_buf_ptr = 0; |
| 12901 | + icount = &info->icount; |
| 12902 | icount->rx++; |
| 12903 | |
| 12904 | - /* keep track of the statistics */ |
| 12905 | - if (status & (DZ_OERR | DZ_FERR | DZ_PERR)) { |
| 12906 | - if (status & DZ_PERR) /* parity error */ |
| 12907 | - icount->parity++; |
| 12908 | - else if (status & DZ_FERR) /* frame error */ |
| 12909 | - icount->frame++; |
| 12910 | - if (status & DZ_OERR) /* overrun error */ |
| 12911 | - icount->overrun++; |
| 12912 | - |
| 12913 | - /* check to see if we should ignore the character |
| 12914 | - and mask off conditions that should be ignored |
| 12915 | + flag = 0; |
| 12916 | + if (status & DZ_FERR) { /* frame error */ |
| 12917 | + /* |
| 12918 | + * There is no separate BREAK status bit, so |
| 12919 | + * treat framing errors as BREAKs for Magic SysRq |
| 12920 | + * and SAK; normally, otherwise. |
| 12921 | */ |
| 12922 | - |
| 12923 | - if (status & info->ignore_status_mask) { |
| 12924 | - if (++ignore > 100) |
| 12925 | - break; |
| 12926 | - goto ignore_char; |
| 12927 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 12928 | + !defined(MODULE) |
| 12929 | + if (info->line == dz_sercons.index) { |
| 12930 | + if (!break_pressed) |
| 12931 | + break_pressed = jiffies; |
| 12932 | + continue; |
| 12933 | } |
| 12934 | - /* mask off the error conditions we want to ignore */ |
| 12935 | - tmp = status & info->read_status_mask; |
| 12936 | - |
| 12937 | - if (tmp & DZ_PERR) { |
| 12938 | - *tty->flip.flag_buf_ptr = TTY_PARITY; |
| 12939 | -#ifdef DEBUG_DZ |
| 12940 | - debug_console("PERR\n", 5); |
| 12941 | -#endif |
| 12942 | - } else if (tmp & DZ_FERR) { |
| 12943 | - *tty->flip.flag_buf_ptr = TTY_FRAME; |
| 12944 | -#ifdef DEBUG_DZ |
| 12945 | - debug_console("FERR\n", 5); |
| 12946 | #endif |
| 12947 | + flag = TTY_BREAK; |
| 12948 | + if (info->flags & DZ_SAK) |
| 12949 | + do_SAK(tty); |
| 12950 | + else |
| 12951 | + flag = TTY_FRAME; |
| 12952 | + } else if (status & DZ_OERR) /* overrun error */ |
| 12953 | + flag = TTY_OVERRUN; |
| 12954 | + else if (status & DZ_PERR) /* parity error */ |
| 12955 | + flag = TTY_PARITY; |
| 12956 | + |
| 12957 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 12958 | + !defined(MODULE) |
| 12959 | + if (break_pressed && info->line == dz_sercons.index) { |
| 12960 | + if (time_before(jiffies, break_pressed + HZ * 5)) { |
| 12961 | + handle_sysrq(ch, regs, NULL, NULL); |
| 12962 | + break_pressed = 0; |
| 12963 | + continue; |
| 12964 | } |
| 12965 | - if (tmp & DZ_OERR) { |
| 12966 | -#ifdef DEBUG_DZ |
| 12967 | - debug_console("OERR\n", 5); |
| 12968 | + break_pressed = 0; |
| 12969 | + } |
| 12970 | #endif |
| 12971 | - if (tty->flip.count < TTY_FLIPBUF_SIZE) { |
| 12972 | - tty->flip.count++; |
| 12973 | - tty->flip.flag_buf_ptr++; |
| 12974 | - tty->flip.char_buf_ptr++; |
| 12975 | - *tty->flip.flag_buf_ptr = TTY_OVERRUN; |
| 12976 | - } |
| 12977 | - } |
| 12978 | + |
| 12979 | + if (info->hook && info->hook->rx_char) { |
| 12980 | + (*info->hook->rx_char)(ch, flag); |
| 12981 | + return; |
| 12982 | } |
| 12983 | - tty->flip.flag_buf_ptr++; |
| 12984 | - tty->flip.char_buf_ptr++; |
| 12985 | - tty->flip.count++; |
| 12986 | - ignore_char: |
| 12987 | - } while (status & DZ_DVAL); |
| 12988 | |
| 12989 | - if (tty) |
| 12990 | - tty_flip_buffer_push(tty); |
| 12991 | + /* keep track of the statistics */ |
| 12992 | + switch (flag) { |
| 12993 | + case TTY_FRAME: |
| 12994 | + icount->frame++; |
| 12995 | + break; |
| 12996 | + case TTY_PARITY: |
| 12997 | + icount->parity++; |
| 12998 | + break; |
| 12999 | + case TTY_OVERRUN: |
| 13000 | + icount->overrun++; |
| 13001 | + break; |
| 13002 | + case TTY_BREAK: |
| 13003 | + icount->brk++; |
| 13004 | + break; |
| 13005 | + default: |
| 13006 | + break; |
| 13007 | + } |
| 13008 | + |
| 13009 | + if ((status & info->ignore_status_mask) == 0) { |
| 13010 | + tty_insert_flip_char(tty, ch, flag); |
| 13011 | + lines_rx[LINE(status)] = 1; |
| 13012 | + } |
| 13013 | + } |
| 13014 | + for (i = 0; i < DZ_NB_PORT; i++) |
| 13015 | + if (lines_rx[i]) |
| 13016 | + tty_flip_buffer_push(lines[i]->tty); |
| 13017 | } |
| 13018 | |
| 13019 | /* |
| 13020 | @@ -292,20 +314,34 @@ static inline void receive_chars(struct |
| 13021 | * This routine deals with outputs to any lines. |
| 13022 | * ------------------------------------------------------------ |
| 13023 | */ |
| 13024 | -static inline void transmit_chars(struct dz_serial *info) |
| 13025 | +static inline void transmit_chars(struct dz_serial *info_in) |
| 13026 | { |
| 13027 | + struct dz_serial *info; |
| 13028 | + unsigned short status; |
| 13029 | unsigned char tmp; |
| 13030 | |
| 13031 | + status = dz_in(info_in, DZ_CSR); |
| 13032 | + info = lines[LINE(status)]; |
| 13033 | |
| 13034 | + if (info->hook || !info->tty) { |
| 13035 | + unsigned short mask, tmp; |
| 13036 | |
| 13037 | - if (info->x_char) { /* XON/XOFF chars */ |
| 13038 | + mask = 1 << info->line; |
| 13039 | + tmp = dz_in(info, DZ_TCR); /* read the TX flag */ |
| 13040 | + tmp &= ~mask; /* clear the TX flag */ |
| 13041 | + dz_out(info, DZ_TCR, tmp); |
| 13042 | + return; |
| 13043 | + } |
| 13044 | + |
| 13045 | + if (info->x_char) { /* XON/XOFF chars */ |
| 13046 | dz_out(info, DZ_TDR, info->x_char); |
| 13047 | info->icount.tx++; |
| 13048 | info->x_char = 0; |
| 13049 | return; |
| 13050 | } |
| 13051 | /* if nothing to do or stopped or hardware stopped */ |
| 13052 | - if ((info->xmit_cnt <= 0) || info->tty->stopped || info->tty->hw_stopped) { |
| 13053 | + if (info->xmit_cnt <= 0 || |
| 13054 | + info->tty->stopped || info->tty->hw_stopped) { |
| 13055 | dz_stop(info->tty); |
| 13056 | return; |
| 13057 | } |
| 13058 | @@ -359,15 +395,14 @@ static inline void check_modem_status(st |
| 13059 | */ |
| 13060 | static void dz_interrupt(int irq, void *dev, struct pt_regs *regs) |
| 13061 | { |
| 13062 | - struct dz_serial *info; |
| 13063 | + struct dz_serial *info = (struct dz_serial *)dev; |
| 13064 | unsigned short status; |
| 13065 | |
| 13066 | /* get the reason why we just got an irq */ |
| 13067 | - status = dz_in((struct dz_serial *) dev, DZ_CSR); |
| 13068 | - info = lines[LINE(status)]; /* re-arrange info the proper port */ |
| 13069 | + status = dz_in(info, DZ_CSR); |
| 13070 | |
| 13071 | if (status & DZ_RDONE) |
| 13072 | - receive_chars(info); /* the receive function */ |
| 13073 | + receive_chars(info, regs); |
| 13074 | |
| 13075 | if (status & DZ_TRDY) |
| 13076 | transmit_chars(info); |
| 13077 | @@ -514,7 +549,7 @@ static void shutdown(struct dz_serial *i |
| 13078 | |
| 13079 | |
| 13080 | info->cflags &= ~DZ_CREAD; /* turn off receive enable flag */ |
| 13081 | - dz_out(info, DZ_LPR, info->cflags); |
| 13082 | + dz_out(info, DZ_LPR, info->cflags | info->line); |
| 13083 | |
| 13084 | if (info->xmit_buf) { /* free Tx buffer */ |
| 13085 | free_page((unsigned long) info->xmit_buf); |
| 13086 | @@ -545,18 +580,21 @@ static void change_speed(struct dz_seria |
| 13087 | { |
| 13088 | unsigned long flags; |
| 13089 | unsigned cflag; |
| 13090 | - int baud; |
| 13091 | + int baud, i; |
| 13092 | |
| 13093 | - if (!info->tty || !info->tty->termios) |
| 13094 | - return; |
| 13095 | + if (!info->hook) { |
| 13096 | + if (!info->tty || !info->tty->termios) |
| 13097 | + return; |
| 13098 | + cflag = info->tty->termios->c_cflag; |
| 13099 | + } else { |
| 13100 | + cflag = info->hook->cflags; |
| 13101 | + } |
| 13102 | |
| 13103 | save_flags(flags); |
| 13104 | cli(); |
| 13105 | |
| 13106 | info->cflags = info->line; |
| 13107 | |
| 13108 | - cflag = info->tty->termios->c_cflag; |
| 13109 | - |
| 13110 | switch (cflag & CSIZE) { |
| 13111 | case CS5: |
| 13112 | info->cflags |= DZ_CS5; |
| 13113 | @@ -579,7 +617,16 @@ static void change_speed(struct dz_seria |
| 13114 | if (cflag & PARODD) |
| 13115 | info->cflags |= DZ_PARODD; |
| 13116 | |
| 13117 | - baud = tty_get_baud_rate(info->tty); |
| 13118 | + i = cflag & CBAUD; |
| 13119 | + if (i & CBAUDEX) { |
| 13120 | + i &= ~CBAUDEX; |
| 13121 | + if (!info->hook) |
| 13122 | + info->tty->termios->c_cflag &= ~CBAUDEX; |
| 13123 | + else |
| 13124 | + info->hook->cflags &= ~CBAUDEX; |
| 13125 | + } |
| 13126 | + baud = baud_table[i]; |
| 13127 | + |
| 13128 | switch (baud) { |
| 13129 | case 50: |
| 13130 | info->cflags |= DZ_B50; |
| 13131 | @@ -629,16 +676,16 @@ static void change_speed(struct dz_seria |
| 13132 | } |
| 13133 | |
| 13134 | info->cflags |= DZ_RXENAB; |
| 13135 | - dz_out(info, DZ_LPR, info->cflags); |
| 13136 | + dz_out(info, DZ_LPR, info->cflags | info->line); |
| 13137 | |
| 13138 | /* setup accept flag */ |
| 13139 | info->read_status_mask = DZ_OERR; |
| 13140 | - if (I_INPCK(info->tty)) |
| 13141 | + if (info->tty && I_INPCK(info->tty)) |
| 13142 | info->read_status_mask |= (DZ_FERR | DZ_PERR); |
| 13143 | |
| 13144 | /* characters to ignore */ |
| 13145 | info->ignore_status_mask = 0; |
| 13146 | - if (I_IGNPAR(info->tty)) |
| 13147 | + if (info->tty && I_IGNPAR(info->tty)) |
| 13148 | info->ignore_status_mask |= (DZ_FERR | DZ_PERR); |
| 13149 | |
| 13150 | restore_flags(flags); |
| 13151 | @@ -694,7 +741,7 @@ static int dz_write(struct tty_struct *t |
| 13152 | |
| 13153 | down(&tmp_buf_sem); |
| 13154 | while (1) { |
| 13155 | - c = MIN(count, MIN(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13156 | + c = min(count, min(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13157 | if (c <= 0) |
| 13158 | break; |
| 13159 | |
| 13160 | @@ -707,7 +754,7 @@ static int dz_write(struct tty_struct *t |
| 13161 | save_flags(flags); |
| 13162 | cli(); |
| 13163 | |
| 13164 | - c = MIN(c, MIN(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13165 | + c = min(c, min(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13166 | memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c); |
| 13167 | info->xmit_head = ((info->xmit_head + c) & (DZ_XMIT_SIZE - 1)); |
| 13168 | info->xmit_cnt += c; |
| 13169 | @@ -727,7 +774,7 @@ static int dz_write(struct tty_struct *t |
| 13170 | save_flags(flags); |
| 13171 | cli(); |
| 13172 | |
| 13173 | - c = MIN(count, MIN(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13174 | + c = min(count, min(DZ_XMIT_SIZE - info->xmit_cnt - 1, DZ_XMIT_SIZE - info->xmit_head)); |
| 13175 | if (c <= 0) { |
| 13176 | restore_flags(flags); |
| 13177 | break; |
| 13178 | @@ -845,7 +892,7 @@ static void dz_send_xchar(struct tty_str |
| 13179 | |
| 13180 | /* |
| 13181 | * ------------------------------------------------------------ |
| 13182 | - * rs_ioctl () and friends |
| 13183 | + * dz_ioctl () and friends |
| 13184 | * ------------------------------------------------------------ |
| 13185 | */ |
| 13186 | static int get_serial_info(struct dz_serial *info, |
| 13187 | @@ -958,6 +1005,9 @@ static int dz_ioctl(struct tty_struct *t |
| 13188 | struct dz_serial *info = (struct dz_serial *) tty->driver_data; |
| 13189 | int retval; |
| 13190 | |
| 13191 | + if (info->hook) |
| 13192 | + return -ENODEV; |
| 13193 | + |
| 13194 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && |
| 13195 | (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) && |
| 13196 | (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) { |
| 13197 | @@ -1252,19 +1302,14 @@ static int dz_open(struct tty_struct *tt |
| 13198 | int retval, line; |
| 13199 | |
| 13200 | line = MINOR(tty->device) - tty->driver.minor_start; |
| 13201 | - |
| 13202 | - /* The dz lines for the mouse/keyboard must be |
| 13203 | - * opened using their respective drivers. |
| 13204 | - */ |
| 13205 | if ((line < 0) || (line >= DZ_NB_PORT)) |
| 13206 | return -ENODEV; |
| 13207 | + info = lines[line]; |
| 13208 | |
| 13209 | - if ((line == DZ_KEYBOARD) || (line == DZ_MOUSE)) |
| 13210 | + if (info->hook) |
| 13211 | return -ENODEV; |
| 13212 | |
| 13213 | - info = lines[line]; |
| 13214 | info->count++; |
| 13215 | - |
| 13216 | tty->driver_data = info; |
| 13217 | info->tty = tty; |
| 13218 | |
| 13219 | @@ -1285,14 +1330,21 @@ static int dz_open(struct tty_struct *tt |
| 13220 | else |
| 13221 | *tty->termios = info->callout_termios; |
| 13222 | change_speed(info); |
| 13223 | - |
| 13224 | } |
| 13225 | +#ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 13226 | + if (dz_sercons.cflag && dz_sercons.index == line) { |
| 13227 | + tty->termios->c_cflag = dz_sercons.cflag; |
| 13228 | + dz_sercons.cflag = 0; |
| 13229 | + change_speed(info); |
| 13230 | + } |
| 13231 | +#endif |
| 13232 | + |
| 13233 | info->session = current->session; |
| 13234 | info->pgrp = current->pgrp; |
| 13235 | return 0; |
| 13236 | } |
| 13237 | |
| 13238 | -static void show_serial_version(void) |
| 13239 | +static void __init show_serial_version(void) |
| 13240 | { |
| 13241 | printk("%s%s\n", dz_name, dz_version); |
| 13242 | } |
| 13243 | @@ -1300,7 +1352,6 @@ static void show_serial_version(void) |
| 13244 | int __init dz_init(void) |
| 13245 | { |
| 13246 | int i; |
| 13247 | - long flags; |
| 13248 | struct dz_serial *info; |
| 13249 | |
| 13250 | /* Setup base handler, and timer table. */ |
| 13251 | @@ -1311,9 +1362,9 @@ int __init dz_init(void) |
| 13252 | memset(&serial_driver, 0, sizeof(struct tty_driver)); |
| 13253 | serial_driver.magic = TTY_DRIVER_MAGIC; |
| 13254 | #if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS)) |
| 13255 | - serial_driver.name = "ttyS"; |
| 13256 | -#else |
| 13257 | serial_driver.name = "tts/%d"; |
| 13258 | +#else |
| 13259 | + serial_driver.name = "ttyS"; |
| 13260 | #endif |
| 13261 | serial_driver.major = TTY_MAJOR; |
| 13262 | serial_driver.minor_start = 64; |
| 13263 | @@ -1352,9 +1403,9 @@ int __init dz_init(void) |
| 13264 | */ |
| 13265 | callout_driver = serial_driver; |
| 13266 | #if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS)) |
| 13267 | - callout_driver.name = "cua"; |
| 13268 | -#else |
| 13269 | callout_driver.name = "cua/%d"; |
| 13270 | +#else |
| 13271 | + callout_driver.name = "cua"; |
| 13272 | #endif |
| 13273 | callout_driver.major = TTYAUX_MAJOR; |
| 13274 | callout_driver.subtype = SERIAL_TYPE_CALLOUT; |
| 13275 | @@ -1363,25 +1414,27 @@ int __init dz_init(void) |
| 13276 | panic("Couldn't register serial driver"); |
| 13277 | if (tty_register_driver(&callout_driver)) |
| 13278 | panic("Couldn't register callout driver"); |
| 13279 | - save_flags(flags); |
| 13280 | - cli(); |
| 13281 | |
| 13282 | for (i = 0; i < DZ_NB_PORT; i++) { |
| 13283 | info = &multi[i]; |
| 13284 | lines[i] = info; |
| 13285 | - info->magic = SERIAL_MAGIC; |
| 13286 | - |
| 13287 | + info->tty = 0; |
| 13288 | + info->x_char = 0; |
| 13289 | if (mips_machtype == MACH_DS23100 || |
| 13290 | mips_machtype == MACH_DS5100) |
| 13291 | info->port = (unsigned long) KN01_DZ11_BASE; |
| 13292 | else |
| 13293 | info->port = (unsigned long) KN02_DZ11_BASE; |
| 13294 | - |
| 13295 | info->line = i; |
| 13296 | - info->tty = 0; |
| 13297 | + |
| 13298 | + if (info->hook && info->hook->init_info) { |
| 13299 | + (*info->hook->init_info)(info); |
| 13300 | + continue; |
| 13301 | + } |
| 13302 | + |
| 13303 | + info->magic = SERIAL_MAGIC; |
| 13304 | info->close_delay = 50; |
| 13305 | info->closing_wait = 3000; |
| 13306 | - info->x_char = 0; |
| 13307 | info->event = 0; |
| 13308 | info->count = 0; |
| 13309 | info->blocked_open = 0; |
| 13310 | @@ -1393,25 +1446,16 @@ int __init dz_init(void) |
| 13311 | info->normal_termios = serial_driver.init_termios; |
| 13312 | init_waitqueue_head(&info->open_wait); |
| 13313 | init_waitqueue_head(&info->close_wait); |
| 13314 | - |
| 13315 | - /* |
| 13316 | - * If we are pointing to address zero then punt - not correctly |
| 13317 | - * set up in setup.c to handle this. |
| 13318 | - */ |
| 13319 | - if (!info->port) |
| 13320 | - return 0; |
| 13321 | - |
| 13322 | - printk("ttyS%02d at 0x%08x (irq = %d)\n", info->line, |
| 13323 | - info->port, dec_interrupt[DEC_IRQ_DZ11]); |
| 13324 | - |
| 13325 | + printk("ttyS%02d at 0x%08x (irq = %d) is a DC7085 DZ\n", |
| 13326 | + info->line, info->port, dec_interrupt[DEC_IRQ_DZ11]); |
| 13327 | tty_register_devfs(&serial_driver, 0, |
| 13328 | - serial_driver.minor_start + info->line); |
| 13329 | + serial_driver.minor_start + info->line); |
| 13330 | tty_register_devfs(&callout_driver, 0, |
| 13331 | - callout_driver.minor_start + info->line); |
| 13332 | + callout_driver.minor_start + info->line); |
| 13333 | } |
| 13334 | |
| 13335 | - /* reset the chip */ |
| 13336 | #ifndef CONFIG_SERIAL_DEC_CONSOLE |
| 13337 | + /* reset the chip */ |
| 13338 | dz_out(info, DZ_CSR, DZ_CLR); |
| 13339 | while (dz_in(info, DZ_CSR) & DZ_CLR); |
| 13340 | iob(); |
| 13341 | @@ -1420,43 +1464,104 @@ int __init dz_init(void) |
| 13342 | dz_out(info, DZ_CSR, DZ_MSE); |
| 13343 | #endif |
| 13344 | |
| 13345 | - /* order matters here... the trick is that flags |
| 13346 | - is updated... in request_irq - to immediatedly obliterate |
| 13347 | - it is unwise. */ |
| 13348 | - restore_flags(flags); |
| 13349 | - |
| 13350 | - |
| 13351 | if (request_irq(dec_interrupt[DEC_IRQ_DZ11], dz_interrupt, |
| 13352 | - SA_INTERRUPT, "DZ", lines[0])) |
| 13353 | + 0, "DZ", lines[0])) |
| 13354 | panic("Unable to register DZ interrupt"); |
| 13355 | |
| 13356 | + for (i = 0; i < DZ_NB_PORT; i++) |
| 13357 | + if (lines[i]->hook) { |
| 13358 | + startup(lines[i]); |
| 13359 | + if (lines[i]->hook->init_channel) |
| 13360 | + (*lines[i]->hook->init_channel)(lines[i]); |
| 13361 | + } |
| 13362 | + |
| 13363 | return 0; |
| 13364 | } |
| 13365 | |
| 13366 | -#ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 13367 | -static void dz_console_put_char(unsigned char ch) |
| 13368 | +/* |
| 13369 | + * polling I/O routines |
| 13370 | + */ |
| 13371 | +static int dz_poll_tx_char(void *handle, unsigned char ch) |
| 13372 | { |
| 13373 | unsigned long flags; |
| 13374 | - int loops = 2500; |
| 13375 | - unsigned short tmp = ch; |
| 13376 | - /* this code sends stuff out to serial device - spinning its |
| 13377 | - wheels and waiting. */ |
| 13378 | + struct dz_serial *info = handle; |
| 13379 | + unsigned short csr, tcr, trdy, mask; |
| 13380 | + int loops = 10000; |
| 13381 | + int ret; |
| 13382 | |
| 13383 | - /* force the issue - point it at lines[3] */ |
| 13384 | - dz_console = &multi[CONSOLE_LINE]; |
| 13385 | + local_irq_save(flags); |
| 13386 | + csr = dz_in(info, DZ_CSR); |
| 13387 | + dz_out(info, DZ_CSR, csr & ~DZ_TIE); |
| 13388 | + tcr = dz_in(info, DZ_TCR); |
| 13389 | + tcr |= 1 << info->line; |
| 13390 | + mask = tcr; |
| 13391 | + dz_out(info, DZ_TCR, mask); |
| 13392 | + iob(); |
| 13393 | + local_irq_restore(flags); |
| 13394 | |
| 13395 | - save_flags(flags); |
| 13396 | - cli(); |
| 13397 | + while (loops--) { |
| 13398 | + trdy = dz_in(info, DZ_CSR); |
| 13399 | + if (!(trdy & DZ_TRDY)) |
| 13400 | + continue; |
| 13401 | + trdy = (trdy & DZ_TLINE) >> 8; |
| 13402 | + if (trdy == info->line) |
| 13403 | + break; |
| 13404 | + mask &= ~(1 << trdy); |
| 13405 | + dz_out(info, DZ_TCR, mask); |
| 13406 | + iob(); |
| 13407 | + udelay(2); |
| 13408 | + } |
| 13409 | |
| 13410 | + if (loops) { |
| 13411 | + dz_out(info, DZ_TDR, ch); |
| 13412 | + ret = 0; |
| 13413 | + } else |
| 13414 | + ret = -EAGAIN; |
| 13415 | |
| 13416 | - /* spin our wheels */ |
| 13417 | - while (((dz_in(dz_console, DZ_CSR) & DZ_TRDY) != DZ_TRDY) && loops--); |
| 13418 | + dz_out(info, DZ_TCR, tcr); |
| 13419 | + dz_out(info, DZ_CSR, csr); |
| 13420 | |
| 13421 | - /* Actually transmit the character. */ |
| 13422 | - dz_out(dz_console, DZ_TDR, tmp); |
| 13423 | + return ret; |
| 13424 | +} |
| 13425 | |
| 13426 | - restore_flags(flags); |
| 13427 | +static int dz_poll_rx_char(void *handle) |
| 13428 | +{ |
| 13429 | + return -ENODEV; |
| 13430 | +} |
| 13431 | + |
| 13432 | +int register_dz_hook(unsigned int channel, struct dec_serial_hook *hook) |
| 13433 | +{ |
| 13434 | + struct dz_serial *info = multi + channel; |
| 13435 | + |
| 13436 | + if (info->hook) { |
| 13437 | + printk("%s: line %d has already a hook registered\n", |
| 13438 | + __FUNCTION__, channel); |
| 13439 | + |
| 13440 | + return 0; |
| 13441 | + } else { |
| 13442 | + hook->poll_rx_char = dz_poll_rx_char; |
| 13443 | + hook->poll_tx_char = dz_poll_tx_char; |
| 13444 | + info->hook = hook; |
| 13445 | + |
| 13446 | + return 1; |
| 13447 | + } |
| 13448 | +} |
| 13449 | + |
| 13450 | +int unregister_dz_hook(unsigned int channel) |
| 13451 | +{ |
| 13452 | + struct dz_serial *info = &multi[channel]; |
| 13453 | + |
| 13454 | + if (info->hook) { |
| 13455 | + info->hook = NULL; |
| 13456 | + return 1; |
| 13457 | + } else { |
| 13458 | + printk("%s: trying to unregister hook on line %d," |
| 13459 | + " but none is registered\n", __FUNCTION__, channel); |
| 13460 | + return 0; |
| 13461 | + } |
| 13462 | } |
| 13463 | + |
| 13464 | +#ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 13465 | /* |
| 13466 | * ------------------------------------------------------------------- |
| 13467 | * dz_console_print () |
| 13468 | @@ -1465,17 +1570,19 @@ static void dz_console_put_char(unsigned |
| 13469 | * The console must be locked when we get here. |
| 13470 | * ------------------------------------------------------------------- |
| 13471 | */ |
| 13472 | -static void dz_console_print(struct console *cons, |
| 13473 | +static void dz_console_print(struct console *co, |
| 13474 | const char *str, |
| 13475 | unsigned int count) |
| 13476 | { |
| 13477 | + struct dz_serial *info = multi + co->index; |
| 13478 | + |
| 13479 | #ifdef DEBUG_DZ |
| 13480 | prom_printf((char *) str); |
| 13481 | #endif |
| 13482 | while (count--) { |
| 13483 | if (*str == '\n') |
| 13484 | - dz_console_put_char('\r'); |
| 13485 | - dz_console_put_char(*str++); |
| 13486 | + dz_poll_tx_char(info, '\r'); |
| 13487 | + dz_poll_tx_char(info, *str++); |
| 13488 | } |
| 13489 | } |
| 13490 | |
| 13491 | @@ -1486,12 +1593,12 @@ static kdev_t dz_console_device(struct c |
| 13492 | |
| 13493 | static int __init dz_console_setup(struct console *co, char *options) |
| 13494 | { |
| 13495 | + struct dz_serial *info = multi + co->index; |
| 13496 | int baud = 9600; |
| 13497 | int bits = 8; |
| 13498 | int parity = 'n'; |
| 13499 | int cflag = CREAD | HUPCL | CLOCAL; |
| 13500 | char *s; |
| 13501 | - unsigned short mask, tmp; |
| 13502 | |
| 13503 | if (options) { |
| 13504 | baud = simple_strtoul(options, NULL, 10); |
| 13505 | @@ -1542,44 +1649,31 @@ static int __init dz_console_setup(struc |
| 13506 | } |
| 13507 | co->cflag = cflag; |
| 13508 | |
| 13509 | - /* TOFIX: force to console line */ |
| 13510 | - dz_console = &multi[CONSOLE_LINE]; |
| 13511 | if ((mips_machtype == MACH_DS23100) || (mips_machtype == MACH_DS5100)) |
| 13512 | - dz_console->port = KN01_DZ11_BASE; |
| 13513 | + info->port = KN01_DZ11_BASE; |
| 13514 | else |
| 13515 | - dz_console->port = KN02_DZ11_BASE; |
| 13516 | - dz_console->line = CONSOLE_LINE; |
| 13517 | + info->port = KN02_DZ11_BASE; |
| 13518 | + info->line = co->index; |
| 13519 | |
| 13520 | - dz_out(dz_console, DZ_CSR, DZ_CLR); |
| 13521 | - while ((tmp = dz_in(dz_console, DZ_CSR)) & DZ_CLR); |
| 13522 | + dz_out(info, DZ_CSR, DZ_CLR); |
| 13523 | + while (dz_in(info, DZ_CSR) & DZ_CLR); |
| 13524 | |
| 13525 | /* enable scanning */ |
| 13526 | - dz_out(dz_console, DZ_CSR, DZ_MSE); |
| 13527 | + dz_out(info, DZ_CSR, DZ_MSE); |
| 13528 | |
| 13529 | /* Set up flags... */ |
| 13530 | - dz_console->cflags = 0; |
| 13531 | - dz_console->cflags |= DZ_B9600; |
| 13532 | - dz_console->cflags |= DZ_CS8; |
| 13533 | - dz_console->cflags |= DZ_PARENB; |
| 13534 | - dz_out(dz_console, DZ_LPR, dz_console->cflags); |
| 13535 | - |
| 13536 | - mask = 1 << dz_console->line; |
| 13537 | - tmp = dz_in(dz_console, DZ_TCR); /* read the TX flag */ |
| 13538 | - if (!(tmp & mask)) { |
| 13539 | - tmp |= mask; /* set the TX flag */ |
| 13540 | - dz_out(dz_console, DZ_TCR, tmp); |
| 13541 | - } |
| 13542 | + dz_out(info, DZ_LPR, cflag | info->line); |
| 13543 | + |
| 13544 | return 0; |
| 13545 | } |
| 13546 | |
| 13547 | -static struct console dz_sercons = |
| 13548 | -{ |
| 13549 | - .name = "ttyS", |
| 13550 | - .write = dz_console_print, |
| 13551 | - .device = dz_console_device, |
| 13552 | - .setup = dz_console_setup, |
| 13553 | - .flags = CON_CONSDEV | CON_PRINTBUFFER, |
| 13554 | - .index = CONSOLE_LINE, |
| 13555 | +static struct console dz_sercons = { |
| 13556 | + .name = "ttyS", |
| 13557 | + .write = dz_console_print, |
| 13558 | + .device = dz_console_device, |
| 13559 | + .setup = dz_console_setup, |
| 13560 | + .flags = CON_PRINTBUFFER, |
| 13561 | + .index = -1, |
| 13562 | }; |
| 13563 | |
| 13564 | void __init dz_serial_console_init(void) |
| 13565 | --- a/drivers/char/dz.h |
| 13566 | +++ b/drivers/char/dz.h |
| 13567 | @@ -10,6 +10,8 @@ |
| 13568 | #ifndef DZ_SERIAL_H |
| 13569 | #define DZ_SERIAL_H |
| 13570 | |
| 13571 | +#include <asm/dec/serial.h> |
| 13572 | + |
| 13573 | #define SERIAL_MAGIC 0x5301 |
| 13574 | |
| 13575 | /* |
| 13576 | @@ -17,6 +19,7 @@ |
| 13577 | */ |
| 13578 | #define DZ_TRDY 0x8000 /* Transmitter empty */ |
| 13579 | #define DZ_TIE 0x4000 /* Transmitter Interrupt Enable */ |
| 13580 | +#define DZ_TLINE 0x0300 /* Transmitter Line Number */ |
| 13581 | #define DZ_RDONE 0x0080 /* Receiver data ready */ |
| 13582 | #define DZ_RIE 0x0040 /* Receive Interrupt Enable */ |
| 13583 | #define DZ_MSE 0x0020 /* Master Scan Enable */ |
| 13584 | @@ -37,19 +40,30 @@ |
| 13585 | #define UCHAR(x) (unsigned char)(x & DZ_RBUF_MASK) |
| 13586 | |
| 13587 | /* |
| 13588 | - * Definitions for the Transmit Register. |
| 13589 | + * Definitions for the Transmit Control Register. |
| 13590 | */ |
| 13591 | #define DZ_LINE_KEYBOARD 0x0001 |
| 13592 | #define DZ_LINE_MOUSE 0x0002 |
| 13593 | #define DZ_LINE_MODEM 0x0004 |
| 13594 | #define DZ_LINE_PRINTER 0x0008 |
| 13595 | |
| 13596 | +#define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */ |
| 13597 | #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */ |
| 13598 | +#define DZ_PRINT_RTS 0x0200 /* RTS for the printer line (3) */ |
| 13599 | +#define DZ_PRINT_DTR 0x0100 /* DTR for the printer line (3) */ |
| 13600 | +#define DZ_LNENB 0x000f /* Transmitter Line Enable */ |
| 13601 | |
| 13602 | /* |
| 13603 | * Definitions for the Modem Status Register. |
| 13604 | */ |
| 13605 | +#define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */ |
| 13606 | +#define DZ_MODEM_CD 0x0400 /* CD for the modem line (2) */ |
| 13607 | #define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */ |
| 13608 | +#define DZ_MODEM_CTS 0x0100 /* CTS for the modem line (2) */ |
| 13609 | +#define DZ_PRINT_RI 0x0008 /* RI for the printer line (2) */ |
| 13610 | +#define DZ_PRINT_CD 0x0004 /* CD for the printer line (2) */ |
| 13611 | +#define DZ_PRINT_DSR 0x0002 /* DSR for the printer line (2) */ |
| 13612 | +#define DZ_PRINT_CTS 0x0001 /* CTS for the printer line (2) */ |
| 13613 | |
| 13614 | /* |
| 13615 | * Definitions for the Transmit Data Register. |
| 13616 | @@ -115,9 +129,6 @@ |
| 13617 | |
| 13618 | #define DZ_EVENT_WRITE_WAKEUP 0 |
| 13619 | |
| 13620 | -#ifndef MIN |
| 13621 | -#define MIN(a,b) ((a) < (b) ? (a) : (b)) |
| 13622 | - |
| 13623 | #define DZ_INITIALIZED 0x80000000 /* Serial port was initialized */ |
| 13624 | #define DZ_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ |
| 13625 | #define DZ_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ |
| 13626 | @@ -129,6 +140,7 @@ |
| 13627 | #define DZ_CLOSING_WAIT_INF 0 |
| 13628 | #define DZ_CLOSING_WAIT_NONE 65535 |
| 13629 | |
| 13630 | +#define DZ_SAK 0x0004 /* Secure Attention Key (Orange book) */ |
| 13631 | #define DZ_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ |
| 13632 | #define DZ_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ |
| 13633 | #define DZ_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ |
| 13634 | @@ -166,79 +178,9 @@ struct dz_serial { |
| 13635 | long session; /* Session of opening process */ |
| 13636 | long pgrp; /* pgrp of opening process */ |
| 13637 | |
| 13638 | + struct dec_serial_hook *hook; /* Hook on this channel. */ |
| 13639 | unsigned char is_console; /* flag indicating a serial console */ |
| 13640 | unsigned char is_initialized; |
| 13641 | }; |
| 13642 | |
| 13643 | -static struct dz_serial multi[DZ_NB_PORT]; /* Four serial lines in the DZ chip */ |
| 13644 | -static struct dz_serial *dz_console; |
| 13645 | -static struct tty_driver serial_driver, callout_driver; |
| 13646 | - |
| 13647 | -static struct tty_struct *serial_table[DZ_NB_PORT]; |
| 13648 | -static struct termios *serial_termios[DZ_NB_PORT]; |
| 13649 | -static struct termios *serial_termios_locked[DZ_NB_PORT]; |
| 13650 | - |
| 13651 | -static int serial_refcount; |
| 13652 | - |
| 13653 | -/* |
| 13654 | - * tmp_buf is used as a temporary buffer by serial_write. We need to |
| 13655 | - * lock it in case the copy_from_user blocks while swapping in a page, |
| 13656 | - * and some other program tries to do a serial write at the same time. |
| 13657 | - * Since the lock will only come under contention when the system is |
| 13658 | - * swapping and available memory is low, it makes sense to share one |
| 13659 | - * buffer across all the serial ports, since it significantly saves |
| 13660 | - * memory if large numbers of serial ports are open. |
| 13661 | - */ |
| 13662 | -static unsigned char *tmp_buf; |
| 13663 | -static DECLARE_MUTEX(tmp_buf_sem); |
| 13664 | - |
| 13665 | -static char *dz_name = "DECstation DZ serial driver version "; |
| 13666 | -static char *dz_version = "1.02"; |
| 13667 | - |
| 13668 | -static inline unsigned short dz_in (struct dz_serial *, unsigned); |
| 13669 | -static inline void dz_out (struct dz_serial *, unsigned, unsigned short); |
| 13670 | - |
| 13671 | -static inline void dz_sched_event (struct dz_serial *, int); |
| 13672 | -static inline void receive_chars (struct dz_serial *); |
| 13673 | -static inline void transmit_chars (struct dz_serial *); |
| 13674 | -static inline void check_modem_status (struct dz_serial *); |
| 13675 | - |
| 13676 | -static void dz_stop (struct tty_struct *); |
| 13677 | -static void dz_start (struct tty_struct *); |
| 13678 | -static void dz_interrupt (int, void *, struct pt_regs *); |
| 13679 | -static void do_serial_bh (void); |
| 13680 | -static void do_softint (void *); |
| 13681 | -static void do_serial_hangup (void *); |
| 13682 | -static void change_speed (struct dz_serial *); |
| 13683 | -static void dz_flush_chars (struct tty_struct *); |
| 13684 | -static void dz_console_print (struct console *, const char *, unsigned int); |
| 13685 | -static void dz_flush_buffer (struct tty_struct *); |
| 13686 | -static void dz_throttle (struct tty_struct *); |
| 13687 | -static void dz_unthrottle (struct tty_struct *); |
| 13688 | -static void dz_send_xchar (struct tty_struct *, char); |
| 13689 | -static void shutdown (struct dz_serial *); |
| 13690 | -static void send_break (struct dz_serial *, int); |
| 13691 | -static void dz_set_termios (struct tty_struct *, struct termios *); |
| 13692 | -static void dz_close (struct tty_struct *, struct file *); |
| 13693 | -static void dz_hangup (struct tty_struct *); |
| 13694 | -static void show_serial_version (void); |
| 13695 | - |
| 13696 | -static int dz_write (struct tty_struct *, int, const unsigned char *, int); |
| 13697 | -static int dz_write_room (struct tty_struct *); |
| 13698 | -static int dz_chars_in_buffer (struct tty_struct *); |
| 13699 | -static int startup (struct dz_serial *); |
| 13700 | -static int get_serial_info (struct dz_serial *, struct serial_struct *); |
| 13701 | -static int set_serial_info (struct dz_serial *, struct serial_struct *); |
| 13702 | -static int get_lsr_info (struct dz_serial *, unsigned int *); |
| 13703 | -static int dz_ioctl (struct tty_struct *, struct file *, unsigned int, unsigned long); |
| 13704 | -static int block_til_ready (struct tty_struct *, struct file *, struct dz_serial *); |
| 13705 | -static int dz_open (struct tty_struct *, struct file *); |
| 13706 | - |
| 13707 | -#ifdef MODULE |
| 13708 | -int init_module (void) |
| 13709 | -void cleanup_module (void) |
| 13710 | -#endif |
| 13711 | - |
| 13712 | -#endif |
| 13713 | - |
| 13714 | #endif /* DZ_SERIAL_H */ |
| 13715 | --- /dev/null |
| 13716 | +++ b/drivers/char/ibm_workpad_keymap.map |
| 13717 | @@ -0,0 +1,343 @@ |
| 13718 | +# Keymap for IBM Workpad z50 |
| 13719 | +# US Mapping |
| 13720 | +# |
| 13721 | +# by Michael Klar <wyldfier@iname.com> |
| 13722 | +# |
| 13723 | +# This is a great big mess on account of how the Caps Lock key is handled as |
| 13724 | +# LeftShift-RightShift. Right shift key had to be broken out, so don't use |
| 13725 | +# use this map file as a basis for other keyboards that don't do the same |
| 13726 | +# thing with Caps Lock. |
| 13727 | +# |
| 13728 | +# This file is subject to the terms and conditions of the GNU General Public |
| 13729 | +# License. See the file "COPYING" in the main directory of this archive |
| 13730 | +# for more details. |
| 13731 | + |
| 13732 | +keymaps 0-2,4-5,8,12,32-33,36-37 |
| 13733 | +strings as usual |
| 13734 | + |
| 13735 | +keycode 0 = F1 F11 Console_13 |
| 13736 | + shiftr keycode 0 = F11 |
| 13737 | + shift shiftr keycode 0 = F11 |
| 13738 | + control keycode 0 = F1 |
| 13739 | + alt keycode 0 = Console_1 |
| 13740 | + control alt keycode 0 = Console_1 |
| 13741 | +keycode 1 = F3 F13 Console_15 |
| 13742 | + shiftr keycode 1 = F13 |
| 13743 | + shift shiftr keycode 1 = F13 |
| 13744 | + control keycode 1 = F3 |
| 13745 | + alt keycode 1 = Console_3 |
| 13746 | + control alt keycode 1 = Console_3 |
| 13747 | +keycode 2 = F5 F15 Console_17 |
| 13748 | + shiftr keycode 2 = F15 |
| 13749 | + shift shiftr keycode 2 = F15 |
| 13750 | + control keycode 2 = F5 |
| 13751 | + alt keycode 2 = Console_5 |
| 13752 | + control alt keycode 2 = Console_5 |
| 13753 | +keycode 3 = F7 F17 Console_19 |
| 13754 | + shiftr keycode 3 = F17 |
| 13755 | + shift shiftr keycode 3 = F17 |
| 13756 | + control keycode 3 = F7 |
| 13757 | + alt keycode 3 = Console_7 |
| 13758 | + control alt keycode 3 = Console_7 |
| 13759 | +keycode 4 = F9 F19 Console_21 |
| 13760 | + shiftr keycode 4 = F19 |
| 13761 | + shift shiftr keycode 4 = F19 |
| 13762 | + control keycode 4 = F9 |
| 13763 | + alt keycode 4 = Console_9 |
| 13764 | + control alt keycode 4 = Console_9 |
| 13765 | +#keycode 5 is contrast down |
| 13766 | +#keycode 6 is contrast up |
| 13767 | +keycode 7 = F11 F11 Console_23 |
| 13768 | + shiftr keycode 7 = F11 |
| 13769 | + shift shiftr keycode 7 = F11 |
| 13770 | + control keycode 7 = F11 |
| 13771 | + alt keycode 7 = Console_11 |
| 13772 | + control alt keycode 7 = Console_11 |
| 13773 | +keycode 8 = F2 F12 Console_14 |
| 13774 | + shiftr keycode 8 = F12 |
| 13775 | + shift shiftr keycode 8 = F12 |
| 13776 | + control keycode 8 = F2 |
| 13777 | + alt keycode 8 = Console_2 |
| 13778 | + control alt keycode 8 = Console_2 |
| 13779 | +keycode 9 = F4 F14 Console_16 |
| 13780 | + shiftr keycode 9 = F14 |
| 13781 | + shift shiftr keycode 9 = F14 |
| 13782 | + control keycode 9 = F4 |
| 13783 | + alt keycode 9 = Console_4 |
| 13784 | + control alt keycode 9 = Console_4 |
| 13785 | +keycode 10 = F6 F16 Console_18 |
| 13786 | + shiftr keycode 10 = F16 |
| 13787 | + shift shiftr keycode 10 = F16 |
| 13788 | + control keycode 10 = F6 |
| 13789 | + alt keycode 10 = Console_6 |
| 13790 | + control alt keycode 10 = Console_6 |
| 13791 | +keycode 11 = F8 F18 Console_20 |
| 13792 | + shiftr keycode 11 = F18 |
| 13793 | + shift shiftr keycode 11 = F18 |
| 13794 | + control keycode 11 = F8 |
| 13795 | + alt keycode 11 = Console_8 |
| 13796 | + control alt keycode 11 = Console_8 |
| 13797 | +keycode 12 = F10 F20 Console_22 |
| 13798 | + shiftr keycode 12 = F20 |
| 13799 | + shift shiftr keycode 12 = F20 |
| 13800 | + control keycode 12 = F10 |
| 13801 | + alt keycode 12 = Console_10 |
| 13802 | + control alt keycode 12 = Console_10 |
| 13803 | +#keycode 13 is brightness down |
| 13804 | +#keycode 14 is brightness up |
| 13805 | +keycode 15 = F12 F12 Console_24 |
| 13806 | + shiftr keycode 15 = F12 |
| 13807 | + shift shiftr keycode 15 = F12 |
| 13808 | + control keycode 15 = F12 |
| 13809 | + alt keycode 15 = Console_12 |
| 13810 | + control alt keycode 15 = Console_12 |
| 13811 | +keycode 16 = apostrophe quotedbl |
| 13812 | + shiftr keycode 16 = quotedbl |
| 13813 | + shift shiftr keycode 16 = quotedbl |
| 13814 | + control keycode 16 = Control_g |
| 13815 | + alt keycode 16 = Meta_apostrophe |
| 13816 | +keycode 17 = bracketleft braceleft |
| 13817 | + shiftr keycode 17 = braceleft |
| 13818 | + shift shiftr keycode 17 = braceleft |
| 13819 | + control keycode 17 = Escape |
| 13820 | + alt keycode 17 = Meta_bracketleft |
| 13821 | +keycode 18 = minus underscore backslash |
| 13822 | + shiftr keycode 18 = underscore |
| 13823 | + shift shiftr keycode 18 = underscore |
| 13824 | + control keycode 18 = Control_underscore |
| 13825 | + shift control keycode 18 = Control_underscore |
| 13826 | + shiftr control keycode 18 = Control_underscore |
| 13827 | + shift shiftr control keycode 18 = Control_underscore |
| 13828 | + alt keycode 18 = Meta_minus |
| 13829 | +keycode 19 = zero parenright braceright |
| 13830 | + shiftr keycode 19 = parenright |
| 13831 | + shift shiftr keycode 19 = parenright |
| 13832 | + alt keycode 19 = Meta_zero |
| 13833 | +keycode 20 = p |
| 13834 | + shiftr keycode 20 = +P |
| 13835 | + shift shiftr keycode 20 = +p |
| 13836 | +keycode 21 = semicolon colon |
| 13837 | + shiftr keycode 21 = colon |
| 13838 | + shift shiftr keycode 21 = colon |
| 13839 | + alt keycode 21 = Meta_semicolon |
| 13840 | +keycode 22 = Up Scroll_Backward |
| 13841 | + shiftr keycode 22 = Scroll_Backward |
| 13842 | + shift shiftr keycode 22 = Scroll_Backward |
| 13843 | + alt keycode 22 = Prior |
| 13844 | +keycode 23 = slash question |
| 13845 | + shiftr keycode 23 = question |
| 13846 | + shift shiftr keycode 23 = question |
| 13847 | + control keycode 23 = Delete |
| 13848 | + alt keycode 23 = Meta_slash |
| 13849 | + |
| 13850 | +keycode 27 = nine parenleft bracketright |
| 13851 | + shiftr keycode 27 = parenleft |
| 13852 | + shift shiftr keycode 27 = parenleft |
| 13853 | + alt keycode 27 = Meta_nine |
| 13854 | +keycode 28 = o |
| 13855 | + shiftr keycode 28 = +O |
| 13856 | + shift shiftr keycode 28 = +o |
| 13857 | +keycode 29 = l |
| 13858 | + shiftr keycode 29 = +L |
| 13859 | + shift shiftr keycode 29 = +l |
| 13860 | +keycode 30 = period greater |
| 13861 | + shiftr keycode 30 = greater |
| 13862 | + shift shiftr keycode 30 = greater |
| 13863 | + control keycode 30 = Compose |
| 13864 | + alt keycode 30 = Meta_period |
| 13865 | + |
| 13866 | +keycode 32 = Left Decr_Console |
| 13867 | + shiftr keycode 32 = Decr_Console |
| 13868 | + shift shiftr keycode 32 = Decr_Console |
| 13869 | + alt keycode 32 = Home |
| 13870 | +keycode 33 = bracketright braceright asciitilde |
| 13871 | + shiftr keycode 33 = braceright |
| 13872 | + shift shiftr keycode 33 = braceright |
| 13873 | + control keycode 33 = Control_bracketright |
| 13874 | + alt keycode 33 = Meta_bracketright |
| 13875 | +keycode 34 = equal plus |
| 13876 | + shiftr keycode 34 = plus |
| 13877 | + shift shiftr keycode 34 = plus |
| 13878 | + alt keycode 34 = Meta_equal |
| 13879 | +keycode 35 = eight asterisk bracketleft |
| 13880 | + shiftr keycode 35 = asterisk |
| 13881 | + shift shiftr keycode 35 = asterisk |
| 13882 | + control keycode 35 = Delete |
| 13883 | + alt keycode 35 = Meta_eight |
| 13884 | +keycode 36 = i |
| 13885 | + shiftr keycode 36 = +I |
| 13886 | + shift shiftr keycode 36 = +i |
| 13887 | +keycode 37 = k |
| 13888 | + shiftr keycode 37 = +K |
| 13889 | + shift shiftr keycode 37 = +k |
| 13890 | +keycode 38 = comma less |
| 13891 | + shiftr keycode 38 = less |
| 13892 | + shift shiftr keycode 38 = less |
| 13893 | + alt keycode 38 = Meta_comma |
| 13894 | + |
| 13895 | +keycode 40 = h |
| 13896 | + shiftr keycode 40 = +H |
| 13897 | + shift shiftr keycode 40 = +h |
| 13898 | +keycode 41 = y |
| 13899 | + shiftr keycode 41 = +Y |
| 13900 | + shift shiftr keycode 41 = +y |
| 13901 | +keycode 42 = six asciicircum |
| 13902 | + shiftr keycode 42 = asciicircum |
| 13903 | + shift shiftr keycode 42 = asciicircum |
| 13904 | + control keycode 42 = Control_asciicircum |
| 13905 | + alt keycode 42 = Meta_six |
| 13906 | +keycode 43 = seven ampersand braceleft |
| 13907 | + shiftr keycode 43 = ampersand |
| 13908 | + shift shiftr keycode 43 = ampersand |
| 13909 | + control keycode 43 = Control_underscore |
| 13910 | + alt keycode 43 = Meta_seven |
| 13911 | +keycode 44 = u |
| 13912 | + shiftr keycode 44 = +U |
| 13913 | + shift shiftr keycode 44 = +u |
| 13914 | +keycode 45 = j |
| 13915 | + shiftr keycode 45 = +J |
| 13916 | + shift shiftr keycode 45 = +j |
| 13917 | +keycode 46 = m |
| 13918 | + shiftr keycode 46 = +M |
| 13919 | + shift shiftr keycode 46 = +m |
| 13920 | +keycode 47 = n |
| 13921 | + shiftr keycode 47 = +N |
| 13922 | + shift shiftr keycode 47 = +n |
| 13923 | + |
| 13924 | +# This is the "Backspace" key: |
| 13925 | +keycode 49 = Delete Delete |
| 13926 | + shiftr keycode 49 = Delete |
| 13927 | + shift shiftr keycode 49 = Delete |
| 13928 | + control keycode 49 = BackSpace |
| 13929 | + alt keycode 49 = Meta_Delete |
| 13930 | +keycode 50 = Num_Lock |
| 13931 | + shift keycode 50 = Bare_Num_Lock |
| 13932 | + shiftr keycode 50 = Bare_Num_Lock |
| 13933 | + shift shiftr keycode 50 = Bare_Num_Lock |
| 13934 | +# This is the "Delete" key: |
| 13935 | +keycode 51 = Remove |
| 13936 | + control alt keycode 51 = Boot |
| 13937 | + |
| 13938 | +keycode 53 = backslash bar |
| 13939 | + shiftr keycode 53 = bar |
| 13940 | + shift shiftr keycode 53 = bar |
| 13941 | + control keycode 53 = Control_backslash |
| 13942 | + alt keycode 53 = Meta_backslash |
| 13943 | +keycode 54 = Return |
| 13944 | + alt keycode 54 = Meta_Control_m |
| 13945 | +keycode 55 = space space |
| 13946 | + shiftr keycode 55 = space |
| 13947 | + shift shiftr keycode 55 = space |
| 13948 | + control keycode 55 = nul |
| 13949 | + alt keycode 55 = Meta_space |
| 13950 | +keycode 56 = g |
| 13951 | + shiftr keycode 56 = +G |
| 13952 | + shift shiftr keycode 56 = +g |
| 13953 | +keycode 57 = t |
| 13954 | + shiftr keycode 57 = +T |
| 13955 | + shift shiftr keycode 57 = +t |
| 13956 | +keycode 58 = five percent |
| 13957 | + shiftr keycode 58 = percent |
| 13958 | + shift shiftr keycode 58 = percent |
| 13959 | + control keycode 58 = Control_bracketright |
| 13960 | + alt keycode 58 = Meta_five |
| 13961 | +keycode 59 = four dollar dollar |
| 13962 | + shiftr keycode 59 = dollar |
| 13963 | + shift shiftr keycode 59 = dollar |
| 13964 | + control keycode 59 = Control_backslash |
| 13965 | + alt keycode 59 = Meta_four |
| 13966 | +keycode 60 = r |
| 13967 | + shiftr keycode 60 = +R |
| 13968 | + shift shiftr keycode 60 = +r |
| 13969 | +keycode 61 = f |
| 13970 | + shiftr keycode 61 = +F |
| 13971 | + shift shiftr keycode 61 = +f |
| 13972 | + altgr keycode 61 = Hex_F |
| 13973 | +keycode 62 = v |
| 13974 | + shiftr keycode 62 = +V |
| 13975 | + shift shiftr keycode 62 = +v |
| 13976 | +keycode 63 = b |
| 13977 | + shiftr keycode 63 = +B |
| 13978 | + shift shiftr keycode 63 = +b |
| 13979 | + altgr keycode 63 = Hex_B |
| 13980 | + |
| 13981 | +keycode 67 = three numbersign |
| 13982 | + shiftr keycode 67 = numbersign |
| 13983 | + shift shiftr keycode 67 = numbersign |
| 13984 | + control keycode 67 = Escape |
| 13985 | + alt keycode 67 = Meta_three |
| 13986 | +keycode 68 = e |
| 13987 | + shiftr keycode 68 = +E |
| 13988 | + shift shiftr keycode 68 = +e |
| 13989 | + altgr keycode 68 = Hex_E |
| 13990 | +keycode 69 = d |
| 13991 | + shiftr keycode 69 = +D |
| 13992 | + shift shiftr keycode 69 = +d |
| 13993 | + altgr keycode 69 = Hex_D |
| 13994 | +keycode 70 = c |
| 13995 | + shiftr keycode 70 = +C |
| 13996 | + shift shiftr keycode 70 = +c |
| 13997 | + altgr keycode 70 = Hex_C |
| 13998 | +keycode 71 = Right Incr_Console |
| 13999 | + shiftr keycode 71 = Incr_Console |
| 14000 | + shift shiftr keycode 71 = Incr_Console |
| 14001 | + alt keycode 71 = End |
| 14002 | + |
| 14003 | +keycode 75 = two at at |
| 14004 | + shiftr keycode 75 = at |
| 14005 | + shift shiftr keycode 75 = at |
| 14006 | + control keycode 75 = nul |
| 14007 | + shift control keycode 75 = nul |
| 14008 | + shiftr control keycode 75 = nul |
| 14009 | + shift shiftr control keycode 75 = nul |
| 14010 | + alt keycode 75 = Meta_two |
| 14011 | +keycode 76 = w |
| 14012 | + shiftr keycode 76 = +W |
| 14013 | + shift shiftr keycode 76 = +w |
| 14014 | +keycode 77 = s |
| 14015 | + shiftr keycode 77 = +S |
| 14016 | + shift shiftr keycode 77 = +s |
| 14017 | +keycode 78 = x |
| 14018 | + shiftr keycode 78 = +X |
| 14019 | + shift shiftr keycode 78 = +x |
| 14020 | +keycode 79 = Down Scroll_Forward |
| 14021 | + shiftr keycode 79 = Scroll_Forward |
| 14022 | + shift shiftr keycode 79 = Scroll_Forward |
| 14023 | + alt keycode 79 = Next |
| 14024 | +keycode 80 = Escape Escape |
| 14025 | + shiftr keycode 80 = Escape |
| 14026 | + shift shiftr keycode 80 = Escape |
| 14027 | + alt keycode 80 = Meta_Escape |
| 14028 | +keycode 81 = Tab Tab |
| 14029 | + shiftr keycode 81 = Tab |
| 14030 | + shift shiftr keycode 81 = Tab |
| 14031 | + alt keycode 81 = Meta_Tab |
| 14032 | +keycode 82 = grave asciitilde |
| 14033 | + shiftr keycode 82 = asciitilde |
| 14034 | + shift shiftr keycode 82 = asciitilde |
| 14035 | + control keycode 82 = nul |
| 14036 | + alt keycode 82 = Meta_grave |
| 14037 | +keycode 83 = one exclam |
| 14038 | + shiftr keycode 83 = exclam |
| 14039 | + shift shiftr keycode 83 = exclam |
| 14040 | + alt keycode 83 = Meta_one |
| 14041 | +keycode 84 = q |
| 14042 | + shiftr keycode 84 = +Q |
| 14043 | + shift shiftr keycode 84 = +q |
| 14044 | +keycode 85 = a |
| 14045 | + shiftr keycode 85 = +A |
| 14046 | + shift shiftr keycode 85 = +a |
| 14047 | + altgr keycode 85 = Hex_A |
| 14048 | +keycode 86 = z |
| 14049 | + shiftr keycode 86 = +Z |
| 14050 | + shift shiftr keycode 86 = +z |
| 14051 | + |
| 14052 | +# This is the windows key: |
| 14053 | +keycode 88 = Decr_Console |
| 14054 | +keycode 89 = Shift |
| 14055 | +keycode 90 = Control |
| 14056 | +keycode 91 = Control |
| 14057 | +keycode 92 = Alt |
| 14058 | +keycode 93 = AltGr |
| 14059 | +keycode 94 = ShiftR |
| 14060 | + shift keycode 94 = Caps_Lock |
| 14061 | --- a/drivers/char/indydog.c |
| 14062 | +++ b/drivers/char/indydog.c |
| 14063 | @@ -1,5 +1,5 @@ |
| 14064 | /* |
| 14065 | - * IndyDog 0.2 A Hardware Watchdog Device for SGI IP22 |
| 14066 | + * IndyDog 0.3 A Hardware Watchdog Device for SGI IP22 |
| 14067 | * |
| 14068 | * (c) Copyright 2002 Guido Guenther <agx@sigxcpu.org>, All Rights Reserved. |
| 14069 | * |
| 14070 | @@ -7,10 +7,10 @@ |
| 14071 | * modify it under the terms of the GNU General Public License |
| 14072 | * as published by the Free Software Foundation; either version |
| 14073 | * 2 of the License, or (at your option) any later version. |
| 14074 | - * |
| 14075 | + * |
| 14076 | * based on softdog.c by Alan Cox <alan@redhat.com> |
| 14077 | */ |
| 14078 | - |
| 14079 | + |
| 14080 | #include <linux/module.h> |
| 14081 | #include <linux/config.h> |
| 14082 | #include <linux/types.h> |
| 14083 | @@ -19,13 +19,12 @@ |
| 14084 | #include <linux/mm.h> |
| 14085 | #include <linux/miscdevice.h> |
| 14086 | #include <linux/watchdog.h> |
| 14087 | -#include <linux/smp_lock.h> |
| 14088 | #include <linux/init.h> |
| 14089 | #include <asm/uaccess.h> |
| 14090 | #include <asm/sgi/mc.h> |
| 14091 | |
| 14092 | -static unsigned long indydog_alive; |
| 14093 | -static int expect_close = 0; |
| 14094 | +#define PFX "indydog: " |
| 14095 | +static int indydog_alive; |
| 14096 | |
| 14097 | #ifdef CONFIG_WATCHDOG_NOWAYOUT |
| 14098 | static int nowayout = 1; |
| 14099 | @@ -33,10 +32,30 @@ static int nowayout = 1; |
| 14100 | static int nowayout = 0; |
| 14101 | #endif |
| 14102 | |
| 14103 | +#define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 14104 | + |
| 14105 | MODULE_PARM(nowayout,"i"); |
| 14106 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); |
| 14107 | |
| 14108 | -static inline void indydog_ping(void) |
| 14109 | +static void indydog_start(void) |
| 14110 | +{ |
| 14111 | + u32 mc_ctrl0 = sgimc->cpuctrl0; |
| 14112 | + |
| 14113 | + mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG; |
| 14114 | + sgimc->cpuctrl0 = mc_ctrl0; |
| 14115 | +} |
| 14116 | + |
| 14117 | +static void indydog_stop(void) |
| 14118 | +{ |
| 14119 | + u32 mc_ctrl0 = sgimc->cpuctrl0; |
| 14120 | + |
| 14121 | + mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG; |
| 14122 | + sgimc->cpuctrl0 = mc_ctrl0; |
| 14123 | + |
| 14124 | + printk(KERN_INFO PFX "Stopped watchdog timer.\n"); |
| 14125 | +} |
| 14126 | + |
| 14127 | +static void indydog_ping(void) |
| 14128 | { |
| 14129 | sgimc->watchdogt = 0; |
| 14130 | } |
| 14131 | @@ -46,18 +65,14 @@ static inline void indydog_ping(void) |
| 14132 | */ |
| 14133 | static int indydog_open(struct inode *inode, struct file *file) |
| 14134 | { |
| 14135 | - u32 mc_ctrl0; |
| 14136 | - |
| 14137 | - if (test_and_set_bit(0,&indydog_alive)) |
| 14138 | + if (indydog_alive) |
| 14139 | return -EBUSY; |
| 14140 | |
| 14141 | - if (nowayout) { |
| 14142 | + if (nowayout) |
| 14143 | MOD_INC_USE_COUNT; |
| 14144 | - } |
| 14145 | |
| 14146 | /* Activate timer */ |
| 14147 | - mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG; |
| 14148 | - sgimc->cpuctrl0 = mc_ctrl0; |
| 14149 | + indydog_start(); |
| 14150 | indydog_ping(); |
| 14151 | |
| 14152 | indydog_alive = 1; |
| 14153 | @@ -69,63 +84,48 @@ static int indydog_open(struct inode *in |
| 14154 | static int indydog_release(struct inode *inode, struct file *file) |
| 14155 | { |
| 14156 | /* Shut off the timer. |
| 14157 | - * Lock it in if it's a module and we set nowayout. */ |
| 14158 | - lock_kernel(); |
| 14159 | - if (expect_close) { |
| 14160 | - u32 mc_ctrl0 = sgimc->cpuctrl0; |
| 14161 | + * Lock it in if it's a module and we defined ...NOWAYOUT */ |
| 14162 | + if (!nowayout) { |
| 14163 | + u32 mc_ctrl0 = sgimc->cpuctrl0; |
| 14164 | mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG; |
| 14165 | sgimc->cpuctrl0 = mc_ctrl0; |
| 14166 | printk(KERN_INFO "Stopped watchdog timer.\n"); |
| 14167 | - } else |
| 14168 | - printk(KERN_CRIT "WDT device closed unexpectedly. WDT will not stop!\n"); |
| 14169 | - clear_bit(0, &indydog_alive); |
| 14170 | - unlock_kernel(); |
| 14171 | + } |
| 14172 | + indydog_alive = 0; |
| 14173 | |
| 14174 | return 0; |
| 14175 | } |
| 14176 | |
| 14177 | static ssize_t indydog_write(struct file *file, const char *data, size_t len, loff_t *ppos) |
| 14178 | { |
| 14179 | - /* Can't seek (pwrite) on this device */ |
| 14180 | + /* Can't seek (pwrite) on this device */ |
| 14181 | if (ppos != &file->f_pos) |
| 14182 | return -ESPIPE; |
| 14183 | |
| 14184 | - /* |
| 14185 | - * Refresh the timer. |
| 14186 | - */ |
| 14187 | + /* Refresh the timer. */ |
| 14188 | if (len) { |
| 14189 | - if (!nowayout) { |
| 14190 | - size_t i; |
| 14191 | - |
| 14192 | - /* In case it was set long ago */ |
| 14193 | - expect_close = 0; |
| 14194 | - |
| 14195 | - for (i = 0; i != len; i++) { |
| 14196 | - char c; |
| 14197 | - if (get_user(c, data + i)) |
| 14198 | - return -EFAULT; |
| 14199 | - if (c == 'V') |
| 14200 | - expect_close = 1; |
| 14201 | - } |
| 14202 | - } |
| 14203 | indydog_ping(); |
| 14204 | - return 1; |
| 14205 | } |
| 14206 | - return 0; |
| 14207 | + return len; |
| 14208 | } |
| 14209 | |
| 14210 | static int indydog_ioctl(struct inode *inode, struct file *file, |
| 14211 | unsigned int cmd, unsigned long arg) |
| 14212 | { |
| 14213 | + int options, retval = -EINVAL; |
| 14214 | static struct watchdog_info ident = { |
| 14215 | - options: WDIOF_MAGICCLOSE, |
| 14216 | - identity: "Hardware Watchdog for SGI IP22", |
| 14217 | + .options = WDIOF_KEEPALIVEPING | |
| 14218 | + WDIOF_MAGICCLOSE, |
| 14219 | + .firmware_version = 0, |
| 14220 | + .identity = "Hardware Watchdog for SGI IP22", |
| 14221 | }; |
| 14222 | + |
| 14223 | switch (cmd) { |
| 14224 | default: |
| 14225 | return -ENOIOCTLCMD; |
| 14226 | case WDIOC_GETSUPPORT: |
| 14227 | - if(copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident))) |
| 14228 | + if (copy_to_user((struct watchdog_info *)arg, |
| 14229 | + &ident, sizeof(ident))) |
| 14230 | return -EFAULT; |
| 14231 | return 0; |
| 14232 | case WDIOC_GETSTATUS: |
| 14233 | @@ -134,31 +134,53 @@ static int indydog_ioctl(struct inode *i |
| 14234 | case WDIOC_KEEPALIVE: |
| 14235 | indydog_ping(); |
| 14236 | return 0; |
| 14237 | + case WDIOC_GETTIMEOUT: |
| 14238 | + return put_user(WATCHDOG_TIMEOUT,(int *)arg); |
| 14239 | + case WDIOC_SETOPTIONS: |
| 14240 | + { |
| 14241 | + if (get_user(options, (int *)arg)) |
| 14242 | + return -EFAULT; |
| 14243 | + |
| 14244 | + if (options & WDIOS_DISABLECARD) { |
| 14245 | + indydog_stop(); |
| 14246 | + retval = 0; |
| 14247 | + } |
| 14248 | + |
| 14249 | + if (options & WDIOS_ENABLECARD) { |
| 14250 | + indydog_start(); |
| 14251 | + retval = 0; |
| 14252 | + } |
| 14253 | + |
| 14254 | + return retval; |
| 14255 | + } |
| 14256 | } |
| 14257 | } |
| 14258 | |
| 14259 | static struct file_operations indydog_fops = { |
| 14260 | - owner: THIS_MODULE, |
| 14261 | - write: indydog_write, |
| 14262 | - ioctl: indydog_ioctl, |
| 14263 | - open: indydog_open, |
| 14264 | - release: indydog_release, |
| 14265 | + .owner = THIS_MODULE, |
| 14266 | + .write = indydog_write, |
| 14267 | + .ioctl = indydog_ioctl, |
| 14268 | + .open = indydog_open, |
| 14269 | + .release = indydog_release, |
| 14270 | }; |
| 14271 | |
| 14272 | static struct miscdevice indydog_miscdev = { |
| 14273 | - minor: WATCHDOG_MINOR, |
| 14274 | - name: "watchdog", |
| 14275 | - fops: &indydog_fops, |
| 14276 | + .minor = WATCHDOG_MINOR, |
| 14277 | + .name = "watchdog", |
| 14278 | + .fops = &indydog_fops, |
| 14279 | }; |
| 14280 | |
| 14281 | -static const char banner[] __initdata = KERN_INFO "Hardware Watchdog Timer for SGI IP22: 0.2\n"; |
| 14282 | +static char banner[] __initdata = |
| 14283 | + KERN_INFO PFX "Hardware Watchdog Timer for SGI IP22: 0.3\n"; |
| 14284 | |
| 14285 | static int __init watchdog_init(void) |
| 14286 | { |
| 14287 | int ret = misc_register(&indydog_miscdev); |
| 14288 | - |
| 14289 | - if (ret) |
| 14290 | + if (ret) { |
| 14291 | + printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", |
| 14292 | + WATCHDOG_MINOR, ret); |
| 14293 | return ret; |
| 14294 | + } |
| 14295 | |
| 14296 | printk(banner); |
| 14297 | |
| 14298 | @@ -172,4 +194,7 @@ static void __exit watchdog_exit(void) |
| 14299 | |
| 14300 | module_init(watchdog_init); |
| 14301 | module_exit(watchdog_exit); |
| 14302 | + |
| 14303 | +MODULE_AUTHOR("Guido Guenther <agx@sigxcpu.org>"); |
| 14304 | +MODULE_DESCRIPTION("Hardware Watchdog Device for SGI IP22"); |
| 14305 | MODULE_LICENSE("GPL"); |
| 14306 | --- a/drivers/char/ip27-rtc.c |
| 14307 | +++ b/drivers/char/ip27-rtc.c |
| 14308 | @@ -44,6 +44,7 @@ |
| 14309 | #include <asm/sn/klconfig.h> |
| 14310 | #include <asm/sn/sn0/ip27.h> |
| 14311 | #include <asm/sn/sn0/hub.h> |
| 14312 | +#include <asm/sn/sn_private.h> |
| 14313 | |
| 14314 | static int rtc_ioctl(struct inode *inode, struct file *file, |
| 14315 | unsigned int cmd, unsigned long arg); |
| 14316 | @@ -209,11 +210,8 @@ static struct miscdevice rtc_dev= |
| 14317 | |
| 14318 | static int __init rtc_init(void) |
| 14319 | { |
| 14320 | - nasid_t nid; |
| 14321 | - |
| 14322 | - nid = get_nasid(); |
| 14323 | rtc = (struct m48t35_rtc *) |
| 14324 | - (KL_CONFIG_CH_CONS_INFO(nid)->memory_base + IOC3_BYTEBUS_DEV0); |
| 14325 | + (KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + IOC3_BYTEBUS_DEV0); |
| 14326 | |
| 14327 | printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION); |
| 14328 | if (misc_register(&rtc_dev)) { |
| 14329 | @@ -325,3 +323,7 @@ static void get_rtc_time(struct rtc_time |
| 14330 | |
| 14331 | rtc_tm->tm_mon--; |
| 14332 | } |
| 14333 | + |
| 14334 | +MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); |
| 14335 | +MODULE_DESCRIPTION("SGI IP27 M48T35 RTC driver"); |
| 14336 | +MODULE_LICENSE("GPL"); |
| 14337 | --- a/drivers/char/Makefile |
| 14338 | +++ b/drivers/char/Makefile |
| 14339 | @@ -48,7 +48,12 @@ ifeq ($(ARCH),mips) |
| 14340 | KEYBD = |
| 14341 | endif |
| 14342 | ifeq ($(CONFIG_VR41XX_KIU),y) |
| 14343 | - KEYMAP = |
| 14344 | + ifeq ($(CONFIG_IBM_WORKPAD),y) |
| 14345 | + KEYMAP = ibm_workpad_keymap.o |
| 14346 | + endif |
| 14347 | + ifeq ($(CONFIG_VICTOR_MPC30X),y) |
| 14348 | + KEYMAP = victor_mpc30x_keymap.o |
| 14349 | + endif |
| 14350 | KEYBD = vr41xx_keyb.o |
| 14351 | endif |
| 14352 | endif |
| 14353 | @@ -251,7 +256,6 @@ obj-$(CONFIG_MK712_MOUSE) += mk712.o |
| 14354 | obj-$(CONFIG_RTC) += rtc.o |
| 14355 | obj-$(CONFIG_GEN_RTC) += genrtc.o |
| 14356 | obj-$(CONFIG_EFI_RTC) += efirtc.o |
| 14357 | -obj-$(CONFIG_SGI_DS1286) += ds1286.o |
| 14358 | obj-$(CONFIG_MIPS_RTC) += mips_rtc.o |
| 14359 | obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o |
| 14360 | ifeq ($(CONFIG_PPC),) |
| 14361 | @@ -259,6 +263,7 @@ ifeq ($(CONFIG_PPC),) |
| 14362 | endif |
| 14363 | obj-$(CONFIG_TOSHIBA) += toshiba.o |
| 14364 | obj-$(CONFIG_I8K) += i8k.o |
| 14365 | +obj-$(CONFIG_DS1286) += ds1286.o |
| 14366 | obj-$(CONFIG_DS1620) += ds1620.o |
| 14367 | obj-$(CONFIG_DS1742) += ds1742.o |
| 14368 | obj-$(CONFIG_INTEL_RNG) += i810_rng.o |
| 14369 | @@ -270,6 +275,7 @@ obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o |
| 14370 | |
| 14371 | obj-$(CONFIG_ITE_GPIO) += ite_gpio.o |
| 14372 | obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o |
| 14373 | +obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o |
| 14374 | obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o |
| 14375 | obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o |
| 14376 | obj-$(CONFIG_COBALT_LCD) += lcd.o |
| 14377 | @@ -357,3 +363,9 @@ defkeymap.c: defkeymap.map |
| 14378 | |
| 14379 | qtronixmap.c: qtronixmap.map |
| 14380 | set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@ |
| 14381 | + |
| 14382 | +ibm_workpad_keymap.c: ibm_workpad_keymap.map |
| 14383 | + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@ |
| 14384 | + |
| 14385 | +victor_mpc30x_keymap.c: victor_mpc30x_keymap.map |
| 14386 | + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@ |
| 14387 | --- a/drivers/char/mips_rtc.c |
| 14388 | +++ b/drivers/char/mips_rtc.c |
| 14389 | @@ -53,14 +53,6 @@ |
| 14390 | #include <asm/io.h> |
| 14391 | #include <asm/uaccess.h> |
| 14392 | #include <asm/system.h> |
| 14393 | - |
| 14394 | -/* |
| 14395 | - * Check machine |
| 14396 | - */ |
| 14397 | -#if !defined(CONFIG_MIPS) || !defined(CONFIG_NEW_TIME_C) |
| 14398 | -#error "This driver is for MIPS machines with CONFIG_NEW_TIME_C defined" |
| 14399 | -#endif |
| 14400 | - |
| 14401 | #include <asm/time.h> |
| 14402 | |
| 14403 | static unsigned long rtc_status = 0; /* bitmapped status byte. */ |
| 14404 | --- a/drivers/char/sb1250_duart.c |
| 14405 | +++ b/drivers/char/sb1250_duart.c |
| 14406 | @@ -328,10 +328,11 @@ static int duart_write(struct tty_struct |
| 14407 | if (c <= 0) break; |
| 14408 | |
| 14409 | if (from_user) { |
| 14410 | + spin_unlock_irqrestore(&us->outp_lock, flags); |
| 14411 | if (copy_from_user(us->outp_buf + us->outp_tail, buf, c)) { |
| 14412 | - spin_unlock_irqrestore(&us->outp_lock, flags); |
| 14413 | return -EFAULT; |
| 14414 | } |
| 14415 | + spin_lock_irqsave(&us->outp_lock, flags); |
| 14416 | } else { |
| 14417 | memcpy(us->outp_buf + us->outp_tail, buf, c); |
| 14418 | } |
| 14419 | @@ -498,9 +499,31 @@ static void duart_set_termios(struct tty |
| 14420 | duart_set_cflag(us->line, tty->termios->c_cflag); |
| 14421 | } |
| 14422 | |
| 14423 | +static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) { |
| 14424 | + |
| 14425 | + struct serial_struct tmp; |
| 14426 | + |
| 14427 | + memset(&tmp, 0, sizeof(tmp)); |
| 14428 | + |
| 14429 | + tmp.type=PORT_SB1250; |
| 14430 | + tmp.line=us->line; |
| 14431 | + tmp.port=A_DUART_CHANREG(tmp.line,0); |
| 14432 | + tmp.irq=K_INT_UART_0 + tmp.line; |
| 14433 | + tmp.xmit_fifo_size=16; /* fixed by hw */ |
| 14434 | + tmp.baud_base=5000000; |
| 14435 | + tmp.io_type=SERIAL_IO_MEM; |
| 14436 | + |
| 14437 | + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo))) |
| 14438 | + return -EFAULT; |
| 14439 | + |
| 14440 | + return 0; |
| 14441 | +} |
| 14442 | + |
| 14443 | static int duart_ioctl(struct tty_struct *tty, struct file * file, |
| 14444 | unsigned int cmd, unsigned long arg) |
| 14445 | { |
| 14446 | + uart_state_t *us = (uart_state_t *) tty->driver_data; |
| 14447 | + |
| 14448 | /* if (serial_paranoia_check(info, tty->device, "rs_ioctl")) |
| 14449 | return -ENODEV;*/ |
| 14450 | switch (cmd) { |
| 14451 | @@ -517,7 +540,7 @@ static int duart_ioctl(struct tty_struct |
| 14452 | printk("Ignoring TIOCMSET\n"); |
| 14453 | break; |
| 14454 | case TIOCGSERIAL: |
| 14455 | - printk("Ignoring TIOCGSERIAL\n"); |
| 14456 | + return get_serial_info(us,(struct serial_struct *) arg); |
| 14457 | break; |
| 14458 | case TIOCSSERIAL: |
| 14459 | printk("Ignoring TIOCSSERIAL\n"); |
| 14460 | --- a/drivers/char/serial.c |
| 14461 | +++ b/drivers/char/serial.c |
| 14462 | @@ -62,6 +62,12 @@ |
| 14463 | * Robert Schwebel <robert@schwebel.de>, |
| 14464 | * Juergen Beisert <jbeisert@eurodsn.de>, |
| 14465 | * Theodore Ts'o <tytso@mit.edu> |
| 14466 | + * |
| 14467 | + * 10/00: Added suport for MIPS Atlas board. |
| 14468 | + * 11/00: Hooks for serial kernel debug port support added. |
| 14469 | + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, |
| 14470 | + * carstenl@mips.com |
| 14471 | + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| 14472 | */ |
| 14473 | |
| 14474 | static char *serial_version = "5.05c"; |
| 14475 | @@ -413,6 +419,22 @@ static inline int serial_paranoia_check( |
| 14476 | return 0; |
| 14477 | } |
| 14478 | |
| 14479 | +#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD) |
| 14480 | + |
| 14481 | +#include <asm/mips-boards/atlas.h> |
| 14482 | + |
| 14483 | +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset) |
| 14484 | +{ |
| 14485 | + return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff); |
| 14486 | +} |
| 14487 | + |
| 14488 | +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value) |
| 14489 | +{ |
| 14490 | + *(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value; |
| 14491 | +} |
| 14492 | + |
| 14493 | +#else |
| 14494 | + |
| 14495 | static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset) |
| 14496 | { |
| 14497 | switch (info->io_type) { |
| 14498 | @@ -447,6 +469,8 @@ static _INLINE_ void serial_out(struct a |
| 14499 | outb(value, info->port+offset); |
| 14500 | } |
| 14501 | } |
| 14502 | +#endif |
| 14503 | + |
| 14504 | |
| 14505 | /* |
| 14506 | * We used to support using pause I/O for certain machines. We |
| 14507 | --- /dev/null |
| 14508 | +++ b/drivers/char/victor_mpc30x_keymap.map |
| 14509 | @@ -0,0 +1,102 @@ |
| 14510 | +# Victor Interlink MP-C303/304 keyboard keymap |
| 14511 | +# |
| 14512 | +# Copyright (C) 2003 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> |
| 14513 | +# |
| 14514 | +# This file is subject to the terms and conditions of the GNU General Public |
| 14515 | +# License. See the file "COPYING" in the main directory of this archive |
| 14516 | +# for more details. |
| 14517 | +keymaps 0-1,4-5,8-9,12 |
| 14518 | +alt_is_meta |
| 14519 | +strings as usual |
| 14520 | +compose as usual for "iso-8859-1" |
| 14521 | + |
| 14522 | +# First line |
| 14523 | +keycode 89 = Escape |
| 14524 | +keycode 9 = Delete |
| 14525 | + |
| 14526 | +# 2nd line |
| 14527 | +keycode 73 = one exclam |
| 14528 | +keycode 18 = two quotedbl |
| 14529 | +keycode 92 = three numbersign |
| 14530 | + control keycode 92 = Escape |
| 14531 | +keycode 53 = four dollar |
| 14532 | + control keycode 53 = Control_backslash |
| 14533 | +keycode 21 = five percent |
| 14534 | + control keycode 21 = Control_bracketright |
| 14535 | +keycode 50 = six ampersand |
| 14536 | + control keycode 50 = Control_underscore |
| 14537 | +keycode 48 = seven apostrophe |
| 14538 | +keycode 51 = eight parenleft |
| 14539 | +keycode 16 = nine parenright |
| 14540 | +keycode 80 = zero asciitilde |
| 14541 | + control keycode 80 = nul |
| 14542 | +keycode 49 = minus equal |
| 14543 | +keycode 30 = asciicircum asciitilde |
| 14544 | + control keycode 30 = Control_asciicircum |
| 14545 | +keycode 5 = backslash bar |
| 14546 | + control keycode 5 = Control_backslash |
| 14547 | +keycode 13 = BackSpace |
| 14548 | +# 3rd line |
| 14549 | +keycode 57 = Tab |
| 14550 | +keycode 74 = q |
| 14551 | +keycode 26 = w |
| 14552 | +keycode 81 = e |
| 14553 | +keycode 29 = r |
| 14554 | +keycode 37 = t |
| 14555 | +keycode 45 = y |
| 14556 | +keycode 72 = u |
| 14557 | +keycode 24 = i |
| 14558 | +keycode 32 = o |
| 14559 | +keycode 41 = p |
| 14560 | +keycode 1 = at grave |
| 14561 | + control keycode 1 = nul |
| 14562 | +keycode 54 = bracketleft braceleft |
| 14563 | +keycode 63 = Return |
| 14564 | + alt keycode 63 = Meta_Control_m |
| 14565 | +# 4th line |
| 14566 | +keycode 23 = Caps_Lock |
| 14567 | +keycode 34 = a |
| 14568 | +keycode 66 = s |
| 14569 | +keycode 52 = d |
| 14570 | +keycode 20 = f |
| 14571 | +keycode 84 = g |
| 14572 | +keycode 67 = h |
| 14573 | +keycode 64 = j |
| 14574 | +keycode 17 = k |
| 14575 | +keycode 83 = l |
| 14576 | +keycode 22 = semicolon plus |
| 14577 | +keycode 61 = colon asterisk |
| 14578 | + control keycode 61 = Control_g |
| 14579 | +keycode 65 = bracketright braceright |
| 14580 | + control keycode 65 = Control_bracketright |
| 14581 | +# 5th line |
| 14582 | +keycode 91 = Shift |
| 14583 | +keycode 76 = z |
| 14584 | +keycode 68 = x |
| 14585 | +keycode 28 = c |
| 14586 | +keycode 36 = v |
| 14587 | +keycode 44 = b |
| 14588 | +keycode 19 = n |
| 14589 | +keycode 27 = m |
| 14590 | +keycode 35 = comma less |
| 14591 | +keycode 3 = period greater |
| 14592 | + control keycode 3 = Compose |
| 14593 | +keycode 38 = slash question |
| 14594 | + control keycode 38 = Delete |
| 14595 | + shift control keycode 38 = Delete |
| 14596 | +keycode 6 = backslash underscore |
| 14597 | + control keycode 6 = Control_backslash |
| 14598 | +keycode 55 = Up |
| 14599 | + alt keycode 55 = PageUp |
| 14600 | +keycode 14 = Shift |
| 14601 | +# 6th line |
| 14602 | +keycode 56 = Control |
| 14603 | +keycode 42 = Alt |
| 14604 | +keycode 33 = space |
| 14605 | + control keycode 33 = nul |
| 14606 | +keycode 7 = Left |
| 14607 | + alt keycode 7 = Home |
| 14608 | +keycode 31 = Down |
| 14609 | + alt keycode 31 = PageDown |
| 14610 | +keycode 47 = Right |
| 14611 | + alt keycode 47 = End |
| 14612 | --- a/drivers/char/vr41xx_keyb.c |
| 14613 | +++ b/drivers/char/vr41xx_keyb.c |
| 14614 | @@ -308,7 +308,7 @@ void __devinit kbd_init_hw(void) |
| 14615 | if (found != 0) { |
| 14616 | kiu_base = VRC4173_KIU_OFFSET; |
| 14617 | mkiuintreg = VRC4173_MKIUINTREG_OFFSET; |
| 14618 | - vrc4173_clock_supply(VRC4173_KIU_CLOCK); |
| 14619 | + vrc4173_supply_clock(VRC4173_KIU_CLOCK); |
| 14620 | } |
| 14621 | } |
| 14622 | #endif |
| 14623 | @@ -325,7 +325,7 @@ void __devinit kbd_init_hw(void) |
| 14624 | |
| 14625 | if (current_cpu_data.cputype == CPU_VR4111 || |
| 14626 | current_cpu_data.cputype == CPU_VR4121) |
| 14627 | - vr41xx_clock_supply(KIU_CLOCK); |
| 14628 | + vr41xx_supply_clock(KIU_CLOCK); |
| 14629 | |
| 14630 | kiu_writew(KIURST_KIURST, KIURST); |
| 14631 | |
| 14632 | --- a/drivers/i2c/Config.in |
| 14633 | +++ b/drivers/i2c/Config.in |
| 14634 | @@ -57,6 +57,10 @@ if [ "$CONFIG_I2C" != "n" ]; then |
| 14635 | if [ "$CONFIG_SGI_IP22" = "y" ]; then |
| 14636 | dep_tristate 'I2C SGI interfaces' CONFIG_I2C_ALGO_SGI $CONFIG_I2C |
| 14637 | fi |
| 14638 | + |
| 14639 | + if [ "$CONFIG_SOC_AU1550" = "y" -o "$CONFIG_SOC_AU1200" ]; then |
| 14640 | + dep_tristate 'Au1550/Au1200 SMBus interface' CONFIG_I2C_ALGO_AU1550 $CONFIG_I2C |
| 14641 | + fi |
| 14642 | |
| 14643 | # This is needed for automatic patch generation: sensors code starts here |
| 14644 | # This is needed for automatic patch generation: sensors code ends here |
| 14645 | --- /dev/null |
| 14646 | +++ b/drivers/i2c/i2c-algo-au1550.c |
| 14647 | @@ -0,0 +1,340 @@ |
| 14648 | +/* |
| 14649 | + * i2c-algo-au1550.c: SMBus (i2c) driver algorithms for Alchemy PSC interface |
| 14650 | + * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> |
| 14651 | + * |
| 14652 | + * The documentation describes this as an SMBus controller, but it doesn't |
| 14653 | + * understand any of the SMBus protocol in hardware. It's really an I2C |
| 14654 | + * controller that could emulate most of the SMBus in software. |
| 14655 | + */ |
| 14656 | + |
| 14657 | +#include <linux/kernel.h> |
| 14658 | +#include <linux/module.h> |
| 14659 | +#include <linux/init.h> |
| 14660 | +#include <linux/errno.h> |
| 14661 | +#include <linux/delay.h> |
| 14662 | + |
| 14663 | +#include <asm/au1000.h> |
| 14664 | +#include <asm/au1xxx_psc.h> |
| 14665 | + |
| 14666 | +#include <linux/i2c.h> |
| 14667 | +#include <linux/i2c-algo-au1550.h> |
| 14668 | + |
| 14669 | +static int |
| 14670 | +wait_xfer_done(struct i2c_algo_au1550_data *adap) |
| 14671 | +{ |
| 14672 | + u32 stat; |
| 14673 | + int i; |
| 14674 | + volatile psc_smb_t *sp; |
| 14675 | + |
| 14676 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14677 | + |
| 14678 | + /* Wait for Tx FIFO Underflow. |
| 14679 | + */ |
| 14680 | + for (i = 0; i < adap->xfer_timeout; i++) { |
| 14681 | + stat = sp->psc_smbevnt; |
| 14682 | + au_sync(); |
| 14683 | + if ((stat & PSC_SMBEVNT_TU) != 0) { |
| 14684 | + /* Clear it. */ |
| 14685 | + sp->psc_smbevnt = PSC_SMBEVNT_TU; |
| 14686 | + au_sync(); |
| 14687 | + return 0; |
| 14688 | + } |
| 14689 | + udelay(1); |
| 14690 | + } |
| 14691 | + |
| 14692 | + return -ETIMEDOUT; |
| 14693 | +} |
| 14694 | + |
| 14695 | +static int |
| 14696 | +wait_ack(struct i2c_algo_au1550_data *adap) |
| 14697 | +{ |
| 14698 | + u32 stat; |
| 14699 | + volatile psc_smb_t *sp; |
| 14700 | + |
| 14701 | + if (wait_xfer_done(adap)) |
| 14702 | + return -ETIMEDOUT; |
| 14703 | + |
| 14704 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14705 | + |
| 14706 | + stat = sp->psc_smbevnt; |
| 14707 | + au_sync(); |
| 14708 | + |
| 14709 | + if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) |
| 14710 | + return -ETIMEDOUT; |
| 14711 | + |
| 14712 | + return 0; |
| 14713 | +} |
| 14714 | + |
| 14715 | +static int |
| 14716 | +wait_master_done(struct i2c_algo_au1550_data *adap) |
| 14717 | +{ |
| 14718 | + u32 stat; |
| 14719 | + int i; |
| 14720 | + volatile psc_smb_t *sp; |
| 14721 | + |
| 14722 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14723 | + |
| 14724 | + /* Wait for Master Done. |
| 14725 | + */ |
| 14726 | + for (i = 0; i < adap->xfer_timeout; i++) { |
| 14727 | + stat = sp->psc_smbevnt; |
| 14728 | + au_sync(); |
| 14729 | + if ((stat & PSC_SMBEVNT_MD) != 0) |
| 14730 | + return 0; |
| 14731 | + udelay(1); |
| 14732 | + } |
| 14733 | + |
| 14734 | + return -ETIMEDOUT; |
| 14735 | +} |
| 14736 | + |
| 14737 | +static int |
| 14738 | +do_address(struct i2c_algo_au1550_data *adap, unsigned int addr, int rd) |
| 14739 | +{ |
| 14740 | + volatile psc_smb_t *sp; |
| 14741 | + u32 stat; |
| 14742 | + |
| 14743 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14744 | + |
| 14745 | + /* Reset the FIFOs, clear events. |
| 14746 | + */ |
| 14747 | + sp->psc_smbpcr = PSC_SMBPCR_DC; |
| 14748 | + sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; |
| 14749 | + au_sync(); |
| 14750 | + do { |
| 14751 | + stat = sp->psc_smbpcr; |
| 14752 | + au_sync(); |
| 14753 | + } while ((stat & PSC_SMBPCR_DC) != 0); |
| 14754 | + |
| 14755 | + /* Write out the i2c chip address and specify operation |
| 14756 | + */ |
| 14757 | + addr <<= 1; |
| 14758 | + if (rd) |
| 14759 | + addr |= 1; |
| 14760 | + |
| 14761 | + /* Put byte into fifo, start up master. |
| 14762 | + */ |
| 14763 | + sp->psc_smbtxrx = addr; |
| 14764 | + au_sync(); |
| 14765 | + sp->psc_smbpcr = PSC_SMBPCR_MS; |
| 14766 | + au_sync(); |
| 14767 | + if (wait_ack(adap)) |
| 14768 | + return -EIO; |
| 14769 | + return 0; |
| 14770 | +} |
| 14771 | + |
| 14772 | +static u32 |
| 14773 | +wait_for_rx_byte(struct i2c_algo_au1550_data *adap, u32 *ret_data) |
| 14774 | +{ |
| 14775 | + int j; |
| 14776 | + u32 data, stat; |
| 14777 | + volatile psc_smb_t *sp; |
| 14778 | + |
| 14779 | + if (wait_xfer_done(adap)) |
| 14780 | + return -EIO; |
| 14781 | + |
| 14782 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14783 | + |
| 14784 | + j = adap->xfer_timeout * 100; |
| 14785 | + do { |
| 14786 | + j--; |
| 14787 | + if (j <= 0) |
| 14788 | + return -EIO; |
| 14789 | + |
| 14790 | + stat = sp->psc_smbstat; |
| 14791 | + au_sync(); |
| 14792 | + if ((stat & PSC_SMBSTAT_RE) == 0) |
| 14793 | + j = 0; |
| 14794 | + else |
| 14795 | + udelay(1); |
| 14796 | + } while (j > 0); |
| 14797 | + data = sp->psc_smbtxrx; |
| 14798 | + au_sync(); |
| 14799 | + *ret_data = data; |
| 14800 | + |
| 14801 | + return 0; |
| 14802 | +} |
| 14803 | + |
| 14804 | +static int |
| 14805 | +i2c_read(struct i2c_algo_au1550_data *adap, unsigned char *buf, |
| 14806 | + unsigned int len) |
| 14807 | +{ |
| 14808 | + int i; |
| 14809 | + u32 data; |
| 14810 | + volatile psc_smb_t *sp; |
| 14811 | + |
| 14812 | + if (len == 0) |
| 14813 | + return 0; |
| 14814 | + |
| 14815 | + /* A read is performed by stuffing the transmit fifo with |
| 14816 | + * zero bytes for timing, waiting for bytes to appear in the |
| 14817 | + * receive fifo, then reading the bytes. |
| 14818 | + */ |
| 14819 | + |
| 14820 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14821 | + |
| 14822 | + i = 0; |
| 14823 | + while (i < (len-1)) { |
| 14824 | + sp->psc_smbtxrx = 0; |
| 14825 | + au_sync(); |
| 14826 | + if (wait_for_rx_byte(adap, &data)) |
| 14827 | + return -EIO; |
| 14828 | + |
| 14829 | + buf[i] = data; |
| 14830 | + i++; |
| 14831 | + } |
| 14832 | + |
| 14833 | + /* The last byte has to indicate transfer done. |
| 14834 | + */ |
| 14835 | + sp->psc_smbtxrx = PSC_SMBTXRX_STP; |
| 14836 | + au_sync(); |
| 14837 | + if (wait_master_done(adap)) |
| 14838 | + return -EIO; |
| 14839 | + |
| 14840 | + data = sp->psc_smbtxrx; |
| 14841 | + au_sync(); |
| 14842 | + buf[i] = data; |
| 14843 | + return 0; |
| 14844 | +} |
| 14845 | + |
| 14846 | +static int |
| 14847 | +i2c_write(struct i2c_algo_au1550_data *adap, unsigned char *buf, |
| 14848 | + unsigned int len) |
| 14849 | +{ |
| 14850 | + int i; |
| 14851 | + u32 data; |
| 14852 | + volatile psc_smb_t *sp; |
| 14853 | + |
| 14854 | + if (len == 0) |
| 14855 | + return 0; |
| 14856 | + |
| 14857 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14858 | + |
| 14859 | + i = 0; |
| 14860 | + while (i < (len-1)) { |
| 14861 | + data = buf[i]; |
| 14862 | + sp->psc_smbtxrx = data; |
| 14863 | + au_sync(); |
| 14864 | + if (wait_ack(adap)) |
| 14865 | + return -EIO; |
| 14866 | + i++; |
| 14867 | + } |
| 14868 | + |
| 14869 | + /* The last byte has to indicate transfer done. |
| 14870 | + */ |
| 14871 | + data = buf[i]; |
| 14872 | + data |= PSC_SMBTXRX_STP; |
| 14873 | + sp->psc_smbtxrx = data; |
| 14874 | + au_sync(); |
| 14875 | + if (wait_master_done(adap)) |
| 14876 | + return -EIO; |
| 14877 | + return 0; |
| 14878 | +} |
| 14879 | + |
| 14880 | +static int |
| 14881 | +au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) |
| 14882 | +{ |
| 14883 | + struct i2c_algo_au1550_data *adap = i2c_adap->algo_data; |
| 14884 | + struct i2c_msg *p; |
| 14885 | + int i, err = 0; |
| 14886 | + |
| 14887 | + for (i = 0; !err && i < num; i++) { |
| 14888 | + p = &msgs[i]; |
| 14889 | + err = do_address(adap, p->addr, p->flags & I2C_M_RD); |
| 14890 | + if (err || !p->len) |
| 14891 | + continue; |
| 14892 | + if (p->flags & I2C_M_RD) |
| 14893 | + err = i2c_read(adap, p->buf, p->len); |
| 14894 | + else |
| 14895 | + err = i2c_write(adap, p->buf, p->len); |
| 14896 | + } |
| 14897 | + |
| 14898 | + /* Return the number of messages processed, or the error code. |
| 14899 | + */ |
| 14900 | + if (err == 0) |
| 14901 | + err = num; |
| 14902 | + return err; |
| 14903 | +} |
| 14904 | + |
| 14905 | +static u32 |
| 14906 | +au1550_func(struct i2c_adapter *adap) |
| 14907 | +{ |
| 14908 | + return I2C_FUNC_I2C; |
| 14909 | +} |
| 14910 | + |
| 14911 | +static struct i2c_algorithm au1550_algo = { |
| 14912 | + .name = "Au1550 algorithm", |
| 14913 | + .id = I2C_ALGO_AU1550, |
| 14914 | + .master_xfer = au1550_xfer, |
| 14915 | + .functionality = au1550_func, |
| 14916 | +}; |
| 14917 | + |
| 14918 | +/* |
| 14919 | + * registering functions to load algorithms at runtime |
| 14920 | + * Prior to calling us, the 50MHz clock frequency and routing |
| 14921 | + * must have been set up for the PSC indicated by the adapter. |
| 14922 | + */ |
| 14923 | +int |
| 14924 | +i2c_au1550_add_bus(struct i2c_adapter *i2c_adap) |
| 14925 | +{ |
| 14926 | + struct i2c_algo_au1550_data *adap = i2c_adap->algo_data; |
| 14927 | + volatile psc_smb_t *sp; |
| 14928 | + u32 stat; |
| 14929 | + |
| 14930 | + i2c_adap->algo = &au1550_algo; |
| 14931 | + |
| 14932 | + /* Now, set up the PSC for SMBus PIO mode. |
| 14933 | + */ |
| 14934 | + sp = (volatile psc_smb_t *)(adap->psc_base); |
| 14935 | + sp->psc_ctrl = PSC_CTRL_DISABLE; |
| 14936 | + au_sync(); |
| 14937 | + sp->psc_sel = PSC_SEL_PS_SMBUSMODE; |
| 14938 | + sp->psc_smbcfg = 0; |
| 14939 | + au_sync(); |
| 14940 | + sp->psc_ctrl = PSC_CTRL_ENABLE; |
| 14941 | + au_sync(); |
| 14942 | + do { |
| 14943 | + stat = sp->psc_smbstat; |
| 14944 | + au_sync(); |
| 14945 | + } while ((stat & PSC_SMBSTAT_SR) == 0); |
| 14946 | + |
| 14947 | + sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | |
| 14948 | + PSC_SMBCFG_DD_DISABLE); |
| 14949 | + |
| 14950 | + /* Divide by 8 to get a 6.25 MHz clock. The later protocol |
| 14951 | + * timings are based on this clock. |
| 14952 | + */ |
| 14953 | + sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV2); |
| 14954 | + sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; |
| 14955 | + au_sync(); |
| 14956 | + |
| 14957 | + /* Set the protocol timer values. See Table 71 in the |
| 14958 | + * Au1550 Data Book for standard timing values. |
| 14959 | + */ |
| 14960 | + sp->psc_smbtmr = PSC_SMBTMR_SET_TH(2) | PSC_SMBTMR_SET_PS(15) | \ |
| 14961 | + PSC_SMBTMR_SET_PU(11) | PSC_SMBTMR_SET_SH(11) | \ |
| 14962 | + PSC_SMBTMR_SET_SU(11) | PSC_SMBTMR_SET_CL(15) | \ |
| 14963 | + PSC_SMBTMR_SET_CH(11); |
| 14964 | + au_sync(); |
| 14965 | + |
| 14966 | + sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; |
| 14967 | + do { |
| 14968 | + stat = sp->psc_smbstat; |
| 14969 | + au_sync(); |
| 14970 | + } while ((stat & PSC_SMBSTAT_DR) == 0); |
| 14971 | + |
| 14972 | + return i2c_add_adapter(i2c_adap); |
| 14973 | +} |
| 14974 | + |
| 14975 | + |
| 14976 | +int |
| 14977 | +i2c_au1550_del_bus(struct i2c_adapter *adap) |
| 14978 | +{ |
| 14979 | + return i2c_del_adapter(adap); |
| 14980 | +} |
| 14981 | + |
| 14982 | +EXPORT_SYMBOL(i2c_au1550_add_bus); |
| 14983 | +EXPORT_SYMBOL(i2c_au1550_del_bus); |
| 14984 | + |
| 14985 | +MODULE_AUTHOR("Dan Malek <dan@embeddededge.com>"); |
| 14986 | +MODULE_DESCRIPTION("SMBus Au1550 algorithm"); |
| 14987 | +MODULE_LICENSE("GPL"); |
| 14988 | --- /dev/null |
| 14989 | +++ b/drivers/i2c/i2c-au1550.c |
| 14990 | @@ -0,0 +1,154 @@ |
| 14991 | +/* |
| 14992 | + * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface |
| 14993 | + * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> |
| 14994 | + * |
| 14995 | + * This is just a skeleton adapter to use with the Au1550 PSC |
| 14996 | + * algorithm. It was developed for the Pb1550, but will work with |
| 14997 | + * any Au1550 board that has a similar PSC configuration. |
| 14998 | + * |
| 14999 | + * This program is free software; you can redistribute it and/or |
| 15000 | + * modify it under the terms of the GNU General Public License |
| 15001 | + * as published by the Free Software Foundation; either version 2 |
| 15002 | + * of the License, or (at your option) any later version. |
| 15003 | + * |
| 15004 | + * This program is distributed in the hope that it will be useful, |
| 15005 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15006 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15007 | + * GNU General Public License for more details. |
| 15008 | + * |
| 15009 | + * You should have received a copy of the GNU General Public License |
| 15010 | + * along with this program; if not, write to the Free Software |
| 15011 | + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 15012 | + */ |
| 15013 | + |
| 15014 | +#include <linux/config.h> |
| 15015 | +#include <linux/kernel.h> |
| 15016 | +#include <linux/module.h> |
| 15017 | +#include <linux/init.h> |
| 15018 | +#include <linux/errno.h> |
| 15019 | + |
| 15020 | +#include <asm/au1000.h> |
| 15021 | +#include <asm/au1xxx_psc.h> |
| 15022 | +#if defined( CONFIG_MIPS_PB1550 ) |
| 15023 | + #include <asm/pb1550.h> |
| 15024 | +#endif |
| 15025 | +#if defined( CONFIG_MIPS_PB1200 ) |
| 15026 | + #include <asm/pb1200.h> |
| 15027 | +#endif |
| 15028 | +#if defined( CONFIG_MIPS_DB1200 ) |
| 15029 | + #include <asm/db1200.h> |
| 15030 | +#endif |
| 15031 | +#if defined( CONFIG_MIPS_FICMMP ) |
| 15032 | + #include <asm/ficmmp.h> |
| 15033 | +#endif |
| 15034 | + |
| 15035 | +#include <linux/i2c.h> |
| 15036 | +#include <linux/i2c-algo-au1550.h> |
| 15037 | + |
| 15038 | + |
| 15039 | + |
| 15040 | +static int |
| 15041 | +pb1550_reg(struct i2c_client *client) |
| 15042 | +{ |
| 15043 | + return 0; |
| 15044 | +} |
| 15045 | + |
| 15046 | +static int |
| 15047 | +pb1550_unreg(struct i2c_client *client) |
| 15048 | +{ |
| 15049 | + return 0; |
| 15050 | +} |
| 15051 | + |
| 15052 | +static void |
| 15053 | +pb1550_inc_use(struct i2c_adapter *adap) |
| 15054 | +{ |
| 15055 | +#ifdef MODULE |
| 15056 | + MOD_INC_USE_COUNT; |
| 15057 | +#endif |
| 15058 | +} |
| 15059 | + |
| 15060 | +static void |
| 15061 | +pb1550_dec_use(struct i2c_adapter *adap) |
| 15062 | +{ |
| 15063 | +#ifdef MODULE |
| 15064 | + MOD_DEC_USE_COUNT; |
| 15065 | +#endif |
| 15066 | +} |
| 15067 | + |
| 15068 | +static struct i2c_algo_au1550_data pb1550_i2c_info = { |
| 15069 | + SMBUS_PSC_BASE, 200, 200 |
| 15070 | +}; |
| 15071 | + |
| 15072 | +static struct i2c_adapter pb1550_board_adapter = { |
| 15073 | + name: "pb1550 adapter", |
| 15074 | + id: I2C_HW_AU1550_PSC, |
| 15075 | + algo: NULL, |
| 15076 | + algo_data: &pb1550_i2c_info, |
| 15077 | + inc_use: pb1550_inc_use, |
| 15078 | + dec_use: pb1550_dec_use, |
| 15079 | + client_register: pb1550_reg, |
| 15080 | + client_unregister: pb1550_unreg, |
| 15081 | + client_count: 0, |
| 15082 | +}; |
| 15083 | + |
| 15084 | +int __init |
| 15085 | +i2c_pb1550_init(void) |
| 15086 | +{ |
| 15087 | + /* This is where we would set up a 50MHz clock source |
| 15088 | + * and routing. On the Pb1550, the SMBus is PSC2, which |
| 15089 | + * uses a shared clock with USB. This has been already |
| 15090 | + * configured by Yamon as a 48MHz clock, close enough |
| 15091 | + * for our work. |
| 15092 | + */ |
| 15093 | + if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) |
| 15094 | + return -ENODEV; |
| 15095 | + |
| 15096 | + return 0; |
| 15097 | +} |
| 15098 | + |
| 15099 | +/* BIG hack to support the control interface on the Wolfson WM8731 |
| 15100 | + * audio codec on the Pb1550 board. We get an address and two data |
| 15101 | + * bytes to write, create an i2c message, and send it across the |
| 15102 | + * i2c transfer function. We do this here because we have access to |
| 15103 | + * the i2c adapter structure. |
| 15104 | + */ |
| 15105 | +static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */ |
| 15106 | +static u8 i2cbuf[2]; |
| 15107 | + |
| 15108 | +int |
| 15109 | +pb1550_wm_codec_write(u8 addr, u8 reg, u8 val) |
| 15110 | +{ |
| 15111 | + wm_i2c_msg.addr = addr; |
| 15112 | + wm_i2c_msg.flags = 0; |
| 15113 | + wm_i2c_msg.buf = i2cbuf; |
| 15114 | + wm_i2c_msg.len = 2; |
| 15115 | + i2cbuf[0] = reg; |
| 15116 | + i2cbuf[1] = val; |
| 15117 | + |
| 15118 | + return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1); |
| 15119 | +} |
| 15120 | + |
| 15121 | +/* the next function is needed by DVB driver. */ |
| 15122 | +int pb1550_i2c_xfer(struct i2c_msg msgs[], int num) |
| 15123 | +{ |
| 15124 | + return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, msgs, num); |
| 15125 | +} |
| 15126 | + |
| 15127 | +EXPORT_SYMBOL(pb1550_wm_codec_write); |
| 15128 | +EXPORT_SYMBOL(pb1550_i2c_xfer); |
| 15129 | + |
| 15130 | +MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); |
| 15131 | +MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); |
| 15132 | +MODULE_LICENSE("GPL"); |
| 15133 | + |
| 15134 | +int |
| 15135 | +init_module(void) |
| 15136 | +{ |
| 15137 | + return i2c_pb1550_init(); |
| 15138 | +} |
| 15139 | + |
| 15140 | +void |
| 15141 | +cleanup_module(void) |
| 15142 | +{ |
| 15143 | + i2c_au1550_del_bus(&pb1550_board_adapter); |
| 15144 | +} |
| 15145 | --- a/drivers/i2c/i2c-core.c |
| 15146 | +++ b/drivers/i2c/i2c-core.c |
| 15147 | @@ -1277,6 +1277,9 @@ static int __init i2c_init(void) |
| 15148 | #ifdef CONFIG_I2C_MAX1617 |
| 15149 | extern int i2c_max1617_init(void); |
| 15150 | #endif |
| 15151 | +#ifdef CONFIG_I2C_ALGO_AU1550 |
| 15152 | + extern int i2c_pb1550_init(void); |
| 15153 | +#endif |
| 15154 | |
| 15155 | #ifdef CONFIG_I2C_PROC |
| 15156 | extern int sensors_init(void); |
| 15157 | @@ -1332,6 +1335,10 @@ int __init i2c_init_all(void) |
| 15158 | i2c_max1617_init(); |
| 15159 | #endif |
| 15160 | |
| 15161 | +#ifdef CONFIG_I2C_ALGO_AU1550 |
| 15162 | + i2c_pb1550_init(); |
| 15163 | +#endif |
| 15164 | + |
| 15165 | /* -------------- proc interface ---- */ |
| 15166 | #ifdef CONFIG_I2C_PROC |
| 15167 | sensors_init(); |
| 15168 | --- a/drivers/i2c/Makefile |
| 15169 | +++ b/drivers/i2c/Makefile |
| 15170 | @@ -6,7 +6,7 @@ O_TARGET := i2c.o |
| 15171 | |
| 15172 | export-objs := i2c-core.o i2c-algo-bit.o i2c-algo-pcf.o \ |
| 15173 | i2c-algo-ite.o i2c-algo-sibyte.o i2c-algo-sgi.o \ |
| 15174 | - i2c-proc.o |
| 15175 | + i2c-algo-au1550.o i2c-proc.o i2c-au1550.o |
| 15176 | |
| 15177 | obj-$(CONFIG_I2C) += i2c-core.o |
| 15178 | obj-$(CONFIG_I2C_CHARDEV) += i2c-dev.o |
| 15179 | @@ -25,6 +25,7 @@ obj-$(CONFIG_I2C_KEYWEST) += i2c-keywest |
| 15180 | obj-$(CONFIG_I2C_ALGO_SIBYTE) += i2c-algo-sibyte.o i2c-sibyte.o |
| 15181 | obj-$(CONFIG_I2C_MAX1617) += i2c-max1617.o |
| 15182 | obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o |
| 15183 | +obj-$(CONFIG_I2C_ALGO_AU1550) += i2c-algo-au1550.o i2c-au1550.o |
| 15184 | |
| 15185 | # This is needed for automatic patch generation: sensors code starts here |
| 15186 | # This is needed for automatic patch generation: sensors code ends here |
| 15187 | --- a/drivers/media/video/indycam.c |
| 15188 | +++ b/drivers/media/video/indycam.c |
| 15189 | @@ -50,13 +50,14 @@ static int indycam_attach(struct i2c_ada |
| 15190 | 0x80, /* INDYCAM_GAMMA */ |
| 15191 | }; |
| 15192 | |
| 15193 | - int err = 0; |
| 15194 | struct indycam *camera; |
| 15195 | struct i2c_client *client; |
| 15196 | + int err = 0; |
| 15197 | |
| 15198 | client = kmalloc(sizeof(*client), GFP_KERNEL); |
| 15199 | - if (!client) |
| 15200 | + if (!client) |
| 15201 | return -ENOMEM; |
| 15202 | + |
| 15203 | camera = kmalloc(sizeof(*camera), GFP_KERNEL); |
| 15204 | if (!camera) { |
| 15205 | err = -ENOMEM; |
| 15206 | @@ -67,7 +68,7 @@ static int indycam_attach(struct i2c_ada |
| 15207 | client->adapter = adap; |
| 15208 | client->addr = addr; |
| 15209 | client->driver = &i2c_driver_indycam; |
| 15210 | - strcpy(client->name, "IndyCam client"); |
| 15211 | + strcpy(client->name, "IndyCam client"); |
| 15212 | camera->client = client; |
| 15213 | |
| 15214 | err = i2c_attach_client(client); |
| 15215 | @@ -75,18 +76,18 @@ static int indycam_attach(struct i2c_ada |
| 15216 | goto out_free_camera; |
| 15217 | |
| 15218 | camera->version = i2c_smbus_read_byte_data(client, INDYCAM_VERSION); |
| 15219 | - if (camera->version != CAMERA_VERSION_INDY && |
| 15220 | - camera->version != CAMERA_VERSION_MOOSE) { |
| 15221 | + if ((camera->version != CAMERA_VERSION_INDY) && |
| 15222 | + (camera->version != CAMERA_VERSION_MOOSE)) { |
| 15223 | err = -ENODEV; |
| 15224 | goto out_detach_client; |
| 15225 | } |
| 15226 | - printk(KERN_INFO "Indycam v%d.%d detected.\n", |
| 15227 | + printk(KERN_INFO "IndyCam v%d.%d detected.\n", |
| 15228 | INDYCAM_VERSION_MAJOR(camera->version), |
| 15229 | INDYCAM_VERSION_MINOR(camera->version)); |
| 15230 | |
| 15231 | err = i2c_master_send(client, initseq, sizeof(initseq)); |
| 15232 | if (err) |
| 15233 | - printk(KERN_INFO "IndyCam initalization failed\n"); |
| 15234 | + printk(KERN_ERR "IndyCam initalization failed.\n"); |
| 15235 | |
| 15236 | MOD_INC_USE_COUNT; |
| 15237 | return 0; |
| 15238 | --- a/drivers/media/video/vino.c |
| 15239 | +++ b/drivers/media/video/vino.c |
| 15240 | @@ -5,6 +5,8 @@ |
| 15241 | * License version 2 as published by the Free Software Foundation. |
| 15242 | * |
| 15243 | * Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org> |
| 15244 | + * Copyright (C) 2004 Mikael Nousiainen <tmnousia@cc.hut.fi> |
| 15245 | + * |
| 15246 | */ |
| 15247 | |
| 15248 | #include <linux/module.h> |
| 15249 | @@ -37,13 +39,23 @@ |
| 15250 | #define DEBUG(x...) |
| 15251 | #endif |
| 15252 | |
| 15253 | +/* Channels (who could have guessed) */ |
| 15254 | +#define VINO_CHAN_NONE 0 |
| 15255 | +#define VINO_CHAN_A 1 |
| 15256 | +#define VINO_CHAN_B 2 |
| 15257 | + |
| 15258 | /* VINO video size */ |
| 15259 | #define VINO_PAL_WIDTH 768 |
| 15260 | #define VINO_PAL_HEIGHT 576 |
| 15261 | #define VINO_NTSC_WIDTH 646 |
| 15262 | #define VINO_NTSC_HEIGHT 486 |
| 15263 | |
| 15264 | -/* set this to some sensible values. note: VINO_MIN_WIDTH has to be 8*x */ |
| 15265 | +/* Minimum value for Y-clipping (for smaller values the images |
| 15266 | + * will be corrupted) */ |
| 15267 | +#define VINO_MIN_Y_CLIPPING 2 |
| 15268 | + |
| 15269 | +/* Set these to some sensible values. |
| 15270 | + * Note: the picture width has to be divisible by 8 */ |
| 15271 | #define VINO_MIN_WIDTH 32 |
| 15272 | #define VINO_MIN_HEIGHT 32 |
| 15273 | |
| 15274 | @@ -64,9 +76,7 @@ static int threshold_b = 512; |
| 15275 | |
| 15276 | struct vino_device { |
| 15277 | struct video_device vdev; |
| 15278 | -#define VINO_CHAN_A 1 |
| 15279 | -#define VINO_CHAN_B 2 |
| 15280 | - int chan; |
| 15281 | + int chan; /* VINO_CHAN_NONE, VINO_CHAN_A or VINO_CHAN_B */ |
| 15282 | int alpha; |
| 15283 | /* clipping... */ |
| 15284 | unsigned int left, right, top, bottom; |
| 15285 | @@ -106,7 +116,7 @@ struct vino_device { |
| 15286 | |
| 15287 | struct vino_client { |
| 15288 | struct i2c_client *driver; |
| 15289 | - int owner; |
| 15290 | + int owner; /* VINO_CHAN_NONE, VINO_CHAN_A or VINO_CHAN_B */ |
| 15291 | }; |
| 15292 | |
| 15293 | struct vino_video { |
| 15294 | @@ -362,6 +372,7 @@ static int set_scaling(struct vino_devic |
| 15295 | static int dma_setup(struct vino_device *v) |
| 15296 | { |
| 15297 | u32 ctrl, intr; |
| 15298 | + int ofs; |
| 15299 | struct sgi_vino_channel *ch; |
| 15300 | |
| 15301 | ch = (v->chan == VINO_CHAN_A) ? &vino->a : &vino->b; |
| 15302 | @@ -377,14 +388,24 @@ static int dma_setup(struct vino_device |
| 15303 | ch->line_size = v->line_size - 8; |
| 15304 | /* set the alpha register */ |
| 15305 | ch->alpha = v->alpha; |
| 15306 | - /* set cliping registers */ |
| 15307 | - ch->clip_start = VINO_CLIP_ODD(v->top) | VINO_CLIP_EVEN(v->top+1) | |
| 15308 | + /* Set the clipping registers, this is the constant source of fun :) |
| 15309 | + * Y clipping start has to be >= 2 and end has to be start + height/2 |
| 15310 | + * The values of top and bottom are even so dividing is not a problem |
| 15311 | + * |
| 15312 | + * The docs say that clipping values for the even field should be |
| 15313 | + * odd_end + something_to_skip_vertical_blanking + some_lines and |
| 15314 | + * even_start + height/2, though the image is good this way also |
| 15315 | + * |
| 15316 | + * TODO: for analog sources (SAA7191), the clipping values are a bit |
| 15317 | + * different and that case isn't yet handled |
| 15318 | + */ |
| 15319 | + ofs = VINO_MIN_Y_CLIPPING; /* Should depend on input source */ |
| 15320 | + ch->clip_start = VINO_CLIP_ODD(ofs + v->top / 2) | |
| 15321 | + VINO_CLIP_EVEN(ofs + v->top / 2 + 1) | |
| 15322 | VINO_CLIP_X(v->left); |
| 15323 | - ch->clip_end = VINO_CLIP_ODD(v->bottom) | VINO_CLIP_EVEN(v->bottom+1) | |
| 15324 | + ch->clip_end = VINO_CLIP_ODD(ofs + v->bottom / 2 - 1) | |
| 15325 | + VINO_CLIP_EVEN(ofs + v->bottom / 2) | |
| 15326 | VINO_CLIP_X(v->right); |
| 15327 | - /* FIXME: end-of-field bug workaround |
| 15328 | - VINO_CLIP_X(VINO_PAL_WIDTH); |
| 15329 | - */ |
| 15330 | /* init the frame rate and norm (full frame rate only for now...) */ |
| 15331 | ch->frame_rate = VINO_FRAMERT_RT(0x1fff) | |
| 15332 | (get_capture_norm(v) == VIDEO_MODE_PAL ? |
| 15333 | @@ -510,6 +531,7 @@ static void field_done(struct vino_devic |
| 15334 | static void vino_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 15335 | { |
| 15336 | u32 intr, ctrl; |
| 15337 | + int a_eof, b_eof; |
| 15338 | |
| 15339 | spin_lock(&Vino->vino_lock); |
| 15340 | ctrl = vino->control; |
| 15341 | @@ -525,12 +547,14 @@ static void vino_interrupt(int irq, void |
| 15342 | vino->control = ctrl; |
| 15343 | clear_eod(&Vino->chB); |
| 15344 | } |
| 15345 | + a_eof = intr & VINO_INTSTAT_A_EOF; |
| 15346 | + b_eof = intr & VINO_INTSTAT_B_EOF; |
| 15347 | vino->intr_status = ~intr; |
| 15348 | spin_unlock(&Vino->vino_lock); |
| 15349 | - /* FIXME: For now we are assuming that interrupt means that frame is |
| 15350 | - * done. That's not true, but we can live with such brokeness for |
| 15351 | - * a while ;-) */ |
| 15352 | - field_done(&Vino->chA); |
| 15353 | + if (a_eof) |
| 15354 | + field_done(&Vino->chA); |
| 15355 | + if (b_eof) |
| 15356 | + field_done(&Vino->chB); |
| 15357 | } |
| 15358 | |
| 15359 | static int vino_grab(struct vino_device *v, int frame) |
| 15360 | --- a/drivers/mtd/devices/docprobe.c |
| 15361 | +++ b/drivers/mtd/devices/docprobe.c |
| 15362 | @@ -89,10 +89,10 @@ static unsigned long __initdata doc_loca |
| 15363 | 0xe4000000, |
| 15364 | #elif defined(CONFIG_MOMENCO_OCELOT) |
| 15365 | 0x2f000000, |
| 15366 | - 0xff000000, |
| 15367 | + 0xff000000, |
| 15368 | #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) |
| 15369 | - 0xff000000, |
| 15370 | -##else |
| 15371 | + 0xff000000, |
| 15372 | +#else |
| 15373 | #warning Unknown architecture for DiskOnChip. No default probe locations defined |
| 15374 | #endif |
| 15375 | 0 }; |
| 15376 | --- a/drivers/mtd/devices/ms02-nv.c |
| 15377 | +++ b/drivers/mtd/devices/ms02-nv.c |
| 15378 | @@ -1,10 +1,10 @@ |
| 15379 | /* |
| 15380 | - * Copyright (c) 2001 Maciej W. Rozycki |
| 15381 | + * Copyright (c) 2001 Maciej W. Rozycki |
| 15382 | * |
| 15383 | - * This program is free software; you can redistribute it and/or |
| 15384 | - * modify it under the terms of the GNU General Public License |
| 15385 | - * as published by the Free Software Foundation; either version |
| 15386 | - * 2 of the License, or (at your option) any later version. |
| 15387 | + * This program is free software; you can redistribute it and/or |
| 15388 | + * modify it under the terms of the GNU General Public License |
| 15389 | + * as published by the Free Software Foundation; either version |
| 15390 | + * 2 of the License, or (at your option) any later version. |
| 15391 | * |
| 15392 | * $Id: ms02-nv.c,v 1.2 2003/01/24 14:05:17 dwmw2 Exp $ |
| 15393 | */ |
| 15394 | @@ -29,18 +29,18 @@ |
| 15395 | |
| 15396 | |
| 15397 | static char version[] __initdata = |
| 15398 | - "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n"; |
| 15399 | + "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n"; |
| 15400 | |
| 15401 | -MODULE_AUTHOR("Maciej W. Rozycki <macro@ds2.pg.gda.pl>"); |
| 15402 | +MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); |
| 15403 | MODULE_DESCRIPTION("DEC MS02-NV NVRAM module driver"); |
| 15404 | MODULE_LICENSE("GPL"); |
| 15405 | |
| 15406 | |
| 15407 | /* |
| 15408 | * Addresses we probe for an MS02-NV at. Modules may be located |
| 15409 | - * at any 8MB boundary within a 0MB up to 112MB range or at any 32MB |
| 15410 | - * boundary within a 0MB up to 448MB range. We don't support a module |
| 15411 | - * at 0MB, though. |
| 15412 | + * at any 8MiB boundary within a 0MiB up to 112MiB range or at any 32MiB |
| 15413 | + * boundary within a 0MiB up to 448MiB range. We don't support a module |
| 15414 | + * at 0MiB, though. |
| 15415 | */ |
| 15416 | static ulong ms02nv_addrs[] __initdata = { |
| 15417 | 0x07000000, 0x06800000, 0x06000000, 0x05800000, 0x05000000, |
| 15418 | @@ -130,7 +130,7 @@ static int __init ms02nv_init_one(ulong |
| 15419 | |
| 15420 | int ret = -ENODEV; |
| 15421 | |
| 15422 | - /* The module decodes 8MB of address space. */ |
| 15423 | + /* The module decodes 8MiB of address space. */ |
| 15424 | mod_res = kmalloc(sizeof(*mod_res), GFP_KERNEL); |
| 15425 | if (!mod_res) |
| 15426 | return -ENOMEM; |
| 15427 | @@ -233,7 +233,7 @@ static int __init ms02nv_init_one(ulong |
| 15428 | goto err_out_csr_res; |
| 15429 | } |
| 15430 | |
| 15431 | - printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %uMB.\n", |
| 15432 | + printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %uMiB.\n", |
| 15433 | mtd->index, ms02nv_name, addr, size >> 20); |
| 15434 | |
| 15435 | mp->next = root_ms02nv_mtd; |
| 15436 | @@ -293,12 +293,12 @@ static int __init ms02nv_init(void) |
| 15437 | |
| 15438 | switch (mips_machtype) { |
| 15439 | case MACH_DS5000_200: |
| 15440 | - csr = (volatile u32 *)KN02_CSR_ADDR; |
| 15441 | + csr = (volatile u32 *)KN02_CSR_BASE; |
| 15442 | if (*csr & KN02_CSR_BNK32M) |
| 15443 | stride = 2; |
| 15444 | break; |
| 15445 | case MACH_DS5000_2X0: |
| 15446 | - case MACH_DS5000: |
| 15447 | + case MACH_DS5900: |
| 15448 | csr = (volatile u32 *)KN03_MCR_BASE; |
| 15449 | if (*csr & KN03_MCR_BNK32M) |
| 15450 | stride = 2; |
| 15451 | --- a/drivers/mtd/devices/ms02-nv.h |
| 15452 | +++ b/drivers/mtd/devices/ms02-nv.h |
| 15453 | @@ -1,32 +1,96 @@ |
| 15454 | /* |
| 15455 | - * Copyright (c) 2001 Maciej W. Rozycki |
| 15456 | + * Copyright (c) 2001, 2003 Maciej W. Rozycki |
| 15457 | * |
| 15458 | - * This program is free software; you can redistribute it and/or |
| 15459 | - * modify it under the terms of the GNU General Public License |
| 15460 | - * as published by the Free Software Foundation; either version |
| 15461 | - * 2 of the License, or (at your option) any later version. |
| 15462 | + * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for |
| 15463 | + * DECstation/DECsystem 5000/2x0 and DECsystem 5900 and 5900/260 |
| 15464 | + * systems. |
| 15465 | + * |
| 15466 | + * This program is free software; you can redistribute it and/or |
| 15467 | + * modify it under the terms of the GNU General Public License |
| 15468 | + * as published by the Free Software Foundation; either version |
| 15469 | + * 2 of the License, or (at your option) any later version. |
| 15470 | + * |
| 15471 | + * $Id: ms02-nv.h,v 1.3 2003/08/19 09:25:36 dwmw2 Exp $ |
| 15472 | */ |
| 15473 | |
| 15474 | #include <linux/ioport.h> |
| 15475 | #include <linux/mtd/mtd.h> |
| 15476 | |
| 15477 | +/* |
| 15478 | + * Addresses are decoded as follows: |
| 15479 | + * |
| 15480 | + * 0x000000 - 0x3fffff SRAM |
| 15481 | + * 0x400000 - 0x7fffff CSR |
| 15482 | + * |
| 15483 | + * Within the SRAM area the following ranges are forced by the system |
| 15484 | + * firmware: |
| 15485 | + * |
| 15486 | + * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot |
| 15487 | + * 0x000400 - ENDofRAM storage area, available to operating systems |
| 15488 | + * |
| 15489 | + * but we can't really use the available area right from 0x000400 as |
| 15490 | + * the first word is used by the firmware as a status flag passed |
| 15491 | + * from an operating system. If anything but the valid data magic |
| 15492 | + * ID value is found, the firmware considers the SRAM clean, i.e. |
| 15493 | + * containing no valid data, and disables the battery resulting in |
| 15494 | + * data being erased as soon as power is switched off. So the choice |
| 15495 | + * for the start address of the user-available is 0x001000 which is |
| 15496 | + * nicely page aligned. The area between 0x000404 and 0x000fff may |
| 15497 | + * be used by the driver for own needs. |
| 15498 | + * |
| 15499 | + * The diagnostic area defines two status words to be read by an |
| 15500 | + * operating system, a magic ID to distinguish a MS02-NV board from |
| 15501 | + * anything else and a status information providing results of tests |
| 15502 | + * as well as the size of SRAM available, which can be 1MiB or 2MiB |
| 15503 | + * (that's what the firmware handles; no idea if 2MiB modules ever |
| 15504 | + * existed). |
| 15505 | + * |
| 15506 | + * The firmware only handles the MS02-NV board if installed in the |
| 15507 | + * last (15th) slot, so for any other location the status information |
| 15508 | + * stored in the SRAM cannot be relied upon. But from the hardware |
| 15509 | + * point of view there is no problem using up to 14 such boards in a |
| 15510 | + * system -- only the 1st slot needs to be filled with a DRAM module. |
| 15511 | + * The MS02-NV board is ECC-protected, like other MS02 memory boards. |
| 15512 | + * |
| 15513 | + * The state of the battery as provided by the CSR is reflected on |
| 15514 | + * the two onboard LEDs. When facing the battery side of the board, |
| 15515 | + * with the LEDs at the top left and the battery at the bottom right |
| 15516 | + * (i.e. looking from the back side of the system box), their meaning |
| 15517 | + * is as follows (the system has to be powered on): |
| 15518 | + * |
| 15519 | + * left LED battery disable status: lit = enabled |
| 15520 | + * right LED battery condition status: lit = OK |
| 15521 | + */ |
| 15522 | + |
| 15523 | /* MS02-NV iomem register offsets. */ |
| 15524 | #define MS02NV_CSR 0x400000 /* control & status register */ |
| 15525 | |
| 15526 | +/* MS02-NV CSR status bits. */ |
| 15527 | +#define MS02NV_CSR_BATT_OK 0x01 /* battery OK */ |
| 15528 | +#define MS02NV_CSR_BATT_OFF 0x02 /* battery disabled */ |
| 15529 | + |
| 15530 | + |
| 15531 | /* MS02-NV memory offsets. */ |
| 15532 | #define MS02NV_DIAG 0x0003f8 /* diagnostic status */ |
| 15533 | #define MS02NV_MAGIC 0x0003fc /* MS02-NV magic ID */ |
| 15534 | -#define MS02NV_RAM 0x000400 /* general-purpose RAM start */ |
| 15535 | +#define MS02NV_VALID 0x000400 /* valid data magic ID */ |
| 15536 | +#define MS02NV_RAM 0x001000 /* user-exposed RAM start */ |
| 15537 | |
| 15538 | -/* MS02-NV diagnostic status constants. */ |
| 15539 | -#define MS02NV_DIAG_SIZE_MASK 0xf0 /* RAM size mask */ |
| 15540 | -#define MS02NV_DIAG_SIZE_SHIFT 0x10 /* RAM size shift (left) */ |
| 15541 | +/* MS02-NV diagnostic status bits. */ |
| 15542 | +#define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */ |
| 15543 | +#define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */ |
| 15544 | +#define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */ |
| 15545 | +#define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */ |
| 15546 | +#define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */ |
| 15547 | +#define MS02NV_DIAG_SIZE_SHIFT 0x10 /* SRAM size shift (left) */ |
| 15548 | |
| 15549 | /* MS02-NV general constants. */ |
| 15550 | #define MS02NV_ID 0x03021966 /* MS02-NV magic ID value */ |
| 15551 | +#define MS02NV_VALID_ID 0xbd100248 /* valid data magic ID value */ |
| 15552 | #define MS02NV_SLOT_SIZE 0x800000 /* size of the address space |
| 15553 | decoded by the module */ |
| 15554 | |
| 15555 | + |
| 15556 | typedef volatile u32 ms02nv_uint; |
| 15557 | |
| 15558 | struct ms02nv_private { |
| 15559 | --- a/drivers/mtd/maps/Config.in |
| 15560 | +++ b/drivers/mtd/maps/Config.in |
| 15561 | @@ -51,11 +51,26 @@ if [ "$CONFIG_MIPS" = "y" ]; then |
| 15562 | dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000 |
| 15563 | dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500 |
| 15564 | dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100 |
| 15565 | + dep_tristate ' Bosporus MTD support' CONFIG_MTD_BOSPORUS $CONFIG_MIPS_BOSPORUS |
| 15566 | + dep_tristate ' XXS1500 boot flash device' CONFIG_MTD_XXS1500 $CONFIG_MIPS_XXS1500 |
| 15567 | + dep_tristate ' MTX-1 flash device' CONFIG_MTD_MTX1 $CONFIG_MIPS_MTX1 |
| 15568 | if [ "$CONFIG_MTD_PB1500" = "y" -o "$CONFIG_MTD_PB1500" = "m" \ |
| 15569 | -o "$CONFIG_MTD_PB1100" = "y" -o "$CONFIG_MTD_PB1100" = "m" ]; then |
| 15570 | bool ' Pb[15]00 boot flash device' CONFIG_MTD_PB1500_BOOT |
| 15571 | bool ' Pb[15]00 user flash device (2nd 32MiB bank)' CONFIG_MTD_PB1500_USER |
| 15572 | fi |
| 15573 | + tristate ' Db1x00 MTD support' CONFIG_MTD_DB1X00 |
| 15574 | + if [ "$CONFIG_MTD_DB1X00" = "y" -o "$CONFIG_MTD_DB1X00" = "m" ]; then |
| 15575 | + bool ' Db1x00 boot flash device' CONFIG_MTD_DB1X00_BOOT |
| 15576 | + bool ' Db1x00 user flash device (2nd bank)' CONFIG_MTD_DB1X00_USER |
| 15577 | + fi |
| 15578 | + tristate ' Pb1550 MTD support' CONFIG_MTD_PB1550 |
| 15579 | + if [ "$CONFIG_MTD_PB1550" = "y" -o "$CONFIG_MTD_PB1550" = "m" ]; then |
| 15580 | + bool ' Pb1550 Boot Flash' CONFIG_MTD_PB1550_BOOT |
| 15581 | + bool ' Pb1550 User Parameter Flash' CONFIG_MTD_PB1550_USER |
| 15582 | + fi |
| 15583 | + dep_tristate ' Hydrogen 3 MTD support' CONFIG_MTD_HYDROGEN3 $CONFIG_MIPS_HYDROGEN3 |
| 15584 | + dep_tristate ' Mirage MTD support' CONFIG_MTD_MIRAGE $CONFIG_MIPS_MIRAGE |
| 15585 | dep_tristate ' Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board' CONFIG_MTD_CSTM_MIPS_IXX $CONFIG_MTD_CFI $CONFIG_MTD_JEDEC $CONFIG_MTD_PARTITIONS |
| 15586 | if [ "$CONFIG_MTD_CSTM_MIPS_IXX" = "y" -o "$CONFIG_MTD_CSTM_MIPS_IXX" = "m" ]; then |
| 15587 | hex ' Physical start address of flash mapping' CONFIG_MTD_CSTM_MIPS_IXX_START 0x8000000 |
| 15588 | --- /dev/null |
| 15589 | +++ b/drivers/mtd/maps/db1x00-flash.c |
| 15590 | @@ -0,0 +1,283 @@ |
| 15591 | +/* |
| 15592 | + * Flash memory access on Alchemy Db1xxx boards |
| 15593 | + * |
| 15594 | + * (C) 2003 Pete Popov <ppopov@pacbell.net> |
| 15595 | + * |
| 15596 | + */ |
| 15597 | + |
| 15598 | +#include <linux/config.h> |
| 15599 | +#include <linux/module.h> |
| 15600 | +#include <linux/types.h> |
| 15601 | +#include <linux/kernel.h> |
| 15602 | + |
| 15603 | +#include <linux/mtd/mtd.h> |
| 15604 | +#include <linux/mtd/map.h> |
| 15605 | +#include <linux/mtd/partitions.h> |
| 15606 | + |
| 15607 | +#include <asm/io.h> |
| 15608 | +#include <asm/au1000.h> |
| 15609 | +#include <asm/db1x00.h> |
| 15610 | + |
| 15611 | +#ifdef DEBUG_RW |
| 15612 | +#define DBG(x...) printk(x) |
| 15613 | +#else |
| 15614 | +#define DBG(x...) |
| 15615 | +#endif |
| 15616 | + |
| 15617 | +static unsigned long window_addr; |
| 15618 | +static unsigned long window_size; |
| 15619 | +static unsigned long flash_size; |
| 15620 | + |
| 15621 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 15622 | +{ |
| 15623 | + __u8 ret; |
| 15624 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 15625 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15626 | + return ret; |
| 15627 | +} |
| 15628 | + |
| 15629 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 15630 | +{ |
| 15631 | + __u16 ret; |
| 15632 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 15633 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15634 | + return ret; |
| 15635 | +} |
| 15636 | + |
| 15637 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 15638 | +{ |
| 15639 | + __u32 ret; |
| 15640 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 15641 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15642 | + return ret; |
| 15643 | +} |
| 15644 | + |
| 15645 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 15646 | +{ |
| 15647 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 15648 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 15649 | +} |
| 15650 | + |
| 15651 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 15652 | +{ |
| 15653 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15654 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 15655 | + mb(); |
| 15656 | +} |
| 15657 | + |
| 15658 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 15659 | +{ |
| 15660 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15661 | + __raw_writew(d, map->map_priv_1 + adr); |
| 15662 | + mb(); |
| 15663 | +} |
| 15664 | + |
| 15665 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 15666 | +{ |
| 15667 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15668 | + __raw_writel(d, map->map_priv_1 + adr); |
| 15669 | + mb(); |
| 15670 | +} |
| 15671 | + |
| 15672 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 15673 | +{ |
| 15674 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 15675 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 15676 | +} |
| 15677 | + |
| 15678 | +static struct map_info db1x00_map = { |
| 15679 | + name: "Db1x00 flash", |
| 15680 | + read8: physmap_read8, |
| 15681 | + read16: physmap_read16, |
| 15682 | + read32: physmap_read32, |
| 15683 | + copy_from: physmap_copy_from, |
| 15684 | + write8: physmap_write8, |
| 15685 | + write16: physmap_write16, |
| 15686 | + write32: physmap_write32, |
| 15687 | + copy_to: physmap_copy_to, |
| 15688 | +}; |
| 15689 | + |
| 15690 | +static unsigned char flash_buswidth = 4; |
| 15691 | + |
| 15692 | +/* |
| 15693 | + * The Db1x boards support different flash densities. We setup |
| 15694 | + * the mtd_partition structures below for default of 64Mbit |
| 15695 | + * flash densities, and override the partitions sizes, if |
| 15696 | + * necessary, after we check the board status register. |
| 15697 | + */ |
| 15698 | + |
| 15699 | +#ifdef DB1X00_BOTH_BANKS |
| 15700 | +/* both banks will be used. Combine the first bank and the first |
| 15701 | + * part of the second bank together into a single jffs/jffs2 |
| 15702 | + * partition. |
| 15703 | + */ |
| 15704 | +static struct mtd_partition db1x00_partitions[] = { |
| 15705 | + { |
| 15706 | + name: "User FS", |
| 15707 | + size: 0x1c00000, |
| 15708 | + offset: 0x0000000 |
| 15709 | + },{ |
| 15710 | + name: "yamon", |
| 15711 | + size: 0x0100000, |
| 15712 | + offset: MTDPART_OFS_APPEND, |
| 15713 | + mask_flags: MTD_WRITEABLE |
| 15714 | + },{ |
| 15715 | + name: "raw kernel", |
| 15716 | + size: (0x300000-0x40000), /* last 256KB is yamon env */ |
| 15717 | + offset: MTDPART_OFS_APPEND, |
| 15718 | + } |
| 15719 | +}; |
| 15720 | +#elif defined(DB1X00_BOOT_ONLY) |
| 15721 | +static struct mtd_partition db1x00_partitions[] = { |
| 15722 | + { |
| 15723 | + name: "User FS", |
| 15724 | + size: 0x00c00000, |
| 15725 | + offset: 0x0000000 |
| 15726 | + },{ |
| 15727 | + name: "yamon", |
| 15728 | + size: 0x0100000, |
| 15729 | + offset: MTDPART_OFS_APPEND, |
| 15730 | + mask_flags: MTD_WRITEABLE |
| 15731 | + },{ |
| 15732 | + name: "raw kernel", |
| 15733 | + size: (0x300000-0x40000), /* last 256KB is yamon env */ |
| 15734 | + offset: MTDPART_OFS_APPEND, |
| 15735 | + } |
| 15736 | +}; |
| 15737 | +#elif defined(DB1X00_USER_ONLY) |
| 15738 | +static struct mtd_partition db1x00_partitions[] = { |
| 15739 | + { |
| 15740 | + name: "User FS", |
| 15741 | + size: 0x0e00000, |
| 15742 | + offset: 0x0000000 |
| 15743 | + },{ |
| 15744 | + name: "raw kernel", |
| 15745 | + size: MTDPART_SIZ_FULL, |
| 15746 | + offset: MTDPART_OFS_APPEND, |
| 15747 | + } |
| 15748 | +}; |
| 15749 | +#else |
| 15750 | +#error MTD_DB1X00 define combo error /* should never happen */ |
| 15751 | +#endif |
| 15752 | + |
| 15753 | + |
| 15754 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 15755 | + |
| 15756 | +static struct mtd_partition *parsed_parts; |
| 15757 | +static struct mtd_info *mymtd; |
| 15758 | + |
| 15759 | +/* |
| 15760 | + * Probe the flash density and setup window address and size |
| 15761 | + * based on user CONFIG options. There are times when we don't |
| 15762 | + * want the MTD driver to be probing the boot or user flash, |
| 15763 | + * so having the option to enable only one bank is important. |
| 15764 | + */ |
| 15765 | +int setup_flash_params() |
| 15766 | +{ |
| 15767 | + switch ((bcsr->status >> 14) & 0x3) { |
| 15768 | + case 0: /* 64Mbit devices */ |
| 15769 | + flash_size = 0x800000; /* 8MB per part */ |
| 15770 | +#if defined(DB1X00_BOTH_BANKS) |
| 15771 | + window_addr = 0x1E000000; |
| 15772 | + window_size = 0x2000000; |
| 15773 | +#elif defined(DB1X00_BOOT_ONLY) |
| 15774 | + window_addr = 0x1F000000; |
| 15775 | + window_size = 0x1000000; |
| 15776 | +#else /* USER ONLY */ |
| 15777 | + window_addr = 0x1E000000; |
| 15778 | + window_size = 0x1000000; |
| 15779 | +#endif |
| 15780 | + break; |
| 15781 | + case 1: |
| 15782 | + /* 128 Mbit devices */ |
| 15783 | + flash_size = 0x1000000; /* 16MB per part */ |
| 15784 | +#if defined(DB1X00_BOTH_BANKS) |
| 15785 | + window_addr = 0x1C000000; |
| 15786 | + window_size = 0x4000000; |
| 15787 | + /* USERFS from 0x1C00 0000 to 0x1FC0 0000 */ |
| 15788 | + db1x00_partitions[0].size = 0x3C00000; |
| 15789 | +#elif defined(DB1X00_BOOT_ONLY) |
| 15790 | + window_addr = 0x1E000000; |
| 15791 | + window_size = 0x2000000; |
| 15792 | + /* USERFS from 0x1E00 0000 to 0x1FC0 0000 */ |
| 15793 | + db1x00_partitions[0].size = 0x1C00000; |
| 15794 | +#else /* USER ONLY */ |
| 15795 | + window_addr = 0x1C000000; |
| 15796 | + window_size = 0x2000000; |
| 15797 | + /* USERFS from 0x1C00 0000 to 0x1DE00000 */ |
| 15798 | + db1x00_partitions[0].size = 0x1DE0000; |
| 15799 | +#endif |
| 15800 | + break; |
| 15801 | + case 2: |
| 15802 | + /* 256 Mbit devices */ |
| 15803 | + flash_size = 0x4000000; /* 64MB per part */ |
| 15804 | +#if defined(DB1X00_BOTH_BANKS) |
| 15805 | + return 1; |
| 15806 | +#elif defined(DB1X00_BOOT_ONLY) |
| 15807 | + /* Boot ROM flash bank only; no user bank */ |
| 15808 | + window_addr = 0x1C000000; |
| 15809 | + window_size = 0x4000000; |
| 15810 | + /* USERFS from 0x1C00 0000 to 0x1FC00000 */ |
| 15811 | + db1x00_partitions[0].size = 0x3C00000; |
| 15812 | +#else /* USER ONLY */ |
| 15813 | + return 1; |
| 15814 | +#endif |
| 15815 | + break; |
| 15816 | + default: |
| 15817 | + return 1; |
| 15818 | + } |
| 15819 | + return 0; |
| 15820 | +} |
| 15821 | + |
| 15822 | +int __init db1x00_mtd_init(void) |
| 15823 | +{ |
| 15824 | + struct mtd_partition *parts; |
| 15825 | + int nb_parts = 0; |
| 15826 | + char *part_type; |
| 15827 | + |
| 15828 | + /* Default flash buswidth */ |
| 15829 | + db1x00_map.buswidth = flash_buswidth; |
| 15830 | + |
| 15831 | + if (setup_flash_params()) |
| 15832 | + return -ENXIO; |
| 15833 | + |
| 15834 | + /* |
| 15835 | + * Static partition definition selection |
| 15836 | + */ |
| 15837 | + part_type = "static"; |
| 15838 | + parts = db1x00_partitions; |
| 15839 | + nb_parts = NB_OF(db1x00_partitions); |
| 15840 | + db1x00_map.size = window_size; |
| 15841 | + |
| 15842 | + /* |
| 15843 | + * Now let's probe for the actual flash. Do it here since |
| 15844 | + * specific machine settings might have been set above. |
| 15845 | + */ |
| 15846 | + printk(KERN_NOTICE "Db1xxx flash: probing %d-bit flash bus\n", |
| 15847 | + db1x00_map.buswidth*8); |
| 15848 | + db1x00_map.map_priv_1 = |
| 15849 | + (unsigned long)ioremap(window_addr, window_size); |
| 15850 | + mymtd = do_map_probe("cfi_probe", &db1x00_map); |
| 15851 | + if (!mymtd) return -ENXIO; |
| 15852 | + mymtd->module = THIS_MODULE; |
| 15853 | + |
| 15854 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 15855 | + return 0; |
| 15856 | +} |
| 15857 | + |
| 15858 | +static void __exit db1x00_mtd_cleanup(void) |
| 15859 | +{ |
| 15860 | + if (mymtd) { |
| 15861 | + del_mtd_partitions(mymtd); |
| 15862 | + map_destroy(mymtd); |
| 15863 | + if (parsed_parts) |
| 15864 | + kfree(parsed_parts); |
| 15865 | + } |
| 15866 | +} |
| 15867 | + |
| 15868 | +module_init(db1x00_mtd_init); |
| 15869 | +module_exit(db1x00_mtd_cleanup); |
| 15870 | + |
| 15871 | +MODULE_AUTHOR("Pete Popov"); |
| 15872 | +MODULE_DESCRIPTION("Db1x00 mtd map driver"); |
| 15873 | +MODULE_LICENSE("GPL"); |
| 15874 | --- /dev/null |
| 15875 | +++ b/drivers/mtd/maps/hydrogen3-flash.c |
| 15876 | @@ -0,0 +1,189 @@ |
| 15877 | +/* |
| 15878 | + * Flash memory access on Alchemy HydrogenIII boards |
| 15879 | + * |
| 15880 | + * (C) 2003 Pete Popov <ppopov@pacbell.net> |
| 15881 | + * |
| 15882 | + */ |
| 15883 | + |
| 15884 | +#include <linux/config.h> |
| 15885 | +#include <linux/module.h> |
| 15886 | +#include <linux/types.h> |
| 15887 | +#include <linux/kernel.h> |
| 15888 | + |
| 15889 | +#include <linux/mtd/mtd.h> |
| 15890 | +#include <linux/mtd/map.h> |
| 15891 | +#include <linux/mtd/partitions.h> |
| 15892 | + |
| 15893 | +#include <asm/io.h> |
| 15894 | +#include <asm/au1000.h> |
| 15895 | + |
| 15896 | +#ifdef DEBUG_RW |
| 15897 | +#define DBG(x...) printk(x) |
| 15898 | +#else |
| 15899 | +#define DBG(x...) |
| 15900 | +#endif |
| 15901 | + |
| 15902 | +#define WINDOW_ADDR 0x1E000000 |
| 15903 | +#define WINDOW_SIZE 0x02000000 |
| 15904 | + |
| 15905 | + |
| 15906 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 15907 | +{ |
| 15908 | + __u8 ret; |
| 15909 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 15910 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15911 | + return ret; |
| 15912 | +} |
| 15913 | + |
| 15914 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 15915 | +{ |
| 15916 | + __u16 ret; |
| 15917 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 15918 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15919 | + return ret; |
| 15920 | +} |
| 15921 | + |
| 15922 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 15923 | +{ |
| 15924 | + __u32 ret; |
| 15925 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 15926 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 15927 | + return ret; |
| 15928 | +} |
| 15929 | + |
| 15930 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 15931 | +{ |
| 15932 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 15933 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 15934 | +} |
| 15935 | + |
| 15936 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 15937 | +{ |
| 15938 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15939 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 15940 | + mb(); |
| 15941 | +} |
| 15942 | + |
| 15943 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 15944 | +{ |
| 15945 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15946 | + __raw_writew(d, map->map_priv_1 + adr); |
| 15947 | + mb(); |
| 15948 | +} |
| 15949 | + |
| 15950 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 15951 | +{ |
| 15952 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 15953 | + __raw_writel(d, map->map_priv_1 + adr); |
| 15954 | + mb(); |
| 15955 | +} |
| 15956 | + |
| 15957 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 15958 | +{ |
| 15959 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 15960 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 15961 | +} |
| 15962 | + |
| 15963 | +static struct map_info hydrogen3_map = { |
| 15964 | + name: "HydrogenIII flash", |
| 15965 | + read8: physmap_read8, |
| 15966 | + read16: physmap_read16, |
| 15967 | + read32: physmap_read32, |
| 15968 | + copy_from: physmap_copy_from, |
| 15969 | + write8: physmap_write8, |
| 15970 | + write16: physmap_write16, |
| 15971 | + write32: physmap_write32, |
| 15972 | + copy_to: physmap_copy_to, |
| 15973 | +}; |
| 15974 | + |
| 15975 | +static unsigned char flash_buswidth = 4; |
| 15976 | + |
| 15977 | +/* MTDPART_OFS_APPEND is vastly preferred to any attempt at statically lining |
| 15978 | + * up the offsets. */ |
| 15979 | +static struct mtd_partition hydrogen3_partitions[] = { |
| 15980 | + { |
| 15981 | + name: "User FS", |
| 15982 | + size: 0x1c00000, |
| 15983 | + offset: 0x0000000 |
| 15984 | + },{ |
| 15985 | + name: "yamon", |
| 15986 | + size: 0x0100000, |
| 15987 | + offset: MTDPART_OFS_APPEND, |
| 15988 | + mask_flags: MTD_WRITEABLE |
| 15989 | + },{ |
| 15990 | + name: "raw kernel", |
| 15991 | + size: 0x02c0000, |
| 15992 | + offset: MTDPART_OFS_APPEND |
| 15993 | + } |
| 15994 | +}; |
| 15995 | + |
| 15996 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 15997 | + |
| 15998 | +static struct mtd_partition *parsed_parts; |
| 15999 | +static struct mtd_info *mymtd; |
| 16000 | + |
| 16001 | +int __init hydrogen3_mtd_init(void) |
| 16002 | +{ |
| 16003 | + struct mtd_partition *parts; |
| 16004 | + int nb_parts = 0; |
| 16005 | + char *part_type; |
| 16006 | + |
| 16007 | + /* Default flash buswidth */ |
| 16008 | + hydrogen3_map.buswidth = flash_buswidth; |
| 16009 | + |
| 16010 | + /* |
| 16011 | + * Static partition definition selection |
| 16012 | + */ |
| 16013 | + part_type = "static"; |
| 16014 | + parts = hydrogen3_partitions; |
| 16015 | + nb_parts = NB_OF(hydrogen3_partitions); |
| 16016 | + hydrogen3_map.size = WINDOW_SIZE; |
| 16017 | + |
| 16018 | + /* |
| 16019 | + * Now let's probe for the actual flash. Do it here since |
| 16020 | + * specific machine settings might have been set above. |
| 16021 | + */ |
| 16022 | + printk(KERN_NOTICE "HydrogenIII flash: probing %d-bit flash bus\n", |
| 16023 | + hydrogen3_map.buswidth*8); |
| 16024 | + hydrogen3_map.map_priv_1 = |
| 16025 | + (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE); |
| 16026 | + mymtd = do_map_probe("cfi_probe", &hydrogen3_map); |
| 16027 | + if (!mymtd) return -ENXIO; |
| 16028 | + mymtd->module = THIS_MODULE; |
| 16029 | + |
| 16030 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 16031 | + return 0; |
| 16032 | +} |
| 16033 | + |
| 16034 | +static void __exit hydrogen3_mtd_cleanup(void) |
| 16035 | +{ |
| 16036 | + if (mymtd) { |
| 16037 | + del_mtd_partitions(mymtd); |
| 16038 | + map_destroy(mymtd); |
| 16039 | + if (parsed_parts) |
| 16040 | + kfree(parsed_parts); |
| 16041 | + } |
| 16042 | +} |
| 16043 | + |
| 16044 | +/*#ifndef MODULE |
| 16045 | + |
| 16046 | +static int __init _bootflashonly(char *str) |
| 16047 | +{ |
| 16048 | + bootflashonly = simple_strtol(str, NULL, 0); |
| 16049 | + return 1; |
| 16050 | +} |
| 16051 | + |
| 16052 | + |
| 16053 | +__setup("bootflashonly=", _bootflashonly); |
| 16054 | + |
| 16055 | +#endif*/ |
| 16056 | + |
| 16057 | + |
| 16058 | +module_init(hydrogen3_mtd_init); |
| 16059 | +module_exit(hydrogen3_mtd_cleanup); |
| 16060 | + |
| 16061 | +MODULE_PARM(bootflashonly, "i"); |
| 16062 | +MODULE_PARM_DESC(bootflashonly, "1=use \"boot flash only\""); |
| 16063 | +MODULE_AUTHOR("Pete Popov"); |
| 16064 | +MODULE_DESCRIPTION("HydrogenIII mtd map driver"); |
| 16065 | +MODULE_LICENSE("GPL"); |
| 16066 | --- a/drivers/mtd/maps/lasat.c |
| 16067 | +++ b/drivers/mtd/maps/lasat.c |
| 16068 | @@ -1,15 +1,6 @@ |
| 16069 | /* |
| 16070 | * Flash device on lasat 100 and 200 boards |
| 16071 | * |
| 16072 | - * Presumably (C) 2002 Brian Murphy <brian@murphy.dk> or whoever he |
| 16073 | - * works for. |
| 16074 | - * |
| 16075 | - * This program is free software; you can redistribute it and/or |
| 16076 | - * modify it under the terms of the GNU General Public License version |
| 16077 | - * 2 as published by the Free Software Foundation. |
| 16078 | - * |
| 16079 | - * $Id: lasat.c,v 1.1 2003/01/24 14:26:38 dwmw2 Exp $ |
| 16080 | - * |
| 16081 | */ |
| 16082 | |
| 16083 | #include <linux/module.h> |
| 16084 | @@ -21,7 +12,6 @@ |
| 16085 | #include <linux/mtd/partitions.h> |
| 16086 | #include <linux/config.h> |
| 16087 | #include <asm/lasat/lasat.h> |
| 16088 | -#include <asm/lasat/lasat_mtd.h> |
| 16089 | |
| 16090 | static struct mtd_info *mymtd; |
| 16091 | |
| 16092 | @@ -69,30 +59,33 @@ static void sp_copy_to(struct map_info * |
| 16093 | } |
| 16094 | |
| 16095 | static struct map_info sp_map = { |
| 16096 | - .name = "SP flash", |
| 16097 | - .buswidth = 4, |
| 16098 | - .read8 = sp_read8, |
| 16099 | - .read16 = sp_read16, |
| 16100 | - .read32 = sp_read32, |
| 16101 | - .copy_from = sp_copy_from, |
| 16102 | - .write8 = sp_write8, |
| 16103 | - .write16 = sp_write16, |
| 16104 | - .write32 = sp_write32, |
| 16105 | - .copy_to = sp_copy_to |
| 16106 | + name: "SP flash", |
| 16107 | + buswidth: 4, |
| 16108 | + read8: sp_read8, |
| 16109 | + read16: sp_read16, |
| 16110 | + read32: sp_read32, |
| 16111 | + copy_from: sp_copy_from, |
| 16112 | + write8: sp_write8, |
| 16113 | + write16: sp_write16, |
| 16114 | + write32: sp_write32, |
| 16115 | + copy_to: sp_copy_to |
| 16116 | }; |
| 16117 | |
| 16118 | static struct mtd_partition partition_info[LASAT_MTD_LAST]; |
| 16119 | -static char *lasat_mtd_partnames[] = {"Bootloader", "Service", "Normal", "Filesystem", "Config"}; |
| 16120 | +static char *lasat_mtd_partnames[] = {"Bootloader", "Service", "Normal", "Config", "Filesystem"}; |
| 16121 | |
| 16122 | static int __init init_sp(void) |
| 16123 | { |
| 16124 | int i; |
| 16125 | + int nparts = 0; |
| 16126 | /* this does not play well with the old flash code which |
| 16127 | * protects and uprotects the flash when necessary */ |
| 16128 | printk(KERN_NOTICE "Unprotecting flash\n"); |
| 16129 | *lasat_misc->flash_wp_reg |= 1 << lasat_misc->flash_wp_bit; |
| 16130 | |
| 16131 | - sp_map.map_priv_1 = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER); |
| 16132 | + sp_map.map_priv_1 = ioremap_nocache( |
| 16133 | + lasat_flash_partition_start(LASAT_MTD_BOOTLOADER), |
| 16134 | + lasat_board_info.li_flash_size); |
| 16135 | sp_map.size = lasat_board_info.li_flash_size; |
| 16136 | |
| 16137 | printk(KERN_NOTICE "sp flash device: %lx at %lx\n", |
| 16138 | @@ -109,12 +102,15 @@ static int __init init_sp(void) |
| 16139 | |
| 16140 | for (i=0; i < LASAT_MTD_LAST; i++) { |
| 16141 | size = lasat_flash_partition_size(i); |
| 16142 | - partition_info[i].size = size; |
| 16143 | - partition_info[i].offset = offset; |
| 16144 | - offset += size; |
| 16145 | + if (size != 0) { |
| 16146 | + nparts++; |
| 16147 | + partition_info[i].size = size; |
| 16148 | + partition_info[i].offset = offset; |
| 16149 | + offset += size; |
| 16150 | + } |
| 16151 | } |
| 16152 | |
| 16153 | - add_mtd_partitions( mymtd, partition_info, LASAT_MTD_LAST ); |
| 16154 | + add_mtd_partitions( mymtd, partition_info, nparts ); |
| 16155 | return 0; |
| 16156 | } |
| 16157 | |
| 16158 | @@ -124,11 +120,11 @@ static int __init init_sp(void) |
| 16159 | static void __exit cleanup_sp(void) |
| 16160 | { |
| 16161 | if (mymtd) { |
| 16162 | - del_mtd_partitions(mymtd); |
| 16163 | - map_destroy(mymtd); |
| 16164 | + del_mtd_partitions(mymtd); |
| 16165 | + map_destroy(mymtd); |
| 16166 | } |
| 16167 | if (sp_map.map_priv_1) { |
| 16168 | - sp_map.map_priv_1 = 0; |
| 16169 | + sp_map.map_priv_1 = 0; |
| 16170 | } |
| 16171 | } |
| 16172 | |
| 16173 | --- a/drivers/mtd/maps/Makefile |
| 16174 | +++ b/drivers/mtd/maps/Makefile |
| 16175 | @@ -52,7 +52,13 @@ obj-$(CONFIG_MTD_PCI) += pci.o |
| 16176 | obj-$(CONFIG_MTD_PB1000) += pb1xxx-flash.o |
| 16177 | obj-$(CONFIG_MTD_PB1100) += pb1xxx-flash.o |
| 16178 | obj-$(CONFIG_MTD_PB1500) += pb1xxx-flash.o |
| 16179 | +obj-$(CONFIG_MTD_XXS1500) += xxs1500.o |
| 16180 | +obj-$(CONFIG_MTD_MTX1) += mtx-1.o |
| 16181 | obj-$(CONFIG_MTD_LASAT) += lasat.o |
| 16182 | +obj-$(CONFIG_MTD_DB1X00) += db1x00-flash.o |
| 16183 | +obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o |
| 16184 | +obj-$(CONFIG_MTD_HYDROGEN3) += hydrogen3-flash.o |
| 16185 | +obj-$(CONFIG_MTD_BOSPORUS) += pb1xxx-flash.o |
| 16186 | obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o |
| 16187 | obj-$(CONFIG_MTD_EDB7312) += edb7312.o |
| 16188 | obj-$(CONFIG_MTD_IMPA7) += impa7.o |
| 16189 | @@ -61,5 +67,6 @@ obj-$(CONFIG_MTD_REDWOOD) += redwood.o |
| 16190 | obj-$(CONFIG_MTD_UCLINUX) += uclinux.o |
| 16191 | obj-$(CONFIG_MTD_NETtel) += nettel.o |
| 16192 | obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o |
| 16193 | +obj-$(CONFIG_MTD_MIRAGE) += mirage-flash.o |
| 16194 | |
| 16195 | include $(TOPDIR)/Rules.make |
| 16196 | --- /dev/null |
| 16197 | +++ b/drivers/mtd/maps/mirage-flash.c |
| 16198 | @@ -0,0 +1,194 @@ |
| 16199 | +/* |
| 16200 | + * Flash memory access on AMD Mirage board. |
| 16201 | + * |
| 16202 | + * (C) 2003 Embedded Edge |
| 16203 | + * based on mirage-flash.c: |
| 16204 | + * (C) 2003 Pete Popov <ppopov@pacbell.net> |
| 16205 | + * |
| 16206 | + */ |
| 16207 | + |
| 16208 | +#include <linux/config.h> |
| 16209 | +#include <linux/module.h> |
| 16210 | +#include <linux/types.h> |
| 16211 | +#include <linux/kernel.h> |
| 16212 | + |
| 16213 | +#include <linux/mtd/mtd.h> |
| 16214 | +#include <linux/mtd/map.h> |
| 16215 | +#include <linux/mtd/partitions.h> |
| 16216 | + |
| 16217 | +#include <asm/io.h> |
| 16218 | +#include <asm/au1000.h> |
| 16219 | +//#include <asm/mirage.h> |
| 16220 | + |
| 16221 | +#ifdef DEBUG_RW |
| 16222 | +#define DBG(x...) printk(x) |
| 16223 | +#else |
| 16224 | +#define DBG(x...) |
| 16225 | +#endif |
| 16226 | + |
| 16227 | +static unsigned long window_addr; |
| 16228 | +static unsigned long window_size; |
| 16229 | +static unsigned long flash_size; |
| 16230 | + |
| 16231 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 16232 | +{ |
| 16233 | + __u8 ret; |
| 16234 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 16235 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16236 | + return ret; |
| 16237 | +} |
| 16238 | + |
| 16239 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 16240 | +{ |
| 16241 | + __u16 ret; |
| 16242 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 16243 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16244 | + return ret; |
| 16245 | +} |
| 16246 | + |
| 16247 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 16248 | +{ |
| 16249 | + __u32 ret; |
| 16250 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 16251 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16252 | + return ret; |
| 16253 | +} |
| 16254 | + |
| 16255 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 16256 | +{ |
| 16257 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 16258 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 16259 | +} |
| 16260 | + |
| 16261 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 16262 | +{ |
| 16263 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16264 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 16265 | + mb(); |
| 16266 | +} |
| 16267 | + |
| 16268 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 16269 | +{ |
| 16270 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16271 | + __raw_writew(d, map->map_priv_1 + adr); |
| 16272 | + mb(); |
| 16273 | +} |
| 16274 | + |
| 16275 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 16276 | +{ |
| 16277 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16278 | + __raw_writel(d, map->map_priv_1 + adr); |
| 16279 | + mb(); |
| 16280 | +} |
| 16281 | + |
| 16282 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 16283 | +{ |
| 16284 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 16285 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 16286 | +} |
| 16287 | + |
| 16288 | +static struct map_info mirage_map = { |
| 16289 | + name: "Mirage flash", |
| 16290 | + read8: physmap_read8, |
| 16291 | + read16: physmap_read16, |
| 16292 | + read32: physmap_read32, |
| 16293 | + copy_from: physmap_copy_from, |
| 16294 | + write8: physmap_write8, |
| 16295 | + write16: physmap_write16, |
| 16296 | + write32: physmap_write32, |
| 16297 | + copy_to: physmap_copy_to, |
| 16298 | +}; |
| 16299 | + |
| 16300 | +static unsigned char flash_buswidth = 4; |
| 16301 | + |
| 16302 | +static struct mtd_partition mirage_partitions[] = { |
| 16303 | + { |
| 16304 | + name: "User FS", |
| 16305 | + size: 0x1c00000, |
| 16306 | + offset: 0x0000000 |
| 16307 | + },{ |
| 16308 | + name: "yamon", |
| 16309 | + size: 0x0100000, |
| 16310 | + offset: MTDPART_OFS_APPEND, |
| 16311 | + mask_flags: MTD_WRITEABLE |
| 16312 | + },{ |
| 16313 | + name: "raw kernel", |
| 16314 | + size: (0x300000-0x40000), /* last 256KB is yamon env */ |
| 16315 | + offset: MTDPART_OFS_APPEND, |
| 16316 | + } |
| 16317 | +}; |
| 16318 | + |
| 16319 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 16320 | + |
| 16321 | +static struct mtd_partition *parsed_parts; |
| 16322 | +static struct mtd_info *mymtd; |
| 16323 | + |
| 16324 | +/* |
| 16325 | + * Probe the flash density and setup window address and size |
| 16326 | + * based on user CONFIG options. There are times when we don't |
| 16327 | + * want the MTD driver to be probing the boot or user flash, |
| 16328 | + * so having the option to enable only one bank is important. |
| 16329 | + */ |
| 16330 | +int setup_flash_params() |
| 16331 | +{ |
| 16332 | + flash_size = 0x4000000; /* 64MB per part */ |
| 16333 | + /* Boot ROM flash bank only; no user bank */ |
| 16334 | + window_addr = 0x1C000000; |
| 16335 | + window_size = 0x4000000; |
| 16336 | + /* USERFS from 0x1C00 0000 to 0x1FC00000 */ |
| 16337 | + mirage_partitions[0].size = 0x3C00000; |
| 16338 | + return 0; |
| 16339 | +} |
| 16340 | + |
| 16341 | +int __init mirage_mtd_init(void) |
| 16342 | +{ |
| 16343 | + struct mtd_partition *parts; |
| 16344 | + int nb_parts = 0; |
| 16345 | + char *part_type; |
| 16346 | + |
| 16347 | + /* Default flash buswidth */ |
| 16348 | + mirage_map.buswidth = flash_buswidth; |
| 16349 | + |
| 16350 | + if (setup_flash_params()) |
| 16351 | + return -ENXIO; |
| 16352 | + |
| 16353 | + /* |
| 16354 | + * Static partition definition selection |
| 16355 | + */ |
| 16356 | + part_type = "static"; |
| 16357 | + parts = mirage_partitions; |
| 16358 | + nb_parts = NB_OF(mirage_partitions); |
| 16359 | + mirage_map.size = window_size; |
| 16360 | + |
| 16361 | + /* |
| 16362 | + * Now let's probe for the actual flash. Do it here since |
| 16363 | + * specific machine settings might have been set above. |
| 16364 | + */ |
| 16365 | + printk(KERN_NOTICE "Mirage flash: probing %d-bit flash bus\n", |
| 16366 | + mirage_map.buswidth*8); |
| 16367 | + mirage_map.map_priv_1 = |
| 16368 | + (unsigned long)ioremap(window_addr, window_size); |
| 16369 | + mymtd = do_map_probe("cfi_probe", &mirage_map); |
| 16370 | + if (!mymtd) return -ENXIO; |
| 16371 | + mymtd->module = THIS_MODULE; |
| 16372 | + |
| 16373 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 16374 | + return 0; |
| 16375 | +} |
| 16376 | + |
| 16377 | +static void __exit mirage_mtd_cleanup(void) |
| 16378 | +{ |
| 16379 | + if (mymtd) { |
| 16380 | + del_mtd_partitions(mymtd); |
| 16381 | + map_destroy(mymtd); |
| 16382 | + if (parsed_parts) |
| 16383 | + kfree(parsed_parts); |
| 16384 | + } |
| 16385 | +} |
| 16386 | + |
| 16387 | +module_init(mirage_mtd_init); |
| 16388 | +module_exit(mirage_mtd_cleanup); |
| 16389 | + |
| 16390 | +MODULE_AUTHOR("Embedded Edge"); |
| 16391 | +MODULE_DESCRIPTION("Mirage mtd map driver"); |
| 16392 | +MODULE_LICENSE("GPL"); |
| 16393 | --- /dev/null |
| 16394 | +++ b/drivers/mtd/maps/mtx-1.c |
| 16395 | @@ -0,0 +1,181 @@ |
| 16396 | +/* |
| 16397 | + * Flash memory access on 4G Systems MTX-1 board |
| 16398 | + * |
| 16399 | + * (C) 2003 Pete Popov <ppopov@mvista.com> |
| 16400 | + * Bruno Randolf <bruno.randolf@4g-systems.de> |
| 16401 | + */ |
| 16402 | + |
| 16403 | +#include <linux/config.h> |
| 16404 | +#include <linux/module.h> |
| 16405 | +#include <linux/types.h> |
| 16406 | +#include <linux/kernel.h> |
| 16407 | + |
| 16408 | +#include <linux/mtd/mtd.h> |
| 16409 | +#include <linux/mtd/map.h> |
| 16410 | +#include <linux/mtd/partitions.h> |
| 16411 | + |
| 16412 | +#include <asm/io.h> |
| 16413 | +#include <asm/au1000.h> |
| 16414 | + |
| 16415 | +#ifdef DEBUG_RW |
| 16416 | +#define DBG(x...) printk(x) |
| 16417 | +#else |
| 16418 | +#define DBG(x...) |
| 16419 | +#endif |
| 16420 | + |
| 16421 | +#ifdef CONFIG_MIPS_MTX1 |
| 16422 | +#define WINDOW_ADDR 0x1E000000 |
| 16423 | +#define WINDOW_SIZE 0x2000000 |
| 16424 | +#endif |
| 16425 | + |
| 16426 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 16427 | +{ |
| 16428 | + __u8 ret; |
| 16429 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 16430 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16431 | + return ret; |
| 16432 | +} |
| 16433 | + |
| 16434 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 16435 | +{ |
| 16436 | + __u16 ret; |
| 16437 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 16438 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16439 | + return ret; |
| 16440 | +} |
| 16441 | + |
| 16442 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 16443 | +{ |
| 16444 | + __u32 ret; |
| 16445 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 16446 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16447 | + return ret; |
| 16448 | +} |
| 16449 | + |
| 16450 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 16451 | +{ |
| 16452 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 16453 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 16454 | +} |
| 16455 | + |
| 16456 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 16457 | +{ |
| 16458 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16459 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 16460 | + mb(); |
| 16461 | +} |
| 16462 | + |
| 16463 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 16464 | +{ |
| 16465 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16466 | + __raw_writew(d, map->map_priv_1 + adr); |
| 16467 | + mb(); |
| 16468 | +} |
| 16469 | + |
| 16470 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 16471 | +{ |
| 16472 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16473 | + __raw_writel(d, map->map_priv_1 + adr); |
| 16474 | + mb(); |
| 16475 | +} |
| 16476 | + |
| 16477 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 16478 | +{ |
| 16479 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 16480 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 16481 | +} |
| 16482 | + |
| 16483 | + |
| 16484 | + |
| 16485 | +static struct map_info mtx1_map = { |
| 16486 | + name: "MTX-1 flash", |
| 16487 | + read8: physmap_read8, |
| 16488 | + read16: physmap_read16, |
| 16489 | + read32: physmap_read32, |
| 16490 | + copy_from: physmap_copy_from, |
| 16491 | + write8: physmap_write8, |
| 16492 | + write16: physmap_write16, |
| 16493 | + write32: physmap_write32, |
| 16494 | + copy_to: physmap_copy_to, |
| 16495 | +}; |
| 16496 | + |
| 16497 | + |
| 16498 | +static unsigned long flash_size = 0x01000000; |
| 16499 | +static unsigned char flash_buswidth = 4; |
| 16500 | +static struct mtd_partition mtx1_partitions[] = { |
| 16501 | + { |
| 16502 | + name: "user fs", |
| 16503 | + size: 0x1c00000, |
| 16504 | + offset: 0, |
| 16505 | + },{ |
| 16506 | + name: "yamon", |
| 16507 | + size: 0x0100000, |
| 16508 | + offset: MTDPART_OFS_APPEND, |
| 16509 | + mask_flags: MTD_WRITEABLE |
| 16510 | + },{ |
| 16511 | + name: "raw kernel", |
| 16512 | + size: 0x02c0000, |
| 16513 | + offset: MTDPART_OFS_APPEND, |
| 16514 | + },{ |
| 16515 | + name: "yamon env vars", |
| 16516 | + size: 0x0040000, |
| 16517 | + offset: MTDPART_OFS_APPEND, |
| 16518 | + mask_flags: MTD_WRITEABLE |
| 16519 | + } |
| 16520 | +}; |
| 16521 | + |
| 16522 | + |
| 16523 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 16524 | + |
| 16525 | +static struct mtd_partition *parsed_parts; |
| 16526 | +static struct mtd_info *mymtd; |
| 16527 | + |
| 16528 | +int __init mtx1_mtd_init(void) |
| 16529 | +{ |
| 16530 | + struct mtd_partition *parts; |
| 16531 | + int nb_parts = 0; |
| 16532 | + char *part_type; |
| 16533 | + |
| 16534 | + /* Default flash buswidth */ |
| 16535 | + mtx1_map.buswidth = flash_buswidth; |
| 16536 | + |
| 16537 | + /* |
| 16538 | + * Static partition definition selection |
| 16539 | + */ |
| 16540 | + part_type = "static"; |
| 16541 | + parts = mtx1_partitions; |
| 16542 | + nb_parts = NB_OF(mtx1_partitions); |
| 16543 | + mtx1_map.size = flash_size; |
| 16544 | + |
| 16545 | + /* |
| 16546 | + * Now let's probe for the actual flash. Do it here since |
| 16547 | + * specific machine settings might have been set above. |
| 16548 | + */ |
| 16549 | + printk(KERN_NOTICE "MTX-1 flash: probing %d-bit flash bus\n", |
| 16550 | + mtx1_map.buswidth*8); |
| 16551 | + mtx1_map.map_priv_1 = |
| 16552 | + (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE); |
| 16553 | + mymtd = do_map_probe("cfi_probe", &mtx1_map); |
| 16554 | + if (!mymtd) return -ENXIO; |
| 16555 | + mymtd->module = THIS_MODULE; |
| 16556 | + |
| 16557 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 16558 | + return 0; |
| 16559 | +} |
| 16560 | + |
| 16561 | +static void __exit mtx1_mtd_cleanup(void) |
| 16562 | +{ |
| 16563 | + if (mymtd) { |
| 16564 | + del_mtd_partitions(mymtd); |
| 16565 | + map_destroy(mymtd); |
| 16566 | + if (parsed_parts) |
| 16567 | + kfree(parsed_parts); |
| 16568 | + } |
| 16569 | +} |
| 16570 | + |
| 16571 | +module_init(mtx1_mtd_init); |
| 16572 | +module_exit(mtx1_mtd_cleanup); |
| 16573 | + |
| 16574 | +MODULE_AUTHOR("Pete Popov"); |
| 16575 | +MODULE_DESCRIPTION("MTX-1 CFI map driver"); |
| 16576 | +MODULE_LICENSE("GPL"); |
| 16577 | --- /dev/null |
| 16578 | +++ b/drivers/mtd/maps/pb1550-flash.c |
| 16579 | @@ -0,0 +1,270 @@ |
| 16580 | +/* |
| 16581 | + * Flash memory access on Alchemy Pb1550 board |
| 16582 | + * |
| 16583 | + * (C) 2004 Embedded Edge, LLC, based on pb1550-flash.c: |
| 16584 | + * (C) 2003 Pete Popov <ppopov@pacbell.net> |
| 16585 | + * |
| 16586 | + */ |
| 16587 | + |
| 16588 | +#include <linux/config.h> |
| 16589 | +#include <linux/module.h> |
| 16590 | +#include <linux/types.h> |
| 16591 | +#include <linux/kernel.h> |
| 16592 | + |
| 16593 | +#include <linux/mtd/mtd.h> |
| 16594 | +#include <linux/mtd/map.h> |
| 16595 | +#include <linux/mtd/partitions.h> |
| 16596 | + |
| 16597 | +#include <asm/io.h> |
| 16598 | +#include <asm/au1000.h> |
| 16599 | +#include <asm/pb1550.h> |
| 16600 | + |
| 16601 | +#ifdef DEBUG_RW |
| 16602 | +#define DBG(x...) printk(x) |
| 16603 | +#else |
| 16604 | +#define DBG(x...) |
| 16605 | +#endif |
| 16606 | + |
| 16607 | +static unsigned long window_addr; |
| 16608 | +static unsigned long window_size; |
| 16609 | + |
| 16610 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 16611 | +{ |
| 16612 | + __u8 ret; |
| 16613 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 16614 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16615 | + return ret; |
| 16616 | +} |
| 16617 | + |
| 16618 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 16619 | +{ |
| 16620 | + __u16 ret; |
| 16621 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 16622 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16623 | + return ret; |
| 16624 | +} |
| 16625 | + |
| 16626 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 16627 | +{ |
| 16628 | + __u32 ret; |
| 16629 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 16630 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16631 | + return ret; |
| 16632 | +} |
| 16633 | + |
| 16634 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 16635 | +{ |
| 16636 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 16637 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 16638 | +} |
| 16639 | + |
| 16640 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 16641 | +{ |
| 16642 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16643 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 16644 | + mb(); |
| 16645 | +} |
| 16646 | + |
| 16647 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 16648 | +{ |
| 16649 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16650 | + __raw_writew(d, map->map_priv_1 + adr); |
| 16651 | + mb(); |
| 16652 | +} |
| 16653 | + |
| 16654 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 16655 | +{ |
| 16656 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16657 | + __raw_writel(d, map->map_priv_1 + adr); |
| 16658 | + mb(); |
| 16659 | +} |
| 16660 | + |
| 16661 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 16662 | +{ |
| 16663 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 16664 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 16665 | +} |
| 16666 | + |
| 16667 | +static struct map_info pb1550_map = { |
| 16668 | + name: "Pb1550 flash", |
| 16669 | + read8: physmap_read8, |
| 16670 | + read16: physmap_read16, |
| 16671 | + read32: physmap_read32, |
| 16672 | + copy_from: physmap_copy_from, |
| 16673 | + write8: physmap_write8, |
| 16674 | + write16: physmap_write16, |
| 16675 | + write32: physmap_write32, |
| 16676 | + copy_to: physmap_copy_to, |
| 16677 | +}; |
| 16678 | + |
| 16679 | +static unsigned char flash_buswidth = 4; |
| 16680 | + |
| 16681 | +/* |
| 16682 | + * Support only 64MB NOR Flash parts |
| 16683 | + */ |
| 16684 | + |
| 16685 | +#ifdef PB1550_BOTH_BANKS |
| 16686 | +/* both banks will be used. Combine the first bank and the first |
| 16687 | + * part of the second bank together into a single jffs/jffs2 |
| 16688 | + * partition. |
| 16689 | + */ |
| 16690 | +static struct mtd_partition pb1550_partitions[] = { |
| 16691 | + /* assume boot[2:0]:swap is '0000' or '1000', which translates to: |
| 16692 | + * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash |
| 16693 | + * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash |
| 16694 | + */ |
| 16695 | + { |
| 16696 | + name: "User FS", |
| 16697 | + size: (0x1FC00000 - 0x18000000), |
| 16698 | + offset: 0x0000000 |
| 16699 | + },{ |
| 16700 | + name: "yamon", |
| 16701 | + size: 0x0100000, |
| 16702 | + offset: MTDPART_OFS_APPEND, |
| 16703 | + mask_flags: MTD_WRITEABLE |
| 16704 | + },{ |
| 16705 | + name: "raw kernel", |
| 16706 | + size: (0x300000 - 0x40000), /* last 256KB is yamon env */ |
| 16707 | + offset: MTDPART_OFS_APPEND, |
| 16708 | + } |
| 16709 | +}; |
| 16710 | +#elif defined(PB1550_BOOT_ONLY) |
| 16711 | +static struct mtd_partition pb1550_partitions[] = { |
| 16712 | + /* assume boot[2:0]:swap is '0000' or '1000', which translates to: |
| 16713 | + * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash |
| 16714 | + */ |
| 16715 | + { |
| 16716 | + name: "User FS", |
| 16717 | + size: 0x03c00000, |
| 16718 | + offset: 0x0000000 |
| 16719 | + },{ |
| 16720 | + name: "yamon", |
| 16721 | + size: 0x0100000, |
| 16722 | + offset: MTDPART_OFS_APPEND, |
| 16723 | + mask_flags: MTD_WRITEABLE |
| 16724 | + },{ |
| 16725 | + name: "raw kernel", |
| 16726 | + size: (0x300000-0x40000), /* last 256KB is yamon env */ |
| 16727 | + offset: MTDPART_OFS_APPEND, |
| 16728 | + } |
| 16729 | +}; |
| 16730 | +#elif defined(PB1550_USER_ONLY) |
| 16731 | +static struct mtd_partition pb1550_partitions[] = { |
| 16732 | + /* assume boot[2:0]:swap is '0000' or '1000', which translates to: |
| 16733 | + * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash |
| 16734 | + */ |
| 16735 | + { |
| 16736 | + name: "User FS", |
| 16737 | + size: (0x4000000 - 0x200000), /* reserve 2MB for raw kernel */ |
| 16738 | + offset: 0x0000000 |
| 16739 | + },{ |
| 16740 | + name: "raw kernel", |
| 16741 | + size: MTDPART_SIZ_FULL, |
| 16742 | + offset: MTDPART_OFS_APPEND, |
| 16743 | + } |
| 16744 | +}; |
| 16745 | +#else |
| 16746 | +#error MTD_PB1550 define combo error /* should never happen */ |
| 16747 | +#endif |
| 16748 | + |
| 16749 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 16750 | + |
| 16751 | +static struct mtd_partition *parsed_parts; |
| 16752 | +static struct mtd_info *mymtd; |
| 16753 | + |
| 16754 | +/* |
| 16755 | + * Probe the flash density and setup window address and size |
| 16756 | + * based on user CONFIG options. There are times when we don't |
| 16757 | + * want the MTD driver to be probing the boot or user flash, |
| 16758 | + * so having the option to enable only one bank is important. |
| 16759 | + */ |
| 16760 | +int setup_flash_params() |
| 16761 | +{ |
| 16762 | + u16 boot_swapboot; |
| 16763 | + boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) | |
| 16764 | + ((bcsr->status >> 6) & 0x1); |
| 16765 | + printk("Pb1550 MTD: boot:swap %d\n", boot_swapboot); |
| 16766 | + |
| 16767 | + switch (boot_swapboot) { |
| 16768 | + case 0: /* 512Mbit devices, both enabled */ |
| 16769 | + case 1: |
| 16770 | + case 8: |
| 16771 | + case 9: |
| 16772 | +#if defined(PB1550_BOTH_BANKS) |
| 16773 | + window_addr = 0x18000000; |
| 16774 | + window_size = 0x8000000; |
| 16775 | +#elif defined(PB1550_BOOT_ONLY) |
| 16776 | + window_addr = 0x1C000000; |
| 16777 | + window_size = 0x4000000; |
| 16778 | +#else /* USER ONLY */ |
| 16779 | + window_addr = 0x1E000000; |
| 16780 | + window_size = 0x1000000; |
| 16781 | +#endif |
| 16782 | + break; |
| 16783 | + case 0xC: |
| 16784 | + case 0xD: |
| 16785 | + case 0xE: |
| 16786 | + case 0xF: |
| 16787 | + /* 64 MB Boot NOR Flash is disabled */ |
| 16788 | + /* and the start address is moved to 0x0C00000 */ |
| 16789 | + window_addr = 0x0C000000; |
| 16790 | + window_size = 0x4000000; |
| 16791 | + default: |
| 16792 | + printk("Pb1550 MTD: unsupported boot:swap setting\n"); |
| 16793 | + return 1; |
| 16794 | + } |
| 16795 | + return 0; |
| 16796 | +} |
| 16797 | + |
| 16798 | +int __init pb1550_mtd_init(void) |
| 16799 | +{ |
| 16800 | + struct mtd_partition *parts; |
| 16801 | + int nb_parts = 0; |
| 16802 | + char *part_type; |
| 16803 | + |
| 16804 | + /* Default flash buswidth */ |
| 16805 | + pb1550_map.buswidth = flash_buswidth; |
| 16806 | + |
| 16807 | + if (setup_flash_params()) |
| 16808 | + return -ENXIO; |
| 16809 | + |
| 16810 | + /* |
| 16811 | + * Static partition definition selection |
| 16812 | + */ |
| 16813 | + part_type = "static"; |
| 16814 | + parts = pb1550_partitions; |
| 16815 | + nb_parts = NB_OF(pb1550_partitions); |
| 16816 | + pb1550_map.size = window_size; |
| 16817 | + |
| 16818 | + /* |
| 16819 | + * Now let's probe for the actual flash. Do it here since |
| 16820 | + * specific machine settings might have been set above. |
| 16821 | + */ |
| 16822 | + printk(KERN_NOTICE "Pb1550 flash: probing %d-bit flash bus\n", |
| 16823 | + pb1550_map.buswidth*8); |
| 16824 | + pb1550_map.map_priv_1 = |
| 16825 | + (unsigned long)ioremap(window_addr, window_size); |
| 16826 | + mymtd = do_map_probe("cfi_probe", &pb1550_map); |
| 16827 | + if (!mymtd) return -ENXIO; |
| 16828 | + mymtd->module = THIS_MODULE; |
| 16829 | + |
| 16830 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 16831 | + return 0; |
| 16832 | +} |
| 16833 | + |
| 16834 | +static void __exit pb1550_mtd_cleanup(void) |
| 16835 | +{ |
| 16836 | + if (mymtd) { |
| 16837 | + del_mtd_partitions(mymtd); |
| 16838 | + map_destroy(mymtd); |
| 16839 | + if (parsed_parts) |
| 16840 | + kfree(parsed_parts); |
| 16841 | + } |
| 16842 | +} |
| 16843 | + |
| 16844 | +module_init(pb1550_mtd_init); |
| 16845 | +module_exit(pb1550_mtd_cleanup); |
| 16846 | + |
| 16847 | +MODULE_AUTHOR("Embedded Edge, LLC"); |
| 16848 | +MODULE_DESCRIPTION("Pb1550 mtd map driver"); |
| 16849 | +MODULE_LICENSE("GPL"); |
| 16850 | --- a/drivers/mtd/maps/pb1xxx-flash.c |
| 16851 | +++ b/drivers/mtd/maps/pb1xxx-flash.c |
| 16852 | @@ -192,6 +192,34 @@ static struct mtd_partition pb1xxx_parti |
| 16853 | #else |
| 16854 | #error MTD_PB1500 define combo error /* should never happen */ |
| 16855 | #endif |
| 16856 | +#elif defined(CONFIG_MTD_BOSPORUS) |
| 16857 | +static unsigned char flash_buswidth = 2; |
| 16858 | +static unsigned long flash_size = 0x02000000; |
| 16859 | +#define WINDOW_ADDR 0x1F000000 |
| 16860 | +#define WINDOW_SIZE 0x2000000 |
| 16861 | +static struct mtd_partition pb1xxx_partitions[] = { |
| 16862 | + { |
| 16863 | + name: "User FS", |
| 16864 | + size: 0x00400000, |
| 16865 | + offset: 0x00000000, |
| 16866 | + },{ |
| 16867 | + name: "Yamon-2", |
| 16868 | + size: 0x00100000, |
| 16869 | + offset: 0x00400000, |
| 16870 | + },{ |
| 16871 | + name: "Root FS", |
| 16872 | + size: 0x00700000, |
| 16873 | + offset: 0x00500000, |
| 16874 | + },{ |
| 16875 | + name: "Yamon-1", |
| 16876 | + size: 0x00100000, |
| 16877 | + offset: 0x00C00000, |
| 16878 | + },{ |
| 16879 | + name: "Kernel", |
| 16880 | + size: 0x00300000, |
| 16881 | + offset: 0x00D00000, |
| 16882 | + } |
| 16883 | +}; |
| 16884 | #else |
| 16885 | #error Unsupported board |
| 16886 | #endif |
| 16887 | --- /dev/null |
| 16888 | +++ b/drivers/mtd/maps/xxs1500.c |
| 16889 | @@ -0,0 +1,186 @@ |
| 16890 | +/* |
| 16891 | + * Flash memory access on MyCable XXS1500 board |
| 16892 | + * |
| 16893 | + * (C) 2003 Pete Popov <ppopov@mvista.com> |
| 16894 | + * |
| 16895 | + * $Id: xxs1500.c,v 1.1.2.1 2003/06/13 21:15:46 ppopov Exp $ |
| 16896 | + */ |
| 16897 | + |
| 16898 | +#include <linux/config.h> |
| 16899 | +#include <linux/module.h> |
| 16900 | +#include <linux/types.h> |
| 16901 | +#include <linux/kernel.h> |
| 16902 | + |
| 16903 | +#include <linux/mtd/mtd.h> |
| 16904 | +#include <linux/mtd/map.h> |
| 16905 | +#include <linux/mtd/partitions.h> |
| 16906 | + |
| 16907 | +#include <asm/io.h> |
| 16908 | +#include <asm/au1000.h> |
| 16909 | + |
| 16910 | +#ifdef DEBUG_RW |
| 16911 | +#define DBG(x...) printk(x) |
| 16912 | +#else |
| 16913 | +#define DBG(x...) |
| 16914 | +#endif |
| 16915 | + |
| 16916 | +#ifdef CONFIG_MIPS_XXS1500 |
| 16917 | +#define WINDOW_ADDR 0x1F000000 |
| 16918 | +#define WINDOW_SIZE 0x1000000 |
| 16919 | +#endif |
| 16920 | + |
| 16921 | +__u8 physmap_read8(struct map_info *map, unsigned long ofs) |
| 16922 | +{ |
| 16923 | + __u8 ret; |
| 16924 | + ret = __raw_readb(map->map_priv_1 + ofs); |
| 16925 | + DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16926 | + return ret; |
| 16927 | +} |
| 16928 | + |
| 16929 | +__u16 physmap_read16(struct map_info *map, unsigned long ofs) |
| 16930 | +{ |
| 16931 | + __u16 ret; |
| 16932 | + ret = __raw_readw(map->map_priv_1 + ofs); |
| 16933 | + DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16934 | + return ret; |
| 16935 | +} |
| 16936 | + |
| 16937 | +__u32 physmap_read32(struct map_info *map, unsigned long ofs) |
| 16938 | +{ |
| 16939 | + __u32 ret; |
| 16940 | + ret = __raw_readl(map->map_priv_1 + ofs); |
| 16941 | + DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret); |
| 16942 | + return ret; |
| 16943 | +} |
| 16944 | + |
| 16945 | +void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
| 16946 | +{ |
| 16947 | + DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to); |
| 16948 | + memcpy_fromio(to, map->map_priv_1 + from, len); |
| 16949 | +} |
| 16950 | + |
| 16951 | +void physmap_write8(struct map_info *map, __u8 d, unsigned long adr) |
| 16952 | +{ |
| 16953 | + DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16954 | + __raw_writeb(d, map->map_priv_1 + adr); |
| 16955 | + mb(); |
| 16956 | +} |
| 16957 | + |
| 16958 | +void physmap_write16(struct map_info *map, __u16 d, unsigned long adr) |
| 16959 | +{ |
| 16960 | + DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16961 | + __raw_writew(d, map->map_priv_1 + adr); |
| 16962 | + mb(); |
| 16963 | +} |
| 16964 | + |
| 16965 | +void physmap_write32(struct map_info *map, __u32 d, unsigned long adr) |
| 16966 | +{ |
| 16967 | + DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d); |
| 16968 | + __raw_writel(d, map->map_priv_1 + adr); |
| 16969 | + mb(); |
| 16970 | +} |
| 16971 | + |
| 16972 | +void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
| 16973 | +{ |
| 16974 | + DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from); |
| 16975 | + memcpy_toio(map->map_priv_1 + to, from, len); |
| 16976 | +} |
| 16977 | + |
| 16978 | + |
| 16979 | + |
| 16980 | +static struct map_info xxs1500_map = { |
| 16981 | + name: "XXS1500 flash", |
| 16982 | + read8: physmap_read8, |
| 16983 | + read16: physmap_read16, |
| 16984 | + read32: physmap_read32, |
| 16985 | + copy_from: physmap_copy_from, |
| 16986 | + write8: physmap_write8, |
| 16987 | + write16: physmap_write16, |
| 16988 | + write32: physmap_write32, |
| 16989 | + copy_to: physmap_copy_to, |
| 16990 | +}; |
| 16991 | + |
| 16992 | + |
| 16993 | +static unsigned long flash_size = 0x00800000; |
| 16994 | +static unsigned char flash_buswidth = 4; |
| 16995 | +static struct mtd_partition xxs1500_partitions[] = { |
| 16996 | + { |
| 16997 | + name: "kernel image", |
| 16998 | + size: 0x00200000, |
| 16999 | + offset: 0, |
| 17000 | + },{ |
| 17001 | + name: "user fs 0", |
| 17002 | + size: (0x00C00000-0x200000), |
| 17003 | + offset: MTDPART_OFS_APPEND, |
| 17004 | + },{ |
| 17005 | + name: "yamon", |
| 17006 | + size: 0x00100000, |
| 17007 | + offset: MTDPART_OFS_APPEND, |
| 17008 | + mask_flags: MTD_WRITEABLE |
| 17009 | + },{ |
| 17010 | + name: "user fs 1", |
| 17011 | + size: 0x2c0000, |
| 17012 | + offset: MTDPART_OFS_APPEND, |
| 17013 | + },{ |
| 17014 | + name: "yamon env vars", |
| 17015 | + size: 0x040000, |
| 17016 | + offset: MTDPART_OFS_APPEND, |
| 17017 | + mask_flags: MTD_WRITEABLE |
| 17018 | + } |
| 17019 | +}; |
| 17020 | + |
| 17021 | + |
| 17022 | +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) |
| 17023 | + |
| 17024 | +static struct mtd_partition *parsed_parts; |
| 17025 | +static struct mtd_info *mymtd; |
| 17026 | + |
| 17027 | +int __init xxs1500_mtd_init(void) |
| 17028 | +{ |
| 17029 | + struct mtd_partition *parts; |
| 17030 | + int nb_parts = 0; |
| 17031 | + char *part_type; |
| 17032 | + |
| 17033 | + /* Default flash buswidth */ |
| 17034 | + xxs1500_map.buswidth = flash_buswidth; |
| 17035 | + |
| 17036 | + /* |
| 17037 | + * Static partition definition selection |
| 17038 | + */ |
| 17039 | + part_type = "static"; |
| 17040 | + parts = xxs1500_partitions; |
| 17041 | + nb_parts = NB_OF(xxs1500_partitions); |
| 17042 | + xxs1500_map.size = flash_size; |
| 17043 | + |
| 17044 | + /* |
| 17045 | + * Now let's probe for the actual flash. Do it here since |
| 17046 | + * specific machine settings might have been set above. |
| 17047 | + */ |
| 17048 | + printk(KERN_NOTICE "XXS1500 flash: probing %d-bit flash bus\n", |
| 17049 | + xxs1500_map.buswidth*8); |
| 17050 | + xxs1500_map.map_priv_1 = |
| 17051 | + (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE); |
| 17052 | + mymtd = do_map_probe("cfi_probe", &xxs1500_map); |
| 17053 | + if (!mymtd) return -ENXIO; |
| 17054 | + mymtd->module = THIS_MODULE; |
| 17055 | + |
| 17056 | + add_mtd_partitions(mymtd, parts, nb_parts); |
| 17057 | + return 0; |
| 17058 | +} |
| 17059 | + |
| 17060 | +static void __exit xxs1500_mtd_cleanup(void) |
| 17061 | +{ |
| 17062 | + if (mymtd) { |
| 17063 | + del_mtd_partitions(mymtd); |
| 17064 | + map_destroy(mymtd); |
| 17065 | + if (parsed_parts) |
| 17066 | + kfree(parsed_parts); |
| 17067 | + } |
| 17068 | +} |
| 17069 | + |
| 17070 | +module_init(xxs1500_mtd_init); |
| 17071 | +module_exit(xxs1500_mtd_cleanup); |
| 17072 | + |
| 17073 | +MODULE_AUTHOR("Pete Popov"); |
| 17074 | +MODULE_DESCRIPTION("XXS1500 CFI map driver"); |
| 17075 | +MODULE_LICENSE("GPL"); |
| 17076 | --- a/drivers/net/defxx.c |
| 17077 | +++ b/drivers/net/defxx.c |
| 17078 | @@ -10,24 +10,18 @@ |
| 17079 | * |
| 17080 | * Abstract: |
| 17081 | * A Linux device driver supporting the Digital Equipment Corporation |
| 17082 | - * FDDI EISA and PCI controller families. Supported adapters include: |
| 17083 | + * FDDI TURBOchannel, EISA and PCI controller families. Supported |
| 17084 | + * adapters include: |
| 17085 | * |
| 17086 | - * DEC FDDIcontroller/EISA (DEFEA) |
| 17087 | - * DEC FDDIcontroller/PCI (DEFPA) |
| 17088 | + * DEC FDDIcontroller/TURBOchannel (DEFTA) |
| 17089 | + * DEC FDDIcontroller/EISA (DEFEA) |
| 17090 | + * DEC FDDIcontroller/PCI (DEFPA) |
| 17091 | * |
| 17092 | - * Maintainers: |
| 17093 | - * LVS Lawrence V. Stefani |
| 17094 | - * |
| 17095 | - * Contact: |
| 17096 | - * The author may be reached at: |
| 17097 | + * The original author: |
| 17098 | + * LVS Lawrence V. Stefani <lstefani@yahoo.com> |
| 17099 | * |
| 17100 | - * Inet: stefani@lkg.dec.com |
| 17101 | - * (NOTE! this address no longer works -jgarzik) |
| 17102 | - * |
| 17103 | - * Mail: Digital Equipment Corporation |
| 17104 | - * 550 King Street |
| 17105 | - * M/S: LKG1-3/M07 |
| 17106 | - * Littleton, MA 01460 |
| 17107 | + * Maintainers: |
| 17108 | + * macro Maciej W. Rozycki <macro@linux-mips.org> |
| 17109 | * |
| 17110 | * Credits: |
| 17111 | * I'd like to thank Patricia Cross for helping me get started with |
| 17112 | @@ -197,16 +191,16 @@ |
| 17113 | * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup |
| 17114 | * Feb 2001 Skb allocation fixes |
| 17115 | * Feb 2001 davej PCI enable cleanups. |
| 17116 | + * 04 Aug 2003 macro Converted to the DMA API. |
| 17117 | + * 14 Aug 2004 macro Fix device names reported. |
| 17118 | + * 26 Sep 2004 macro TURBOchannel support. |
| 17119 | */ |
| 17120 | |
| 17121 | /* Include files */ |
| 17122 | |
| 17123 | #include <linux/module.h> |
| 17124 | - |
| 17125 | #include <linux/kernel.h> |
| 17126 | -#include <linux/sched.h> |
| 17127 | #include <linux/string.h> |
| 17128 | -#include <linux/ptrace.h> |
| 17129 | #include <linux/errno.h> |
| 17130 | #include <linux/ioport.h> |
| 17131 | #include <linux/slab.h> |
| 17132 | @@ -215,19 +209,33 @@ |
| 17133 | #include <linux/delay.h> |
| 17134 | #include <linux/init.h> |
| 17135 | #include <linux/netdevice.h> |
| 17136 | +#include <linux/fddidevice.h> |
| 17137 | +#include <linux/skbuff.h> |
| 17138 | + |
| 17139 | #include <asm/byteorder.h> |
| 17140 | #include <asm/bitops.h> |
| 17141 | #include <asm/io.h> |
| 17142 | |
| 17143 | -#include <linux/fddidevice.h> |
| 17144 | -#include <linux/skbuff.h> |
| 17145 | +#ifdef CONFIG_TC |
| 17146 | +#include <asm/dec/tc.h> |
| 17147 | +#else |
| 17148 | +static int search_tc_card(const char *name) { return -ENODEV; } |
| 17149 | +static void claim_tc_card(int slot) { } |
| 17150 | +static void release_tc_card(int slot) { } |
| 17151 | +static unsigned long get_tc_base_addr(int slot) { return 0; } |
| 17152 | +static unsigned long get_tc_irq_nr(int slot) { return -1; } |
| 17153 | +#endif |
| 17154 | |
| 17155 | #include "defxx.h" |
| 17156 | |
| 17157 | -/* Version information string - should be updated prior to each new release!!! */ |
| 17158 | +/* Version information string should be updated prior to each new release! */ |
| 17159 | +#define DRV_NAME "defxx" |
| 17160 | +#define DRV_VERSION "v1.07T" |
| 17161 | +#define DRV_RELDATE "2004/09/26" |
| 17162 | |
| 17163 | static char version[] __devinitdata = |
| 17164 | - "defxx.c:v1.05e 2001/02/03 Lawrence V. Stefani and others\n"; |
| 17165 | + DRV_NAME ": " DRV_VERSION " " DRV_RELDATE |
| 17166 | + " Lawrence V. Stefani and others\n"; |
| 17167 | |
| 17168 | #define DYNAMIC_BUFFERS 1 |
| 17169 | |
| 17170 | @@ -243,7 +251,7 @@ static char version[] __devinitdata = |
| 17171 | static void dfx_bus_init(struct net_device *dev); |
| 17172 | static void dfx_bus_config_check(DFX_board_t *bp); |
| 17173 | |
| 17174 | -static int dfx_driver_init(struct net_device *dev); |
| 17175 | +static int dfx_driver_init(struct net_device *dev, const char *print_name); |
| 17176 | static int dfx_adap_init(DFX_board_t *bp, int get_buffers); |
| 17177 | |
| 17178 | static int dfx_open(struct net_device *dev); |
| 17179 | @@ -337,48 +345,84 @@ static inline void dfx_port_write_byte( |
| 17180 | int offset, |
| 17181 | u8 data |
| 17182 | ) |
| 17183 | +{ |
| 17184 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17185 | + { |
| 17186 | + volatile u8 *addr = (void *)(bp->base_addr + offset); |
| 17187 | |
| 17188 | + *addr = data; |
| 17189 | + mb(); |
| 17190 | + } |
| 17191 | + else |
| 17192 | { |
| 17193 | u16 port = bp->base_addr + offset; |
| 17194 | |
| 17195 | outb(data, port); |
| 17196 | } |
| 17197 | +} |
| 17198 | |
| 17199 | static inline void dfx_port_read_byte( |
| 17200 | DFX_board_t *bp, |
| 17201 | int offset, |
| 17202 | u8 *data |
| 17203 | ) |
| 17204 | +{ |
| 17205 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17206 | + { |
| 17207 | + volatile u8 *addr = (void *)(bp->base_addr + offset); |
| 17208 | |
| 17209 | + mb(); |
| 17210 | + *data = *addr; |
| 17211 | + } |
| 17212 | + else |
| 17213 | { |
| 17214 | u16 port = bp->base_addr + offset; |
| 17215 | |
| 17216 | *data = inb(port); |
| 17217 | } |
| 17218 | +} |
| 17219 | |
| 17220 | static inline void dfx_port_write_long( |
| 17221 | DFX_board_t *bp, |
| 17222 | int offset, |
| 17223 | u32 data |
| 17224 | ) |
| 17225 | +{ |
| 17226 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17227 | + { |
| 17228 | + volatile u32 *addr = (void *)(bp->base_addr + offset); |
| 17229 | |
| 17230 | + *addr = data; |
| 17231 | + mb(); |
| 17232 | + } |
| 17233 | + else |
| 17234 | { |
| 17235 | u16 port = bp->base_addr + offset; |
| 17236 | |
| 17237 | outl(data, port); |
| 17238 | } |
| 17239 | +} |
| 17240 | |
| 17241 | static inline void dfx_port_read_long( |
| 17242 | DFX_board_t *bp, |
| 17243 | int offset, |
| 17244 | u32 *data |
| 17245 | ) |
| 17246 | +{ |
| 17247 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17248 | + { |
| 17249 | + volatile u32 *addr = (void *)(bp->base_addr + offset); |
| 17250 | |
| 17251 | + mb(); |
| 17252 | + *data = *addr; |
| 17253 | + } |
| 17254 | + else |
| 17255 | { |
| 17256 | u16 port = bp->base_addr + offset; |
| 17257 | |
| 17258 | *data = inl(port); |
| 17259 | } |
| 17260 | +} |
| 17261 | |
| 17262 | |
| 17263 | /* |
| 17264 | @@ -393,8 +437,9 @@ static inline void dfx_port_read_long( |
| 17265 | * Condition code |
| 17266 | * |
| 17267 | * Arguments: |
| 17268 | - * pdev - pointer to pci device information (NULL for EISA) |
| 17269 | - * ioaddr - pointer to port (NULL for PCI) |
| 17270 | + * pdev - pointer to pci device information (NULL for EISA or TURBOchannel) |
| 17271 | + * bus_type - bus type (one of DFX_BUS_TYPE_*) |
| 17272 | + * handle - bus-specific data: slot (TC), pointer to port (EISA), NULL (PCI) |
| 17273 | * |
| 17274 | * Functional Description: |
| 17275 | * |
| 17276 | @@ -410,54 +455,68 @@ static inline void dfx_port_read_long( |
| 17277 | * initialized and the board resources are read and stored in |
| 17278 | * the device structure. |
| 17279 | */ |
| 17280 | -static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr) |
| 17281 | +static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, u32 bus_type, long handle) |
| 17282 | { |
| 17283 | + static int version_disp; |
| 17284 | + char *print_name = DRV_NAME; |
| 17285 | struct net_device *dev; |
| 17286 | DFX_board_t *bp; /* board pointer */ |
| 17287 | + long ioaddr; /* pointer to port */ |
| 17288 | + unsigned long len; /* resource length */ |
| 17289 | + int alloc_size; /* total buffer size used */ |
| 17290 | int err; |
| 17291 | |
| 17292 | -#ifndef MODULE |
| 17293 | - static int version_disp; |
| 17294 | - |
| 17295 | - if (!version_disp) /* display version info if adapter is found */ |
| 17296 | - { |
| 17297 | + if (!version_disp) { /* display version info if adapter is found */ |
| 17298 | version_disp = 1; /* set display flag to TRUE so that */ |
| 17299 | printk(version); /* we only display this string ONCE */ |
| 17300 | } |
| 17301 | -#endif |
| 17302 | |
| 17303 | - /* |
| 17304 | - * init_fddidev() allocates a device structure with private data, clears the device structure and private data, |
| 17305 | - * and calls fddi_setup() and register_netdev(). Not much left to do for us here. |
| 17306 | - */ |
| 17307 | - dev = init_fddidev(NULL, sizeof(*bp)); |
| 17308 | + if (pdev != NULL) |
| 17309 | + print_name = pdev->slot_name; |
| 17310 | + |
| 17311 | + dev = alloc_fddidev(sizeof(*bp)); |
| 17312 | if (!dev) { |
| 17313 | - printk (KERN_ERR "defxx: unable to allocate fddidev, aborting\n"); |
| 17314 | + printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n", |
| 17315 | + print_name); |
| 17316 | return -ENOMEM; |
| 17317 | } |
| 17318 | |
| 17319 | /* Enable PCI device. */ |
| 17320 | - if (pdev != NULL) { |
| 17321 | + if (bus_type == DFX_BUS_TYPE_PCI) { |
| 17322 | err = pci_enable_device (pdev); |
| 17323 | if (err) goto err_out; |
| 17324 | ioaddr = pci_resource_start (pdev, 1); |
| 17325 | } |
| 17326 | |
| 17327 | SET_MODULE_OWNER(dev); |
| 17328 | + SET_NETDEV_DEV(dev, &pdev->dev); |
| 17329 | |
| 17330 | bp = dev->priv; |
| 17331 | |
| 17332 | - if (!request_region (ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, dev->name)) { |
| 17333 | - printk (KERN_ERR "%s: Cannot reserve I/O resource 0x%x @ 0x%lx, aborting\n", |
| 17334 | - dev->name, PFI_K_CSR_IO_LEN, ioaddr); |
| 17335 | + if (bus_type == DFX_BUS_TYPE_TC) { |
| 17336 | + /* TURBOchannel board */ |
| 17337 | + bp->slot = handle; |
| 17338 | + claim_tc_card(bp->slot); |
| 17339 | + ioaddr = get_tc_base_addr(handle) + PI_TC_K_CSR_OFFSET; |
| 17340 | + len = PI_TC_K_CSR_LEN; |
| 17341 | + } else if (bus_type == DFX_BUS_TYPE_EISA) { |
| 17342 | + /* EISA board */ |
| 17343 | + ioaddr = handle; |
| 17344 | + len = PI_ESIC_K_CSR_IO_LEN; |
| 17345 | + } else |
| 17346 | + /* PCI board */ |
| 17347 | + len = PFI_K_CSR_IO_LEN; |
| 17348 | + dev->base_addr = ioaddr; /* save port (I/O) base address */ |
| 17349 | + |
| 17350 | + if (!request_region(ioaddr, len, print_name)) { |
| 17351 | + printk(KERN_ERR "%s: Cannot reserve I/O resource " |
| 17352 | + "0x%lx @ 0x%lx, aborting\n", print_name, len, ioaddr); |
| 17353 | err = -EBUSY; |
| 17354 | goto err_out; |
| 17355 | } |
| 17356 | |
| 17357 | /* Initialize new device structure */ |
| 17358 | |
| 17359 | - dev->base_addr = ioaddr; /* save port (I/O) base address */ |
| 17360 | - |
| 17361 | dev->get_stats = dfx_ctl_get_stats; |
| 17362 | dev->open = dfx_open; |
| 17363 | dev->stop = dfx_close; |
| 17364 | @@ -465,37 +524,54 @@ static int __devinit dfx_init_one_pci_or |
| 17365 | dev->set_multicast_list = dfx_ctl_set_multicast_list; |
| 17366 | dev->set_mac_address = dfx_ctl_set_mac_address; |
| 17367 | |
| 17368 | - if (pdev == NULL) { |
| 17369 | - /* EISA board */ |
| 17370 | - bp->bus_type = DFX_BUS_TYPE_EISA; |
| 17371 | + bp->bus_type = bus_type; |
| 17372 | + if (bus_type == DFX_BUS_TYPE_TC || bus_type == DFX_BUS_TYPE_EISA) { |
| 17373 | + /* TURBOchannel or EISA board */ |
| 17374 | bp->next = root_dfx_eisa_dev; |
| 17375 | root_dfx_eisa_dev = dev; |
| 17376 | } else { |
| 17377 | /* PCI board */ |
| 17378 | - bp->bus_type = DFX_BUS_TYPE_PCI; |
| 17379 | bp->pci_dev = pdev; |
| 17380 | pci_set_drvdata (pdev, dev); |
| 17381 | pci_set_master (pdev); |
| 17382 | } |
| 17383 | |
| 17384 | - if (dfx_driver_init(dev) != DFX_K_SUCCESS) { |
| 17385 | + |
| 17386 | + if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) { |
| 17387 | err = -ENODEV; |
| 17388 | goto err_out_region; |
| 17389 | } |
| 17390 | |
| 17391 | + err = register_netdev(dev); |
| 17392 | + if (err) |
| 17393 | + goto err_out_kfree; |
| 17394 | + |
| 17395 | + printk("%s: registered as %s\n", print_name, dev->name); |
| 17396 | return 0; |
| 17397 | |
| 17398 | +err_out_kfree: |
| 17399 | + alloc_size = sizeof(PI_DESCR_BLOCK) + |
| 17400 | + PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + |
| 17401 | +#ifndef DYNAMIC_BUFFERS |
| 17402 | + (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + |
| 17403 | +#endif |
| 17404 | + sizeof(PI_CONSUMER_BLOCK) + |
| 17405 | + (PI_ALIGN_K_DESC_BLK - 1); |
| 17406 | + if (bp->kmalloced) |
| 17407 | + pci_free_consistent(pdev, alloc_size, |
| 17408 | + bp->kmalloced, bp->kmalloced_dma); |
| 17409 | err_out_region: |
| 17410 | - release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN); |
| 17411 | + release_region(ioaddr, len); |
| 17412 | err_out: |
| 17413 | - unregister_netdev(dev); |
| 17414 | - kfree(dev); |
| 17415 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17416 | + release_tc_card(bp->slot); |
| 17417 | + free_netdev(dev); |
| 17418 | return err; |
| 17419 | } |
| 17420 | |
| 17421 | static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 17422 | { |
| 17423 | - return dfx_init_one_pci_or_eisa(pdev, 0); |
| 17424 | + return dfx_init_one_pci_or_eisa(pdev, DFX_BUS_TYPE_PCI, 0); |
| 17425 | } |
| 17426 | |
| 17427 | static int __init dfx_eisa_init(void) |
| 17428 | @@ -507,6 +583,7 @@ static int __init dfx_eisa_init(void) |
| 17429 | |
| 17430 | DBG_printk("In dfx_eisa_init...\n"); |
| 17431 | |
| 17432 | +#ifdef CONFIG_EISA |
| 17433 | /* Scan for FDDI EISA controllers */ |
| 17434 | |
| 17435 | for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */ |
| 17436 | @@ -517,9 +594,27 @@ static int __init dfx_eisa_init(void) |
| 17437 | { |
| 17438 | port = (i << 12); /* recalc base addr */ |
| 17439 | |
| 17440 | - if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0; |
| 17441 | + if (dfx_init_one_pci_or_eisa(NULL, DFX_BUS_TYPE_EISA, port) == 0) rc = 0; |
| 17442 | } |
| 17443 | } |
| 17444 | +#endif |
| 17445 | + return rc; |
| 17446 | +} |
| 17447 | + |
| 17448 | +static int __init dfx_tc_init(void) |
| 17449 | +{ |
| 17450 | + int rc = -ENODEV; |
| 17451 | + int slot; /* TC slot number */ |
| 17452 | + |
| 17453 | + DBG_printk("In dfx_tc_init...\n"); |
| 17454 | + |
| 17455 | + /* Scan for FDDI TC controllers */ |
| 17456 | + while ((slot = search_tc_card("PMAF-F")) >= 0) { |
| 17457 | + if (dfx_init_one_pci_or_eisa(NULL, DFX_BUS_TYPE_TC, slot) == 0) |
| 17458 | + rc = 0; |
| 17459 | + else |
| 17460 | + break; |
| 17461 | + } |
| 17462 | return rc; |
| 17463 | } |
| 17464 | |
| 17465 | @@ -583,8 +678,9 @@ static void __devinit dfx_bus_init(struc |
| 17466 | |
| 17467 | /* Initialize adapter based on bus type */ |
| 17468 | |
| 17469 | - if (bp->bus_type == DFX_BUS_TYPE_EISA) |
| 17470 | - { |
| 17471 | + if (bp->bus_type == DFX_BUS_TYPE_TC) { |
| 17472 | + dev->irq = get_tc_irq_nr(bp->slot); |
| 17473 | + } else if (bp->bus_type == DFX_BUS_TYPE_EISA) { |
| 17474 | /* Get the interrupt level from the ESIC chip */ |
| 17475 | |
| 17476 | dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val); |
| 17477 | @@ -766,6 +862,7 @@ static void __devinit dfx_bus_config_che |
| 17478 | * |
| 17479 | * Arguments: |
| 17480 | * dev - pointer to device information |
| 17481 | + * print_name - printable device name |
| 17482 | * |
| 17483 | * Functional Description: |
| 17484 | * This function allocates additional resources such as the host memory |
| 17485 | @@ -780,20 +877,21 @@ static void __devinit dfx_bus_config_che |
| 17486 | * or read adapter MAC address |
| 17487 | * |
| 17488 | * Assumptions: |
| 17489 | - * Memory allocated from kmalloc() call is physically contiguous, locked |
| 17490 | - * memory whose physical address equals its virtual address. |
| 17491 | + * Memory allocated from pci_alloc_consistent() call is physically |
| 17492 | + * contiguous, locked memory. |
| 17493 | * |
| 17494 | * Side Effects: |
| 17495 | * Adapter is reset and should be in DMA_UNAVAILABLE state before |
| 17496 | * returning from this routine. |
| 17497 | */ |
| 17498 | |
| 17499 | -static int __devinit dfx_driver_init(struct net_device *dev) |
| 17500 | +static int __devinit dfx_driver_init(struct net_device *dev, |
| 17501 | + const char *print_name) |
| 17502 | { |
| 17503 | DFX_board_t *bp = dev->priv; |
| 17504 | int alloc_size; /* total buffer size needed */ |
| 17505 | char *top_v, *curr_v; /* virtual addrs into memory block */ |
| 17506 | - u32 top_p, curr_p; /* physical addrs into memory block */ |
| 17507 | + dma_addr_t top_p, curr_p; /* physical addrs into memory block */ |
| 17508 | u32 data; /* host data register value */ |
| 17509 | |
| 17510 | DBG_printk("In dfx_driver_init...\n"); |
| 17511 | @@ -837,26 +935,20 @@ static int __devinit dfx_driver_init(str |
| 17512 | |
| 17513 | /* Read the factory MAC address from the adapter then save it */ |
| 17514 | |
| 17515 | - if (dfx_hw_port_ctrl_req(bp, |
| 17516 | - PI_PCTRL_M_MLA, |
| 17517 | - PI_PDATA_A_MLA_K_LO, |
| 17518 | - 0, |
| 17519 | - &data) != DFX_K_SUCCESS) |
| 17520 | - { |
| 17521 | - printk("%s: Could not read adapter factory MAC address!\n", dev->name); |
| 17522 | + if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, |
| 17523 | + &data) != DFX_K_SUCCESS) { |
| 17524 | + printk("%s: Could not read adapter factory MAC address!\n", |
| 17525 | + print_name); |
| 17526 | return(DFX_K_FAILURE); |
| 17527 | - } |
| 17528 | + } |
| 17529 | memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); |
| 17530 | |
| 17531 | - if (dfx_hw_port_ctrl_req(bp, |
| 17532 | - PI_PCTRL_M_MLA, |
| 17533 | - PI_PDATA_A_MLA_K_HI, |
| 17534 | - 0, |
| 17535 | - &data) != DFX_K_SUCCESS) |
| 17536 | - { |
| 17537 | - printk("%s: Could not read adapter factory MAC address!\n", dev->name); |
| 17538 | + if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, |
| 17539 | + &data) != DFX_K_SUCCESS) { |
| 17540 | + printk("%s: Could not read adapter factory MAC address!\n", |
| 17541 | + print_name); |
| 17542 | return(DFX_K_FAILURE); |
| 17543 | - } |
| 17544 | + } |
| 17545 | memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); |
| 17546 | |
| 17547 | /* |
| 17548 | @@ -867,28 +959,27 @@ static int __devinit dfx_driver_init(str |
| 17549 | */ |
| 17550 | |
| 17551 | memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); |
| 17552 | - if (bp->bus_type == DFX_BUS_TYPE_EISA) |
| 17553 | - printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", |
| 17554 | - dev->name, |
| 17555 | - dev->base_addr, |
| 17556 | - dev->irq, |
| 17557 | - dev->dev_addr[0], |
| 17558 | - dev->dev_addr[1], |
| 17559 | - dev->dev_addr[2], |
| 17560 | - dev->dev_addr[3], |
| 17561 | - dev->dev_addr[4], |
| 17562 | - dev->dev_addr[5]); |
| 17563 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17564 | + printk("%s: DEFTA at addr = 0x%lX, IRQ = %d, " |
| 17565 | + "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", |
| 17566 | + print_name, dev->base_addr, dev->irq, |
| 17567 | + dev->dev_addr[0], dev->dev_addr[1], |
| 17568 | + dev->dev_addr[2], dev->dev_addr[3], |
| 17569 | + dev->dev_addr[4], dev->dev_addr[5]); |
| 17570 | + else if (bp->bus_type == DFX_BUS_TYPE_EISA) |
| 17571 | + printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, " |
| 17572 | + "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", |
| 17573 | + print_name, dev->base_addr, dev->irq, |
| 17574 | + dev->dev_addr[0], dev->dev_addr[1], |
| 17575 | + dev->dev_addr[2], dev->dev_addr[3], |
| 17576 | + dev->dev_addr[4], dev->dev_addr[5]); |
| 17577 | else |
| 17578 | - printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", |
| 17579 | - dev->name, |
| 17580 | - dev->base_addr, |
| 17581 | - dev->irq, |
| 17582 | - dev->dev_addr[0], |
| 17583 | - dev->dev_addr[1], |
| 17584 | - dev->dev_addr[2], |
| 17585 | - dev->dev_addr[3], |
| 17586 | - dev->dev_addr[4], |
| 17587 | - dev->dev_addr[5]); |
| 17588 | + printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, " |
| 17589 | + "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", |
| 17590 | + print_name, dev->base_addr, dev->irq, |
| 17591 | + dev->dev_addr[0], dev->dev_addr[1], |
| 17592 | + dev->dev_addr[2], dev->dev_addr[3], |
| 17593 | + dev->dev_addr[4], dev->dev_addr[5]); |
| 17594 | |
| 17595 | /* |
| 17596 | * Get memory for descriptor block, consumer block, and other buffers |
| 17597 | @@ -903,14 +994,15 @@ static int __devinit dfx_driver_init(str |
| 17598 | #endif |
| 17599 | sizeof(PI_CONSUMER_BLOCK) + |
| 17600 | (PI_ALIGN_K_DESC_BLK - 1); |
| 17601 | - bp->kmalloced = top_v = (char *) kmalloc(alloc_size, GFP_KERNEL); |
| 17602 | - if (top_v == NULL) |
| 17603 | - { |
| 17604 | - printk("%s: Could not allocate memory for host buffers and structures!\n", dev->name); |
| 17605 | + bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size, |
| 17606 | + &bp->kmalloced_dma); |
| 17607 | + if (top_v == NULL) { |
| 17608 | + printk("%s: Could not allocate memory for host buffers " |
| 17609 | + "and structures!\n", print_name); |
| 17610 | return(DFX_K_FAILURE); |
| 17611 | - } |
| 17612 | + } |
| 17613 | memset(top_v, 0, alloc_size); /* zero out memory before continuing */ |
| 17614 | - top_p = virt_to_bus(top_v); /* get physical address of buffer */ |
| 17615 | + top_p = bp->kmalloced_dma; /* get physical address of buffer */ |
| 17616 | |
| 17617 | /* |
| 17618 | * To guarantee the 8K alignment required for the descriptor block, 8K - 1 |
| 17619 | @@ -924,7 +1016,7 @@ static int __devinit dfx_driver_init(str |
| 17620 | * for allocating the needed memory. |
| 17621 | */ |
| 17622 | |
| 17623 | - curr_p = (u32) (ALIGN(top_p, PI_ALIGN_K_DESC_BLK)); |
| 17624 | + curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); |
| 17625 | curr_v = top_v + (curr_p - top_p); |
| 17626 | |
| 17627 | /* Reserve space for descriptor block */ |
| 17628 | @@ -965,14 +1057,20 @@ static int __devinit dfx_driver_init(str |
| 17629 | |
| 17630 | /* Display virtual and physical addresses if debug driver */ |
| 17631 | |
| 17632 | - DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys); |
| 17633 | - DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys); |
| 17634 | - DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); |
| 17635 | - DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys); |
| 17636 | - DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys); |
| 17637 | + DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", |
| 17638 | + print_name, |
| 17639 | + (long)bp->descr_block_virt, bp->descr_block_phys); |
| 17640 | + DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", |
| 17641 | + print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); |
| 17642 | + DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", |
| 17643 | + print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); |
| 17644 | + DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", |
| 17645 | + print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); |
| 17646 | + DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", |
| 17647 | + print_name, (long)bp->cons_block_virt, bp->cons_block_phys); |
| 17648 | |
| 17649 | return(DFX_K_SUCCESS); |
| 17650 | - } |
| 17651 | +} |
| 17652 | |
| 17653 | |
| 17654 | /* |
| 17655 | @@ -1218,7 +1316,9 @@ static int dfx_open(struct net_device *d |
| 17656 | |
| 17657 | /* Register IRQ - support shared interrupts by passing device ptr */ |
| 17658 | |
| 17659 | - ret = request_irq(dev->irq, (void *)dfx_interrupt, SA_SHIRQ, dev->name, dev); |
| 17660 | + ret = request_irq(dev->irq, (void *)dfx_interrupt, |
| 17661 | + (bp->bus_type == DFX_BUS_TYPE_TC) ? 0 : SA_SHIRQ, |
| 17662 | + dev->name, dev); |
| 17663 | if (ret) { |
| 17664 | printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); |
| 17665 | return ret; |
| 17666 | @@ -1737,7 +1837,7 @@ static void dfx_interrupt(int irq, void |
| 17667 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, |
| 17668 | (PFI_MODE_M_PDQ_INT_ENB + PFI_MODE_M_DMA_ENB)); |
| 17669 | } |
| 17670 | - else |
| 17671 | + else if (bp->bus_type == DFX_BUS_TYPE_EISA) |
| 17672 | { |
| 17673 | /* Disable interrupts at the ESIC */ |
| 17674 | |
| 17675 | @@ -1755,6 +1855,13 @@ static void dfx_interrupt(int irq, void |
| 17676 | tmp |= PI_CONFIG_STAT_0_M_INT_ENB; |
| 17677 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, tmp); |
| 17678 | } |
| 17679 | + else { |
| 17680 | + /* TC doesn't share interrupts so no need to disable them */ |
| 17681 | + |
| 17682 | + /* Call interrupt service routine for this adapter */ |
| 17683 | + |
| 17684 | + dfx_int_common(dev); |
| 17685 | + } |
| 17686 | |
| 17687 | spin_unlock(&bp->lock); |
| 17688 | } |
| 17689 | @@ -2663,12 +2770,12 @@ static int dfx_hw_dma_uninit(DFX_board_t |
| 17690 | |
| 17691 | static void my_skb_align(struct sk_buff *skb, int n) |
| 17692 | { |
| 17693 | - u32 x=(u32)skb->data; /* We only want the low bits .. */ |
| 17694 | - u32 v; |
| 17695 | + unsigned long x = (unsigned long)skb->data; |
| 17696 | + unsigned long v; |
| 17697 | |
| 17698 | - v=(x+n-1)&~(n-1); /* Where we want to be */ |
| 17699 | + v = ALIGN(x, n); /* Where we want to be */ |
| 17700 | |
| 17701 | - skb_reserve(skb, v-x); |
| 17702 | + skb_reserve(skb, v - x); |
| 17703 | } |
| 17704 | |
| 17705 | |
| 17706 | @@ -2745,7 +2852,10 @@ static int dfx_rcv_init(DFX_board_t *bp, |
| 17707 | */ |
| 17708 | |
| 17709 | my_skb_align(newskb, 128); |
| 17710 | - bp->descr_block_virt->rcv_data[i+j].long_1 = virt_to_bus(newskb->data); |
| 17711 | + bp->descr_block_virt->rcv_data[i + j].long_1 = |
| 17712 | + (u32)pci_map_single(bp->pci_dev, newskb->data, |
| 17713 | + NEW_SKB_SIZE, |
| 17714 | + PCI_DMA_FROMDEVICE); |
| 17715 | /* |
| 17716 | * p_rcv_buff_va is only used inside the |
| 17717 | * kernel so we put the skb pointer here. |
| 17718 | @@ -2859,9 +2969,17 @@ static void dfx_rcv_queue_process( |
| 17719 | |
| 17720 | my_skb_align(newskb, 128); |
| 17721 | skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; |
| 17722 | + pci_unmap_single(bp->pci_dev, |
| 17723 | + bp->descr_block_virt->rcv_data[entry].long_1, |
| 17724 | + NEW_SKB_SIZE, |
| 17725 | + PCI_DMA_FROMDEVICE); |
| 17726 | skb_reserve(skb, RCV_BUFF_K_PADDING); |
| 17727 | bp->p_rcv_buff_va[entry] = (char *)newskb; |
| 17728 | - bp->descr_block_virt->rcv_data[entry].long_1 = virt_to_bus(newskb->data); |
| 17729 | + bp->descr_block_virt->rcv_data[entry].long_1 = |
| 17730 | + (u32)pci_map_single(bp->pci_dev, |
| 17731 | + newskb->data, |
| 17732 | + NEW_SKB_SIZE, |
| 17733 | + PCI_DMA_FROMDEVICE); |
| 17734 | } else |
| 17735 | skb = NULL; |
| 17736 | } else |
| 17737 | @@ -2934,7 +3052,7 @@ static void dfx_rcv_queue_process( |
| 17738 | * is contained in a single physically contiguous buffer |
| 17739 | * in which the virtual address of the start of packet |
| 17740 | * (skb->data) can be converted to a physical address |
| 17741 | - * by using virt_to_bus(). |
| 17742 | + * by using pci_map_single(). |
| 17743 | * |
| 17744 | * Since the adapter architecture requires a three byte |
| 17745 | * packet request header to prepend the start of packet, |
| 17746 | @@ -3082,12 +3200,13 @@ static int dfx_xmt_queue_pkt( |
| 17747 | * skb->data. |
| 17748 | * 6. The physical address of the start of packet |
| 17749 | * can be determined from the virtual address |
| 17750 | - * by using virt_to_bus() and is only 32-bits |
| 17751 | + * by using pci_map_single() and is only 32-bits |
| 17752 | * wide. |
| 17753 | */ |
| 17754 | |
| 17755 | p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); |
| 17756 | - p_xmt_descr->long_1 = (u32) virt_to_bus(skb->data); |
| 17757 | + p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data, |
| 17758 | + skb->len, PCI_DMA_TODEVICE); |
| 17759 | |
| 17760 | /* |
| 17761 | * Verify that descriptor is actually available |
| 17762 | @@ -3171,6 +3290,7 @@ static int dfx_xmt_done(DFX_board_t *bp) |
| 17763 | { |
| 17764 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ |
| 17765 | PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ |
| 17766 | + u8 comp; /* local transmit completion index */ |
| 17767 | int freed = 0; /* buffers freed */ |
| 17768 | |
| 17769 | /* Service all consumed transmit frames */ |
| 17770 | @@ -3188,7 +3308,11 @@ static int dfx_xmt_done(DFX_board_t *bp) |
| 17771 | bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; |
| 17772 | |
| 17773 | /* Return skb to operating system */ |
| 17774 | - |
| 17775 | + comp = bp->rcv_xmt_reg.index.xmt_comp; |
| 17776 | + pci_unmap_single(bp->pci_dev, |
| 17777 | + bp->descr_block_virt->xmt_data[comp].long_1, |
| 17778 | + p_xmt_drv_descr->p_skb->len, |
| 17779 | + PCI_DMA_TODEVICE); |
| 17780 | dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); |
| 17781 | |
| 17782 | /* |
| 17783 | @@ -3297,6 +3421,7 @@ static void dfx_xmt_flush( DFX_board_t * |
| 17784 | { |
| 17785 | u32 prod_cons; /* rcv/xmt consumer block longword */ |
| 17786 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ |
| 17787 | + u8 comp; /* local transmit completion index */ |
| 17788 | |
| 17789 | /* Flush all outstanding transmit frames */ |
| 17790 | |
| 17791 | @@ -3307,7 +3432,11 @@ static void dfx_xmt_flush( DFX_board_t * |
| 17792 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); |
| 17793 | |
| 17794 | /* Return skb to operating system */ |
| 17795 | - |
| 17796 | + comp = bp->rcv_xmt_reg.index.xmt_comp; |
| 17797 | + pci_unmap_single(bp->pci_dev, |
| 17798 | + bp->descr_block_virt->xmt_data[comp].long_1, |
| 17799 | + p_xmt_drv_descr->p_skb->len, |
| 17800 | + PCI_DMA_TODEVICE); |
| 17801 | dev_kfree_skb(p_xmt_drv_descr->p_skb); |
| 17802 | |
| 17803 | /* Increment transmit error counter */ |
| 17804 | @@ -3337,12 +3466,36 @@ static void dfx_xmt_flush( DFX_board_t * |
| 17805 | |
| 17806 | static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev) |
| 17807 | { |
| 17808 | - DFX_board_t *bp = dev->priv; |
| 17809 | + DFX_board_t *bp = dev->priv; |
| 17810 | + unsigned long len; /* resource length */ |
| 17811 | + int alloc_size; /* total buffer size used */ |
| 17812 | |
| 17813 | + if (bp->bus_type == DFX_BUS_TYPE_TC) { |
| 17814 | + /* TURBOchannel board */ |
| 17815 | + len = PI_TC_K_CSR_LEN; |
| 17816 | + } else if (bp->bus_type == DFX_BUS_TYPE_EISA) { |
| 17817 | + /* EISA board */ |
| 17818 | + len = PI_ESIC_K_CSR_IO_LEN; |
| 17819 | + } else { |
| 17820 | + len = PFI_K_CSR_IO_LEN; |
| 17821 | + } |
| 17822 | unregister_netdev(dev); |
| 17823 | - release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN ); |
| 17824 | - if (bp->kmalloced) kfree(bp->kmalloced); |
| 17825 | - kfree(dev); |
| 17826 | + release_region(dev->base_addr, len); |
| 17827 | + |
| 17828 | + if (bp->bus_type == DFX_BUS_TYPE_TC) |
| 17829 | + release_tc_card(bp->slot); |
| 17830 | + |
| 17831 | + alloc_size = sizeof(PI_DESCR_BLOCK) + |
| 17832 | + PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + |
| 17833 | +#ifndef DYNAMIC_BUFFERS |
| 17834 | + (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + |
| 17835 | +#endif |
| 17836 | + sizeof(PI_CONSUMER_BLOCK) + |
| 17837 | + (PI_ALIGN_K_DESC_BLK - 1); |
| 17838 | + if (bp->kmalloced) |
| 17839 | + pci_free_consistent(pdev, alloc_size, bp->kmalloced, |
| 17840 | + bp->kmalloced_dma); |
| 17841 | + free_netdev(dev); |
| 17842 | } |
| 17843 | |
| 17844 | static void __devexit dfx_remove_one (struct pci_dev *pdev) |
| 17845 | @@ -3353,21 +3506,22 @@ static void __devexit dfx_remove_one (st |
| 17846 | pci_set_drvdata(pdev, NULL); |
| 17847 | } |
| 17848 | |
| 17849 | -static struct pci_device_id dfx_pci_tbl[] __devinitdata = { |
| 17850 | +static struct pci_device_id dfx_pci_tbl[] = { |
| 17851 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, }, |
| 17852 | { 0, } |
| 17853 | }; |
| 17854 | MODULE_DEVICE_TABLE(pci, dfx_pci_tbl); |
| 17855 | |
| 17856 | static struct pci_driver dfx_driver = { |
| 17857 | - name: "defxx", |
| 17858 | - probe: dfx_init_one, |
| 17859 | - remove: __devexit_p(dfx_remove_one), |
| 17860 | - id_table: dfx_pci_tbl, |
| 17861 | + .name = "defxx", |
| 17862 | + .probe = dfx_init_one, |
| 17863 | + .remove = __devexit_p(dfx_remove_one), |
| 17864 | + .id_table = dfx_pci_tbl, |
| 17865 | }; |
| 17866 | |
| 17867 | static int dfx_have_pci; |
| 17868 | static int dfx_have_eisa; |
| 17869 | +static int dfx_have_tc; |
| 17870 | |
| 17871 | |
| 17872 | static void __exit dfx_eisa_cleanup(void) |
| 17873 | @@ -3388,12 +3542,7 @@ static void __exit dfx_eisa_cleanup(void |
| 17874 | |
| 17875 | static int __init dfx_init(void) |
| 17876 | { |
| 17877 | - int rc_pci, rc_eisa; |
| 17878 | - |
| 17879 | -/* when a module, this is printed whether or not devices are found in probe */ |
| 17880 | -#ifdef MODULE |
| 17881 | - printk(version); |
| 17882 | -#endif |
| 17883 | + int rc_pci, rc_eisa, rc_tc; |
| 17884 | |
| 17885 | rc_pci = pci_module_init(&dfx_driver); |
| 17886 | if (rc_pci >= 0) dfx_have_pci = 1; |
| 17887 | @@ -3401,20 +3550,27 @@ static int __init dfx_init(void) |
| 17888 | rc_eisa = dfx_eisa_init(); |
| 17889 | if (rc_eisa >= 0) dfx_have_eisa = 1; |
| 17890 | |
| 17891 | - return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci); |
| 17892 | + rc_tc = dfx_tc_init(); |
| 17893 | + if (rc_tc >= 0) dfx_have_tc = 1; |
| 17894 | + |
| 17895 | + return ((rc_tc < 0) ? 0 : rc_tc) + |
| 17896 | + ((rc_eisa < 0) ? 0 : rc_eisa) + |
| 17897 | + ((rc_pci < 0) ? 0 : rc_pci); |
| 17898 | } |
| 17899 | |
| 17900 | static void __exit dfx_cleanup(void) |
| 17901 | { |
| 17902 | if (dfx_have_pci) |
| 17903 | pci_unregister_driver(&dfx_driver); |
| 17904 | - if (dfx_have_eisa) |
| 17905 | + if (dfx_have_eisa || dfx_have_tc) |
| 17906 | dfx_eisa_cleanup(); |
| 17907 | - |
| 17908 | } |
| 17909 | |
| 17910 | module_init(dfx_init); |
| 17911 | module_exit(dfx_cleanup); |
| 17912 | +MODULE_AUTHOR("Lawrence V. Stefani"); |
| 17913 | +MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver " |
| 17914 | + DRV_VERSION " " DRV_RELDATE); |
| 17915 | MODULE_LICENSE("GPL"); |
| 17916 | |
| 17917 | |
| 17918 | --- a/drivers/net/defxx.h |
| 17919 | +++ b/drivers/net/defxx.h |
| 17920 | @@ -12,17 +12,11 @@ |
| 17921 | * Contains all definitions specified by port specification and required |
| 17922 | * by the defxx.c driver. |
| 17923 | * |
| 17924 | - * Maintainers: |
| 17925 | - * LVS Lawrence V. Stefani |
| 17926 | - * |
| 17927 | - * Contact: |
| 17928 | - * The author may be reached at: |
| 17929 | + * The original author: |
| 17930 | + * LVS Lawrence V. Stefani <lstefani@yahoo.com> |
| 17931 | * |
| 17932 | - * Inet: stefani@lkg.dec.com |
| 17933 | - * Mail: Digital Equipment Corporation |
| 17934 | - * 550 King Street |
| 17935 | - * M/S: LKG1-3/M07 |
| 17936 | - * Littleton, MA 01460 |
| 17937 | + * Maintainers: |
| 17938 | + * macro Maciej W. Rozycki <macro@linux-mips.org> |
| 17939 | * |
| 17940 | * Modification History: |
| 17941 | * Date Name Description |
| 17942 | @@ -30,6 +24,7 @@ |
| 17943 | * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O |
| 17944 | * macros to DEFXX.C. |
| 17945 | * 12-Sep-96 LVS Removed packet request header pointers. |
| 17946 | + * 04 Aug 2003 macro Converted to the DMA API. |
| 17947 | */ |
| 17948 | |
| 17949 | #ifndef _DEFXX_H_ |
| 17950 | @@ -1467,6 +1462,11 @@ typedef union |
| 17951 | |
| 17952 | #endif /* #ifndef BIG_ENDIAN */ |
| 17953 | |
| 17954 | +/* Define TC PDQ CSR offset and length */ |
| 17955 | + |
| 17956 | +#define PI_TC_K_CSR_OFFSET 0x100000 |
| 17957 | +#define PI_TC_K_CSR_LEN 0x80 /* 128 bytes */ |
| 17958 | + |
| 17959 | /* Define EISA controller register offsets */ |
| 17960 | |
| 17961 | #define PI_ESIC_K_BURST_HOLDOFF 0x040 |
| 17962 | @@ -1634,6 +1634,7 @@ typedef union |
| 17963 | |
| 17964 | #define DFX_BUS_TYPE_PCI 0 /* type code for DEC FDDIcontroller/PCI */ |
| 17965 | #define DFX_BUS_TYPE_EISA 1 /* type code for DEC FDDIcontroller/EISA */ |
| 17966 | +#define DFX_BUS_TYPE_TC 2 /* type code for DEC FDDIcontroller/TURBOchannel */ |
| 17967 | |
| 17968 | #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */ |
| 17969 | #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */ |
| 17970 | @@ -1704,17 +1705,19 @@ typedef struct DFX_board_tag |
| 17971 | { |
| 17972 | /* Keep virtual and physical pointers to locked, physically contiguous memory */ |
| 17973 | |
| 17974 | - char *kmalloced; /* kfree this on unload */ |
| 17975 | + char *kmalloced; /* pci_free_consistent this on unload */ |
| 17976 | + dma_addr_t kmalloced_dma; |
| 17977 | + /* DMA handle for the above */ |
| 17978 | PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */ |
| 17979 | - u32 descr_block_phys; /* PDQ descriptor block phys address */ |
| 17980 | + dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */ |
| 17981 | PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */ |
| 17982 | - u32 cmd_req_phys; /* Command request buffer phys address */ |
| 17983 | + dma_addr_t cmd_req_phys; /* Command request buffer phys address */ |
| 17984 | PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */ |
| 17985 | - u32 cmd_rsp_phys; /* Command response buffer phys address */ |
| 17986 | + dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */ |
| 17987 | char *rcv_block_virt; /* LLC host receive queue buf blk virt */ |
| 17988 | - u32 rcv_block_phys; /* LLC host receive queue buf blk phys */ |
| 17989 | + dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */ |
| 17990 | PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */ |
| 17991 | - u32 cons_block_phys; /* PDQ consumer block phys address */ |
| 17992 | + dma_addr_t cons_block_phys; /* PDQ consumer block phys address */ |
| 17993 | |
| 17994 | /* Keep local copies of Type 1 and Type 2 register data */ |
| 17995 | |
| 17996 | @@ -1758,8 +1761,9 @@ typedef struct DFX_board_tag |
| 17997 | |
| 17998 | struct net_device *dev; /* pointer to device structure */ |
| 17999 | struct net_device *next; |
| 18000 | - u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */ |
| 18001 | - u16 base_addr; /* base I/O address (same as dev->base_addr) */ |
| 18002 | + u32 bus_type; /* bus type (0 == PCI, 1 == EISA, 2 == TC) */ |
| 18003 | + long base_addr; /* base I/O address (same as dev->base_addr) */ |
| 18004 | + int slot; /* TC slot number */ |
| 18005 | struct pci_dev * pci_dev; |
| 18006 | u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */ |
| 18007 | u32 req_ttrt; /* requested TTRT value (in 80ns units) */ |
| 18008 | --- a/drivers/net/hamradio/hdlcdrv.c |
| 18009 | +++ b/drivers/net/hamradio/hdlcdrv.c |
| 18010 | @@ -587,6 +587,8 @@ static int hdlcdrv_close(struct net_devi |
| 18011 | return -EINVAL; |
| 18012 | s = (struct hdlcdrv_state *)dev->priv; |
| 18013 | |
| 18014 | + netif_stop_queue(dev); |
| 18015 | + |
| 18016 | if (s->ops && s->ops->close) |
| 18017 | i = s->ops->close(dev); |
| 18018 | if (s->skb) |
| 18019 | --- a/drivers/net/irda/au1k_ir.c |
| 18020 | +++ b/drivers/net/irda/au1k_ir.c |
| 18021 | @@ -81,10 +81,6 @@ static char version[] __devinitdata = |
| 18022 | |
| 18023 | #define RUN_AT(x) (jiffies + (x)) |
| 18024 | |
| 18025 | -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) |
| 18026 | -static BCSR * const bcsr = (BCSR *)0xAE000000; |
| 18027 | -#endif |
| 18028 | - |
| 18029 | static spinlock_t ir_lock = SPIN_LOCK_UNLOCKED; |
| 18030 | |
| 18031 | /* |
| 18032 | --- a/drivers/net/sgiseeq.c |
| 18033 | +++ b/drivers/net/sgiseeq.c |
| 18034 | @@ -24,16 +24,16 @@ |
| 18035 | #include <asm/io.h> |
| 18036 | #include <asm/system.h> |
| 18037 | #include <asm/bitops.h> |
| 18038 | +#include <asm/paccess.h> |
| 18039 | #include <asm/page.h> |
| 18040 | #include <asm/pgtable.h> |
| 18041 | +#include <asm/sgi/mc.h> |
| 18042 | #include <asm/sgi/hpc3.h> |
| 18043 | #include <asm/sgi/ip22.h> |
| 18044 | #include <asm/sgialib.h> |
| 18045 | |
| 18046 | #include "sgiseeq.h" |
| 18047 | |
| 18048 | -static char *version = "sgiseeq.c: David S. Miller (dm@engr.sgi.com)\n"; |
| 18049 | - |
| 18050 | static char *sgiseeqstr = "SGI Seeq8003"; |
| 18051 | |
| 18052 | /* |
| 18053 | @@ -113,9 +113,9 @@ static struct net_device *root_sgiseeq_d |
| 18054 | |
| 18055 | static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs) |
| 18056 | { |
| 18057 | - hregs->rx_reset = HPC3_ERXRST_CRESET | HPC3_ERXRST_CLRIRQ; |
| 18058 | + hregs->reset = HPC3_ERST_CRESET | HPC3_ERST_CLRIRQ; |
| 18059 | udelay(20); |
| 18060 | - hregs->rx_reset = 0; |
| 18061 | + hregs->reset = 0; |
| 18062 | } |
| 18063 | |
| 18064 | static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs, |
| 18065 | @@ -238,7 +238,6 @@ void sgiseeq_dump_rings(void) |
| 18066 | |
| 18067 | #define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF) |
| 18068 | #define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2) |
| 18069 | -#define RDMACFG_INIT (HPC3_ERXDCFG_FRXDC | HPC3_ERXDCFG_FEOP | HPC3_ERXDCFG_FIRQ) |
| 18070 | |
| 18071 | static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp, |
| 18072 | struct sgiseeq_regs *sregs) |
| 18073 | @@ -260,8 +259,6 @@ static int init_seeq(struct net_device * |
| 18074 | sregs->tstat = TSTAT_INIT_SEEQ; |
| 18075 | } |
| 18076 | |
| 18077 | - hregs->rx_dconfig |= RDMACFG_INIT; |
| 18078 | - |
| 18079 | hregs->rx_ndptr = PHYSADDR(&sp->srings.rx_desc[0]); |
| 18080 | hregs->tx_ndptr = PHYSADDR(&sp->srings.tx_desc[0]); |
| 18081 | |
| 18082 | @@ -432,7 +429,7 @@ static void sgiseeq_interrupt(int irq, v |
| 18083 | spin_lock(&sp->tx_lock); |
| 18084 | |
| 18085 | /* Ack the IRQ and set software state. */ |
| 18086 | - hregs->rx_reset = HPC3_ERXRST_CLRIRQ; |
| 18087 | + hregs->reset = HPC3_ERST_CLRIRQ; |
| 18088 | |
| 18089 | /* Always check for received packets. */ |
| 18090 | sgiseeq_rx(dev, sp, hregs, sregs); |
| 18091 | @@ -616,7 +613,7 @@ static inline void setup_rx_ring(struct |
| 18092 | |
| 18093 | #define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf)) |
| 18094 | |
| 18095 | -int sgiseeq_init(struct hpc3_regs* regs, int irq) |
| 18096 | +int sgiseeq_init(struct hpc3_regs* hpcregs, int irq, int has_eeprom) |
| 18097 | { |
| 18098 | struct net_device *dev; |
| 18099 | struct sgiseeq_private *sp; |
| 18100 | @@ -629,7 +626,7 @@ int sgiseeq_init(struct hpc3_regs* regs, |
| 18101 | goto err_out; |
| 18102 | } |
| 18103 | /* Make private data page aligned */ |
| 18104 | - sp = (struct sgiseeq_private *) get_zeroed_page(GFP_KERNEL); |
| 18105 | + sp = (struct sgiseeq_private *) get_zeroed_page(GFP_KERNEL); |
| 18106 | if (!sp) { |
| 18107 | printk(KERN_ERR "Sgiseeq: Page alloc failed, aborting.\n"); |
| 18108 | err = -ENOMEM; |
| 18109 | @@ -644,7 +641,9 @@ int sgiseeq_init(struct hpc3_regs* regs, |
| 18110 | |
| 18111 | #define EADDR_NVOFS 250 |
| 18112 | for (i = 0; i < 3; i++) { |
| 18113 | - unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i); |
| 18114 | + unsigned short tmp = has_eeprom ? |
| 18115 | + ip22_eeprom_read(&hpcregs->eeprom, EADDR_NVOFS / 2+i) : |
| 18116 | + ip22_nvram_read(EADDR_NVOFS / 2+i); |
| 18117 | |
| 18118 | dev->dev_addr[2 * i] = tmp >> 8; |
| 18119 | dev->dev_addr[2 * i + 1] = tmp & 0xff; |
| 18120 | @@ -654,8 +653,8 @@ int sgiseeq_init(struct hpc3_regs* regs, |
| 18121 | gpriv = sp; |
| 18122 | gdev = dev; |
| 18123 | #endif |
| 18124 | - sp->sregs = (struct sgiseeq_regs *) &hpc3c0->eth_ext[0]; |
| 18125 | - sp->hregs = &hpc3c0->ethregs; |
| 18126 | + sp->sregs = (struct sgiseeq_regs *) &hpcregs->eth_ext[0]; |
| 18127 | + sp->hregs = &hpcregs->ethregs; |
| 18128 | sp->name = sgiseeqstr; |
| 18129 | sp->mode = SEEQ_RCMD_RBCAST; |
| 18130 | |
| 18131 | @@ -672,6 +671,11 @@ int sgiseeq_init(struct hpc3_regs* regs, |
| 18132 | setup_rx_ring(sp->srings.rx_desc, SEEQ_RX_BUFFERS); |
| 18133 | setup_tx_ring(sp->srings.tx_desc, SEEQ_TX_BUFFERS); |
| 18134 | |
| 18135 | + /* Setup PIO and DMA transfer timing */ |
| 18136 | + sp->hregs->pconfig = 0x161; |
| 18137 | + sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP | |
| 18138 | + HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026; |
| 18139 | + |
| 18140 | /* Reset the chip. */ |
| 18141 | hpc3_eth_reset(sp->hregs); |
| 18142 | |
| 18143 | @@ -699,7 +703,7 @@ int sgiseeq_init(struct hpc3_regs* regs, |
| 18144 | goto err_out_free_irq; |
| 18145 | } |
| 18146 | |
| 18147 | - printk(KERN_INFO "%s: SGI Seeq8003 ", dev->name); |
| 18148 | + printk(KERN_INFO "%s: %s ", dev->name, sgiseeqstr); |
| 18149 | for (i = 0; i < 6; i++) |
| 18150 | printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':'); |
| 18151 | |
| 18152 | @@ -721,10 +725,22 @@ err_out: |
| 18153 | |
| 18154 | static int __init sgiseeq_probe(void) |
| 18155 | { |
| 18156 | - printk(version); |
| 18157 | + unsigned int tmp, ret1, ret2 = 0; |
| 18158 | |
| 18159 | /* On board adapter on 1st HPC is always present */ |
| 18160 | - return sgiseeq_init(hpc3c0, SGI_ENET_IRQ); |
| 18161 | + ret1 = sgiseeq_init(hpc3c0, SGI_ENET_IRQ, 0); |
| 18162 | + /* Let's see if second HPC is there */ |
| 18163 | + if (!(ip22_is_fullhouse()) && |
| 18164 | + get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]) == 0) { |
| 18165 | + sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | |
| 18166 | + SGIMC_GIOPAR_EXP164 | |
| 18167 | + SGIMC_GIOPAR_HPC264; |
| 18168 | + hpc3c1->pbus_piocfg[0][0] = 0x3ffff; |
| 18169 | + /* interrupt/config register on Challenge S Mezz board */ |
| 18170 | + hpc3c1->pbus_extregs[0][0] = 0x30; |
| 18171 | + ret2 = sgiseeq_init(hpc3c1, SGI_GIO_0_IRQ, 1); |
| 18172 | + } |
| 18173 | + return (ret1 & ret2) ? ret1 : 0; |
| 18174 | } |
| 18175 | |
| 18176 | static void __exit sgiseeq_exit(void) |
| 18177 | @@ -747,4 +763,6 @@ static void __exit sgiseeq_exit(void) |
| 18178 | module_init(sgiseeq_probe); |
| 18179 | module_exit(sgiseeq_exit); |
| 18180 | |
| 18181 | +MODULE_DESCRIPTION("SGI Seeq 8003 driver"); |
| 18182 | +MODULE_AUTHOR("David S. Miller"); |
| 18183 | MODULE_LICENSE("GPL"); |
| 18184 | --- a/drivers/pci/pci.c |
| 18185 | +++ b/drivers/pci/pci.c |
| 18186 | @@ -1281,11 +1281,17 @@ static int __devinit pci_scan_bridge(str |
| 18187 | { |
| 18188 | unsigned int buses; |
| 18189 | unsigned short cr; |
| 18190 | + unsigned short bctl; |
| 18191 | struct pci_bus *child; |
| 18192 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
| 18193 | |
| 18194 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
| 18195 | DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev->slot_name, buses & 0xffffff, pass); |
| 18196 | + /* Disable MasterAbortMode during probing to avoid reporting |
| 18197 | + of bus errors (in some architectures) */ |
| 18198 | + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
| 18199 | + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
| 18200 | + bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
| 18201 | if ((buses & 0xffff00) && !pcibios_assign_all_busses()) { |
| 18202 | /* |
| 18203 | * Bus already configured by firmware, process it in the first |
| 18204 | @@ -1351,6 +1357,7 @@ static int __devinit pci_scan_bridge(str |
| 18205 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
| 18206 | pci_write_config_word(dev, PCI_COMMAND, cr); |
| 18207 | } |
| 18208 | + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
| 18209 | sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number); |
| 18210 | return max; |
| 18211 | } |
| 18212 | --- a/drivers/pcmcia/au1000_db1x00.c |
| 18213 | +++ b/drivers/pcmcia/au1000_db1x00.c |
| 18214 | @@ -1,6 +1,6 @@ |
| 18215 | /* |
| 18216 | * |
| 18217 | - * Alchemy Semi Db1x00 boards specific pcmcia routines. |
| 18218 | + * AMD Alchemy DUAL-SLOT Db1x00 boards' specific pcmcia routines. |
| 18219 | * |
| 18220 | * Copyright 2002 MontaVista Software Inc. |
| 18221 | * Author: MontaVista Software, Inc. |
| 18222 | @@ -54,9 +54,20 @@ |
| 18223 | #include <asm/au1000.h> |
| 18224 | #include <asm/au1000_pcmcia.h> |
| 18225 | |
| 18226 | +#if defined(CONFIG_MIPS_PB1200) |
| 18227 | +#include <asm/pb1200.h> |
| 18228 | +#elif defined(CONFIG_MIPS_DB1200) |
| 18229 | +#include <asm/db1200.h> |
| 18230 | +#else |
| 18231 | #include <asm/db1x00.h> |
| 18232 | +#endif |
| 18233 | |
| 18234 | -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 18235 | +#define PCMCIA_MAX_SOCK 1 |
| 18236 | +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) |
| 18237 | + |
| 18238 | +/* VPP/VCC */ |
| 18239 | +#define SET_VCC_VPP(VCC, VPP, SLOT)\ |
| 18240 | + ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) |
| 18241 | |
| 18242 | static int db1x00_pcmcia_init(struct pcmcia_init *init) |
| 18243 | { |
| 18244 | @@ -76,7 +87,7 @@ static int |
| 18245 | db1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state) |
| 18246 | { |
| 18247 | u32 inserted; |
| 18248 | - unsigned char vs; |
| 18249 | + u16 vs; |
| 18250 | |
| 18251 | if(sock > PCMCIA_MAX_SOCK) return -1; |
| 18252 | |
| 18253 | @@ -87,11 +98,11 @@ db1x00_pcmcia_socket_state(unsigned sock |
| 18254 | |
| 18255 | if (sock == 0) { |
| 18256 | vs = bcsr->status & 0x3; |
| 18257 | - inserted = !(bcsr->status & (1<<4)); |
| 18258 | + inserted = BOARD_CARD_INSERTED(0); |
| 18259 | } |
| 18260 | else { |
| 18261 | vs = (bcsr->status & 0xC)>>2; |
| 18262 | - inserted = !(bcsr->status & (1<<5)); |
| 18263 | + inserted = BOARD_CARD_INSERTED(1); |
| 18264 | } |
| 18265 | |
| 18266 | DEBUG(KERN_DEBUG "db1x00 socket %d: inserted %d, vs %d\n", |
| 18267 | @@ -144,16 +155,9 @@ static int db1x00_pcmcia_get_irq_info(st |
| 18268 | if(info->sock > PCMCIA_MAX_SOCK) return -1; |
| 18269 | |
| 18270 | if(info->sock == 0) |
| 18271 | -#ifdef CONFIG_MIPS_DB1550 |
| 18272 | - info->irq = AU1000_GPIO_3; |
| 18273 | + info->irq = BOARD_PC0_INT; |
| 18274 | else |
| 18275 | - info->irq = AU1000_GPIO_5; |
| 18276 | -#else |
| 18277 | - info->irq = AU1000_GPIO_2; |
| 18278 | - else |
| 18279 | - info->irq = AU1000_GPIO_5; |
| 18280 | -#endif |
| 18281 | - |
| 18282 | + info->irq = BOARD_PC1_INT; |
| 18283 | return 0; |
| 18284 | } |
| 18285 | |
| 18286 | --- a/drivers/pcmcia/Config.in |
| 18287 | +++ b/drivers/pcmcia/Config.in |
| 18288 | @@ -30,16 +30,14 @@ if [ "$CONFIG_PCMCIA" != "n" ]; then |
| 18289 | dep_tristate ' M8xx support' CONFIG_PCMCIA_M8XX $CONFIG_PCMCIA |
| 18290 | fi |
| 18291 | if [ "$CONFIG_SOC_AU1X00" = "y" ]; then |
| 18292 | - dep_tristate ' Au1x00 PCMCIA support' CONFIG_PCMCIA_AU1X00 $CONFIG_PCMCIA |
| 18293 | - if [ "$CONFIG_PCMCIA_AU1X00" != "n" ]; then |
| 18294 | - bool ' Pb1x00 board support' CONFIG_PCMCIA_PB1X00 |
| 18295 | - bool ' Db1x00 board support' CONFIG_PCMCIA_DB1X00 |
| 18296 | - bool ' XXS1500 board support' CONFIG_PCMCIA_XXS1500 |
| 18297 | - fi |
| 18298 | + dep_tristate ' Au1x00 PCMCIA support' CONFIG_PCMCIA_AU1X00 $CONFIG_PCMCIA |
| 18299 | fi |
| 18300 | if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then |
| 18301 | dep_bool ' SiByte PCMCIA support' CONFIG_PCMCIA_SIBYTE $CONFIG_PCMCIA $CONFIG_BLK_DEV_IDE_SIBYTE |
| 18302 | fi |
| 18303 | + if [ "$CONFIG_VRC4171" = "y" -o "$CONFIG_VRC4171" = "m" ]; then |
| 18304 | + dep_tristate ' NEC VRC4171 Card Controllers support' CONFIG_PCMCIA_VRC4171 $CONFIG_PCMCIA |
| 18305 | + fi |
| 18306 | if [ "$CONFIG_VRC4173" = "y" -o "$CONFIG_VRC4173" = "m" ]; then |
| 18307 | dep_tristate ' NEC VRC4173 CARDU support' CONFIG_PCMCIA_VRC4173 $CONFIG_PCMCIA |
| 18308 | fi |
| 18309 | --- a/drivers/pcmcia/Makefile |
| 18310 | +++ b/drivers/pcmcia/Makefile |
| 18311 | @@ -61,9 +61,18 @@ endif |
| 18312 | |
| 18313 | obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o |
| 18314 | au1000_ss-objs-y := au1000_generic.o |
| 18315 | -au1000_ss-objs-$(CONFIG_PCMCIA_PB1X00) += au1000_pb1x00.o |
| 18316 | -au1000_ss-objs-$(CONFIG_PCMCIA_DB1X00) += au1000_db1x00.o |
| 18317 | -au1000_ss-objs-$(CONFIG_PCMCIA_XXS1500) += au1000_xxs1500.o |
| 18318 | +au1000_ss-objs-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o |
| 18319 | +au1000_ss-objs-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o |
| 18320 | +au1000_ss-objs-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o |
| 18321 | +au1000_ss-objs-$(CONFIG_MIPS_PB1550) += au1000_pb1550.o |
| 18322 | +au1000_ss-objs-$(CONFIG_MIPS_PB1200) += au1000_db1x00.o |
| 18323 | +au1000_ss-objs-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o |
| 18324 | +au1000_ss-objs-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o |
| 18325 | +au1000_ss-objs-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o |
| 18326 | +au1000_ss-objs-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o |
| 18327 | +au1000_ss-objs-$(CONFIG_MIPS_DB1200) += au1000_db1x00.o |
| 18328 | +au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o |
| 18329 | +au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o |
| 18330 | |
| 18331 | obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o |
| 18332 | obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o |
| 18333 | @@ -89,6 +98,7 @@ sa1100_cs-objs-$(CONFIG_SA1100_STORK) + |
| 18334 | sa1100_cs-objs-$(CONFIG_SA1100_XP860) += sa1100_xp860.o sa1111_generic.o |
| 18335 | sa1100_cs-objs-$(CONFIG_SA1100_YOPY) += sa1100_yopy.o |
| 18336 | |
| 18337 | +obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o |
| 18338 | obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o |
| 18339 | |
| 18340 | include $(TOPDIR)/Rules.make |
| 18341 | --- /dev/null |
| 18342 | +++ b/drivers/pcmcia/vrc4171_card.c |
| 18343 | @@ -0,0 +1,886 @@ |
| 18344 | +/* |
| 18345 | + * vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services. |
| 18346 | + * |
| 18347 | + * Copyright (C) 2003 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> |
| 18348 | + * |
| 18349 | + * This program is free software; you can redistribute it and/or modify |
| 18350 | + * it under the terms of the GNU General Public License as published by |
| 18351 | + * the Free Software Foundation; either version 2 of the License, or |
| 18352 | + * (at your option) any later version. |
| 18353 | + * |
| 18354 | + * This program is distributed in the hope that it will be useful, |
| 18355 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18356 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18357 | + * GNU General Public License for more details. |
| 18358 | + * |
| 18359 | + * You should have received a copy of the GNU General Public License |
| 18360 | + * along with this program; if not, write to the Free Software |
| 18361 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18362 | + */ |
| 18363 | +#include <linux/init.h> |
| 18364 | +#include <linux/ioport.h> |
| 18365 | +#include <linux/irq.h> |
| 18366 | +#include <linux/module.h> |
| 18367 | +#include <linux/spinlock.h> |
| 18368 | +#include <linux/sched.h> |
| 18369 | +#include <linux/types.h> |
| 18370 | + |
| 18371 | +#include <asm/io.h> |
| 18372 | +#include <asm/vr41xx/vrc4171.h> |
| 18373 | + |
| 18374 | +#include <pcmcia/ss.h> |
| 18375 | + |
| 18376 | +#include "i82365.h" |
| 18377 | + |
| 18378 | +MODULE_DESCRIPTION("NEC VRC4171 Card Controllers driver for Socket Services"); |
| 18379 | +MODULE_AUTHOR("Yoichi Yuasa <yuasa@hh.iij4u.or.jp>"); |
| 18380 | +MODULE_LICENSE("GPL"); |
| 18381 | + |
| 18382 | +#define CARD_MAX_SLOTS 2 |
| 18383 | +#define CARD_SLOTA 0 |
| 18384 | +#define CARD_SLOTB 1 |
| 18385 | +#define CARD_SLOTB_OFFSET 0x40 |
| 18386 | + |
| 18387 | +#define CARD_MEM_START 0x10000000 |
| 18388 | +#define CARD_MEM_END 0x13ffffff |
| 18389 | +#define CARD_MAX_MEM_OFFSET 0x3ffffff |
| 18390 | +#define CARD_MAX_MEM_SPEED 1000 |
| 18391 | + |
| 18392 | +#define CARD_CONTROLLER_INDEX 0x03e0 |
| 18393 | +#define CARD_CONTROLLER_DATA 0x03e1 |
| 18394 | +#define CARD_CONTROLLER_SIZE 2 |
| 18395 | + /* Power register */ |
| 18396 | + #define VPP_GET_VCC 0x01 |
| 18397 | + #define POWER_ENABLE 0x10 |
| 18398 | + #define CARD_VOLTAGE_SENSE 0x1f |
| 18399 | + #define VCC_3VORXV_CAPABLE 0x00 |
| 18400 | + #define VCC_XV_ONLY 0x01 |
| 18401 | + #define VCC_3V_CAPABLE 0x02 |
| 18402 | + #define VCC_5V_ONLY 0x03 |
| 18403 | + #define CARD_VOLTAGE_SELECT 0x2f |
| 18404 | + #define VCC_3V 0x01 |
| 18405 | + #define VCC_5V 0x00 |
| 18406 | + #define VCC_XV 0x02 |
| 18407 | + #define VCC_STATUS_3V 0x02 |
| 18408 | + #define VCC_STATUS_5V 0x01 |
| 18409 | + #define VCC_STATUS_XV 0x03 |
| 18410 | + #define GLOBAL_CONTROL 0x1e |
| 18411 | + #define EXWRBK 0x04 |
| 18412 | + #define IRQPM_EN 0x08 |
| 18413 | + #define CLRPMIRQ 0x10 |
| 18414 | + |
| 18415 | +#define IO_MAX_MAPS 2 |
| 18416 | +#define MEM_MAX_MAPS 5 |
| 18417 | + |
| 18418 | +enum { |
| 18419 | + SLOTB_PROBE = 0, |
| 18420 | + SLOTB_NOPROBE_IO, |
| 18421 | + SLOTB_NOPROBE_MEM, |
| 18422 | + SLOTB_NOPROBE_ALL |
| 18423 | +}; |
| 18424 | + |
| 18425 | +typedef struct vrc4171_socket { |
| 18426 | + int noprobe; |
| 18427 | + void (*handler)(void *, unsigned int); |
| 18428 | + void *info; |
| 18429 | + socket_cap_t cap; |
| 18430 | + spinlock_t event_lock; |
| 18431 | + uint16_t events; |
| 18432 | + struct socket_info_t *pcmcia_socket; |
| 18433 | + struct tq_struct tq_task; |
| 18434 | + char name[24]; |
| 18435 | + int csc_irq; |
| 18436 | + int io_irq; |
| 18437 | +} vrc4171_socket_t; |
| 18438 | + |
| 18439 | +static vrc4171_socket_t vrc4171_sockets[CARD_MAX_SLOTS]; |
| 18440 | +static int vrc4171_slotb = SLOTB_IS_NONE; |
| 18441 | +static unsigned int vrc4171_irq; |
| 18442 | +static uint16_t vrc4171_irq_mask = 0xdeb8; |
| 18443 | + |
| 18444 | +extern struct socket_info_t *pcmcia_register_socket(int slot, |
| 18445 | + struct pccard_operations *vtable, |
| 18446 | + int use_bus_pm); |
| 18447 | +extern void pcmcia_unregister_socket(struct socket_info_t *s); |
| 18448 | + |
| 18449 | +static inline uint8_t exca_read_byte(int slot, uint8_t index) |
| 18450 | +{ |
| 18451 | + if (slot == CARD_SLOTB) |
| 18452 | + index += CARD_SLOTB_OFFSET; |
| 18453 | + |
| 18454 | + outb(index, CARD_CONTROLLER_INDEX); |
| 18455 | + return inb(CARD_CONTROLLER_DATA); |
| 18456 | +} |
| 18457 | + |
| 18458 | +static inline uint16_t exca_read_word(int slot, uint8_t index) |
| 18459 | +{ |
| 18460 | + uint16_t data; |
| 18461 | + |
| 18462 | + if (slot == CARD_SLOTB) |
| 18463 | + index += CARD_SLOTB_OFFSET; |
| 18464 | + |
| 18465 | + outb(index++, CARD_CONTROLLER_INDEX); |
| 18466 | + data = inb(CARD_CONTROLLER_DATA); |
| 18467 | + |
| 18468 | + outb(index, CARD_CONTROLLER_INDEX); |
| 18469 | + data |= ((uint16_t)inb(CARD_CONTROLLER_DATA)) << 8; |
| 18470 | + |
| 18471 | + return data; |
| 18472 | +} |
| 18473 | + |
| 18474 | +static inline uint8_t exca_write_byte(int slot, uint8_t index, uint8_t data) |
| 18475 | +{ |
| 18476 | + if (slot == CARD_SLOTB) |
| 18477 | + index += CARD_SLOTB_OFFSET; |
| 18478 | + |
| 18479 | + outb(index, CARD_CONTROLLER_INDEX); |
| 18480 | + outb(data, CARD_CONTROLLER_DATA); |
| 18481 | + |
| 18482 | + return data; |
| 18483 | +} |
| 18484 | + |
| 18485 | +static inline uint16_t exca_write_word(int slot, uint8_t index, uint16_t data) |
| 18486 | +{ |
| 18487 | + if (slot == CARD_SLOTB) |
| 18488 | + index += CARD_SLOTB_OFFSET; |
| 18489 | + |
| 18490 | + outb(index++, CARD_CONTROLLER_INDEX); |
| 18491 | + outb(data, CARD_CONTROLLER_DATA); |
| 18492 | + |
| 18493 | + outb(index, CARD_CONTROLLER_INDEX); |
| 18494 | + outb((uint8_t)(data >> 8), CARD_CONTROLLER_DATA); |
| 18495 | + |
| 18496 | + return data; |
| 18497 | +} |
| 18498 | + |
| 18499 | +static inline int search_nonuse_irq(void) |
| 18500 | +{ |
| 18501 | + int i; |
| 18502 | + |
| 18503 | + for (i = 0; i < 16; i++) { |
| 18504 | + if (vrc4171_irq_mask & (1 << i)) { |
| 18505 | + vrc4171_irq_mask &= ~(1 << i); |
| 18506 | + return i; |
| 18507 | + } |
| 18508 | + } |
| 18509 | + |
| 18510 | + return -1; |
| 18511 | +} |
| 18512 | + |
| 18513 | +static int pccard_init(unsigned int slot) |
| 18514 | +{ |
| 18515 | + vrc4171_socket_t *socket = &vrc4171_sockets[slot]; |
| 18516 | + |
| 18517 | + socket->cap.features |= SS_CAP_PCCARD | SS_CAP_PAGE_REGS; |
| 18518 | + socket->cap.irq_mask = 0; |
| 18519 | + socket->cap.pci_irq = vrc4171_irq; |
| 18520 | + socket->cap.map_size = 0x1000; |
| 18521 | + socket->events = 0; |
| 18522 | + spin_lock_init(socket->event_lock); |
| 18523 | + socket->csc_irq = search_nonuse_irq(); |
| 18524 | + socket->io_irq = search_nonuse_irq(); |
| 18525 | + |
| 18526 | + return 0; |
| 18527 | +} |
| 18528 | + |
| 18529 | +static int pccard_suspend(unsigned int slot) |
| 18530 | +{ |
| 18531 | + return -EINVAL; |
| 18532 | +} |
| 18533 | + |
| 18534 | +static int pccard_register_callback(unsigned int slot, |
| 18535 | + void (*handler)(void *, unsigned int), |
| 18536 | + void *info) |
| 18537 | +{ |
| 18538 | + vrc4171_socket_t *socket; |
| 18539 | + |
| 18540 | + if (slot >= CARD_MAX_SLOTS) |
| 18541 | + return -EINVAL; |
| 18542 | + |
| 18543 | + socket = &vrc4171_sockets[slot]; |
| 18544 | + |
| 18545 | + socket->handler = handler; |
| 18546 | + socket->info = info; |
| 18547 | + |
| 18548 | + if (handler) |
| 18549 | + MOD_INC_USE_COUNT; |
| 18550 | + else |
| 18551 | + MOD_DEC_USE_COUNT; |
| 18552 | + |
| 18553 | + return 0; |
| 18554 | +} |
| 18555 | + |
| 18556 | +static int pccard_inquire_socket(unsigned int slot, socket_cap_t *cap) |
| 18557 | +{ |
| 18558 | + vrc4171_socket_t *socket; |
| 18559 | + |
| 18560 | + if (slot >= CARD_MAX_SLOTS || cap == NULL) |
| 18561 | + return -EINVAL; |
| 18562 | + |
| 18563 | + socket = &vrc4171_sockets[slot]; |
| 18564 | + |
| 18565 | + *cap = socket->cap; |
| 18566 | + |
| 18567 | + return 0; |
| 18568 | +} |
| 18569 | + |
| 18570 | +static int pccard_get_status(unsigned int slot, u_int *value) |
| 18571 | +{ |
| 18572 | + uint8_t status, sense; |
| 18573 | + u_int val = 0; |
| 18574 | + |
| 18575 | + if (slot >= CARD_MAX_SLOTS || value == NULL) |
| 18576 | + return -EINVAL; |
| 18577 | + |
| 18578 | + status = exca_read_byte(slot, I365_STATUS); |
| 18579 | + if (exca_read_byte(slot, I365_INTCTL) & I365_PC_IOCARD) { |
| 18580 | + if (status & I365_CS_STSCHG) |
| 18581 | + val |= SS_STSCHG; |
| 18582 | + } else { |
| 18583 | + if (!(status & I365_CS_BVD1)) |
| 18584 | + val |= SS_BATDEAD; |
| 18585 | + else if ((status & (I365_CS_BVD1 | I365_CS_BVD2)) == I365_CS_BVD1) |
| 18586 | + val |= SS_BATWARN; |
| 18587 | + } |
| 18588 | + if ((status & I365_CS_DETECT) == I365_CS_DETECT) |
| 18589 | + val |= SS_DETECT; |
| 18590 | + if (status & I365_CS_WRPROT) |
| 18591 | + val |= SS_WRPROT; |
| 18592 | + if (status & I365_CS_READY) |
| 18593 | + val |= SS_READY; |
| 18594 | + if (status & I365_CS_POWERON) |
| 18595 | + val |= SS_POWERON; |
| 18596 | + |
| 18597 | + sense = exca_read_byte(slot, CARD_VOLTAGE_SENSE); |
| 18598 | + switch (sense) { |
| 18599 | + case VCC_3VORXV_CAPABLE: |
| 18600 | + val |= SS_3VCARD | SS_XVCARD; |
| 18601 | + break; |
| 18602 | + case VCC_XV_ONLY: |
| 18603 | + val |= SS_XVCARD; |
| 18604 | + break; |
| 18605 | + case VCC_3V_CAPABLE: |
| 18606 | + val |= SS_3VCARD; |
| 18607 | + break; |
| 18608 | + default: |
| 18609 | + /* 5V only */ |
| 18610 | + break; |
| 18611 | + } |
| 18612 | + |
| 18613 | + *value = val; |
| 18614 | + |
| 18615 | + return 0; |
| 18616 | +} |
| 18617 | + |
| 18618 | +static inline u_char get_Vcc_value(uint8_t voltage) |
| 18619 | +{ |
| 18620 | + switch (voltage) { |
| 18621 | + case VCC_STATUS_3V: |
| 18622 | + return 33; |
| 18623 | + case VCC_STATUS_5V: |
| 18624 | + return 50; |
| 18625 | + default: |
| 18626 | + break; |
| 18627 | + } |
| 18628 | + |
| 18629 | + return 0; |
| 18630 | +} |
| 18631 | + |
| 18632 | +static inline u_char get_Vpp_value(uint8_t power, u_char Vcc) |
| 18633 | +{ |
| 18634 | + if ((power & 0x03) == 0x01 || (power & 0x03) == 0x02) |
| 18635 | + return Vcc; |
| 18636 | + |
| 18637 | + return 0; |
| 18638 | +} |
| 18639 | + |
| 18640 | +static int pccard_get_socket(unsigned int slot, socket_state_t *state) |
| 18641 | +{ |
| 18642 | + vrc4171_socket_t *socket; |
| 18643 | + uint8_t power, voltage, control, cscint; |
| 18644 | + |
| 18645 | + if (slot >= CARD_MAX_SLOTS || state == NULL) |
| 18646 | + return -EINVAL; |
| 18647 | + |
| 18648 | + socket = &vrc4171_sockets[slot]; |
| 18649 | + |
| 18650 | + power = exca_read_byte(slot, I365_POWER); |
| 18651 | + voltage = exca_read_byte(slot, CARD_VOLTAGE_SELECT); |
| 18652 | + |
| 18653 | + state->Vcc = get_Vcc_value(voltage); |
| 18654 | + state->Vpp = get_Vpp_value(power, state->Vcc); |
| 18655 | + |
| 18656 | + state->flags = 0; |
| 18657 | + if (power & POWER_ENABLE) |
| 18658 | + state->flags |= SS_PWR_AUTO; |
| 18659 | + if (power & I365_PWR_OUT) |
| 18660 | + state->flags |= SS_OUTPUT_ENA; |
| 18661 | + |
| 18662 | + control = exca_read_byte(slot, I365_INTCTL); |
| 18663 | + if (control & I365_PC_IOCARD) |
| 18664 | + state->flags |= SS_IOCARD; |
| 18665 | + if (!(control & I365_PC_RESET)) |
| 18666 | + state->flags |= SS_RESET; |
| 18667 | + |
| 18668 | + cscint = exca_read_byte(slot, I365_CSCINT); |
| 18669 | + state->csc_mask = 0; |
| 18670 | + if (state->flags & SS_IOCARD) { |
| 18671 | + if (cscint & I365_CSC_STSCHG) |
| 18672 | + state->flags |= SS_STSCHG; |
| 18673 | + } else { |
| 18674 | + if (cscint & I365_CSC_BVD1) |
| 18675 | + state->csc_mask |= SS_BATDEAD; |
| 18676 | + if (cscint & I365_CSC_BVD2) |
| 18677 | + state->csc_mask |= SS_BATWARN; |
| 18678 | + } |
| 18679 | + if (cscint & I365_CSC_READY) |
| 18680 | + state->csc_mask |= SS_READY; |
| 18681 | + if (cscint & I365_CSC_DETECT) |
| 18682 | + state->csc_mask |= SS_DETECT; |
| 18683 | + |
| 18684 | + return 0; |
| 18685 | +} |
| 18686 | + |
| 18687 | +static inline uint8_t set_Vcc_value(u_char Vcc) |
| 18688 | +{ |
| 18689 | + switch (Vcc) { |
| 18690 | + case 33: |
| 18691 | + return VCC_3V; |
| 18692 | + case 50: |
| 18693 | + return VCC_5V; |
| 18694 | + } |
| 18695 | + |
| 18696 | + /* Small voltage is chosen for safety. */ |
| 18697 | + return VCC_3V; |
| 18698 | +} |
| 18699 | + |
| 18700 | +static int pccard_set_socket(unsigned int slot, socket_state_t *state) |
| 18701 | +{ |
| 18702 | + vrc4171_socket_t *socket; |
| 18703 | + uint8_t voltage, power, control, cscint; |
| 18704 | + |
| 18705 | + if (slot >= CARD_MAX_SLOTS || |
| 18706 | + (state->Vpp != state->Vcc && state->Vpp != 0) || |
| 18707 | + (state->Vcc != 50 && state->Vcc != 33 && state->Vcc != 0)) |
| 18708 | + return -EINVAL; |
| 18709 | + |
| 18710 | + socket = &vrc4171_sockets[slot]; |
| 18711 | + |
| 18712 | + spin_lock_irq(&socket->event_lock); |
| 18713 | + |
| 18714 | + voltage = set_Vcc_value(state->Vcc); |
| 18715 | + exca_write_byte(slot, CARD_VOLTAGE_SELECT, voltage); |
| 18716 | + |
| 18717 | + power = POWER_ENABLE; |
| 18718 | + if (state->Vpp == state->Vcc) |
| 18719 | + power |= VPP_GET_VCC; |
| 18720 | + if (state->flags & SS_OUTPUT_ENA) |
| 18721 | + power |= I365_PWR_OUT; |
| 18722 | + exca_write_byte(slot, I365_POWER, power); |
| 18723 | + |
| 18724 | + control = 0; |
| 18725 | + if (state->io_irq != 0) |
| 18726 | + control |= socket->io_irq; |
| 18727 | + if (state->flags & SS_IOCARD) |
| 18728 | + control |= I365_PC_IOCARD; |
| 18729 | + if (state->flags & SS_RESET) |
| 18730 | + control &= ~I365_PC_RESET; |
| 18731 | + else |
| 18732 | + control |= I365_PC_RESET; |
| 18733 | + exca_write_byte(slot, I365_INTCTL, control); |
| 18734 | + |
| 18735 | + cscint = 0; |
| 18736 | + exca_write_byte(slot, I365_CSCINT, cscint); |
| 18737 | + exca_read_byte(slot, I365_CSC); /* clear CardStatus change */ |
| 18738 | + if (state->csc_mask != 0) |
| 18739 | + cscint |= socket->csc_irq << 8; |
| 18740 | + if (state->flags & SS_IOCARD) { |
| 18741 | + if (state->csc_mask & SS_STSCHG) |
| 18742 | + cscint |= I365_CSC_STSCHG; |
| 18743 | + } else { |
| 18744 | + if (state->csc_mask & SS_BATDEAD) |
| 18745 | + cscint |= I365_CSC_BVD1; |
| 18746 | + if (state->csc_mask & SS_BATWARN) |
| 18747 | + cscint |= I365_CSC_BVD2; |
| 18748 | + } |
| 18749 | + if (state->csc_mask & SS_READY) |
| 18750 | + cscint |= I365_CSC_READY; |
| 18751 | + if (state->csc_mask & SS_DETECT) |
| 18752 | + cscint |= I365_CSC_DETECT; |
| 18753 | + exca_write_byte(slot, I365_CSCINT, cscint); |
| 18754 | + |
| 18755 | + spin_unlock_irq(&socket->event_lock); |
| 18756 | + |
| 18757 | + return 0; |
| 18758 | +} |
| 18759 | + |
| 18760 | +static int pccard_get_io_map(unsigned int slot, struct pccard_io_map *io) |
| 18761 | +{ |
| 18762 | + vrc4171_socket_t *socket; |
| 18763 | + uint8_t ioctl, addrwin; |
| 18764 | + u_char map; |
| 18765 | + |
| 18766 | + if (slot >= CARD_MAX_SLOTS || io == NULL || |
| 18767 | + io->map >= IO_MAX_MAPS) |
| 18768 | + return -EINVAL; |
| 18769 | + |
| 18770 | + socket = &vrc4171_sockets[slot]; |
| 18771 | + map = io->map; |
| 18772 | + |
| 18773 | + io->start = exca_read_word(slot, I365_IO(map)+I365_W_START); |
| 18774 | + io->stop = exca_read_word(slot, I365_IO(map)+I365_W_STOP); |
| 18775 | + |
| 18776 | + ioctl = exca_read_byte(slot, I365_IOCTL); |
| 18777 | + if (io->flags & I365_IOCTL_WAIT(map)) |
| 18778 | + io->speed = 1; |
| 18779 | + else |
| 18780 | + io->speed = 0; |
| 18781 | + |
| 18782 | + io->flags = 0; |
| 18783 | + if (ioctl & I365_IOCTL_16BIT(map)) |
| 18784 | + io->flags |= MAP_16BIT; |
| 18785 | + if (ioctl & I365_IOCTL_IOCS16(map)) |
| 18786 | + io->flags |= MAP_AUTOSZ; |
| 18787 | + if (ioctl & I365_IOCTL_0WS(map)) |
| 18788 | + io->flags |= MAP_0WS; |
| 18789 | + |
| 18790 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 18791 | + if (addrwin & I365_ENA_IO(map)) |
| 18792 | + io->flags |= MAP_ACTIVE; |
| 18793 | + |
| 18794 | + return 0; |
| 18795 | +} |
| 18796 | + |
| 18797 | +static int pccard_set_io_map(unsigned int slot, struct pccard_io_map *io) |
| 18798 | +{ |
| 18799 | + vrc4171_socket_t *socket; |
| 18800 | + uint8_t ioctl, addrwin; |
| 18801 | + u_char map; |
| 18802 | + |
| 18803 | + if (slot >= CARD_MAX_SLOTS || |
| 18804 | + io == NULL || io->map >= IO_MAX_MAPS || |
| 18805 | + io->start > 0xffff || io->stop > 0xffff || io->start > io->stop) |
| 18806 | + return -EINVAL; |
| 18807 | + |
| 18808 | + socket = &vrc4171_sockets[slot]; |
| 18809 | + map = io->map; |
| 18810 | + |
| 18811 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 18812 | + if (addrwin & I365_ENA_IO(map)) { |
| 18813 | + addrwin &= ~I365_ENA_IO(map); |
| 18814 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 18815 | + } |
| 18816 | + |
| 18817 | + exca_write_word(slot, I365_IO(map)+I365_W_START, io->start); |
| 18818 | + exca_write_word(slot, I365_IO(map)+I365_W_STOP, io->stop); |
| 18819 | + |
| 18820 | + ioctl = 0; |
| 18821 | + if (io->speed > 0) |
| 18822 | + ioctl |= I365_IOCTL_WAIT(map); |
| 18823 | + if (io->flags & MAP_16BIT) |
| 18824 | + ioctl |= I365_IOCTL_16BIT(map); |
| 18825 | + if (io->flags & MAP_AUTOSZ) |
| 18826 | + ioctl |= I365_IOCTL_IOCS16(map); |
| 18827 | + if (io->flags & MAP_0WS) |
| 18828 | + ioctl |= I365_IOCTL_0WS(map); |
| 18829 | + exca_write_byte(slot, I365_IOCTL, ioctl); |
| 18830 | + |
| 18831 | + if (io->flags & MAP_ACTIVE) { |
| 18832 | + addrwin |= I365_ENA_IO(map); |
| 18833 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 18834 | + } |
| 18835 | + |
| 18836 | + return 0; |
| 18837 | +} |
| 18838 | + |
| 18839 | +static int pccard_get_mem_map(unsigned int slot, struct pccard_mem_map *mem) |
| 18840 | +{ |
| 18841 | + vrc4171_socket_t *socket; |
| 18842 | + uint8_t addrwin; |
| 18843 | + u_long start, stop; |
| 18844 | + u_int offset; |
| 18845 | + u_char map; |
| 18846 | + |
| 18847 | + if (slot >= CARD_MAX_SLOTS || mem == NULL || mem->map >= MEM_MAX_MAPS) |
| 18848 | + return -EINVAL; |
| 18849 | + |
| 18850 | + socket = &vrc4171_sockets[slot]; |
| 18851 | + map = mem->map; |
| 18852 | + |
| 18853 | + mem->flags = 0; |
| 18854 | + mem->speed = 0; |
| 18855 | + |
| 18856 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 18857 | + if (addrwin & I365_ENA_MEM(map)) |
| 18858 | + mem->flags |= MAP_ACTIVE; |
| 18859 | + |
| 18860 | + start = exca_read_word(slot, I365_MEM(map)+I365_W_START); |
| 18861 | + if (start & I365_MEM_16BIT) |
| 18862 | + mem->flags |= MAP_16BIT; |
| 18863 | + mem->sys_start = (start & 0x3fffUL) << 12; |
| 18864 | + |
| 18865 | + stop = exca_read_word(slot, I365_MEM(map)+I365_W_STOP); |
| 18866 | + if (start & I365_MEM_WS0) |
| 18867 | + mem->speed += 1; |
| 18868 | + if (start & I365_MEM_WS1) |
| 18869 | + mem->speed += 2; |
| 18870 | + mem->sys_stop = ((stop & 0x3fffUL) << 12) + 0xfffUL; |
| 18871 | + |
| 18872 | + offset = exca_read_word(slot, I365_MEM(map)+I365_W_OFF); |
| 18873 | + if (offset & I365_MEM_REG) |
| 18874 | + mem->flags |= MAP_ATTRIB; |
| 18875 | + if (offset & I365_MEM_WRPROT) |
| 18876 | + mem->flags |= MAP_WRPROT; |
| 18877 | + mem->card_start = (offset & 0x3fffUL) << 12; |
| 18878 | + |
| 18879 | + mem->sys_start += CARD_MEM_START; |
| 18880 | + mem->sys_stop += CARD_MEM_START; |
| 18881 | + |
| 18882 | + return 0; |
| 18883 | +} |
| 18884 | + |
| 18885 | +static int pccard_set_mem_map(unsigned int slot, struct pccard_mem_map *mem) |
| 18886 | +{ |
| 18887 | + vrc4171_socket_t *socket; |
| 18888 | + uint16_t start, stop, offset; |
| 18889 | + uint8_t addrwin; |
| 18890 | + u_char map; |
| 18891 | + |
| 18892 | + if (slot >= CARD_MAX_SLOTS || |
| 18893 | + mem == NULL || mem->map >= MEM_MAX_MAPS || |
| 18894 | + mem->sys_start < CARD_MEM_START || mem->sys_start > CARD_MEM_END || |
| 18895 | + mem->sys_stop < CARD_MEM_START || mem->sys_stop > CARD_MEM_END || |
| 18896 | + mem->sys_start > mem->sys_stop || |
| 18897 | + mem->card_start > CARD_MAX_MEM_OFFSET || |
| 18898 | + mem->speed > CARD_MAX_MEM_SPEED) |
| 18899 | + return -EINVAL; |
| 18900 | + |
| 18901 | + socket = &vrc4171_sockets[slot]; |
| 18902 | + map = mem->map; |
| 18903 | + |
| 18904 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 18905 | + if (addrwin & I365_ENA_MEM(map)) { |
| 18906 | + addrwin &= ~I365_ENA_MEM(map); |
| 18907 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 18908 | + } |
| 18909 | + |
| 18910 | + start = (mem->sys_start >> 12) & 0x3fff; |
| 18911 | + if (mem->flags & MAP_16BIT) |
| 18912 | + start |= I365_MEM_16BIT; |
| 18913 | + exca_write_word(slot, I365_MEM(map)+I365_W_START, start); |
| 18914 | + |
| 18915 | + stop = (mem->sys_stop >> 12) & 0x3fff; |
| 18916 | + switch (mem->speed) { |
| 18917 | + case 0: |
| 18918 | + break; |
| 18919 | + case 1: |
| 18920 | + stop |= I365_MEM_WS0; |
| 18921 | + break; |
| 18922 | + case 2: |
| 18923 | + stop |= I365_MEM_WS1; |
| 18924 | + break; |
| 18925 | + default: |
| 18926 | + stop |= I365_MEM_WS0 | I365_MEM_WS1; |
| 18927 | + break; |
| 18928 | + } |
| 18929 | + exca_write_word(slot, I365_MEM(map)+I365_W_STOP, stop); |
| 18930 | + |
| 18931 | + offset = (mem->card_start >> 12) & 0x3fff; |
| 18932 | + if (mem->flags & MAP_ATTRIB) |
| 18933 | + offset |= I365_MEM_REG; |
| 18934 | + if (mem->flags & MAP_WRPROT) |
| 18935 | + offset |= I365_MEM_WRPROT; |
| 18936 | + exca_write_word(slot, I365_MEM(map)+I365_W_OFF, offset); |
| 18937 | + |
| 18938 | + if (mem->flags & MAP_ACTIVE) { |
| 18939 | + addrwin |= I365_ENA_MEM(map); |
| 18940 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 18941 | + } |
| 18942 | + |
| 18943 | + return 0; |
| 18944 | +} |
| 18945 | + |
| 18946 | +static void pccard_proc_setup(unsigned int slot, struct proc_dir_entry *base) |
| 18947 | +{ |
| 18948 | +} |
| 18949 | + |
| 18950 | +static struct pccard_operations vrc4171_pccard_operations = { |
| 18951 | + .init = pccard_init, |
| 18952 | + .suspend = pccard_suspend, |
| 18953 | + .register_callback = pccard_register_callback, |
| 18954 | + .inquire_socket = pccard_inquire_socket, |
| 18955 | + .get_status = pccard_get_status, |
| 18956 | + .get_socket = pccard_get_socket, |
| 18957 | + .set_socket = pccard_set_socket, |
| 18958 | + .get_io_map = pccard_get_io_map, |
| 18959 | + .set_io_map = pccard_set_io_map, |
| 18960 | + .get_mem_map = pccard_get_mem_map, |
| 18961 | + .set_mem_map = pccard_set_mem_map, |
| 18962 | + .proc_setup = pccard_proc_setup, |
| 18963 | +}; |
| 18964 | + |
| 18965 | +static void pccard_bh(void *data) |
| 18966 | +{ |
| 18967 | + vrc4171_socket_t *socket = (vrc4171_socket_t *)data; |
| 18968 | + uint16_t events; |
| 18969 | + |
| 18970 | + spin_lock_irq(&socket->event_lock); |
| 18971 | + events = socket->events; |
| 18972 | + socket->events = 0; |
| 18973 | + spin_unlock_irq(&socket->event_lock); |
| 18974 | + |
| 18975 | + if (socket->handler) |
| 18976 | + socket->handler(socket->info, events); |
| 18977 | +} |
| 18978 | + |
| 18979 | +static inline uint16_t get_events(int slot) |
| 18980 | +{ |
| 18981 | + uint16_t events = 0; |
| 18982 | + uint8_t status, csc; |
| 18983 | + |
| 18984 | + status = exca_read_byte(slot, I365_STATUS); |
| 18985 | + csc = exca_read_byte(slot, I365_CSC); |
| 18986 | + |
| 18987 | + if (exca_read_byte(slot, I365_INTCTL) & I365_PC_IOCARD) { |
| 18988 | + if ((csc & I365_CSC_STSCHG) && (status & I365_CS_STSCHG)) |
| 18989 | + events |= SS_STSCHG; |
| 18990 | + } else { |
| 18991 | + if (csc & (I365_CSC_BVD1 | I365_CSC_BVD2)) { |
| 18992 | + if (!(status & I365_CS_BVD1)) |
| 18993 | + events |= SS_BATDEAD; |
| 18994 | + else if ((status & (I365_CS_BVD1 | I365_CS_BVD2)) == I365_CS_BVD1) |
| 18995 | + events |= SS_BATWARN; |
| 18996 | + } |
| 18997 | + } |
| 18998 | + if ((csc & I365_CSC_READY) && (status & I365_CS_READY)) |
| 18999 | + events |= SS_READY; |
| 19000 | + if ((csc & I365_CSC_DETECT) && ((status & I365_CS_DETECT) == I365_CS_DETECT)) |
| 19001 | + events |= SS_DETECT; |
| 19002 | + |
| 19003 | + return events; |
| 19004 | +} |
| 19005 | + |
| 19006 | +static void pccard_status_change(int slot, vrc4171_socket_t *socket) |
| 19007 | +{ |
| 19008 | + uint16_t events; |
| 19009 | + |
| 19010 | + socket->tq_task.routine = pccard_bh; |
| 19011 | + socket->tq_task.data = socket; |
| 19012 | + |
| 19013 | + events = get_events(slot); |
| 19014 | + if (events) { |
| 19015 | + spin_lock(&socket->event_lock); |
| 19016 | + socket->events |= events; |
| 19017 | + spin_unlock(&socket->event_lock); |
| 19018 | + schedule_task(&socket->tq_task); |
| 19019 | + } |
| 19020 | +} |
| 19021 | + |
| 19022 | +static void pccard_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 19023 | +{ |
| 19024 | + vrc4171_socket_t *socket; |
| 19025 | + uint16_t status; |
| 19026 | + |
| 19027 | + status = vrc4171_get_irq_status(); |
| 19028 | + if (status & IRQ_A) { |
| 19029 | + socket = &vrc4171_sockets[CARD_SLOTA]; |
| 19030 | + if (socket->noprobe == SLOTB_PROBE) { |
| 19031 | + if (status & (1 << socket->csc_irq)) |
| 19032 | + pccard_status_change(CARD_SLOTA, socket); |
| 19033 | + } |
| 19034 | + } |
| 19035 | + |
| 19036 | + if (status & IRQ_B) { |
| 19037 | + socket = &vrc4171_sockets[CARD_SLOTB]; |
| 19038 | + if (socket->noprobe == SLOTB_PROBE) { |
| 19039 | + if (status & (1 << socket->csc_irq)) |
| 19040 | + pccard_status_change(CARD_SLOTB, socket); |
| 19041 | + } |
| 19042 | + } |
| 19043 | +} |
| 19044 | + |
| 19045 | +static inline void reserve_using_irq(int slot) |
| 19046 | +{ |
| 19047 | + unsigned int irq; |
| 19048 | + |
| 19049 | + irq = exca_read_byte(slot, I365_INTCTL); |
| 19050 | + irq &= 0x0f; |
| 19051 | + vrc4171_irq_mask &= ~(1 << irq); |
| 19052 | + |
| 19053 | + irq = exca_read_byte(slot, I365_CSCINT); |
| 19054 | + irq = (irq & 0xf0) >> 4; |
| 19055 | + vrc4171_irq_mask &= ~(1 << irq); |
| 19056 | +} |
| 19057 | + |
| 19058 | +static int __devinit vrc4171_add_socket(int slot) |
| 19059 | +{ |
| 19060 | + vrc4171_socket_t *socket; |
| 19061 | + |
| 19062 | + if (slot >= CARD_MAX_SLOTS) |
| 19063 | + return -EINVAL; |
| 19064 | + |
| 19065 | + socket = &vrc4171_sockets[slot]; |
| 19066 | + if (socket->noprobe != SLOTB_PROBE) { |
| 19067 | + uint8_t addrwin; |
| 19068 | + |
| 19069 | + switch (socket->noprobe) { |
| 19070 | + case SLOTB_NOPROBE_MEM: |
| 19071 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 19072 | + addrwin &= 0x1f; |
| 19073 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 19074 | + break; |
| 19075 | + case SLOTB_NOPROBE_IO: |
| 19076 | + addrwin = exca_read_byte(slot, I365_ADDRWIN); |
| 19077 | + addrwin &= 0xc0; |
| 19078 | + exca_write_byte(slot, I365_ADDRWIN, addrwin); |
| 19079 | + break; |
| 19080 | + default: |
| 19081 | + break; |
| 19082 | + } |
| 19083 | + |
| 19084 | + reserve_using_irq(slot); |
| 19085 | + |
| 19086 | + return 0; |
| 19087 | + } |
| 19088 | + |
| 19089 | + sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot); |
| 19090 | + |
| 19091 | + socket->pcmcia_socket = pcmcia_register_socket(slot, &vrc4171_pccard_operations, 1); |
| 19092 | + if (socket->pcmcia_socket == NULL) |
| 19093 | + return -ENOMEM; |
| 19094 | + |
| 19095 | + exca_write_byte(slot, I365_ADDRWIN, 0); |
| 19096 | + |
| 19097 | + exca_write_byte(slot, GLOBAL_CONTROL, 0); |
| 19098 | + |
| 19099 | + return 0; |
| 19100 | +} |
| 19101 | + |
| 19102 | +static void vrc4171_remove_socket(int slot) |
| 19103 | +{ |
| 19104 | + vrc4171_socket_t *socket; |
| 19105 | + |
| 19106 | + if (slot >= CARD_MAX_SLOTS) |
| 19107 | + return; |
| 19108 | + |
| 19109 | + socket = &vrc4171_sockets[slot]; |
| 19110 | + |
| 19111 | + if (socket->pcmcia_socket != NULL) { |
| 19112 | + pcmcia_unregister_socket(socket->pcmcia_socket); |
| 19113 | + socket->pcmcia_socket = NULL; |
| 19114 | + } |
| 19115 | +} |
| 19116 | + |
| 19117 | +static int __devinit vrc4171_card_setup(char *options) |
| 19118 | +{ |
| 19119 | + if (options == NULL || *options == '\0') |
| 19120 | + return 0; |
| 19121 | + |
| 19122 | + if (strncmp(options, "irq:", 4) == 0) { |
| 19123 | + int irq; |
| 19124 | + options += 4; |
| 19125 | + irq = simple_strtoul(options, &options, 0); |
| 19126 | + if (irq >= 0 && irq < NR_IRQS) |
| 19127 | + vrc4171_irq = irq; |
| 19128 | + |
| 19129 | + if (*options != ',') |
| 19130 | + return 0; |
| 19131 | + options++; |
| 19132 | + } |
| 19133 | + |
| 19134 | + if (strncmp(options, "slota:", 6) == 0) { |
| 19135 | + options += 6; |
| 19136 | + if (*options != '\0') { |
| 19137 | + if (strncmp(options, "noprobe", 7) == 0) { |
| 19138 | + vrc4171_sockets[CARD_SLOTA].noprobe = 1; |
| 19139 | + options += 7; |
| 19140 | + } |
| 19141 | + |
| 19142 | + if (*options != ',') |
| 19143 | + return 0; |
| 19144 | + options++; |
| 19145 | + } else |
| 19146 | + return 0; |
| 19147 | + |
| 19148 | + } |
| 19149 | + |
| 19150 | + if (strncmp(options, "slotb:", 6) == 0) { |
| 19151 | + options += 6; |
| 19152 | + if (*options != '\0') { |
| 19153 | + if (strncmp(options, "pccard", 6) == 0) { |
| 19154 | + vrc4171_slotb = SLOTB_IS_PCCARD; |
| 19155 | + options += 6; |
| 19156 | + } else if (strncmp(options, "cf", 2) == 0) { |
| 19157 | + vrc4171_slotb = SLOTB_IS_CF; |
| 19158 | + options += 2; |
| 19159 | + } else if (strncmp(options, "flashrom", 8) == 0) { |
| 19160 | + vrc4171_slotb = SLOTB_IS_FLASHROM; |
| 19161 | + options += 8; |
| 19162 | + } else if (strncmp(options, "none", 4) == 0) { |
| 19163 | + vrc4171_slotb = SLOTB_IS_NONE; |
| 19164 | + options += 4; |
| 19165 | + } |
| 19166 | + |
| 19167 | + if (*options != ',') |
| 19168 | + return 0; |
| 19169 | + options++; |
| 19170 | + |
| 19171 | + if ( strncmp(options, "memnoprobe", 10) == 0) |
| 19172 | + vrc4171_sockets[CARD_SLOTB].noprobe = SLOTB_NOPROBE_MEM; |
| 19173 | + if ( strncmp(options, "ionoprobe", 9) == 0) |
| 19174 | + vrc4171_sockets[CARD_SLOTB].noprobe = SLOTB_NOPROBE_IO; |
| 19175 | + if ( strncmp(options, "noprobe", 7) == 0) |
| 19176 | + vrc4171_sockets[CARD_SLOTB].noprobe = SLOTB_NOPROBE_ALL; |
| 19177 | + } |
| 19178 | + } |
| 19179 | + |
| 19180 | + return 0; |
| 19181 | +} |
| 19182 | + |
| 19183 | +__setup("vrc4171_card=", vrc4171_card_setup); |
| 19184 | + |
| 19185 | +static int __devinit vrc4171_card_init(void) |
| 19186 | +{ |
| 19187 | + int retval, slot; |
| 19188 | + |
| 19189 | + vrc4171_set_multifunction_pin(vrc4171_slotb); |
| 19190 | + |
| 19191 | + if (request_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE, |
| 19192 | + "NEC VRC4171 Card Controller") == NULL) |
| 19193 | + return -EBUSY; |
| 19194 | + |
| 19195 | + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) { |
| 19196 | + if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE) |
| 19197 | + break; |
| 19198 | + |
| 19199 | + retval = vrc4171_add_socket(slot); |
| 19200 | + if (retval != 0) |
| 19201 | + return retval; |
| 19202 | + } |
| 19203 | + |
| 19204 | + retval = request_irq(vrc4171_irq, pccard_interrupt, SA_SHIRQ, |
| 19205 | + "NEC VRC4171 Card Controller", vrc4171_sockets); |
| 19206 | + if (retval < 0) { |
| 19207 | + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) |
| 19208 | + vrc4171_remove_socket(slot); |
| 19209 | + |
| 19210 | + return retval; |
| 19211 | + } |
| 19212 | + |
| 19213 | + printk(KERN_INFO "NEC VRC4171 Card Controller, connected to IRQ %d\n", vrc4171_irq); |
| 19214 | + |
| 19215 | + return 0; |
| 19216 | +} |
| 19217 | + |
| 19218 | +static void __devexit vrc4171_card_exit(void) |
| 19219 | +{ |
| 19220 | + int slot; |
| 19221 | + |
| 19222 | + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) |
| 19223 | + vrc4171_remove_socket(slot); |
| 19224 | + |
| 19225 | + release_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE); |
| 19226 | +} |
| 19227 | + |
| 19228 | +module_init(vrc4171_card_init); |
| 19229 | +module_exit(vrc4171_card_exit); |
| 19230 | --- a/drivers/scsi/NCR53C9x.h |
| 19231 | +++ b/drivers/scsi/NCR53C9x.h |
| 19232 | @@ -144,12 +144,7 @@ |
| 19233 | |
| 19234 | #ifndef MULTIPLE_PAD_SIZES |
| 19235 | |
| 19236 | -#ifdef CONFIG_CPU_HAS_WB |
| 19237 | -#include <asm/wbflush.h> |
| 19238 | -#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0) |
| 19239 | -#else |
| 19240 | -#define esp_write(__reg, __val) ((__reg) = (__val)) |
| 19241 | -#endif |
| 19242 | +#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0) |
| 19243 | #define esp_read(__reg) (__reg) |
| 19244 | |
| 19245 | struct ESP_regs { |
| 19246 | --- a/drivers/sound/au1550_i2s.c |
| 19247 | +++ b/drivers/sound/au1550_i2s.c |
| 19248 | @@ -41,6 +41,7 @@ |
| 19249 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19250 | * |
| 19251 | */ |
| 19252 | + |
| 19253 | #include <linux/version.h> |
| 19254 | #include <linux/module.h> |
| 19255 | #include <linux/string.h> |
| 19256 | @@ -62,7 +63,45 @@ |
| 19257 | #include <asm/uaccess.h> |
| 19258 | #include <asm/hardirq.h> |
| 19259 | #include <asm/au1000.h> |
| 19260 | + |
| 19261 | +#if defined(CONFIG_SOC_AU1550) |
| 19262 | #include <asm/pb1550.h> |
| 19263 | +#endif |
| 19264 | + |
| 19265 | +#if defined(CONFIG_MIPS_PB1200) |
| 19266 | +#define WM8731 |
| 19267 | +#define WM_MODE_USB |
| 19268 | +#include <asm/pb1200.h> |
| 19269 | +#endif |
| 19270 | + |
| 19271 | +#if defined(CONFIG_MIPS_FICMMP) |
| 19272 | +#define WM8721 |
| 19273 | +#define WM_MODE_NORMAL |
| 19274 | +#include <asm/ficmmp.h> |
| 19275 | +#endif |
| 19276 | + |
| 19277 | + |
| 19278 | +#define WM_VOLUME_MIN 47 |
| 19279 | +#define WM_VOLUME_SCALE 80 |
| 19280 | + |
| 19281 | +#if defined(WM8731) |
| 19282 | + /* OSS interface to the wm i2s.. */ |
| 19283 | + #define CODEC_NAME "Wolfson WM8731 I2S" |
| 19284 | + #define WM_I2S_STEREO_MASK (SOUND_MASK_PCM | SOUND_MASK_LINE) |
| 19285 | + #define WM_I2S_SUPPORTED_MASK (WM_I2S_STEREO_MASK | SOUND_MASK_MIC) |
| 19286 | + #define WM_I2S_RECORD_MASK (SOUND_MASK_MIC | SOUND_MASK_LINE1 | SOUND_MASK_LINE) |
| 19287 | +#elif defined(WM8721) |
| 19288 | + #define CODEC_NAME "Wolfson WM8721 I2S" |
| 19289 | + #define WM_I2S_STEREO_MASK (SOUND_MASK_PCM) |
| 19290 | + #define WM_I2S_SUPPORTED_MASK (WM_I2S_STEREO_MASK) |
| 19291 | + #define WM_I2S_RECORD_MASK (0) |
| 19292 | +#endif |
| 19293 | + |
| 19294 | + |
| 19295 | +#define supported_mixer(FOO) ((FOO >= 0) && \ |
| 19296 | + (FOO < SOUND_MIXER_NRDEVICES) && \ |
| 19297 | + WM_I2S_SUPPORTED_MASK & (1<<FOO) ) |
| 19298 | + |
| 19299 | #include <asm/au1xxx_psc.h> |
| 19300 | #include <asm/au1xxx_dbdma.h> |
| 19301 | |
| 19302 | @@ -98,13 +137,51 @@ |
| 19303 | * 0 = no VRA, 1 = use VRA if codec supports it |
| 19304 | * The framework is here, but we currently force no VRA. |
| 19305 | */ |
| 19306 | +#if defined(CONFIG_MIPS_PB1200) | defined(CONFIG_MIPS_PB1550) |
| 19307 | static int vra = 0; |
| 19308 | +#elif defined(CONFIG_MIPS_FICMMP) |
| 19309 | +static int vra = 1; |
| 19310 | +#endif |
| 19311 | + |
| 19312 | +#define WM_REG_L_HEADPHONE_OUT 0x02 |
| 19313 | +#define WM_REG_R_HEADPHONE_OUT 0x03 |
| 19314 | +#define WM_REG_ANALOGUE_AUDIO_PATH_CTRL 0x04 |
| 19315 | +#define WM_REG_DIGITAL_AUDIO_PATH_CTRL 0x05 |
| 19316 | +#define WM_REG_POWER_DOWN_CTRL 0x06 |
| 19317 | +#define WM_REG_DIGITAL_AUDIO_IF 0x07 |
| 19318 | +#define WM_REG_SAMPLING_CONTROL 0x08 |
| 19319 | +#define WM_REG_ACTIVE_CTRL 0x09 |
| 19320 | +#define WM_REG_RESET 0x0F |
| 19321 | +#define WM_SC_SR_96000 (0x7<<2) |
| 19322 | +#define WM_SC_SR_88200 (0xF<<2) |
| 19323 | +#define WM_SC_SR_48000 (0x0<<2) |
| 19324 | +#define WM_SC_SR_44100 (0x8<<2) |
| 19325 | +#define WM_SC_SR_32000 (0x6<<2) |
| 19326 | +#define WM_SC_SR_8018 (0x9<<2) |
| 19327 | +#define WM_SC_SR_8000 (0x1<<2) |
| 19328 | +#define WM_SC_MODE_USB 1 |
| 19329 | +#define WM_SC_MODE_NORMAL 0 |
| 19330 | +#define WM_SC_BOSR_250FS (0<<1) |
| 19331 | +#define WM_SC_BOSR_272FS (1<<1) |
| 19332 | +#define WM_SC_BOSR_256FS (0<<1) |
| 19333 | +#define WM_SC_BOSR_128FS (0<<1) |
| 19334 | +#define WM_SC_BOSR_384FS (1<<1) |
| 19335 | +#define WM_SC_BOSR_192FS (1<<1) |
| 19336 | + |
| 19337 | +#define WS_64FS 31 |
| 19338 | +#define WS_96FS 47 |
| 19339 | +#define WS_128FS 63 |
| 19340 | +#define WS_192FS 95 |
| 19341 | + |
| 19342 | +#define MIN_Q_COUNT 2 |
| 19343 | + |
| 19344 | MODULE_PARM(vra, "i"); |
| 19345 | MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it"); |
| 19346 | |
| 19347 | static struct au1550_state { |
| 19348 | /* soundcore stuff */ |
| 19349 | int dev_audio; |
| 19350 | + int dev_mixer; |
| 19351 | |
| 19352 | spinlock_t lock; |
| 19353 | struct semaphore open_sem; |
| 19354 | @@ -114,6 +191,11 @@ static struct au1550_state { |
| 19355 | int no_vra; |
| 19356 | volatile psc_i2s_t *psc_addr; |
| 19357 | |
| 19358 | + int level_line; |
| 19359 | + int level_mic; |
| 19360 | + int level_left; |
| 19361 | + int level_right; |
| 19362 | + |
| 19363 | struct dmabuf { |
| 19364 | u32 dmanr; |
| 19365 | unsigned sample_rate; |
| 19366 | @@ -195,60 +277,224 @@ au1550_delay(int msec) |
| 19367 | } |
| 19368 | } |
| 19369 | |
| 19370 | -/* Just a place holder. The Wolfson codec is a write only device, |
| 19371 | - * so we would have to keep a local copy of the data. |
| 19372 | - */ |
| 19373 | -#if 0 |
| 19374 | -static u8 |
| 19375 | -rdcodec(u8 addr) |
| 19376 | -{ |
| 19377 | - return 0 /* data */; |
| 19378 | -} |
| 19379 | -#endif |
| 19380 | - |
| 19381 | - |
| 19382 | static void |
| 19383 | -wrcodec(u8 ctlreg, u8 val) |
| 19384 | +wrcodec(u8 ctlreg, u16 val) |
| 19385 | { |
| 19386 | int rcnt; |
| 19387 | extern int pb1550_wm_codec_write(u8 addr, u8 reg, u8 val); |
| 19388 | - |
| 19389 | /* The codec is a write only device, with a 16-bit control/data |
| 19390 | * word. Although it is written as two bytes on the I2C, the |
| 19391 | * format is actually 7 bits of register and 9 bits of data. |
| 19392 | * The ls bit of the first byte is the ms bit of the data. |
| 19393 | */ |
| 19394 | rcnt = 0; |
| 19395 | - while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1) |
| 19396 | - && (rcnt < 50)) { |
| 19397 | + while ((pb1550_wm_codec_write((0x36 >> 1), |
| 19398 | + (ctlreg << 1) | ((val >> 8) & 0x01), |
| 19399 | + (u8) (val & 0x00FF)) != 1) && |
| 19400 | + (rcnt < 50)) { |
| 19401 | rcnt++; |
| 19402 | -#if 0 |
| 19403 | - printk("Codec write retry %02x %02x\n", ctlreg, val); |
| 19404 | -#endif |
| 19405 | } |
| 19406 | + |
| 19407 | + au1550_delay(10); |
| 19408 | +} |
| 19409 | + |
| 19410 | +static int |
| 19411 | +au1550_open_mixdev(struct inode *inode, struct file *file) |
| 19412 | +{ |
| 19413 | + file->private_data = &au1550_state; |
| 19414 | + return 0; |
| 19415 | +} |
| 19416 | + |
| 19417 | +static int |
| 19418 | +au1550_release_mixdev(struct inode *inode, struct file *file) |
| 19419 | +{ |
| 19420 | + return 0; |
| 19421 | +} |
| 19422 | + |
| 19423 | +static int wm_i2s_read_mixer(struct au1550_state *s, int oss_channel) |
| 19424 | +{ |
| 19425 | + int ret = 0; |
| 19426 | + |
| 19427 | + if (WM_I2S_STEREO_MASK & (1 << oss_channel)) { |
| 19428 | + /* nice stereo mixers .. */ |
| 19429 | + |
| 19430 | + ret = s->level_left | (s->level_right << 8); |
| 19431 | + } else if (oss_channel == SOUND_MIXER_MIC) { |
| 19432 | + ret = 0; |
| 19433 | + /* TODO: Implement read mixer for input/output codecs */ |
| 19434 | + } |
| 19435 | + |
| 19436 | + return ret; |
| 19437 | } |
| 19438 | |
| 19439 | +static void wm_i2s_write_mixer(struct au1550_state *s, int oss_channel, unsigned int left, unsigned int right) |
| 19440 | +{ |
| 19441 | + if (WM_I2S_STEREO_MASK & (1 << oss_channel)) { |
| 19442 | + /* stereo mixers */ |
| 19443 | + s->level_left = left; |
| 19444 | + s->level_right = right; |
| 19445 | + |
| 19446 | + right = (right * WM_VOLUME_SCALE) / 100; |
| 19447 | + left = (left * WM_VOLUME_SCALE) / 100; |
| 19448 | + if (right > WM_VOLUME_SCALE) |
| 19449 | + right = WM_VOLUME_SCALE; |
| 19450 | + if (left > WM_VOLUME_SCALE) |
| 19451 | + left = WM_VOLUME_SCALE; |
| 19452 | + |
| 19453 | + right += WM_VOLUME_MIN; |
| 19454 | + left += WM_VOLUME_MIN; |
| 19455 | + |
| 19456 | + wrcodec(WM_REG_L_HEADPHONE_OUT, left); |
| 19457 | + wrcodec(WM_REG_R_HEADPHONE_OUT, right); |
| 19458 | + |
| 19459 | + }else if (oss_channel == SOUND_MIXER_MIC) { |
| 19460 | + /* TODO: implement write mixer for input/output codecs */ |
| 19461 | + } |
| 19462 | +} |
| 19463 | + |
| 19464 | +/* a thin wrapper for write_mixer */ |
| 19465 | +static void wm_i2s_set_mixer(struct au1550_state *s, unsigned int oss_mixer, unsigned int val ) |
| 19466 | +{ |
| 19467 | + unsigned int left,right; |
| 19468 | + |
| 19469 | + /* cleanse input a little */ |
| 19470 | + right = ((val >> 8) & 0xff) ; |
| 19471 | + left = (val & 0xff) ; |
| 19472 | + |
| 19473 | + if (right > 100) right = 100; |
| 19474 | + if (left > 100) left = 100; |
| 19475 | + |
| 19476 | + wm_i2s_write_mixer(s, oss_mixer, left, right); |
| 19477 | +} |
| 19478 | + |
| 19479 | +static int |
| 19480 | +au1550_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
| 19481 | +{ |
| 19482 | + struct au1550_state *s = (struct au1550_state *)file->private_data; |
| 19483 | + |
| 19484 | + int i, val = 0; |
| 19485 | + |
| 19486 | + if (cmd == SOUND_MIXER_INFO) { |
| 19487 | + mixer_info info; |
| 19488 | + strncpy(info.id, CODEC_NAME, sizeof(info.id)); |
| 19489 | + strncpy(info.name, CODEC_NAME, sizeof(info.name)); |
| 19490 | + info.modify_counter = 0; |
| 19491 | + if (copy_to_user((void *)arg, &info, sizeof(info))) |
| 19492 | + return -EFAULT; |
| 19493 | + return 0; |
| 19494 | + } |
| 19495 | + if (cmd == SOUND_OLD_MIXER_INFO) { |
| 19496 | + _old_mixer_info info; |
| 19497 | + strncpy(info.id, CODEC_NAME, sizeof(info.id)); |
| 19498 | + strncpy(info.name, CODEC_NAME, sizeof(info.name)); |
| 19499 | + if (copy_to_user((void *)arg, &info, sizeof(info))) |
| 19500 | + return -EFAULT; |
| 19501 | + return 0; |
| 19502 | + } |
| 19503 | + |
| 19504 | + if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) |
| 19505 | + return -EINVAL; |
| 19506 | + |
| 19507 | + if (cmd == OSS_GETVERSION) |
| 19508 | + return put_user(SOUND_VERSION, (int *)arg); |
| 19509 | + |
| 19510 | + if (_SIOC_DIR(cmd) == _SIOC_READ) { |
| 19511 | + switch (_IOC_NR(cmd)) { |
| 19512 | + case SOUND_MIXER_RECSRC: /* give them the current record src */ |
| 19513 | + val = 0; |
| 19514 | + /* |
| 19515 | + if (!codec->recmask_io) { |
| 19516 | + val = 0; |
| 19517 | + } else { |
| 19518 | + val = codec->recmask_io(codec, 1, 0); |
| 19519 | + }*/ |
| 19520 | + break; |
| 19521 | + |
| 19522 | + case SOUND_MIXER_DEVMASK: /* give them the supported mixers */ |
| 19523 | + val = WM_I2S_SUPPORTED_MASK; |
| 19524 | + break; |
| 19525 | + |
| 19526 | + case SOUND_MIXER_RECMASK: |
| 19527 | + /* Arg contains a bit for each supported recording |
| 19528 | + * source */ |
| 19529 | + val = WM_I2S_RECORD_MASK; |
| 19530 | + break; |
| 19531 | + |
| 19532 | + case SOUND_MIXER_STEREODEVS: |
| 19533 | + /* Mixer channels supporting stereo */ |
| 19534 | + val = WM_I2S_STEREO_MASK; |
| 19535 | + break; |
| 19536 | + |
| 19537 | + case SOUND_MIXER_CAPS: |
| 19538 | + val = SOUND_CAP_EXCL_INPUT; |
| 19539 | + break; |
| 19540 | + |
| 19541 | + default: /* read a specific mixer */ |
| 19542 | + i = _IOC_NR(cmd); |
| 19543 | + |
| 19544 | + if (!supported_mixer(i)) |
| 19545 | + return -EINVAL; |
| 19546 | + |
| 19547 | + val = wm_i2s_read_mixer(s, i); |
| 19548 | + break; |
| 19549 | + } |
| 19550 | + return put_user(val, (int *)arg); |
| 19551 | + } |
| 19552 | + |
| 19553 | + if (_SIOC_DIR(cmd) == (_SIOC_WRITE|_SIOC_READ)) { |
| 19554 | + if (get_user(val, (int *)arg)) |
| 19555 | + return -EFAULT; |
| 19556 | + |
| 19557 | + switch (_IOC_NR(cmd)) { |
| 19558 | + case SOUND_MIXER_RECSRC: |
| 19559 | + /* Arg contains a bit for each recording source */ |
| 19560 | + if (!WM_I2S_RECORD_MASK) |
| 19561 | + return -EINVAL; |
| 19562 | + if (!val) |
| 19563 | + return 0; |
| 19564 | + if (!(val &= WM_I2S_RECORD_MASK)) |
| 19565 | + return -EINVAL; |
| 19566 | + |
| 19567 | + return 0; |
| 19568 | + default: /* write a specific mixer */ |
| 19569 | + i = _IOC_NR(cmd); |
| 19570 | + |
| 19571 | + if (!supported_mixer(i)) |
| 19572 | + return -EINVAL; |
| 19573 | + |
| 19574 | + wm_i2s_set_mixer(s, i, val); |
| 19575 | + |
| 19576 | + return 0; |
| 19577 | + } |
| 19578 | +} |
| 19579 | + return -EINVAL; |
| 19580 | +} |
| 19581 | + |
| 19582 | +static loff_t |
| 19583 | +au1550_llseek(struct file *file, loff_t offset, int origin) |
| 19584 | +{ |
| 19585 | + return -ESPIPE; |
| 19586 | +} |
| 19587 | + |
| 19588 | +static /*const */ struct file_operations au1550_mixer_fops = { |
| 19589 | + owner:THIS_MODULE, |
| 19590 | + llseek:au1550_llseek, |
| 19591 | + ioctl:au1550_ioctl_mixdev, |
| 19592 | + open:au1550_open_mixdev, |
| 19593 | + release:au1550_release_mixdev, |
| 19594 | +}; |
| 19595 | + |
| 19596 | void |
| 19597 | -codec_init(void) |
| 19598 | +codec_init(struct au1550_state *s) |
| 19599 | { |
| 19600 | - wrcodec(0x1e, 0x00); /* Reset */ |
| 19601 | - au1550_delay(200); |
| 19602 | - wrcodec(0x0c, 0x00); /* Power up everything */ |
| 19603 | - au1550_delay(10); |
| 19604 | - wrcodec(0x12, 0x00); /* Deactivate codec */ |
| 19605 | - au1550_delay(10); |
| 19606 | - wrcodec(0x08, 0x10); /* Select DAC outputs to line out */ |
| 19607 | - au1550_delay(10); |
| 19608 | - wrcodec(0x0a, 0x00); /* Disable output mute */ |
| 19609 | - au1550_delay(10); |
| 19610 | - wrcodec(0x05, 0x70); /* lower output volume on headphone */ |
| 19611 | - au1550_delay(10); |
| 19612 | - wrcodec(0x0e, 0x02); /* Set slave, 16-bit, I2S modes */ |
| 19613 | - au1550_delay(10); |
| 19614 | - wrcodec(0x10, 0x01); /* 12MHz (USB), 250fs */ |
| 19615 | - au1550_delay(10); |
| 19616 | - wrcodec(0x12, 0x01); /* Activate codec */ |
| 19617 | - au1550_delay(10); |
| 19618 | + wrcodec(WM_REG_RESET, 0x00); /* Reset */ |
| 19619 | + wrcodec(WM_REG_POWER_DOWN_CTRL, 0x00); /* Power up everything */ |
| 19620 | + wrcodec(WM_REG_ACTIVE_CTRL, 0x00); /* Deactivate codec */ |
| 19621 | + wrcodec(WM_REG_ANALOGUE_AUDIO_PATH_CTRL, 0x10); /* Select DAC outputs to line out */ |
| 19622 | + wrcodec(WM_REG_DIGITAL_AUDIO_PATH_CTRL, 0x00); /* Disable output mute */ |
| 19623 | + wm_i2s_write_mixer(s, SOUND_MIXER_PCM, 74, 74); |
| 19624 | + wrcodec(WM_REG_DIGITAL_AUDIO_IF, 0x02); /* Set slave, 16-bit, I2S modes */ |
| 19625 | + wrcodec(WM_REG_ACTIVE_CTRL, 0x01); /* Activate codec */ |
| 19626 | } |
| 19627 | |
| 19628 | /* stop the ADC before calling */ |
| 19629 | @@ -256,27 +502,16 @@ static void |
| 19630 | set_adc_rate(struct au1550_state *s, unsigned rate) |
| 19631 | { |
| 19632 | struct dmabuf *adc = &s->dma_adc; |
| 19633 | - struct dmabuf *dac = &s->dma_dac; |
| 19634 | |
| 19635 | - if (s->no_vra) { |
| 19636 | - /* calc SRC factor |
| 19637 | - */ |
| 19638 | + #if defined(WM_MODE_USB) |
| 19639 | adc->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1; |
| 19640 | adc->sample_rate = SAMP_RATE / adc->src_factor; |
| 19641 | return; |
| 19642 | - } |
| 19643 | + #else |
| 19644 | + //TODO: Need code for normal mode |
| 19645 | + #endif |
| 19646 | |
| 19647 | adc->src_factor = 1; |
| 19648 | - |
| 19649 | - |
| 19650 | -#if 0 |
| 19651 | - rate = rate > SAMP_RATE ? SAMP_RATE : rate; |
| 19652 | - |
| 19653 | - wrcodec(0, 0); /* I don't yet know what to write here if we vra */ |
| 19654 | - |
| 19655 | - adc->sample_rate = rate; |
| 19656 | - dac->sample_rate = rate; |
| 19657 | -#endif |
| 19658 | } |
| 19659 | |
| 19660 | /* stop the DAC before calling */ |
| 19661 | @@ -284,26 +519,89 @@ static void |
| 19662 | set_dac_rate(struct au1550_state *s, unsigned rate) |
| 19663 | { |
| 19664 | struct dmabuf *dac = &s->dma_dac; |
| 19665 | - struct dmabuf *adc = &s->dma_adc; |
| 19666 | |
| 19667 | - if (s->no_vra) { |
| 19668 | - /* calc SRC factor |
| 19669 | - */ |
| 19670 | - dac->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1; |
| 19671 | - dac->sample_rate = SAMP_RATE / dac->src_factor; |
| 19672 | - return; |
| 19673 | + u16 sr, ws, div, bosr, mode; |
| 19674 | + volatile psc_i2s_t* ip = (volatile psc_i2s_t *)I2S_PSC_BASE; |
| 19675 | + u32 cfg; |
| 19676 | + |
| 19677 | + #if defined(CONFIG_MIPS_FICMMP) |
| 19678 | + rate = ficmmp_set_i2s_sample_rate(rate); |
| 19679 | + #endif |
| 19680 | + |
| 19681 | + switch(rate) |
| 19682 | + { |
| 19683 | + case 96000: |
| 19684 | + sr = WM_SC_SR_96000; |
| 19685 | + ws = WS_64FS; |
| 19686 | + div = PSC_I2SCFG_DIV2; |
| 19687 | + break; |
| 19688 | + case 88200: |
| 19689 | + sr = WM_SC_SR_88200; |
| 19690 | + ws = WS_64FS; |
| 19691 | + div = PSC_I2SCFG_DIV2; |
| 19692 | + break; |
| 19693 | + case 44100: |
| 19694 | + sr = WM_SC_SR_44100; |
| 19695 | + ws = WS_128FS; |
| 19696 | + div = PSC_I2SCFG_DIV2; |
| 19697 | + break; |
| 19698 | + case 48000: |
| 19699 | + sr = WM_SC_SR_48000; |
| 19700 | + ws = WS_128FS; |
| 19701 | + div = PSC_I2SCFG_DIV2; |
| 19702 | + break; |
| 19703 | + case 32000: |
| 19704 | + sr = WM_SC_SR_32000; |
| 19705 | + ws = WS_96FS; |
| 19706 | + div = PSC_I2SCFG_DIV4; |
| 19707 | + break; |
| 19708 | + case 8018: |
| 19709 | + sr = WM_SC_SR_8018; |
| 19710 | + ws = WS_128FS; |
| 19711 | + div = PSC_I2SCFG_DIV2; |
| 19712 | + break; |
| 19713 | + case 8000: |
| 19714 | + default: |
| 19715 | + sr = WM_SC_SR_8000; |
| 19716 | + ws = WS_96FS; |
| 19717 | + div = PSC_I2SCFG_DIV16; |
| 19718 | + break; |
| 19719 | } |
| 19720 | |
| 19721 | + #if defined(WM_MODE_USB) |
| 19722 | + mode = WM_SC_MODE_USB; |
| 19723 | + #else |
| 19724 | + mode = WM_SC_MODE_NORMAL; |
| 19725 | + #endif |
| 19726 | + |
| 19727 | + bosr = 0; |
| 19728 | + |
| 19729 | dac->src_factor = 1; |
| 19730 | + dac->sample_rate = rate; |
| 19731 | |
| 19732 | -#if 0 |
| 19733 | - rate = rate > SAMP_RATE ? SAMP_RATE : rate; |
| 19734 | + /* Deactivate codec */ |
| 19735 | + wrcodec(WM_REG_ACTIVE_CTRL, 0x00); |
| 19736 | |
| 19737 | - wrcodec(0, 0); /* I don't yet know what to write here if we vra */ |
| 19738 | + /* Disable I2S controller */ |
| 19739 | + ip->psc_i2scfg &= ~PSC_I2SCFG_DE_ENABLE; |
| 19740 | + /* Wait for device disabled */ |
| 19741 | + while ((ip->psc_i2sstat & PSC_I2SSTAT_DR) == 1); |
| 19742 | + |
| 19743 | + cfg = ip->psc_i2scfg; |
| 19744 | + /* Clear WS and DIVIDER values */ |
| 19745 | + cfg &= ~(PSC_I2SCFG_WS_MASK | PSC_I2SCFG_DIV_MASK); |
| 19746 | + cfg |= PSC_I2SCFG_WS(ws) | div; |
| 19747 | + /* Reconfigure and enable */ |
| 19748 | + ip->psc_i2scfg = cfg | PSC_I2SCFG_DE_ENABLE; |
| 19749 | |
| 19750 | - adc->sample_rate = rate; |
| 19751 | - dac->sample_rate = rate; |
| 19752 | -#endif |
| 19753 | + /* Wait for device enabled */ |
| 19754 | + while ((ip->psc_i2sstat & PSC_I2SSTAT_DR) == 0); |
| 19755 | + |
| 19756 | + /* Set appropriate sampling rate */ |
| 19757 | + wrcodec(WM_REG_SAMPLING_CONTROL, bosr | mode | sr); |
| 19758 | + |
| 19759 | + /* Activate codec */ |
| 19760 | + wrcodec(WM_REG_ACTIVE_CTRL, 0x01); |
| 19761 | } |
| 19762 | |
| 19763 | static void |
| 19764 | @@ -354,8 +652,7 @@ stop_adc(struct au1550_state *s) |
| 19765 | ip->psc_i2spcr = PSC_I2SPCR_RP; |
| 19766 | au_sync(); |
| 19767 | |
| 19768 | - /* Wait for Receive Busy to show disabled. |
| 19769 | - */ |
| 19770 | + /* Wait for Receive Busy to show disabled. */ |
| 19771 | do { |
| 19772 | stat = ip->psc_i2sstat; |
| 19773 | au_sync(); |
| 19774 | @@ -463,7 +760,6 @@ prog_dmabuf(struct au1550_state *s, stru |
| 19775 | if (db->num_channels == 1) |
| 19776 | db->cnt_factor *= 2; |
| 19777 | db->cnt_factor *= db->src_factor; |
| 19778 | - |
| 19779 | db->count = 0; |
| 19780 | db->dma_qcount = 0; |
| 19781 | db->nextIn = db->nextOut = db->rawbuf; |
| 19782 | @@ -546,12 +842,13 @@ dac_dma_interrupt(int irq, void *dev_id, |
| 19783 | if (i2s_stat & (PSC_I2SSTAT_TF | PSC_I2SSTAT_TR | PSC_I2SSTAT_TF)) |
| 19784 | dbg("I2S status = 0x%08x", i2s_stat); |
| 19785 | #endif |
| 19786 | + |
| 19787 | db->dma_qcount--; |
| 19788 | |
| 19789 | if (db->count >= db->fragsize) { |
| 19790 | - if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, |
| 19791 | - db->fragsize) == 0) { |
| 19792 | - err("qcount < 2 and no ring room!"); |
| 19793 | + if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, db->fragsize) == 0) |
| 19794 | + { |
| 19795 | + err("qcount < MIN_Q_COUNT and no ring room!"); |
| 19796 | } |
| 19797 | db->nextOut += db->fragsize; |
| 19798 | if (db->nextOut >= db->rawbuf + db->dmasize) |
| 19799 | @@ -606,65 +903,43 @@ adc_dma_interrupt(int irq, void *dev_id, |
| 19800 | |
| 19801 | } |
| 19802 | |
| 19803 | -static loff_t |
| 19804 | -au1550_llseek(struct file *file, loff_t offset, int origin) |
| 19805 | -{ |
| 19806 | - return -ESPIPE; |
| 19807 | -} |
| 19808 | - |
| 19809 | - |
| 19810 | -#if 0 |
| 19811 | -static int |
| 19812 | -au1550_open_mixdev(struct inode *inode, struct file *file) |
| 19813 | -{ |
| 19814 | - file->private_data = &au1550_state; |
| 19815 | - return 0; |
| 19816 | -} |
| 19817 | - |
| 19818 | -static int |
| 19819 | -au1550_release_mixdev(struct inode *inode, struct file *file) |
| 19820 | -{ |
| 19821 | - return 0; |
| 19822 | -} |
| 19823 | - |
| 19824 | -static int |
| 19825 | -mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, |
| 19826 | - unsigned long arg) |
| 19827 | -{ |
| 19828 | - return codec->mixer_ioctl(codec, cmd, arg); |
| 19829 | -} |
| 19830 | - |
| 19831 | -static int |
| 19832 | -au1550_ioctl_mixdev(struct inode *inode, struct file *file, |
| 19833 | - unsigned int cmd, unsigned long arg) |
| 19834 | -{ |
| 19835 | - struct au1550_state *s = (struct au1550_state *)file->private_data; |
| 19836 | - struct ac97_codec *codec = s->codec; |
| 19837 | - |
| 19838 | - return mixdev_ioctl(codec, cmd, arg); |
| 19839 | -} |
| 19840 | - |
| 19841 | -static /*const */ struct file_operations au1550_mixer_fops = { |
| 19842 | - owner:THIS_MODULE, |
| 19843 | - llseek:au1550_llseek, |
| 19844 | - ioctl:au1550_ioctl_mixdev, |
| 19845 | - open:au1550_open_mixdev, |
| 19846 | - release:au1550_release_mixdev, |
| 19847 | -}; |
| 19848 | -#endif |
| 19849 | - |
| 19850 | static int |
| 19851 | drain_dac(struct au1550_state *s, int nonblock) |
| 19852 | { |
| 19853 | unsigned long flags; |
| 19854 | int count, tmo; |
| 19855 | |
| 19856 | + struct dmabuf *db = &s->dma_dac; |
| 19857 | + |
| 19858 | + //DPRINTF(); |
| 19859 | if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped) |
| 19860 | return 0; |
| 19861 | |
| 19862 | for (;;) { |
| 19863 | spin_lock_irqsave(&s->lock, flags); |
| 19864 | - count = s->dma_dac.count; |
| 19865 | + count = db->count; |
| 19866 | + |
| 19867 | + /* Pad the ddma buffer with zeros if the amount remaining |
| 19868 | + * is not a multiple of fragsize */ |
| 19869 | + if(count % db->fragsize != 0) |
| 19870 | + { |
| 19871 | + int pad = db->fragsize - (count % db->fragsize); |
| 19872 | + char* bufptr = db->nextIn; |
| 19873 | + char* bufend = db->rawbuf + db->dmasize; |
| 19874 | + |
| 19875 | + if((bufend - bufptr) < pad) |
| 19876 | + printk("Error! ddma padding is bigger than available ring space!\n"); |
| 19877 | + else |
| 19878 | + { |
| 19879 | + memset((void*)bufptr, 0, pad); |
| 19880 | + count += pad; |
| 19881 | + db->nextIn += pad; |
| 19882 | + db->count += pad; |
| 19883 | + if (db->dma_qcount == 0) |
| 19884 | + start_dac(s); |
| 19885 | + db->dma_qcount++; |
| 19886 | + } |
| 19887 | + } |
| 19888 | spin_unlock_irqrestore(&s->lock, flags); |
| 19889 | if (count <= 0) |
| 19890 | break; |
| 19891 | @@ -672,9 +947,9 @@ drain_dac(struct au1550_state *s, int no |
| 19892 | break; |
| 19893 | if (nonblock) |
| 19894 | return -EBUSY; |
| 19895 | - tmo = 1000 * count / (s->no_vra ? |
| 19896 | - SAMP_RATE : s->dma_dac.sample_rate); |
| 19897 | + tmo = 1000 * count / s->dma_dac.sample_rate; |
| 19898 | tmo /= s->dma_dac.dma_bytes_per_sample; |
| 19899 | + |
| 19900 | au1550_delay(tmo); |
| 19901 | } |
| 19902 | if (signal_pending(current)) |
| 19903 | @@ -698,8 +973,7 @@ static inline s16 U8_TO_S16(u8 ch) |
| 19904 | * If interpolating (no VRA), duplicate every audio frame src_factor times. |
| 19905 | */ |
| 19906 | static int |
| 19907 | -translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf, |
| 19908 | - int dmacount) |
| 19909 | +translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf, int dmacount) |
| 19910 | { |
| 19911 | int sample, i; |
| 19912 | int interp_bytes_per_sample; |
| 19913 | @@ -737,11 +1011,12 @@ translate_from_user(struct dmabuf *db, c |
| 19914 | |
| 19915 | /* duplicate every audio frame src_factor times |
| 19916 | */ |
| 19917 | - for (i = 0; i < db->src_factor; i++) |
| 19918 | + for (i = 0; i < db->src_factor; i++) { |
| 19919 | memcpy(dmabuf, dmasample, db->dma_bytes_per_sample); |
| 19920 | + dmabuf += interp_bytes_per_sample; |
| 19921 | + } |
| 19922 | |
| 19923 | userbuf += db->user_bytes_per_sample; |
| 19924 | - dmabuf += interp_bytes_per_sample; |
| 19925 | } |
| 19926 | |
| 19927 | return num_samples * interp_bytes_per_sample; |
| 19928 | @@ -996,15 +1271,14 @@ au1550_write(struct file *file, const ch |
| 19929 | * on the dma queue. If the queue count reaches zero, |
| 19930 | * we know the dma has stopped. |
| 19931 | */ |
| 19932 | - while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) { |
| 19933 | + while ((db->dma_qcount < MIN_Q_COUNT) && (db->count >= db->fragsize)) { |
| 19934 | if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, |
| 19935 | db->fragsize) == 0) { |
| 19936 | - err("qcount < 2 and no ring room!"); |
| 19937 | + err("qcount < MIN_Q_COUNT and no ring room!"); |
| 19938 | } |
| 19939 | db->nextOut += db->fragsize; |
| 19940 | if (db->nextOut >= db->rawbuf + db->dmasize) |
| 19941 | db->nextOut -= db->dmasize; |
| 19942 | - db->count -= db->fragsize; |
| 19943 | db->total_bytes += db->dma_fragsize; |
| 19944 | if (db->dma_qcount == 0) |
| 19945 | start_dac(s); |
| 19946 | @@ -1017,7 +1291,6 @@ au1550_write(struct file *file, const ch |
| 19947 | buffer += usercnt; |
| 19948 | ret += usercnt; |
| 19949 | } /* while (count > 0) */ |
| 19950 | - |
| 19951 | out: |
| 19952 | up(&s->sem); |
| 19953 | out2: |
| 19954 | @@ -1371,9 +1644,6 @@ au1550_ioctl(struct inode *inode, struct |
| 19955 | s->dma_dac.cnt_factor; |
| 19956 | abinfo.fragstotal = s->dma_dac.numfrag; |
| 19957 | abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; |
| 19958 | -#ifdef AU1000_VERBOSE_DEBUG |
| 19959 | - dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments); |
| 19960 | -#endif |
| 19961 | return copy_to_user((void *) arg, &abinfo, |
| 19962 | sizeof(abinfo)) ? -EFAULT : 0; |
| 19963 | |
| 19964 | @@ -1536,13 +1806,9 @@ au1550_ioctl(struct inode *inode, struct |
| 19965 | case SNDCTL_DSP_SETSYNCRO: |
| 19966 | case SOUND_PCM_READ_FILTER: |
| 19967 | return -EINVAL; |
| 19968 | + default: break; |
| 19969 | } |
| 19970 | - |
| 19971 | -#if 0 |
| 19972 | - return mixdev_ioctl(s->codec, cmd, arg); |
| 19973 | -#else |
| 19974 | return 0; |
| 19975 | -#endif |
| 19976 | } |
| 19977 | |
| 19978 | |
| 19979 | @@ -1664,15 +1930,15 @@ static /*const */ struct file_operations |
| 19980 | MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com"); |
| 19981 | MODULE_DESCRIPTION("Au1550 Audio Driver"); |
| 19982 | |
| 19983 | +#if defined(WM_MODE_USB) |
| 19984 | /* Set up an internal clock for the PSC3. This will then get |
| 19985 | * driven out of the Au1550 as the master. |
| 19986 | */ |
| 19987 | static void |
| 19988 | intclk_setup(void) |
| 19989 | { |
| 19990 | - uint clk, rate, stat; |
| 19991 | - |
| 19992 | - /* Wire up Freq4 as a clock for the PSC3. |
| 19993 | + uint clk, rate; |
| 19994 | + /* Wire up Freq4 as a clock for the PSC. |
| 19995 | * We know SMBus uses Freq3. |
| 19996 | * By making changes to this rate, plus the word strobe |
| 19997 | * size, we can make fine adjustments to the actual data rate. |
| 19998 | @@ -1700,11 +1966,17 @@ intclk_setup(void) |
| 19999 | */ |
| 20000 | clk = au_readl(SYS_CLKSRC); |
| 20001 | au_sync(); |
| 20002 | +#if defined(CONFIG_SOC_AU1550) |
| 20003 | clk &= ~0x01f00000; |
| 20004 | clk |= (6 << 22); |
| 20005 | +#elif defined(CONFIG_SOC_AU1200) |
| 20006 | + clk &= ~0x3e000000; |
| 20007 | + clk |= (6 << 27); |
| 20008 | +#endif |
| 20009 | au_writel(clk, SYS_CLKSRC); |
| 20010 | au_sync(); |
| 20011 | } |
| 20012 | +#endif |
| 20013 | |
| 20014 | static int __devinit |
| 20015 | au1550_probe(void) |
| 20016 | @@ -1724,6 +1996,11 @@ au1550_probe(void) |
| 20017 | init_MUTEX(&s->open_sem); |
| 20018 | spin_lock_init(&s->lock); |
| 20019 | |
| 20020 | + /* CPLD Mux for I2s */ |
| 20021 | + |
| 20022 | +#if defined(CONFIG_MIPS_PB1200) |
| 20023 | + bcsr->resets |= BCSR_RESETS_PCS1MUX; |
| 20024 | +#endif |
| 20025 | |
| 20026 | s->psc_addr = (volatile psc_i2s_t *)I2S_PSC_BASE; |
| 20027 | ip = s->psc_addr; |
| 20028 | @@ -1765,9 +2042,8 @@ au1550_probe(void) |
| 20029 | |
| 20030 | if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0) |
| 20031 | goto err_dev1; |
| 20032 | -#if 0 |
| 20033 | - if ((s->codec->dev_mixer = |
| 20034 | - register_sound_mixer(&au1550_mixer_fops, -1)) < 0) |
| 20035 | +#if 1 |
| 20036 | + if ((s->dev_mixer = register_sound_mixer(&au1550_mixer_fops, -1)) < 0) |
| 20037 | goto err_dev2; |
| 20038 | #endif |
| 20039 | |
| 20040 | @@ -1777,7 +2053,6 @@ au1550_probe(void) |
| 20041 | proc_au1550_dump, NULL); |
| 20042 | #endif /* AU1550_DEBUG */ |
| 20043 | |
| 20044 | - intclk_setup(); |
| 20045 | |
| 20046 | /* The GPIO for the appropriate PSC was configured by the |
| 20047 | * board specific start up. |
| 20048 | @@ -1786,7 +2061,12 @@ au1550_probe(void) |
| 20049 | */ |
| 20050 | ip->psc_ctrl = PSC_CTRL_DISABLE; /* Disable PSC */ |
| 20051 | au_sync(); |
| 20052 | +#if defined(WM_MODE_USB) |
| 20053 | + intclk_setup(); |
| 20054 | ip->psc_sel = (PSC_SEL_CLK_INTCLK | PSC_SEL_PS_I2SMODE); |
| 20055 | +#else |
| 20056 | + ip->psc_sel = (PSC_SEL_CLK_EXTCLK | PSC_SEL_PS_I2SMODE); |
| 20057 | +#endif |
| 20058 | au_sync(); |
| 20059 | |
| 20060 | /* Enable PSC |
| 20061 | @@ -1806,42 +2086,18 @@ au1550_probe(void) |
| 20062 | * Actual I2S mode (first bit delayed by one clock). |
| 20063 | * Master mode (We provide the clock from the PSC). |
| 20064 | */ |
| 20065 | - val = PSC_I2SCFG_SET_LEN(16); |
| 20066 | -#ifdef TRY_441KHz |
| 20067 | - /* This really should be 250, but it appears that all of the |
| 20068 | - * PLLs, dividers and so on in the chain shift it. That's the |
| 20069 | - * problem with sourceing the clock instead of letting the very |
| 20070 | - * stable codec provide it. But, the PSC doesn't appear to want |
| 20071 | - * to work in slave mode, so this is what we get. It's not |
| 20072 | - * studio quality timing, but it's good enough for listening |
| 20073 | - * to mp3s. |
| 20074 | - */ |
| 20075 | - val |= PSC_I2SCFG_SET_WS(252); |
| 20076 | -#else |
| 20077 | - val |= PSC_I2SCFG_SET_WS(250); |
| 20078 | -#endif |
| 20079 | - val |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \ |
| 20080 | + |
| 20081 | + val = PSC_I2SCFG_SET_LEN(16) | PSC_I2SCFG_WS(WS_128FS) | PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \ |
| 20082 | PSC_I2SCFG_BI | PSC_I2SCFG_XM; |
| 20083 | |
| 20084 | - ip->psc_i2scfg = val; |
| 20085 | - au_sync(); |
| 20086 | - val |= PSC_I2SCFG_DE_ENABLE; |
| 20087 | - ip->psc_i2scfg = val; |
| 20088 | - au_sync(); |
| 20089 | + ip->psc_i2scfg = val | PSC_I2SCFG_DE_ENABLE; |
| 20090 | |
| 20091 | - /* Wait for Device ready. |
| 20092 | - */ |
| 20093 | - do { |
| 20094 | - val = ip->psc_i2sstat; |
| 20095 | - au_sync(); |
| 20096 | - } while ((val & PSC_I2SSTAT_DR) == 0); |
| 20097 | + set_dac_rate(s, 8000); //Set default rate |
| 20098 | |
| 20099 | - val = ip->psc_i2scfg; |
| 20100 | - au_sync(); |
| 20101 | + codec_init(s); |
| 20102 | |
| 20103 | - codec_init(); |
| 20104 | + s->no_vra = vra ? 0 : 1; |
| 20105 | |
| 20106 | - s->no_vra = 1; |
| 20107 | if (s->no_vra) |
| 20108 | info("no VRA, interpolating and decimating"); |
| 20109 | |
| 20110 | @@ -1866,6 +2122,8 @@ au1550_probe(void) |
| 20111 | err_dev2: |
| 20112 | unregister_sound_dsp(s->dev_audio); |
| 20113 | #endif |
| 20114 | + err_dev2: |
| 20115 | + unregister_sound_dsp(s->dev_audio); |
| 20116 | err_dev1: |
| 20117 | au1xxx_dbdma_chan_free(s->dma_adc.dmanr); |
| 20118 | err_dma2: |
| 20119 | --- a/drivers/sound/au1550_psc.c |
| 20120 | +++ b/drivers/sound/au1550_psc.c |
| 20121 | @@ -30,6 +30,7 @@ |
| 20122 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20123 | * |
| 20124 | */ |
| 20125 | + |
| 20126 | #include <linux/version.h> |
| 20127 | #include <linux/module.h> |
| 20128 | #include <linux/string.h> |
| 20129 | @@ -63,6 +64,14 @@ |
| 20130 | #include <asm/db1x00.h> |
| 20131 | #endif |
| 20132 | |
| 20133 | +#ifdef CONFIG_MIPS_PB1200 |
| 20134 | +#include <asm/pb1200.h> |
| 20135 | +#endif |
| 20136 | + |
| 20137 | +#ifdef CONFIG_MIPS_DB1200 |
| 20138 | +#include <asm/db1200.h> |
| 20139 | +#endif |
| 20140 | + |
| 20141 | #undef OSS_DOCUMENTED_MIXER_SEMANTICS |
| 20142 | |
| 20143 | #define AU1550_MODULE_NAME "Au1550 psc audio" |
| 20144 | @@ -521,7 +530,14 @@ stop_adc(struct au1550_state *s) |
| 20145 | spin_unlock_irqrestore(&s->lock, flags); |
| 20146 | } |
| 20147 | |
| 20148 | - |
| 20149 | +/* |
| 20150 | + NOTE: The xmit slots cannot be changed on the fly when in full-duplex |
| 20151 | + because the AC'97 block must be stopped/started. When using this driver |
| 20152 | + in full-duplex (in & out at the same time), the DMA engine will stop if |
| 20153 | + you disable the block. |
| 20154 | + TODO: change implementation to properly restart adc/dac after setting |
| 20155 | + xmit slots. |
| 20156 | +*/ |
| 20157 | static void |
| 20158 | set_xmit_slots(int num_channels) |
| 20159 | { |
| 20160 | @@ -565,6 +581,14 @@ set_xmit_slots(int num_channels) |
| 20161 | } while ((stat & PSC_AC97STAT_DR) == 0); |
| 20162 | } |
| 20163 | |
| 20164 | +/* |
| 20165 | + NOTE: The recv slots cannot be changed on the fly when in full-duplex |
| 20166 | + because the AC'97 block must be stopped/started. When using this driver |
| 20167 | + in full-duplex (in & out at the same time), the DMA engine will stop if |
| 20168 | + you disable the block. |
| 20169 | + TODO: change implementation to properly restart adc/dac after setting |
| 20170 | + recv slots. |
| 20171 | +*/ |
| 20172 | static void |
| 20173 | set_recv_slots(int num_channels) |
| 20174 | { |
| 20175 | @@ -608,7 +632,6 @@ start_dac(struct au1550_state *s) |
| 20176 | |
| 20177 | spin_lock_irqsave(&s->lock, flags); |
| 20178 | |
| 20179 | - set_xmit_slots(db->num_channels); |
| 20180 | au_writel(PSC_AC97PCR_TC, PSC_AC97PCR); |
| 20181 | au_sync(); |
| 20182 | au_writel(PSC_AC97PCR_TS, PSC_AC97PCR); |
| 20183 | @@ -640,7 +663,6 @@ start_adc(struct au1550_state *s) |
| 20184 | db->nextIn -= db->dmasize; |
| 20185 | } |
| 20186 | |
| 20187 | - set_recv_slots(db->num_channels); |
| 20188 | au1xxx_dbdma_start(db->dmanr); |
| 20189 | au_writel(PSC_AC97PCR_RC, PSC_AC97PCR); |
| 20190 | au_sync(); |
| 20191 | @@ -752,12 +774,16 @@ dac_dma_interrupt(int irq, void *dev_id, |
| 20192 | if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE)) |
| 20193 | dbg("AC97C status = 0x%08x", ac97c_stat); |
| 20194 | #endif |
| 20195 | + /* There is a possiblity that we are getting 1 interrupt for |
| 20196 | + multiple descriptors. Use ddma api to find out how many |
| 20197 | + completed. |
| 20198 | + */ |
| 20199 | db->dma_qcount--; |
| 20200 | |
| 20201 | if (db->count >= db->fragsize) { |
| 20202 | if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, |
| 20203 | db->fragsize) == 0) { |
| 20204 | - err("qcount < 2 and no ring room!"); |
| 20205 | + err("qcount < 2 and no ring room1!"); |
| 20206 | } |
| 20207 | db->nextOut += db->fragsize; |
| 20208 | if (db->nextOut >= db->rawbuf + db->dmasize) |
| 20209 | @@ -941,11 +967,12 @@ translate_from_user(struct dmabuf *db, c |
| 20210 | |
| 20211 | /* duplicate every audio frame src_factor times |
| 20212 | */ |
| 20213 | - for (i = 0; i < db->src_factor; i++) |
| 20214 | + for (i = 0; i < db->src_factor; i++) { |
| 20215 | memcpy(dmabuf, dmasample, db->dma_bytes_per_sample); |
| 20216 | + dmabuf += interp_bytes_per_sample; |
| 20217 | + } |
| 20218 | |
| 20219 | userbuf += db->user_bytes_per_sample; |
| 20220 | - dmabuf += interp_bytes_per_sample; |
| 20221 | } |
| 20222 | |
| 20223 | return num_samples * interp_bytes_per_sample; |
| 20224 | @@ -1203,7 +1230,7 @@ au1550_write(struct file *file, const ch |
| 20225 | while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) { |
| 20226 | if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut, |
| 20227 | db->fragsize) == 0) { |
| 20228 | - err("qcount < 2 and no ring room!"); |
| 20229 | + err("qcount < 2 and no ring room!0"); |
| 20230 | } |
| 20231 | db->nextOut += db->fragsize; |
| 20232 | if (db->nextOut >= db->rawbuf + db->dmasize) |
| 20233 | @@ -1481,6 +1508,7 @@ au1550_ioctl(struct inode *inode, struct |
| 20234 | return -EINVAL; |
| 20235 | stop_adc(s); |
| 20236 | s->dma_adc.num_channels = val; |
| 20237 | + set_recv_slots(val); |
| 20238 | if ((ret = prog_dmabuf_adc(s))) |
| 20239 | return ret; |
| 20240 | } |
| 20241 | @@ -1538,6 +1566,7 @@ au1550_ioctl(struct inode *inode, struct |
| 20242 | } |
| 20243 | |
| 20244 | s->dma_dac.num_channels = val; |
| 20245 | + set_xmit_slots(val); |
| 20246 | if ((ret = prog_dmabuf_dac(s))) |
| 20247 | return ret; |
| 20248 | } |
| 20249 | @@ -1832,10 +1861,8 @@ au1550_open(struct inode *inode, struct |
| 20250 | down(&s->open_sem); |
| 20251 | } |
| 20252 | |
| 20253 | - stop_dac(s); |
| 20254 | - stop_adc(s); |
| 20255 | - |
| 20256 | if (file->f_mode & FMODE_READ) { |
| 20257 | + stop_adc(s); |
| 20258 | s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = |
| 20259 | s->dma_adc.subdivision = s->dma_adc.total_bytes = 0; |
| 20260 | s->dma_adc.num_channels = 1; |
| 20261 | @@ -1846,6 +1873,7 @@ au1550_open(struct inode *inode, struct |
| 20262 | } |
| 20263 | |
| 20264 | if (file->f_mode & FMODE_WRITE) { |
| 20265 | + stop_dac(s); |
| 20266 | s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = |
| 20267 | s->dma_dac.subdivision = s->dma_dac.total_bytes = 0; |
| 20268 | s->dma_dac.num_channels = 1; |
| 20269 | @@ -2091,6 +2119,9 @@ au1550_probe(void) |
| 20270 | ac97_read_proc, &s->codec); |
| 20271 | #endif |
| 20272 | |
| 20273 | + set_xmit_slots(1); |
| 20274 | + set_recv_slots(1); |
| 20275 | + |
| 20276 | return 0; |
| 20277 | |
| 20278 | err_dev3: |
| 20279 | --- a/drivers/sound/Config.in |
| 20280 | +++ b/drivers/sound/Config.in |
| 20281 | @@ -72,10 +72,15 @@ fi |
| 20282 | if [ "$CONFIG_DDB5477" = "y" ]; then |
| 20283 | dep_tristate ' NEC Vrc5477 AC97 sound' CONFIG_SOUND_VRC5477 $CONFIG_SOUND |
| 20284 | fi |
| 20285 | -if [ "$CONFIG_SOC_AU1X00" = "y" -o "$CONFIG_SOC_AU1500" = "y" ]; then |
| 20286 | - dep_tristate ' Au1x00 Sound' CONFIG_SOUND_AU1X00 $CONFIG_SOUND |
| 20287 | - dep_tristate ' Au1550 PSC Sound' CONFIG_SOUND_AU1550_PSC $CONFIG_SOUND |
| 20288 | - dep_tristate ' Au1550 I2S Sound' CONFIG_SOUND_AU1550_I2S $CONFIG_SOUND |
| 20289 | +if [ "$CONFIG_SOC_AU1000" = "y" -o \ |
| 20290 | + "$CONFIG_SOC_AU1500" = "y" -o \ |
| 20291 | + "$CONFIG_SOC_AU1100" = "y" ]; then |
| 20292 | + dep_tristate ' Au1x00 AC97 Sound' CONFIG_SOUND_AU1X00 $CONFIG_SOUND |
| 20293 | +fi |
| 20294 | +if [ "$CONFIG_SOC_AU1550" = "y" -o \ |
| 20295 | + "$CONFIG_SOC_AU1200" = "y" ]; then |
| 20296 | + dep_tristate ' Au1550/Au1200 PSC AC97 Sound' CONFIG_SOUND_AU1550_PSC $CONFIG_SOUND |
| 20297 | + dep_tristate ' Au1550/Au1200 PSC I2S Sound' CONFIG_SOUND_AU1550_I2S $CONFIG_SOUND |
| 20298 | fi |
| 20299 | |
| 20300 | dep_tristate ' Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core' CONFIG_SOUND_TRIDENT $CONFIG_SOUND $CONFIG_PCI |
| 20301 | --- a/drivers/tc/lk201.c |
| 20302 | +++ b/drivers/tc/lk201.c |
| 20303 | @@ -5,7 +5,7 @@ |
| 20304 | * for more details. |
| 20305 | * |
| 20306 | * Copyright (C) 1999-2002 Harald Koerfgen <hkoerfg@web.de> |
| 20307 | - * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki <macro@ds2.pg.gda.pl> |
| 20308 | + * Copyright (C) 2001, 2002, 2003, 2004 Maciej W. Rozycki |
| 20309 | */ |
| 20310 | |
| 20311 | #include <linux/config.h> |
| 20312 | @@ -23,8 +23,8 @@ |
| 20313 | #include <asm/keyboard.h> |
| 20314 | #include <asm/dec/tc.h> |
| 20315 | #include <asm/dec/machtype.h> |
| 20316 | +#include <asm/dec/serial.h> |
| 20317 | |
| 20318 | -#include "zs.h" |
| 20319 | #include "lk201.h" |
| 20320 | |
| 20321 | /* |
| 20322 | @@ -55,19 +55,20 @@ unsigned char *kbd_sysrq_xlate = lk201_s |
| 20323 | unsigned char kbd_sysrq_key = -1; |
| 20324 | #endif |
| 20325 | |
| 20326 | -#define KEYB_LINE 3 |
| 20327 | +#define KEYB_LINE_ZS 3 |
| 20328 | +#define KEYB_LINE_DZ 0 |
| 20329 | |
| 20330 | -static int __init lk201_init(struct dec_serial *); |
| 20331 | -static void __init lk201_info(struct dec_serial *); |
| 20332 | -static void lk201_kbd_rx_char(unsigned char, unsigned char); |
| 20333 | +static int __init lk201_init(void *); |
| 20334 | +static void __init lk201_info(void *); |
| 20335 | +static void lk201_rx_char(unsigned char, unsigned char); |
| 20336 | |
| 20337 | -struct zs_hook lk201_kbdhook = { |
| 20338 | +static struct dec_serial_hook lk201_hook = { |
| 20339 | .init_channel = lk201_init, |
| 20340 | .init_info = lk201_info, |
| 20341 | .rx_char = NULL, |
| 20342 | .poll_rx_char = NULL, |
| 20343 | .poll_tx_char = NULL, |
| 20344 | - .cflags = B4800 | CS8 | CSTOPB | CLOCAL |
| 20345 | + .cflags = B4800 | CS8 | CSTOPB | CLOCAL, |
| 20346 | }; |
| 20347 | |
| 20348 | /* |
| 20349 | @@ -93,28 +94,28 @@ static unsigned char lk201_reset_string[ |
| 20350 | LK_CMD_ENB_BELL, LK_PARAM_VOLUME(4), |
| 20351 | }; |
| 20352 | |
| 20353 | -static struct dec_serial* lk201kbd_info; |
| 20354 | +static void *lk201_handle; |
| 20355 | |
| 20356 | -static int lk201_send(struct dec_serial *info, unsigned char ch) |
| 20357 | +static int lk201_send(unsigned char ch) |
| 20358 | { |
| 20359 | - if (info->hook->poll_tx_char(info, ch)) { |
| 20360 | + if (lk201_hook.poll_tx_char(lk201_handle, ch)) { |
| 20361 | printk(KERN_ERR "lk201: transmit timeout\n"); |
| 20362 | return -EIO; |
| 20363 | } |
| 20364 | return 0; |
| 20365 | } |
| 20366 | |
| 20367 | -static inline int lk201_get_id(struct dec_serial *info) |
| 20368 | +static inline int lk201_get_id(void) |
| 20369 | { |
| 20370 | - return lk201_send(info, LK_CMD_REQ_ID); |
| 20371 | + return lk201_send(LK_CMD_REQ_ID); |
| 20372 | } |
| 20373 | |
| 20374 | -static int lk201_reset(struct dec_serial *info) |
| 20375 | +static int lk201_reset(void) |
| 20376 | { |
| 20377 | int i, r; |
| 20378 | |
| 20379 | for (i = 0; i < sizeof(lk201_reset_string); i++) { |
| 20380 | - r = lk201_send(info, lk201_reset_string[i]); |
| 20381 | + r = lk201_send(lk201_reset_string[i]); |
| 20382 | if (r < 0) |
| 20383 | return r; |
| 20384 | } |
| 20385 | @@ -203,24 +204,26 @@ static void parse_kbd_rate(struct kbd_re |
| 20386 | |
| 20387 | static int write_kbd_rate(struct kbd_repeat *rep) |
| 20388 | { |
| 20389 | - struct dec_serial* info = lk201kbd_info; |
| 20390 | int delay, rate; |
| 20391 | int i; |
| 20392 | |
| 20393 | delay = rep->delay / 5; |
| 20394 | rate = rep->rate; |
| 20395 | for (i = 0; i < 4; i++) { |
| 20396 | - if (info->hook->poll_tx_char(info, LK_CMD_RPT_RATE(i))) |
| 20397 | + if (lk201_hook.poll_tx_char(lk201_handle, |
| 20398 | + LK_CMD_RPT_RATE(i))) |
| 20399 | return 1; |
| 20400 | - if (info->hook->poll_tx_char(info, LK_PARAM_DELAY(delay))) |
| 20401 | + if (lk201_hook.poll_tx_char(lk201_handle, |
| 20402 | + LK_PARAM_DELAY(delay))) |
| 20403 | return 1; |
| 20404 | - if (info->hook->poll_tx_char(info, LK_PARAM_RATE(rate))) |
| 20405 | + if (lk201_hook.poll_tx_char(lk201_handle, |
| 20406 | + LK_PARAM_RATE(rate))) |
| 20407 | return 1; |
| 20408 | } |
| 20409 | return 0; |
| 20410 | } |
| 20411 | |
| 20412 | -static int lk201kbd_rate(struct kbd_repeat *rep) |
| 20413 | +static int lk201_kbd_rate(struct kbd_repeat *rep) |
| 20414 | { |
| 20415 | if (rep == NULL) |
| 20416 | return -EINVAL; |
| 20417 | @@ -237,10 +240,8 @@ static int lk201kbd_rate(struct kbd_repe |
| 20418 | return 0; |
| 20419 | } |
| 20420 | |
| 20421 | -static void lk201kd_mksound(unsigned int hz, unsigned int ticks) |
| 20422 | +static void lk201_kd_mksound(unsigned int hz, unsigned int ticks) |
| 20423 | { |
| 20424 | - struct dec_serial* info = lk201kbd_info; |
| 20425 | - |
| 20426 | if (!ticks) |
| 20427 | return; |
| 20428 | |
| 20429 | @@ -253,20 +254,19 @@ static void lk201kd_mksound(unsigned int |
| 20430 | ticks = 7; |
| 20431 | ticks = 7 - ticks; |
| 20432 | |
| 20433 | - if (info->hook->poll_tx_char(info, LK_CMD_ENB_BELL)) |
| 20434 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_CMD_ENB_BELL)) |
| 20435 | return; |
| 20436 | - if (info->hook->poll_tx_char(info, LK_PARAM_VOLUME(ticks))) |
| 20437 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_PARAM_VOLUME(ticks))) |
| 20438 | return; |
| 20439 | - if (info->hook->poll_tx_char(info, LK_CMD_BELL)) |
| 20440 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_CMD_BELL)) |
| 20441 | return; |
| 20442 | } |
| 20443 | |
| 20444 | void kbd_leds(unsigned char leds) |
| 20445 | { |
| 20446 | - struct dec_serial* info = lk201kbd_info; |
| 20447 | unsigned char l = 0; |
| 20448 | |
| 20449 | - if (!info) /* FIXME */ |
| 20450 | + if (!lk201_handle) /* FIXME */ |
| 20451 | return; |
| 20452 | |
| 20453 | /* FIXME -- Only Hold and Lock LEDs for now. --macro */ |
| 20454 | @@ -275,13 +275,13 @@ void kbd_leds(unsigned char leds) |
| 20455 | if (leds & LED_CAP) |
| 20456 | l |= LK_LED_LOCK; |
| 20457 | |
| 20458 | - if (info->hook->poll_tx_char(info, LK_CMD_LEDS_ON)) |
| 20459 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_CMD_LEDS_ON)) |
| 20460 | return; |
| 20461 | - if (info->hook->poll_tx_char(info, LK_PARAM_LED_MASK(l))) |
| 20462 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_PARAM_LED_MASK(l))) |
| 20463 | return; |
| 20464 | - if (info->hook->poll_tx_char(info, LK_CMD_LEDS_OFF)) |
| 20465 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_CMD_LEDS_OFF)) |
| 20466 | return; |
| 20467 | - if (info->hook->poll_tx_char(info, LK_PARAM_LED_MASK(~l))) |
| 20468 | + if (lk201_hook.poll_tx_char(lk201_handle, LK_PARAM_LED_MASK(~l))) |
| 20469 | return; |
| 20470 | } |
| 20471 | |
| 20472 | @@ -307,7 +307,7 @@ char kbd_unexpected_up(unsigned char key |
| 20473 | return 0x80; |
| 20474 | } |
| 20475 | |
| 20476 | -static void lk201_kbd_rx_char(unsigned char ch, unsigned char stat) |
| 20477 | +static void lk201_rx_char(unsigned char ch, unsigned char fl) |
| 20478 | { |
| 20479 | static unsigned char id[6]; |
| 20480 | static int id_i; |
| 20481 | @@ -316,9 +316,8 @@ static void lk201_kbd_rx_char(unsigned c |
| 20482 | static int prev_scancode; |
| 20483 | unsigned char c = scancodeRemap[ch]; |
| 20484 | |
| 20485 | - if (stat && stat != TTY_OVERRUN) { |
| 20486 | - printk(KERN_ERR "lk201: keyboard receive error: 0x%02x\n", |
| 20487 | - stat); |
| 20488 | + if (fl != TTY_NORMAL && fl != TTY_OVERRUN) { |
| 20489 | + printk(KERN_ERR "lk201: keyboard receive error: 0x%02x\n", fl); |
| 20490 | return; |
| 20491 | } |
| 20492 | |
| 20493 | @@ -335,7 +334,7 @@ static void lk201_kbd_rx_char(unsigned c |
| 20494 | /* OK, the power-up concluded. */ |
| 20495 | lk201_report(id); |
| 20496 | if (id[2] == LK_STAT_PWRUP_OK) |
| 20497 | - lk201_get_id(lk201kbd_info); |
| 20498 | + lk201_get_id(); |
| 20499 | else { |
| 20500 | id_i = 0; |
| 20501 | printk(KERN_ERR "lk201: keyboard power-up " |
| 20502 | @@ -345,7 +344,7 @@ static void lk201_kbd_rx_char(unsigned c |
| 20503 | /* We got the ID; report it and start operation. */ |
| 20504 | id_i = 0; |
| 20505 | lk201_id(id); |
| 20506 | - lk201_reset(lk201kbd_info); |
| 20507 | + lk201_reset(); |
| 20508 | } |
| 20509 | return; |
| 20510 | } |
| 20511 | @@ -398,29 +397,28 @@ static void lk201_kbd_rx_char(unsigned c |
| 20512 | tasklet_schedule(&keyboard_tasklet); |
| 20513 | } |
| 20514 | |
| 20515 | -static void __init lk201_info(struct dec_serial *info) |
| 20516 | +static void __init lk201_info(void *handle) |
| 20517 | { |
| 20518 | } |
| 20519 | |
| 20520 | -static int __init lk201_init(struct dec_serial *info) |
| 20521 | +static int __init lk201_init(void *handle) |
| 20522 | { |
| 20523 | /* First install handlers. */ |
| 20524 | - lk201kbd_info = info; |
| 20525 | - kbd_rate = lk201kbd_rate; |
| 20526 | - kd_mksound = lk201kd_mksound; |
| 20527 | + lk201_handle = handle; |
| 20528 | + kbd_rate = lk201_kbd_rate; |
| 20529 | + kd_mksound = lk201_kd_mksound; |
| 20530 | |
| 20531 | - info->hook->rx_char = lk201_kbd_rx_char; |
| 20532 | + lk201_hook.rx_char = lk201_rx_char; |
| 20533 | |
| 20534 | /* Then just issue a reset -- the handlers will do the rest. */ |
| 20535 | - lk201_send(info, LK_CMD_POWER_UP); |
| 20536 | + lk201_send(LK_CMD_POWER_UP); |
| 20537 | |
| 20538 | return 0; |
| 20539 | } |
| 20540 | |
| 20541 | void __init kbd_init_hw(void) |
| 20542 | { |
| 20543 | - extern int register_zs_hook(unsigned int, struct zs_hook *); |
| 20544 | - extern int unregister_zs_hook(unsigned int); |
| 20545 | + int keyb_line; |
| 20546 | |
| 20547 | /* Maxine uses LK501 at the Access.Bus. */ |
| 20548 | if (!LK_IFACE) |
| 20549 | @@ -428,19 +426,15 @@ void __init kbd_init_hw(void) |
| 20550 | |
| 20551 | printk(KERN_INFO "lk201: DECstation LK keyboard driver v0.05.\n"); |
| 20552 | |
| 20553 | - if (LK_IFACE_ZS) { |
| 20554 | - /* |
| 20555 | - * kbd_init_hw() is being called before |
| 20556 | - * rs_init() so just register the kbd hook |
| 20557 | - * and let zs_init do the rest :-) |
| 20558 | - */ |
| 20559 | - if(!register_zs_hook(KEYB_LINE, &lk201_kbdhook)) |
| 20560 | - unregister_zs_hook(KEYB_LINE); |
| 20561 | - } else { |
| 20562 | - /* |
| 20563 | - * TODO: modify dz.c to allow similar hooks |
| 20564 | - * for LK201 handling on DS2100, DS3100, and DS5000/200 |
| 20565 | - */ |
| 20566 | - printk(KERN_ERR "lk201: support for DZ11 not yet ready.\n"); |
| 20567 | - } |
| 20568 | + /* |
| 20569 | + * kbd_init_hw() is being called before |
| 20570 | + * rs_init() so just register the kbd hook |
| 20571 | + * and let zs_init do the rest :-) |
| 20572 | + */ |
| 20573 | + if (LK_IFACE_ZS) |
| 20574 | + keyb_line = KEYB_LINE_ZS; |
| 20575 | + else |
| 20576 | + keyb_line = KEYB_LINE_DZ; |
| 20577 | + if (!register_dec_serial_hook(keyb_line, &lk201_hook)) |
| 20578 | + unregister_dec_serial_hook(keyb_line); |
| 20579 | } |
| 20580 | --- a/drivers/tc/zs.c |
| 20581 | +++ b/drivers/tc/zs.c |
| 20582 | @@ -68,6 +68,8 @@ |
| 20583 | #include <asm/bitops.h> |
| 20584 | #include <asm/uaccess.h> |
| 20585 | #include <asm/bootinfo.h> |
| 20586 | +#include <asm/dec/serial.h> |
| 20587 | + |
| 20588 | #ifdef CONFIG_DECSTATION |
| 20589 | #include <asm/dec/interrupts.h> |
| 20590 | #include <asm/dec/machtype.h> |
| 20591 | @@ -160,8 +162,8 @@ struct tty_struct zs_ttys[NUM_CHANNELS]; |
| 20592 | #ifdef CONFIG_SERIAL_DEC_CONSOLE |
| 20593 | static struct console sercons; |
| 20594 | #endif |
| 20595 | -#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) \ |
| 20596 | - && !defined(MODULE) |
| 20597 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 20598 | + !defined(MODULE) |
| 20599 | static unsigned long break_pressed; /* break, really ... */ |
| 20600 | #endif |
| 20601 | |
| 20602 | @@ -196,7 +198,6 @@ static int serial_refcount; |
| 20603 | /* |
| 20604 | * Debugging. |
| 20605 | */ |
| 20606 | -#undef SERIAL_DEBUG_INTR |
| 20607 | #undef SERIAL_DEBUG_OPEN |
| 20608 | #undef SERIAL_DEBUG_FLOW |
| 20609 | #undef SERIAL_DEBUG_THROTTLE |
| 20610 | @@ -221,10 +222,6 @@ static struct tty_struct *serial_table[N |
| 20611 | static struct termios *serial_termios[NUM_CHANNELS]; |
| 20612 | static struct termios *serial_termios_locked[NUM_CHANNELS]; |
| 20613 | |
| 20614 | -#ifndef MIN |
| 20615 | -#define MIN(a,b) ((a) < (b) ? (a) : (b)) |
| 20616 | -#endif |
| 20617 | - |
| 20618 | /* |
| 20619 | * tmp_buf is used as a temporary buffer by serial_write. We need to |
| 20620 | * lock it in case the copy_from_user blocks while swapping in a page, |
| 20621 | @@ -386,8 +383,6 @@ static inline void rs_recv_clear(struct |
| 20622 | * ----------------------------------------------------------------------- |
| 20623 | */ |
| 20624 | |
| 20625 | -static int tty_break; /* Set whenever BREAK condition is detected. */ |
| 20626 | - |
| 20627 | /* |
| 20628 | * This routine is used by the interrupt handler to schedule |
| 20629 | * processing in the software interrupt portion of the driver. |
| 20630 | @@ -414,20 +409,15 @@ static _INLINE_ void receive_chars(struc |
| 20631 | if (!tty && (!info->hook || !info->hook->rx_char)) |
| 20632 | continue; |
| 20633 | |
| 20634 | - if (tty_break) { |
| 20635 | - tty_break = 0; |
| 20636 | -#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && !defined(MODULE) |
| 20637 | - if (info->line == sercons.index) { |
| 20638 | - if (!break_pressed) { |
| 20639 | - break_pressed = jiffies; |
| 20640 | - goto ignore_char; |
| 20641 | - } |
| 20642 | - break_pressed = 0; |
| 20643 | - } |
| 20644 | -#endif |
| 20645 | + flag = TTY_NORMAL; |
| 20646 | + if (info->tty_break) { |
| 20647 | + info->tty_break = 0; |
| 20648 | flag = TTY_BREAK; |
| 20649 | if (info->flags & ZILOG_SAK) |
| 20650 | do_SAK(tty); |
| 20651 | + /* Ignore the null char got when BREAK is removed. */ |
| 20652 | + if (ch == 0) |
| 20653 | + continue; |
| 20654 | } else { |
| 20655 | if (stat & Rx_OVR) { |
| 20656 | flag = TTY_OVERRUN; |
| 20657 | @@ -435,20 +425,22 @@ static _INLINE_ void receive_chars(struc |
| 20658 | flag = TTY_FRAME; |
| 20659 | } else if (stat & PAR_ERR) { |
| 20660 | flag = TTY_PARITY; |
| 20661 | - } else |
| 20662 | - flag = 0; |
| 20663 | - if (flag) |
| 20664 | + } |
| 20665 | + if (flag != TTY_NORMAL) |
| 20666 | /* reset the error indication */ |
| 20667 | write_zsreg(info->zs_channel, R0, ERR_RES); |
| 20668 | } |
| 20669 | |
| 20670 | -#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && !defined(MODULE) |
| 20671 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 20672 | + !defined(MODULE) |
| 20673 | if (break_pressed && info->line == sercons.index) { |
| 20674 | - if (ch != 0 && |
| 20675 | - time_before(jiffies, break_pressed + HZ*5)) { |
| 20676 | + /* Ignore the null char got when BREAK is removed. */ |
| 20677 | + if (ch == 0) |
| 20678 | + continue; |
| 20679 | + if (time_before(jiffies, break_pressed + HZ * 5)) { |
| 20680 | handle_sysrq(ch, regs, NULL, NULL); |
| 20681 | break_pressed = 0; |
| 20682 | - goto ignore_char; |
| 20683 | + continue; |
| 20684 | } |
| 20685 | break_pressed = 0; |
| 20686 | } |
| 20687 | @@ -459,23 +451,7 @@ static _INLINE_ void receive_chars(struc |
| 20688 | return; |
| 20689 | } |
| 20690 | |
| 20691 | - if (tty->flip.count >= TTY_FLIPBUF_SIZE) { |
| 20692 | - static int flip_buf_ovf; |
| 20693 | - ++flip_buf_ovf; |
| 20694 | - continue; |
| 20695 | - } |
| 20696 | - tty->flip.count++; |
| 20697 | - { |
| 20698 | - static int flip_max_cnt; |
| 20699 | - if (flip_max_cnt < tty->flip.count) |
| 20700 | - flip_max_cnt = tty->flip.count; |
| 20701 | - } |
| 20702 | - |
| 20703 | - *tty->flip.flag_buf_ptr++ = flag; |
| 20704 | - *tty->flip.char_buf_ptr++ = ch; |
| 20705 | -#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && !defined(MODULE) |
| 20706 | - ignore_char: |
| 20707 | -#endif |
| 20708 | + tty_insert_flip_char(tty, ch, flag); |
| 20709 | } |
| 20710 | if (tty) |
| 20711 | tty_flip_buffer_push(tty); |
| 20712 | @@ -517,11 +493,15 @@ static _INLINE_ void status_handle(struc |
| 20713 | /* Get status from Read Register 0 */ |
| 20714 | stat = read_zsreg(info->zs_channel, R0); |
| 20715 | |
| 20716 | - if (stat & BRK_ABRT) { |
| 20717 | -#ifdef SERIAL_DEBUG_INTR |
| 20718 | - printk("handling break...."); |
| 20719 | + if ((stat & BRK_ABRT) && !(info->read_reg_zero & BRK_ABRT)) { |
| 20720 | +#if defined(CONFIG_SERIAL_DEC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) && \ |
| 20721 | + !defined(MODULE) |
| 20722 | + if (info->line == sercons.index) { |
| 20723 | + if (!break_pressed) |
| 20724 | + break_pressed = jiffies; |
| 20725 | + } else |
| 20726 | #endif |
| 20727 | - tty_break = 1; |
| 20728 | + info->tty_break = 1; |
| 20729 | } |
| 20730 | |
| 20731 | if (info->zs_channel != info->zs_chan_a) { |
| 20732 | @@ -957,7 +937,7 @@ static int rs_write(struct tty_struct * |
| 20733 | save_flags(flags); |
| 20734 | while (1) { |
| 20735 | cli(); |
| 20736 | - c = MIN(count, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
| 20737 | + c = min(count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
| 20738 | SERIAL_XMIT_SIZE - info->xmit_head)); |
| 20739 | if (c <= 0) |
| 20740 | break; |
| 20741 | @@ -965,7 +945,7 @@ static int rs_write(struct tty_struct * |
| 20742 | if (from_user) { |
| 20743 | down(&tmp_buf_sem); |
| 20744 | copy_from_user(tmp_buf, buf, c); |
| 20745 | - c = MIN(c, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
| 20746 | + c = min(c, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
| 20747 | SERIAL_XMIT_SIZE - info->xmit_head)); |
| 20748 | memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c); |
| 20749 | up(&tmp_buf_sem); |
| 20750 | @@ -1282,46 +1262,48 @@ static int rs_ioctl(struct tty_struct *t |
| 20751 | } |
| 20752 | |
| 20753 | switch (cmd) { |
| 20754 | - case TIOCMGET: |
| 20755 | - error = verify_area(VERIFY_WRITE, (void *) arg, |
| 20756 | - sizeof(unsigned int)); |
| 20757 | - if (error) |
| 20758 | - return error; |
| 20759 | - return get_modem_info(info, (unsigned int *) arg); |
| 20760 | - case TIOCMBIS: |
| 20761 | - case TIOCMBIC: |
| 20762 | - case TIOCMSET: |
| 20763 | - return set_modem_info(info, cmd, (unsigned int *) arg); |
| 20764 | - case TIOCGSERIAL: |
| 20765 | - error = verify_area(VERIFY_WRITE, (void *) arg, |
| 20766 | - sizeof(struct serial_struct)); |
| 20767 | - if (error) |
| 20768 | - return error; |
| 20769 | - return get_serial_info(info, |
| 20770 | - (struct serial_struct *) arg); |
| 20771 | - case TIOCSSERIAL: |
| 20772 | - return set_serial_info(info, |
| 20773 | - (struct serial_struct *) arg); |
| 20774 | - case TIOCSERGETLSR: /* Get line status register */ |
| 20775 | - error = verify_area(VERIFY_WRITE, (void *) arg, |
| 20776 | - sizeof(unsigned int)); |
| 20777 | - if (error) |
| 20778 | - return error; |
| 20779 | - else |
| 20780 | - return get_lsr_info(info, (unsigned int *) arg); |
| 20781 | + case TIOCMGET: |
| 20782 | + error = verify_area(VERIFY_WRITE, (void *)arg, |
| 20783 | + sizeof(unsigned int)); |
| 20784 | + if (error) |
| 20785 | + return error; |
| 20786 | + return get_modem_info(info, (unsigned int *)arg); |
| 20787 | |
| 20788 | - case TIOCSERGSTRUCT: |
| 20789 | - error = verify_area(VERIFY_WRITE, (void *) arg, |
| 20790 | - sizeof(struct dec_serial)); |
| 20791 | - if (error) |
| 20792 | - return error; |
| 20793 | - copy_from_user((struct dec_serial *) arg, |
| 20794 | - info, sizeof(struct dec_serial)); |
| 20795 | - return 0; |
| 20796 | + case TIOCMBIS: |
| 20797 | + case TIOCMBIC: |
| 20798 | + case TIOCMSET: |
| 20799 | + return set_modem_info(info, cmd, (unsigned int *)arg); |
| 20800 | |
| 20801 | - default: |
| 20802 | - return -ENOIOCTLCMD; |
| 20803 | - } |
| 20804 | + case TIOCGSERIAL: |
| 20805 | + error = verify_area(VERIFY_WRITE, (void *)arg, |
| 20806 | + sizeof(struct serial_struct)); |
| 20807 | + if (error) |
| 20808 | + return error; |
| 20809 | + return get_serial_info(info, (struct serial_struct *)arg); |
| 20810 | + |
| 20811 | + case TIOCSSERIAL: |
| 20812 | + return set_serial_info(info, (struct serial_struct *)arg); |
| 20813 | + |
| 20814 | + case TIOCSERGETLSR: /* Get line status register */ |
| 20815 | + error = verify_area(VERIFY_WRITE, (void *)arg, |
| 20816 | + sizeof(unsigned int)); |
| 20817 | + if (error) |
| 20818 | + return error; |
| 20819 | + else |
| 20820 | + return get_lsr_info(info, (unsigned int *)arg); |
| 20821 | + |
| 20822 | + case TIOCSERGSTRUCT: |
| 20823 | + error = verify_area(VERIFY_WRITE, (void *)arg, |
| 20824 | + sizeof(struct dec_serial)); |
| 20825 | + if (error) |
| 20826 | + return error; |
| 20827 | + copy_from_user((struct dec_serial *)arg, info, |
| 20828 | + sizeof(struct dec_serial)); |
| 20829 | + return 0; |
| 20830 | + |
| 20831 | + default: |
| 20832 | + return -ENOIOCTLCMD; |
| 20833 | + } |
| 20834 | return 0; |
| 20835 | } |
| 20836 | |
| 20837 | @@ -1446,7 +1428,8 @@ static void rs_close(struct tty_struct * |
| 20838 | static void rs_wait_until_sent(struct tty_struct *tty, int timeout) |
| 20839 | { |
| 20840 | struct dec_serial *info = (struct dec_serial *) tty->driver_data; |
| 20841 | - unsigned long orig_jiffies, char_time; |
| 20842 | + unsigned long orig_jiffies; |
| 20843 | + int char_time; |
| 20844 | |
| 20845 | if (serial_paranoia_check(info, tty->device, "rs_wait_until_sent")) |
| 20846 | return; |
| 20847 | @@ -1462,7 +1445,7 @@ static void rs_wait_until_sent(struct tt |
| 20848 | if (char_time == 0) |
| 20849 | char_time = 1; |
| 20850 | if (timeout) |
| 20851 | - char_time = MIN(char_time, timeout); |
| 20852 | + char_time = min(char_time, timeout); |
| 20853 | while ((read_zsreg(info->zs_channel, 1) & Tx_BUF_EMP) == 0) { |
| 20854 | current->state = TASK_INTERRUPTIBLE; |
| 20855 | schedule_timeout(char_time); |
| 20856 | @@ -1714,7 +1697,7 @@ int rs_open(struct tty_struct *tty, stru |
| 20857 | |
| 20858 | static void __init show_serial_version(void) |
| 20859 | { |
| 20860 | - printk("DECstation Z8530 serial driver version 0.08\n"); |
| 20861 | + printk("DECstation Z8530 serial driver version 0.09\n"); |
| 20862 | } |
| 20863 | |
| 20864 | /* Initialize Z8530s zs_channels |
| 20865 | @@ -1994,8 +1977,9 @@ int __init zs_init(void) |
| 20866 | * polling I/O routines |
| 20867 | */ |
| 20868 | static int |
| 20869 | -zs_poll_tx_char(struct dec_serial *info, unsigned char ch) |
| 20870 | +zs_poll_tx_char(void *handle, unsigned char ch) |
| 20871 | { |
| 20872 | + struct dec_serial *info = handle; |
| 20873 | struct dec_zschannel *chan = info->zs_channel; |
| 20874 | int ret; |
| 20875 | |
| 20876 | @@ -2017,8 +2001,9 @@ zs_poll_tx_char(struct dec_serial *info, |
| 20877 | } |
| 20878 | |
| 20879 | static int |
| 20880 | -zs_poll_rx_char(struct dec_serial *info) |
| 20881 | +zs_poll_rx_char(void *handle) |
| 20882 | { |
| 20883 | + struct dec_serial *info = handle; |
| 20884 | struct dec_zschannel *chan = info->zs_channel; |
| 20885 | int ret; |
| 20886 | |
| 20887 | @@ -2038,12 +2023,13 @@ zs_poll_rx_char(struct dec_serial *info) |
| 20888 | return -ENODEV; |
| 20889 | } |
| 20890 | |
| 20891 | -unsigned int register_zs_hook(unsigned int channel, struct zs_hook *hook) |
| 20892 | +int register_zs_hook(unsigned int channel, struct dec_serial_hook *hook) |
| 20893 | { |
| 20894 | struct dec_serial *info = &zs_soft[channel]; |
| 20895 | |
| 20896 | if (info->hook) { |
| 20897 | - printk(__FUNCTION__": line %d has already a hook registered\n", channel); |
| 20898 | + printk("%s: line %d has already a hook registered\n", |
| 20899 | + __FUNCTION__, channel); |
| 20900 | |
| 20901 | return 0; |
| 20902 | } else { |
| 20903 | @@ -2055,7 +2041,7 @@ unsigned int register_zs_hook(unsigned i |
| 20904 | } |
| 20905 | } |
| 20906 | |
| 20907 | -unsigned int unregister_zs_hook(unsigned int channel) |
| 20908 | +int unregister_zs_hook(unsigned int channel) |
| 20909 | { |
| 20910 | struct dec_serial *info = &zs_soft[channel]; |
| 20911 | |
| 20912 | @@ -2063,8 +2049,8 @@ unsigned int unregister_zs_hook(unsigned |
| 20913 | info->hook = NULL; |
| 20914 | return 1; |
| 20915 | } else { |
| 20916 | - printk(__FUNCTION__": trying to unregister hook on line %d," |
| 20917 | - " but none is registered\n", channel); |
| 20918 | + printk("%s: trying to unregister hook on line %d," |
| 20919 | + " but none is registered\n", __FUNCTION__, channel); |
| 20920 | return 0; |
| 20921 | } |
| 20922 | } |
| 20923 | @@ -2319,22 +2305,23 @@ void kgdb_interruptible(int yes) |
| 20924 | write_zsreg(chan, 9, nine); |
| 20925 | } |
| 20926 | |
| 20927 | -static int kgdbhook_init_channel(struct dec_serial* info) |
| 20928 | +static int kgdbhook_init_channel(void *handle) |
| 20929 | { |
| 20930 | return 0; |
| 20931 | } |
| 20932 | |
| 20933 | -static void kgdbhook_init_info(struct dec_serial* info) |
| 20934 | +static void kgdbhook_init_info(void *handle) |
| 20935 | { |
| 20936 | } |
| 20937 | |
| 20938 | -static void kgdbhook_rx_char(struct dec_serial* info, |
| 20939 | - unsigned char ch, unsigned char stat) |
| 20940 | +static void kgdbhook_rx_char(void *handle, unsigned char ch, unsigned char fl) |
| 20941 | { |
| 20942 | + struct dec_serial *info = handle; |
| 20943 | + |
| 20944 | + if (fl != TTY_NORMAL) |
| 20945 | + return; |
| 20946 | if (ch == 0x03 || ch == '$') |
| 20947 | breakpoint(); |
| 20948 | - if (stat & (Rx_OVR|FRM_ERR|PAR_ERR)) |
| 20949 | - write_zsreg(info->zs_channel, 0, ERR_RES); |
| 20950 | } |
| 20951 | |
| 20952 | /* This sets up the serial port we're using, and turns on |
| 20953 | @@ -2360,11 +2347,11 @@ static inline void kgdb_chaninit(struct |
| 20954 | * for /dev/ttyb which is determined in setup_arch() from the |
| 20955 | * boot command line flags. |
| 20956 | */ |
| 20957 | -struct zs_hook zs_kgdbhook = { |
| 20958 | - init_channel : kgdbhook_init_channel, |
| 20959 | - init_info : kgdbhook_init_info, |
| 20960 | - cflags : B38400|CS8|CLOCAL, |
| 20961 | - rx_char : kgdbhook_rx_char, |
| 20962 | +struct dec_serial_hook zs_kgdbhook = { |
| 20963 | + .init_channel = kgdbhook_init_channel, |
| 20964 | + .init_info = kgdbhook_init_info, |
| 20965 | + .rx_char = kgdbhook_rx_char, |
| 20966 | + .cflags = B38400 | CS8 | CLOCAL, |
| 20967 | } |
| 20968 | |
| 20969 | void __init zs_kgdb_hook(int tty_num) |
| 20970 | --- a/drivers/tc/zs.h |
| 20971 | +++ b/drivers/tc/zs.h |
| 20972 | @@ -1,14 +1,18 @@ |
| 20973 | /* |
| 20974 | - * macserial.h: Definitions for the Macintosh Z8530 serial driver. |
| 20975 | + * drivers/tc/zs.h: Definitions for the DECstation Z85C30 serial driver. |
| 20976 | * |
| 20977 | * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras. |
| 20978 | + * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen. |
| 20979 | * |
| 20980 | * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) |
| 20981 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
| 20982 | + * Copyright (C) 2004 Maciej W. Rozycki |
| 20983 | */ |
| 20984 | #ifndef _DECSERIAL_H |
| 20985 | #define _DECSERIAL_H |
| 20986 | |
| 20987 | +#include <asm/dec/serial.h> |
| 20988 | + |
| 20989 | #define NUM_ZSREGS 16 |
| 20990 | |
| 20991 | struct serial_struct { |
| 20992 | @@ -89,63 +93,50 @@ struct dec_zschannel { |
| 20993 | unsigned char curregs[NUM_ZSREGS]; |
| 20994 | }; |
| 20995 | |
| 20996 | -struct dec_serial; |
| 20997 | - |
| 20998 | -struct zs_hook { |
| 20999 | - int (*init_channel)(struct dec_serial* info); |
| 21000 | - void (*init_info)(struct dec_serial* info); |
| 21001 | - void (*rx_char)(unsigned char ch, unsigned char stat); |
| 21002 | - int (*poll_rx_char)(struct dec_serial* info); |
| 21003 | - int (*poll_tx_char)(struct dec_serial* info, |
| 21004 | - unsigned char ch); |
| 21005 | - unsigned cflags; |
| 21006 | -}; |
| 21007 | - |
| 21008 | struct dec_serial { |
| 21009 | - struct dec_serial *zs_next; /* For IRQ servicing chain */ |
| 21010 | - struct dec_zschannel *zs_channel; /* Channel registers */ |
| 21011 | - struct dec_zschannel *zs_chan_a; /* A side registers */ |
| 21012 | - unsigned char read_reg_zero; |
| 21013 | - |
| 21014 | - char soft_carrier; /* Use soft carrier on this channel */ |
| 21015 | - char break_abort; /* Is serial console in, so process brk/abrt */ |
| 21016 | - struct zs_hook *hook; /* Hook on this channel */ |
| 21017 | - char is_cons; /* Is this our console. */ |
| 21018 | - unsigned char tx_active; /* character is being xmitted */ |
| 21019 | - unsigned char tx_stopped; /* output is suspended */ |
| 21020 | - |
| 21021 | - /* We need to know the current clock divisor |
| 21022 | - * to read the bps rate the chip has currently |
| 21023 | - * loaded. |
| 21024 | + struct dec_serial *zs_next; /* For IRQ servicing chain. */ |
| 21025 | + struct dec_zschannel *zs_channel; /* Channel registers. */ |
| 21026 | + struct dec_zschannel *zs_chan_a; /* A side registers. */ |
| 21027 | + unsigned char read_reg_zero; |
| 21028 | + |
| 21029 | + struct dec_serial_hook *hook; /* Hook on this channel. */ |
| 21030 | + int tty_break; /* Set on BREAK condition. */ |
| 21031 | + int is_cons; /* Is this our console. */ |
| 21032 | + int tx_active; /* Char is being xmitted. */ |
| 21033 | + int tx_stopped; /* Output is suspended. */ |
| 21034 | + |
| 21035 | + /* |
| 21036 | + * We need to know the current clock divisor |
| 21037 | + * to read the bps rate the chip has currently loaded. |
| 21038 | */ |
| 21039 | - unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ |
| 21040 | - int zs_baud; |
| 21041 | + int clk_divisor; /* May be 1, 16, 32, or 64. */ |
| 21042 | + int zs_baud; |
| 21043 | |
| 21044 | - char change_needed; |
| 21045 | + char change_needed; |
| 21046 | |
| 21047 | int magic; |
| 21048 | int baud_base; |
| 21049 | int port; |
| 21050 | int irq; |
| 21051 | - int flags; /* defined in tty.h */ |
| 21052 | - int type; /* UART type */ |
| 21053 | + int flags; /* Defined in tty.h. */ |
| 21054 | + int type; /* UART type. */ |
| 21055 | struct tty_struct *tty; |
| 21056 | int read_status_mask; |
| 21057 | int ignore_status_mask; |
| 21058 | int timeout; |
| 21059 | int xmit_fifo_size; |
| 21060 | int custom_divisor; |
| 21061 | - int x_char; /* xon/xoff character */ |
| 21062 | + int x_char; /* XON/XOFF character. */ |
| 21063 | int close_delay; |
| 21064 | unsigned short closing_wait; |
| 21065 | unsigned short closing_wait2; |
| 21066 | unsigned long event; |
| 21067 | unsigned long last_active; |
| 21068 | int line; |
| 21069 | - int count; /* # of fd on device */ |
| 21070 | - int blocked_open; /* # of blocked opens */ |
| 21071 | - long session; /* Session of opening process */ |
| 21072 | - long pgrp; /* pgrp of opening process */ |
| 21073 | + int count; /* # of fds on device. */ |
| 21074 | + int blocked_open; /* # of blocked opens. */ |
| 21075 | + long session; /* Sess of opening process. */ |
| 21076 | + long pgrp; /* Pgrp of opening process. */ |
| 21077 | unsigned char *xmit_buf; |
| 21078 | int xmit_head; |
| 21079 | int xmit_tail; |
| 21080 | --- /dev/null |
| 21081 | +++ b/drivers/video/au1200fb.c |
| 21082 | @@ -0,0 +1,1564 @@ |
| 21083 | +/* |
| 21084 | + * BRIEF MODULE DESCRIPTION |
| 21085 | + * Au1200 LCD Driver. |
| 21086 | + * |
| 21087 | + * Copyright 2004 AMD |
| 21088 | + * Author: AMD |
| 21089 | + * |
| 21090 | + * Based on: |
| 21091 | + * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device |
| 21092 | + * Created 28 Dec 1997 by Geert Uytterhoeven |
| 21093 | + * |
| 21094 | + * This program is free software; you can redistribute it and/or modify it |
| 21095 | + * under the terms of the GNU General Public License as published by the |
| 21096 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 21097 | + * option) any later version. |
| 21098 | + * |
| 21099 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 21100 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 21101 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 21102 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21103 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 21104 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 21105 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 21106 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 21107 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 21108 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 21109 | + * |
| 21110 | + * You should have received a copy of the GNU General Public License along |
| 21111 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 21112 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21113 | + */ |
| 21114 | + |
| 21115 | +#include <linux/module.h> |
| 21116 | +#include <linux/kernel.h> |
| 21117 | +#include <linux/errno.h> |
| 21118 | +#include <linux/string.h> |
| 21119 | +#include <linux/mm.h> |
| 21120 | +#include <linux/tty.h> |
| 21121 | +#include <linux/slab.h> |
| 21122 | +#include <linux/delay.h> |
| 21123 | +#include <linux/fb.h> |
| 21124 | +#include <linux/init.h> |
| 21125 | +#include <asm/uaccess.h> |
| 21126 | + |
| 21127 | +#include <asm/au1000.h> |
| 21128 | +#include <asm/au1xxx_gpio.h> |
| 21129 | +#include "au1200fb.h" |
| 21130 | + |
| 21131 | +#include <video/fbcon.h> |
| 21132 | +#include <video/fbcon-cfb16.h> |
| 21133 | +#include <video/fbcon-cfb32.h> |
| 21134 | +#define CMAPSIZE 16 |
| 21135 | + |
| 21136 | +#define AU1200_LCD_GET_WINENABLE 1 |
| 21137 | +#define AU1200_LCD_SET_WINENABLE 2 |
| 21138 | +#define AU1200_LCD_GET_WINLOCATION 3 |
| 21139 | +#define AU1200_LCD_SET_WINLOCATION 4 |
| 21140 | +#define AU1200_LCD_GET_WINSIZE 5 |
| 21141 | +#define AU1200_LCD_SET_WINSIZE 6 |
| 21142 | +#define AU1200_LCD_GET_BACKCOLOR 7 |
| 21143 | +#define AU1200_LCD_SET_BACKCOLOR 8 |
| 21144 | +#define AU1200_LCD_GET_COLORKEY 9 |
| 21145 | +#define AU1200_LCD_SET_COLORKEY 10 |
| 21146 | +#define AU1200_LCD_GET_PANEL 11 |
| 21147 | +#define AU1200_LCD_SET_PANEL 12 |
| 21148 | + |
| 21149 | +typedef struct au1200_lcd_getset_t |
| 21150 | +{ |
| 21151 | + unsigned int subcmd; |
| 21152 | + union { |
| 21153 | + struct { |
| 21154 | + int enable; |
| 21155 | + } winenable; |
| 21156 | + struct { |
| 21157 | + int x, y; |
| 21158 | + } winlocation; |
| 21159 | + struct { |
| 21160 | + int hsz, vsz; |
| 21161 | + } winsize; |
| 21162 | + struct { |
| 21163 | + unsigned int color; |
| 21164 | + } backcolor; |
| 21165 | + struct { |
| 21166 | + unsigned int key; |
| 21167 | + unsigned int mask; |
| 21168 | + } colorkey; |
| 21169 | + struct { |
| 21170 | + int panel; |
| 21171 | + char desc[80]; |
| 21172 | + } panel; |
| 21173 | + }; |
| 21174 | +} au1200_lcd_getset_t; |
| 21175 | + |
| 21176 | +AU1200_LCD *lcd = (AU1200_LCD *)AU1200_LCD_ADDR; |
| 21177 | +static int window_index = 0; /* default is zero */ |
| 21178 | +static int panel_index = -1; /* default is call board_au1200fb_panel */ |
| 21179 | + |
| 21180 | +struct window_settings |
| 21181 | +{ |
| 21182 | + unsigned char name[64]; |
| 21183 | + uint32 mode_backcolor; |
| 21184 | + uint32 mode_colorkey; |
| 21185 | + uint32 mode_colorkeymsk; |
| 21186 | + struct |
| 21187 | + { |
| 21188 | + int xres; |
| 21189 | + int yres; |
| 21190 | + int xpos; |
| 21191 | + int ypos; |
| 21192 | + uint32 mode_winctrl1; /* winctrl1[FRM,CCO,PO,PIPE] */ |
| 21193 | + uint32 mode_winenable; |
| 21194 | + } w[4]; |
| 21195 | +}; |
| 21196 | + |
| 21197 | +struct panel_settings |
| 21198 | +{ |
| 21199 | + unsigned char name[64]; |
| 21200 | + /* panel physical dimensions */ |
| 21201 | + uint32 Xres; |
| 21202 | + uint32 Yres; |
| 21203 | + /* panel timings */ |
| 21204 | + uint32 mode_screen; |
| 21205 | + uint32 mode_horztiming; |
| 21206 | + uint32 mode_verttiming; |
| 21207 | + uint32 mode_clkcontrol; |
| 21208 | + uint32 mode_pwmdiv; |
| 21209 | + uint32 mode_pwmhi; |
| 21210 | + uint32 mode_outmask; |
| 21211 | + uint32 mode_fifoctrl; |
| 21212 | + uint32 mode_toyclksrc; |
| 21213 | + uint32 mode_backlight; |
| 21214 | + uint32 mode_auxpll; |
| 21215 | + int (*device_init)(void); |
| 21216 | + int (*device_shutdown)(void); |
| 21217 | +}; |
| 21218 | + |
| 21219 | +#if defined(__BIG_ENDIAN) |
| 21220 | +#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_00 |
| 21221 | +#else |
| 21222 | +#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01 |
| 21223 | +#endif |
| 21224 | + |
| 21225 | +extern int board_au1200fb_panel (void); |
| 21226 | +extern int board_au1200fb_panel_init (void); |
| 21227 | +extern int board_au1200fb_panel_shutdown (void); |
| 21228 | + |
| 21229 | +#if defined(CONFIG_FOCUS_ENHANCEMENTS) |
| 21230 | +extern int board_au1200fb_focus_init_hdtv(void); |
| 21231 | +extern int board_au1200fb_focus_init_component(void); |
| 21232 | +extern int board_au1200fb_focus_init_cvsv(void); |
| 21233 | +extern int board_au1200fb_focus_shutdown(void); |
| 21234 | +#endif |
| 21235 | + |
| 21236 | +/* |
| 21237 | + * Default window configurations |
| 21238 | + */ |
| 21239 | +static struct window_settings windows[] = |
| 21240 | +{ |
| 21241 | + { /* Index 0 */ |
| 21242 | + "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx", |
| 21243 | + /* mode_backcolor */ 0x006600ff, |
| 21244 | + /* mode_colorkey,msk*/ 0, 0, |
| 21245 | + { |
| 21246 | + { |
| 21247 | + /* xres, yres, xpos, ypos */ 0, 0, 0, 0, |
| 21248 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP, |
| 21249 | + /* mode_winenable*/ LCD_WINENABLE_WEN0, |
| 21250 | + }, |
| 21251 | + { |
| 21252 | + /* xres, yres, xpos, ypos */ 0, 0, 0, 0, |
| 21253 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP, |
| 21254 | + /* mode_winenable*/ 0, |
| 21255 | + }, |
| 21256 | + { |
| 21257 | + /* xres, yres, xpos, ypos */ 0, 0, 0, 0, |
| 21258 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP|LCD_WINCTRL1_PIPE, |
| 21259 | + /* mode_winenable*/ 0, |
| 21260 | + }, |
| 21261 | + { |
| 21262 | + /* xres, yres, xpos, ypos */ 0, 0, 0, 0, |
| 21263 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP|LCD_WINCTRL1_PIPE, |
| 21264 | + /* mode_winenable*/ 0, |
| 21265 | + }, |
| 21266 | + }, |
| 21267 | + }, |
| 21268 | + |
| 21269 | + { /* Index 1 */ |
| 21270 | + "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx", |
| 21271 | + /* mode_backcolor */ 0x006600ff, |
| 21272 | + /* mode_colorkey,msk*/ 0, 0, |
| 21273 | + { |
| 21274 | + { |
| 21275 | + /* xres, yres, xpos, ypos */ 320, 240, 5, 5, |
| 21276 | +#if 0 |
| 21277 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP, |
| 21278 | +#endif |
| 21279 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_24BPP|LCD_WINCTRL1_PO_00, |
| 21280 | + /* mode_winenable*/ LCD_WINENABLE_WEN0, |
| 21281 | + }, |
| 21282 | + { |
| 21283 | + /* xres, yres, xpos, ypos */ 0, 0, 0, 0, |
| 21284 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP, |
| 21285 | + /* mode_winenable*/ 0, |
| 21286 | + }, |
| 21287 | + { |
| 21288 | + /* xres, yres, xpos, ypos */ 100, 100, 0, 0, |
| 21289 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP|LCD_WINCTRL1_PIPE, |
| 21290 | + /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/, |
| 21291 | + }, |
| 21292 | + { |
| 21293 | + /* xres, yres, xpos, ypos */ 200, 25, 0, 0, |
| 21294 | + /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565|LCD_WINCTRL1_PO_16BPP|LCD_WINCTRL1_PIPE, |
| 21295 | + /* mode_winenable*/ 0, |
| 21296 | + }, |
| 21297 | + }, |
| 21298 | + }, |
| 21299 | + /* Need VGA 640 @ 24bpp, @ 32bpp */ |
| 21300 | + /* Need VGA 800 @ 24bpp, @ 32bpp */ |
| 21301 | + /* Need VGA 1024 @ 24bpp, @ 32bpp */ |
| 21302 | +} ; |
| 21303 | + |
| 21304 | +/* |
| 21305 | + * Controller configurations for various panels. |
| 21306 | + */ |
| 21307 | +static struct panel_settings panels[] = |
| 21308 | +{ |
| 21309 | + { /* Index 0: QVGA 320x240 H:33.3kHz V:110Hz */ |
| 21310 | + "VGA_320x240", |
| 21311 | + 320, 240, |
| 21312 | + /* mode_screen */ LCD_SCREEN_SX_N(320) | LCD_SCREEN_SY_N(240), |
| 21313 | + /* mode_horztiming */ 0x00c4623b, |
| 21314 | + /* mode_verttiming */ 0x00502814, |
| 21315 | + /* mode_clkcontrol */ 0x00020002, /* /4=24Mhz */ |
| 21316 | + /* mode_pwmdiv */ 0x00000000, |
| 21317 | + /* mode_pwmhi */ 0x00000000, |
| 21318 | + /* mode_outmask */ 0x00FFFFFF, |
| 21319 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21320 | + /* mode_toyclksrc */ 0x00000004, /* 96MHz AUXPLL directly */ |
| 21321 | + /* mode_backlight */ 0x00000000, |
| 21322 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21323 | + /* device_init */ NULL, |
| 21324 | + /* device_shutdown */ NULL, |
| 21325 | + }, |
| 21326 | + |
| 21327 | + { /* Index 1: VGA 640x480 H:30.3kHz V:58Hz */ |
| 21328 | + "VGA_640x480", |
| 21329 | + 640, 480, |
| 21330 | + /* mode_screen */ 0x13f9df80, |
| 21331 | + /* mode_horztiming */ 0x003c5859, |
| 21332 | + /* mode_verttiming */ 0x00741201, |
| 21333 | + /* mode_clkcontrol */ 0x00020001, /* /4=24Mhz */ |
| 21334 | + /* mode_pwmdiv */ 0x00000000, |
| 21335 | + /* mode_pwmhi */ 0x00000000, |
| 21336 | + /* mode_outmask */ 0x00FFFFFF, |
| 21337 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21338 | + /* mode_toyclksrc */ 0x00000004, /* AUXPLL directly */ |
| 21339 | + /* mode_backlight */ 0x00000000, |
| 21340 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21341 | + /* device_init */ NULL, |
| 21342 | + /* device_shutdown */ NULL, |
| 21343 | + }, |
| 21344 | + |
| 21345 | + { /* Index 2: SVGA 800x600 H:46.1kHz V:69Hz */ |
| 21346 | + "SVGA_800x600", |
| 21347 | + 800, 600, |
| 21348 | + /* mode_screen */ 0x18fa5780, |
| 21349 | + /* mode_horztiming */ 0x00dc7e77, |
| 21350 | + /* mode_verttiming */ 0x00584805, |
| 21351 | + /* mode_clkcontrol */ 0x00020000, /* /2=48Mhz */ |
| 21352 | + /* mode_pwmdiv */ 0x00000000, |
| 21353 | + /* mode_pwmhi */ 0x00000000, |
| 21354 | + /* mode_outmask */ 0x00FFFFFF, |
| 21355 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21356 | + /* mode_toyclksrc */ 0x00000004, /* AUXPLL directly */ |
| 21357 | + /* mode_backlight */ 0x00000000, |
| 21358 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21359 | + /* device_init */ NULL, |
| 21360 | + /* device_shutdown */ NULL, |
| 21361 | + }, |
| 21362 | + |
| 21363 | + { /* Index 3: XVGA 1024x768 H:56.2kHz V:70Hz */ |
| 21364 | + "XVGA_1024x768", |
| 21365 | + 1024, 768, |
| 21366 | + /* mode_screen */ 0x1ffaff80, |
| 21367 | + /* mode_horztiming */ 0x007d0e57, |
| 21368 | + /* mode_verttiming */ 0x00740a01, |
| 21369 | + /* mode_clkcontrol */ 0x000A0000, /* /1 */ |
| 21370 | + /* mode_pwmdiv */ 0x00000000, |
| 21371 | + /* mode_pwmhi */ 0x00000000, |
| 21372 | + /* mode_outmask */ 0x00FFFFFF, |
| 21373 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21374 | + /* mode_toyclksrc */ 0x00000004, /* AUXPLL directly */ |
| 21375 | + /* mode_backlight */ 0x00000000, |
| 21376 | + /* mode_auxpll */ 6, /* 72MHz AUXPLL */ |
| 21377 | + /* device_init */ NULL, |
| 21378 | + /* device_shutdown */ NULL, |
| 21379 | + }, |
| 21380 | + |
| 21381 | + { /* Index 4: XVGA 1280x1024 H:68.5kHz V:65Hz */ |
| 21382 | + "XVGA_1280x1024", |
| 21383 | + 1280, 1024, |
| 21384 | + /* mode_screen */ 0x27fbff80, |
| 21385 | + /* mode_horztiming */ 0x00cdb2c7, |
| 21386 | + /* mode_verttiming */ 0x00600002, |
| 21387 | + /* mode_clkcontrol */ 0x000A0000, /* /1 */ |
| 21388 | + /* mode_pwmdiv */ 0x00000000, |
| 21389 | + /* mode_pwmhi */ 0x00000000, |
| 21390 | + /* mode_outmask */ 0x00FFFFFF, |
| 21391 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21392 | + /* mode_toyclksrc */ 0x00000004, /* AUXPLL directly */ |
| 21393 | + /* mode_backlight */ 0x00000000, |
| 21394 | + /* mode_auxpll */ 10, /* 120MHz AUXPLL */ |
| 21395 | + /* device_init */ NULL, |
| 21396 | + /* device_shutdown */ NULL, |
| 21397 | + }, |
| 21398 | + |
| 21399 | + { /* Index 5: Samsung 1024x768 TFT */ |
| 21400 | + "Samsung_1024x768_TFT", |
| 21401 | + 1024, 768, |
| 21402 | + /* mode_screen */ 0x1ffaff80, |
| 21403 | + /* mode_horztiming */ 0x018cc677, |
| 21404 | + /* mode_verttiming */ 0x00241217, |
| 21405 | + /* mode_clkcontrol */ 0x00000000, /* SCB 0x1 /4=24Mhz */ |
| 21406 | + /* mode_pwmdiv */ 0x8000063f, /* SCB 0x0 */ |
| 21407 | + /* mode_pwmhi */ 0x03400000, /* SCB 0x0 */ |
| 21408 | + /* mode_outmask */ 0x00fcfcfc, |
| 21409 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21410 | + /* mode_toyclksrc */ 0x00000004, /* 96MHz AUXPLL directly */ |
| 21411 | + /* mode_backlight */ 0x00000000, |
| 21412 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21413 | + /* device_init */ board_au1200fb_panel_init, |
| 21414 | + /* device_shutdown */ board_au1200fb_panel_shutdown, |
| 21415 | + }, |
| 21416 | + |
| 21417 | + { /* Index 6: Toshiba 640x480 TFT */ |
| 21418 | + "Toshiba_640x480_TFT", |
| 21419 | + 640, 480, |
| 21420 | + /* mode_screen */ LCD_SCREEN_SX_N(640) | LCD_SCREEN_SY_N(480), |
| 21421 | + /* mode_horztiming */ LCD_HORZTIMING_HPW_N(96) | LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(51), |
| 21422 | + /* mode_verttiming */ LCD_VERTTIMING_VPW_N(2) | LCD_VERTTIMING_VND1_N(11) | LCD_VERTTIMING_VND2_N(32) , |
| 21423 | + /* mode_clkcontrol */ 0x00000000, /* /4=24Mhz */ |
| 21424 | + /* mode_pwmdiv */ 0x8000063f, |
| 21425 | + /* mode_pwmhi */ 0x03400000, |
| 21426 | + /* mode_outmask */ 0x00fcfcfc, |
| 21427 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21428 | + /* mode_toyclksrc */ 0x00000004, /* 96MHz AUXPLL directly */ |
| 21429 | + /* mode_backlight */ 0x00000000, |
| 21430 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21431 | + /* device_init */ board_au1200fb_panel_init, |
| 21432 | + /* device_shutdown */ board_au1200fb_panel_shutdown, |
| 21433 | + }, |
| 21434 | + |
| 21435 | + { /* Index 7: Sharp 320x240 TFT */ |
| 21436 | + "Sharp_320x240_TFT", |
| 21437 | + 320, 240, |
| 21438 | + /* mode_screen */ LCD_SCREEN_SX_N(320) | LCD_SCREEN_SY_N(240), |
| 21439 | + /* mode_horztiming */ LCD_HORZTIMING_HPW_N(60) | LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2), |
| 21440 | + /* mode_verttiming */ LCD_VERTTIMING_VPW_N(2) | LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5) , |
| 21441 | + /* mode_clkcontrol */ LCD_CLKCONTROL_PCD_N(7), /* /16=6Mhz */ |
| 21442 | + /* mode_pwmdiv */ 0x8000063f, |
| 21443 | + /* mode_pwmhi */ 0x03400000, |
| 21444 | + /* mode_outmask */ 0x00fcfcfc, |
| 21445 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21446 | + /* mode_toyclksrc */ 0x00000004, /* 96MHz AUXPLL directly */ |
| 21447 | + /* mode_backlight */ 0x00000000, |
| 21448 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21449 | + /* device_init */ board_au1200fb_panel_init, |
| 21450 | + /* device_shutdown */ board_au1200fb_panel_shutdown, |
| 21451 | + }, |
| 21452 | + { /* Index 8: Toppoly TD070WGCB2 7" 854x480 TFT */ |
| 21453 | + "Toppoly_TD070WGCB2", |
| 21454 | + 854, 480, |
| 21455 | + /* mode_screen */ LCD_SCREEN_SX_N(854) | LCD_SCREEN_SY_N(480), |
| 21456 | + /* mode_horztiming */ LCD_HORZTIMING_HND2_N(44) | LCD_HORZTIMING_HND1_N(44) | LCD_HORZTIMING_HPW_N(114), |
| 21457 | + /* mode_verttiming */ LCD_VERTTIMING_VND2_N(20) | LCD_VERTTIMING_VND1_N(21) | LCD_VERTTIMING_VPW_N(4), |
| 21458 | + /* mode_clkcontrol */ 0x00020001, /* /4=24Mhz */ |
| 21459 | + /* mode_pwmdiv */ 0x8000063f, |
| 21460 | + /* mode_pwmhi */ 0x03400000, |
| 21461 | + /* mode_outmask */ 0x00FCFCFC, |
| 21462 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21463 | + /* mode_toyclksrc */ 0x00000004, /* AUXPLL directly */ |
| 21464 | + /* mode_backlight */ 0x00000000, |
| 21465 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21466 | + /* device_init */ board_au1200fb_panel_init, |
| 21467 | + /* device_shutdown */ board_au1200fb_panel_shutdown, |
| 21468 | + }, |
| 21469 | +#if defined(CONFIG_FOCUS_ENHANCEMENTS) |
| 21470 | + { /* Index 9: Focus FS453 TV-Out 640x480 */ |
| 21471 | + "FS453_640x480 (Composite/S-Video)", |
| 21472 | + 640, 480, |
| 21473 | + /* mode_screen */ LCD_SCREEN_SX_N(640) | LCD_SCREEN_SY_N(480), |
| 21474 | + /* mode_horztiming */ LCD_HORZTIMING_HND2_N(143) | LCD_HORZTIMING_HND1_N(143) | LCD_HORZTIMING_HPW_N(10), |
| 21475 | + /* mode_verttiming */ LCD_VERTTIMING_VND2_N(30) | LCD_VERTTIMING_VND1_N(30) | LCD_VERTTIMING_VPW_N(5), |
| 21476 | + /* mode_clkcontrol */ 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */ |
| 21477 | + /* mode_pwmdiv */ 0x00000000, |
| 21478 | + /* mode_pwmhi */ 0x00000000, |
| 21479 | + /* mode_outmask */ 0x00FFFFFF, |
| 21480 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21481 | + /* mode_toyclksrc */ 0x00000000, |
| 21482 | + /* mode_backlight */ 0x00000000, |
| 21483 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21484 | + /* device_init */ board_au1200fb_focus_init_cvsv, |
| 21485 | + /* device_shutdown */ board_au1200fb_focus_shutdown, |
| 21486 | + }, |
| 21487 | + |
| 21488 | + { /* Index 10: Focus FS453 TV-Out 640x480 */ |
| 21489 | + "FS453_640x480 (Component Video)", |
| 21490 | + 640, 480, |
| 21491 | + /* mode_screen */ LCD_SCREEN_SX_N(640) | LCD_SCREEN_SY_N(480), |
| 21492 | + /* mode_horztiming */ LCD_HORZTIMING_HND2_N(143) | LCD_HORZTIMING_HND1_N(143) | LCD_HORZTIMING_HPW_N(10), |
| 21493 | + /* mode_verttiming */ LCD_VERTTIMING_VND2_N(30) | LCD_VERTTIMING_VND1_N(30) | LCD_VERTTIMING_VPW_N(5), |
| 21494 | + /* mode_clkcontrol */ 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */ |
| 21495 | + /* mode_pwmdiv */ 0x00000000, |
| 21496 | + /* mode_pwmhi */ 0x00000000, |
| 21497 | + /* mode_outmask */ 0x00FFFFFF, |
| 21498 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21499 | + /* mode_toyclksrc */ 0x00000000, |
| 21500 | + /* mode_backlight */ 0x00000000, |
| 21501 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21502 | + /* device_init */ board_au1200fb_focus_init_component, |
| 21503 | + /* device_shutdown */ board_au1200fb_focus_shutdown, |
| 21504 | + }, |
| 21505 | + |
| 21506 | + { /* Index 11: Focus FS453 TV-Out 640x480 */ |
| 21507 | + "FS453_640x480 (HDTV)", |
| 21508 | + 720, 480, |
| 21509 | + /* mode_screen */ LCD_SCREEN_SX_N(720) | LCD_SCREEN_SY_N(480), |
| 21510 | + /* mode_horztiming */ LCD_HORZTIMING_HND2_N(28) | LCD_HORZTIMING_HND1_N(46) | LCD_HORZTIMING_HPW_N(64), |
| 21511 | + /* mode_verttiming */ LCD_VERTTIMING_VND2_N(7) | LCD_VERTTIMING_VND1_N(31) | LCD_VERTTIMING_VPW_N(7), |
| 21512 | + /* mode_clkcontrol */ 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */ |
| 21513 | + /* mode_pwmdiv */ 0x00000000, |
| 21514 | + /* mode_pwmhi */ 0x00000000, |
| 21515 | + /* mode_outmask */ 0x00FFFFFF, |
| 21516 | + /* mode_fifoctrl */ 0x2f2f2f2f, |
| 21517 | + /* mode_toyclksrc */ 0x00000000, |
| 21518 | + /* mode_backlight */ 0x00000000, |
| 21519 | + /* mode_auxpll */ 8, /* 96MHz AUXPLL */ |
| 21520 | + /* device_init */ board_au1200fb_focus_init_hdtv, |
| 21521 | + /* device_shutdown */ board_au1200fb_focus_shutdown, |
| 21522 | + }, |
| 21523 | +#endif |
| 21524 | +}; |
| 21525 | + |
| 21526 | +#define NUM_PANELS (sizeof(panels) / sizeof(struct panel_settings)) |
| 21527 | + |
| 21528 | +static struct window_settings *win; |
| 21529 | +static struct panel_settings *panel; |
| 21530 | + |
| 21531 | +struct au1200fb_info { |
| 21532 | + struct fb_info_gen gen; |
| 21533 | + unsigned long fb_virt_start; |
| 21534 | + unsigned long fb_size; |
| 21535 | + unsigned long fb_phys; |
| 21536 | + int mmaped; |
| 21537 | + int nohwcursor; |
| 21538 | + int noblanking; |
| 21539 | + |
| 21540 | + struct { unsigned red, green, blue, pad; } palette[256]; |
| 21541 | + |
| 21542 | +#if defined(FBCON_HAS_CFB16) |
| 21543 | + u16 fbcon_cmap16[16]; |
| 21544 | +#endif |
| 21545 | +#if defined(FBCON_HAS_CFB32) |
| 21546 | + u32 fbcon_cmap32[16]; |
| 21547 | +#endif |
| 21548 | +}; |
| 21549 | + |
| 21550 | + |
| 21551 | +struct au1200fb_par { |
| 21552 | + struct fb_var_screeninfo var; |
| 21553 | + |
| 21554 | + int line_length; /* in bytes */ |
| 21555 | + int cmap_len; /* color-map length */ |
| 21556 | +}; |
| 21557 | + |
| 21558 | +#ifndef CONFIG_FB_AU1200_DEVS |
| 21559 | +#define CONFIG_FB_AU1200_DEVS 1 |
| 21560 | +#endif |
| 21561 | + |
| 21562 | +static struct au1200fb_info fb_infos[CONFIG_FB_AU1200_DEVS]; |
| 21563 | +static struct au1200fb_par fb_pars[CONFIG_FB_AU1200_DEVS]; |
| 21564 | +static struct display disps[CONFIG_FB_AU1200_DEVS]; |
| 21565 | + |
| 21566 | +int au1200fb_init(void); |
| 21567 | +void au1200fb_setup(char *options, int *ints); |
| 21568 | +static int au1200fb_mmap(struct fb_info *fb, struct file *file, |
| 21569 | + struct vm_area_struct *vma); |
| 21570 | +static int au1200_blank(int blank_mode, struct fb_info_gen *info); |
| 21571 | +static int au1200fb_ioctl(struct inode *inode, struct file *file, u_int cmd, |
| 21572 | + u_long arg, int con, struct fb_info *info); |
| 21573 | + |
| 21574 | +void au1200_nocursor(struct display *p, int mode, int xx, int yy){}; |
| 21575 | + |
| 21576 | +static int au1200_setlocation (int plane, int xpos, int ypos); |
| 21577 | +static int au1200_setsize (int plane, int xres, int yres); |
| 21578 | +static void au1200_setmode(int plane); |
| 21579 | +static void au1200_setpanel (struct panel_settings *newpanel); |
| 21580 | + |
| 21581 | +static struct fb_ops au1200fb_ops = { |
| 21582 | + owner: THIS_MODULE, |
| 21583 | + fb_get_fix: fbgen_get_fix, |
| 21584 | + fb_get_var: fbgen_get_var, |
| 21585 | + fb_set_var: fbgen_set_var, |
| 21586 | + fb_get_cmap: fbgen_get_cmap, |
| 21587 | + fb_set_cmap: fbgen_set_cmap, |
| 21588 | + fb_pan_display: fbgen_pan_display, |
| 21589 | + fb_ioctl: au1200fb_ioctl, |
| 21590 | + fb_mmap: au1200fb_mmap, |
| 21591 | +}; |
| 21592 | + |
| 21593 | + |
| 21594 | +static int |
| 21595 | +winbpp (unsigned int winctrl1) |
| 21596 | +{ |
| 21597 | + /* how many bytes of memory are needed for each pixel format */ |
| 21598 | + switch (winctrl1 & LCD_WINCTRL1_FRM) |
| 21599 | + { |
| 21600 | + case LCD_WINCTRL1_FRM_1BPP: return 1; break; |
| 21601 | + case LCD_WINCTRL1_FRM_2BPP: return 2; break; |
| 21602 | + case LCD_WINCTRL1_FRM_4BPP: return 4; break; |
| 21603 | + case LCD_WINCTRL1_FRM_8BPP: return 8; break; |
| 21604 | + case LCD_WINCTRL1_FRM_12BPP: return 16; break; |
| 21605 | + case LCD_WINCTRL1_FRM_16BPP655: return 16; break; |
| 21606 | + case LCD_WINCTRL1_FRM_16BPP565: return 16; break; |
| 21607 | + case LCD_WINCTRL1_FRM_16BPP556: return 16; break; |
| 21608 | + case LCD_WINCTRL1_FRM_16BPPI1555: return 16; break; |
| 21609 | + case LCD_WINCTRL1_FRM_16BPPI5551: return 16; break; |
| 21610 | + case LCD_WINCTRL1_FRM_16BPPA1555: return 16; break; |
| 21611 | + case LCD_WINCTRL1_FRM_16BPPA5551: return 16; break; |
| 21612 | + case LCD_WINCTRL1_FRM_24BPP: return 32; break; |
| 21613 | + case LCD_WINCTRL1_FRM_32BPP: return 32; break; |
| 21614 | + default: return 0; break; |
| 21615 | + } |
| 21616 | +} |
| 21617 | + |
| 21618 | +static int |
| 21619 | +fbinfo2index (struct fb_info *fb_info) |
| 21620 | +{ |
| 21621 | + int i; |
| 21622 | + for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i) |
| 21623 | + { |
| 21624 | + if (fb_info == (struct fb_info *)(&fb_infos[i])) |
| 21625 | + return i; |
| 21626 | + } |
| 21627 | + printk("au1200fb: ERROR: fbinfo2index failed!\n"); |
| 21628 | + return -1; |
| 21629 | +} |
| 21630 | + |
| 21631 | +static void au1200_detect(void) |
| 21632 | +{ |
| 21633 | + /* |
| 21634 | + * This function should detect the current video mode settings |
| 21635 | + * and store it as the default video mode |
| 21636 | + * Yeh, well, we're not going to change any settings so we're |
| 21637 | + * always stuck with the default ... |
| 21638 | + */ |
| 21639 | +} |
| 21640 | + |
| 21641 | +static int au1200_encode_fix(struct fb_fix_screeninfo *fix, |
| 21642 | + const void *_par, struct fb_info_gen *_info) |
| 21643 | +{ |
| 21644 | + struct au1200fb_info *info = (struct au1200fb_info *) _info; |
| 21645 | + struct au1200fb_par *par = (struct au1200fb_par *) _par; |
| 21646 | + int plane; |
| 21647 | + |
| 21648 | + plane = fbinfo2index(info); |
| 21649 | + |
| 21650 | + memset(fix, 0, sizeof(struct fb_fix_screeninfo)); |
| 21651 | + |
| 21652 | + fix->smem_start = info->fb_phys; |
| 21653 | + fix->smem_len = info->fb_size; |
| 21654 | + fix->type = FB_TYPE_PACKED_PIXELS; |
| 21655 | + fix->type_aux = 0; |
| 21656 | + fix->visual = (par->var.bits_per_pixel == 8) ? |
| 21657 | + FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
| 21658 | + fix->ywrapstep = 0; |
| 21659 | + fix->xpanstep = 1; |
| 21660 | + fix->ypanstep = 1; |
| 21661 | + /* FIX!!!! why doesn't par->line_length work???? it does for au1100 */ |
| 21662 | + fix->line_length = fb_pars[plane].line_length; /*par->line_length;*/ |
| 21663 | + return 0; |
| 21664 | +} |
| 21665 | + |
| 21666 | +static void set_color_bitfields(struct fb_var_screeninfo *var, int plane) |
| 21667 | +{ |
| 21668 | + if (var->bits_per_pixel == 8) |
| 21669 | + { |
| 21670 | + var->red.offset = 0; |
| 21671 | + var->red.length = 8; |
| 21672 | + var->green.offset = 0; |
| 21673 | + var->green.length = 8; |
| 21674 | + var->blue.offset = 0; |
| 21675 | + var->blue.length = 8; |
| 21676 | + var->transp.offset = 0; |
| 21677 | + var->transp.length = 0; |
| 21678 | + } |
| 21679 | + else |
| 21680 | + |
| 21681 | + if (var->bits_per_pixel == 16) |
| 21682 | + { |
| 21683 | + /* FIX!!! How does CCO affect this ? */ |
| 21684 | + /* FIX!!! Not exactly sure how many of these work with FB */ |
| 21685 | + switch (win->w[plane].mode_winctrl1 & LCD_WINCTRL1_FRM) |
| 21686 | + { |
| 21687 | + case LCD_WINCTRL1_FRM_16BPP655: |
| 21688 | + var->red.offset = 10; |
| 21689 | + var->red.length = 6; |
| 21690 | + var->green.offset = 5; |
| 21691 | + var->green.length = 5; |
| 21692 | + var->blue.offset = 0; |
| 21693 | + var->blue.length = 5; |
| 21694 | + var->transp.offset = 0; |
| 21695 | + var->transp.length = 0; |
| 21696 | + break; |
| 21697 | + |
| 21698 | + case LCD_WINCTRL1_FRM_16BPP565: |
| 21699 | + var->red.offset = 11; |
| 21700 | + var->red.length = 5; |
| 21701 | + var->green.offset = 5; |
| 21702 | + var->green.length = 6; |
| 21703 | + var->blue.offset = 0; |
| 21704 | + var->blue.length = 5; |
| 21705 | + var->transp.offset = 0; |
| 21706 | + var->transp.length = 0; |
| 21707 | + break; |
| 21708 | + |
| 21709 | + case LCD_WINCTRL1_FRM_16BPP556: |
| 21710 | + var->red.offset = 11; |
| 21711 | + var->red.length = 5; |
| 21712 | + var->green.offset = 6; |
| 21713 | + var->green.length = 5; |
| 21714 | + var->blue.offset = 0; |
| 21715 | + var->blue.length = 6; |
| 21716 | + var->transp.offset = 0; |
| 21717 | + var->transp.length = 0; |
| 21718 | + break; |
| 21719 | + |
| 21720 | + case LCD_WINCTRL1_FRM_16BPPI1555: |
| 21721 | + var->red.offset = 10; |
| 21722 | + var->red.length = 5; |
| 21723 | + var->green.offset = 5; |
| 21724 | + var->green.length = 5; |
| 21725 | + var->blue.offset = 0; |
| 21726 | + var->blue.length = 5; |
| 21727 | + var->transp.offset = 0; |
| 21728 | + var->transp.length = 0; |
| 21729 | + break; |
| 21730 | + |
| 21731 | + case LCD_WINCTRL1_FRM_16BPPI5551: |
| 21732 | + var->red.offset = 11; |
| 21733 | + var->red.length = 5; |
| 21734 | + var->green.offset = 6; |
| 21735 | + var->green.length = 5; |
| 21736 | + var->blue.offset = 1; |
| 21737 | + var->blue.length = 5; |
| 21738 | + var->transp.offset = 0; |
| 21739 | + var->transp.length = 0; |
| 21740 | + break; |
| 21741 | + |
| 21742 | + case LCD_WINCTRL1_FRM_16BPPA1555: |
| 21743 | + var->red.offset = 10; |
| 21744 | + var->red.length = 5; |
| 21745 | + var->green.offset = 5; |
| 21746 | + var->green.length = 5; |
| 21747 | + var->blue.offset = 0; |
| 21748 | + var->blue.length = 5; |
| 21749 | + var->transp.offset = 15; |
| 21750 | + var->transp.length = 1; |
| 21751 | + break; |
| 21752 | + |
| 21753 | + case LCD_WINCTRL1_FRM_16BPPA5551: |
| 21754 | + var->red.offset = 11; |
| 21755 | + var->red.length = 5; |
| 21756 | + var->green.offset = 6; |
| 21757 | + var->green.length = 5; |
| 21758 | + var->blue.offset = 1; |
| 21759 | + var->blue.length = 5; |
| 21760 | + var->transp.offset = 0; |
| 21761 | + var->transp.length = 1; |
| 21762 | + break; |
| 21763 | + |
| 21764 | + default: |
| 21765 | + printk("ERROR: Invalid PIXEL FORMAT!!!\n"); break; |
| 21766 | + } |
| 21767 | + } |
| 21768 | + else |
| 21769 | + |
| 21770 | + if (var->bits_per_pixel == 32) |
| 21771 | + { |
| 21772 | + switch (win->w[plane].mode_winctrl1 & LCD_WINCTRL1_FRM) |
| 21773 | + { |
| 21774 | + case LCD_WINCTRL1_FRM_24BPP: |
| 21775 | + var->red.offset = 16; |
| 21776 | + var->red.length = 8; |
| 21777 | + var->green.offset = 8; |
| 21778 | + var->green.length = 8; |
| 21779 | + var->blue.offset = 0; |
| 21780 | + var->blue.length = 8; |
| 21781 | + var->transp.offset = 0; |
| 21782 | + var->transp.length = 0; |
| 21783 | + break; |
| 21784 | + |
| 21785 | + case LCD_WINCTRL1_FRM_32BPP: |
| 21786 | + var->red.offset = 16; |
| 21787 | + var->red.length = 8; |
| 21788 | + var->green.offset = 8; |
| 21789 | + var->green.length = 8; |
| 21790 | + var->blue.offset = 0; |
| 21791 | + var->blue.length = 8; |
| 21792 | + var->transp.offset = 24; |
| 21793 | + var->transp.length = 8; |
| 21794 | + break; |
| 21795 | + } |
| 21796 | + } |
| 21797 | + var->red.msb_right = 0; |
| 21798 | + var->green.msb_right = 0; |
| 21799 | + var->blue.msb_right = 0; |
| 21800 | + var->transp.msb_right = 0; |
| 21801 | +#if 0 |
| 21802 | +printk("set_color_bitfields(a=%d, r=%d..%d, g=%d..%d, b=%d..%d)\n", |
| 21803 | + var->transp.offset, |
| 21804 | + var->red.offset+var->red.length-1, var->red.offset, |
| 21805 | + var->green.offset+var->green.length-1, var->green.offset, |
| 21806 | + var->blue.offset+var->blue.length-1, var->blue.offset); |
| 21807 | +#endif |
| 21808 | +} |
| 21809 | + |
| 21810 | +static int au1200_decode_var(const struct fb_var_screeninfo *var, |
| 21811 | + void *_par, struct fb_info_gen *_info) |
| 21812 | +{ |
| 21813 | + struct au1200fb_par *par = (struct au1200fb_par *)_par; |
| 21814 | + int plane, bpp; |
| 21815 | + |
| 21816 | + plane = fbinfo2index((struct fb_info *)_info); |
| 21817 | + |
| 21818 | + /* |
| 21819 | + * Don't allow setting any of these yet: xres and yres don't |
| 21820 | + * make sense for LCD panels. |
| 21821 | + */ |
| 21822 | + if (var->xres != win->w[plane].xres || |
| 21823 | + var->yres != win->w[plane].yres || |
| 21824 | + var->xres != win->w[plane].xres || |
| 21825 | + var->yres != win->w[plane].yres) { |
| 21826 | + return -EINVAL; |
| 21827 | + } |
| 21828 | + |
| 21829 | + bpp = winbpp(win->w[plane].mode_winctrl1); |
| 21830 | + if(var->bits_per_pixel != bpp) { |
| 21831 | + /* on au1200, window pixel format is independent of panel pixel */ |
| 21832 | + printk("WARNING: bits_per_pizel != panel->bpp\n"); |
| 21833 | + } |
| 21834 | + |
| 21835 | + memset(par, 0, sizeof(struct au1200fb_par)); |
| 21836 | + par->var = *var; |
| 21837 | + |
| 21838 | + /* FIX!!! */ |
| 21839 | + switch (var->bits_per_pixel) { |
| 21840 | + case 8: |
| 21841 | + par->var.bits_per_pixel = 8; |
| 21842 | + break; |
| 21843 | + case 16: |
| 21844 | + par->var.bits_per_pixel = 16; |
| 21845 | + break; |
| 21846 | + case 24: |
| 21847 | + case 32: |
| 21848 | + par->var.bits_per_pixel = 32; |
| 21849 | + break; |
| 21850 | + default: |
| 21851 | + printk("color depth %d bpp not supported\n", |
| 21852 | + var->bits_per_pixel); |
| 21853 | + return -EINVAL; |
| 21854 | + |
| 21855 | + } |
| 21856 | + set_color_bitfields(&par->var, plane); |
| 21857 | + /* FIX!!! what is this for 24/32bpp? */ |
| 21858 | + par->cmap_len = (par->var.bits_per_pixel == 8) ? 256 : 16; |
| 21859 | + return 0; |
| 21860 | +} |
| 21861 | + |
| 21862 | +static int au1200_encode_var(struct fb_var_screeninfo *var, |
| 21863 | + const void *par, struct fb_info_gen *_info) |
| 21864 | +{ |
| 21865 | + *var = ((struct au1200fb_par *)par)->var; |
| 21866 | + return 0; |
| 21867 | +} |
| 21868 | + |
| 21869 | +static void |
| 21870 | +au1200_get_par(void *_par, struct fb_info_gen *_info) |
| 21871 | +{ |
| 21872 | + int index; |
| 21873 | + |
| 21874 | + index = fbinfo2index((struct fb_info *)_info); |
| 21875 | + *(struct au1200fb_par *)_par = fb_pars[index]; |
| 21876 | +} |
| 21877 | + |
| 21878 | +static void au1200_set_par(const void *par, struct fb_info_gen *info) |
| 21879 | +{ |
| 21880 | + /* nothing to do: we don't change any settings */ |
| 21881 | +} |
| 21882 | + |
| 21883 | +static int au1200_getcolreg(unsigned regno, unsigned *red, unsigned *green, |
| 21884 | + unsigned *blue, unsigned *transp, |
| 21885 | + struct fb_info *info) |
| 21886 | +{ |
| 21887 | + struct au1200fb_info* i = (struct au1200fb_info*)info; |
| 21888 | + |
| 21889 | + if (regno > 255) |
| 21890 | + return 1; |
| 21891 | + |
| 21892 | + *red = i->palette[regno].red; |
| 21893 | + *green = i->palette[regno].green; |
| 21894 | + *blue = i->palette[regno].blue; |
| 21895 | + *transp = 0; |
| 21896 | + |
| 21897 | + return 0; |
| 21898 | +} |
| 21899 | + |
| 21900 | +static int au1200_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 21901 | + unsigned blue, unsigned transp, |
| 21902 | + struct fb_info *info) |
| 21903 | +{ |
| 21904 | + struct au1200fb_info* i = (struct au1200fb_info *)info; |
| 21905 | + u32 rgbcol; |
| 21906 | + int plane, bpp; |
| 21907 | + |
| 21908 | + plane = fbinfo2index((struct fb_info *)info); |
| 21909 | + bpp = winbpp(win->w[plane].mode_winctrl1); |
| 21910 | + |
| 21911 | + if (regno > 255) |
| 21912 | + return 1; |
| 21913 | + |
| 21914 | + i->palette[regno].red = red; |
| 21915 | + i->palette[regno].green = green; |
| 21916 | + i->palette[regno].blue = blue; |
| 21917 | + |
| 21918 | + switch(bpp) { |
| 21919 | +#ifdef FBCON_HAS_CFB8 |
| 21920 | + case 8: |
| 21921 | + red >>= 10; |
| 21922 | + green >>= 10; |
| 21923 | + blue >>= 10; |
| 21924 | + panel_reg->lcd_pallettebase[regno] = (blue&0x1f) | |
| 21925 | + ((green&0x3f)<<5) | ((red&0x1f)<<11); |
| 21926 | + break; |
| 21927 | +#endif |
| 21928 | +#ifdef FBCON_HAS_CFB16 |
| 21929 | +/* FIX!!!! depends upon pixel format */ |
| 21930 | + case 16: |
| 21931 | + i->fbcon_cmap16[regno] = |
| 21932 | + ((red & 0xf800) >> 0) | |
| 21933 | + ((green & 0xfc00) >> 5) | |
| 21934 | + ((blue & 0xf800) >> 11); |
| 21935 | + break; |
| 21936 | +#endif |
| 21937 | +#ifdef FBCON_HAS_CFB32 |
| 21938 | + case 32: |
| 21939 | + i->fbcon_cmap32[regno] = |
| 21940 | + (((u32 )transp & 0xff00) << 16) | |
| 21941 | + (((u32 )red & 0xff00) << 8) | |
| 21942 | + (((u32 )green & 0xff00)) | |
| 21943 | + (((u32 )blue & 0xff00) >> 8); |
| 21944 | + break; |
| 21945 | +#endif |
| 21946 | + default: |
| 21947 | + printk("unsupported au1200_setcolreg(%d)\n", bpp); |
| 21948 | + break; |
| 21949 | + } |
| 21950 | + |
| 21951 | + return 0; |
| 21952 | +} |
| 21953 | + |
| 21954 | + |
| 21955 | +static int au1200_blank(int blank_mode, struct fb_info_gen *_info) |
| 21956 | +{ |
| 21957 | + struct au1200fb_info *fb_info = (struct au1200fb_info *)_info; |
| 21958 | + int plane; |
| 21959 | + |
| 21960 | + /* Short-circuit screen blanking */ |
| 21961 | + if (fb_info->noblanking) |
| 21962 | + return 0; |
| 21963 | + |
| 21964 | + plane = fbinfo2index((struct fb_info *)_info); |
| 21965 | + |
| 21966 | + switch (blank_mode) { |
| 21967 | + case VESA_NO_BLANKING: |
| 21968 | + /* printk("turn on panel\n"); */ |
| 21969 | + au1200_setpanel(panel); |
| 21970 | + break; |
| 21971 | + |
| 21972 | + case VESA_VSYNC_SUSPEND: |
| 21973 | + case VESA_HSYNC_SUSPEND: |
| 21974 | + case VESA_POWERDOWN: |
| 21975 | + /* printk("turn off panel\n"); */ |
| 21976 | + au1200_setpanel(NULL); |
| 21977 | + break; |
| 21978 | + default: |
| 21979 | + break; |
| 21980 | + |
| 21981 | + } |
| 21982 | + return 0; |
| 21983 | +} |
| 21984 | + |
| 21985 | +static void au1200_set_disp(const void *unused, struct display *disp, |
| 21986 | + struct fb_info_gen *info) |
| 21987 | +{ |
| 21988 | + struct au1200fb_info *fb_info; |
| 21989 | + int plane; |
| 21990 | + |
| 21991 | + fb_info = (struct au1200fb_info *)info; |
| 21992 | + |
| 21993 | + disp->screen_base = (char *)fb_info->fb_virt_start; |
| 21994 | + |
| 21995 | + switch (disp->var.bits_per_pixel) { |
| 21996 | +#ifdef FBCON_HAS_CFB8 |
| 21997 | + case 8: |
| 21998 | + disp->dispsw = &fbcon_cfb8; |
| 21999 | + if (fb_info->nohwcursor) |
| 22000 | + fbcon_cfb8.cursor = au1200_nocursor; |
| 22001 | + break; |
| 22002 | +#endif |
| 22003 | +#ifdef FBCON_HAS_CFB16 |
| 22004 | + case 16: |
| 22005 | + disp->dispsw = &fbcon_cfb16; |
| 22006 | + disp->dispsw_data = fb_info->fbcon_cmap16; |
| 22007 | + if (fb_info->nohwcursor) |
| 22008 | + fbcon_cfb16.cursor = au1200_nocursor; |
| 22009 | + break; |
| 22010 | +#endif |
| 22011 | +#ifdef FBCON_HAS_CFB32 |
| 22012 | + case 32: |
| 22013 | + disp->dispsw = &fbcon_cfb32; |
| 22014 | + disp->dispsw_data = fb_info->fbcon_cmap32; |
| 22015 | + if (fb_info->nohwcursor) |
| 22016 | + fbcon_cfb32.cursor = au1200_nocursor; |
| 22017 | + break; |
| 22018 | +#endif |
| 22019 | + default: |
| 22020 | + disp->dispsw = &fbcon_dummy; |
| 22021 | + disp->dispsw_data = NULL; |
| 22022 | + break; |
| 22023 | + } |
| 22024 | +} |
| 22025 | + |
| 22026 | +static int |
| 22027 | +au1200fb_mmap(struct fb_info *_fb, |
| 22028 | + struct file *file, |
| 22029 | + struct vm_area_struct *vma) |
| 22030 | +{ |
| 22031 | + unsigned int len; |
| 22032 | + unsigned long start=0, off; |
| 22033 | + |
| 22034 | + struct au1200fb_info *fb_info = (struct au1200fb_info *)_fb; |
| 22035 | + |
| 22036 | + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { |
| 22037 | + return -EINVAL; |
| 22038 | + } |
| 22039 | + |
| 22040 | + start = fb_info->fb_phys & PAGE_MASK; |
| 22041 | + len = PAGE_ALIGN((start & ~PAGE_MASK) + fb_info->fb_size); |
| 22042 | + |
| 22043 | + off = vma->vm_pgoff << PAGE_SHIFT; |
| 22044 | + |
| 22045 | + if ((vma->vm_end - vma->vm_start + off) > len) { |
| 22046 | + return -EINVAL; |
| 22047 | + } |
| 22048 | + |
| 22049 | + off += start; |
| 22050 | + vma->vm_pgoff = off >> PAGE_SHIFT; |
| 22051 | + |
| 22052 | + pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; |
| 22053 | + pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED; |
| 22054 | + |
| 22055 | + /* This is an IO map - tell maydump to skip this VMA */ |
| 22056 | + vma->vm_flags |= VM_IO; |
| 22057 | + |
| 22058 | + if (io_remap_page_range(vma->vm_start, off, |
| 22059 | + vma->vm_end - vma->vm_start, |
| 22060 | + vma->vm_page_prot)) { |
| 22061 | + return -EAGAIN; |
| 22062 | + } |
| 22063 | + |
| 22064 | + fb_info->mmaped = 1; |
| 22065 | + return 0; |
| 22066 | +} |
| 22067 | + |
| 22068 | +int au1200_pan_display(const struct fb_var_screeninfo *var, |
| 22069 | + struct fb_info_gen *info) |
| 22070 | +{ |
| 22071 | + return 0; |
| 22072 | +} |
| 22073 | + |
| 22074 | + |
| 22075 | +static int au1200fb_ioctl(struct inode *inode, struct file *file, u_int cmd, |
| 22076 | + u_long arg, int con, struct fb_info *info) |
| 22077 | +{ |
| 22078 | + int plane; |
| 22079 | + |
| 22080 | + plane = fbinfo2index(info); |
| 22081 | + |
| 22082 | + /* printk("au1200fb: ioctl %d on plane %d\n", cmd, plane); */ |
| 22083 | + |
| 22084 | + if (cmd == 0x46FF) |
| 22085 | + { |
| 22086 | + au1200_lcd_getset_t iodata; |
| 22087 | + |
| 22088 | + if (copy_from_user(&iodata, (void *) arg, sizeof(au1200_lcd_getset_t))) |
| 22089 | + return -EFAULT; |
| 22090 | + |
| 22091 | + switch (iodata.subcmd) |
| 22092 | + { |
| 22093 | + case AU1200_LCD_GET_WINENABLE: |
| 22094 | + iodata.winenable.enable = (lcd->winenable & (1<<plane)) ? 1 : 0; |
| 22095 | + break; |
| 22096 | + case AU1200_LCD_SET_WINENABLE: |
| 22097 | + { |
| 22098 | + u32 winenable; |
| 22099 | + winenable = lcd->winenable; |
| 22100 | + winenable &= ~(1<<plane); |
| 22101 | + winenable |= (iodata.winenable.enable) ? (1<<plane) : 0; |
| 22102 | + lcd->winenable = winenable; |
| 22103 | + } |
| 22104 | + break; |
| 22105 | + case AU1200_LCD_GET_WINLOCATION: |
| 22106 | + iodata.winlocation.x = |
| 22107 | + (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OX) >> 21; |
| 22108 | + iodata.winlocation.y = |
| 22109 | + (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OY) >> 10; |
| 22110 | + break; |
| 22111 | + case AU1200_LCD_SET_WINLOCATION: |
| 22112 | + au1200_setlocation(plane, iodata.winlocation.x, iodata.winlocation.y); |
| 22113 | + break; |
| 22114 | + case AU1200_LCD_GET_WINSIZE: |
| 22115 | + iodata.winsize.hsz = |
| 22116 | + (lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZX) >> 11; |
| 22117 | + iodata.winsize.vsz = |
| 22118 | + (lcd->window[plane].winctrl0 & LCD_WINCTRL1_SZY) >> 0; |
| 22119 | + break; |
| 22120 | + case AU1200_LCD_SET_WINSIZE: |
| 22121 | + au1200_setsize(plane, iodata.winsize.hsz, iodata.winsize.vsz); |
| 22122 | + break; |
| 22123 | + case AU1200_LCD_GET_BACKCOLOR: |
| 22124 | + iodata.backcolor.color = lcd->backcolor; |
| 22125 | + break; |
| 22126 | + case AU1200_LCD_SET_BACKCOLOR: |
| 22127 | + lcd->backcolor = iodata.backcolor.color; |
| 22128 | + break; |
| 22129 | + case AU1200_LCD_GET_COLORKEY: |
| 22130 | + iodata.colorkey.key = lcd->colorkey; |
| 22131 | + iodata.colorkey.mask = lcd->colorkeymsk; |
| 22132 | + break; |
| 22133 | + case AU1200_LCD_SET_COLORKEY: |
| 22134 | + lcd->colorkey = iodata.colorkey.key; |
| 22135 | + lcd->colorkeymsk = iodata.colorkey.mask; |
| 22136 | + break; |
| 22137 | + case AU1200_LCD_GET_PANEL: |
| 22138 | + iodata.panel.panel = panel_index; |
| 22139 | + break; |
| 22140 | + case AU1200_LCD_SET_PANEL: |
| 22141 | + if ((iodata.panel.panel >= 0) && (iodata.panel.panel < NUM_PANELS)) |
| 22142 | + { |
| 22143 | + struct panel_settings *newpanel; |
| 22144 | + panel_index = iodata.panel.panel; |
| 22145 | + newpanel = &panels[panel_index]; |
| 22146 | + au1200_setpanel(newpanel); |
| 22147 | + } |
| 22148 | + break; |
| 22149 | + } |
| 22150 | + |
| 22151 | + return copy_to_user((void *) arg, &iodata, sizeof(au1200_lcd_getset_t)) ? -EFAULT : 0; |
| 22152 | + } |
| 22153 | + |
| 22154 | + return -EINVAL; |
| 22155 | +} |
| 22156 | + |
| 22157 | +static struct fbgen_hwswitch au1200_switch = { |
| 22158 | + au1200_detect, |
| 22159 | + au1200_encode_fix, |
| 22160 | + au1200_decode_var, |
| 22161 | + au1200_encode_var, |
| 22162 | + au1200_get_par, |
| 22163 | + au1200_set_par, |
| 22164 | + au1200_getcolreg, |
| 22165 | + au1200_setcolreg, |
| 22166 | + au1200_pan_display, |
| 22167 | + au1200_blank, |
| 22168 | + au1200_set_disp |
| 22169 | +}; |
| 22170 | + |
| 22171 | +static void au1200_setpanel (struct panel_settings *newpanel) |
| 22172 | +{ |
| 22173 | + /* |
| 22174 | + * Perform global setup/init of LCD controller |
| 22175 | + */ |
| 22176 | + uint32 winenable; |
| 22177 | + |
| 22178 | + /* Make sure all windows disabled */ |
| 22179 | + winenable = lcd->winenable; |
| 22180 | + lcd->winenable = 0; |
| 22181 | + |
| 22182 | + /* |
| 22183 | + * Ensure everything is disabled before reconfiguring |
| 22184 | + */ |
| 22185 | + if (lcd->screen & LCD_SCREEN_SEN) |
| 22186 | + { |
| 22187 | + /* Wait for vertical sync period */ |
| 22188 | + lcd->intstatus = LCD_INT_SS; |
| 22189 | + while ((lcd->intstatus & LCD_INT_SS) == 0) |
| 22190 | + ; |
| 22191 | + |
| 22192 | + lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/ |
| 22193 | + |
| 22194 | + do |
| 22195 | + { |
| 22196 | + lcd->intstatus = lcd->intstatus; /*clear interrupts*/ |
| 22197 | + } |
| 22198 | + /*wait for controller to shut down*/ |
| 22199 | + while ((lcd->intstatus & LCD_INT_SD) == 0); |
| 22200 | + |
| 22201 | + /* Call shutdown of current panel (if up) */ |
| 22202 | + /* this must occur last, because if an external clock is driving |
| 22203 | + the controller, the clock cannot be turned off before first |
| 22204 | + shutting down the controller. |
| 22205 | + */ |
| 22206 | + if (panel->device_shutdown != NULL) panel->device_shutdown(); |
| 22207 | + } |
| 22208 | + |
| 22209 | + /* Check if only needing to turn off panel */ |
| 22210 | + if (panel == NULL) return; |
| 22211 | + |
| 22212 | + panel = newpanel; |
| 22213 | + |
| 22214 | + printk("Panel(%s), %dx%d\n", panel->name, panel->Xres, panel->Yres); |
| 22215 | + |
| 22216 | + /* |
| 22217 | + * Setup clocking if internal LCD clock source (assumes sys_auxpll valid) |
| 22218 | + */ |
| 22219 | + if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT)) |
| 22220 | + { |
| 22221 | + uint32 sys_clksrc; |
| 22222 | + /* WARNING! This should really be a check since other peripherals can |
| 22223 | + be affected by changins sys_auxpll */ |
| 22224 | + au_writel(panel->mode_auxpll, SYS_AUXPLL); |
| 22225 | + sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f; |
| 22226 | + sys_clksrc |= panel->mode_toyclksrc; |
| 22227 | + au_writel(sys_clksrc, SYS_CLKSRC); |
| 22228 | + } |
| 22229 | + |
| 22230 | + /* |
| 22231 | + * Configure panel timings |
| 22232 | + */ |
| 22233 | + lcd->screen = panel->mode_screen; |
| 22234 | + lcd->horztiming = panel->mode_horztiming; |
| 22235 | + lcd->verttiming = panel->mode_verttiming; |
| 22236 | + lcd->clkcontrol = panel->mode_clkcontrol; |
| 22237 | + lcd->pwmdiv = panel->mode_pwmdiv; |
| 22238 | + lcd->pwmhi = panel->mode_pwmhi; |
| 22239 | + lcd->outmask = panel->mode_outmask; |
| 22240 | + lcd->fifoctrl = panel->mode_fifoctrl; |
| 22241 | + au_sync(); |
| 22242 | + |
| 22243 | + /* FIX!!! Check window settings to make sure still valid for new geometry */ |
| 22244 | + au1200_setlocation(0, win->w[0].xpos, win->w[0].ypos); |
| 22245 | + au1200_setlocation(1, win->w[1].xpos, win->w[1].ypos); |
| 22246 | + au1200_setlocation(2, win->w[2].xpos, win->w[2].ypos); |
| 22247 | + au1200_setlocation(3, win->w[3].xpos, win->w[3].ypos); |
| 22248 | + lcd->winenable = winenable; |
| 22249 | + |
| 22250 | + /* |
| 22251 | + * Re-enable screen now that it is configured |
| 22252 | + */ |
| 22253 | + lcd->screen |= LCD_SCREEN_SEN; |
| 22254 | + au_sync(); |
| 22255 | + |
| 22256 | + /* Call init of panel */ |
| 22257 | + if (panel->device_init != NULL) panel->device_init(); |
| 22258 | + |
| 22259 | +#if 0 |
| 22260 | +#define D(X) printk("%25s: %08X\n", #X, X) |
| 22261 | + D(lcd->screen); |
| 22262 | + D(lcd->horztiming); |
| 22263 | + D(lcd->verttiming); |
| 22264 | + D(lcd->clkcontrol); |
| 22265 | + D(lcd->pwmdiv); |
| 22266 | + D(lcd->pwmhi); |
| 22267 | + D(lcd->outmask); |
| 22268 | + D(lcd->fifoctrl); |
| 22269 | + D(lcd->window[0].winctrl0); |
| 22270 | + D(lcd->window[0].winctrl1); |
| 22271 | + D(lcd->window[0].winctrl2); |
| 22272 | + D(lcd->window[0].winbuf0); |
| 22273 | + D(lcd->window[0].winbuf1); |
| 22274 | + D(lcd->window[0].winbufctrl); |
| 22275 | + D(lcd->window[1].winctrl0); |
| 22276 | + D(lcd->window[1].winctrl1); |
| 22277 | + D(lcd->window[1].winctrl2); |
| 22278 | + D(lcd->window[1].winbuf0); |
| 22279 | + D(lcd->window[1].winbuf1); |
| 22280 | + D(lcd->window[1].winbufctrl); |
| 22281 | + D(lcd->window[2].winctrl0); |
| 22282 | + D(lcd->window[2].winctrl1); |
| 22283 | + D(lcd->window[2].winctrl2); |
| 22284 | + D(lcd->window[2].winbuf0); |
| 22285 | + D(lcd->window[2].winbuf1); |
| 22286 | + D(lcd->window[2].winbufctrl); |
| 22287 | + D(lcd->window[3].winctrl0); |
| 22288 | + D(lcd->window[3].winctrl1); |
| 22289 | + D(lcd->window[3].winctrl2); |
| 22290 | + D(lcd->window[3].winbuf0); |
| 22291 | + D(lcd->window[3].winbuf1); |
| 22292 | + D(lcd->window[3].winbufctrl); |
| 22293 | + D(lcd->winenable); |
| 22294 | + D(lcd->intenable); |
| 22295 | + D(lcd->intstatus); |
| 22296 | + D(lcd->backcolor); |
| 22297 | + D(lcd->winenable); |
| 22298 | + D(lcd->colorkey); |
| 22299 | + D(lcd->colorkeymsk); |
| 22300 | + D(lcd->hwc.cursorctrl); |
| 22301 | + D(lcd->hwc.cursorpos); |
| 22302 | + D(lcd->hwc.cursorcolor0); |
| 22303 | + D(lcd->hwc.cursorcolor1); |
| 22304 | + D(lcd->hwc.cursorcolor2); |
| 22305 | + D(lcd->hwc.cursorcolor3); |
| 22306 | +#endif |
| 22307 | +} |
| 22308 | + |
| 22309 | +static int au1200_setsize (int plane, int xres, int yres) |
| 22310 | +{ |
| 22311 | +#if 0 |
| 22312 | + uint32 winctrl0, winctrl1, winenable; |
| 22313 | + int xsz, ysz; |
| 22314 | + |
| 22315 | + /* FIX!!! X*Y can not surpass allocated memory */ |
| 22316 | + |
| 22317 | + printk("setsize: x %d y %d\n", xres, yres); |
| 22318 | + winctrl1 = lcd->window[plane].winctrl1; |
| 22319 | + printk("org winctrl1 %08X\n", winctrl1); |
| 22320 | + winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY); |
| 22321 | + |
| 22322 | + xres -= 1; |
| 22323 | + yres -= 1; |
| 22324 | + winctrl1 |= (xres << 11); |
| 22325 | + winctrl1 |= (yres << 0); |
| 22326 | + |
| 22327 | + printk("new winctrl1 %08X\n", winctrl1); |
| 22328 | + |
| 22329 | + /*winenable = lcd->winenable & (1 << plane); */ |
| 22330 | + /*lcd->winenable &= ~(1 << plane); */ |
| 22331 | + lcd->window[plane].winctrl1 = winctrl1; |
| 22332 | + /*lcd->winenable |= winenable; */ |
| 22333 | +#endif |
| 22334 | + return 0; |
| 22335 | +} |
| 22336 | + |
| 22337 | +static int au1200_setlocation (int plane, int xpos, int ypos) |
| 22338 | +{ |
| 22339 | + uint32 winctrl0, winctrl1, winenable, fb_offset = 0; |
| 22340 | + int xsz, ysz; |
| 22341 | + |
| 22342 | + /* FIX!!! NOT CHECKING FOR COMPLETE OFFSCREEN YET */ |
| 22343 | + |
| 22344 | + winctrl0 = lcd->window[plane].winctrl0; |
| 22345 | + winctrl1 = lcd->window[plane].winctrl1; |
| 22346 | + winctrl0 &= (LCD_WINCTRL0_A | LCD_WINCTRL0_AEN); |
| 22347 | + winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY); |
| 22348 | + |
| 22349 | + /* Check for off-screen adjustments */ |
| 22350 | + xsz = win->w[plane].xres; |
| 22351 | + ysz = win->w[plane].yres; |
| 22352 | + if ((xpos + win->w[plane].xres) > panel->Xres) |
| 22353 | + { |
| 22354 | + /* Off-screen to the right */ |
| 22355 | + xsz = panel->Xres - xpos; /* off by 1 ??? */ |
| 22356 | + /*printk("off screen right\n");*/ |
| 22357 | + } |
| 22358 | + |
| 22359 | + if ((ypos + win->w[plane].yres) > panel->Yres) |
| 22360 | + { |
| 22361 | + /* Off-screen to the bottom */ |
| 22362 | + ysz = panel->Yres - ypos; /* off by 1 ??? */ |
| 22363 | + /*printk("off screen bottom\n");*/ |
| 22364 | + } |
| 22365 | + |
| 22366 | + if (xpos < 0) |
| 22367 | + { |
| 22368 | + /* Off-screen to the left */ |
| 22369 | + xsz = win->w[plane].xres + xpos; |
| 22370 | + fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8); |
| 22371 | + xpos = 0; |
| 22372 | + /*printk("off screen left\n");*/ |
| 22373 | + } |
| 22374 | + |
| 22375 | + if (ypos < 0) |
| 22376 | + { |
| 22377 | + /* Off-screen to the top */ |
| 22378 | + ysz = win->w[plane].yres + ypos; |
| 22379 | + fb_offset += ((0 - ypos) * fb_pars[plane].line_length); |
| 22380 | + ypos = 0; |
| 22381 | + /*printk("off screen top\n");*/ |
| 22382 | + } |
| 22383 | + |
| 22384 | + /* record settings */ |
| 22385 | + win->w[plane].xpos = xpos; |
| 22386 | + win->w[plane].ypos = ypos; |
| 22387 | + |
| 22388 | + xsz -= 1; |
| 22389 | + ysz -= 1; |
| 22390 | + winctrl0 |= (xpos << 21); |
| 22391 | + winctrl0 |= (ypos << 10); |
| 22392 | + winctrl1 |= (xsz << 11); |
| 22393 | + winctrl1 |= (ysz << 0); |
| 22394 | + |
| 22395 | + /* Disable the window while making changes, then restore WINEN */ |
| 22396 | + winenable = lcd->winenable & (1 << plane); |
| 22397 | + lcd->winenable &= ~(1 << plane); |
| 22398 | + lcd->window[plane].winctrl0 = winctrl0; |
| 22399 | + lcd->window[plane].winctrl1 = winctrl1; |
| 22400 | + lcd->window[plane].winbuf0 = |
| 22401 | + lcd->window[plane].winbuf1 = fb_infos[plane].fb_phys + fb_offset; |
| 22402 | + lcd->window[plane].winbufctrl = 0; /* select winbuf0 */ |
| 22403 | + lcd->winenable |= winenable; |
| 22404 | + |
| 22405 | + return 0; |
| 22406 | +} |
| 22407 | + |
| 22408 | +static void au1200_setmode(int plane) |
| 22409 | +{ |
| 22410 | + /* Window/plane setup */ |
| 22411 | + lcd->window[plane].winctrl1 = ( 0 |
| 22412 | + | LCD_WINCTRL1_PRI_N(plane) |
| 22413 | + | win->w[plane].mode_winctrl1 /* FRM,CCO,PO,PIPE */ |
| 22414 | + ) ; |
| 22415 | + |
| 22416 | + au1200_setlocation(plane, win->w[plane].xpos, win->w[plane].ypos); |
| 22417 | + |
| 22418 | + lcd->window[plane].winctrl2 = ( 0 |
| 22419 | + | LCD_WINCTRL2_CKMODE_00 |
| 22420 | + | LCD_WINCTRL2_DBM |
| 22421 | +/* | LCD_WINCTRL2_RAM */ |
| 22422 | + | LCD_WINCTRL2_BX_N(fb_pars[plane].line_length) |
| 22423 | + | LCD_WINCTRL2_SCX_1 |
| 22424 | + | LCD_WINCTRL2_SCY_1 |
| 22425 | + ) ; |
| 22426 | + lcd->winenable |= win->w[plane].mode_winenable; |
| 22427 | + au_sync(); |
| 22428 | + |
| 22429 | +} |
| 22430 | + |
| 22431 | +static unsigned long |
| 22432 | +au1200fb_alloc_fbmem (unsigned long size) |
| 22433 | +{ |
| 22434 | + /* __get_free_pages() fulfills a max request of 2MB */ |
| 22435 | + /* do multiple requests to obtain large contigous mem */ |
| 22436 | +#define MAX_GFP 0x00200000 |
| 22437 | + |
| 22438 | + unsigned long mem, amem, alloced = 0, allocsize; |
| 22439 | + |
| 22440 | + size += 0x1000; |
| 22441 | + allocsize = (size < MAX_GFP) ? size : MAX_GFP; |
| 22442 | + |
| 22443 | + /* Get first chunk */ |
| 22444 | + mem = (unsigned long ) |
| 22445 | + __get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(allocsize)); |
| 22446 | + if (mem != 0) alloced = allocsize; |
| 22447 | + |
| 22448 | + /* Get remaining, contiguous chunks */ |
| 22449 | + while (alloced < size) |
| 22450 | + { |
| 22451 | + amem = (unsigned long ) |
| 22452 | + __get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(allocsize)); |
| 22453 | + if (amem != 0) |
| 22454 | + alloced += allocsize; |
| 22455 | + |
| 22456 | + /* check for contiguous mem alloced */ |
| 22457 | + if ((amem == 0) || (amem + allocsize) != mem) |
| 22458 | + break; |
| 22459 | + else |
| 22460 | + mem = amem; |
| 22461 | + } |
| 22462 | + return mem; |
| 22463 | +} |
| 22464 | + |
| 22465 | +int __init au1200fb_init(void) |
| 22466 | +{ |
| 22467 | + int num_panels = sizeof(panels)/sizeof(struct panel_settings); |
| 22468 | + struct au1200fb_info *fb_info; |
| 22469 | + struct display *disp; |
| 22470 | + struct au1200fb_par *par; |
| 22471 | + unsigned long page; |
| 22472 | + int plane, bpp; |
| 22473 | + |
| 22474 | + /* |
| 22475 | + * Get the panel information/display mode |
| 22476 | + */ |
| 22477 | + if (panel_index < 0) |
| 22478 | + panel_index = board_au1200fb_panel(); |
| 22479 | + if ((panel_index < 0) || (panel_index >= num_panels)) { |
| 22480 | + printk("ERROR: INVALID PANEL %d\n", panel_index); |
| 22481 | + return -EINVAL; |
| 22482 | + } |
| 22483 | + panel = &panels[panel_index]; |
| 22484 | + win = &windows[window_index]; |
| 22485 | + |
| 22486 | + printk("au1200fb: Panel %d %s\n", panel_index, panel->name); |
| 22487 | + printk("au1200fb: Win %d %s\n", window_index, win->name); |
| 22488 | + |
| 22489 | + /* Global setup/init */ |
| 22490 | + au1200_setpanel(panel); |
| 22491 | + lcd->intenable = 0; |
| 22492 | + lcd->intstatus = ~0; |
| 22493 | + lcd->backcolor = win->mode_backcolor; |
| 22494 | + lcd->winenable = 0; |
| 22495 | + |
| 22496 | + /* Setup Color Key - FIX!!! */ |
| 22497 | + lcd->colorkey = win->mode_colorkey; |
| 22498 | + lcd->colorkeymsk = win->mode_colorkeymsk; |
| 22499 | + |
| 22500 | + /* Setup HWCursor - FIX!!! Need to support this eventually */ |
| 22501 | + lcd->hwc.cursorctrl = 0; |
| 22502 | + lcd->hwc.cursorpos = 0; |
| 22503 | + lcd->hwc.cursorcolor0 = 0; |
| 22504 | + lcd->hwc.cursorcolor1 = 0; |
| 22505 | + lcd->hwc.cursorcolor2 = 0; |
| 22506 | + lcd->hwc.cursorcolor3 = 0; |
| 22507 | + |
| 22508 | + /* Register each plane as a frame buffer device */ |
| 22509 | + for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) |
| 22510 | + { |
| 22511 | + fb_info = &fb_infos[plane]; |
| 22512 | + disp = &disps[plane]; |
| 22513 | + par = &fb_pars[plane]; |
| 22514 | + |
| 22515 | + bpp = winbpp(win->w[plane].mode_winctrl1); |
| 22516 | + if (win->w[plane].xres == 0) |
| 22517 | + win->w[plane].xres = panel->Xres; |
| 22518 | + if (win->w[plane].yres == 0) |
| 22519 | + win->w[plane].yres = panel->Yres; |
| 22520 | + |
| 22521 | + par->var.xres = |
| 22522 | + par->var.xres_virtual = win->w[plane].xres; |
| 22523 | + par->var.yres = |
| 22524 | + par->var.yres_virtual = win->w[plane].yres; |
| 22525 | + par->var.bits_per_pixel = bpp; |
| 22526 | + par->line_length = win->w[plane].xres * bpp / 8; /* in bytes */ |
| 22527 | + /* |
| 22528 | + * Allocate LCD framebuffer from system memory |
| 22529 | + * Set page reserved so that mmap will work. This is necessary |
| 22530 | + * since we'll be remapping normal memory. |
| 22531 | + */ |
| 22532 | + fb_info->fb_size = (win->w[plane].xres * win->w[plane].yres * bpp) / 8; |
| 22533 | + fb_info->fb_virt_start = au1200fb_alloc_fbmem(fb_info->fb_size); |
| 22534 | + if (!fb_info->fb_virt_start) { |
| 22535 | + printk("Unable to allocate fb memory\n"); |
| 22536 | + return -ENOMEM; |
| 22537 | + } |
| 22538 | + fb_info->fb_phys = virt_to_bus((void *)fb_info->fb_virt_start); |
| 22539 | + for (page = fb_info->fb_virt_start; |
| 22540 | + page < PAGE_ALIGN(fb_info->fb_virt_start + fb_info->fb_size); |
| 22541 | + page += PAGE_SIZE) { |
| 22542 | + SetPageReserved(virt_to_page(page)); |
| 22543 | + } |
| 22544 | + /* Convert to kseg1 */ |
| 22545 | + fb_info->fb_virt_start = |
| 22546 | + (void *)((u32)fb_info->fb_virt_start | 0xA0000000); |
| 22547 | + /* FIX!!! may wish to avoid this to save startup time??? */ |
| 22548 | + memset((void *)fb_info->fb_virt_start, 0, fb_info->fb_size); |
| 22549 | + |
| 22550 | + fb_info->gen.parsize = sizeof(struct au1200fb_par); |
| 22551 | + fb_info->gen.fbhw = &au1200_switch; |
| 22552 | + strcpy(fb_info->gen.info.modename, "Au1200 LCD"); |
| 22553 | + fb_info->gen.info.changevar = NULL; |
| 22554 | + fb_info->gen.info.node = -1; |
| 22555 | + |
| 22556 | + fb_info->gen.info.fbops = &au1200fb_ops; |
| 22557 | + fb_info->gen.info.disp = disp; |
| 22558 | + fb_info->gen.info.switch_con = &fbgen_switch; |
| 22559 | + fb_info->gen.info.updatevar = &fbgen_update_var; |
| 22560 | + fb_info->gen.info.blank = &fbgen_blank; |
| 22561 | + fb_info->gen.info.flags = FBINFO_FLAG_DEFAULT; |
| 22562 | + |
| 22563 | + fb_info->nohwcursor = 1; |
| 22564 | + fb_info->noblanking = 1; |
| 22565 | + |
| 22566 | + /* This should give a reasonable default video mode */ |
| 22567 | + fbgen_get_var(&disp->var, -1, &fb_info->gen.info); |
| 22568 | + fbgen_do_set_var(&disp->var, 1, &fb_info->gen); |
| 22569 | + fbgen_set_disp(-1, &fb_info->gen); |
| 22570 | + fbgen_install_cmap(0, &fb_info->gen); |
| 22571 | + |
| 22572 | + /* Turn on plane */ |
| 22573 | + au1200_setmode(plane); |
| 22574 | + |
| 22575 | + if (register_framebuffer(&fb_info->gen.info) < 0) |
| 22576 | + return -EINVAL; |
| 22577 | + |
| 22578 | + printk(KERN_INFO "fb%d: %s plane %d @ %08X (%d x %d x %d)\n", |
| 22579 | + GET_FB_IDX(fb_info->gen.info.node), |
| 22580 | + fb_info->gen.info.modename, plane, fb_info->fb_phys, |
| 22581 | + win->w[plane].xres, win->w[plane].yres, bpp); |
| 22582 | + } |
| 22583 | + /* uncomment this if your driver cannot be unloaded */ |
| 22584 | + /* MOD_INC_USE_COUNT; */ |
| 22585 | + return 0; |
| 22586 | +} |
| 22587 | + |
| 22588 | +void au1200fb_setup(char *options, int *ints) |
| 22589 | +{ |
| 22590 | + char* this_opt; |
| 22591 | + int i; |
| 22592 | + int num_panels = sizeof(panels)/sizeof(struct panel_settings); |
| 22593 | + |
| 22594 | + if (!options || !*options) |
| 22595 | + return; |
| 22596 | + |
| 22597 | + for(this_opt=strtok(options, ","); this_opt; |
| 22598 | + this_opt=strtok(NULL, ",")) { |
| 22599 | + if (!strncmp(this_opt, "panel:", 6)) { |
| 22600 | + int i; |
| 22601 | + long int li; |
| 22602 | + char *endptr; |
| 22603 | + this_opt += 6; |
| 22604 | + |
| 22605 | + /* Panel name can be name, "bs" for board-switch, or number/index */ |
| 22606 | + li = simple_strtol(this_opt, &endptr, 0); |
| 22607 | + if (*endptr == '\0') { |
| 22608 | + panel_index = (int)li; |
| 22609 | + } |
| 22610 | + else if (strcmp(this_opt, "bs") == 0) { |
| 22611 | + panel_index = board_au1200fb_panel(); |
| 22612 | + } |
| 22613 | + else |
| 22614 | + for (i=0; i<num_panels; i++) { |
| 22615 | + if (!strcmp(this_opt, panels[i].name)) { |
| 22616 | + panel_index = i; |
| 22617 | + break; |
| 22618 | + } |
| 22619 | + } |
| 22620 | + } |
| 22621 | + else if (!strncmp(this_opt, "nohwcursor", 10)) { |
| 22622 | + printk("nohwcursor\n"); |
| 22623 | + fb_infos[0].nohwcursor = 1; |
| 22624 | + } |
| 22625 | + } |
| 22626 | + |
| 22627 | + printk("au1200fb: Panel %d %s\n", panel_index, |
| 22628 | + panels[panel_index].name); |
| 22629 | +} |
| 22630 | + |
| 22631 | + |
| 22632 | + |
| 22633 | +#ifdef MODULE |
| 22634 | +MODULE_LICENSE("GPL"); |
| 22635 | +MODULE_DESCRIPTION("Au1200 LCD framebuffer driver"); |
| 22636 | + |
| 22637 | +void au1200fb_cleanup(struct fb_info *info) |
| 22638 | +{ |
| 22639 | + unregister_framebuffer(info); |
| 22640 | +} |
| 22641 | + |
| 22642 | +module_init(au1200fb_init); |
| 22643 | +module_exit(au1200fb_cleanup); |
| 22644 | +#endif /* MODULE */ |
| 22645 | + |
| 22646 | + |
| 22647 | --- /dev/null |
| 22648 | +++ b/drivers/video/au1200fb.h |
| 22649 | @@ -0,0 +1,288 @@ |
| 22650 | +/* |
| 22651 | + * BRIEF MODULE DESCRIPTION |
| 22652 | + * Hardware definitions for the Au1200 LCD controller |
| 22653 | + * |
| 22654 | + * Copyright 2004 AMD |
| 22655 | + * Author: AMD |
| 22656 | + * |
| 22657 | + * This program is free software; you can redistribute it and/or modify it |
| 22658 | + * under the terms of the GNU General Public License as published by the |
| 22659 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 22660 | + * option) any later version. |
| 22661 | + * |
| 22662 | + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 22663 | + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 22664 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 22665 | + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22666 | + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22667 | + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 22668 | + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 22669 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 22670 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 22671 | + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 22672 | + * |
| 22673 | + * You should have received a copy of the GNU General Public License along |
| 22674 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 22675 | + * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 22676 | + */ |
| 22677 | + |
| 22678 | +#ifndef _AU1200LCD_H |
| 22679 | +#define _AU1200LCD_H |
| 22680 | + |
| 22681 | +/********************************************************************/ |
| 22682 | +#define AU1200_LCD_ADDR 0xB5000000 |
| 22683 | + |
| 22684 | +#define uint8 unsigned char |
| 22685 | +#define uint32 unsigned int |
| 22686 | + |
| 22687 | +typedef volatile struct |
| 22688 | +{ |
| 22689 | + uint32 reserved0; |
| 22690 | + uint32 screen; |
| 22691 | + uint32 backcolor; |
| 22692 | + uint32 horztiming; |
| 22693 | + uint32 verttiming; |
| 22694 | + uint32 clkcontrol; |
| 22695 | + uint32 pwmdiv; |
| 22696 | + uint32 pwmhi; |
| 22697 | + uint32 reserved1; |
| 22698 | + uint32 winenable; |
| 22699 | + uint32 colorkey; |
| 22700 | + uint32 colorkeymsk; |
| 22701 | + struct |
| 22702 | + { |
| 22703 | + uint32 cursorctrl; |
| 22704 | + uint32 cursorpos; |
| 22705 | + uint32 cursorcolor0; |
| 22706 | + uint32 cursorcolor1; |
| 22707 | + uint32 cursorcolor2; |
| 22708 | + uint32 cursorcolor3; |
| 22709 | + } hwc; |
| 22710 | + uint32 intstatus; |
| 22711 | + uint32 intenable; |
| 22712 | + uint32 outmask; |
| 22713 | + uint32 fifoctrl; |
| 22714 | + uint32 reserved2[(0x0100-0x0058)/4]; |
| 22715 | + struct |
| 22716 | + { |
| 22717 | + uint32 winctrl0; |
| 22718 | + uint32 winctrl1; |
| 22719 | + uint32 winctrl2; |
| 22720 | + uint32 winbuf0; |
| 22721 | + uint32 winbuf1; |
| 22722 | + uint32 winbufctrl; |
| 22723 | + uint32 winreserved0; |
| 22724 | + uint32 winreserved1; |
| 22725 | + } window[4]; |
| 22726 | + |
| 22727 | + uint32 reserved3[(0x0400-0x0180)/4]; |
| 22728 | + |
| 22729 | + uint32 palette[(0x0800-0x0400)/4]; |
| 22730 | + |
| 22731 | + uint8 cursorpattern[256]; |
| 22732 | + |
| 22733 | +} AU1200_LCD; |
| 22734 | + |
| 22735 | +/* lcd_screen */ |
| 22736 | +#define LCD_SCREEN_SEN (1<<31) |
| 22737 | +#define LCD_SCREEN_SX (0x07FF<<19) |
| 22738 | +#define LCD_SCREEN_SY (0x07FF<< 8) |
| 22739 | +#define LCD_SCREEN_SWP (1<<7) |
| 22740 | +#define LCD_SCREEN_SWD (1<<6) |
| 22741 | +#define LCD_SCREEN_ST (7<<0) |
| 22742 | +#define LCD_SCREEN_ST_TFT (0<<0) |
| 22743 | +#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19) |
| 22744 | +#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8) |
| 22745 | +#define LCD_SCREEN_ST_CSTN (1<<0) |
| 22746 | +#define LCD_SCREEN_ST_CDSTN (2<<0) |
| 22747 | +#define LCD_SCREEN_ST_M8STN (3<<0) |
| 22748 | +#define LCD_SCREEN_ST_M4STN (4<<0) |
| 22749 | + |
| 22750 | +/* lcd_backcolor */ |
| 22751 | +#define LCD_BACKCOLOR_SBGR (0xFF<<16) |
| 22752 | +#define LCD_BACKCOLOR_SBGG (0xFF<<8) |
| 22753 | +#define LCD_BACKCOLOR_SBGB (0xFF<<0) |
| 22754 | +#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16) |
| 22755 | +#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8) |
| 22756 | +#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0) |
| 22757 | + |
| 22758 | +/* lcd_winenable */ |
| 22759 | +#define LCD_WINENABLE_WEN3 (1<<3) |
| 22760 | +#define LCD_WINENABLE_WEN2 (1<<2) |
| 22761 | +#define LCD_WINENABLE_WEN1 (1<<1) |
| 22762 | +#define LCD_WINENABLE_WEN0 (1<<0) |
| 22763 | + |
| 22764 | +/* lcd_colorkey */ |
| 22765 | +#define LCD_COLORKEY_CKR (0xFF<<16) |
| 22766 | +#define LCD_COLORKEY_CKG (0xFF<<8) |
| 22767 | +#define LCD_COLORKEY_CKB (0xFF<<0) |
| 22768 | +#define LCD_COLORKEY_CKR_N(N) ((N)<<16) |
| 22769 | +#define LCD_COLORKEY_CKG_N(N) ((N)<<8) |
| 22770 | +#define LCD_COLORKEY_CKB_N(N) ((N)<<0) |
| 22771 | + |
| 22772 | +/* lcd_colorkeymsk */ |
| 22773 | +#define LCD_COLORKEYMSK_CKMR (0xFF<<16) |
| 22774 | +#define LCD_COLORKEYMSK_CKMG (0xFF<<8) |
| 22775 | +#define LCD_COLORKEYMSK_CKMB (0xFF<<0) |
| 22776 | +#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16) |
| 22777 | +#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8) |
| 22778 | +#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0) |
| 22779 | + |
| 22780 | +/* lcd windows control 0 */ |
| 22781 | +#define LCD_WINCTRL0_OX (0x07FF<<21) |
| 22782 | +#define LCD_WINCTRL0_OY (0x07FF<<10) |
| 22783 | +#define LCD_WINCTRL0_A (0x00FF<<2) |
| 22784 | +#define LCD_WINCTRL0_AEN (1<<1) |
| 22785 | +#define LCD_WINCTRL0_OX_N(N) ((N)<<21) |
| 22786 | +#define LCD_WINCTRL0_OY_N(N) ((N)<<10) |
| 22787 | +#define LCD_WINCTRL0_A_N(N) ((N)<<2) |
| 22788 | + |
| 22789 | +/* lcd windows control 1 */ |
| 22790 | +#define LCD_WINCTRL1_PRI (3<<30) |
| 22791 | +#define LCD_WINCTRL1_PIPE (1<<29) |
| 22792 | +#define LCD_WINCTRL1_FRM (0xF<<25) |
| 22793 | +#define LCD_WINCTRL1_CCO (1<<24) |
| 22794 | +#define LCD_WINCTRL1_PO (3<<22) |
| 22795 | +#define LCD_WINCTRL1_SZX (0x07FF<<11) |
| 22796 | +#define LCD_WINCTRL1_SZY (0x07FF<<0) |
| 22797 | +#define LCD_WINCTRL1_FRM_1BPP (0<<25) |
| 22798 | +#define LCD_WINCTRL1_FRM_2BPP (1<<25) |
| 22799 | +#define LCD_WINCTRL1_FRM_4BPP (2<<25) |
| 22800 | +#define LCD_WINCTRL1_FRM_8BPP (3<<25) |
| 22801 | +#define LCD_WINCTRL1_FRM_12BPP (4<<25) |
| 22802 | +#define LCD_WINCTRL1_FRM_16BPP655 (5<<25) |
| 22803 | +#define LCD_WINCTRL1_FRM_16BPP565 (6<<25) |
| 22804 | +#define LCD_WINCTRL1_FRM_16BPP556 (7<<25) |
| 22805 | +#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25) |
| 22806 | +#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25) |
| 22807 | +#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25) |
| 22808 | +#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25) |
| 22809 | +#define LCD_WINCTRL1_FRM_24BPP (12<<25) |
| 22810 | +#define LCD_WINCTRL1_FRM_32BPP (13<<25) |
| 22811 | +#define LCD_WINCTRL1_PRI_N(N) ((N)<<30) |
| 22812 | +#define LCD_WINCTRL1_PO_00 (0<<22) |
| 22813 | +#define LCD_WINCTRL1_PO_01 (1<<22) |
| 22814 | +#define LCD_WINCTRL1_PO_10 (2<<22) |
| 22815 | +#define LCD_WINCTRL1_PO_11 (3<<22) |
| 22816 | +#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11) |
| 22817 | +#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0) |
| 22818 | + |
| 22819 | +/* lcd windows control 2 */ |
| 22820 | +#define LCD_WINCTRL2_CKMODE (3<<24) |
| 22821 | +#define LCD_WINCTRL2_DBM (1<<23) |
| 22822 | +#define LCD_WINCTRL2_RAM (3<<21) |
| 22823 | +#define LCD_WINCTRL2_BX (0x1FFF<<8) |
| 22824 | +#define LCD_WINCTRL2_SCX (0xF<<4) |
| 22825 | +#define LCD_WINCTRL2_SCY (0xF<<0) |
| 22826 | +#define LCD_WINCTRL2_CKMODE_00 (0<<24) |
| 22827 | +#define LCD_WINCTRL2_CKMODE_01 (1<<24) |
| 22828 | +#define LCD_WINCTRL2_CKMODE_10 (2<<24) |
| 22829 | +#define LCD_WINCTRL2_CKMODE_11 (3<<24) |
| 22830 | +#define LCD_WINCTRL2_RAM_NONE (0<<21) |
| 22831 | +#define LCD_WINCTRL2_RAM_PALETTE (1<<21) |
| 22832 | +#define LCD_WINCTRL2_RAM_GAMMA (2<<21) |
| 22833 | +#define LCD_WINCTRL2_RAM_BUFFER (3<<21) |
| 22834 | +#define LCD_WINCTRL2_BX_N(N) ((N)<<8) |
| 22835 | +#define LCD_WINCTRL2_SCX_1 (0<<4) |
| 22836 | +#define LCD_WINCTRL2_SCX_2 (1<<4) |
| 22837 | +#define LCD_WINCTRL2_SCX_4 (2<<4) |
| 22838 | +#define LCD_WINCTRL2_SCY_1 (0<<0) |
| 22839 | +#define LCD_WINCTRL2_SCY_2 (1<<0) |
| 22840 | +#define LCD_WINCTRL2_SCY_4 (2<<0) |
| 22841 | + |
| 22842 | +/* lcd windows buffer control */ |
| 22843 | +#define LCD_WINBUFCTRL_DB (1<<1) |
| 22844 | +#define LCD_WINBUFCTRL_DBN (1<<0) |
| 22845 | + |
| 22846 | +/* lcd_intstatus, lcd_intenable */ |
| 22847 | +#define LCD_INT_IFO (0xF<<14) |
| 22848 | +#define LCD_INT_IFU (0xF<<10) |
| 22849 | +#define LCD_INT_OFO (1<<9) |
| 22850 | +#define LCD_INT_OFU (1<<8) |
| 22851 | +#define LCD_INT_WAIT (1<<3) |
| 22852 | +#define LCD_INT_SD (1<<2) |
| 22853 | +#define LCD_INT_SA (1<<1) |
| 22854 | +#define LCD_INT_SS (1<<0) |
| 22855 | + |
| 22856 | +/* lcd_horztiming */ |
| 22857 | +#define LCD_HORZTIMING_HND2 (0x1FF<<18) |
| 22858 | +#define LCD_HORZTIMING_HND1 (0x1FF<<9) |
| 22859 | +#define LCD_HORZTIMING_HPW (0x1FF<<0) |
| 22860 | +#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18) |
| 22861 | +#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9) |
| 22862 | +#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0) |
| 22863 | + |
| 22864 | +/* lcd_verttiming */ |
| 22865 | +#define LCD_VERTTIMING_VND2 (0x1FF<<18) |
| 22866 | +#define LCD_VERTTIMING_VND1 (0x1FF<<9) |
| 22867 | +#define LCD_VERTTIMING_VPW (0x1FF<<0) |
| 22868 | +#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18) |
| 22869 | +#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9) |
| 22870 | +#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0) |
| 22871 | + |
| 22872 | +/* lcd_clkcontrol */ |
| 22873 | +#define LCD_CLKCONTROL_EXT (1<<22) |
| 22874 | +#define LCD_CLKCONTROL_DELAY (3<<20) |
| 22875 | +#define LCD_CLKCONTROL_CDD (1<<19) |
| 22876 | +#define LCD_CLKCONTROL_IB (1<<18) |
| 22877 | +#define LCD_CLKCONTROL_IC (1<<17) |
| 22878 | +#define LCD_CLKCONTROL_IH (1<<16) |
| 22879 | +#define LCD_CLKCONTROL_IV (1<<15) |
| 22880 | +#define LCD_CLKCONTROL_BF (0x1F<<10) |
| 22881 | +#define LCD_CLKCONTROL_PCD (0x3FF<<0) |
| 22882 | +#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10) |
| 22883 | +#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0) |
| 22884 | + |
| 22885 | +/* lcd_pwmdiv */ |
| 22886 | +#define LCD_PWMDIV_EN (1<<31) |
| 22887 | +#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0) |
| 22888 | +#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0) |
| 22889 | + |
| 22890 | +/* lcd_pwmhi */ |
| 22891 | +#define LCD_PWMHI_PWMHI1 (0xFFFF<<16) |
| 22892 | +#define LCD_PWMHI_PWMHI0 (0xFFFF<<0) |
| 22893 | +#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16) |
| 22894 | +#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0) |
| 22895 | + |
| 22896 | +/* lcd_hwccon */ |
| 22897 | +#define LCD_HWCCON_EN (1<<0) |
| 22898 | + |
| 22899 | +/* lcd_cursorpos */ |
| 22900 | +#define LCD_CURSORPOS_HWCXOFF (0x1F<<27) |
| 22901 | +#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16) |
| 22902 | +#define LCD_CURSORPOS_HWCYOFF (0x1F<<11) |
| 22903 | +#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0) |
| 22904 | +#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27) |
| 22905 | +#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16) |
| 22906 | +#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11) |
| 22907 | +#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0) |
| 22908 | + |
| 22909 | +/* lcd_cursorcolor */ |
| 22910 | +#define LCD_CURSORCOLOR_HWCA (0xFF<<24) |
| 22911 | +#define LCD_CURSORCOLOR_HWCR (0xFF<<16) |
| 22912 | +#define LCD_CURSORCOLOR_HWCG (0xFF<<8) |
| 22913 | +#define LCD_CURSORCOLOR_HWCB (0xFF<<0) |
| 22914 | +#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24) |
| 22915 | +#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16) |
| 22916 | +#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8) |
| 22917 | +#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0) |
| 22918 | + |
| 22919 | +/* lcd_fifoctrl */ |
| 22920 | +#define LCD_FIFOCTRL_F3IF (1<<29) |
| 22921 | +#define LCD_FIFOCTRL_F3REQ (0x1F<<24) |
| 22922 | +#define LCD_FIFOCTRL_F2IF (1<<29) |
| 22923 | +#define LCD_FIFOCTRL_F2REQ (0x1F<<16) |
| 22924 | +#define LCD_FIFOCTRL_F1IF (1<<29) |
| 22925 | +#define LCD_FIFOCTRL_F1REQ (0x1F<<8) |
| 22926 | +#define LCD_FIFOCTRL_F0IF (1<<29) |
| 22927 | +#define LCD_FIFOCTRL_F0REQ (0x1F<<0) |
| 22928 | +#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24) |
| 22929 | +#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16) |
| 22930 | +#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8) |
| 22931 | +#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0) |
| 22932 | + |
| 22933 | +/* lcd_outmask */ |
| 22934 | +#define LCD_OUTMASK_MASK (0x00FFFFFF) |
| 22935 | + |
| 22936 | +/********************************************************************/ |
| 22937 | +#endif /* _AU1200LCD_H */ |
| 22938 | --- a/drivers/video/Config.in |
| 22939 | +++ b/drivers/video/Config.in |
| 22940 | @@ -87,8 +87,8 @@ if [ "$CONFIG_FB" = "y" ]; then |
| 22941 | if [ "$CONFIG_HP300" = "y" ]; then |
| 22942 | define_bool CONFIG_FB_HP300 y |
| 22943 | fi |
| 22944 | - if [ "$ARCH" = "alpha" ]; then |
| 22945 | - tristate ' TGA framebuffer support' CONFIG_FB_TGA |
| 22946 | + if [ "$ARCH" = "alpha" -o "$CONFIG_TC" = "y" ]; then |
| 22947 | + tristate ' TGA/SFB+ framebuffer support' CONFIG_FB_TGA |
| 22948 | fi |
| 22949 | if [ "$CONFIG_X86" = "y" ]; then |
| 22950 | bool ' VESA VGA graphics console' CONFIG_FB_VESA |
| 22951 | @@ -121,6 +121,17 @@ if [ "$CONFIG_FB" = "y" ]; then |
| 22952 | hex ' Framebuffer Base Address' CONFIG_E1355_FB_BASE a8200000 |
| 22953 | fi |
| 22954 | fi |
| 22955 | + if [ "$CONFIG_SOC_AU1100" = "y" ]; then |
| 22956 | + bool ' Au1100 LCD Driver' CONFIG_FB_AU1100 |
| 22957 | + fi |
| 22958 | + |
| 22959 | + if [ "$CONFIG_SOC_AU1200" = "y" ]; then |
| 22960 | + bool ' Au1200 LCD Driver' CONFIG_FB_AU1200 |
| 22961 | + if [ "$CONFIG_FB_AU1200" = "y" ]; then |
| 22962 | + int ' Number of planes (1 to 4)' CONFIG_FB_AU1200_DEVS 1 |
| 22963 | + fi |
| 22964 | + fi |
| 22965 | + |
| 22966 | if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then |
| 22967 | if [ "$CONFIG_PCI" != "n" ]; then |
| 22968 | tristate ' Matrox acceleration (EXPERIMENTAL)' CONFIG_FB_MATROX |
| 22969 | @@ -178,9 +189,6 @@ if [ "$CONFIG_FB" = "y" ]; then |
| 22970 | bool ' Use CRT on Pb1100 ' CONFIG_PB1500_CRT |
| 22971 | bool ' Use TFT Panel on Pb1100 ' CONFIG_PB1500_TFT |
| 22972 | fi |
| 22973 | - if [ "$CONFIG_SOC_AU1100" = "y" ]; then |
| 22974 | - bool ' Au1100 LCD Driver' CONFIG_FB_AU1100 |
| 22975 | - fi |
| 22976 | fi |
| 22977 | fi |
| 22978 | fi |
| 22979 | --- a/drivers/video/fbmem.c |
| 22980 | +++ b/drivers/video/fbmem.c |
| 22981 | @@ -139,6 +139,8 @@ extern int e1356fb_init(void); |
| 22982 | extern int e1356fb_setup(char*); |
| 22983 | extern int au1100fb_init(void); |
| 22984 | extern int au1100fb_setup(char*); |
| 22985 | +extern int au1200fb_init(void); |
| 22986 | +extern int au1200fb_setup(char*); |
| 22987 | extern int pvr2fb_init(void); |
| 22988 | extern int pvr2fb_setup(char*); |
| 22989 | extern int sstfb_init(void); |
| 22990 | @@ -331,6 +333,9 @@ static struct { |
| 22991 | #ifdef CONFIG_FB_AU1100 |
| 22992 | { "au1100fb", au1100fb_init, au1100fb_setup }, |
| 22993 | #endif |
| 22994 | +#ifdef CONFIG_FB_AU1200 |
| 22995 | + { "au1200fb", au1200fb_init, au1200fb_setup }, |
| 22996 | +#endif |
| 22997 | #ifdef CONFIG_FB_IT8181 |
| 22998 | { "it8181fb", it8181fb_init, it8181fb_setup }, |
| 22999 | #endif |
| 23000 | --- /dev/null |
| 23001 | +++ b/drivers/video/ims332.h |
| 23002 | @@ -0,0 +1,275 @@ |
| 23003 | +/* |
| 23004 | + * linux/drivers/video/ims332.h |
| 23005 | + * |
| 23006 | + * Copyright 2003 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> |
| 23007 | + * |
| 23008 | + * This file is subject to the terms and conditions of the GNU General |
| 23009 | + * Public License. See the file COPYING in the main directory of this |
| 23010 | + * archive for more details. |
| 23011 | + */ |
| 23012 | +#include <linux/types.h> |
| 23013 | + |
| 23014 | +/* |
| 23015 | + * IMS332 16-bit wide, 128-bit aligned registers. |
| 23016 | + */ |
| 23017 | +struct _ims332_reg { |
| 23018 | + volatile u16 r; |
| 23019 | + u16 pad[7]; |
| 23020 | +}; |
| 23021 | + |
| 23022 | +struct _ims332_regs { |
| 23023 | +#define IMS332_BOOT_PLL_MUTLIPLIER 0x00001f |
| 23024 | +#define IMS332_BOOT_CLOCK_SOURCE_SEL 0x000020 |
| 23025 | +#define IMS332_BOOT_ADDRESS_ALIGNMENT 0x000040 |
| 23026 | +#define IMS332_BOOT_WRITE_ZERO 0xffff80 |
| 23027 | + struct _ims332_reg boot; |
| 23028 | + struct _ims332_reg pad0[0x020 - 0x000]; |
| 23029 | + struct _ims332_reg half_sync; |
| 23030 | + struct _ims332_reg back_porch; |
| 23031 | + struct _ims332_reg display; |
| 23032 | + struct _ims332_reg short_display; |
| 23033 | + struct _ims332_reg broad_pulse; |
| 23034 | + struct _ims332_reg vsync; |
| 23035 | + struct _ims332_reg vpre_equalise; |
| 23036 | + struct _ims332_reg vpost_equalise; |
| 23037 | + struct _ims332_reg vblank; |
| 23038 | + struct _ims332_reg vdisplay; |
| 23039 | + struct _ims332_reg line_time; |
| 23040 | + struct _ims332_reg line_start; |
| 23041 | + struct _ims332_reg mem_init; |
| 23042 | + struct _ims332_reg transfer_delay; |
| 23043 | + struct _ims332_reg pad1[0x03f - 0x02e]; |
| 23044 | + struct _ims332_reg pixel_address_mask; |
| 23045 | + struct _ims332_reg pad2[0x05f - 0x040]; |
| 23046 | + |
| 23047 | +#define IMS332_CTRL_A_BOOT_ENABLE_VTG 0x000001 |
| 23048 | +#define IMS332_CTRL_A_SCREEN_FORMAT 0x000002 |
| 23049 | +#define IMS332_CTRL_A_INTERLACED_STANDARD 0x000004 |
| 23050 | +#define IMS332_CTRL_A_OPERATING_MODE 0x000008 |
| 23051 | +#define IMS332_CTRL_A_FRAME_FLYBACK_PATTERN 0x000010 |
| 23052 | +#define IMS332_CTRL_A_DIGITAL_SYNC_FORMAT 0x000020 |
| 23053 | +#define IMS332_CTRL_A_ANALOGUE_VIDEO_FORMAT 0x000040 |
| 23054 | +#define IMS332_CTRL_A_BLANK_LEVEL 0x000080 |
| 23055 | +#define IMS332_CTRL_A_BLANK_IO 0x000100 |
| 23056 | +#define IMS332_CTRL_A_BLANK_FUNCTION_SWITCH 0x000200 |
| 23057 | +#define IMS332_CTRL_A_FORCE_BLANKING 0x000400 |
| 23058 | +#define IMS332_CTRL_A_TURN_OFF_BLANKING 0x000800 |
| 23059 | +#define IMS332_CTRL_A_VRAM_ADDRESS_INCREMENT 0x003000 |
| 23060 | +#define IMS332_CTRL_A_TURN_OFF_DMA 0x004000 |
| 23061 | +#define IMS332_CTRL_A_SYNC_DELAY 0x038000 |
| 23062 | +#define IMS332_CTRL_A_PIXEL_PORT_INTERLEAVING 0x040000 |
| 23063 | +#define IMS332_CTRL_A_DELAYED_SAMPLING 0x080000 |
| 23064 | +#define IMS332_CTRL_A_BITS_PER_PIXEL 0x700000 |
| 23065 | +#define IMS332_CTRL_A_CURSOR_DISABLE 0x800000 |
| 23066 | + struct _ims332_reg config_control_a; |
| 23067 | + struct _ims332_reg pad3[0x06f - 0x060]; |
| 23068 | + |
| 23069 | +#define IMS332_CTRL_B_WRITE_ZERO 0xffffff |
| 23070 | + struct _ims332_reg config_control_b; |
| 23071 | + struct _ims332_reg pad4[0x07f - 0x070]; |
| 23072 | + struct _ims332_reg screen_top; |
| 23073 | + struct _ims332_reg pad5[0x0a0 - 0x080]; |
| 23074 | + /* cursor color palette, 3 entries, reg no. 0xa1 - 0xa3 */ |
| 23075 | + struct _ims332_reg cursor_color_palette0; |
| 23076 | + struct _ims332_reg cursor_color_palette1; |
| 23077 | + struct _ims332_reg cursor_color_palette2; |
| 23078 | + struct _ims332_reg pad6[0x0bf - 0x0a3]; |
| 23079 | + struct _ims332_reg rgb_frame_checksum0; |
| 23080 | + struct _ims332_reg rgb_frame_checksum1; |
| 23081 | + struct _ims332_reg rgb_frame_checksum2; |
| 23082 | + struct _ims332_reg pad7[0x0c6 - 0x0c2]; |
| 23083 | + struct _ims332_reg cursor_start; |
| 23084 | + struct _ims332_reg pad8[0x0ff - 0x0c7]; |
| 23085 | + /* color palette, 256 entries of form 0x00BBGGRR, reg no. 0x100 - 0x1ff */ |
| 23086 | + struct _ims332_reg color_palette[0x1ff - 0x0ff]; |
| 23087 | + /* hardware cursor bitmap, reg no. 0x200 - 0x3ff */ |
| 23088 | + struct _ims332_reg cursor_ram[0x3ff - 0x1ff]; |
| 23089 | +}; |
| 23090 | + |
| 23091 | +/* |
| 23092 | + * In the functions below we use some weird looking helper variables to |
| 23093 | + * access most members of this struct, otherwise the compiler splits |
| 23094 | + * the read/write in two byte accesses. |
| 23095 | + */ |
| 23096 | +struct ims332_regs { |
| 23097 | + struct _ims332_regs rw; |
| 23098 | + char pad0[0x80000 - sizeof (struct _ims332_regs)]; |
| 23099 | + struct _ims332_regs r; |
| 23100 | + char pad1[0xa0000 - (sizeof (struct _ims332_regs) + 0x80000)]; |
| 23101 | + struct _ims332_regs w; |
| 23102 | +} __attribute__((packed)); |
| 23103 | + |
| 23104 | +static inline void ims332_control_reg_bits(struct ims332_regs *regs, u32 mask, |
| 23105 | + u32 val) |
| 23106 | +{ |
| 23107 | + volatile u16 *ctr = &(regs->r.config_control_a.r); |
| 23108 | + volatile u16 *ctw = &(regs->w.config_control_a.r); |
| 23109 | + u32 ctrl; |
| 23110 | + |
| 23111 | + mb(); |
| 23112 | + ctrl = *ctr; |
| 23113 | + rmb(); |
| 23114 | + ctrl |= ((regs->rw.boot.r << 8) & 0x00ff0000); |
| 23115 | + ctrl |= val & mask; |
| 23116 | + ctrl &= ~(~val & mask); |
| 23117 | + wmb(); |
| 23118 | + regs->rw.boot.r = (ctrl >> 8) & 0xff00; |
| 23119 | + wmb(); |
| 23120 | + *ctw = ctrl & 0xffff; |
| 23121 | +} |
| 23122 | + |
| 23123 | +/* FIXME: This is maxinefb specific. */ |
| 23124 | +static inline void ims332_bootstrap(struct ims332_regs *regs) |
| 23125 | +{ |
| 23126 | + volatile u16 *ctw = &(regs->w.config_control_a.r); |
| 23127 | + u32 ctrl = IMS332_CTRL_A_BOOT_ENABLE_VTG | IMS332_CTRL_A_TURN_OFF_DMA; |
| 23128 | + |
| 23129 | + /* bootstrap sequence */ |
| 23130 | + mb(); |
| 23131 | + regs->rw.boot.r = 0; |
| 23132 | + wmb(); |
| 23133 | + *ctw = 0; |
| 23134 | + |
| 23135 | + /* init control A register */ |
| 23136 | + wmb(); |
| 23137 | + regs->rw.boot.r = (ctrl >> 8) & 0xff00; |
| 23138 | + wmb(); |
| 23139 | + *ctw = ctrl & 0xffff; |
| 23140 | +} |
| 23141 | + |
| 23142 | +static inline void ims332_blank_screen(struct ims332_regs *regs, int blank) |
| 23143 | +{ |
| 23144 | + ims332_control_reg_bits(regs, IMS332_CTRL_A_FORCE_BLANKING, |
| 23145 | + blank ? IMS332_CTRL_A_FORCE_BLANKING : 0); |
| 23146 | +} |
| 23147 | + |
| 23148 | +static inline void ims332_set_color_depth(struct ims332_regs *regs, u32 depth) |
| 23149 | +{ |
| 23150 | + u32 dp; |
| 23151 | + u32 mask = (IMS332_CTRL_A_PIXEL_PORT_INTERLEAVING |
| 23152 | + | IMS332_CTRL_A_DELAYED_SAMPLING |
| 23153 | + | IMS332_CTRL_A_BITS_PER_PIXEL); |
| 23154 | + |
| 23155 | + switch (depth) { |
| 23156 | + case 1: dp = 0 << 20; break; |
| 23157 | + case 2: dp = 1 << 20; break; |
| 23158 | + case 4: dp = 2 << 20; break; |
| 23159 | + case 8: dp = 3 << 20; break; |
| 23160 | + case 15: dp = (4 << 20) | IMS332_CTRL_A_PIXEL_PORT_INTERLEAVING; break; |
| 23161 | + case 16: dp = (5 << 20) | IMS332_CTRL_A_PIXEL_PORT_INTERLEAVING; break; |
| 23162 | + default: return; |
| 23163 | + } |
| 23164 | + ims332_control_reg_bits(regs, mask, dp); |
| 23165 | + |
| 23166 | + if (depth <= 8) { |
| 23167 | + volatile u16 *pmask = &(regs->w.pixel_address_mask.r); |
| 23168 | + u32 dm = (1 << depth) - 1; |
| 23169 | + |
| 23170 | + wmb(); |
| 23171 | + regs->rw.boot.r = dm << 8; |
| 23172 | + wmb(); |
| 23173 | + *pmask = dm << 8 | dm; |
| 23174 | + } |
| 23175 | +} |
| 23176 | + |
| 23177 | +static inline void ims332_set_screen_top(struct ims332_regs *regs, u16 top) |
| 23178 | +{ |
| 23179 | + volatile u16 *st = &(regs->w.screen_top.r); |
| 23180 | + |
| 23181 | + mb(); |
| 23182 | + *st = top & 0xffff; |
| 23183 | +} |
| 23184 | + |
| 23185 | +static inline void ims332_enable_cursor(struct ims332_regs *regs, int on) |
| 23186 | +{ |
| 23187 | + ims332_control_reg_bits(regs, IMS332_CTRL_A_CURSOR_DISABLE, |
| 23188 | + on ? 0 : IMS332_CTRL_A_CURSOR_DISABLE); |
| 23189 | +} |
| 23190 | + |
| 23191 | +static inline void ims332_position_cursor(struct ims332_regs *regs, |
| 23192 | + u16 x, u16 y) |
| 23193 | +{ |
| 23194 | + volatile u16 *cp = &(regs->w.cursor_start.r); |
| 23195 | + u32 val = ((x & 0xfff) << 12) | (y & 0xfff); |
| 23196 | + |
| 23197 | + if (x > 2303 || y > 2303) |
| 23198 | + return; |
| 23199 | + |
| 23200 | + mb(); |
| 23201 | + regs->rw.boot.r = (val >> 8) & 0xff00; |
| 23202 | + wmb(); |
| 23203 | + *cp = val & 0xffff; |
| 23204 | +} |
| 23205 | + |
| 23206 | +static inline void ims332_set_font(struct ims332_regs *regs, u8 fgc, |
| 23207 | + u16 width, u16 height) |
| 23208 | +{ |
| 23209 | + volatile u16 *cp0 = &(regs->w.cursor_color_palette0.r); |
| 23210 | + int i; |
| 23211 | + |
| 23212 | + mb(); |
| 23213 | + for (i = 0; i < 0x200; i++) { |
| 23214 | + volatile u16 *cram = &(regs->w.cursor_ram[i].r); |
| 23215 | + |
| 23216 | + if (height << 6 <= i << 3) |
| 23217 | + *cram = 0x0000; |
| 23218 | + else if (width <= i % 8 << 3) |
| 23219 | + *cram = 0x0000; |
| 23220 | + else if (((width >> 3) & 0xffff) > i % 8) |
| 23221 | + *cram = 0x5555; |
| 23222 | + else |
| 23223 | + *cram = 0x5555 & ~(0xffff << (width % 8 << 1)); |
| 23224 | + wmb(); |
| 23225 | + } |
| 23226 | + regs->rw.boot.r = fgc << 8; |
| 23227 | + wmb(); |
| 23228 | + *cp0 = fgc << 8 | fgc; |
| 23229 | +} |
| 23230 | + |
| 23231 | +static inline void ims332_read_cmap(struct ims332_regs *regs, u8 reg, |
| 23232 | + u8* red, u8* green, u8* blue) |
| 23233 | +{ |
| 23234 | + volatile u16 *rptr = &(regs->r.color_palette[reg].r); |
| 23235 | + u16 val; |
| 23236 | + |
| 23237 | + mb(); |
| 23238 | + val = *rptr; |
| 23239 | + *red = val & 0xff; |
| 23240 | + *green = (val >> 8) & 0xff; |
| 23241 | + rmb(); |
| 23242 | + *blue = (regs->rw.boot.r >> 8) & 0xff; |
| 23243 | +} |
| 23244 | + |
| 23245 | +static inline void ims332_write_cmap(struct ims332_regs *regs, u8 reg, |
| 23246 | + u8 red, u8 green, u8 blue) |
| 23247 | +{ |
| 23248 | + volatile u16 *wptr = &(regs->w.color_palette[reg].r); |
| 23249 | + |
| 23250 | + mb(); |
| 23251 | + regs->rw.boot.r = blue << 8; |
| 23252 | + wmb(); |
| 23253 | + *wptr = (green << 8) + red; |
| 23254 | +} |
| 23255 | + |
| 23256 | +static inline void ims332_dump_regs(struct ims332_regs *regs) |
| 23257 | +{ |
| 23258 | + int i; |
| 23259 | + |
| 23260 | + printk(__FUNCTION__); |
| 23261 | + ims332_control_reg_bits(regs, IMS332_CTRL_A_BOOT_ENABLE_VTG, 0); |
| 23262 | + for (i = 0; i < 0x100; i++) { |
| 23263 | + volatile u16 *cpad = (u16 *)((char *)(®s->r) + sizeof(struct _ims332_reg) * i); |
| 23264 | + u32 val; |
| 23265 | + |
| 23266 | + val = *cpad; |
| 23267 | + rmb(); |
| 23268 | + val |= regs->rw.boot.r << 8; |
| 23269 | + rmb(); |
| 23270 | + if (! (i % 8)) |
| 23271 | + printk("\n%02x:", i); |
| 23272 | + printk(" %06x", val); |
| 23273 | + } |
| 23274 | + ims332_control_reg_bits(regs, IMS332_CTRL_A_BOOT_ENABLE_VTG, |
| 23275 | + IMS332_CTRL_A_BOOT_ENABLE_VTG); |
| 23276 | + printk("\n"); |
| 23277 | +} |
| 23278 | --- a/drivers/video/Makefile |
| 23279 | +++ b/drivers/video/Makefile |
| 23280 | @@ -87,6 +87,7 @@ obj-$(CONFIG_FB_PMAGB_B) += pma |
| 23281 | obj-$(CONFIG_FB_MAXINE) += maxinefb.o |
| 23282 | obj-$(CONFIG_FB_TX3912) += tx3912fb.o |
| 23283 | obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o |
| 23284 | +obj-$(CONFIG_FB_AU1200) += au1200fb.o fbgen.o |
| 23285 | obj-$(CONFIG_FB_IT8181) += it8181fb.o fbgen.o |
| 23286 | |
| 23287 | subdir-$(CONFIG_STI_CONSOLE) += sti |
| 23288 | --- a/drivers/video/maxinefb.h |
| 23289 | +++ /dev/null |
| 23290 | @@ -1,38 +0,0 @@ |
| 23291 | -/* |
| 23292 | - * linux/drivers/video/maxinefb.h |
| 23293 | - * |
| 23294 | - * DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by |
| 23295 | - * Michael Engel <engel@unix-ag.org> and Karsten Merker <merker@guug.de> |
| 23296 | - * This file is subject to the terms and conditions of the GNU General |
| 23297 | - * Public License. See the file COPYING in the main directory of this |
| 23298 | - * archive for more details. |
| 23299 | - */ |
| 23300 | - |
| 23301 | -#include <asm/addrspace.h> |
| 23302 | - |
| 23303 | -/* |
| 23304 | - * IMS332 video controller register base address |
| 23305 | - */ |
| 23306 | -#define MAXINEFB_IMS332_ADDRESS KSEG1ADDR(0x1c140000) |
| 23307 | - |
| 23308 | -/* |
| 23309 | - * Begin of DECstation 5000/xx onboard framebuffer memory, default resolution |
| 23310 | - * is 1024x768x8 |
| 23311 | - */ |
| 23312 | -#define DS5000_xx_ONBOARD_FBMEM_START KSEG1ADDR(0x0a000000) |
| 23313 | - |
| 23314 | -/* |
| 23315 | - * The IMS 332 video controller used in the DECstation 5000/xx series |
| 23316 | - * uses 32 bits wide registers; the following defines declare the |
| 23317 | - * register numbers, to get the real offset, these have to be multiplied |
| 23318 | - * by four. |
| 23319 | - */ |
| 23320 | - |
| 23321 | -#define IMS332_REG_CURSOR_RAM 0x200 /* hardware cursor bitmap */ |
| 23322 | - |
| 23323 | -/* |
| 23324 | - * The color palette entries have the form 0x00BBGGRR |
| 23325 | - */ |
| 23326 | -#define IMS332_REG_COLOR_PALETTE 0x100 /* color palette, 256 entries */ |
| 23327 | -#define IMS332_REG_CURSOR_COLOR_PALETTE 0x0a1 /* cursor color palette, */ |
| 23328 | - /* 3 entries */ |
| 23329 | --- a/drivers/video/newport_con.c |
| 23330 | +++ b/drivers/video/newport_con.c |
| 23331 | @@ -22,6 +22,7 @@ |
| 23332 | #include <linux/module.h> |
| 23333 | #include <linux/slab.h> |
| 23334 | |
| 23335 | +#include <asm/io.h> |
| 23336 | #include <asm/uaccess.h> |
| 23337 | #include <asm/system.h> |
| 23338 | #include <asm/page.h> |
| 23339 | @@ -77,7 +78,7 @@ static int newport_set_def_font(int unit |
| 23340 | static inline void newport_render_background(int xstart, int ystart, |
| 23341 | int xend, int yend, int ci) |
| 23342 | { |
| 23343 | - newport_wait(); |
| 23344 | + newport_wait(npregs); |
| 23345 | npregs->set.wrmask = 0xffffffff; |
| 23346 | npregs->set.drawmode0 = (NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK | |
| 23347 | NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX |
| 23348 | @@ -94,7 +95,7 @@ static inline void newport_init_cmap(voi |
| 23349 | unsigned short i; |
| 23350 | |
| 23351 | for (i = 0; i < 16; i++) { |
| 23352 | - newport_bfwait(); |
| 23353 | + newport_bfwait(npregs); |
| 23354 | newport_cmap_setaddr(npregs, color_table[i]); |
| 23355 | newport_cmap_setrgb(npregs, |
| 23356 | default_red[i], |
| 23357 | @@ -107,7 +108,7 @@ static inline void newport_show_logo(voi |
| 23358 | unsigned long i; |
| 23359 | |
| 23360 | for (i = 0; i < LINUX_LOGO_COLORS; i++) { |
| 23361 | - newport_bfwait(); |
| 23362 | + newport_bfwait(npregs); |
| 23363 | newport_cmap_setaddr(npregs, i + 0x20); |
| 23364 | newport_cmap_setrgb(npregs, |
| 23365 | linux_logo_red[i], |
| 23366 | @@ -115,13 +116,13 @@ static inline void newport_show_logo(voi |
| 23367 | linux_logo_blue[i]); |
| 23368 | } |
| 23369 | |
| 23370 | - newport_wait(); |
| 23371 | + newport_wait(npregs); |
| 23372 | npregs->set.drawmode0 = (NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK | |
| 23373 | NPORT_DMODE0_CHOST); |
| 23374 | |
| 23375 | npregs->set.xystarti = ((newport_xsize - LOGO_W) << 16) | (0); |
| 23376 | npregs->set.xyendi = ((newport_xsize - 1) << 16); |
| 23377 | - newport_wait(); |
| 23378 | + newport_wait(npregs); |
| 23379 | |
| 23380 | for (i = 0; i < LOGO_W * LOGO_H; i++) |
| 23381 | npregs->go.hostrw0 = linux_logo[i] << 24; |
| 23382 | @@ -133,7 +134,7 @@ static inline void newport_clear_screen( |
| 23383 | if (logo_active) |
| 23384 | return; |
| 23385 | |
| 23386 | - newport_wait(); |
| 23387 | + newport_wait(npregs); |
| 23388 | npregs->set.wrmask = 0xffffffff; |
| 23389 | npregs->set.drawmode0 = (NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK | |
| 23390 | NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX |
| 23391 | @@ -155,7 +156,7 @@ void newport_reset(void) |
| 23392 | unsigned short treg; |
| 23393 | int i; |
| 23394 | |
| 23395 | - newport_wait(); |
| 23396 | + newport_wait(npregs); |
| 23397 | treg = newport_vc2_get(npregs, VC2_IREG_CONTROL); |
| 23398 | newport_vc2_set(npregs, VC2_IREG_CONTROL, |
| 23399 | (treg | VC2_CTRL_EVIDEO)); |
| 23400 | @@ -165,7 +166,7 @@ void newport_reset(void) |
| 23401 | npregs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM | |
| 23402 | NPORT_DMODE_W2 | VC2_PROTOCOL); |
| 23403 | for (i = 0; i < 128; i++) { |
| 23404 | - newport_bfwait(); |
| 23405 | + newport_bfwait(npregs); |
| 23406 | if (i == 92 || i == 94) |
| 23407 | npregs->set.dcbdata0.byshort.s1 = 0xff00; |
| 23408 | else |
| 23409 | @@ -205,7 +206,7 @@ void newport_get_screensize(void) |
| 23410 | npregs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM | |
| 23411 | NPORT_DMODE_W2 | VC2_PROTOCOL); |
| 23412 | for (i = 0; i < 128; i++) { |
| 23413 | - newport_bfwait(); |
| 23414 | + newport_bfwait(npregs); |
| 23415 | linetable[i] = npregs->set.dcbdata0.byshort.s1; |
| 23416 | } |
| 23417 | |
| 23418 | @@ -216,12 +217,12 @@ void newport_get_screensize(void) |
| 23419 | npregs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM | |
| 23420 | NPORT_DMODE_W2 | VC2_PROTOCOL); |
| 23421 | do { |
| 23422 | - newport_bfwait(); |
| 23423 | + newport_bfwait(npregs); |
| 23424 | treg = npregs->set.dcbdata0.byshort.s1; |
| 23425 | if ((treg & 1) == 0) |
| 23426 | cols += (treg >> 7) & 0xfe; |
| 23427 | if ((treg & 0x80) == 0) { |
| 23428 | - newport_bfwait(); |
| 23429 | + newport_bfwait(npregs); |
| 23430 | treg = npregs->set.dcbdata0.byshort.s1; |
| 23431 | } |
| 23432 | } while ((treg & 0x8000) == 0); |
| 23433 | @@ -291,16 +292,16 @@ static const char *newport_startup(void) |
| 23434 | |
| 23435 | if (!sgi_gfxaddr) |
| 23436 | return NULL; |
| 23437 | - npregs = (struct newport_regs *) (KSEG1 + sgi_gfxaddr); |
| 23438 | + npregs = (struct newport_regs *) /* ioremap cannot fail */ |
| 23439 | + ioremap(sgi_gfxaddr, sizeof(struct newport_regs)); |
| 23440 | npregs->cset.config = NPORT_CFG_GD0; |
| 23441 | |
| 23442 | - if (newport_wait()) { |
| 23443 | - return NULL; |
| 23444 | - } |
| 23445 | + if (newport_wait(npregs)) |
| 23446 | + goto out_unmap; |
| 23447 | |
| 23448 | npregs->set.xstarti = TESTVAL; |
| 23449 | if (npregs->set._xstart.word != XSTI_TO_FXSTART(TESTVAL)) |
| 23450 | - return NULL; |
| 23451 | + goto out_unmap; |
| 23452 | |
| 23453 | for (i = 0; i < MAX_NR_CONSOLES; i++) |
| 23454 | font_data[i] = FONT_DATA; |
| 23455 | @@ -310,6 +311,10 @@ static const char *newport_startup(void) |
| 23456 | newport_get_screensize(); |
| 23457 | |
| 23458 | return "SGI Newport"; |
| 23459 | + |
| 23460 | +out_unmap: |
| 23461 | + iounmap((void *)npregs); |
| 23462 | + return NULL; |
| 23463 | } |
| 23464 | |
| 23465 | static void newport_init(struct vc_data *vc, int init) |
| 23466 | @@ -363,7 +368,7 @@ static void newport_putc(struct vc_data |
| 23467 | (charattr & 0xf0) >> 4); |
| 23468 | |
| 23469 | /* Set the color and drawing mode. */ |
| 23470 | - newport_wait(); |
| 23471 | + newport_wait(npregs); |
| 23472 | npregs->set.colori = charattr & 0xf; |
| 23473 | npregs->set.drawmode0 = (NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK | |
| 23474 | NPORT_DMODE0_STOPX | NPORT_DMODE0_ZPENAB | |
| 23475 | @@ -372,7 +377,7 @@ static void newport_putc(struct vc_data |
| 23476 | /* Set coordinates for bitmap operation. */ |
| 23477 | npregs->set.xystarti = (xpos << 16) | ((ypos + topscan) & 0x3ff); |
| 23478 | npregs->set.xyendi = ((xpos + 7) << 16); |
| 23479 | - newport_wait(); |
| 23480 | + newport_wait(npregs); |
| 23481 | |
| 23482 | /* Go, baby, go... */ |
| 23483 | RENDER(npregs, p); |
| 23484 | @@ -396,7 +401,7 @@ static void newport_putcs(struct vc_data |
| 23485 | xpos + ((count - 1) << 3), ypos, |
| 23486 | (charattr & 0xf0) >> 4); |
| 23487 | |
| 23488 | - newport_wait(); |
| 23489 | + newport_wait(npregs); |
| 23490 | |
| 23491 | /* Set the color and drawing mode. */ |
| 23492 | npregs->set.colori = charattr & 0xf; |
| 23493 | @@ -407,7 +412,7 @@ static void newport_putcs(struct vc_data |
| 23494 | for (i = 0; i < count; i++, xpos += 8) { |
| 23495 | p = &font_data[vc->vc_num][(scr_readw(s++) & 0xff) << 4]; |
| 23496 | |
| 23497 | - newport_wait(); |
| 23498 | + newport_wait(npregs); |
| 23499 | |
| 23500 | /* Set coordinates for bitmap operation. */ |
| 23501 | npregs->set.xystarti = |
| 23502 | @@ -689,7 +694,7 @@ static void newport_bmove(struct vc_data |
| 23503 | xe = xs; |
| 23504 | xs = tmp; |
| 23505 | } |
| 23506 | - newport_wait(); |
| 23507 | + newport_wait(npregs); |
| 23508 | npregs->set.drawmode0 = (NPORT_DMODE0_S2S | NPORT_DMODE0_BLOCK | |
| 23509 | NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX |
| 23510 | | NPORT_DMODE0_STOPY); |
| 23511 | @@ -706,35 +711,35 @@ static int newport_dummy(struct vc_data |
| 23512 | #define DUMMY (void *) newport_dummy |
| 23513 | |
| 23514 | const struct consw newport_con = { |
| 23515 | - con_startup: newport_startup, |
| 23516 | - con_init: newport_init, |
| 23517 | - con_deinit: newport_deinit, |
| 23518 | - con_clear: newport_clear, |
| 23519 | - con_putc: newport_putc, |
| 23520 | - con_putcs: newport_putcs, |
| 23521 | - con_cursor: newport_cursor, |
| 23522 | - con_scroll: newport_scroll, |
| 23523 | - con_bmove: newport_bmove, |
| 23524 | - con_switch: newport_switch, |
| 23525 | - con_blank: newport_blank, |
| 23526 | - con_font_op: newport_font_op, |
| 23527 | - con_set_palette: newport_set_palette, |
| 23528 | - con_scrolldelta: newport_scrolldelta, |
| 23529 | - con_set_origin: DUMMY, |
| 23530 | - con_save_screen: DUMMY |
| 23531 | + .con_startup = newport_startup, |
| 23532 | + .con_init = newport_init, |
| 23533 | + .con_deinit = newport_deinit, |
| 23534 | + .con_clear = newport_clear, |
| 23535 | + .con_putc = newport_putc, |
| 23536 | + .con_putcs = newport_putcs, |
| 23537 | + .con_cursor = newport_cursor, |
| 23538 | + .con_scroll = newport_scroll, |
| 23539 | + .con_bmove = newport_bmove, |
| 23540 | + .con_switch = newport_switch, |
| 23541 | + .con_blank = newport_blank, |
| 23542 | + .con_font_op = newport_font_op, |
| 23543 | + .con_set_palette = newport_set_palette, |
| 23544 | + .con_scrolldelta = newport_scrolldelta, |
| 23545 | + .con_set_origin = DUMMY, |
| 23546 | + .con_save_screen = DUMMY |
| 23547 | }; |
| 23548 | |
| 23549 | #ifdef MODULE |
| 23550 | static int __init newport_console_init(void) |
| 23551 | { |
| 23552 | take_over_console(&newport_con, 0, MAX_NR_CONSOLES - 1, 1); |
| 23553 | - |
| 23554 | return 0; |
| 23555 | } |
| 23556 | |
| 23557 | static void __exit newport_console_exit(void) |
| 23558 | { |
| 23559 | give_up_console(&newport_con); |
| 23560 | + iounmap((void *)npregs); |
| 23561 | } |
| 23562 | |
| 23563 | module_init(newport_console_init); |
| 23564 | --- a/drivers/video/tgafb.c |
| 23565 | +++ b/drivers/video/tgafb.c |
| 23566 | @@ -45,6 +45,15 @@ |
| 23567 | #include <linux/console.h> |
| 23568 | #include <asm/io.h> |
| 23569 | |
| 23570 | +#ifdef CONFIG_TC |
| 23571 | +#include <asm/dec/tc.h> |
| 23572 | +#else |
| 23573 | +static int search_tc_card(const char *) { return -1; } |
| 23574 | +static void claim_tc_card(int) { } |
| 23575 | +static void release_tc_card(int) { } |
| 23576 | +static unsigned long get_tc_base_addr(int) { return 0; } |
| 23577 | +#endif |
| 23578 | + |
| 23579 | #include <video/fbcon.h> |
| 23580 | #include <video/fbcon-cfb8.h> |
| 23581 | #include <video/fbcon-cfb32.h> |
| 23582 | @@ -84,10 +93,10 @@ static unsigned int fb_offset_presets[4] |
| 23583 | }; |
| 23584 | |
| 23585 | static unsigned int deep_presets[4] = { |
| 23586 | - 0x00014000, |
| 23587 | - 0x0001440d, |
| 23588 | + 0x00004000, |
| 23589 | + 0x0000440d, |
| 23590 | 0xffffffff, |
| 23591 | - 0x0001441d |
| 23592 | + 0x0000441d |
| 23593 | }; |
| 23594 | |
| 23595 | static unsigned int rasterop_presets[4] = { |
| 23596 | @@ -131,6 +140,13 @@ static struct { |
| 23597 | 0, |
| 23598 | FB_VMODE_NONINTERLACED |
| 23599 | }}, |
| 23600 | + { "1280x1024-72", { /* mode #0 of PMAGD boards */ |
| 23601 | + 1280, 1024, 1280, 1024, 0, 0, 0, 0, |
| 23602 | + {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, |
| 23603 | + 0, 0, -1, -1, FB_ACCELF_TEXT, 7692, 232, 32, 34, 3, 160, 3, |
| 23604 | + FB_SYNC_ON_GREEN, |
| 23605 | + FB_VMODE_NONINTERLACED |
| 23606 | + }}, |
| 23607 | { "800x600-56", { |
| 23608 | 800, 600, 800, 600, 0, 0, 0, 0, |
| 23609 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, |
| 23610 | @@ -488,7 +504,8 @@ static void tgafb_set_par(const void *fb |
| 23611 | continue; |
| 23612 | |
| 23613 | mb(); |
| 23614 | - TGA_WRITE_REG(deep_presets[fb_info.tga_type], TGA_DEEP_REG); |
| 23615 | + TGA_WRITE_REG(deep_presets[fb_info.tga_type] | |
| 23616 | + (par->sync_on_green ? 0x0 : 0x00010000), TGA_DEEP_REG); |
| 23617 | while (TGA_READ_REG(TGA_CMD_STAT_REG) & 1) /* wait for not busy */ |
| 23618 | continue; |
| 23619 | mb(); |
| 23620 | @@ -548,7 +565,7 @@ static void tgafb_set_par(const void *fb |
| 23621 | BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, 0x40); |
| 23622 | BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, 0x08); |
| 23623 | BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, |
| 23624 | - (par->sync_on_green ? 0x80 : 0x40)); |
| 23625 | + (par->sync_on_green ? 0xc0 : 0x40)); |
| 23626 | |
| 23627 | BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, 0xff); |
| 23628 | BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, 0xff); |
| 23629 | @@ -921,19 +938,34 @@ int __init tgafb_setup(char *options) { |
| 23630 | int __init tgafb_init(void) |
| 23631 | { |
| 23632 | struct pci_dev *pdev; |
| 23633 | + int slot; |
| 23634 | |
| 23635 | pdev = pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, NULL); |
| 23636 | if (!pdev) |
| 23637 | + slot = search_tc_card("PMAGD"); |
| 23638 | + if (!pdev && slot < 0) |
| 23639 | return -ENXIO; |
| 23640 | |
| 23641 | /* divine board type */ |
| 23642 | |
| 23643 | - fb_info.tga_mem_base = (unsigned long)ioremap(pdev->resource[0].start, 0); |
| 23644 | - fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f; |
| 23645 | - fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET; |
| 23646 | - fb_info.tga_fb_base = (fb_info.tga_mem_base |
| 23647 | + if (pdev) { |
| 23648 | + fb_info.tga_mem_base = (unsigned long)ioremap(pdev->resource[0].start, |
| 23649 | + 0); |
| 23650 | + fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f; |
| 23651 | + fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET; |
| 23652 | + fb_info.tga_fb_base = (fb_info.tga_mem_base |
| 23653 | + fb_offset_presets[fb_info.tga_type]); |
| 23654 | - pci_read_config_byte(pdev, PCI_REVISION_ID, &fb_info.tga_chip_rev); |
| 23655 | + pci_read_config_byte(pdev, PCI_REVISION_ID, &fb_info.tga_chip_rev); |
| 23656 | + |
| 23657 | + } else { |
| 23658 | + claim_tc_card(slot); |
| 23659 | + fb_info.tga_mem_base = get_tc_base_addr(slot); |
| 23660 | + fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f; /* ? */ |
| 23661 | + fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET; |
| 23662 | + fb_info.tga_fb_base = (fb_info.tga_mem_base |
| 23663 | + + fb_offset_presets[fb_info.tga_type]); |
| 23664 | + fb_info.tga_chip_rev = TGA_READ_REG(TGA_START_REG) & 0xff; |
| 23665 | + } |
| 23666 | |
| 23667 | /* setup framebuffer */ |
| 23668 | |
| 23669 | @@ -950,40 +982,62 @@ int __init tgafb_init(void) |
| 23670 | fb_info.gen.fbhw = &tgafb_hwswitch; |
| 23671 | fb_info.gen.fbhw->detect(); |
| 23672 | |
| 23673 | - printk (KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", fb_info.tga_chip_rev); |
| 23674 | - printk (KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", |
| 23675 | - pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
| 23676 | + if (pdev) { |
| 23677 | + printk (KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", |
| 23678 | + fb_info.tga_chip_rev); |
| 23679 | + printk (KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", |
| 23680 | + pdev->bus->number, |
| 23681 | + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
| 23682 | + } else { |
| 23683 | + printk (KERN_INFO "tgafb: SFB+ detected, rev=0x%02x\n", |
| 23684 | + fb_info.tga_chip_rev); |
| 23685 | + } |
| 23686 | |
| 23687 | switch (fb_info.tga_type) |
| 23688 | { |
| 23689 | case TGA_TYPE_8PLANE: |
| 23690 | - strcpy (fb_info.gen.info.modename,"Digital ZLXp-E1"); |
| 23691 | + if (pdev) |
| 23692 | + strcpy (fb_info.gen.info.modename,"Digital ZLXp-E1"); |
| 23693 | + else |
| 23694 | + strcpy (fb_info.gen.info.modename,"Digital ZLX-E1"); |
| 23695 | break; |
| 23696 | |
| 23697 | case TGA_TYPE_24PLANE: |
| 23698 | - strcpy (fb_info.gen.info.modename,"Digital ZLXp-E2"); |
| 23699 | + if (pdev) |
| 23700 | + strcpy (fb_info.gen.info.modename,"Digital ZLXp-E2"); |
| 23701 | + else |
| 23702 | + strcpy (fb_info.gen.info.modename,"Digital ZLX-E2"); |
| 23703 | break; |
| 23704 | |
| 23705 | case TGA_TYPE_24PLUSZ: |
| 23706 | - strcpy (fb_info.gen.info.modename,"Digital ZLXp-E3"); |
| 23707 | + if (pdev) |
| 23708 | + strcpy (fb_info.gen.info.modename,"Digital ZLXp-E3"); |
| 23709 | + else |
| 23710 | + strcpy (fb_info.gen.info.modename,"Digital ZLX-E3"); |
| 23711 | break; |
| 23712 | } |
| 23713 | |
| 23714 | /* This should give a reasonable default video mode */ |
| 23715 | |
| 23716 | if (!default_var_valid) { |
| 23717 | - default_var = tgafb_predefined[0].var; |
| 23718 | + if (pdev) |
| 23719 | + default_var = tgafb_predefined[0].var; |
| 23720 | + else |
| 23721 | + default_var = tgafb_predefined[1].var; |
| 23722 | } |
| 23723 | fbgen_get_var(&disp.var, -1, &fb_info.gen.info); |
| 23724 | disp.var.activate = FB_ACTIVATE_NOW; |
| 23725 | fbgen_do_set_var(&disp.var, 1, &fb_info.gen); |
| 23726 | fbgen_set_disp(-1, &fb_info.gen); |
| 23727 | fbgen_install_cmap(0, &fb_info.gen); |
| 23728 | - if (register_framebuffer(&fb_info.gen.info) < 0) |
| 23729 | + if (register_framebuffer(&fb_info.gen.info) < 0) { |
| 23730 | + if (slot >= 0) |
| 23731 | + release_tc_card(slot); |
| 23732 | return -EINVAL; |
| 23733 | - printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n", |
| 23734 | + } |
| 23735 | + printk(KERN_INFO "fb%d: %s frame buffer device at 0x%llx\n", |
| 23736 | GET_FB_IDX(fb_info.gen.info.node), fb_info.gen.info.modename, |
| 23737 | - pdev->resource[0].start); |
| 23738 | + fb_info.tga_mem_base); |
| 23739 | return 0; |
| 23740 | } |
| 23741 | |
| 23742 | --- a/drivers/video/tgafb.h |
| 23743 | +++ b/drivers/video/tgafb.h |
| 23744 | @@ -36,6 +36,7 @@ |
| 23745 | #define TGA_RASTEROP_REG 0x0034 |
| 23746 | #define TGA_PIXELSHIFT_REG 0x0038 |
| 23747 | #define TGA_DEEP_REG 0x0050 |
| 23748 | +#define TGA_START_REG 0x0054 |
| 23749 | #define TGA_PIXELMASK_REG 0x005c |
| 23750 | #define TGA_CURSOR_BASE_REG 0x0060 |
| 23751 | #define TGA_HORIZ_REG 0x0064 |
| 23752 | --- a/fs/binfmt_elf.c |
| 23753 | +++ b/fs/binfmt_elf.c |
| 23754 | @@ -665,6 +665,9 @@ static int load_elf_binary(struct linux_ |
| 23755 | bprm->argc++; |
| 23756 | } |
| 23757 | } |
| 23758 | + } else { |
| 23759 | + /* Executables without an interpreter also need a personality */ |
| 23760 | + SET_PERSONALITY(elf_ex, ibcs2_interpreter); |
| 23761 | } |
| 23762 | |
| 23763 | /* Flush all traces of the currently running executable */ |
| 23764 | @@ -1225,7 +1228,11 @@ static int elf_core_dump(long signr, str |
| 23765 | elf.e_entry = 0; |
| 23766 | elf.e_phoff = sizeof(elf); |
| 23767 | elf.e_shoff = 0; |
| 23768 | +#ifdef ELF_CORE_EFLAGS |
| 23769 | + elf.e_flags = ELF_CORE_EFLAGS; |
| 23770 | +#else |
| 23771 | elf.e_flags = 0; |
| 23772 | +#endif |
| 23773 | elf.e_ehsize = sizeof(elf); |
| 23774 | elf.e_phentsize = sizeof(struct elf_phdr); |
| 23775 | elf.e_phnum = segs+1; /* Include notes */ |
| 23776 | --- a/fs/partitions/sgi.c |
| 23777 | +++ b/fs/partitions/sgi.c |
| 23778 | @@ -17,6 +17,11 @@ |
| 23779 | #include "check.h" |
| 23780 | #include "sgi.h" |
| 23781 | |
| 23782 | +#if CONFIG_BLK_DEV_MD |
| 23783 | +extern void md_autodetect_dev(kdev_t dev); |
| 23784 | +#endif |
| 23785 | + |
| 23786 | + |
| 23787 | int sgi_partition(struct gendisk *hd, struct block_device *bdev, unsigned long first_sector, int current_minor) |
| 23788 | { |
| 23789 | int i, csum, magic; |
| 23790 | @@ -77,6 +82,10 @@ int sgi_partition(struct gendisk *hd, st |
| 23791 | if(!blocks) |
| 23792 | continue; |
| 23793 | add_gd_partition(hd, current_minor, start, blocks); |
| 23794 | +#ifdef CONFIG_BLK_DEV_MD |
| 23795 | + if (be32_to_cpu(p->type) == LINUX_RAID_PARTITION) |
| 23796 | + md_autodetect_dev(MKDEV(hd->major, current_minor)); |
| 23797 | +#endif |
| 23798 | current_minor++; |
| 23799 | } |
| 23800 | printk("\n"); |
| 23801 | --- a/fs/proc/array.c |
| 23802 | +++ b/fs/proc/array.c |
| 23803 | @@ -376,15 +376,15 @@ int proc_pid_stat(struct task_struct *ta |
| 23804 | task->cmin_flt, |
| 23805 | task->maj_flt, |
| 23806 | task->cmaj_flt, |
| 23807 | - task->times.tms_utime, |
| 23808 | - task->times.tms_stime, |
| 23809 | - task->times.tms_cutime, |
| 23810 | - task->times.tms_cstime, |
| 23811 | + hz_to_std(task->times.tms_utime), |
| 23812 | + hz_to_std(task->times.tms_stime), |
| 23813 | + hz_to_std(task->times.tms_cutime), |
| 23814 | + hz_to_std(task->times.tms_cstime), |
| 23815 | priority, |
| 23816 | nice, |
| 23817 | 0UL /* removed */, |
| 23818 | task->it_real_value, |
| 23819 | - task->start_time, |
| 23820 | + hz_to_std(task->start_time), |
| 23821 | vsize, |
| 23822 | mm ? mm->rss : 0, /* you might want to shift this left 3 */ |
| 23823 | task->rlim[RLIMIT_RSS].rlim_cur, |
| 23824 | @@ -629,14 +629,14 @@ int proc_pid_cpu(struct task_struct *tas |
| 23825 | |
| 23826 | len = sprintf(buffer, |
| 23827 | "cpu %lu %lu\n", |
| 23828 | - task->times.tms_utime, |
| 23829 | - task->times.tms_stime); |
| 23830 | + hz_to_std(task->times.tms_utime), |
| 23831 | + hz_to_std(task->times.tms_stime)); |
| 23832 | |
| 23833 | for (i = 0 ; i < smp_num_cpus; i++) |
| 23834 | len += sprintf(buffer + len, "cpu%d %lu %lu\n", |
| 23835 | i, |
| 23836 | - task->per_cpu_utime[cpu_logical_map(i)], |
| 23837 | - task->per_cpu_stime[cpu_logical_map(i)]); |
| 23838 | + hz_to_std(task->per_cpu_utime[cpu_logical_map(i)]), |
| 23839 | + hz_to_std(task->per_cpu_stime[cpu_logical_map(i)])); |
| 23840 | |
| 23841 | return len; |
| 23842 | } |
| 23843 | --- a/fs/proc/proc_misc.c |
| 23844 | +++ b/fs/proc/proc_misc.c |
| 23845 | @@ -308,16 +308,16 @@ static int kstat_read_proc(char *page, c |
| 23846 | { |
| 23847 | int i, len = 0; |
| 23848 | extern unsigned long total_forks; |
| 23849 | - unsigned long jif = jiffies; |
| 23850 | + unsigned long jif = hz_to_std(jiffies); |
| 23851 | unsigned int sum = 0, user = 0, nice = 0, system = 0; |
| 23852 | int major, disk; |
| 23853 | |
| 23854 | for (i = 0 ; i < smp_num_cpus; i++) { |
| 23855 | int cpu = cpu_logical_map(i), j; |
| 23856 | |
| 23857 | - user += kstat.per_cpu_user[cpu]; |
| 23858 | - nice += kstat.per_cpu_nice[cpu]; |
| 23859 | - system += kstat.per_cpu_system[cpu]; |
| 23860 | + user += hz_to_std(kstat.per_cpu_user[cpu]); |
| 23861 | + nice += hz_to_std(kstat.per_cpu_nice[cpu]); |
| 23862 | + system += hz_to_std(kstat.per_cpu_system[cpu]); |
| 23863 | #if !defined(CONFIG_ARCH_S390) |
| 23864 | for (j = 0 ; j < NR_IRQS ; j++) |
| 23865 | sum += kstat.irqs[cpu][j]; |
| 23866 | @@ -331,10 +331,10 @@ static int kstat_read_proc(char *page, c |
| 23867 | proc_sprintf(page, &off, &len, |
| 23868 | "cpu%d %u %u %u %lu\n", |
| 23869 | i, |
| 23870 | - kstat.per_cpu_user[cpu_logical_map(i)], |
| 23871 | - kstat.per_cpu_nice[cpu_logical_map(i)], |
| 23872 | - kstat.per_cpu_system[cpu_logical_map(i)], |
| 23873 | - jif - ( kstat.per_cpu_user[cpu_logical_map(i)] \ |
| 23874 | + hz_to_std(kstat.per_cpu_user[cpu_logical_map(i)]), |
| 23875 | + hz_to_std(kstat.per_cpu_nice[cpu_logical_map(i)]), |
| 23876 | + hz_to_std(kstat.per_cpu_system[cpu_logical_map(i)]), |
| 23877 | + jif - hz_to_std( kstat.per_cpu_user[cpu_logical_map(i)] \ |
| 23878 | + kstat.per_cpu_nice[cpu_logical_map(i)] \ |
| 23879 | + kstat.per_cpu_system[cpu_logical_map(i)])); |
| 23880 | proc_sprintf(page, &off, &len, |
| 23881 | --- a/include/asm-alpha/param.h |
| 23882 | +++ b/include/asm-alpha/param.h |
| 23883 | @@ -13,6 +13,9 @@ |
| 23884 | # else |
| 23885 | # define HZ 1200 |
| 23886 | # endif |
| 23887 | +#ifdef __KERNEL__ |
| 23888 | +# define hz_to_std(a) (a) |
| 23889 | +#endif |
| 23890 | #endif |
| 23891 | |
| 23892 | #define EXEC_PAGESIZE 8192 |
| 23893 | --- a/include/asm-i386/param.h |
| 23894 | +++ b/include/asm-i386/param.h |
| 23895 | @@ -3,6 +3,9 @@ |
| 23896 | |
| 23897 | #ifndef HZ |
| 23898 | #define HZ 100 |
| 23899 | +#ifdef __KERNEL__ |
| 23900 | +#define hz_to_std(a) (a) |
| 23901 | +#endif |
| 23902 | #endif |
| 23903 | |
| 23904 | #define EXEC_PAGESIZE 4096 |
| 23905 | --- a/include/asm-ia64/param.h |
| 23906 | +++ b/include/asm-ia64/param.h |
| 23907 | @@ -7,9 +7,15 @@ |
| 23908 | * Based on <asm-i386/param.h>. |
| 23909 | * |
| 23910 | * Modified 1998, 1999, 2002-2003 |
| 23911 | - * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co |
| 23912 | + * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co |
| 23913 | */ |
| 23914 | |
| 23915 | +#include <linux/config.h> |
| 23916 | + |
| 23917 | +#ifdef __KERNEL__ |
| 23918 | +#define hz_to_std(a) (a) |
| 23919 | +#endif |
| 23920 | + |
| 23921 | #define EXEC_PAGESIZE 65536 |
| 23922 | |
| 23923 | #ifndef NGROUPS |
| 23924 | --- a/include/asm-m68k/param.h |
| 23925 | +++ b/include/asm-m68k/param.h |
| 23926 | @@ -3,6 +3,9 @@ |
| 23927 | |
| 23928 | #ifndef HZ |
| 23929 | #define HZ 100 |
| 23930 | +#ifdef __KERNEL__ |
| 23931 | +#define hz_to_std(a) (a) |
| 23932 | +#endif |
| 23933 | #endif |
| 23934 | |
| 23935 | #define EXEC_PAGESIZE 8192 |
| 23936 | --- a/include/asm-mips/au1000_gpio.h |
| 23937 | +++ b/include/asm-mips/au1000_gpio.h |
| 23938 | @@ -30,6 +30,13 @@ |
| 23939 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23940 | */ |
| 23941 | |
| 23942 | +/* |
| 23943 | + * Revision history |
| 23944 | + * 01/31/02 0.01 Initial release. Steve Longerbeam, MontaVista |
| 23945 | + * 10/12/03 0.1 Added Au1100/Au1500, GPIO2, and bit operations. K.C. Nishio, AMD |
| 23946 | + * 08/05/04 0.11 Added Au1550 and Au1200. K.C. Nishio |
| 23947 | + */ |
| 23948 | + |
| 23949 | #ifndef __AU1000_GPIO_H |
| 23950 | #define __AU1000_GPIO_H |
| 23951 | |
| 23952 | @@ -44,13 +51,94 @@ |
| 23953 | #define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int) |
| 23954 | #define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int) |
| 23955 | |
| 23956 | +// bit operations |
| 23957 | +#define AU1000GPIO_BIT_READ _IOW (AU1000GPIO_IOC_MAGIC, 6, int) |
| 23958 | +#define AU1000GPIO_BIT_SET _IOW (AU1000GPIO_IOC_MAGIC, 7, int) |
| 23959 | +#define AU1000GPIO_BIT_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 8, int) |
| 23960 | +#define AU1000GPIO_BIT_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 9, int) |
| 23961 | +#define AU1000GPIO_BIT_INIT _IOW (AU1000GPIO_IOC_MAGIC, 10, int) |
| 23962 | +#define AU1000GPIO_BIT_TERM _IOW (AU1000GPIO_IOC_MAGIC, 11, int) |
| 23963 | + |
| 23964 | +/* set this major numer same as the CRIS GPIO driver */ |
| 23965 | +#define AU1X00_GPIO_MAJOR (120) |
| 23966 | + |
| 23967 | +#define ENABLED_ZERO (0) |
| 23968 | +#define ENABLED_ONE (1) |
| 23969 | +#define ENABLED_10 (0x2) |
| 23970 | +#define ENABLED_11 (0x3) |
| 23971 | +#define ENABLED_111 (0x7) |
| 23972 | +#define NOT_AVAIL (-1) |
| 23973 | +#define AU1X00_MAX_PRIMARY_GPIO (32) |
| 23974 | + |
| 23975 | +#define AU1000_GPIO_MINOR_MAX AU1X00_MAX_PRIMARY_GPIO |
| 23976 | +/* Au1100, 1500, 1550 and 1200 have the secondary GPIO block */ |
| 23977 | +#define AU1XX0_GPIO_MINOR_MAX (48) |
| 23978 | + |
| 23979 | +#define AU1X00_GPIO_NAME "gpio" |
| 23980 | + |
| 23981 | +/* GPIO pins which are not multiplexed */ |
| 23982 | +#if defined(CONFIG_SOC_AU1000) |
| 23983 | + #define NATIVE_GPIOPIN ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 1) | (1 << 0)) |
| 23984 | + #define NATIVE_GPIO2PIN (0) |
| 23985 | +#elif defined(CONFIG_SOC_AU1100) |
| 23986 | + #define NATIVE_GPIOPIN ((1 << 23) | (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) | (1 << 18) | \ |
| 23987 | + (1 << 17) | (1 << 16) | (1 << 7) | (1 << 1) | (1 << 0)) |
| 23988 | + #define NATIVE_GPIO2PIN (0) |
| 23989 | +#elif defined(CONFIG_SOC_AU1500) |
| 23990 | + #define NATIVE_GPIOPIN ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 1) | (1 << 0)) |
| 23991 | + /* exclude the PCI reset output signal: GPIO[200], DMA_REQ2 and DMA_REQ3 */ |
| 23992 | + #define NATIVE_GPIO2PIN (0xfffe & ~((1 << 9) | (1 << 8))) |
| 23993 | +#elif defined(CONFIG_SOC_AU1550) |
| 23994 | + #define NATIVE_GPIOPIN ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 6) | (1 << 1) | (1 << 0)) |
| 23995 | + /* please refere Au1550 Data Book, chapter 15 */ |
| 23996 | + #define NATIVE_GPIO2PIN (1 << 5) |
| 23997 | +#elif defined(CONFIG_SOC_AU1200) |
| 23998 | + #define NATIVE_GPIOPIN ((1 << 7) | (1 << 5)) |
| 23999 | + #define NATIVE_GPIO2PIN (0) |
| 24000 | +#endif |
| 24001 | + |
| 24002 | +/* minor as u32 */ |
| 24003 | +#define MINOR_TO_GPIOPIN(minor) ((minor < AU1X00_MAX_PRIMARY_GPIO) ? minor : (minor - AU1X00_MAX_PRIMARY_GPIO)) |
| 24004 | +#define IS_PRIMARY_GPIOPIN(minor) ((minor < AU1X00_MAX_PRIMARY_GPIO) ? 1 : 0) |
| 24005 | + |
| 24006 | +/* |
| 24007 | + * pin to minor mapping. |
| 24008 | + * GPIO0-GPIO31, minor=0-31. |
| 24009 | + * GPIO200-GPIO215, minor=32-47. |
| 24010 | + */ |
| 24011 | +typedef struct _au1x00_gpio_bit_ctl { |
| 24012 | + int direction; // The direction of this GPIO pin. 0: IN, 1: OUT. |
| 24013 | + int data; // Pin output when itized (0/1), or at the term. 0/1/-1 (tristate). |
| 24014 | +} au1x00_gpio_bit_ctl; |
| 24015 | + |
| 24016 | +typedef struct _au1x00_gpio_driver { |
| 24017 | + const char *driver_name; |
| 24018 | + const char *name; |
| 24019 | + int name_base; /* offset of printed name */ |
| 24020 | + short major; /* major device number */ |
| 24021 | + short minor_start; /* start of minor device number*/ |
| 24022 | + short num; /* number of devices */ |
| 24023 | +} au1x00_gpio_driver; |
| 24024 | + |
| 24025 | #ifdef __KERNEL__ |
| 24026 | -extern u32 get_au1000_avail_gpio_mask(void); |
| 24027 | -extern int au1000gpio_tristate(u32 data); |
| 24028 | -extern int au1000gpio_in(u32 *data); |
| 24029 | -extern int au1000gpio_set(u32 data); |
| 24030 | -extern int au1000gpio_clear(u32 data); |
| 24031 | -extern int au1000gpio_out(u32 data); |
| 24032 | +extern u32 get_au1000_avail_gpio_mask(u32 *avail_gpio2); |
| 24033 | +extern int au1000gpio_tristate(u32 minor, u32 data); |
| 24034 | +extern int au1000gpio_in(u32 minor, u32 *data); |
| 24035 | +extern int au1000gpio_set(u32 minor, u32 data); |
| 24036 | +extern int au1000gpio_clear(u32 minor, u32 data); |
| 24037 | +extern int au1000gpio_out(u32 minor, u32 data); |
| 24038 | +extern int au1000gpio_bit_read(u32 minor, u32 *read_data); |
| 24039 | +extern int au1000gpio_bit_set(u32 minor); |
| 24040 | +extern int au1000gpio_bit_clear(u32 minor); |
| 24041 | +extern int au1000gpio_bit_tristate(u32 minor); |
| 24042 | +extern int check_minor_to_gpio(u32 minor); |
| 24043 | +extern int au1000gpio_bit_init(u32 minor, au1x00_gpio_bit_ctl *bit_opt); |
| 24044 | +extern int au1000gpio_bit_term(u32 minor, au1x00_gpio_bit_ctl *bit_opt); |
| 24045 | + |
| 24046 | +extern void gpio_register_devfs (au1x00_gpio_driver *driver, unsigned int flags, unsigned minor); |
| 24047 | +extern void gpio_unregister_devfs (au1x00_gpio_driver *driver, unsigned minor); |
| 24048 | +extern int gpio_register_driver(au1x00_gpio_driver *driver); |
| 24049 | +extern int gpio_unregister_driver(au1x00_gpio_driver *driver); |
| 24050 | #endif |
| 24051 | |
| 24052 | #endif |
| 24053 | --- a/include/asm-mips/au1000.h |
| 24054 | +++ b/include/asm-mips/au1000.h |
| 24055 | @@ -160,28 +160,356 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24056 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) |
| 24057 | #endif |
| 24058 | |
| 24059 | -/* SDRAM Controller */ |
| 24060 | +/* |
| 24061 | + * SDRAM Register Offsets |
| 24062 | + */ |
| 24063 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) |
| 24064 | -#define MEM_SDMODE0 0xB4000000 |
| 24065 | -#define MEM_SDMODE1 0xB4000004 |
| 24066 | -#define MEM_SDMODE2 0xB4000008 |
| 24067 | - |
| 24068 | -#define MEM_SDADDR0 0xB400000C |
| 24069 | -#define MEM_SDADDR1 0xB4000010 |
| 24070 | -#define MEM_SDADDR2 0xB4000014 |
| 24071 | - |
| 24072 | -#define MEM_SDREFCFG 0xB4000018 |
| 24073 | -#define MEM_SDPRECMD 0xB400001C |
| 24074 | -#define MEM_SDAUTOREF 0xB4000020 |
| 24075 | - |
| 24076 | -#define MEM_SDWRMD0 0xB4000024 |
| 24077 | -#define MEM_SDWRMD1 0xB4000028 |
| 24078 | -#define MEM_SDWRMD2 0xB400002C |
| 24079 | +#define MEM_SDMODE0 (0x0000) |
| 24080 | +#define MEM_SDMODE1 (0x0004) |
| 24081 | +#define MEM_SDMODE2 (0x0008) |
| 24082 | +#define MEM_SDADDR0 (0x000C) |
| 24083 | +#define MEM_SDADDR1 (0x0010) |
| 24084 | +#define MEM_SDADDR2 (0x0014) |
| 24085 | +#define MEM_SDREFCFG (0x0018) |
| 24086 | +#define MEM_SDPRECMD (0x001C) |
| 24087 | +#define MEM_SDAUTOREF (0x0020) |
| 24088 | +#define MEM_SDWRMD0 (0x0024) |
| 24089 | +#define MEM_SDWRMD1 (0x0028) |
| 24090 | +#define MEM_SDWRMD2 (0x002C) |
| 24091 | +#define MEM_SDSLEEP (0x0030) |
| 24092 | +#define MEM_SDSMCKE (0x0034) |
| 24093 | + |
| 24094 | +#ifndef ASSEMBLER |
| 24095 | +/*typedef volatile struct |
| 24096 | +{ |
| 24097 | + uint32 sdmode0; |
| 24098 | + uint32 sdmode1; |
| 24099 | + uint32 sdmode2; |
| 24100 | + uint32 sdaddr0; |
| 24101 | + uint32 sdaddr1; |
| 24102 | + uint32 sdaddr2; |
| 24103 | + uint32 sdrefcfg; |
| 24104 | + uint32 sdautoref; |
| 24105 | + uint32 sdwrmd0; |
| 24106 | + uint32 sdwrmd1; |
| 24107 | + uint32 sdwrmd2; |
| 24108 | + uint32 sdsleep; |
| 24109 | + uint32 sdsmcke; |
| 24110 | + |
| 24111 | +} AU1X00_SDRAM;*/ |
| 24112 | +#endif |
| 24113 | + |
| 24114 | +/* |
| 24115 | + * MEM_SDMODE register content definitions |
| 24116 | + */ |
| 24117 | +#define MEM_SDMODE_F (1<<22) |
| 24118 | +#define MEM_SDMODE_SR (1<<21) |
| 24119 | +#define MEM_SDMODE_BS (1<<20) |
| 24120 | +#define MEM_SDMODE_RS (3<<18) |
| 24121 | +#define MEM_SDMODE_CS (7<<15) |
| 24122 | +#define MEM_SDMODE_TRAS (15<<11) |
| 24123 | +#define MEM_SDMODE_TMRD (3<<9) |
| 24124 | +#define MEM_SDMODE_TWR (3<<7) |
| 24125 | +#define MEM_SDMODE_TRP (3<<5) |
| 24126 | +#define MEM_SDMODE_TRCD (3<<3) |
| 24127 | +#define MEM_SDMODE_TCL (7<<0) |
| 24128 | + |
| 24129 | +#define MEM_SDMODE_BS_2Bank (0<<20) |
| 24130 | +#define MEM_SDMODE_BS_4Bank (1<<20) |
| 24131 | +#define MEM_SDMODE_RS_11Row (0<<18) |
| 24132 | +#define MEM_SDMODE_RS_12Row (1<<18) |
| 24133 | +#define MEM_SDMODE_RS_13Row (2<<18) |
| 24134 | +#define MEM_SDMODE_RS_N(N) ((N)<<18) |
| 24135 | +#define MEM_SDMODE_CS_7Col (0<<15) |
| 24136 | +#define MEM_SDMODE_CS_8Col (1<<15) |
| 24137 | +#define MEM_SDMODE_CS_9Col (2<<15) |
| 24138 | +#define MEM_SDMODE_CS_10Col (3<<15) |
| 24139 | +#define MEM_SDMODE_CS_11Col (4<<15) |
| 24140 | +#define MEM_SDMODE_CS_N(N) ((N)<<15) |
| 24141 | +#define MEM_SDMODE_TRAS_N(N) ((N)<<11) |
| 24142 | +#define MEM_SDMODE_TMRD_N(N) ((N)<<9) |
| 24143 | +#define MEM_SDMODE_TWR_N(N) ((N)<<7) |
| 24144 | +#define MEM_SDMODE_TRP_N(N) ((N)<<5) |
| 24145 | +#define MEM_SDMODE_TRCD_N(N) ((N)<<3) |
| 24146 | +#define MEM_SDMODE_TCL_N(N) ((N)<<0) |
| 24147 | + |
| 24148 | +/* |
| 24149 | + * MEM_SDADDR register contents definitions |
| 24150 | + */ |
| 24151 | +#define MEM_SDADDR_E (1<<20) |
| 24152 | +#define MEM_SDADDR_CSBA (0x03FF<<10) |
| 24153 | +#define MEM_SDADDR_CSMASK (0x03FF<<0) |
| 24154 | +#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) |
| 24155 | +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) |
| 24156 | + |
| 24157 | +/* |
| 24158 | + * MEM_SDREFCFG register content definitions |
| 24159 | + */ |
| 24160 | +#define MEM_SDREFCFG_TRC (15<<28) |
| 24161 | +#define MEM_SDREFCFG_TRPM (3<<26) |
| 24162 | +#define MEM_SDREFCFG_E (1<<25) |
| 24163 | +#define MEM_SDREFCFG_RE (0x1ffffff<<0) |
| 24164 | +#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) |
| 24165 | +#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) |
| 24166 | +#define MEM_SDREFCFG_REF_N(N) (N) |
| 24167 | +#endif |
| 24168 | + |
| 24169 | +/***********************************************************************/ |
| 24170 | + |
| 24171 | +/* |
| 24172 | + * Au1550 SDRAM Register Offsets |
| 24173 | + */ |
| 24174 | + |
| 24175 | +/***********************************************************************/ |
| 24176 | + |
| 24177 | +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
| 24178 | +#define MEM_SDMODE0 (0x0800) |
| 24179 | +#define MEM_SDMODE1 (0x0808) |
| 24180 | +#define MEM_SDMODE2 (0x0810) |
| 24181 | +#define MEM_SDADDR0 (0x0820) |
| 24182 | +#define MEM_SDADDR1 (0x0828) |
| 24183 | +#define MEM_SDADDR2 (0x0830) |
| 24184 | +#define MEM_SDCONFIGA (0x0840) |
| 24185 | +#define MEM_SDCONFIGB (0x0848) |
| 24186 | +#define MEM_SDSTAT (0x0850) |
| 24187 | +#define MEM_SDERRADDR (0x0858) |
| 24188 | +#define MEM_SDSTRIDE0 (0x0860) |
| 24189 | +#define MEM_SDSTRIDE1 (0x0868) |
| 24190 | +#define MEM_SDSTRIDE2 (0x0870) |
| 24191 | +#define MEM_SDWRMD0 (0x0880) |
| 24192 | +#define MEM_SDWRMD1 (0x0888) |
| 24193 | +#define MEM_SDWRMD2 (0x0890) |
| 24194 | +#define MEM_SDPRECMD (0x08C0) |
| 24195 | +#define MEM_SDAUTOREF (0x08C8) |
| 24196 | +#define MEM_SDSREF (0x08D0) |
| 24197 | +#define MEM_SDSLEEP MEM_SDSREF |
| 24198 | + |
| 24199 | +#ifndef ASSEMBLER |
| 24200 | +/*typedef volatile struct |
| 24201 | +{ |
| 24202 | + uint32 sdmode0; |
| 24203 | + uint32 reserved0; |
| 24204 | + uint32 sdmode1; |
| 24205 | + uint32 reserved1; |
| 24206 | + uint32 sdmode2; |
| 24207 | + uint32 reserved2[3]; |
| 24208 | + uint32 sdaddr0; |
| 24209 | + uint32 reserved3; |
| 24210 | + uint32 sdaddr1; |
| 24211 | + uint32 reserved4; |
| 24212 | + uint32 sdaddr2; |
| 24213 | + uint32 reserved5[3]; |
| 24214 | + uint32 sdconfiga; |
| 24215 | + uint32 reserved6; |
| 24216 | + uint32 sdconfigb; |
| 24217 | + uint32 reserved7; |
| 24218 | + uint32 sdstat; |
| 24219 | + uint32 reserved8; |
| 24220 | + uint32 sderraddr; |
| 24221 | + uint32 reserved9; |
| 24222 | + uint32 sdstride0; |
| 24223 | + uint32 reserved10; |
| 24224 | + uint32 sdstride1; |
| 24225 | + uint32 reserved11; |
| 24226 | + uint32 sdstride2; |
| 24227 | + uint32 reserved12[3]; |
| 24228 | + uint32 sdwrmd0; |
| 24229 | + uint32 reserved13; |
| 24230 | + uint32 sdwrmd1; |
| 24231 | + uint32 reserved14; |
| 24232 | + uint32 sdwrmd2; |
| 24233 | + uint32 reserved15[11]; |
| 24234 | + uint32 sdprecmd; |
| 24235 | + uint32 reserved16; |
| 24236 | + uint32 sdautoref; |
| 24237 | + uint32 reserved17; |
| 24238 | + uint32 sdsref; |
| 24239 | + |
| 24240 | +} AU1550_SDRAM;*/ |
| 24241 | +#endif |
| 24242 | +#endif |
| 24243 | + |
| 24244 | +/* |
| 24245 | + * Physical base addresses for integrated peripherals |
| 24246 | + */ |
| 24247 | + |
| 24248 | +#ifdef CONFIG_SOC_AU1000 |
| 24249 | +#define MEM_PHYS_ADDR 0x14000000 |
| 24250 | +#define STATIC_MEM_PHYS_ADDR 0x14001000 |
| 24251 | +#define DMA0_PHYS_ADDR 0x14002000 |
| 24252 | +#define DMA1_PHYS_ADDR 0x14002100 |
| 24253 | +#define DMA2_PHYS_ADDR 0x14002200 |
| 24254 | +#define DMA3_PHYS_ADDR 0x14002300 |
| 24255 | +#define DMA4_PHYS_ADDR 0x14002400 |
| 24256 | +#define DMA5_PHYS_ADDR 0x14002500 |
| 24257 | +#define DMA6_PHYS_ADDR 0x14002600 |
| 24258 | +#define DMA7_PHYS_ADDR 0x14002700 |
| 24259 | +#define IC0_PHYS_ADDR 0x10400000 |
| 24260 | +#define IC1_PHYS_ADDR 0x11800000 |
| 24261 | +#define AC97_PHYS_ADDR 0x10000000 |
| 24262 | +#define USBH_PHYS_ADDR 0x10100000 |
| 24263 | +#define USBD_PHYS_ADDR 0x10200000 |
| 24264 | +#define IRDA_PHYS_ADDR 0x10300000 |
| 24265 | +#define MAC0_PHYS_ADDR 0x10500000 |
| 24266 | +#define MAC1_PHYS_ADDR 0x10510000 |
| 24267 | +#define MACEN_PHYS_ADDR 0x10520000 |
| 24268 | +#define MACDMA0_PHYS_ADDR 0x14004000 |
| 24269 | +#define MACDMA1_PHYS_ADDR 0x14004200 |
| 24270 | +#define I2S_PHYS_ADDR 0x11000000 |
| 24271 | +#define UART0_PHYS_ADDR 0x11100000 |
| 24272 | +#define UART1_PHYS_ADDR 0x11200000 |
| 24273 | +#define UART2_PHYS_ADDR 0x11300000 |
| 24274 | +#define UART3_PHYS_ADDR 0x11400000 |
| 24275 | +#define SSI0_PHYS_ADDR 0x11600000 |
| 24276 | +#define SSI1_PHYS_ADDR 0x11680000 |
| 24277 | +#define SYS_PHYS_ADDR 0x11900000 |
| 24278 | +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 |
| 24279 | +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 |
| 24280 | +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 |
| 24281 | +#endif |
| 24282 | + |
| 24283 | +/********************************************************************/ |
| 24284 | |
| 24285 | -#define MEM_SDSLEEP 0xB4000030 |
| 24286 | -#define MEM_SDSMCKE 0xB4000034 |
| 24287 | +#ifdef CONFIG_SOC_AU1500 |
| 24288 | +#define MEM_PHYS_ADDR 0x14000000 |
| 24289 | +#define STATIC_MEM_PHYS_ADDR 0x14001000 |
| 24290 | +#define DMA0_PHYS_ADDR 0x14002000 |
| 24291 | +#define DMA1_PHYS_ADDR 0x14002100 |
| 24292 | +#define DMA2_PHYS_ADDR 0x14002200 |
| 24293 | +#define DMA3_PHYS_ADDR 0x14002300 |
| 24294 | +#define DMA4_PHYS_ADDR 0x14002400 |
| 24295 | +#define DMA5_PHYS_ADDR 0x14002500 |
| 24296 | +#define DMA6_PHYS_ADDR 0x14002600 |
| 24297 | +#define DMA7_PHYS_ADDR 0x14002700 |
| 24298 | +#define IC0_PHYS_ADDR 0x10400000 |
| 24299 | +#define IC1_PHYS_ADDR 0x11800000 |
| 24300 | +#define AC97_PHYS_ADDR 0x10000000 |
| 24301 | +#define USBH_PHYS_ADDR 0x10100000 |
| 24302 | +#define USBD_PHYS_ADDR 0x10200000 |
| 24303 | +#define PCI_PHYS_ADDR 0x14005000 |
| 24304 | +#define MAC0_PHYS_ADDR 0x11500000 |
| 24305 | +#define MAC1_PHYS_ADDR 0x11510000 |
| 24306 | +#define MACEN_PHYS_ADDR 0x11520000 |
| 24307 | +#define MACDMA0_PHYS_ADDR 0x14004000 |
| 24308 | +#define MACDMA1_PHYS_ADDR 0x14004200 |
| 24309 | +#define I2S_PHYS_ADDR 0x11000000 |
| 24310 | +#define UART0_PHYS_ADDR 0x11100000 |
| 24311 | +#define UART3_PHYS_ADDR 0x11400000 |
| 24312 | +#define GPIO2_PHYS_ADDR 0x11700000 |
| 24313 | +#define SYS_PHYS_ADDR 0x11900000 |
| 24314 | +#define PCI_MEM_PHYS_ADDR 0x400000000 |
| 24315 | +#define PCI_IO_PHYS_ADDR 0x500000000 |
| 24316 | +#define PCI_CONFIG0_PHYS_ADDR 0x600000000 |
| 24317 | +#define PCI_CONFIG1_PHYS_ADDR 0x680000000 |
| 24318 | +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 |
| 24319 | +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 |
| 24320 | +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 |
| 24321 | #endif |
| 24322 | |
| 24323 | +/********************************************************************/ |
| 24324 | + |
| 24325 | +#ifdef CONFIG_SOC_AU1100 |
| 24326 | +#define MEM_PHYS_ADDR 0x14000000 |
| 24327 | +#define STATIC_MEM_PHYS_ADDR 0x14001000 |
| 24328 | +#define DMA0_PHYS_ADDR 0x14002000 |
| 24329 | +#define DMA1_PHYS_ADDR 0x14002100 |
| 24330 | +#define DMA2_PHYS_ADDR 0x14002200 |
| 24331 | +#define DMA3_PHYS_ADDR 0x14002300 |
| 24332 | +#define DMA4_PHYS_ADDR 0x14002400 |
| 24333 | +#define DMA5_PHYS_ADDR 0x14002500 |
| 24334 | +#define DMA6_PHYS_ADDR 0x14002600 |
| 24335 | +#define DMA7_PHYS_ADDR 0x14002700 |
| 24336 | +#define IC0_PHYS_ADDR 0x10400000 |
| 24337 | +#define SD0_PHYS_ADDR 0x10600000 |
| 24338 | +#define SD1_PHYS_ADDR 0x10680000 |
| 24339 | +#define IC1_PHYS_ADDR 0x11800000 |
| 24340 | +#define AC97_PHYS_ADDR 0x10000000 |
| 24341 | +#define USBH_PHYS_ADDR 0x10100000 |
| 24342 | +#define USBD_PHYS_ADDR 0x10200000 |
| 24343 | +#define IRDA_PHYS_ADDR 0x10300000 |
| 24344 | +#define MAC0_PHYS_ADDR 0x10500000 |
| 24345 | +#define MACEN_PHYS_ADDR 0x10520000 |
| 24346 | +#define MACDMA0_PHYS_ADDR 0x14004000 |
| 24347 | +#define MACDMA1_PHYS_ADDR 0x14004200 |
| 24348 | +#define I2S_PHYS_ADDR 0x11000000 |
| 24349 | +#define UART0_PHYS_ADDR 0x11100000 |
| 24350 | +#define UART1_PHYS_ADDR 0x11200000 |
| 24351 | +#define UART3_PHYS_ADDR 0x11400000 |
| 24352 | +#define SSI0_PHYS_ADDR 0x11600000 |
| 24353 | +#define SSI1_PHYS_ADDR 0x11680000 |
| 24354 | +#define GPIO2_PHYS_ADDR 0x11700000 |
| 24355 | +#define SYS_PHYS_ADDR 0x11900000 |
| 24356 | +#define LCD_PHYS_ADDR 0x15000000 |
| 24357 | +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 |
| 24358 | +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 |
| 24359 | +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 |
| 24360 | +#endif |
| 24361 | + |
| 24362 | +/***********************************************************************/ |
| 24363 | + |
| 24364 | +#ifdef CONFIG_SOC_AU1550 |
| 24365 | +#define MEM_PHYS_ADDR 0x14000000 |
| 24366 | +#define STATIC_MEM_PHYS_ADDR 0x14001000 |
| 24367 | +#define IC0_PHYS_ADDR 0x10400000 |
| 24368 | +#define IC1_PHYS_ADDR 0x11800000 |
| 24369 | +#define USBH_PHYS_ADDR 0x14020000 |
| 24370 | +#define USBD_PHYS_ADDR 0x10200000 |
| 24371 | +#define PCI_PHYS_ADDR 0x14005000 |
| 24372 | +#define MAC0_PHYS_ADDR 0x10500000 |
| 24373 | +#define MAC1_PHYS_ADDR 0x10510000 |
| 24374 | +#define MACEN_PHYS_ADDR 0x10520000 |
| 24375 | +#define MACDMA0_PHYS_ADDR 0x14004000 |
| 24376 | +#define MACDMA1_PHYS_ADDR 0x14004200 |
| 24377 | +#define UART0_PHYS_ADDR 0x11100000 |
| 24378 | +#define UART1_PHYS_ADDR 0x11200000 |
| 24379 | +#define UART3_PHYS_ADDR 0x11400000 |
| 24380 | +#define GPIO2_PHYS_ADDR 0x11700000 |
| 24381 | +#define SYS_PHYS_ADDR 0x11900000 |
| 24382 | +#define DDMA_PHYS_ADDR 0x14002000 |
| 24383 | +#define PE_PHYS_ADDR 0x14008000 |
| 24384 | +#define PSC0_PHYS_ADDR 0x11A00000 |
| 24385 | +#define PSC1_PHYS_ADDR 0x11B00000 |
| 24386 | +#define PSC2_PHYS_ADDR 0x10A00000 |
| 24387 | +#define PSC3_PHYS_ADDR 0x10B00000 |
| 24388 | +#define PCI_MEM_PHYS_ADDR 0x400000000 |
| 24389 | +#define PCI_IO_PHYS_ADDR 0x500000000 |
| 24390 | +#define PCI_CONFIG0_PHYS_ADDR 0x600000000 |
| 24391 | +#define PCI_CONFIG1_PHYS_ADDR 0x680000000 |
| 24392 | +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 |
| 24393 | +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 |
| 24394 | +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 |
| 24395 | +#endif |
| 24396 | + |
| 24397 | +/***********************************************************************/ |
| 24398 | + |
| 24399 | +#ifdef CONFIG_SOC_AU1200 |
| 24400 | +#define MEM_PHYS_ADDR 0x14000000 |
| 24401 | +#define STATIC_MEM_PHYS_ADDR 0x14001000 |
| 24402 | +#define AES_PHYS_ADDR 0x10300000 |
| 24403 | +#define CIM_PHYS_ADDR 0x14004000 |
| 24404 | +#define IC0_PHYS_ADDR 0x10400000 |
| 24405 | +#define IC1_PHYS_ADDR 0x11800000 |
| 24406 | +#define USBM_PHYS_ADDR 0x14020000 |
| 24407 | +#define USBH_PHYS_ADDR 0x14020100 |
| 24408 | +#define UART0_PHYS_ADDR 0x11100000 |
| 24409 | +#define UART1_PHYS_ADDR 0x11200000 |
| 24410 | +#define GPIO2_PHYS_ADDR 0x11700000 |
| 24411 | +#define SYS_PHYS_ADDR 0x11900000 |
| 24412 | +#define DDMA_PHYS_ADDR 0x14002000 |
| 24413 | +#define PSC0_PHYS_ADDR 0x11A00000 |
| 24414 | +#define PSC1_PHYS_ADDR 0x11B00000 |
| 24415 | +#define PCMCIA_IO_PHYS_ADDR 0xF00000000 |
| 24416 | +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 |
| 24417 | +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 |
| 24418 | +#define SD0_PHYS_ADDR 0x10600000 |
| 24419 | +#define SD1_PHYS_ADDR 0x10680000 |
| 24420 | +#define LCD_PHYS_ADDR 0x15000000 |
| 24421 | +#define SWCNT_PHYS_ADDR 0x1110010C |
| 24422 | +#define MAEFE_PHYS_ADDR 0x14012000 |
| 24423 | +#define MAEBE_PHYS_ADDR 0x14010000 |
| 24424 | +#endif |
| 24425 | + |
| 24426 | + |
| 24427 | /* Static Bus Controller */ |
| 24428 | #define MEM_STCFG0 0xB4001000 |
| 24429 | #define MEM_STTIME0 0xB4001004 |
| 24430 | @@ -367,7 +695,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24431 | #define AU1000_MAC0_ENABLE 0xB0520000 |
| 24432 | #define AU1000_MAC1_ENABLE 0xB0520004 |
| 24433 | #define NUM_ETH_INTERFACES 2 |
| 24434 | -#endif // CONFIG_SOC_AU1000 |
| 24435 | +#endif /* CONFIG_SOC_AU1000 */ |
| 24436 | |
| 24437 | /* Au1500 */ |
| 24438 | #ifdef CONFIG_SOC_AU1500 |
| 24439 | @@ -438,7 +766,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24440 | #define AU1500_MAC0_ENABLE 0xB1520000 |
| 24441 | #define AU1500_MAC1_ENABLE 0xB1520004 |
| 24442 | #define NUM_ETH_INTERFACES 2 |
| 24443 | -#endif // CONFIG_SOC_AU1500 |
| 24444 | +#endif /* CONFIG_SOC_AU1500 */ |
| 24445 | |
| 24446 | /* Au1100 */ |
| 24447 | #ifdef CONFIG_SOC_AU1100 |
| 24448 | @@ -483,6 +811,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24449 | #define AU1000_GPIO_13 45 |
| 24450 | #define AU1000_GPIO_14 46 |
| 24451 | #define AU1000_GPIO_15 47 |
| 24452 | +#define AU1000_GPIO_16 48 |
| 24453 | +#define AU1000_GPIO_17 49 |
| 24454 | +#define AU1000_GPIO_18 50 |
| 24455 | +#define AU1000_GPIO_19 51 |
| 24456 | +#define AU1000_GPIO_20 52 |
| 24457 | +#define AU1000_GPIO_21 53 |
| 24458 | +#define AU1000_GPIO_22 54 |
| 24459 | +#define AU1000_GPIO_23 55 |
| 24460 | +#define AU1000_GPIO_24 56 |
| 24461 | +#define AU1000_GPIO_25 57 |
| 24462 | +#define AU1000_GPIO_26 58 |
| 24463 | +#define AU1000_GPIO_27 59 |
| 24464 | +#define AU1000_GPIO_28 60 |
| 24465 | +#define AU1000_GPIO_29 61 |
| 24466 | +#define AU1000_GPIO_30 62 |
| 24467 | +#define AU1000_GPIO_31 63 |
| 24468 | |
| 24469 | #define UART0_ADDR 0xB1100000 |
| 24470 | #define UART1_ADDR 0xB1200000 |
| 24471 | @@ -494,7 +838,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24472 | #define AU1100_ETH0_BASE 0xB0500000 |
| 24473 | #define AU1100_MAC0_ENABLE 0xB0520000 |
| 24474 | #define NUM_ETH_INTERFACES 1 |
| 24475 | -#endif // CONFIG_SOC_AU1100 |
| 24476 | +#endif /* CONFIG_SOC_AU1100 */ |
| 24477 | |
| 24478 | #ifdef CONFIG_SOC_AU1550 |
| 24479 | #define AU1550_UART0_INT 0 |
| 24480 | @@ -511,14 +855,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24481 | #define AU1550_PSC1_INT 11 |
| 24482 | #define AU1550_PSC2_INT 12 |
| 24483 | #define AU1550_PSC3_INT 13 |
| 24484 | -#define AU1550_TOY_INT 14 |
| 24485 | -#define AU1550_TOY_MATCH0_INT 15 |
| 24486 | -#define AU1550_TOY_MATCH1_INT 16 |
| 24487 | -#define AU1550_TOY_MATCH2_INT 17 |
| 24488 | -#define AU1550_RTC_INT 18 |
| 24489 | -#define AU1550_RTC_MATCH0_INT 19 |
| 24490 | -#define AU1550_RTC_MATCH1_INT 20 |
| 24491 | -#define AU1550_RTC_MATCH2_INT 21 |
| 24492 | +#define AU1000_TOY_INT 14 |
| 24493 | +#define AU1000_TOY_MATCH0_INT 15 |
| 24494 | +#define AU1000_TOY_MATCH1_INT 16 |
| 24495 | +#define AU1000_TOY_MATCH2_INT 17 |
| 24496 | +#define AU1000_RTC_INT 18 |
| 24497 | +#define AU1000_RTC_MATCH0_INT 19 |
| 24498 | +#define AU1000_RTC_MATCH1_INT 20 |
| 24499 | +#define AU1000_RTC_MATCH2_INT 21 |
| 24500 | #define AU1550_NAND_INT 23 |
| 24501 | #define AU1550_USB_DEV_REQ_INT 24 |
| 24502 | #define AU1550_USB_DEV_SUS_INT 25 |
| 24503 | @@ -573,7 +917,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24504 | #define AU1550_MAC0_ENABLE 0xB0520000 |
| 24505 | #define AU1550_MAC1_ENABLE 0xB0520004 |
| 24506 | #define NUM_ETH_INTERFACES 2 |
| 24507 | -#endif // CONFIG_SOC_AU1550 |
| 24508 | +#endif /* CONFIG_SOC_AU1550 */ |
| 24509 | |
| 24510 | #ifdef CONFIG_SOC_AU1200 |
| 24511 | #define AU1200_UART0_INT 0 |
| 24512 | @@ -590,14 +934,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24513 | #define AU1200_PSC1_INT 11 |
| 24514 | #define AU1200_AES_INT 12 |
| 24515 | #define AU1200_CAMERA_INT 13 |
| 24516 | -#define AU1200_TOY_INT 14 |
| 24517 | -#define AU1200_TOY_MATCH0_INT 15 |
| 24518 | -#define AU1200_TOY_MATCH1_INT 16 |
| 24519 | -#define AU1200_TOY_MATCH2_INT 17 |
| 24520 | -#define AU1200_RTC_INT 18 |
| 24521 | -#define AU1200_RTC_MATCH0_INT 19 |
| 24522 | -#define AU1200_RTC_MATCH1_INT 20 |
| 24523 | -#define AU1200_RTC_MATCH2_INT 21 |
| 24524 | +#define AU1000_TOY_INT 14 |
| 24525 | +#define AU1000_TOY_MATCH0_INT 15 |
| 24526 | +#define AU1000_TOY_MATCH1_INT 16 |
| 24527 | +#define AU1000_TOY_MATCH2_INT 17 |
| 24528 | +#define AU1000_RTC_INT 18 |
| 24529 | +#define AU1000_RTC_MATCH0_INT 19 |
| 24530 | +#define AU1000_RTC_MATCH1_INT 20 |
| 24531 | +#define AU1000_RTC_MATCH2_INT 21 |
| 24532 | #define AU1200_NAND_INT 23 |
| 24533 | #define AU1200_GPIO_204 24 |
| 24534 | #define AU1200_GPIO_205 25 |
| 24535 | @@ -605,6 +949,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24536 | #define AU1200_GPIO_207 27 |
| 24537 | #define AU1200_GPIO_208_215 28 // Logical OR of 208:215 |
| 24538 | #define AU1200_USB_INT 29 |
| 24539 | +#define AU1000_USB_HOST_INT AU1200_USB_INT |
| 24540 | #define AU1200_LCD_INT 30 |
| 24541 | #define AU1200_MAE_BOTH_INT 31 |
| 24542 | #define AU1000_GPIO_0 32 |
| 24543 | @@ -643,21 +988,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24544 | #define UART0_ADDR 0xB1100000 |
| 24545 | #define UART1_ADDR 0xB1200000 |
| 24546 | |
| 24547 | -#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap |
| 24548 | -#define USB_HOST_CONFIG 0xB4027ffc |
| 24549 | +#define USB_UOC_BASE 0x14020020 |
| 24550 | +#define USB_UOC_LEN 0x20 |
| 24551 | +#define USB_OHCI_BASE 0x14020100 |
| 24552 | +#define USB_OHCI_LEN 0x100 |
| 24553 | +#define USB_EHCI_BASE 0x14020200 |
| 24554 | +#define USB_EHCI_LEN 0x100 |
| 24555 | +#define USB_UDC_BASE 0x14022000 |
| 24556 | +#define USB_UDC_LEN 0x2000 |
| 24557 | +#define USB_MSR_BASE 0xB4020000 |
| 24558 | +#define USB_MSR_MCFG 4 |
| 24559 | +#define USBMSRMCFG_OMEMEN 0 |
| 24560 | +#define USBMSRMCFG_OBMEN 1 |
| 24561 | +#define USBMSRMCFG_EMEMEN 2 |
| 24562 | +#define USBMSRMCFG_EBMEN 3 |
| 24563 | +#define USBMSRMCFG_DMEMEN 4 |
| 24564 | +#define USBMSRMCFG_DBMEN 5 |
| 24565 | +#define USBMSRMCFG_GMEMEN 6 |
| 24566 | +#define USBMSRMCFG_OHCCLKEN 16 |
| 24567 | +#define USBMSRMCFG_EHCCLKEN 17 |
| 24568 | +#define USBMSRMCFG_UDCCLKEN 18 |
| 24569 | +#define USBMSRMCFG_PHYPLLEN 19 |
| 24570 | +#define USBMSRMCFG_RDCOMB 30 |
| 24571 | +#define USBMSRMCFG_PFEN 31 |
| 24572 | |
| 24573 | -// these are here for prototyping on au1550 (do not exist on au1200) |
| 24574 | -#define AU1200_ETH0_BASE 0xB0500000 |
| 24575 | -#define AU1200_ETH1_BASE 0xB0510000 |
| 24576 | -#define AU1200_MAC0_ENABLE 0xB0520000 |
| 24577 | -#define AU1200_MAC1_ENABLE 0xB0520004 |
| 24578 | -#define NUM_ETH_INTERFACES 2 |
| 24579 | -#endif // CONFIG_SOC_AU1200 |
| 24580 | +#endif /* CONFIG_SOC_AU1200 */ |
| 24581 | |
| 24582 | #define AU1000_LAST_INTC0_INT 31 |
| 24583 | +#define AU1000_LAST_INTC1_INT 63 |
| 24584 | #define AU1000_MAX_INTR 63 |
| 24585 | |
| 24586 | - |
| 24587 | /* Programmable Counters 0 and 1 */ |
| 24588 | #define SYS_BASE 0xB1900000 |
| 24589 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) |
| 24590 | @@ -728,6 +1088,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24591 | #define I2S_CONTROL_D (1<<1) |
| 24592 | #define I2S_CONTROL_CE (1<<0) |
| 24593 | |
| 24594 | +#ifndef CONFIG_SOC_AU1200 |
| 24595 | + |
| 24596 | /* USB Host Controller */ |
| 24597 | #define USB_OHCI_LEN 0x00100000 |
| 24598 | |
| 24599 | @@ -773,6 +1135,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24600 | #define USBDEV_ENABLE (1<<1) |
| 24601 | #define USBDEV_CE (1<<0) |
| 24602 | |
| 24603 | +#endif /* !CONFIG_SOC_AU1200 */ |
| 24604 | + |
| 24605 | /* Ethernet Controllers */ |
| 24606 | |
| 24607 | /* 4 byte offsets from AU1000_ETH_BASE */ |
| 24608 | @@ -1171,6 +1535,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24609 | #define SYS_PF_PSC1_S1 (1 << 1) |
| 24610 | #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) |
| 24611 | |
| 24612 | +/* Au1200 Only */ |
| 24613 | +#ifdef CONFIG_SOC_AU1200 |
| 24614 | +#define SYS_PINFUNC_DMA (1<<31) |
| 24615 | +#define SYS_PINFUNC_S0A (1<<30) |
| 24616 | +#define SYS_PINFUNC_S1A (1<<29) |
| 24617 | +#define SYS_PINFUNC_LP0 (1<<28) |
| 24618 | +#define SYS_PINFUNC_LP1 (1<<27) |
| 24619 | +#define SYS_PINFUNC_LD16 (1<<26) |
| 24620 | +#define SYS_PINFUNC_LD8 (1<<25) |
| 24621 | +#define SYS_PINFUNC_LD1 (1<<24) |
| 24622 | +#define SYS_PINFUNC_LD0 (1<<23) |
| 24623 | +#define SYS_PINFUNC_P1A (3<<21) |
| 24624 | +#define SYS_PINFUNC_P1B (1<<20) |
| 24625 | +#define SYS_PINFUNC_FS3 (1<<19) |
| 24626 | +#define SYS_PINFUNC_P0A (3<<17) |
| 24627 | +#define SYS_PINFUNC_CS (1<<16) |
| 24628 | +#define SYS_PINFUNC_CIM (1<<15) |
| 24629 | +#define SYS_PINFUNC_P1C (1<<14) |
| 24630 | +#define SYS_PINFUNC_U1T (1<<12) |
| 24631 | +#define SYS_PINFUNC_U1R (1<<11) |
| 24632 | +#define SYS_PINFUNC_EX1 (1<<10) |
| 24633 | +#define SYS_PINFUNC_EX0 (1<<9) |
| 24634 | +#define SYS_PINFUNC_U0R (1<<8) |
| 24635 | +#define SYS_PINFUNC_MC (1<<7) |
| 24636 | +#define SYS_PINFUNC_S0B (1<<6) |
| 24637 | +#define SYS_PINFUNC_S0C (1<<5) |
| 24638 | +#define SYS_PINFUNC_P0B (1<<4) |
| 24639 | +#define SYS_PINFUNC_U0T (1<<3) |
| 24640 | +#define SYS_PINFUNC_S1B (1<<2) |
| 24641 | +#endif |
| 24642 | + |
| 24643 | #define SYS_TRIOUTRD 0xB1900100 |
| 24644 | #define SYS_TRIOUTCLR 0xB1900100 |
| 24645 | #define SYS_OUTPUTRD 0xB1900108 |
| 24646 | @@ -1298,7 +1693,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24647 | #define SD1_XMIT_FIFO 0xB0680000 |
| 24648 | #define SD1_RECV_FIFO 0xB0680004 |
| 24649 | |
| 24650 | - |
| 24651 | #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
| 24652 | /* Au1500 PCI Controller */ |
| 24653 | #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr |
| 24654 | @@ -1388,9 +1782,60 @@ extern au1xxx_irq_map_t au1xxx_irq_map[] |
| 24655 | |
| 24656 | #endif |
| 24657 | |
| 24658 | +#ifndef _LANGUAGE_ASSEMBLY |
| 24659 | +typedef volatile struct |
| 24660 | +{ |
| 24661 | + /* 0x0000 */ u32 toytrim; |
| 24662 | + /* 0x0004 */ u32 toywrite; |
| 24663 | + /* 0x0008 */ u32 toymatch0; |
| 24664 | + /* 0x000C */ u32 toymatch1; |
| 24665 | + /* 0x0010 */ u32 toymatch2; |
| 24666 | + /* 0x0014 */ u32 cntrctrl; |
| 24667 | + /* 0x0018 */ u32 scratch0; |
| 24668 | + /* 0x001C */ u32 scratch1; |
| 24669 | + /* 0x0020 */ u32 freqctrl0; |
| 24670 | + /* 0x0024 */ u32 freqctrl1; |
| 24671 | + /* 0x0028 */ u32 clksrc; |
| 24672 | + /* 0x002C */ u32 pinfunc; |
| 24673 | + /* 0x0030 */ u32 reserved0; |
| 24674 | + /* 0x0034 */ u32 wakemsk; |
| 24675 | + /* 0x0038 */ u32 endian; |
| 24676 | + /* 0x003C */ u32 powerctrl; |
| 24677 | + /* 0x0040 */ u32 toyread; |
| 24678 | + /* 0x0044 */ u32 rtctrim; |
| 24679 | + /* 0x0048 */ u32 rtcwrite; |
| 24680 | + /* 0x004C */ u32 rtcmatch0; |
| 24681 | + /* 0x0050 */ u32 rtcmatch1; |
| 24682 | + /* 0x0054 */ u32 rtcmatch2; |
| 24683 | + /* 0x0058 */ u32 rtcread; |
| 24684 | + /* 0x005C */ u32 wakesrc; |
| 24685 | + /* 0x0060 */ u32 cpupll; |
| 24686 | + /* 0x0064 */ u32 auxpll; |
| 24687 | + /* 0x0068 */ u32 reserved1; |
| 24688 | + /* 0x006C */ u32 reserved2; |
| 24689 | + /* 0x0070 */ u32 reserved3; |
| 24690 | + /* 0x0074 */ u32 reserved4; |
| 24691 | + /* 0x0078 */ u32 slppwr; |
| 24692 | + /* 0x007C */ u32 sleep; |
| 24693 | + /* 0x0080 */ u32 reserved5[32]; |
| 24694 | + /* 0x0100 */ u32 trioutrd; |
| 24695 | +#define trioutclr trioutrd |
| 24696 | + /* 0x0104 */ u32 reserved6; |
| 24697 | + /* 0x0108 */ u32 outputrd; |
| 24698 | +#define outputset outputrd |
| 24699 | + /* 0x010C */ u32 outputclr; |
| 24700 | + /* 0x0110 */ u32 pinstaterd; |
| 24701 | +#define pininputen pinstaterd |
| 24702 | + |
| 24703 | +} AU1X00_SYS; |
| 24704 | + |
| 24705 | +static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; |
| 24706 | + |
| 24707 | +#endif |
| 24708 | /* Processor information base on prid. |
| 24709 | * Copied from PowerPC. |
| 24710 | */ |
| 24711 | +#ifndef _LANGUAGE_ASSEMBLY |
| 24712 | struct cpu_spec { |
| 24713 | /* CPU is matched via (PRID & prid_mask) == prid_value */ |
| 24714 | unsigned int prid_mask; |
| 24715 | @@ -1404,3 +1849,6 @@ struct cpu_spec { |
| 24716 | extern struct cpu_spec cpu_specs[]; |
| 24717 | extern struct cpu_spec *cur_cpu_spec[]; |
| 24718 | #endif |
| 24719 | + |
| 24720 | +#endif |
| 24721 | + |
| 24722 | --- a/include/asm-mips/au1000_pcmcia.h |
| 24723 | +++ b/include/asm-mips/au1000_pcmcia.h |
| 24724 | @@ -38,16 +38,41 @@ |
| 24725 | #define AU1X_SOCK0_PHYS_MEM 0xF80000000 |
| 24726 | |
| 24727 | /* pcmcia socket 1 needs external glue logic so the memory map |
| 24728 | - * differs from board to board. |
| 24729 | + * differs from board to board. the general rule is that |
| 24730 | + * static bus address bit 26 should be used to decode socket 0 |
| 24731 | + * from socket 1. alas, some boards dont follow this... |
| 24732 | + * These really belong in a board-specific header file... |
| 24733 | */ |
| 24734 | -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) |
| 24735 | -#define AU1X_SOCK1_IO 0xF08000000 |
| 24736 | -#define AU1X_SOCK1_PHYS_ATTR 0xF48000000 |
| 24737 | -#define AU1X_SOCK1_PHYS_MEM 0xF88000000 |
| 24738 | -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) |
| 24739 | -#define AU1X_SOCK1_IO 0xF04000000 |
| 24740 | -#define AU1X_SOCK1_PHYS_ATTR 0xF44000000 |
| 24741 | -#define AU1X_SOCK1_PHYS_MEM 0xF84000000 |
| 24742 | +#ifdef CONFIG_MIPS_PB1000 |
| 24743 | +#define SOCK1_DECODE (1<<27) |
| 24744 | +#endif |
| 24745 | +#ifdef CONFIG_MIPS_DB1000 |
| 24746 | +#define SOCK1_DECODE (1<<26) |
| 24747 | +#endif |
| 24748 | +#ifdef CONFIG_MIPS_DB1500 |
| 24749 | +#define SOCK1_DECODE (1<<26) |
| 24750 | +#endif |
| 24751 | +#ifdef CONFIG_MIPS_DB1100 |
| 24752 | +#define SOCK1_DECODE (1<<26) |
| 24753 | +#endif |
| 24754 | +#ifdef CONFIG_MIPS_DB1550 |
| 24755 | +#define SOCK1_DECODE (1<<26) |
| 24756 | +#endif |
| 24757 | +#ifdef CONFIG_MIPS_DB1200 |
| 24758 | +#define SOCK1_DECODE (1<<26) |
| 24759 | +#endif |
| 24760 | +#ifdef CONFIG_MIPS_PB1550 |
| 24761 | +#define SOCK1_DECODE (1<<26) |
| 24762 | +#endif |
| 24763 | +#ifdef CONFIG_MIPS_PB1200 |
| 24764 | +#define SOCK1_DECODE (1<<26) |
| 24765 | +#endif |
| 24766 | + |
| 24767 | +/* The board has a second PCMCIA socket */ |
| 24768 | +#ifdef SOCK1_DECODE |
| 24769 | +#define AU1X_SOCK1_IO (0xF00000000|SOCK1_DECODE) |
| 24770 | +#define AU1X_SOCK1_PHYS_ATTR (0xF40000000|SOCK1_DECODE) |
| 24771 | +#define AU1X_SOCK1_PHYS_MEM (0xF80000000|SOCK1_DECODE) |
| 24772 | #endif |
| 24773 | |
| 24774 | struct pcmcia_state { |
| 24775 | --- a/include/asm-mips/au1100_mmc.h |
| 24776 | +++ b/include/asm-mips/au1100_mmc.h |
| 24777 | @@ -39,16 +39,22 @@ |
| 24778 | #define __ASM_AU1100_MMC_H |
| 24779 | |
| 24780 | |
| 24781 | -#define NUM_AU1100_MMC_CONTROLLERS 2 |
| 24782 | - |
| 24783 | - |
| 24784 | -#define AU1100_SD_IRQ 2 |
| 24785 | - |
| 24786 | +#if defined(CONFIG_SOC_AU1100) |
| 24787 | +#define NUM_MMC_CONTROLLERS 2 |
| 24788 | +#define AU1X_MMC_INT AU1100_SD_INT |
| 24789 | +#endif |
| 24790 | + |
| 24791 | +#if defined(CONFIG_SOC_AU1200) |
| 24792 | +#define NUM_MMC_CONTROLLERS 2 |
| 24793 | +#define AU1X_MMC_INT AU1200_SD_INT |
| 24794 | +#endif |
| 24795 | |
| 24796 | #define SD0_BASE 0xB0600000 |
| 24797 | #define SD1_BASE 0xB0680000 |
| 24798 | |
| 24799 | |
| 24800 | + |
| 24801 | + |
| 24802 | /* |
| 24803 | * Register offsets. |
| 24804 | */ |
| 24805 | @@ -201,5 +207,12 @@ |
| 24806 | #define SD_CMD_RT_1B (0x00810000) |
| 24807 | |
| 24808 | |
| 24809 | +/* support routines required on a platform-specific basis */ |
| 24810 | +extern void mmc_card_inserted(int _n_, int *_res_); |
| 24811 | +extern void mmc_card_writable(int _n_, int *_res_); |
| 24812 | +extern void mmc_power_on(int _n_); |
| 24813 | +extern void mmc_power_off(int _n_); |
| 24814 | + |
| 24815 | + |
| 24816 | #endif /* __ASM_AU1100_MMC_H */ |
| 24817 | |
| 24818 | --- a/include/asm-mips/au1xxx_dbdma.h |
| 24819 | +++ b/include/asm-mips/au1xxx_dbdma.h |
| 24820 | @@ -43,7 +43,7 @@ |
| 24821 | #define DDMA_GLOBAL_BASE 0xb4003000 |
| 24822 | #define DDMA_CHANNEL_BASE 0xb4002000 |
| 24823 | |
| 24824 | -typedef struct dbdma_global { |
| 24825 | +typedef volatile struct dbdma_global { |
| 24826 | u32 ddma_config; |
| 24827 | u32 ddma_intstat; |
| 24828 | u32 ddma_throttle; |
| 24829 | @@ -60,7 +60,7 @@ typedef struct dbdma_global { |
| 24830 | |
| 24831 | /* The structure of a DMA Channel. |
| 24832 | */ |
| 24833 | -typedef struct au1xxx_dma_channel { |
| 24834 | +typedef volatile struct au1xxx_dma_channel { |
| 24835 | u32 ddma_cfg; /* See below */ |
| 24836 | u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ |
| 24837 | u32 ddma_statptr; /* word aligned pointer to status word */ |
| 24838 | @@ -96,7 +96,7 @@ typedef struct au1xxx_dma_channel { |
| 24839 | /* "Standard" DDMA Descriptor. |
| 24840 | * Must be 32-byte aligned. |
| 24841 | */ |
| 24842 | -typedef struct au1xxx_ddma_desc { |
| 24843 | +typedef volatile struct au1xxx_ddma_desc { |
| 24844 | u32 dscr_cmd0; /* See below */ |
| 24845 | u32 dscr_cmd1; /* See below */ |
| 24846 | u32 dscr_source0; /* source phys address */ |
| 24847 | @@ -105,6 +105,12 @@ typedef struct au1xxx_ddma_desc { |
| 24848 | u32 dscr_dest1; /* See below */ |
| 24849 | u32 dscr_stat; /* completion status */ |
| 24850 | u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ |
| 24851 | + /* First 32bytes are HW specific!!! |
| 24852 | + Lets have some SW data following.. make sure its 32bytes |
| 24853 | + */ |
| 24854 | + u32 sw_status; |
| 24855 | + u32 sw_context; |
| 24856 | + u32 sw_reserved[6]; |
| 24857 | } au1x_ddma_desc_t; |
| 24858 | |
| 24859 | #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ |
| 24860 | @@ -123,6 +129,8 @@ typedef struct au1xxx_ddma_desc { |
| 24861 | #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ |
| 24862 | #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ |
| 24863 | |
| 24864 | +#define SW_STATUS_INUSE (1<<0) |
| 24865 | + |
| 24866 | /* Command 0 device IDs. |
| 24867 | */ |
| 24868 | #ifdef CONFIG_SOC_AU1550 |
| 24869 | @@ -169,8 +177,8 @@ typedef struct au1xxx_ddma_desc { |
| 24870 | #define DSCR_CMD0_SDMS_RX0 9 |
| 24871 | #define DSCR_CMD0_SDMS_TX1 10 |
| 24872 | #define DSCR_CMD0_SDMS_RX1 11 |
| 24873 | -#define DSCR_CMD0_AES_TX 12 |
| 24874 | -#define DSCR_CMD0_AES_RX 13 |
| 24875 | +#define DSCR_CMD0_AES_TX 13 |
| 24876 | +#define DSCR_CMD0_AES_RX 12 |
| 24877 | #define DSCR_CMD0_PSC0_TX 14 |
| 24878 | #define DSCR_CMD0_PSC0_RX 15 |
| 24879 | #define DSCR_CMD0_PSC1_TX 16 |
| 24880 | @@ -189,6 +197,10 @@ typedef struct au1xxx_ddma_desc { |
| 24881 | #define DSCR_CMD0_THROTTLE 30 |
| 24882 | #define DSCR_CMD0_ALWAYS 31 |
| 24883 | #define DSCR_NDEV_IDS 32 |
| 24884 | +/* THis macro is used to find/create custom device types */ |
| 24885 | +#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) |
| 24886 | +#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) |
| 24887 | + |
| 24888 | |
| 24889 | #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) |
| 24890 | #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) |
| 24891 | @@ -277,6 +289,43 @@ typedef struct au1xxx_ddma_desc { |
| 24892 | */ |
| 24893 | #define NUM_DBDMA_CHANS 16 |
| 24894 | |
| 24895 | +/* |
| 24896 | + * Ddma API definitions |
| 24897 | + * FIXME: may not fit to this header file |
| 24898 | + */ |
| 24899 | +typedef struct dbdma_device_table { |
| 24900 | + u32 dev_id; |
| 24901 | + u32 dev_flags; |
| 24902 | + u32 dev_tsize; |
| 24903 | + u32 dev_devwidth; |
| 24904 | + u32 dev_physaddr; /* If FIFO */ |
| 24905 | + u32 dev_intlevel; |
| 24906 | + u32 dev_intpolarity; |
| 24907 | +} dbdev_tab_t; |
| 24908 | + |
| 24909 | + |
| 24910 | +typedef struct dbdma_chan_config { |
| 24911 | + spinlock_t lock; |
| 24912 | + |
| 24913 | + u32 chan_flags; |
| 24914 | + u32 chan_index; |
| 24915 | + dbdev_tab_t *chan_src; |
| 24916 | + dbdev_tab_t *chan_dest; |
| 24917 | + au1x_dma_chan_t *chan_ptr; |
| 24918 | + au1x_ddma_desc_t *chan_desc_base; |
| 24919 | + au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; |
| 24920 | + void *chan_callparam; |
| 24921 | + void (*chan_callback)(int, void *, struct pt_regs *); |
| 24922 | +} chan_tab_t; |
| 24923 | + |
| 24924 | +#define DEV_FLAGS_INUSE (1 << 0) |
| 24925 | +#define DEV_FLAGS_ANYUSE (1 << 1) |
| 24926 | +#define DEV_FLAGS_OUT (1 << 2) |
| 24927 | +#define DEV_FLAGS_IN (1 << 3) |
| 24928 | +#define DEV_FLAGS_BURSTABLE (1 << 4) |
| 24929 | +#define DEV_FLAGS_SYNC (1 << 5) |
| 24930 | +/* end Ddma API definitions */ |
| 24931 | + |
| 24932 | /* External functions for drivers to use. |
| 24933 | */ |
| 24934 | /* Use this to allocate a dbdma channel. The device ids are one of the |
| 24935 | @@ -299,8 +348,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, |
| 24936 | |
| 24937 | /* Put buffers on source/destination descriptors. |
| 24938 | */ |
| 24939 | -u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); |
| 24940 | -u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); |
| 24941 | +u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); |
| 24942 | +u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); |
| 24943 | |
| 24944 | /* Get a buffer from the destination descriptor. |
| 24945 | */ |
| 24946 | @@ -314,5 +363,25 @@ u32 au1xxx_get_dma_residue(u32 chanid); |
| 24947 | void au1xxx_dbdma_chan_free(u32 chanid); |
| 24948 | void au1xxx_dbdma_dump(u32 chanid); |
| 24949 | |
| 24950 | +u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ); |
| 24951 | + |
| 24952 | +u32 au1xxx_ddma_add_device( dbdev_tab_t *dev ); |
| 24953 | + |
| 24954 | +/* |
| 24955 | + Some compatibilty macros -- |
| 24956 | + Needed to make changes to API without breaking existing drivers |
| 24957 | +*/ |
| 24958 | +#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) |
| 24959 | +#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) |
| 24960 | + |
| 24961 | +#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) |
| 24962 | +#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) |
| 24963 | + |
| 24964 | +/* |
| 24965 | + * Flags for the put_source/put_dest functions. |
| 24966 | + */ |
| 24967 | +#define DDMA_FLAGS_IE (1<<0) |
| 24968 | +#define DDMA_FLAGS_NOIE (1<<1) |
| 24969 | + |
| 24970 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 24971 | #endif /* _AU1000_DBDMA_H_ */ |
| 24972 | --- /dev/null |
| 24973 | +++ b/include/asm-mips/au1xxx_gpio.h |
| 24974 | @@ -0,0 +1,22 @@ |
| 24975 | + |
| 24976 | + |
| 24977 | +#ifndef __AU1XXX_GPIO_H |
| 24978 | +#define __AU1XXX_GPIO_H |
| 24979 | + |
| 24980 | +void au1xxx_gpio1_set_inputs(void); |
| 24981 | +void au1xxx_gpio_tristate(int signal); |
| 24982 | +void au1xxx_gpio_write(int signal, int value); |
| 24983 | +int au1xxx_gpio_read(int signal); |
| 24984 | + |
| 24985 | +typedef volatile struct |
| 24986 | +{ |
| 24987 | + u32 dir; |
| 24988 | + u32 reserved; |
| 24989 | + u32 output; |
| 24990 | + u32 pinstate; |
| 24991 | + u32 inten; |
| 24992 | + u32 enable; |
| 24993 | + |
| 24994 | +} AU1X00_GPIO2; |
| 24995 | + |
| 24996 | +#endif //__AU1XXX_GPIO_H |
| 24997 | --- a/include/asm-mips/au1xxx_psc.h |
| 24998 | +++ b/include/asm-mips/au1xxx_psc.h |
| 24999 | @@ -41,6 +41,11 @@ |
| 25000 | #define PSC3_BASE_ADDR 0xb0d00000 |
| 25001 | #endif |
| 25002 | |
| 25003 | +#ifdef CONFIG_SOC_AU1200 |
| 25004 | +#define PSC0_BASE_ADDR 0xb1a00000 |
| 25005 | +#define PSC1_BASE_ADDR 0xb1b00000 |
| 25006 | +#endif |
| 25007 | + |
| 25008 | /* The PSC select and control registers are common to |
| 25009 | * all protocols. |
| 25010 | */ |
| 25011 | @@ -226,6 +231,8 @@ typedef struct psc_i2s { |
| 25012 | #define PSC_I2SCFG_DD_DISABLE (1 << 27) |
| 25013 | #define PSC_I2SCFG_DE_ENABLE (1 << 26) |
| 25014 | #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) |
| 25015 | +#define PSC_I2SCFG_WS(n) ((n&0xFF)<<16) |
| 25016 | +#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) |
| 25017 | #define PSC_I2SCFG_WI (1 << 15) |
| 25018 | |
| 25019 | #define PSC_I2SCFG_DIV_MASK (3 << 13) |
| 25020 | --- a/include/asm-mips/bootinfo.h |
| 25021 | +++ b/include/asm-mips/bootinfo.h |
| 25022 | @@ -180,6 +180,9 @@ |
| 25023 | #define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ |
| 25024 | #define MACH_CSB250 8 /* Cogent Au1500 */ |
| 25025 | #define MACH_PB1550 9 /* Au1550-based eval board */ |
| 25026 | +#define MACH_PB1200 10 /* Au1200-based eval board */ |
| 25027 | +#define MACH_DB1550 11 /* Au1550-based eval board */ |
| 25028 | +#define MACH_DB1200 12 /* Au1200-based eval board */ |
| 25029 | |
| 25030 | /* |
| 25031 | * Valid machtype for group NEC_VR41XX |
| 25032 | --- /dev/null |
| 25033 | +++ b/include/asm-mips/db1200.h |
| 25034 | @@ -0,0 +1,214 @@ |
| 25035 | +/* |
| 25036 | + * AMD Alchemy DB1200 Referrence Board |
| 25037 | + * Board Registers defines. |
| 25038 | + * |
| 25039 | + * ######################################################################## |
| 25040 | + * |
| 25041 | + * This program is free software; you can distribute it and/or modify it |
| 25042 | + * under the terms of the GNU General Public License (Version 2) as |
| 25043 | + * published by the Free Software Foundation. |
| 25044 | + * |
| 25045 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 25046 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 25047 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 25048 | + * for more details. |
| 25049 | + * |
| 25050 | + * You should have received a copy of the GNU General Public License along |
| 25051 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 25052 | + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 25053 | + * |
| 25054 | + * ######################################################################## |
| 25055 | + * |
| 25056 | + * |
| 25057 | + */ |
| 25058 | +#ifndef __ASM_DB1200_H |
| 25059 | +#define __ASM_DB1200_H |
| 25060 | + |
| 25061 | +#include <linux/types.h> |
| 25062 | + |
| 25063 | +// This is defined in au1000.h with bogus value |
| 25064 | +#undef AU1X00_EXTERNAL_INT |
| 25065 | + |
| 25066 | +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
| 25067 | +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX |
| 25068 | +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX |
| 25069 | +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX |
| 25070 | + |
| 25071 | +/* SPI and SMB are muxed on the Pb1200 board. |
| 25072 | + Refer to board documentation. |
| 25073 | + */ |
| 25074 | +#define SPI_PSC_BASE PSC0_BASE_ADDR |
| 25075 | +#define SMBUS_PSC_BASE PSC0_BASE_ADDR |
| 25076 | +/* AC97 and I2S are muxed on the Pb1200 board. |
| 25077 | + Refer to board documentation. |
| 25078 | + */ |
| 25079 | +#define AC97_PSC_BASE PSC1_BASE_ADDR |
| 25080 | +#define I2S_PSC_BASE PSC1_BASE_ADDR |
| 25081 | + |
| 25082 | +#define BCSR_KSEG1_ADDR 0xB9800000 |
| 25083 | + |
| 25084 | +typedef volatile struct |
| 25085 | +{ |
| 25086 | + /*00*/ u16 whoami; |
| 25087 | + u16 reserved0; |
| 25088 | + /*04*/ u16 status; |
| 25089 | + u16 reserved1; |
| 25090 | + /*08*/ u16 switches; |
| 25091 | + u16 reserved2; |
| 25092 | + /*0C*/ u16 resets; |
| 25093 | + u16 reserved3; |
| 25094 | + |
| 25095 | + /*10*/ u16 pcmcia; |
| 25096 | + u16 reserved4; |
| 25097 | + /*14*/ u16 board; |
| 25098 | + u16 reserved5; |
| 25099 | + /*18*/ u16 disk_leds; |
| 25100 | + u16 reserved6; |
| 25101 | + /*1C*/ u16 system; |
| 25102 | + u16 reserved7; |
| 25103 | + |
| 25104 | + /*20*/ u16 intclr; |
| 25105 | + u16 reserved8; |
| 25106 | + /*24*/ u16 intset; |
| 25107 | + u16 reserved9; |
| 25108 | + /*28*/ u16 intclr_mask; |
| 25109 | + u16 reserved10; |
| 25110 | + /*2C*/ u16 intset_mask; |
| 25111 | + u16 reserved11; |
| 25112 | + |
| 25113 | + /*30*/ u16 sig_status; |
| 25114 | + u16 reserved12; |
| 25115 | + /*34*/ u16 int_status; |
| 25116 | + u16 reserved13; |
| 25117 | + /*38*/ u16 reserved14; |
| 25118 | + u16 reserved15; |
| 25119 | + /*3C*/ u16 reserved16; |
| 25120 | + u16 reserved17; |
| 25121 | + |
| 25122 | +} BCSR; |
| 25123 | + |
| 25124 | +static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 25125 | + |
| 25126 | +/* |
| 25127 | + * Register bit definitions for the BCSRs |
| 25128 | + */ |
| 25129 | +#define BCSR_WHOAMI_DCID 0x000F |
| 25130 | +#define BCSR_WHOAMI_CPLD 0x00F0 |
| 25131 | +#define BCSR_WHOAMI_BOARD 0x0F00 |
| 25132 | + |
| 25133 | +#define BCSR_STATUS_PCMCIA0VS 0x0003 |
| 25134 | +#define BCSR_STATUS_PCMCIA1VS 0x000C |
| 25135 | +#define BCSR_STATUS_SWAPBOOT 0x0040 |
| 25136 | +#define BCSR_STATUS_FLASHBUSY 0x0100 |
| 25137 | +#define BCSR_STATUS_IDECBLID 0x0200 |
| 25138 | +#define BCSR_STATUS_SD0WP 0x0400 |
| 25139 | +#define BCSR_STATUS_U0RXD 0x1000 |
| 25140 | +#define BCSR_STATUS_U1RXD 0x2000 |
| 25141 | + |
| 25142 | +#define BCSR_SWITCHES_OCTAL 0x00FF |
| 25143 | +#define BCSR_SWITCHES_DIP_1 0x0080 |
| 25144 | +#define BCSR_SWITCHES_DIP_2 0x0040 |
| 25145 | +#define BCSR_SWITCHES_DIP_3 0x0020 |
| 25146 | +#define BCSR_SWITCHES_DIP_4 0x0010 |
| 25147 | +#define BCSR_SWITCHES_DIP_5 0x0008 |
| 25148 | +#define BCSR_SWITCHES_DIP_6 0x0004 |
| 25149 | +#define BCSR_SWITCHES_DIP_7 0x0002 |
| 25150 | +#define BCSR_SWITCHES_DIP_8 0x0001 |
| 25151 | +#define BCSR_SWITCHES_ROTARY 0x0F00 |
| 25152 | + |
| 25153 | +#define BCSR_RESETS_ETH 0x0001 |
| 25154 | +#define BCSR_RESETS_CAMERA 0x0002 |
| 25155 | +#define BCSR_RESETS_DC 0x0004 |
| 25156 | +#define BCSR_RESETS_IDE 0x0008 |
| 25157 | +#define BCSR_RESETS_TV 0x0010 |
| 25158 | +/* not resets but in the same register */ |
| 25159 | +#define BCSR_RESETS_PWMR1mUX 0x0800 |
| 25160 | +#define BCSR_RESETS_PCS0MUX 0x1000 |
| 25161 | +#define BCSR_RESETS_PCS1MUX 0x2000 |
| 25162 | +#define BCSR_RESETS_SPISEL 0x4000 |
| 25163 | + |
| 25164 | +#define BCSR_PCMCIA_PC0VPP 0x0003 |
| 25165 | +#define BCSR_PCMCIA_PC0VCC 0x000C |
| 25166 | +#define BCSR_PCMCIA_PC0DRVEN 0x0010 |
| 25167 | +#define BCSR_PCMCIA_PC0RST 0x0080 |
| 25168 | +#define BCSR_PCMCIA_PC1VPP 0x0300 |
| 25169 | +#define BCSR_PCMCIA_PC1VCC 0x0C00 |
| 25170 | +#define BCSR_PCMCIA_PC1DRVEN 0x1000 |
| 25171 | +#define BCSR_PCMCIA_PC1RST 0x8000 |
| 25172 | + |
| 25173 | +#define BCSR_BOARD_LCDVEE 0x0001 |
| 25174 | +#define BCSR_BOARD_LCDVDD 0x0002 |
| 25175 | +#define BCSR_BOARD_LCDBL 0x0004 |
| 25176 | +#define BCSR_BOARD_CAMSNAP 0x0010 |
| 25177 | +#define BCSR_BOARD_CAMPWR 0x0020 |
| 25178 | +#define BCSR_BOARD_SD0PWR 0x0040 |
| 25179 | + |
| 25180 | +#define BCSR_LEDS_DECIMALS 0x0003 |
| 25181 | +#define BCSR_LEDS_LED0 0x0100 |
| 25182 | +#define BCSR_LEDS_LED1 0x0200 |
| 25183 | +#define BCSR_LEDS_LED2 0x0400 |
| 25184 | +#define BCSR_LEDS_LED3 0x0800 |
| 25185 | + |
| 25186 | +#define BCSR_SYSTEM_POWEROFF 0x4000 |
| 25187 | +#define BCSR_SYSTEM_RESET 0x8000 |
| 25188 | + |
| 25189 | +/* Bit positions for the different interrupt sources */ |
| 25190 | +#define BCSR_INT_IDE 0x0001 |
| 25191 | +#define BCSR_INT_ETH 0x0002 |
| 25192 | +#define BCSR_INT_PC0 0x0004 |
| 25193 | +#define BCSR_INT_PC0STSCHG 0x0008 |
| 25194 | +#define BCSR_INT_PC1 0x0010 |
| 25195 | +#define BCSR_INT_PC1STSCHG 0x0020 |
| 25196 | +#define BCSR_INT_DC 0x0040 |
| 25197 | +#define BCSR_INT_FLASHBUSY 0x0080 |
| 25198 | +#define BCSR_INT_PC0INSERT 0x0100 |
| 25199 | +#define BCSR_INT_PC0EJECT 0x0200 |
| 25200 | +#define BCSR_INT_PC1INSERT 0x0400 |
| 25201 | +#define BCSR_INT_PC1EJECT 0x0800 |
| 25202 | +#define BCSR_INT_SD0INSERT 0x1000 |
| 25203 | +#define BCSR_INT_SD0EJECT 0x2000 |
| 25204 | + |
| 25205 | +#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) |
| 25206 | +#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT |
| 25207 | + |
| 25208 | +#define AU1XXX_ATA_PHYS_ADDR (0x18800000) |
| 25209 | +#define AU1XXX_ATA_PHYS_LEN (0x100) |
| 25210 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 25211 | +#define AU1XXX_ATA_INT DB1200_IDE_INT |
| 25212 | +#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; |
| 25213 | +#define AU1XXX_ATA_RQSIZE 128 |
| 25214 | + |
| 25215 | +#define NAND_PHYS_ADDR 0x20000000 |
| 25216 | + |
| 25217 | +/* |
| 25218 | + * External Interrupts for Pb1200 as of 8/6/2004. |
| 25219 | + * Bit positions in the CPLD registers can be calculated by taking |
| 25220 | + * the interrupt define and subtracting the DB1200_INT_BEGIN value. |
| 25221 | + * *example: IDE bis pos is = 64 - 64 |
| 25222 | + ETH bit pos is = 65 - 64 |
| 25223 | + */ |
| 25224 | +#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) |
| 25225 | +#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) |
| 25226 | +#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) |
| 25227 | +#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) |
| 25228 | +#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) |
| 25229 | +#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) |
| 25230 | +#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) |
| 25231 | +#define DB1200_DC_INT (DB1200_INT_BEGIN + 6) |
| 25232 | +#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) |
| 25233 | +#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) |
| 25234 | +#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) |
| 25235 | +#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) |
| 25236 | +#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) |
| 25237 | +#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) |
| 25238 | +#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) |
| 25239 | + |
| 25240 | +#define DB1200_INT_END (DB1200_INT_BEGIN + 15) |
| 25241 | + |
| 25242 | +/* For drivers/pcmcia/au1000_db1x00.c */ |
| 25243 | +#define BOARD_PC0_INT DB1200_PC0_INT |
| 25244 | +#define BOARD_PC1_INT DB1200_PC1_INT |
| 25245 | +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) |
| 25246 | + |
| 25247 | +#endif /* __ASM_DB1200_H */ |
| 25248 | + |
| 25249 | --- a/include/asm-mips/db1x00.h |
| 25250 | +++ b/include/asm-mips/db1x00.h |
| 25251 | @@ -1,5 +1,5 @@ |
| 25252 | /* |
| 25253 | - * AMD Alchemy DB1x00 Reference Boards |
| 25254 | + * AMD Alchemy DB1x00 Reference Boards (BUT NOT DB1200) |
| 25255 | * |
| 25256 | * Copyright 2001 MontaVista Software Inc. |
| 25257 | * Author: MontaVista Software, Inc. |
| 25258 | @@ -36,9 +36,18 @@ |
| 25259 | #define AC97_PSC_BASE PSC1_BASE_ADDR |
| 25260 | #define SMBUS_PSC_BASE PSC2_BASE_ADDR |
| 25261 | #define I2S_PSC_BASE PSC3_BASE_ADDR |
| 25262 | +#define NAND_CS 1 |
| 25263 | +/* for drivers/pcmcia/au1000_db1x00.c */ |
| 25264 | +#define BOARD_PC0_INT AU1000_GPIO_3 |
| 25265 | +#define BOARD_PC1_INT AU1000_GPIO_5 |
| 25266 | +#define BOARD_CARD_INSERTED(SOCKET) !(bcsr->status & (1<<(4+SOCKET))) |
| 25267 | |
| 25268 | #else |
| 25269 | #define BCSR_KSEG1_ADDR 0xAE000000 |
| 25270 | +/* for drivers/pcmcia/au1000_db1x00.c */ |
| 25271 | +#define BOARD_PC0_INT AU1000_GPIO_2 |
| 25272 | +#define BOARD_PC1_INT AU1000_GPIO_5 |
| 25273 | +#define BOARD_CARD_INSERTED(SOCKET) !(bcsr->status & (1<<(4+SOCKET))) |
| 25274 | #endif |
| 25275 | |
| 25276 | /* |
| 25277 | @@ -66,6 +75,7 @@ typedef volatile struct |
| 25278 | |
| 25279 | } BCSR; |
| 25280 | |
| 25281 | +static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 25282 | |
| 25283 | /* |
| 25284 | * Register/mask bit definitions for the BCSRs |
| 25285 | @@ -130,14 +140,6 @@ typedef volatile struct |
| 25286 | |
| 25287 | #define BCSR_SWRESET_RESET 0x0080 |
| 25288 | |
| 25289 | -/* PCMCIA Db1x00 specific defines */ |
| 25290 | -#define PCMCIA_MAX_SOCK 1 |
| 25291 | -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) |
| 25292 | - |
| 25293 | -/* VPP/VCC */ |
| 25294 | -#define SET_VCC_VPP(VCC, VPP, SLOT)\ |
| 25295 | - ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) |
| 25296 | - |
| 25297 | /* MTD CONFIG OPTIONS */ |
| 25298 | #if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER) |
| 25299 | #define DB1X00_BOTH_BANKS |
| 25300 | @@ -147,48 +149,15 @@ typedef volatile struct |
| 25301 | #define DB1X00_USER_ONLY |
| 25302 | #endif |
| 25303 | |
| 25304 | -/* SD controller macros */ |
| 25305 | -/* |
| 25306 | - * Detect card. |
| 25307 | - */ |
| 25308 | -#define mmc_card_inserted(_n_, _res_) \ |
| 25309 | - do { \ |
| 25310 | - BCSR * const bcsr = (BCSR *)0xAE000000; \ |
| 25311 | - unsigned long mmc_wp, board_specific; \ |
| 25312 | - if ((_n_)) { \ |
| 25313 | - mmc_wp = BCSR_BOARD_SD1_WP; \ |
| 25314 | - } else { \ |
| 25315 | - mmc_wp = BCSR_BOARD_SD0_WP; \ |
| 25316 | - } \ |
| 25317 | - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ |
| 25318 | - if (!(board_specific & mmc_wp)) {/* low means card present */ \ |
| 25319 | - *(int *)(_res_) = 1; \ |
| 25320 | - } else { \ |
| 25321 | - *(int *)(_res_) = 0; \ |
| 25322 | - } \ |
| 25323 | - } while (0) |
| 25324 | - |
| 25325 | +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) && defined(CONFIG_MIPS_DB1550) |
| 25326 | /* |
| 25327 | - * Apply power to card slot(s). |
| 25328 | + * Daughter card information. |
| 25329 | */ |
| 25330 | -#define mmc_power_on(_n_) \ |
| 25331 | - do { \ |
| 25332 | - BCSR * const bcsr = (BCSR *)0xAE000000; \ |
| 25333 | - unsigned long mmc_pwr, mmc_wp, board_specific; \ |
| 25334 | - if ((_n_)) { \ |
| 25335 | - mmc_pwr = BCSR_BOARD_SD1_PWR; \ |
| 25336 | - mmc_wp = BCSR_BOARD_SD1_WP; \ |
| 25337 | - } else { \ |
| 25338 | - mmc_pwr = BCSR_BOARD_SD0_PWR; \ |
| 25339 | - mmc_wp = BCSR_BOARD_SD0_WP; \ |
| 25340 | - } \ |
| 25341 | - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ |
| 25342 | - if (!(board_specific & mmc_wp)) {/* low means card present */ \ |
| 25343 | - board_specific |= mmc_pwr; \ |
| 25344 | - au_writel(board_specific, (int)(&bcsr->specific)); \ |
| 25345 | - au_sync(); \ |
| 25346 | - } \ |
| 25347 | - } while (0) |
| 25348 | +#define DAUGHTER_CARD_IRQ (AU1000_GPIO_8) |
| 25349 | +/* DC_IDE */ |
| 25350 | +#define AU1XXX_ATA_PHYS_ADDR (0x0C000000) |
| 25351 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 25352 | +#endif /* CONFIG_MIPS_DB1550 */ |
| 25353 | |
| 25354 | #endif /* __ASM_DB1X00_H */ |
| 25355 | |
| 25356 | --- a/include/asm-mips/elf.h |
| 25357 | +++ b/include/asm-mips/elf.h |
| 25358 | @@ -66,9 +66,10 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N |
| 25359 | #define USE_ELF_CORE_DUMP |
| 25360 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
| 25361 | |
| 25362 | -#define ELF_CORE_COPY_REGS(_dest,_regs) \ |
| 25363 | - memcpy((char *) &_dest, (char *) _regs, \ |
| 25364 | - sizeof(struct pt_regs)); |
| 25365 | +extern void dump_regs(elf_greg_t *, struct pt_regs *regs); |
| 25366 | + |
| 25367 | +#define ELF_CORE_COPY_REGS(elf_regs, regs) \ |
| 25368 | + dump_regs((elf_greg_t *)&(elf_regs), regs); |
| 25369 | |
| 25370 | /* This yields a mask that user programs can use to figure out what |
| 25371 | instruction set this cpu supports. This could be done in userspace, |
| 25372 | --- /dev/null |
| 25373 | +++ b/include/asm-mips/ficmmp.h |
| 25374 | @@ -0,0 +1,156 @@ |
| 25375 | +/* |
| 25376 | + * FIC MMP |
| 25377 | + * |
| 25378 | + * ######################################################################## |
| 25379 | + * |
| 25380 | + * This program is free software; you can distribute it and/or modify it |
| 25381 | + * under the terms of the GNU General Public License (Version 2) as |
| 25382 | + * published by the Free Software Foundation. |
| 25383 | + * |
| 25384 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 25385 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 25386 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 25387 | + * for more details. |
| 25388 | + * |
| 25389 | + * You should have received a copy of the GNU General Public License along |
| 25390 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 25391 | + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 25392 | + * |
| 25393 | + * ######################################################################## |
| 25394 | + * |
| 25395 | + * |
| 25396 | + */ |
| 25397 | +#ifndef __ASM_FICMMP_H |
| 25398 | +#define __ASM_FICMMP_H |
| 25399 | + |
| 25400 | +#include <linux/types.h> |
| 25401 | +#include <asm/au1000.h> |
| 25402 | +#include <asm/au1xxx_gpio.h> |
| 25403 | + |
| 25404 | +// This is defined in au1000.h with bogus value |
| 25405 | +#undef AU1X00_EXTERNAL_INT |
| 25406 | + |
| 25407 | +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
| 25408 | +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX |
| 25409 | +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX |
| 25410 | +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX |
| 25411 | +/* SPI and SMB are muxed on the Pb1200 board. |
| 25412 | + Refer to board documentation. |
| 25413 | + */ |
| 25414 | +#define SPI_PSC_BASE PSC0_BASE_ADDR |
| 25415 | +#define SMBUS_PSC_BASE PSC0_BASE_ADDR |
| 25416 | +/* AC97 and I2S are muxed on the Pb1200 board. |
| 25417 | + Refer to board documentation. |
| 25418 | + */ |
| 25419 | +#define AC97_PSC_BASE PSC1_BASE_ADDR |
| 25420 | +#define I2S_PSC_BASE PSC1_BASE_ADDR |
| 25421 | + |
| 25422 | + |
| 25423 | +/* |
| 25424 | + * SMSC LAN91C111 |
| 25425 | + */ |
| 25426 | +#define AU1XXX_SMC91111_PHYS_ADDR (0xAC000300) |
| 25427 | +#define AU1XXX_SMC91111_IRQ AU1000_GPIO_5 |
| 25428 | + |
| 25429 | +/* DC_IDE and DC_ETHERNET */ |
| 25430 | +#define FICMMP_IDE_INT AU1000_GPIO_4 |
| 25431 | + |
| 25432 | +#define AU1XXX_ATA_PHYS_ADDR (0x0C800000) |
| 25433 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 25434 | +/* |
| 25435 | +#define AU1XXX_ATA_BASE (0x0C800000) |
| 25436 | +#define AU1XXX_ATA_END (0x0CFFFFFF) |
| 25437 | +#define AU1XXX_ATA_MEM_SIZE (AU1XXX_ATA_END - AU1XXX_ATA_BASE +1) |
| 25438 | + |
| 25439 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 25440 | +*/ |
| 25441 | +/* VPP/VCC */ |
| 25442 | +#define SET_VCC_VPP(VCC, VPP, SLOT)\ |
| 25443 | + ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) |
| 25444 | + |
| 25445 | + |
| 25446 | +#define FICMMP_CONFIG_BASE 0xAD000000 |
| 25447 | +#define FICMMP_CONFIG_ENABLE 13 |
| 25448 | + |
| 25449 | +#define FICMMP_CONFIG_I2SFREQ(N) (N<<0) |
| 25450 | +#define FICMMP_CONFIG_I2SXTAL0 (1<<0) |
| 25451 | +#define FICMMP_CONFIG_I2SXTAL1 (1<<1) |
| 25452 | +#define FICMMP_CONFIG_I2SXTAL2 (1<<2) |
| 25453 | +#define FICMMP_CONFIG_I2SXTAL3 (1<<3) |
| 25454 | +#define FICMMP_CONFIG_ADV1 (1<<4) |
| 25455 | +#define FICMMP_CONFIG_IDERST (1<<5) |
| 25456 | +#define FICMMP_CONFIG_LCMEN (1<<6) |
| 25457 | +#define FICMMP_CONFIG_CAMPWDN (1<<7) |
| 25458 | +#define FICMMP_CONFIG_USBPWREN (1<<8) |
| 25459 | +#define FICMMP_CONFIG_LCMPWREN (1<<9) |
| 25460 | +#define FICMMP_CONFIG_TVOUTPWREN (1<<10) |
| 25461 | +#define FICMMP_CONFIG_RS232PWREN (1<<11) |
| 25462 | +#define FICMMP_CONFIG_LCMDATAOUT (1<<12) |
| 25463 | +#define FICMMP_CONFIG_TVODATAOUT (1<<13) |
| 25464 | +#define FICMMP_CONFIG_ADV3 (1<<14) |
| 25465 | +#define FICMMP_CONFIG_ADV4 (1<<15) |
| 25466 | + |
| 25467 | +#define I2S_FREQ_8_192 (0x0) |
| 25468 | +#define I2S_FREQ_11_2896 (0x1) |
| 25469 | +#define I2S_FREQ_12_288 (0x2) |
| 25470 | +#define I2S_FREQ_24_576 (0x3) |
| 25471 | +//#define I2S_FREQ_12_288 (0x4) |
| 25472 | +#define I2S_FREQ_16_9344 (0x5) |
| 25473 | +#define I2S_FREQ_18_432 (0x6) |
| 25474 | +#define I2S_FREQ_36_864 (0x7) |
| 25475 | +#define I2S_FREQ_16_384 (0x8) |
| 25476 | +#define I2S_FREQ_22_5792 (0x9) |
| 25477 | +//#define I2S_FREQ_24_576 (0x10) |
| 25478 | +#define I2S_FREQ_49_152 (0x11) |
| 25479 | +//#define I2S_FREQ_24_576 (0x12) |
| 25480 | +#define I2S_FREQ_33_8688 (0x13) |
| 25481 | +//#define I2S_FREQ_36_864 (0x14) |
| 25482 | +#define I2S_FREQ_73_728 (0x15) |
| 25483 | + |
| 25484 | +#define FICMMP_IDE_PWR 9 |
| 25485 | +#define FICMMP_FOCUS_RST 2 |
| 25486 | + |
| 25487 | +static __inline void ficmmp_config_set(u16 bits) |
| 25488 | +{ |
| 25489 | + extern u16 ficmmp_config; |
| 25490 | + //printk("set_config: %X, Old: %X, New: %X\n", bits, ficmmp_config, ficmmp_config | bits); |
| 25491 | + ficmmp_config |= bits; |
| 25492 | + *((u16*)FICMMP_CONFIG_BASE) = ficmmp_config; |
| 25493 | +} |
| 25494 | + |
| 25495 | +static __inline void ficmmp_config_clear(u16 bits) |
| 25496 | +{ |
| 25497 | + extern u16 ficmmp_config; |
| 25498 | +// printk("clear_config: %X, Old: %X, New: %X\n", bits, ficmmp_config, ficmmp_config & ~bits); |
| 25499 | + ficmmp_config &= ~bits; |
| 25500 | + *((u16*)FICMMP_CONFIG_BASE) = ficmmp_config; |
| 25501 | +} |
| 25502 | + |
| 25503 | +static __inline void ficmmp_config_init(void) |
| 25504 | +{ |
| 25505 | + au1xxx_gpio_write(FICMMP_CONFIG_ENABLE, 0); //Enable configuration latch |
| 25506 | + ficmmp_config_set(FICMMP_CONFIG_LCMDATAOUT | FICMMP_CONFIG_TVODATAOUT | FICMMP_CONFIG_IDERST); //Disable display data buffers |
| 25507 | + ficmmp_config_set(FICMMP_CONFIG_I2SFREQ(I2S_FREQ_36_864)); |
| 25508 | +} |
| 25509 | + |
| 25510 | +static __inline u32 ficmmp_set_i2s_sample_rate(u32 rate) |
| 25511 | +{ |
| 25512 | + u32 freq; |
| 25513 | + |
| 25514 | + switch(rate) |
| 25515 | + { |
| 25516 | + case 88200: |
| 25517 | + case 44100: |
| 25518 | + case 8018: freq = I2S_FREQ_11_2896; break; |
| 25519 | + case 48000: |
| 25520 | + case 32000: //freq = I2S_FREQ_18_432; break; |
| 25521 | + case 8000: freq = I2S_FREQ_12_288; break; |
| 25522 | + default: freq = I2S_FREQ_12_288; rate = 8000; |
| 25523 | + } |
| 25524 | + ficmmp_config_clear(FICMMP_CONFIG_I2SFREQ(0xF)); |
| 25525 | + ficmmp_config_set(FICMMP_CONFIG_I2SFREQ(freq)); |
| 25526 | + return rate; |
| 25527 | +} |
| 25528 | + |
| 25529 | +#endif /* __ASM_FICMMP_H */ |
| 25530 | + |
| 25531 | --- a/include/asm-mips/hazards.h |
| 25532 | +++ b/include/asm-mips/hazards.h |
| 25533 | @@ -3,7 +3,7 @@ |
| 25534 | * License. See the file "COPYING" in the main directory of this archive |
| 25535 | * for more details. |
| 25536 | * |
| 25537 | - * Copyright (C) 2003 Ralf Baechle |
| 25538 | + * Copyright (C) 2003, 2004 Ralf Baechle |
| 25539 | */ |
| 25540 | #ifndef _ASM_HAZARDS_H |
| 25541 | #define _ASM_HAZARDS_H |
| 25542 | @@ -12,38 +12,200 @@ |
| 25543 | |
| 25544 | #ifdef __ASSEMBLY__ |
| 25545 | |
| 25546 | + .macro _ssnop |
| 25547 | + sll $0, $0, 1 |
| 25548 | + .endm |
| 25549 | + |
| 25550 | /* |
| 25551 | * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent |
| 25552 | * use of the JTLB for instructions should not occur for 4 cpu cycles and use |
| 25553 | * for data translations should not occur for 3 cpu cycles. |
| 25554 | */ |
| 25555 | #ifdef CONFIG_CPU_RM9000 |
| 25556 | -#define rm9000_tlb_hazard \ |
| 25557 | + |
| 25558 | +#define mtc0_tlbw_hazard \ |
| 25559 | .set push; \ |
| 25560 | .set mips32; \ |
| 25561 | - ssnop; ssnop; ssnop; ssnop; \ |
| 25562 | + _ssnop; _ssnop; _ssnop; _ssnop; \ |
| 25563 | .set pop |
| 25564 | + |
| 25565 | +#define tlbw_eret_hazard \ |
| 25566 | + .set push; \ |
| 25567 | + .set mips32; \ |
| 25568 | + _ssnop; _ssnop; _ssnop; _ssnop; \ |
| 25569 | + .set pop |
| 25570 | + |
| 25571 | #else |
| 25572 | -#define rm9000_tlb_hazard |
| 25573 | + |
| 25574 | +/* |
| 25575 | + * The taken branch will result in a two cycle penalty for the two killed |
| 25576 | + * instructions on R4000 / R4400. Other processors only have a single cycle |
| 25577 | + * hazard so this is nice trick to have an optimal code for a range of |
| 25578 | + * processors. |
| 25579 | + */ |
| 25580 | +#define mtc0_tlbw_hazard \ |
| 25581 | + b . + 8 |
| 25582 | +#define tlbw_eret_hazard \ |
| 25583 | + nop |
| 25584 | #endif |
| 25585 | |
| 25586 | +/* |
| 25587 | + * mtc0->mfc0 hazard |
| 25588 | + * The 24K has a 2 cycle mtc0/mfc0 execution hazard. |
| 25589 | + * It is a MIPS32R2 processor so ehb will clear the hazard. |
| 25590 | + */ |
| 25591 | + |
| 25592 | +#ifdef CONFIG_CPU_MIPSR2 |
| 25593 | +/* |
| 25594 | + * Use a macro for ehb unless explicit support for MIPSR2 is enabled |
| 25595 | + */ |
| 25596 | + .macro ehb |
| 25597 | + sll $0, $0, 3 |
| 25598 | + .endm |
| 25599 | + |
| 25600 | +#define irq_enable_hazard \ |
| 25601 | + ehb # irq_enable_hazard |
| 25602 | + |
| 25603 | +#define irq_disable_hazard \ |
| 25604 | + ehb # irq_disable_hazard |
| 25605 | + |
| 25606 | +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) |
| 25607 | + |
| 25608 | +/* |
| 25609 | + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
| 25610 | + */ |
| 25611 | + |
| 25612 | +#define irq_enable_hazard |
| 25613 | + |
| 25614 | +#define irq_disable_hazard |
| 25615 | + |
| 25616 | #else |
| 25617 | |
| 25618 | /* |
| 25619 | + * Classic MIPS needs 1 - 3 nops or ssnops |
| 25620 | + */ |
| 25621 | +#define irq_enable_hazard |
| 25622 | +#define irq_disable_hazard \ |
| 25623 | + _ssnop; _ssnop; _ssnop |
| 25624 | + |
| 25625 | +#endif |
| 25626 | + |
| 25627 | +#else /* __ASSEMBLY__ */ |
| 25628 | + |
| 25629 | +/* |
| 25630 | * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent |
| 25631 | * use of the JTLB for instructions should not occur for 4 cpu cycles and use |
| 25632 | * for data translations should not occur for 3 cpu cycles. |
| 25633 | */ |
| 25634 | #ifdef CONFIG_CPU_RM9000 |
| 25635 | -#define rm9000_tlb_hazard() \ |
| 25636 | + |
| 25637 | +#define mtc0_tlbw_hazard() \ |
| 25638 | __asm__ __volatile__( \ |
| 25639 | ".set\tmips32\n\t" \ |
| 25640 | - "ssnop; ssnop; ssnop; ssnop\n\t" \ |
| 25641 | + "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ |
| 25642 | + ".set\tmips0") |
| 25643 | + |
| 25644 | +#define tlbw_use_hazard() \ |
| 25645 | + __asm__ __volatile__( \ |
| 25646 | + ".set\tmips32\n\t" \ |
| 25647 | + "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ |
| 25648 | ".set\tmips0") |
| 25649 | #else |
| 25650 | -#define rm9000_tlb_hazard() do { } while (0) |
| 25651 | + |
| 25652 | +/* |
| 25653 | + * Overkill warning ... |
| 25654 | + */ |
| 25655 | +#define mtc0_tlbw_hazard() \ |
| 25656 | + __asm__ __volatile__( \ |
| 25657 | + ".set noreorder\n\t" \ |
| 25658 | + "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 25659 | + ".set reorder\n\t") |
| 25660 | + |
| 25661 | +#define tlbw_use_hazard() \ |
| 25662 | + __asm__ __volatile__( \ |
| 25663 | + ".set noreorder\n\t" \ |
| 25664 | + "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 25665 | + ".set reorder\n\t") |
| 25666 | + |
| 25667 | #endif |
| 25668 | |
| 25669 | +/* |
| 25670 | + * mtc0->mfc0 hazard |
| 25671 | + * The 24K has a 2 cycle mtc0/mfc0 execution hazard. |
| 25672 | + * It is a MIPS32R2 processor so ehb will clear the hazard. |
| 25673 | + */ |
| 25674 | + |
| 25675 | +#ifdef CONFIG_CPU_MIPSR2 |
| 25676 | +/* |
| 25677 | + * Use a macro for ehb unless explicit support for MIPSR2 is enabled |
| 25678 | + */ |
| 25679 | +__asm__( |
| 25680 | + " .macro ehb \n\t" |
| 25681 | + " sll $0, $0, 3 \n\t" |
| 25682 | + " .endm \n\t" |
| 25683 | + " \n\t" |
| 25684 | + " .macro\tirq_enable_hazard \n\t" |
| 25685 | + " ehb \n\t" |
| 25686 | + " .endm \n\t" |
| 25687 | + " \n\t" |
| 25688 | + " .macro\tirq_disable_hazard \n\t" |
| 25689 | + " ehb \n\t" |
| 25690 | + " .endm"); |
| 25691 | + |
| 25692 | +#define irq_enable_hazard() \ |
| 25693 | + __asm__ __volatile__( \ |
| 25694 | + "ehb\t\t\t\t# irq_enable_hazard") |
| 25695 | + |
| 25696 | +#define irq_disable_hazard() \ |
| 25697 | + __asm__ __volatile__( \ |
| 25698 | + "ehb\t\t\t\t# irq_disable_hazard") |
| 25699 | + |
| 25700 | +#elif defined(CONFIG_CPU_R10000) |
| 25701 | + |
| 25702 | +/* |
| 25703 | + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
| 25704 | + */ |
| 25705 | + |
| 25706 | +__asm__( |
| 25707 | + " .macro\tirq_enable_hazard \n\t" |
| 25708 | + " .endm \n\t" |
| 25709 | + " \n\t" |
| 25710 | + " .macro\tirq_disable_hazard \n\t" |
| 25711 | + " .endm"); |
| 25712 | + |
| 25713 | +#define irq_enable_hazard() do { } while (0) |
| 25714 | +#define irq_disable_hazard() do { } while (0) |
| 25715 | + |
| 25716 | +#else |
| 25717 | + |
| 25718 | +/* |
| 25719 | + * Default for classic MIPS processors. Assume worst case hazards but don't |
| 25720 | + * care about the irq_enable_hazard - sooner or later the hardware will |
| 25721 | + * enable it and we don't care when exactly. |
| 25722 | + */ |
| 25723 | + |
| 25724 | +__asm__( |
| 25725 | + " .macro _ssnop \n\t" |
| 25726 | + " sll $0, $2, 1 \n\t" |
| 25727 | + " .endm \n\t" |
| 25728 | + " \n\t" |
| 25729 | + " # \n\t" |
| 25730 | + " # There is a hazard but we do not care \n\t" |
| 25731 | + " # \n\t" |
| 25732 | + " .macro\tirq_enable_hazard \n\t" |
| 25733 | + " .endm \n\t" |
| 25734 | + " \n\t" |
| 25735 | + " .macro\tirq_disable_hazard \n\t" |
| 25736 | + " _ssnop; _ssnop; _ssnop \n\t" |
| 25737 | + " .endm"); |
| 25738 | + |
| 25739 | +#define irq_enable_hazard() do { } while (0) |
| 25740 | +#define irq_disable_hazard() \ |
| 25741 | + __asm__ __volatile__( \ |
| 25742 | + "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") |
| 25743 | + |
| 25744 | #endif |
| 25745 | |
| 25746 | +#endif /* __ASSEMBLY__ */ |
| 25747 | + |
| 25748 | #endif /* _ASM_HAZARDS_H */ |
| 25749 | --- a/include/asm-mips/ide.h |
| 25750 | +++ b/include/asm-mips/ide.h |
| 25751 | @@ -32,12 +32,12 @@ struct ide_ops { |
| 25752 | |
| 25753 | extern struct ide_ops *ide_ops; |
| 25754 | |
| 25755 | -static __inline__ int ide_default_irq(ide_ioreg_t base) |
| 25756 | +static inline int ide_default_irq(ide_ioreg_t base) |
| 25757 | { |
| 25758 | return ide_ops->ide_default_irq(base); |
| 25759 | } |
| 25760 | |
| 25761 | -static __inline__ ide_ioreg_t ide_default_io_base(int index) |
| 25762 | +static inline ide_ioreg_t ide_default_io_base(int index) |
| 25763 | { |
| 25764 | return ide_ops->ide_default_io_base(index); |
| 25765 | } |
| 25766 | @@ -48,7 +48,7 @@ static inline void ide_init_hwif_ports(h |
| 25767 | ide_ops->ide_init_hwif_ports(hw, data_port, ctrl_port, irq); |
| 25768 | } |
| 25769 | |
| 25770 | -static __inline__ void ide_init_default_hwifs(void) |
| 25771 | +static inline void ide_init_default_hwifs(void) |
| 25772 | { |
| 25773 | #ifndef CONFIG_BLK_DEV_IDEPCI |
| 25774 | hw_regs_t hw; |
| 25775 | @@ -68,7 +68,89 @@ static __inline__ void ide_init_default_ |
| 25776 | #define ide_ack_intr(hwif) ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1) |
| 25777 | #endif |
| 25778 | |
| 25779 | -#include <asm-generic/ide_iops.h> |
| 25780 | +/* MIPS port and memory-mapped I/O string operations. */ |
| 25781 | + |
| 25782 | +static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) |
| 25783 | +{ |
| 25784 | + if (cpu_has_dc_aliases) { |
| 25785 | + unsigned long end = addr + size; |
| 25786 | + for (; addr < end; addr += PAGE_SIZE) |
| 25787 | + flush_dcache_page(virt_to_page(addr)); |
| 25788 | + } |
| 25789 | +} |
| 25790 | + |
| 25791 | +static inline void __ide_insw(unsigned long port, void *addr, |
| 25792 | + unsigned int count) |
| 25793 | +{ |
| 25794 | + insw(port, addr, count); |
| 25795 | + __ide_flush_dcache_range((unsigned long)addr, count * 2); |
| 25796 | +} |
| 25797 | + |
| 25798 | +static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) |
| 25799 | +{ |
| 25800 | + insl(port, addr, count); |
| 25801 | + __ide_flush_dcache_range((unsigned long)addr, count * 4); |
| 25802 | +} |
| 25803 | + |
| 25804 | +static inline void __ide_outsw(unsigned long port, const void *addr, |
| 25805 | + unsigned long count) |
| 25806 | +{ |
| 25807 | + outsw(port, addr, count); |
| 25808 | + __ide_flush_dcache_range((unsigned long)addr, count * 2); |
| 25809 | +} |
| 25810 | + |
| 25811 | +static inline void __ide_outsl(unsigned long port, const void *addr, |
| 25812 | + unsigned long count) |
| 25813 | +{ |
| 25814 | + outsl(port, addr, count); |
| 25815 | + __ide_flush_dcache_range((unsigned long)addr, count * 4); |
| 25816 | +} |
| 25817 | + |
| 25818 | +static inline void __ide_mm_insw(unsigned long port, void *addr, u32 count) |
| 25819 | +{ |
| 25820 | + unsigned long start = (unsigned long) addr; |
| 25821 | + |
| 25822 | + while (count--) { |
| 25823 | + *(u16 *)addr = readw(port); |
| 25824 | + addr += 2; |
| 25825 | + } |
| 25826 | + __ide_flush_dcache_range(start, count * 2); |
| 25827 | +} |
| 25828 | + |
| 25829 | +static inline void __ide_mm_insl(unsigned long port, void *addr, u32 count) |
| 25830 | +{ |
| 25831 | + unsigned long start = (unsigned long) addr; |
| 25832 | + |
| 25833 | + while (count--) { |
| 25834 | + *(u32 *)addr = readl(port); |
| 25835 | + addr += 4; |
| 25836 | + } |
| 25837 | + __ide_flush_dcache_range(start, count * 4); |
| 25838 | +} |
| 25839 | + |
| 25840 | +static inline void __ide_mm_outsw(unsigned long port, const void *addr, |
| 25841 | + u32 count) |
| 25842 | +{ |
| 25843 | + unsigned long start = (unsigned long) addr; |
| 25844 | + |
| 25845 | + while (count--) { |
| 25846 | + writew(*(u16 *)addr, port); |
| 25847 | + addr += 2; |
| 25848 | + } |
| 25849 | + __ide_flush_dcache_range(start, count * 2); |
| 25850 | +} |
| 25851 | + |
| 25852 | +static inline void __ide_mm_outsl(unsigned long port, const void *addr, |
| 25853 | + u32 count) |
| 25854 | +{ |
| 25855 | + unsigned long start = (unsigned long) addr; |
| 25856 | + |
| 25857 | + while (count--) { |
| 25858 | + writel(*(u32 *)addr, port); |
| 25859 | + addr += 4; |
| 25860 | + } |
| 25861 | + __ide_flush_dcache_range(start, count * 4); |
| 25862 | +} |
| 25863 | |
| 25864 | #endif /* __KERNEL__ */ |
| 25865 | |
| 25866 | --- a/include/asm-mips/io.h |
| 25867 | +++ b/include/asm-mips/io.h |
| 25868 | @@ -392,7 +392,8 @@ static inline unsigned int inl_p(unsigne |
| 25869 | return __ioswab32(__val); |
| 25870 | } |
| 25871 | |
| 25872 | -static inline void __outsb(unsigned long port, void *addr, unsigned int count) |
| 25873 | +static inline void __outsb(unsigned long port, const void *addr, |
| 25874 | + unsigned int count) |
| 25875 | { |
| 25876 | while (count--) { |
| 25877 | outb(*(u8 *)addr, port); |
| 25878 | @@ -408,7 +409,8 @@ static inline void __insb(unsigned long |
| 25879 | } |
| 25880 | } |
| 25881 | |
| 25882 | -static inline void __outsw(unsigned long port, void *addr, unsigned int count) |
| 25883 | +static inline void __outsw(unsigned long port, const void *addr, |
| 25884 | + unsigned int count) |
| 25885 | { |
| 25886 | while (count--) { |
| 25887 | outw(*(u16 *)addr, port); |
| 25888 | @@ -424,7 +426,8 @@ static inline void __insw(unsigned long |
| 25889 | } |
| 25890 | } |
| 25891 | |
| 25892 | -static inline void __outsl(unsigned long port, void *addr, unsigned int count) |
| 25893 | +static inline void __outsl(unsigned long port, const void *addr, |
| 25894 | + unsigned int count) |
| 25895 | { |
| 25896 | while (count--) { |
| 25897 | outl(*(u32 *)addr, port); |
| 25898 | --- a/include/asm-mips/mipsregs.h |
| 25899 | +++ b/include/asm-mips/mipsregs.h |
| 25900 | @@ -757,10 +757,18 @@ do { \ |
| 25901 | #define read_c0_config1() __read_32bit_c0_register($16, 1) |
| 25902 | #define read_c0_config2() __read_32bit_c0_register($16, 2) |
| 25903 | #define read_c0_config3() __read_32bit_c0_register($16, 3) |
| 25904 | +#define read_c0_config4() __read_32bit_c0_register($16, 4) |
| 25905 | +#define read_c0_config5() __read_32bit_c0_register($16, 5) |
| 25906 | +#define read_c0_config6() __read_32bit_c0_register($16, 6) |
| 25907 | +#define read_c0_config7() __read_32bit_c0_register($16, 7) |
| 25908 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
| 25909 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) |
| 25910 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) |
| 25911 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) |
| 25912 | +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
| 25913 | +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) |
| 25914 | +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) |
| 25915 | +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) |
| 25916 | |
| 25917 | /* |
| 25918 | * The WatchLo register. There may be upto 8 of them. |
| 25919 | @@ -874,42 +882,34 @@ do { \ |
| 25920 | */ |
| 25921 | static inline void tlb_probe(void) |
| 25922 | { |
| 25923 | - rm9000_tlb_hazard(); |
| 25924 | __asm__ __volatile__( |
| 25925 | ".set noreorder\n\t" |
| 25926 | "tlbp\n\t" |
| 25927 | ".set reorder"); |
| 25928 | - rm9000_tlb_hazard(); |
| 25929 | } |
| 25930 | |
| 25931 | static inline void tlb_read(void) |
| 25932 | { |
| 25933 | - rm9000_tlb_hazard(); |
| 25934 | __asm__ __volatile__( |
| 25935 | ".set noreorder\n\t" |
| 25936 | "tlbr\n\t" |
| 25937 | ".set reorder"); |
| 25938 | - rm9000_tlb_hazard(); |
| 25939 | } |
| 25940 | |
| 25941 | static inline void tlb_write_indexed(void) |
| 25942 | { |
| 25943 | - rm9000_tlb_hazard(); |
| 25944 | __asm__ __volatile__( |
| 25945 | ".set noreorder\n\t" |
| 25946 | "tlbwi\n\t" |
| 25947 | ".set reorder"); |
| 25948 | - rm9000_tlb_hazard(); |
| 25949 | } |
| 25950 | |
| 25951 | static inline void tlb_write_random(void) |
| 25952 | { |
| 25953 | - rm9000_tlb_hazard(); |
| 25954 | __asm__ __volatile__( |
| 25955 | ".set noreorder\n\t" |
| 25956 | "tlbwr\n\t" |
| 25957 | ".set reorder"); |
| 25958 | - rm9000_tlb_hazard(); |
| 25959 | } |
| 25960 | |
| 25961 | /* |
| 25962 | --- a/include/asm-mips/mmu_context.h |
| 25963 | +++ b/include/asm-mips/mmu_context.h |
| 25964 | @@ -27,7 +27,7 @@ |
| 25965 | #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ |
| 25966 | pgd_current[smp_processor_id()] = (unsigned long)(pgd) |
| 25967 | #define TLBMISS_HANDLER_SETUP() \ |
| 25968 | - write_c0_context((unsigned long) smp_processor_id() << (23 + 3)); \ |
| 25969 | + write_c0_context((unsigned long) smp_processor_id() << 23); \ |
| 25970 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
| 25971 | extern unsigned long pgd_current[]; |
| 25972 | |
| 25973 | --- a/include/asm-mips/pb1100.h |
| 25974 | +++ b/include/asm-mips/pb1100.h |
| 25975 | @@ -1,5 +1,5 @@ |
| 25976 | /* |
| 25977 | - * Alchemy Semi PB1100 Referrence Board |
| 25978 | + * AMD Alchemy PB1100 Reference Boards |
| 25979 | * |
| 25980 | * Copyright 2001 MontaVista Software Inc. |
| 25981 | * Author: MontaVista Software, Inc. |
| 25982 | @@ -27,55 +27,108 @@ |
| 25983 | #ifndef __ASM_PB1100_H |
| 25984 | #define __ASM_PB1100_H |
| 25985 | |
| 25986 | -#define PB1100_IDENT 0xAE000000 |
| 25987 | -#define BOARD_STATUS_REG 0xAE000004 |
| 25988 | - #define PB1100_ROM_SEL (1<<15) |
| 25989 | - #define PB1100_ROM_SIZ (1<<14) |
| 25990 | - #define PB1100_SWAP_BOOT (1<<13) |
| 25991 | - #define PB1100_FLASH_WP (1<<12) |
| 25992 | - #define PB1100_ROM_H_STS (1<<11) |
| 25993 | - #define PB1100_ROM_L_STS (1<<10) |
| 25994 | - #define PB1100_FLASH_H_STS (1<<9) |
| 25995 | - #define PB1100_FLASH_L_STS (1<<8) |
| 25996 | - #define PB1100_SRAM_SIZ (1<<7) |
| 25997 | - #define PB1100_TSC_BUSY (1<<6) |
| 25998 | - #define PB1100_PCMCIA_VS_MASK (3<<4) |
| 25999 | - #define PB1100_RS232_CD (1<<3) |
| 26000 | - #define PB1100_RS232_CTS (1<<2) |
| 26001 | - #define PB1100_RS232_DSR (1<<1) |
| 26002 | - #define PB1100_RS232_RI (1<<0) |
| 26003 | - |
| 26004 | -#define PB1100_IRDA_RS232 0xAE00000C |
| 26005 | - #define PB1100_IRDA_FULL (0<<14) /* full power */ |
| 26006 | - #define PB1100_IRDA_SHUTDOWN (1<<14) |
| 26007 | - #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ |
| 26008 | - #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ |
| 26009 | - #define PB1100_IRDA_FIR (1<<13) |
| 26010 | - |
| 26011 | -#define PCMCIA_BOARD_REG 0xAE000010 |
| 26012 | - #define PB1100_SD_WP1_RO (1<<15) /* read only */ |
| 26013 | - #define PB1100_SD_WP0_RO (1<<14) /* read only */ |
| 26014 | - #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ |
| 26015 | - #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ |
| 26016 | - #define PB1100_SEL_SD_CONN1 (1<<9) |
| 26017 | - #define PB1100_SEL_SD_CONN0 (1<<8) |
| 26018 | - #define PC_DEASSERT_RST (1<<7) |
| 26019 | - #define PC_DRV_EN (1<<4) |
| 26020 | - |
| 26021 | -#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ |
| 26022 | - |
| 26023 | -#define PB1100_RST_VDDI 0xAE00001C |
| 26024 | - #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ |
| 26025 | - #define PB1100_VDDI_MASK (0x1F) |
| 26026 | +#define BCSR_KSEG1_ADDR 0xAE000000 |
| 26027 | + |
| 26028 | +/* |
| 26029 | + * Overlay data structure of the Pb1100 board registers. |
| 26030 | + * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx |
| 26031 | + */ |
| 26032 | +typedef volatile struct |
| 26033 | +{ |
| 26034 | + /*00*/ unsigned short whoami; |
| 26035 | + unsigned short reserved0; |
| 26036 | + /*04*/ unsigned short status; |
| 26037 | + unsigned short reserved1; |
| 26038 | + /*08*/ unsigned short switches; |
| 26039 | + unsigned short reserved2; |
| 26040 | + /*0C*/ unsigned short resets; |
| 26041 | + unsigned short reserved3; |
| 26042 | + /*10*/ unsigned short pcmcia; |
| 26043 | + unsigned short reserved4; |
| 26044 | + /*14*/ unsigned short graphics; |
| 26045 | + unsigned short reserved5; |
| 26046 | + /*18*/ unsigned short leds; |
| 26047 | + unsigned short reserved6; |
| 26048 | + /*1C*/ unsigned short swreset; |
| 26049 | + unsigned short reserved7; |
| 26050 | + |
| 26051 | +} BCSR; |
| 26052 | |
| 26053 | -#define PB1100_LEDS 0xAE000018 |
| 26054 | |
| 26055 | -/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. |
| 26056 | - * 7:0 is the LED Display's decimal points. |
| 26057 | +/* |
| 26058 | + * Register/mask bit definitions for the BCSRs |
| 26059 | */ |
| 26060 | -#define PB1100_HEX_LED 0xAE000018 |
| 26061 | +#define BCSR_WHOAMI_DCID 0x000F |
| 26062 | +#define BCSR_WHOAMI_CPLD 0x00F0 |
| 26063 | +#define BCSR_WHOAMI_BOARD 0x0F00 |
| 26064 | + |
| 26065 | +#define BCSR_STATUS_RS232_RI 0x0001 |
| 26066 | +#define BCSR_STATUS_RS232_DSR 0x0002 |
| 26067 | +#define BCSR_STATUS_RS232_CTS 0x0004 |
| 26068 | +#define BCSR_STATUS_RS232_CD 0x0008 |
| 26069 | +#define BCSR_STATUS_PCMCIA_VS_MASK 0x0030 |
| 26070 | +#define BCSR_STATUS_TSC_BUSY 0x0040 |
| 26071 | +#define BCSR_STATUS_SRAM_SIZ 0x0080 |
| 26072 | +#define BCSR_STATUS_FLASH_L_STS 0x0100 |
| 26073 | +#define BCSR_STATUS_FLASH_H_STS 0x0200 |
| 26074 | +#define BCSR_STATUS_ROM_H_STS 0x0400 |
| 26075 | +#define BCSR_STATUS_ROM_L_STS 0x0800 |
| 26076 | +#define BCSR_STATUS_FLASH_WP 0x1000 |
| 26077 | +#define BCSR_STATUS_SWAP_BOOT 0x2000 |
| 26078 | +#define BCSR_STATUS_ROM_SIZ 0x4000 |
| 26079 | +#define BCSR_STATUS_ROM_SEL 0x8000 |
| 26080 | + |
| 26081 | +#define BCSR_SWITCHES_DIP 0x00FF |
| 26082 | +#define BCSR_SWITCHES_DIP_1 0x0080 |
| 26083 | +#define BCSR_SWITCHES_DIP_2 0x0040 |
| 26084 | +#define BCSR_SWITCHES_DIP_3 0x0020 |
| 26085 | +#define BCSR_SWITCHES_DIP_4 0x0010 |
| 26086 | +#define BCSR_SWITCHES_DIP_5 0x0008 |
| 26087 | +#define BCSR_SWITCHES_DIP_6 0x0004 |
| 26088 | +#define BCSR_SWITCHES_DIP_7 0x0002 |
| 26089 | +#define BCSR_SWITCHES_DIP_8 0x0001 |
| 26090 | +#define BCSR_SWITCHES_ROTARY 0x0F00 |
| 26091 | +#define BCSR_SWITCHES_SDO_CL 0x8000 |
| 26092 | + |
| 26093 | +#define BCSR_RESETS_PHY0 0x0001 |
| 26094 | +#define BCSR_RESETS_PHY1 0x0002 |
| 26095 | +#define BCSR_RESETS_DC 0x0004 |
| 26096 | +#define BCSR_RESETS_RS232_RTS 0x0100 |
| 26097 | +#define BCSR_RESETS_RS232_DTR 0x0200 |
| 26098 | +#define BCSR_RESETS_FIR_SEL 0x2000 |
| 26099 | +#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 |
| 26100 | +#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 |
| 26101 | +#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 |
| 26102 | +#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 |
| 26103 | +#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 |
| 26104 | + |
| 26105 | +#define BCSR_PCMCIA_PC0VPP 0x0003 |
| 26106 | +#define BCSR_PCMCIA_PC0VCC 0x000C |
| 26107 | +#define BCSR_PCMCIA_PC0_DR_VEN 0x0010 |
| 26108 | +#define BCSR_PCMCIA_PC0RST 0x0080 |
| 26109 | +#define BCSR_PCMCIA_SEL_SD_CON0 0x0100 |
| 26110 | +#define BCSR_PCMCIA_SEL_SD_CON1 0x0200 |
| 26111 | +#define BCSR_PCMCIA_SD0_PWR 0x0400 |
| 26112 | +#define BCSR_PCMCIA_SD1_PWR 0x0800 |
| 26113 | +#define BCSR_PCMCIA_SD0_WP 0x4000 |
| 26114 | +#define BCSR_PCMCIA_SD1_WP 0x8000 |
| 26115 | + |
| 26116 | +#define PB1100_G_CONTROL 0xAE000014 |
| 26117 | +#define BCSR_GRAPHICS_GPX_SMPASS 0x0010 |
| 26118 | +#define BCSR_GRAPHICS_GPX_BIG_ENDIAN 0x0020 |
| 26119 | +#define BCSR_GRAPHICS_GPX_RST 0x0040 |
| 26120 | + |
| 26121 | +#define BCSR_LEDS_DECIMALS 0x00FF |
| 26122 | +#define BCSR_LEDS_LED0 0x0100 |
| 26123 | +#define BCSR_LEDS_LED1 0x0200 |
| 26124 | +#define BCSR_LEDS_LED2 0x0400 |
| 26125 | +#define BCSR_LEDS_LED3 0x0800 |
| 26126 | + |
| 26127 | +#define BCSR_SWRESET_RESET 0x0080 |
| 26128 | +#define BCSR_VDDI_VDI 0x001F |
| 26129 | |
| 26130 | -/* PCMCIA PB1100 specific defines */ |
| 26131 | + |
| 26132 | + /* PCMCIA Pb1x00 specific defines */ |
| 26133 | #define PCMCIA_MAX_SOCK 0 |
| 26134 | #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) |
| 26135 | |
| 26136 | @@ -83,3 +136,4 @@ |
| 26137 | #define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) |
| 26138 | |
| 26139 | #endif /* __ASM_PB1100_H */ |
| 26140 | + |
| 26141 | --- /dev/null |
| 26142 | +++ b/include/asm-mips/pb1200.h |
| 26143 | @@ -0,0 +1,244 @@ |
| 26144 | +/* |
| 26145 | + * AMD Alchemy PB1200 Referrence Board |
| 26146 | + * Board Registers defines. |
| 26147 | + * |
| 26148 | + * ######################################################################## |
| 26149 | + * |
| 26150 | + * This program is free software; you can distribute it and/or modify it |
| 26151 | + * under the terms of the GNU General Public License (Version 2) as |
| 26152 | + * published by the Free Software Foundation. |
| 26153 | + * |
| 26154 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 26155 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 26156 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 26157 | + * for more details. |
| 26158 | + * |
| 26159 | + * You should have received a copy of the GNU General Public License along |
| 26160 | + * with this program; if not, write to the Free Software Foundation, Inc., |
| 26161 | + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 26162 | + * |
| 26163 | + * ######################################################################## |
| 26164 | + * |
| 26165 | + * |
| 26166 | + */ |
| 26167 | +#ifndef __ASM_PB1200_H |
| 26168 | +#define __ASM_PB1200_H |
| 26169 | + |
| 26170 | +#include <linux/types.h> |
| 26171 | + |
| 26172 | +// This is defined in au1000.h with bogus value |
| 26173 | +#undef AU1X00_EXTERNAL_INT |
| 26174 | + |
| 26175 | +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
| 26176 | +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX |
| 26177 | +#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX |
| 26178 | +#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX |
| 26179 | + |
| 26180 | +/* SPI and SMB are muxed on the Pb1200 board. |
| 26181 | + Refer to board documentation. |
| 26182 | + */ |
| 26183 | +#define SPI_PSC_BASE PSC0_BASE_ADDR |
| 26184 | +#define SMBUS_PSC_BASE PSC0_BASE_ADDR |
| 26185 | +/* AC97 and I2S are muxed on the Pb1200 board. |
| 26186 | + Refer to board documentation. |
| 26187 | + */ |
| 26188 | +#define AC97_PSC_BASE PSC1_BASE_ADDR |
| 26189 | +#define I2S_PSC_BASE PSC1_BASE_ADDR |
| 26190 | + |
| 26191 | +#define BCSR_KSEG1_ADDR 0xAD800000 |
| 26192 | + |
| 26193 | +typedef volatile struct |
| 26194 | +{ |
| 26195 | + /*00*/ u16 whoami; |
| 26196 | + u16 reserved0; |
| 26197 | + /*04*/ u16 status; |
| 26198 | + u16 reserved1; |
| 26199 | + /*08*/ u16 switches; |
| 26200 | + u16 reserved2; |
| 26201 | + /*0C*/ u16 resets; |
| 26202 | + u16 reserved3; |
| 26203 | + |
| 26204 | + /*10*/ u16 pcmcia; |
| 26205 | + u16 reserved4; |
| 26206 | + /*14*/ u16 board; |
| 26207 | + u16 reserved5; |
| 26208 | + /*18*/ u16 disk_leds; |
| 26209 | + u16 reserved6; |
| 26210 | + /*1C*/ u16 system; |
| 26211 | + u16 reserved7; |
| 26212 | + |
| 26213 | + /*20*/ u16 intclr; |
| 26214 | + u16 reserved8; |
| 26215 | + /*24*/ u16 intset; |
| 26216 | + u16 reserved9; |
| 26217 | + /*28*/ u16 intclr_mask; |
| 26218 | + u16 reserved10; |
| 26219 | + /*2C*/ u16 intset_mask; |
| 26220 | + u16 reserved11; |
| 26221 | + |
| 26222 | + /*30*/ u16 sig_status; |
| 26223 | + u16 reserved12; |
| 26224 | + /*34*/ u16 int_status; |
| 26225 | + u16 reserved13; |
| 26226 | + /*38*/ u16 reserved14; |
| 26227 | + u16 reserved15; |
| 26228 | + /*3C*/ u16 reserved16; |
| 26229 | + u16 reserved17; |
| 26230 | + |
| 26231 | +} BCSR; |
| 26232 | + |
| 26233 | +static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 26234 | + |
| 26235 | +/* |
| 26236 | + * Register bit definitions for the BCSRs |
| 26237 | + */ |
| 26238 | +#define BCSR_WHOAMI_DCID 0x000F |
| 26239 | +#define BCSR_WHOAMI_CPLD 0x00F0 |
| 26240 | +#define BCSR_WHOAMI_BOARD 0x0F00 |
| 26241 | + |
| 26242 | +#define BCSR_STATUS_PCMCIA0VS 0x0003 |
| 26243 | +#define BCSR_STATUS_PCMCIA1VS 0x000C |
| 26244 | +#define BCSR_STATUS_SWAPBOOT 0x0040 |
| 26245 | +#define BCSR_STATUS_FLASHBUSY 0x0100 |
| 26246 | +#define BCSR_STATUS_IDECBLID 0x0200 |
| 26247 | +#define BCSR_STATUS_SD0WP 0x0400 |
| 26248 | +#define BCSR_STATUS_SD1WP 0x0800 |
| 26249 | +#define BCSR_STATUS_U0RXD 0x1000 |
| 26250 | +#define BCSR_STATUS_U1RXD 0x2000 |
| 26251 | + |
| 26252 | +#define BCSR_SWITCHES_OCTAL 0x00FF |
| 26253 | +#define BCSR_SWITCHES_DIP_1 0x0080 |
| 26254 | +#define BCSR_SWITCHES_DIP_2 0x0040 |
| 26255 | +#define BCSR_SWITCHES_DIP_3 0x0020 |
| 26256 | +#define BCSR_SWITCHES_DIP_4 0x0010 |
| 26257 | +#define BCSR_SWITCHES_DIP_5 0x0008 |
| 26258 | +#define BCSR_SWITCHES_DIP_6 0x0004 |
| 26259 | +#define BCSR_SWITCHES_DIP_7 0x0002 |
| 26260 | +#define BCSR_SWITCHES_DIP_8 0x0001 |
| 26261 | +#define BCSR_SWITCHES_ROTARY 0x0F00 |
| 26262 | + |
| 26263 | +#define BCSR_RESETS_ETH 0x0001 |
| 26264 | +#define BCSR_RESETS_CAMERA 0x0002 |
| 26265 | +#define BCSR_RESETS_DC 0x0004 |
| 26266 | +#define BCSR_RESETS_IDE 0x0008 |
| 26267 | +/* not resets but in the same register */ |
| 26268 | +#define BCSR_RESETS_WSCFSM 0x0800 |
| 26269 | +#define BCSR_RESETS_PCS0MUX 0x1000 |
| 26270 | +#define BCSR_RESETS_PCS1MUX 0x2000 |
| 26271 | +#define BCSR_RESETS_SPISEL 0x4000 |
| 26272 | +#define BCSR_RESETS_SD1MUX 0x8000 |
| 26273 | + |
| 26274 | +#define BCSR_PCMCIA_PC0VPP 0x0003 |
| 26275 | +#define BCSR_PCMCIA_PC0VCC 0x000C |
| 26276 | +#define BCSR_PCMCIA_PC0DRVEN 0x0010 |
| 26277 | +#define BCSR_PCMCIA_PC0RST 0x0080 |
| 26278 | +#define BCSR_PCMCIA_PC1VPP 0x0300 |
| 26279 | +#define BCSR_PCMCIA_PC1VCC 0x0C00 |
| 26280 | +#define BCSR_PCMCIA_PC1DRVEN 0x1000 |
| 26281 | +#define BCSR_PCMCIA_PC1RST 0x8000 |
| 26282 | + |
| 26283 | +#define BCSR_BOARD_LCDVEE 0x0001 |
| 26284 | +#define BCSR_BOARD_LCDVDD 0x0002 |
| 26285 | +#define BCSR_BOARD_LCDBL 0x0004 |
| 26286 | +#define BCSR_BOARD_CAMSNAP 0x0010 |
| 26287 | +#define BCSR_BOARD_CAMPWR 0x0020 |
| 26288 | +#define BCSR_BOARD_SD0PWR 0x0040 |
| 26289 | +#define BCSR_BOARD_SD1PWR 0x0080 |
| 26290 | + |
| 26291 | +#define BCSR_LEDS_DECIMALS 0x00FF |
| 26292 | +#define BCSR_LEDS_LED0 0x0100 |
| 26293 | +#define BCSR_LEDS_LED1 0x0200 |
| 26294 | +#define BCSR_LEDS_LED2 0x0400 |
| 26295 | +#define BCSR_LEDS_LED3 0x0800 |
| 26296 | + |
| 26297 | +#define BCSR_SYSTEM_VDDI 0x001F |
| 26298 | +#define BCSR_SYSTEM_POWEROFF 0x4000 |
| 26299 | +#define BCSR_SYSTEM_RESET 0x8000 |
| 26300 | + |
| 26301 | +/* Bit positions for the different interrupt sources */ |
| 26302 | +#define BCSR_INT_IDE 0x0001 |
| 26303 | +#define BCSR_INT_ETH 0x0002 |
| 26304 | +#define BCSR_INT_PC0 0x0004 |
| 26305 | +#define BCSR_INT_PC0STSCHG 0x0008 |
| 26306 | +#define BCSR_INT_PC1 0x0010 |
| 26307 | +#define BCSR_INT_PC1STSCHG 0x0020 |
| 26308 | +#define BCSR_INT_DC 0x0040 |
| 26309 | +#define BCSR_INT_FLASHBUSY 0x0080 |
| 26310 | +#define BCSR_INT_PC0INSERT 0x0100 |
| 26311 | +#define BCSR_INT_PC0EJECT 0x0200 |
| 26312 | +#define BCSR_INT_PC1INSERT 0x0400 |
| 26313 | +#define BCSR_INT_PC1EJECT 0x0800 |
| 26314 | +#define BCSR_INT_SD0INSERT 0x1000 |
| 26315 | +#define BCSR_INT_SD0EJECT 0x2000 |
| 26316 | +#define BCSR_INT_SD1INSERT 0x4000 |
| 26317 | +#define BCSR_INT_SD1EJECT 0x8000 |
| 26318 | + |
| 26319 | +#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300) |
| 26320 | +#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT |
| 26321 | + |
| 26322 | +#define AU1XXX_ATA_PHYS_ADDR (0x0C800000) |
| 26323 | +#define AU1XXX_ATA_PHYS_LEN (0x100) |
| 26324 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 26325 | +#define AU1XXX_ATA_INT PB1200_IDE_INT |
| 26326 | +#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; |
| 26327 | +#define AU1XXX_ATA_RQSIZE 128 |
| 26328 | + |
| 26329 | +#define NAND_PHYS_ADDR 0x1C000000 |
| 26330 | + |
| 26331 | +/* Timing values as described in databook, * ns value stripped of |
| 26332 | + * lower 2 bits. |
| 26333 | + * These defines are here rather than an SOC1200 generic file because |
| 26334 | + * the parts chosen on another board may be different and may require |
| 26335 | + * different timings. |
| 26336 | + */ |
| 26337 | +#define NAND_T_H (18 >> 2) |
| 26338 | +#define NAND_T_PUL (30 >> 2) |
| 26339 | +#define NAND_T_SU (30 >> 2) |
| 26340 | +#define NAND_T_WH (30 >> 2) |
| 26341 | + |
| 26342 | +/* Bitfield shift amounts */ |
| 26343 | +#define NAND_T_H_SHIFT 0 |
| 26344 | +#define NAND_T_PUL_SHIFT 4 |
| 26345 | +#define NAND_T_SU_SHIFT 8 |
| 26346 | +#define NAND_T_WH_SHIFT 12 |
| 26347 | + |
| 26348 | +#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ |
| 26349 | + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ |
| 26350 | + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ |
| 26351 | + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) |
| 26352 | + |
| 26353 | + |
| 26354 | +/* |
| 26355 | + * External Interrupts for Pb1200 as of 8/6/2004. |
| 26356 | + * Bit positions in the CPLD registers can be calculated by taking |
| 26357 | + * the interrupt define and subtracting the PB1200_INT_BEGIN value. |
| 26358 | + * *example: IDE bis pos is = 64 - 64 |
| 26359 | + ETH bit pos is = 65 - 64 |
| 26360 | + */ |
| 26361 | +#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) |
| 26362 | +#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0) |
| 26363 | +#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1) |
| 26364 | +#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2) |
| 26365 | +#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3) |
| 26366 | +#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4) |
| 26367 | +#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5) |
| 26368 | +#define PB1200_DC_INT (PB1200_INT_BEGIN + 6) |
| 26369 | +#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7) |
| 26370 | +#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8) |
| 26371 | +#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9) |
| 26372 | +#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10) |
| 26373 | +#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11) |
| 26374 | +#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12) |
| 26375 | +#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13) |
| 26376 | +#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14) |
| 26377 | +#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15) |
| 26378 | + |
| 26379 | +#define PB1200_INT_END (PB1200_INT_BEGIN + 15) |
| 26380 | + |
| 26381 | +/* For drivers/pcmcia/au1000_db1x00.c */ |
| 26382 | +#define BOARD_PC0_INT PB1200_PC0_INT |
| 26383 | +#define BOARD_PC1_INT PB1200_PC1_INT |
| 26384 | +#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) |
| 26385 | + |
| 26386 | +#endif /* __ASM_PB1200_H */ |
| 26387 | + |
| 26388 | --- a/include/asm-mips/pb1550.h |
| 26389 | +++ b/include/asm-mips/pb1550.h |
| 26390 | @@ -30,13 +30,11 @@ |
| 26391 | |
| 26392 | #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
| 26393 | #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX |
| 26394 | -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX |
| 26395 | -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX |
| 26396 | - |
| 26397 | #define SPI_PSC_BASE PSC0_BASE_ADDR |
| 26398 | #define AC97_PSC_BASE PSC1_BASE_ADDR |
| 26399 | #define SMBUS_PSC_BASE PSC2_BASE_ADDR |
| 26400 | #define I2S_PSC_BASE PSC3_BASE_ADDR |
| 26401 | +#define NAND_CS 1 |
| 26402 | |
| 26403 | #define BCSR_PHYS_ADDR 0xAF000000 |
| 26404 | |
| 26405 | @@ -160,9 +158,23 @@ static BCSR * const bcsr = (BCSR *)BCSR_ |
| 26406 | #define NAND_T_SU_SHIFT 8 |
| 26407 | #define NAND_T_WH_SHIFT 12 |
| 26408 | |
| 26409 | -#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ |
| 26410 | - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ |
| 26411 | - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ |
| 26412 | - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) |
| 26413 | +#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ |
| 26414 | + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ |
| 26415 | + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ |
| 26416 | + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) |
| 26417 | + |
| 26418 | +/* |
| 26419 | + * Daughter card information. |
| 26420 | + */ |
| 26421 | +#define DAUGHTER_CARD_BASE (0xAC000000) |
| 26422 | +#define DAUGHTER_CARD_MEM_SIZE (0xADFFFFFF - DAUGHTER_CARD_BASE + 1) |
| 26423 | +#define DAUGHTER_CARD_IRQ (AU1000_GPIO_3) |
| 26424 | + |
| 26425 | +/* DC_IDE and DC_ETHERNET */ |
| 26426 | +#define AU1XXX_ATA_PHYS_ADDR (0x0C000000) |
| 26427 | +#define AU1XXX_ATA_REG_OFFSET (5) |
| 26428 | + |
| 26429 | +#define AU1XXX_SMC91111_PHYS_ADDR (0x0C000300) |
| 26430 | +#define AU1XXX_SMC91111_IRQ AU1000_GPIO_3 |
| 26431 | |
| 26432 | #endif /* __ASM_PB1550_H */ |
| 26433 | --- a/include/asm-mips/reg.h |
| 26434 | +++ b/include/asm-mips/reg.h |
| 26435 | @@ -45,6 +45,9 @@ |
| 26436 | /* |
| 26437 | * k0/k1 unsaved |
| 26438 | */ |
| 26439 | +#define EF_REG26 32 |
| 26440 | +#define EF_REG27 33 |
| 26441 | + |
| 26442 | #define EF_REG28 34 |
| 26443 | #define EF_REG29 35 |
| 26444 | #define EF_REG30 36 |
| 26445 | @@ -60,6 +63,7 @@ |
| 26446 | #define EF_CP0_BADVADDR 41 |
| 26447 | #define EF_CP0_STATUS 42 |
| 26448 | #define EF_CP0_CAUSE 43 |
| 26449 | +#define EF_UNUSED0 44 |
| 26450 | |
| 26451 | #define EF_SIZE 180 /* size in bytes */ |
| 26452 | |
| 26453 | --- a/include/asm-mips/sgi/hpc3.h |
| 26454 | +++ b/include/asm-mips/sgi/hpc3.h |
| 26455 | @@ -128,26 +128,26 @@ struct hpc3_ethregs { |
| 26456 | volatile u32 rx_gfptr; /* current GIO fifo ptr */ |
| 26457 | volatile u32 rx_dfptr; /* current device fifo ptr */ |
| 26458 | u32 _unused1; /* padding */ |
| 26459 | - volatile u32 rx_reset; /* reset register */ |
| 26460 | -#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ |
| 26461 | -#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ |
| 26462 | -#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ |
| 26463 | - |
| 26464 | - volatile u32 rx_dconfig; /* DMA configuration register */ |
| 26465 | -#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ |
| 26466 | -#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ |
| 26467 | -#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ |
| 26468 | -#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ |
| 26469 | -#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ |
| 26470 | -#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ |
| 26471 | -#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ |
| 26472 | -#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ |
| 26473 | - |
| 26474 | - volatile u32 rx_pconfig; /* PIO configuration register */ |
| 26475 | -#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ |
| 26476 | -#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ |
| 26477 | -#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ |
| 26478 | -#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ |
| 26479 | + volatile u32 reset; /* reset register */ |
| 26480 | +#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */ |
| 26481 | +#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */ |
| 26482 | +#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ |
| 26483 | + |
| 26484 | + volatile u32 dconfig; /* DMA configuration register */ |
| 26485 | +#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ |
| 26486 | +#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ |
| 26487 | +#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ |
| 26488 | +#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ |
| 26489 | +#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ |
| 26490 | +#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ |
| 26491 | +#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ |
| 26492 | +#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ |
| 26493 | + |
| 26494 | + volatile u32 pconfig; /* PIO configuration register */ |
| 26495 | +#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ |
| 26496 | +#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ |
| 26497 | +#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ |
| 26498 | +#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ |
| 26499 | |
| 26500 | u32 _unused2[0x1000/4 - 8]; /* padding */ |
| 26501 | |
| 26502 | @@ -221,7 +221,7 @@ struct hpc3_regs { |
| 26503 | #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ |
| 26504 | |
| 26505 | u32 _unused1[0x14000/4 - 5]; /* padding */ |
| 26506 | - |
| 26507 | + |
| 26508 | /* Now direct PIO per-HPC3 peripheral access to external regs. */ |
| 26509 | volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ |
| 26510 | u32 _unused2[0x7c00/4]; |
| 26511 | @@ -304,7 +304,7 @@ struct hpc3_regs { |
| 26512 | volatile u32 bbram[8192-50-14]; /* Battery backed ram */ |
| 26513 | }; |
| 26514 | |
| 26515 | -/* |
| 26516 | +/* |
| 26517 | * It is possible to have two HPC3's within the address space on |
| 26518 | * one machine, though only having one is more likely on an Indy. |
| 26519 | */ |
| 26520 | --- a/include/asm-mips/tx4927/tx4927.h |
| 26521 | +++ b/include/asm-mips/tx4927/tx4927.h |
| 26522 | @@ -88,8 +88,8 @@ |
| 26523 | |
| 26524 | |
| 26525 | /* TX4927 Configuration registers (64-bit registers) */ |
| 26526 | -#define TX4927_CONFIG_BASE 0xe300 |
| 26527 | -#define TX4927_CONFIG_CCFG 0xe300 |
| 26528 | +#define TX4927_CONFIG_BASE 0xe000 |
| 26529 | +#define TX4927_CONFIG_CCFG 0xe000 |
| 26530 | #define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 |
| 26531 | #define TX4927_CONFIG_CCFG_WDRST BM_41_41 |
| 26532 | #define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 |
| 26533 | @@ -124,14 +124,14 @@ |
| 26534 | #define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 |
| 26535 | #define TX4927_CONFIG_CCFG_ARMODE BM_01_01 |
| 26536 | #define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 |
| 26537 | -#define TX4927_CONFIG_REVID 0xe308 |
| 26538 | +#define TX4927_CONFIG_REVID 0xe008 |
| 26539 | #define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 |
| 26540 | #define TX4927_CONFIG_REVID_PCODE BM_16_31 |
| 26541 | #define TX4927_CONFIG_REVID_MJERREV BM_12_15 |
| 26542 | #define TX4927_CONFIG_REVID_MINEREV BM_08_11 |
| 26543 | #define TX4927_CONFIG_REVID_MJREV BM_04_07 |
| 26544 | #define TX4927_CONFIG_REVID_MINREV BM_00_03 |
| 26545 | -#define TX4927_CONFIG_PCFG 0xe310 |
| 26546 | +#define TX4927_CONFIG_PCFG 0xe010 |
| 26547 | #define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 |
| 26548 | #define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 |
| 26549 | #define TX4927_CONFIG_PCFG_DRVCB BM_55_55 |
| 26550 | @@ -197,10 +197,10 @@ |
| 26551 | #define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 |
| 26552 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 |
| 26553 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 |
| 26554 | -#define TX4927_CONFIG_TOEA 0xe318 |
| 26555 | +#define TX4927_CONFIG_TOEA 0xe018 |
| 26556 | #define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 |
| 26557 | #define TX4927_CONFIG_TOEA_TOEA BM_00_35 |
| 26558 | -#define TX4927_CONFIG_CLKCTR 0xe320 |
| 26559 | +#define TX4927_CONFIG_CLKCTR 0xe020 |
| 26560 | #define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 |
| 26561 | #define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 |
| 26562 | #define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 |
| 26563 | @@ -223,7 +223,7 @@ |
| 26564 | #define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 |
| 26565 | #define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 |
| 26566 | #define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 |
| 26567 | -#define TX4927_CONFIG_GARBC 0xe330 |
| 26568 | +#define TX4927_CONFIG_GARBC 0xe030 |
| 26569 | #define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 |
| 26570 | #define TX4927_CONFIG_GARBC_SET_09 BM_09_09 |
| 26571 | #define TX4927_CONFIG_GARBC_ARBMD BM_08_08 |
| 26572 | @@ -243,7 +243,7 @@ |
| 26573 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 |
| 26574 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 |
| 26575 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 |
| 26576 | -#define TX4927_CONFIG_RAMP 0xe348 |
| 26577 | +#define TX4927_CONFIG_RAMP 0xe048 |
| 26578 | #define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 |
| 26579 | #define TX4927_CONFIG_RAMP_RAMP BM_00_19 |
| 26580 | #define TX4927_CONFIG_LIMIT 0xefff |
| 26581 | @@ -456,7 +456,7 @@ |
| 26582 | #define TX4927_ACLC_ACINTSTS 0xf710 |
| 26583 | #define TX4927_ACLC_ACINTMSTS 0xf714 |
| 26584 | #define TX4927_ACLC_ACINTEN 0xf718 |
| 26585 | -#define TX4927_ACLC_ACINTDIS 0xfR71c |
| 26586 | +#define TX4927_ACLC_ACINTDIS 0xf71c |
| 26587 | #define TX4927_ACLC_ACSEMAPH 0xf720 |
| 26588 | #define TX4927_ACLC_ACGPIDAT 0xf740 |
| 26589 | #define TX4927_ACLC_ACGPODAT 0xf744 |
| 26590 | --- a/include/asm-mips/unistd.h |
| 26591 | +++ b/include/asm-mips/unistd.h |
| 26592 | @@ -760,7 +760,7 @@ type name(void) \ |
| 26593 | if (__a3 == 0) \ |
| 26594 | return (type) __v0; \ |
| 26595 | errno = __v0; \ |
| 26596 | - return -1; \ |
| 26597 | + return (type)-1; \ |
| 26598 | } |
| 26599 | |
| 26600 | /* |
| 26601 | @@ -788,7 +788,7 @@ type name(atype a) \ |
| 26602 | if (__a3 == 0) \ |
| 26603 | return (type) __v0; \ |
| 26604 | errno = __v0; \ |
| 26605 | - return -1; \ |
| 26606 | + return (type)-1; \ |
| 26607 | } |
| 26608 | |
| 26609 | #define _syscall2(type,name,atype,a,btype,b) \ |
| 26610 | @@ -813,7 +813,7 @@ type name(atype a, btype b) \ |
| 26611 | if (__a3 == 0) \ |
| 26612 | return (type) __v0; \ |
| 26613 | errno = __v0; \ |
| 26614 | - return -1; \ |
| 26615 | + return (type)-1; \ |
| 26616 | } |
| 26617 | |
| 26618 | #define _syscall3(type,name,atype,a,btype,b,ctype,c) \ |
| 26619 | @@ -839,7 +839,7 @@ type name(atype a, btype b, ctype c) \ |
| 26620 | if (__a3 == 0) \ |
| 26621 | return (type) __v0; \ |
| 26622 | errno = __v0; \ |
| 26623 | - return -1; \ |
| 26624 | + return (type)-1; \ |
| 26625 | } |
| 26626 | |
| 26627 | #define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ |
| 26628 | @@ -865,7 +865,7 @@ type name(atype a, btype b, ctype c, dty |
| 26629 | if (__a3 == 0) \ |
| 26630 | return (type) __v0; \ |
| 26631 | errno = __v0; \ |
| 26632 | - return -1; \ |
| 26633 | + return (type)-1; \ |
| 26634 | } |
| 26635 | |
| 26636 | #if (_MIPS_SIM == _MIPS_SIM_ABI32) |
| 26637 | @@ -902,7 +902,7 @@ type name(atype a, btype b, ctype c, dty |
| 26638 | if (__a3 == 0) \ |
| 26639 | return (type) __v0; \ |
| 26640 | errno = __v0; \ |
| 26641 | - return -1; \ |
| 26642 | + return (type)-1; \ |
| 26643 | } |
| 26644 | |
| 26645 | #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ |
| 26646 | @@ -935,7 +935,7 @@ type name(atype a, btype b, ctype c, dty |
| 26647 | if (__a3 == 0) \ |
| 26648 | return (type) __v0; \ |
| 26649 | errno = __v0; \ |
| 26650 | - return -1; \ |
| 26651 | + return (type)-1; \ |
| 26652 | } |
| 26653 | |
| 26654 | #endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */ |
| 26655 | @@ -966,7 +966,7 @@ type name (atype a,btype b,ctype c,dtype |
| 26656 | if (__a3 == 0) \ |
| 26657 | return (type) __v0; \ |
| 26658 | errno = __v0; \ |
| 26659 | - return -1; \ |
| 26660 | + return (type)-1; \ |
| 26661 | } |
| 26662 | |
| 26663 | #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ |
| 26664 | @@ -995,7 +995,7 @@ type name (atype a,btype b,ctype c,dtype |
| 26665 | if (__a3 == 0) \ |
| 26666 | return (type) __v0; \ |
| 26667 | errno = __v0; \ |
| 26668 | - return -1; \ |
| 26669 | + return (type)-1; \ |
| 26670 | } |
| 26671 | |
| 26672 | #endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ |
| 26673 | --- a/include/asm-mips64/checksum.h |
| 26674 | +++ b/include/asm-mips64/checksum.h |
| 26675 | @@ -144,7 +144,7 @@ static inline unsigned long csum_tcpudp_ |
| 26676 | "daddu\t%0, %4\n\t" |
| 26677 | "dsll32\t$1, %0, 0\n\t" |
| 26678 | "daddu\t%0, $1\n\t" |
| 26679 | - "dsrl32\t%0, %0, 0\n\t" |
| 26680 | + "dsra32\t%0, %0, 0\n\t" |
| 26681 | ".set\tat" |
| 26682 | : "=&r" (sum) |
| 26683 | : "0" (daddr), "r"(saddr), |
| 26684 | --- a/include/asm-mips64/elf.h |
| 26685 | +++ b/include/asm-mips64/elf.h |
| 26686 | @@ -64,9 +64,10 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N |
| 26687 | #define USE_ELF_CORE_DUMP |
| 26688 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
| 26689 | |
| 26690 | -#define ELF_CORE_COPY_REGS(_dest,_regs) \ |
| 26691 | - memcpy((char *) &_dest, (char *) _regs, \ |
| 26692 | - sizeof(struct pt_regs)); |
| 26693 | +extern void dump_regs(elf_greg_t *, struct pt_regs *regs); |
| 26694 | + |
| 26695 | +#define ELF_CORE_COPY_REGS(elf_regs, regs) \ |
| 26696 | + dump_regs((elf_greg_t *)&(elf_regs), regs); |
| 26697 | |
| 26698 | /* This yields a mask that user programs can use to figure out what |
| 26699 | instruction set this cpu supports. This could be done in userspace, |
| 26700 | --- a/include/asm-mips64/hazards.h |
| 26701 | +++ b/include/asm-mips64/hazards.h |
| 26702 | @@ -3,7 +3,7 @@ |
| 26703 | * License. See the file "COPYING" in the main directory of this archive |
| 26704 | * for more details. |
| 26705 | * |
| 26706 | - * Copyright (C) 2003 Ralf Baechle |
| 26707 | + * Copyright (C) 2003, 2004 Ralf Baechle |
| 26708 | */ |
| 26709 | #ifndef _ASM_HAZARDS_H |
| 26710 | #define _ASM_HAZARDS_H |
| 26711 | @@ -12,37 +12,200 @@ |
| 26712 | |
| 26713 | #ifdef __ASSEMBLY__ |
| 26714 | |
| 26715 | + .macro _ssnop |
| 26716 | + sll $0, $0, 1 |
| 26717 | + .endm |
| 26718 | + |
| 26719 | /* |
| 26720 | * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent |
| 26721 | * use of the JTLB for instructions should not occur for 4 cpu cycles and use |
| 26722 | * for data translations should not occur for 3 cpu cycles. |
| 26723 | */ |
| 26724 | #ifdef CONFIG_CPU_RM9000 |
| 26725 | -#define rm9000_tlb_hazard \ |
| 26726 | + |
| 26727 | +#define mtc0_tlbw_hazard \ |
| 26728 | + .set push; \ |
| 26729 | .set mips32; \ |
| 26730 | - ssnop; ssnop; ssnop; ssnop; \ |
| 26731 | - .set mips0 |
| 26732 | + _ssnop; _ssnop; _ssnop; _ssnop; \ |
| 26733 | + .set pop |
| 26734 | + |
| 26735 | +#define tlbw_eret_hazard \ |
| 26736 | + .set push; \ |
| 26737 | + .set mips32; \ |
| 26738 | + _ssnop; _ssnop; _ssnop; _ssnop; \ |
| 26739 | + .set pop |
| 26740 | + |
| 26741 | #else |
| 26742 | -#define rm9000_tlb_hazard |
| 26743 | + |
| 26744 | +/* |
| 26745 | + * The taken branch will result in a two cycle penalty for the two killed |
| 26746 | + * instructions on R4000 / R4400. Other processors only have a single cycle |
| 26747 | + * hazard so this is nice trick to have an optimal code for a range of |
| 26748 | + * processors. |
| 26749 | + */ |
| 26750 | +#define mtc0_tlbw_hazard \ |
| 26751 | + b . + 8 |
| 26752 | +#define tlbw_eret_hazard \ |
| 26753 | + nop |
| 26754 | #endif |
| 26755 | |
| 26756 | +/* |
| 26757 | + * mtc0->mfc0 hazard |
| 26758 | + * The 24K has a 2 cycle mtc0/mfc0 execution hazard. |
| 26759 | + * It is a MIPS32R2 processor so ehb will clear the hazard. |
| 26760 | + */ |
| 26761 | + |
| 26762 | +#ifdef CONFIG_CPU_MIPSR2 |
| 26763 | +/* |
| 26764 | + * Use a macro for ehb unless explicit support for MIPSR2 is enabled |
| 26765 | + */ |
| 26766 | + .macro ehb |
| 26767 | + sll $0, $0, 3 |
| 26768 | + .endm |
| 26769 | + |
| 26770 | +#define irq_enable_hazard \ |
| 26771 | + ehb # irq_enable_hazard |
| 26772 | + |
| 26773 | +#define irq_disable_hazard \ |
| 26774 | + ehb # irq_disable_hazard |
| 26775 | + |
| 26776 | +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) |
| 26777 | + |
| 26778 | +/* |
| 26779 | + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
| 26780 | + */ |
| 26781 | + |
| 26782 | +#define irq_enable_hazard |
| 26783 | + |
| 26784 | +#define irq_disable_hazard |
| 26785 | + |
| 26786 | #else |
| 26787 | |
| 26788 | /* |
| 26789 | + * Classic MIPS needs 1 - 3 nops or ssnops |
| 26790 | + */ |
| 26791 | +#define irq_enable_hazard |
| 26792 | +#define irq_disable_hazard \ |
| 26793 | + _ssnop; _ssnop; _ssnop |
| 26794 | + |
| 26795 | +#endif |
| 26796 | + |
| 26797 | +#else /* __ASSEMBLY__ */ |
| 26798 | + |
| 26799 | +/* |
| 26800 | * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent |
| 26801 | * use of the JTLB for instructions should not occur for 4 cpu cycles and use |
| 26802 | * for data translations should not occur for 3 cpu cycles. |
| 26803 | */ |
| 26804 | #ifdef CONFIG_CPU_RM9000 |
| 26805 | -#define rm9000_tlb_hazard() \ |
| 26806 | + |
| 26807 | +#define mtc0_tlbw_hazard() \ |
| 26808 | + __asm__ __volatile__( \ |
| 26809 | + ".set\tmips32\n\t" \ |
| 26810 | + "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ |
| 26811 | + ".set\tmips0") |
| 26812 | + |
| 26813 | +#define tlbw_use_hazard() \ |
| 26814 | __asm__ __volatile__( \ |
| 26815 | ".set\tmips32\n\t" \ |
| 26816 | - "ssnop; ssnop; ssnop; ssnop\n\t" \ |
| 26817 | + "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ |
| 26818 | ".set\tmips0") |
| 26819 | #else |
| 26820 | -#define rm9000_tlb_hazard() do { } while (0) |
| 26821 | + |
| 26822 | +/* |
| 26823 | + * Overkill warning ... |
| 26824 | + */ |
| 26825 | +#define mtc0_tlbw_hazard() \ |
| 26826 | + __asm__ __volatile__( \ |
| 26827 | + ".set noreorder\n\t" \ |
| 26828 | + "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 26829 | + ".set reorder\n\t") |
| 26830 | + |
| 26831 | +#define tlbw_use_hazard() \ |
| 26832 | + __asm__ __volatile__( \ |
| 26833 | + ".set noreorder\n\t" \ |
| 26834 | + "nop; nop; nop; nop; nop; nop;\n\t" \ |
| 26835 | + ".set reorder\n\t") |
| 26836 | + |
| 26837 | #endif |
| 26838 | |
| 26839 | +/* |
| 26840 | + * mtc0->mfc0 hazard |
| 26841 | + * The 24K has a 2 cycle mtc0/mfc0 execution hazard. |
| 26842 | + * It is a MIPS32R2 processor so ehb will clear the hazard. |
| 26843 | + */ |
| 26844 | + |
| 26845 | +#ifdef CONFIG_CPU_MIPSR2 |
| 26846 | +/* |
| 26847 | + * Use a macro for ehb unless explicit support for MIPSR2 is enabled |
| 26848 | + */ |
| 26849 | +__asm__( |
| 26850 | + " .macro ehb \n\t" |
| 26851 | + " sll $0, $0, 3 \n\t" |
| 26852 | + " .endm \n\t" |
| 26853 | + " \n\t" |
| 26854 | + " .macro\tirq_enable_hazard \n\t" |
| 26855 | + " ehb \n\t" |
| 26856 | + " .endm \n\t" |
| 26857 | + " \n\t" |
| 26858 | + " .macro\tirq_disable_hazard \n\t" |
| 26859 | + " ehb \n\t" |
| 26860 | + " .endm"); |
| 26861 | + |
| 26862 | +#define irq_enable_hazard() \ |
| 26863 | + __asm__ __volatile__( \ |
| 26864 | + "ehb\t\t\t\t# irq_enable_hazard") |
| 26865 | + |
| 26866 | +#define irq_disable_hazard() \ |
| 26867 | + __asm__ __volatile__( \ |
| 26868 | + "ehb\t\t\t\t# irq_disable_hazard") |
| 26869 | + |
| 26870 | +#elif defined(CONFIG_CPU_R10000) |
| 26871 | + |
| 26872 | +/* |
| 26873 | + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
| 26874 | + */ |
| 26875 | + |
| 26876 | +__asm__( |
| 26877 | + " .macro\tirq_enable_hazard \n\t" |
| 26878 | + " .endm \n\t" |
| 26879 | + " \n\t" |
| 26880 | + " .macro\tirq_disable_hazard \n\t" |
| 26881 | + " .endm"); |
| 26882 | + |
| 26883 | +#define irq_enable_hazard() do { } while (0) |
| 26884 | +#define irq_disable_hazard() do { } while (0) |
| 26885 | + |
| 26886 | +#else |
| 26887 | + |
| 26888 | +/* |
| 26889 | + * Default for classic MIPS processors. Assume worst case hazards but don't |
| 26890 | + * care about the irq_enable_hazard - sooner or later the hardware will |
| 26891 | + * enable it and we don't care when exactly. |
| 26892 | + */ |
| 26893 | + |
| 26894 | +__asm__( |
| 26895 | + " .macro _ssnop \n\t" |
| 26896 | + " sll $0, $2, 1 \n\t" |
| 26897 | + " .endm \n\t" |
| 26898 | + " \n\t" |
| 26899 | + " # \n\t" |
| 26900 | + " # There is a hazard but we do not care \n\t" |
| 26901 | + " # \n\t" |
| 26902 | + " .macro\tirq_enable_hazard \n\t" |
| 26903 | + " .endm \n\t" |
| 26904 | + " \n\t" |
| 26905 | + " .macro\tirq_disable_hazard \n\t" |
| 26906 | + " _ssnop; _ssnop; _ssnop \n\t" |
| 26907 | + " .endm"); |
| 26908 | + |
| 26909 | +#define irq_enable_hazard() do { } while (0) |
| 26910 | +#define irq_disable_hazard() \ |
| 26911 | + __asm__ __volatile__( \ |
| 26912 | + "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") |
| 26913 | + |
| 26914 | #endif |
| 26915 | |
| 26916 | +#endif /* __ASSEMBLY__ */ |
| 26917 | + |
| 26918 | #endif /* _ASM_HAZARDS_H */ |
| 26919 | --- a/include/asm-mips64/ide.h |
| 26920 | +++ b/include/asm-mips64/ide.h |
| 26921 | @@ -32,12 +32,12 @@ struct ide_ops { |
| 26922 | |
| 26923 | extern struct ide_ops *ide_ops; |
| 26924 | |
| 26925 | -static __inline__ int ide_default_irq(ide_ioreg_t base) |
| 26926 | +static inline int ide_default_irq(ide_ioreg_t base) |
| 26927 | { |
| 26928 | return ide_ops->ide_default_irq(base); |
| 26929 | } |
| 26930 | |
| 26931 | -static __inline__ ide_ioreg_t ide_default_io_base(int index) |
| 26932 | +static inline ide_ioreg_t ide_default_io_base(int index) |
| 26933 | { |
| 26934 | return ide_ops->ide_default_io_base(index); |
| 26935 | } |
| 26936 | @@ -48,7 +48,7 @@ static inline void ide_init_hwif_ports(h |
| 26937 | ide_ops->ide_init_hwif_ports(hw, data_port, ctrl_port, irq); |
| 26938 | } |
| 26939 | |
| 26940 | -static __inline__ void ide_init_default_hwifs(void) |
| 26941 | +static inline void ide_init_default_hwifs(void) |
| 26942 | { |
| 26943 | #ifndef CONFIG_BLK_DEV_IDEPCI |
| 26944 | hw_regs_t hw; |
| 26945 | @@ -68,7 +68,89 @@ static __inline__ void ide_init_default_ |
| 26946 | #define ide_ack_intr(hwif) ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1) |
| 26947 | #endif |
| 26948 | |
| 26949 | -#include <asm-generic/ide_iops.h> |
| 26950 | +/* MIPS port and memory-mapped I/O string operations. */ |
| 26951 | + |
| 26952 | +static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) |
| 26953 | +{ |
| 26954 | + if (cpu_has_dc_aliases) { |
| 26955 | + unsigned long end = addr + size; |
| 26956 | + for (; addr < end; addr += PAGE_SIZE) |
| 26957 | + flush_dcache_page(virt_to_page(addr)); |
| 26958 | + } |
| 26959 | +} |
| 26960 | + |
| 26961 | +static inline void __ide_insw(unsigned long port, void *addr, |
| 26962 | + unsigned int count) |
| 26963 | +{ |
| 26964 | + insw(port, addr, count); |
| 26965 | + __ide_flush_dcache_range((unsigned long)addr, count * 2); |
| 26966 | +} |
| 26967 | + |
| 26968 | +static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) |
| 26969 | +{ |
| 26970 | + insl(port, addr, count); |
| 26971 | + __ide_flush_dcache_range((unsigned long)addr, count * 4); |
| 26972 | +} |
| 26973 | + |
| 26974 | +static inline void __ide_outsw(unsigned long port, const void *addr, |
| 26975 | + unsigned long count) |
| 26976 | +{ |
| 26977 | + outsw(port, addr, count); |
| 26978 | + __ide_flush_dcache_range((unsigned long)addr, count * 2); |
| 26979 | +} |
| 26980 | + |
| 26981 | +static inline void __ide_outsl(unsigned long port, const void *addr, |
| 26982 | + unsigned long count) |
| 26983 | +{ |
| 26984 | + outsl(port, addr, count); |
| 26985 | + __ide_flush_dcache_range((unsigned long)addr, count * 4); |
| 26986 | +} |
| 26987 | + |
| 26988 | +static inline void __ide_mm_insw(unsigned long port, void *addr, u32 count) |
| 26989 | +{ |
| 26990 | + unsigned long start = (unsigned long) addr; |
| 26991 | + |
| 26992 | + while (count--) { |
| 26993 | + *(u16 *)addr = readw(port); |
| 26994 | + addr += 2; |
| 26995 | + } |
| 26996 | + __ide_flush_dcache_range(start, count * 2); |
| 26997 | +} |
| 26998 | + |
| 26999 | +static inline void __ide_mm_insl(unsigned long port, void *addr, u32 count) |
| 27000 | +{ |
| 27001 | + unsigned long start = (unsigned long) addr; |
| 27002 | + |
| 27003 | + while (count--) { |
| 27004 | + *(u32 *)addr = readl(port); |
| 27005 | + addr += 4; |
| 27006 | + } |
| 27007 | + __ide_flush_dcache_range(start, count * 4); |
| 27008 | +} |
| 27009 | + |
| 27010 | +static inline void __ide_mm_outsw(unsigned long port, const void *addr, |
| 27011 | + u32 count) |
| 27012 | +{ |
| 27013 | + unsigned long start = (unsigned long) addr; |
| 27014 | + |
| 27015 | + while (count--) { |
| 27016 | + writew(*(u16 *)addr, port); |
| 27017 | + addr += 2; |
| 27018 | + } |
| 27019 | + __ide_flush_dcache_range(start, count * 2); |
| 27020 | +} |
| 27021 | + |
| 27022 | +static inline void __ide_mm_outsl(unsigned long port, const void *addr, |
| 27023 | + u32 count) |
| 27024 | +{ |
| 27025 | + unsigned long start = (unsigned long) addr; |
| 27026 | + |
| 27027 | + while (count--) { |
| 27028 | + writel(*(u32 *)addr, port); |
| 27029 | + addr += 4; |
| 27030 | + } |
| 27031 | + __ide_flush_dcache_range(start, count * 4); |
| 27032 | +} |
| 27033 | |
| 27034 | #endif /* __KERNEL__ */ |
| 27035 | |
| 27036 | --- a/include/asm-mips64/io.h |
| 27037 | +++ b/include/asm-mips64/io.h |
| 27038 | @@ -414,7 +414,8 @@ static inline unsigned int inl_p(unsigne |
| 27039 | return __ioswab32(__val); |
| 27040 | } |
| 27041 | |
| 27042 | -static inline void __outsb(unsigned long port, void *addr, unsigned int count) |
| 27043 | +static inline void __outsb(unsigned long port, const void *addr, |
| 27044 | + unsigned int count) |
| 27045 | { |
| 27046 | while (count--) { |
| 27047 | outb(*(u8 *)addr, port); |
| 27048 | @@ -430,7 +431,8 @@ static inline void __insb(unsigned long |
| 27049 | } |
| 27050 | } |
| 27051 | |
| 27052 | -static inline void __outsw(unsigned long port, void *addr, unsigned int count) |
| 27053 | +static inline void __outsw(unsigned long port, const void *addr, |
| 27054 | + unsigned int count) |
| 27055 | { |
| 27056 | while (count--) { |
| 27057 | outw(*(u16 *)addr, port); |
| 27058 | @@ -446,7 +448,8 @@ static inline void __insw(unsigned long |
| 27059 | } |
| 27060 | } |
| 27061 | |
| 27062 | -static inline void __outsl(unsigned long port, void *addr, unsigned int count) |
| 27063 | +static inline void __outsl(unsigned long port, const void *addr, |
| 27064 | + unsigned int count) |
| 27065 | { |
| 27066 | while (count--) { |
| 27067 | outl(*(u32 *)addr, port); |
| 27068 | --- a/include/asm-mips64/mipsregs.h |
| 27069 | +++ b/include/asm-mips64/mipsregs.h |
| 27070 | @@ -757,10 +757,18 @@ do { \ |
| 27071 | #define read_c0_config1() __read_32bit_c0_register($16, 1) |
| 27072 | #define read_c0_config2() __read_32bit_c0_register($16, 2) |
| 27073 | #define read_c0_config3() __read_32bit_c0_register($16, 3) |
| 27074 | +#define read_c0_config4() __read_32bit_c0_register($16, 4) |
| 27075 | +#define read_c0_config5() __read_32bit_c0_register($16, 5) |
| 27076 | +#define read_c0_config6() __read_32bit_c0_register($16, 6) |
| 27077 | +#define read_c0_config7() __read_32bit_c0_register($16, 7) |
| 27078 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
| 27079 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) |
| 27080 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) |
| 27081 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) |
| 27082 | +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
| 27083 | +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) |
| 27084 | +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) |
| 27085 | +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) |
| 27086 | |
| 27087 | /* |
| 27088 | * The WatchLo register. There may be upto 8 of them. |
| 27089 | @@ -856,42 +864,34 @@ do { \ |
| 27090 | */ |
| 27091 | static inline void tlb_probe(void) |
| 27092 | { |
| 27093 | - rm9000_tlb_hazard(); |
| 27094 | __asm__ __volatile__( |
| 27095 | ".set noreorder\n\t" |
| 27096 | "tlbp\n\t" |
| 27097 | ".set reorder"); |
| 27098 | - rm9000_tlb_hazard(); |
| 27099 | } |
| 27100 | |
| 27101 | static inline void tlb_read(void) |
| 27102 | { |
| 27103 | - rm9000_tlb_hazard(); |
| 27104 | __asm__ __volatile__( |
| 27105 | ".set noreorder\n\t" |
| 27106 | "tlbr\n\t" |
| 27107 | ".set reorder"); |
| 27108 | - rm9000_tlb_hazard(); |
| 27109 | } |
| 27110 | |
| 27111 | static inline void tlb_write_indexed(void) |
| 27112 | { |
| 27113 | - rm9000_tlb_hazard(); |
| 27114 | __asm__ __volatile__( |
| 27115 | ".set noreorder\n\t" |
| 27116 | "tlbwi\n\t" |
| 27117 | ".set reorder"); |
| 27118 | - rm9000_tlb_hazard(); |
| 27119 | } |
| 27120 | |
| 27121 | static inline void tlb_write_random(void) |
| 27122 | { |
| 27123 | - rm9000_tlb_hazard(); |
| 27124 | __asm__ __volatile__( |
| 27125 | ".set noreorder\n\t" |
| 27126 | "tlbwr\n\t" |
| 27127 | ".set reorder"); |
| 27128 | - rm9000_tlb_hazard(); |
| 27129 | } |
| 27130 | |
| 27131 | /* |
| 27132 | --- a/include/asm-mips64/reg.h |
| 27133 | +++ b/include/asm-mips64/reg.h |
| 27134 | @@ -46,6 +46,9 @@ |
| 27135 | /* |
| 27136 | * k0/k1 unsaved |
| 27137 | */ |
| 27138 | +#define EF_REG26 26 |
| 27139 | +#define EF_REG27 27 |
| 27140 | + |
| 27141 | #define EF_REG28 28 |
| 27142 | #define EF_REG29 29 |
| 27143 | #define EF_REG30 30 |
| 27144 | --- a/include/asm-mips64/sgi/hpc3.h |
| 27145 | +++ b/include/asm-mips64/sgi/hpc3.h |
| 27146 | @@ -128,26 +128,26 @@ struct hpc3_ethregs { |
| 27147 | volatile u32 rx_gfptr; /* current GIO fifo ptr */ |
| 27148 | volatile u32 rx_dfptr; /* current device fifo ptr */ |
| 27149 | u32 _unused1; /* padding */ |
| 27150 | - volatile u32 rx_reset; /* reset register */ |
| 27151 | -#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ |
| 27152 | -#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ |
| 27153 | -#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ |
| 27154 | - |
| 27155 | - volatile u32 rx_dconfig; /* DMA configuration register */ |
| 27156 | -#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ |
| 27157 | -#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ |
| 27158 | -#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ |
| 27159 | -#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ |
| 27160 | -#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ |
| 27161 | -#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ |
| 27162 | -#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ |
| 27163 | -#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ |
| 27164 | - |
| 27165 | - volatile u32 rx_pconfig; /* PIO configuration register */ |
| 27166 | -#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ |
| 27167 | -#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ |
| 27168 | -#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ |
| 27169 | -#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ |
| 27170 | + volatile u32 reset; /* reset register */ |
| 27171 | +#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */ |
| 27172 | +#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */ |
| 27173 | +#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ |
| 27174 | + |
| 27175 | + volatile u32 dconfig; /* DMA configuration register */ |
| 27176 | +#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ |
| 27177 | +#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ |
| 27178 | +#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ |
| 27179 | +#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ |
| 27180 | +#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ |
| 27181 | +#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ |
| 27182 | +#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ |
| 27183 | +#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ |
| 27184 | + |
| 27185 | + volatile u32 pconfig; /* PIO configuration register */ |
| 27186 | +#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ |
| 27187 | +#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ |
| 27188 | +#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ |
| 27189 | +#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ |
| 27190 | |
| 27191 | u32 _unused2[0x1000/4 - 8]; /* padding */ |
| 27192 | |
| 27193 | @@ -221,7 +221,7 @@ struct hpc3_regs { |
| 27194 | #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ |
| 27195 | |
| 27196 | u32 _unused1[0x14000/4 - 5]; /* padding */ |
| 27197 | - |
| 27198 | + |
| 27199 | /* Now direct PIO per-HPC3 peripheral access to external regs. */ |
| 27200 | volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ |
| 27201 | u32 _unused2[0x7c00/4]; |
| 27202 | @@ -304,7 +304,7 @@ struct hpc3_regs { |
| 27203 | volatile u32 bbram[8192-50-14]; /* Battery backed ram */ |
| 27204 | }; |
| 27205 | |
| 27206 | -/* |
| 27207 | +/* |
| 27208 | * It is possible to have two HPC3's within the address space on |
| 27209 | * one machine, though only having one is more likely on an Indy. |
| 27210 | */ |
| 27211 | --- a/include/asm-mips64/sn/nmi.h |
| 27212 | +++ b/include/asm-mips64/sn/nmi.h |
| 27213 | @@ -8,7 +8,7 @@ |
| 27214 | #ifndef __ASM_SN_NMI_H |
| 27215 | #define __ASM_SN_NMI_H |
| 27216 | |
| 27217 | -#ident "$Revision: 1.2.4.2 $" |
| 27218 | +#ident "$Revision: 1.2.4.1 $" |
| 27219 | |
| 27220 | #include <asm/sn/addrs.h> |
| 27221 | |
| 27222 | --- a/include/asm-mips64/unistd.h |
| 27223 | +++ b/include/asm-mips64/unistd.h |
| 27224 | @@ -760,7 +760,7 @@ type name(void) \ |
| 27225 | if (__a3 == 0) \ |
| 27226 | return (type) __v0; \ |
| 27227 | errno = __v0; \ |
| 27228 | - return -1; \ |
| 27229 | + return (type)-1; \ |
| 27230 | } |
| 27231 | |
| 27232 | /* |
| 27233 | @@ -788,7 +788,7 @@ type name(atype a) \ |
| 27234 | if (__a3 == 0) \ |
| 27235 | return (type) __v0; \ |
| 27236 | errno = __v0; \ |
| 27237 | - return -1; \ |
| 27238 | + return (type)-1; \ |
| 27239 | } |
| 27240 | |
| 27241 | #define _syscall2(type,name,atype,a,btype,b) \ |
| 27242 | @@ -813,7 +813,7 @@ type name(atype a, btype b) \ |
| 27243 | if (__a3 == 0) \ |
| 27244 | return (type) __v0; \ |
| 27245 | errno = __v0; \ |
| 27246 | - return -1; \ |
| 27247 | + return (type)-1; \ |
| 27248 | } |
| 27249 | |
| 27250 | #define _syscall3(type,name,atype,a,btype,b,ctype,c) \ |
| 27251 | @@ -839,7 +839,7 @@ type name(atype a, btype b, ctype c) \ |
| 27252 | if (__a3 == 0) \ |
| 27253 | return (type) __v0; \ |
| 27254 | errno = __v0; \ |
| 27255 | - return -1; \ |
| 27256 | + return (type)-1; \ |
| 27257 | } |
| 27258 | |
| 27259 | #define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ |
| 27260 | @@ -865,7 +865,7 @@ type name(atype a, btype b, ctype c, dty |
| 27261 | if (__a3 == 0) \ |
| 27262 | return (type) __v0; \ |
| 27263 | errno = __v0; \ |
| 27264 | - return -1; \ |
| 27265 | + return (type)-1; \ |
| 27266 | } |
| 27267 | |
| 27268 | #if (_MIPS_SIM == _MIPS_SIM_ABI32) |
| 27269 | @@ -902,7 +902,7 @@ type name(atype a, btype b, ctype c, dty |
| 27270 | if (__a3 == 0) \ |
| 27271 | return (type) __v0; \ |
| 27272 | errno = __v0; \ |
| 27273 | - return -1; \ |
| 27274 | + return (type)-1; \ |
| 27275 | } |
| 27276 | |
| 27277 | #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ |
| 27278 | @@ -935,7 +935,7 @@ type name(atype a, btype b, ctype c, dty |
| 27279 | if (__a3 == 0) \ |
| 27280 | return (type) __v0; \ |
| 27281 | errno = __v0; \ |
| 27282 | - return -1; \ |
| 27283 | + return (type)-1; \ |
| 27284 | } |
| 27285 | |
| 27286 | #endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */ |
| 27287 | @@ -966,7 +966,7 @@ type name (atype a,btype b,ctype c,dtype |
| 27288 | if (__a3 == 0) \ |
| 27289 | return (type) __v0; \ |
| 27290 | errno = __v0; \ |
| 27291 | - return -1; \ |
| 27292 | + return (type)-1; \ |
| 27293 | } |
| 27294 | |
| 27295 | #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ |
| 27296 | @@ -995,7 +995,7 @@ type name (atype a,btype b,ctype c,dtype |
| 27297 | if (__a3 == 0) \ |
| 27298 | return (type) __v0; \ |
| 27299 | errno = __v0; \ |
| 27300 | - return -1; \ |
| 27301 | + return (type)-1; \ |
| 27302 | } |
| 27303 | |
| 27304 | #endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ |
| 27305 | --- a/include/asm-ppc/param.h |
| 27306 | +++ b/include/asm-ppc/param.h |
| 27307 | @@ -3,6 +3,9 @@ |
| 27308 | |
| 27309 | #ifndef HZ |
| 27310 | #define HZ 100 |
| 27311 | +#ifdef __KERNEL__ |
| 27312 | +#define hz_to_std(a) (a) |
| 27313 | +#endif |
| 27314 | #endif |
| 27315 | |
| 27316 | #define EXEC_PAGESIZE 4096 |
| 27317 | --- a/include/asm-s390/param.h |
| 27318 | +++ b/include/asm-s390/param.h |
| 27319 | @@ -11,6 +11,9 @@ |
| 27320 | |
| 27321 | #ifndef HZ |
| 27322 | #define HZ 100 |
| 27323 | +#ifdef __KERNEL__ |
| 27324 | +#define hz_to_std(a) (a) |
| 27325 | +#endif |
| 27326 | #endif |
| 27327 | |
| 27328 | #define EXEC_PAGESIZE 4096 |
| 27329 | --- a/include/asm-sh/param.h |
| 27330 | +++ b/include/asm-sh/param.h |
| 27331 | @@ -3,6 +3,9 @@ |
| 27332 | |
| 27333 | #ifndef HZ |
| 27334 | #define HZ 100 |
| 27335 | +#ifdef __KERNEL__ |
| 27336 | +#define hz_to_std(a) (a) |
| 27337 | +#endif |
| 27338 | #endif |
| 27339 | |
| 27340 | #define EXEC_PAGESIZE 4096 |
| 27341 | --- a/include/asm-sparc/param.h |
| 27342 | +++ b/include/asm-sparc/param.h |
| 27343 | @@ -4,6 +4,9 @@ |
| 27344 | |
| 27345 | #ifndef HZ |
| 27346 | #define HZ 100 |
| 27347 | +#ifdef __KERNEL__ |
| 27348 | +#define hz_to_std(a) (a) |
| 27349 | +#endif |
| 27350 | #endif |
| 27351 | |
| 27352 | #define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */ |
| 27353 | --- a/include/asm-sparc64/param.h |
| 27354 | +++ b/include/asm-sparc64/param.h |
| 27355 | @@ -4,6 +4,9 @@ |
| 27356 | |
| 27357 | #ifndef HZ |
| 27358 | #define HZ 100 |
| 27359 | +#ifdef __KERNEL__ |
| 27360 | +#define hz_to_std(a) (a) |
| 27361 | +#endif |
| 27362 | #endif |
| 27363 | |
| 27364 | #define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */ |
| 27365 | --- /dev/null |
| 27366 | +++ b/include/linux/i2c-algo-au1550.h |
| 27367 | @@ -0,0 +1,31 @@ |
| 27368 | +/* |
| 27369 | + * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> |
| 27370 | + * |
| 27371 | + * This program is free software; you can redistribute it and/or modify |
| 27372 | + * it under the terms of the GNU General Public License as published by |
| 27373 | + * the Free Software Foundation; either version 2 of the License, or |
| 27374 | + * (at your option) any later version. |
| 27375 | + * |
| 27376 | + * This program is distributed in the hope that it will be useful, |
| 27377 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27378 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 27379 | + * GNU General Public License for more details. |
| 27380 | + * |
| 27381 | + * You should have received a copy of the GNU General Public License |
| 27382 | + * along with this program; if not, write to the Free Software |
| 27383 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 27384 | + */ |
| 27385 | + |
| 27386 | +#ifndef I2C_ALGO_AU1550_H |
| 27387 | +#define I2C_ALGO_AU1550_H 1 |
| 27388 | + |
| 27389 | +struct i2c_algo_au1550_data { |
| 27390 | + u32 psc_base; |
| 27391 | + int xfer_timeout; |
| 27392 | + int ack_timeout; |
| 27393 | +}; |
| 27394 | + |
| 27395 | +int i2c_au1550_add_bus(struct i2c_adapter *); |
| 27396 | +int i2c_au1550_del_bus(struct i2c_adapter *); |
| 27397 | + |
| 27398 | +#endif /* I2C_ALGO_AU1550_H */ |
| 27399 | --- a/include/linux/i2c-id.h |
| 27400 | +++ b/include/linux/i2c-id.h |
| 27401 | @@ -155,6 +155,8 @@ |
| 27402 | #define I2C_ALGO_SIBYTE 0x150000 /* Broadcom SiByte SOCs */ |
| 27403 | #define I2C_ALGO_SGI 0x160000 /* SGI algorithm */ |
| 27404 | |
| 27405 | +#define I2C_ALGO_AU1550 0x140000 /* Alchemy Au1550 PSC */ |
| 27406 | + |
| 27407 | #define I2C_ALGO_EXP 0x800000 /* experimental */ |
| 27408 | |
| 27409 | #define I2C_ALGO_MASK 0xff0000 /* Mask for algorithms */ |
| 27410 | @@ -203,6 +205,9 @@ |
| 27411 | #define I2C_HW_SGI_VINO 0x00 |
| 27412 | #define I2C_HW_SGI_MACE 0x01 |
| 27413 | |
| 27414 | +/* --- Au1550 PSC adapters */ |
| 27415 | +#define I2C_HW_AU1550_PSC 0x00 |
| 27416 | + |
| 27417 | /* --- SMBus only adapters */ |
| 27418 | #define I2C_HW_SMBUS_PIIX4 0x00 |
| 27419 | #define I2C_HW_SMBUS_ALI15X3 0x01 |
| 27420 | --- a/include/linux/sched.h |
| 27421 | +++ b/include/linux/sched.h |
| 27422 | @@ -619,6 +619,10 @@ asmlinkage long sys_wait4(pid_t pid,unsi |
| 27423 | extern int in_group_p(gid_t); |
| 27424 | extern int in_egroup_p(gid_t); |
| 27425 | |
| 27426 | +extern ATTRIB_NORET void cpu_idle(void); |
| 27427 | + |
| 27428 | +extern void release_task(struct task_struct * p); |
| 27429 | + |
| 27430 | extern void proc_caches_init(void); |
| 27431 | extern void flush_signals(struct task_struct *); |
| 27432 | extern void flush_signal_handlers(struct task_struct *); |
| 27433 | --- a/include/linux/serial.h |
| 27434 | +++ b/include/linux/serial.h |
| 27435 | @@ -75,7 +75,8 @@ struct serial_struct { |
| 27436 | #define PORT_16654 11 |
| 27437 | #define PORT_16850 12 |
| 27438 | #define PORT_RSA 13 /* RSA-DV II/S card */ |
| 27439 | -#define PORT_MAX 13 |
| 27440 | +#define PORT_SB1250 14 |
| 27441 | +#define PORT_MAX 14 |
| 27442 | |
| 27443 | #define SERIAL_IO_PORT 0 |
| 27444 | #define SERIAL_IO_HUB6 1 |
| 27445 | --- a/include/linux/swap.h |
| 27446 | +++ b/include/linux/swap.h |
| 27447 | @@ -1,6 +1,12 @@ |
| 27448 | #ifndef _LINUX_SWAP_H |
| 27449 | #define _LINUX_SWAP_H |
| 27450 | |
| 27451 | +#include <linux/config.h> |
| 27452 | + |
| 27453 | +#define MAX_SWAPFILES 32 |
| 27454 | + |
| 27455 | +#ifdef __KERNEL__ |
| 27456 | + |
| 27457 | #include <linux/spinlock.h> |
| 27458 | #include <asm/page.h> |
| 27459 | |
| 27460 | @@ -8,8 +14,6 @@ |
| 27461 | #define SWAP_FLAG_PRIO_MASK 0x7fff |
| 27462 | #define SWAP_FLAG_PRIO_SHIFT 0 |
| 27463 | |
| 27464 | -#define MAX_SWAPFILES 32 |
| 27465 | - |
| 27466 | /* |
| 27467 | * Magic header for a swap area. The first part of the union is |
| 27468 | * what the swap magic looks like for the old (limited to 128MB) |
| 27469 | @@ -39,8 +43,6 @@ union swap_header { |
| 27470 | } info; |
| 27471 | }; |
| 27472 | |
| 27473 | -#ifdef __KERNEL__ |
| 27474 | - |
| 27475 | /* |
| 27476 | * Max bad pages in the new format.. |
| 27477 | */ |
| 27478 | --- a/include/video/newport.h |
| 27479 | +++ b/include/video/newport.h |
| 27480 | @@ -291,8 +291,6 @@ struct newport_regs { |
| 27481 | unsigned int _unused2[0x1ef]; |
| 27482 | struct newport_cregs cgo; |
| 27483 | }; |
| 27484 | -extern struct newport_regs *npregs; |
| 27485 | - |
| 27486 | |
| 27487 | typedef struct { |
| 27488 | unsigned int drawmode1; |
| 27489 | @@ -450,38 +448,26 @@ static __inline__ void newport_cmap_setr |
| 27490 | |
| 27491 | /* Miscellaneous NEWPORT routines. */ |
| 27492 | #define BUSY_TIMEOUT 100000 |
| 27493 | -static __inline__ int newport_wait(void) |
| 27494 | +static __inline__ int newport_wait(struct newport_regs *regs) |
| 27495 | { |
| 27496 | - int i = 0; |
| 27497 | + int t = BUSY_TIMEOUT; |
| 27498 | |
| 27499 | - while(i < BUSY_TIMEOUT) |
| 27500 | - if(!(npregs->cset.status & NPORT_STAT_GBUSY)) |
| 27501 | + while (t--) |
| 27502 | + if (!(regs->cset.status & NPORT_STAT_GBUSY)) |
| 27503 | break; |
| 27504 | - if(i == BUSY_TIMEOUT) |
| 27505 | - return 1; |
| 27506 | - return 0; |
| 27507 | + return !t; |
| 27508 | } |
| 27509 | |
| 27510 | -static __inline__ int newport_bfwait(void) |
| 27511 | +static __inline__ int newport_bfwait(struct newport_regs *regs) |
| 27512 | { |
| 27513 | - int i = 0; |
| 27514 | + int t = BUSY_TIMEOUT; |
| 27515 | |
| 27516 | - while(i < BUSY_TIMEOUT) |
| 27517 | - if(!(npregs->cset.status & NPORT_STAT_BBUSY)) |
| 27518 | + while (t--) |
| 27519 | + if(!(regs->cset.status & NPORT_STAT_BBUSY)) |
| 27520 | break; |
| 27521 | - if(i == BUSY_TIMEOUT) |
| 27522 | - return 1; |
| 27523 | - return 0; |
| 27524 | + return !t; |
| 27525 | } |
| 27526 | |
| 27527 | -/* newport.c and cons_newport.c routines */ |
| 27528 | -extern struct graphics_ops *newport_probe (int, const char **); |
| 27529 | - |
| 27530 | -void newport_save (void *); |
| 27531 | -void newport_restore (void *); |
| 27532 | -void newport_reset (void); |
| 27533 | -int newport_ioctl (int card, int cmd, unsigned long arg); |
| 27534 | - |
| 27535 | /* |
| 27536 | * DCBMODE register defines: |
| 27537 | */ |
| 27538 | @@ -564,7 +550,7 @@ xmap9FIFOWait (struct newport_regs *rex) |
| 27539 | { |
| 27540 | rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | |
| 27541 | DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; |
| 27542 | - newport_bfwait (); |
| 27543 | + newport_bfwait (rex); |
| 27544 | |
| 27545 | while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) |
| 27546 | ; |
| 27547 | --- a/init/main.c |
| 27548 | +++ b/init/main.c |
| 27549 | @@ -296,7 +296,6 @@ static void __init parse_options(char *l |
| 27550 | |
| 27551 | |
| 27552 | extern void setup_arch(char **); |
| 27553 | -extern void cpu_idle(void); |
| 27554 | |
| 27555 | unsigned long wait_init_idle; |
| 27556 | |
| 27557 | --- a/kernel/exit.c |
| 27558 | +++ b/kernel/exit.c |
| 27559 | @@ -26,7 +26,7 @@ extern struct task_struct *child_reaper; |
| 27560 | |
| 27561 | int getrusage(struct task_struct *, int, struct rusage *); |
| 27562 | |
| 27563 | -static void release_task(struct task_struct * p) |
| 27564 | +void release_task(struct task_struct * p) |
| 27565 | { |
| 27566 | if (p != current) { |
| 27567 | #ifdef CONFIG_SMP |
| 27568 | --- a/kernel/signal.c |
| 27569 | +++ b/kernel/signal.c |
| 27570 | @@ -14,6 +14,7 @@ |
| 27571 | #include <linux/init.h> |
| 27572 | #include <linux/sched.h> |
| 27573 | |
| 27574 | +#include <asm/param.h> |
| 27575 | #include <asm/uaccess.h> |
| 27576 | |
| 27577 | /* |
| 27578 | @@ -28,6 +29,14 @@ |
| 27579 | #define SIG_SLAB_DEBUG 0 |
| 27580 | #endif |
| 27581 | |
| 27582 | +#define DEBUG_SIG 0 |
| 27583 | + |
| 27584 | +#if DEBUG_SIG |
| 27585 | +#define SIG_SLAB_DEBUG (SLAB_DEBUG_FREE | SLAB_RED_ZONE /* | SLAB_POISON */) |
| 27586 | +#else |
| 27587 | +#define SIG_SLAB_DEBUG 0 |
| 27588 | +#endif |
| 27589 | + |
| 27590 | static kmem_cache_t *sigqueue_cachep; |
| 27591 | |
| 27592 | atomic_t nr_queued_signals; |
| 27593 | @@ -270,6 +279,11 @@ printk("SIG dequeue (%s:%d): %d ", curre |
| 27594 | signal_pending(current)); |
| 27595 | #endif |
| 27596 | |
| 27597 | +#if DEBUG_SIG |
| 27598 | +printk("SIG dequeue (%s:%d): %d ", current->comm, current->pid, |
| 27599 | + signal_pending(current)); |
| 27600 | +#endif |
| 27601 | + |
| 27602 | sig = next_signal(current, mask); |
| 27603 | if (sig) { |
| 27604 | if (current->notifier) { |
| 27605 | @@ -293,6 +307,10 @@ printk("SIG dequeue (%s:%d): %d ", curre |
| 27606 | printk(" %d -> %d\n", signal_pending(current), sig); |
| 27607 | #endif |
| 27608 | |
| 27609 | +#if DEBUG_SIG |
| 27610 | +printk(" %d -> %d\n", signal_pending(current), sig); |
| 27611 | +#endif |
| 27612 | + |
| 27613 | return sig; |
| 27614 | } |
| 27615 | |
| 27616 | @@ -551,6 +569,11 @@ send_sig_info(int sig, struct siginfo *i |
| 27617 | printk("SIG queue (%s:%d): %d ", t->comm, t->pid, sig); |
| 27618 | #endif |
| 27619 | |
| 27620 | + |
| 27621 | +#if DEBUG_SIG |
| 27622 | +printk("SIG queue (%s:%d): %d ", t->comm, t->pid, sig); |
| 27623 | +#endif |
| 27624 | + |
| 27625 | ret = -EINVAL; |
| 27626 | if (sig < 0 || sig > _NSIG) |
| 27627 | goto out_nolock; |
| 27628 | @@ -789,8 +812,8 @@ void do_notify_parent(struct task_struct |
| 27629 | info.si_uid = tsk->uid; |
| 27630 | |
| 27631 | /* FIXME: find out whether or not this is supposed to be c*time. */ |
| 27632 | - info.si_utime = tsk->times.tms_utime; |
| 27633 | - info.si_stime = tsk->times.tms_stime; |
| 27634 | + info.si_utime = hz_to_std(tsk->times.tms_utime); |
| 27635 | + info.si_stime = hz_to_std(tsk->times.tms_stime); |
| 27636 | |
| 27637 | status = tsk->exit_code & 0x7f; |
| 27638 | why = SI_KERNEL; /* shouldn't happen */ |
| 27639 | --- a/kernel/sys.c |
| 27640 | +++ b/kernel/sys.c |
| 27641 | @@ -801,16 +801,23 @@ asmlinkage long sys_setfsgid(gid_t gid) |
| 27642 | |
| 27643 | asmlinkage long sys_times(struct tms * tbuf) |
| 27644 | { |
| 27645 | + struct tms temp; |
| 27646 | + |
| 27647 | /* |
| 27648 | * In the SMP world we might just be unlucky and have one of |
| 27649 | * the times increment as we use it. Since the value is an |
| 27650 | * atomically safe type this is just fine. Conceptually its |
| 27651 | * as if the syscall took an instant longer to occur. |
| 27652 | */ |
| 27653 | - if (tbuf) |
| 27654 | - if (copy_to_user(tbuf, ¤t->times, sizeof(struct tms))) |
| 27655 | + if (tbuf) { |
| 27656 | + temp.tms_utime = hz_to_std(current->times.tms_utime); |
| 27657 | + temp.tms_stime = hz_to_std(current->times.tms_stime); |
| 27658 | + temp.tms_cutime = hz_to_std(current->times.tms_cutime); |
| 27659 | + temp.tms_cstime = hz_to_std(current->times.tms_cstime); |
| 27660 | + if (copy_to_user(tbuf, &temp, sizeof(struct tms))) |
| 27661 | return -EFAULT; |
| 27662 | - return jiffies; |
| 27663 | + } |
| 27664 | + return hz_to_std(jiffies); |
| 27665 | } |
| 27666 | |
| 27667 | /* |
| 27668 | --- a/lib/Makefile |
| 27669 | +++ b/lib/Makefile |
| 27670 | @@ -27,6 +27,7 @@ obj-$(CONFIG_CRC32) += crc32.o |
| 27671 | subdir-$(CONFIG_ZLIB_INFLATE) += zlib_inflate |
| 27672 | subdir-$(CONFIG_ZLIB_DEFLATE) += zlib_deflate |
| 27673 | |
| 27674 | +-include $(TOPDIR)/arch/$(ARCH)/Makefile.lib |
| 27675 | include $(TOPDIR)/drivers/net/Makefile.lib |
| 27676 | include $(TOPDIR)/drivers/usb/Makefile.lib |
| 27677 | include $(TOPDIR)/drivers/bluetooth/Makefile.lib |
| 27678 | --- a/Makefile |
| 27679 | +++ b/Makefile |
| 27680 | @@ -476,10 +476,11 @@ mrproper: clean archmrproper |
| 27681 | $(MAKE) -C Documentation/DocBook mrproper |
| 27682 | |
| 27683 | distclean: mrproper |
| 27684 | - rm -f core `find . \( -not -type d \) -and \ |
| 27685 | - \( -name '*.orig' -o -name '*.rej' -o -name '*~' \ |
| 27686 | - -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \ |
| 27687 | - -o -name '.*.rej' -o -name '.SUMS' -o -size 0 \) -type f -print` TAGS tags cscope* |
| 27688 | + find . \( -not -type d \) -and \ |
| 27689 | + \( -name core -o -name '*.orig' -o -name '*.rej' \ |
| 27690 | + -o -name '*~' -o -name '*.bak' -o -name '#*#' \ |
| 27691 | + -o -name '.*.rej' -o -name '.SUMS' -o -size 0 \ |
| 27692 | + -o -name TAGS -o -name tags -o -name 'cscope*' \) -print | env -i xargs rm -f |
| 27693 | |
| 27694 | backup: mrproper |
| 27695 | cd .. && tar cf - linux/ | gzip -9 > backup.gz |
| 27696 | @@ -506,7 +507,7 @@ mandocs: |
| 27697 | $(MAKE) -C Documentation/DocBook man |
| 27698 | |
| 27699 | sums: |
| 27700 | - find . -type f -print | sort | xargs sum > .SUMS |
| 27701 | + find . -type f -print | sort | env -i xargs sum > .SUMS |
| 27702 | |
| 27703 | dep-files: scripts/mkdep archdep include/linux/version.h |
| 27704 | rm -f .depend .hdepend |
| 27705 | |
