Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8306.c

1/*
2 * rtl8306.c: RTL8306S switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/if.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/list.h>
20#include <linux/if_ether.h>
21#include <linux/skbuff.h>
22#include <linux/netdevice.h>
23#include <linux/netlink.h>
24#include <net/genetlink.h>
25#include <linux/switch.h>
26#include <linux/delay.h>
27#include <linux/phy.h>
28
29//#define DEBUG 1
30
31/* Global (PHY0) */
32#define RTL8306_REG_PAGE 16
33#define RTL8306_REG_PAGE_LO (1 << 15)
34#define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
35
36#define RTL8306_NUM_VLANS 16
37#define RTL8306_NUM_PORTS 6
38#define RTL8306_PORT_CPU 5
39#define RTL8306_NUM_PAGES 4
40#define RTL8306_NUM_REGS 32
41
42#define RTL_NAME_S "RTL8306S"
43#define RTL_NAME_SD "RTL8306SD"
44#define RTL_NAME_SDM "RTL8306SDM"
45#define RTL_NAME_UNKNOWN "RTL8306(unknown)"
46
47#define RTL8306_MAGIC 0x8306
48
49static LIST_HEAD(phydevs);
50
51struct rtl_priv {
52    struct list_head list;
53    struct switch_dev dev;
54    int page;
55    int type;
56    int do_cpu;
57    struct mii_bus *bus;
58    char hwname[sizeof(RTL_NAME_UNKNOWN)];
59};
60
61struct rtl_phyregs {
62    int nway;
63    int speed;
64    int duplex;
65};
66
67#define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
68
69enum {
70    RTL_TYPE_S,
71    RTL_TYPE_SD,
72    RTL_TYPE_SDM,
73};
74
75struct rtl_reg {
76    int page;
77    int phy;
78    int reg;
79    int bits;
80    int shift;
81    int inverted;
82};
83
84#define RTL_VLAN_REGOFS(name) \
85    (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
86
87#define RTL_PORT_REGOFS(name) \
88    (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
89
90#define RTL_PORT_REG(id, reg) \
91    (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
92
93#define RTL_VLAN_REG(id, reg) \
94    (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
95
96#define RTL_GLOBAL_REGATTR(reg) \
97    .id = RTL_REG_##reg, \
98    .type = SWITCH_TYPE_INT, \
99    .ofs = 0, \
100    .set = rtl_attr_set_int, \
101    .get = rtl_attr_get_int
102
103#define RTL_PORT_REGATTR(reg) \
104    .id = RTL_REG_PORT0_##reg, \
105    .type = SWITCH_TYPE_INT, \
106    .ofs = RTL_PORT_REGOFS(reg), \
107    .set = rtl_attr_set_port_int, \
108    .get = rtl_attr_get_port_int
109
110#define RTL_VLAN_REGATTR(reg) \
111    .id = RTL_REG_VLAN0_##reg, \
112    .type = SWITCH_TYPE_INT, \
113    .ofs = RTL_VLAN_REGOFS(reg), \
114    .set = rtl_attr_set_vlan_int, \
115    .get = rtl_attr_get_vlan_int
116
117enum rtl_regidx {
118    RTL_REG_CHIPID,
119    RTL_REG_CHIPVER,
120    RTL_REG_CHIPTYPE,
121    RTL_REG_CPUPORT,
122
123    RTL_REG_EN_CPUPORT,
124    RTL_REG_EN_TAG_OUT,
125    RTL_REG_EN_TAG_CLR,
126    RTL_REG_EN_TAG_IN,
127    RTL_REG_TRAP_CPU,
128    RTL_REG_TRUNK_PORTSEL,
129    RTL_REG_EN_TRUNK,
130    RTL_REG_RESET,
131
132    RTL_REG_VLAN_ENABLE,
133    RTL_REG_VLAN_FILTER,
134    RTL_REG_VLAN_TAG_ONLY,
135    RTL_REG_VLAN_TAG_AWARE,
136#define RTL_VLAN_ENUM(id) \
137    RTL_REG_VLAN##id##_VID, \
138    RTL_REG_VLAN##id##_PORTMASK
139    RTL_VLAN_ENUM(0),
140    RTL_VLAN_ENUM(1),
141    RTL_VLAN_ENUM(2),
142    RTL_VLAN_ENUM(3),
143    RTL_VLAN_ENUM(4),
144    RTL_VLAN_ENUM(5),
145    RTL_VLAN_ENUM(6),
146    RTL_VLAN_ENUM(7),
147    RTL_VLAN_ENUM(8),
148    RTL_VLAN_ENUM(9),
149    RTL_VLAN_ENUM(10),
150    RTL_VLAN_ENUM(11),
151    RTL_VLAN_ENUM(12),
152    RTL_VLAN_ENUM(13),
153    RTL_VLAN_ENUM(14),
154    RTL_VLAN_ENUM(15),
155#define RTL_PORT_ENUM(id) \
156    RTL_REG_PORT##id##_PVID, \
157    RTL_REG_PORT##id##_NULL_VID_REPLACE, \
158    RTL_REG_PORT##id##_NON_PVID_DISCARD, \
159    RTL_REG_PORT##id##_VID_INSERT, \
160    RTL_REG_PORT##id##_TAG_INSERT, \
161    RTL_REG_PORT##id##_LINK, \
162    RTL_REG_PORT##id##_SPEED, \
163    RTL_REG_PORT##id##_NWAY, \
164    RTL_REG_PORT##id##_NRESTART, \
165    RTL_REG_PORT##id##_DUPLEX, \
166    RTL_REG_PORT##id##_RXEN, \
167    RTL_REG_PORT##id##_TXEN
168    RTL_PORT_ENUM(0),
169    RTL_PORT_ENUM(1),
170    RTL_PORT_ENUM(2),
171    RTL_PORT_ENUM(3),
172    RTL_PORT_ENUM(4),
173    RTL_PORT_ENUM(5),
174};
175
176static const struct rtl_reg rtl_regs[] = {
177    [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
178    [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
179    [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
180
181    /* CPU port number */
182    [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
183    /* Enable CPU port function */
184    [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
185    /* Enable CPU port tag insertion */
186    [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
187    /* Enable CPU port tag removal */
188    [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
189    /* Enable CPU port tag checking */
190    [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
191    [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
192    [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
193    [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
194
195    [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
196
197    [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
198    [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
199    [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
200    [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
201
202#define RTL_VLAN_REGS(id, phy, page, regofs) \
203    [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
204    [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
205    RTL_VLAN_REGS( 0, 0, 0, 0),
206    RTL_VLAN_REGS( 1, 1, 0, 0),
207    RTL_VLAN_REGS( 2, 2, 0, 0),
208    RTL_VLAN_REGS( 3, 3, 0, 0),
209    RTL_VLAN_REGS( 4, 4, 0, 0),
210    RTL_VLAN_REGS( 5, 0, 1, 2),
211    RTL_VLAN_REGS( 6, 1, 1, 2),
212    RTL_VLAN_REGS( 7, 2, 1, 2),
213    RTL_VLAN_REGS( 8, 3, 1, 2),
214    RTL_VLAN_REGS( 9, 4, 1, 2),
215    RTL_VLAN_REGS(10, 0, 1, 4),
216    RTL_VLAN_REGS(11, 1, 1, 4),
217    RTL_VLAN_REGS(12, 2, 1, 4),
218    RTL_VLAN_REGS(13, 3, 1, 4),
219    RTL_VLAN_REGS(14, 4, 1, 4),
220    RTL_VLAN_REGS(15, 0, 1, 6),
221
222#define REG_PORT_SETTING(port, phy) \
223    [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
224    [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
225    [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
226    [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
227    [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
228    [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
229    [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
230    [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
231    [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
232    [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
233    [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
234
235    REG_PORT_SETTING(0, 0),
236    REG_PORT_SETTING(1, 1),
237    REG_PORT_SETTING(2, 2),
238    REG_PORT_SETTING(3, 3),
239    REG_PORT_SETTING(4, 4),
240    REG_PORT_SETTING(5, 6),
241
242#define REG_PORT_PVID(phy, page, regofs) \
243    { page, phy, 24 + regofs, 4, 12, 0 }
244    [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
245    [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
246    [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
247    [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
248    [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
249    [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
250};
251
252
253/* IFXMIPS compat stuff - remove after PHY layer migration */
254static struct switch_dev rtldev;
255/* END IFXMIPS compat stuff */
256
257
258static inline void
259rtl_set_page(struct rtl_priv *priv, unsigned int page)
260{
261    struct mii_bus *bus = priv->bus;
262    u16 pgsel;
263
264    if (priv->page == page)
265        return;
266
267    BUG_ON(page > RTL8306_NUM_PAGES);
268    pgsel = bus->read(bus, 0, RTL8306_REG_PAGE);
269    pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
270    if (page & (1 << 0))
271        pgsel |= RTL8306_REG_PAGE_LO;
272    if (!(page & (1 << 1))) /* bit is inverted */
273        pgsel |= RTL8306_REG_PAGE_HI;
274    bus->write(bus, 0, RTL8306_REG_PAGE, pgsel);
275}
276
277static inline int
278rtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val)
279{
280    struct rtl_priv *priv = to_rtl(dev);
281    struct mii_bus *bus = priv->bus;
282
283    rtl_set_page(priv, page);
284    bus->write(bus, phy, reg, val);
285    bus->read(bus, phy, reg); /* flush */
286    return 0;
287}
288
289static inline int
290rtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg)
291{
292    struct rtl_priv *priv = to_rtl(dev);
293    struct mii_bus *bus = priv->bus;
294
295    rtl_set_page(priv, page);
296    return bus->read(bus, phy, reg);
297}
298
299static inline u16
300rtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val)
301{
302    struct rtl_priv *priv = to_rtl(dev);
303    struct mii_bus *bus = priv->bus;
304    u16 r;
305
306    rtl_set_page(priv, page);
307    r = bus->read(bus, phy, reg);
308    r &= ~mask;
309    r |= val;
310    bus->write(bus, phy, reg, r);
311    return bus->read(bus, phy, reg); /* flush */
312}
313
314
315static inline int
316rtl_get(struct switch_dev *dev, enum rtl_regidx s)
317{
318    const struct rtl_reg *r = &rtl_regs[s];
319    u16 val;
320
321    BUG_ON(s >= ARRAY_SIZE(rtl_regs));
322    if (r->bits == 0) /* unimplemented */
323        return 0;
324
325    val = rtl_r16(dev, r->page, r->phy, r->reg);
326
327    if (r->shift > 0)
328        val >>= r->shift;
329
330    if (r->inverted)
331        val = ~val;
332
333    val &= (1 << r->bits) - 1;
334
335    return val;
336}
337
338static int
339rtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val)
340{
341    const struct rtl_reg *r = &rtl_regs[s];
342    u16 mask = 0xffff;
343
344    BUG_ON(s >= ARRAY_SIZE(rtl_regs));
345
346    if (r->bits == 0) /* unimplemented */
347        return 0;
348
349    if (r->shift > 0)
350        val <<= r->shift;
351
352    if (r->inverted)
353        val = ~val;
354
355    if (r->bits != 16) {
356        mask = (1 << r->bits) - 1;
357        mask <<= r->shift;
358    }
359    val &= mask;
360    return rtl_rmw(dev, r->page, r->phy, r->reg, mask, val);
361}
362
363static void
364rtl_phy_save(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
365{
366    regs->nway = rtl_get(dev, RTL_PORT_REG(port, NWAY));
367    regs->speed = rtl_get(dev, RTL_PORT_REG(port, SPEED));
368    regs->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));
369}
370
371static void
372rtl_phy_restore(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
373{
374    rtl_set(dev, RTL_PORT_REG(port, NWAY), regs->nway);
375    rtl_set(dev, RTL_PORT_REG(port, SPEED), regs->speed);
376    rtl_set(dev, RTL_PORT_REG(port, DUPLEX), regs->duplex);
377}
378
379static void
380rtl_port_set_enable(struct switch_dev *dev, int port, int enabled)
381{
382    rtl_set(dev, RTL_PORT_REG(port, RXEN), enabled);
383    rtl_set(dev, RTL_PORT_REG(port, TXEN), enabled);
384
385    if ((port >= 5) || !enabled)
386        return;
387
388    /* restart autonegotiation if enabled */
389    rtl_set(dev, RTL_PORT_REG(port, NRESTART), 1);
390}
391
392static int
393rtl_hw_apply(struct switch_dev *dev)
394{
395    int i;
396    int trunk_en, trunk_psel;
397    struct rtl_phyregs port5;
398
399    rtl_phy_save(dev, 5, &port5);
400
401    /* disable rx/tx from PHYs */
402    for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
403        rtl_port_set_enable(dev, i, 0);
404    }
405
406    /* save trunking status */
407    trunk_en = rtl_get(dev, RTL_REG_EN_TRUNK);
408    trunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL);
409
410    /* trunk port 3 and 4
411     * XXX: Big WTF, but RealTek seems to do it */
412    rtl_set(dev, RTL_REG_EN_TRUNK, 1);
413    rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1);
414
415    /* execute the software reset */
416    rtl_set(dev, RTL_REG_RESET, 1);
417
418    /* wait for the reset to complete,
419     * but don't wait for too long */
420    for (i = 0; i < 10; i++) {
421        if (rtl_get(dev, RTL_REG_RESET) == 0)
422            break;
423
424        msleep(1);
425    }
426
427    /* enable rx/tx from PHYs */
428    for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
429        rtl_port_set_enable(dev, i, 1);
430    }
431
432    /* restore trunking settings */
433    rtl_set(dev, RTL_REG_EN_TRUNK, trunk_en);
434    rtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel);
435    rtl_phy_restore(dev, 5, &port5);
436
437    return 0;
438}
439
440static void
441rtl_hw_init(struct switch_dev *dev)
442{
443    struct rtl_priv *priv = to_rtl(dev);
444    int cpu_mask = 1 << dev->cpu_port;
445    int i;
446
447    rtl_set(dev, RTL_REG_VLAN_ENABLE, 0);
448    rtl_set(dev, RTL_REG_VLAN_FILTER, 0);
449    rtl_set(dev, RTL_REG_EN_TRUNK, 0);
450    rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0);
451
452    /* initialize cpu port settings */
453    if (priv->do_cpu) {
454        rtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port);
455        rtl_set(dev, RTL_REG_EN_CPUPORT, 1);
456    } else {
457        rtl_set(dev, RTL_REG_CPUPORT, 7);
458        rtl_set(dev, RTL_REG_EN_CPUPORT, 0);
459    }
460    rtl_set(dev, RTL_REG_EN_TAG_OUT, 0);
461    rtl_set(dev, RTL_REG_EN_TAG_IN, 0);
462    rtl_set(dev, RTL_REG_EN_TAG_CLR, 0);
463
464    /* reset all vlans */
465    for (i = 0; i < RTL8306_NUM_VLANS; i++) {
466        rtl_set(dev, RTL_VLAN_REG(i, VID), i);
467        rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0);
468    }
469
470    /* default to port isolation */
471    for (i = 0; i < RTL8306_NUM_PORTS; i++) {
472        unsigned long mask;
473
474        if ((1 << i) == cpu_mask)
475            mask = ((1 << RTL8306_NUM_PORTS) - 1) & ~cpu_mask; /* all bits set */
476        else
477            mask = cpu_mask | (1 << i);
478
479        rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), mask);
480        rtl_set(dev, RTL_PORT_REG(i, PVID), i);
481        rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
482        rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);
483        rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3);
484    }
485    rtl_hw_apply(dev);
486}
487
488#ifdef DEBUG
489static int
490rtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
491{
492    struct rtl_priv *priv = to_rtl(dev);
493    priv->do_cpu = val->value.i;
494    rtl_hw_init(dev);
495    return 0;
496}
497
498static int
499rtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
500{
501    struct rtl_priv *priv = to_rtl(dev);
502    val->value.i = priv->do_cpu;
503    return 0;
504}
505
506static int
507rtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
508{
509    dev->cpu_port = val->value.i;
510    rtl_hw_init(dev);
511    return 0;
512}
513
514static int
515rtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
516{
517    val->value.i = dev->cpu_port;
518    return 0;
519}
520#endif
521
522static int
523rtl_reset(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
524{
525    rtl_hw_init(dev);
526    return 0;
527}
528
529static int
530rtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
531{
532    int idx = attr->id + (val->port_vlan * attr->ofs);
533    struct rtl_phyregs port;
534
535    if (attr->id >= ARRAY_SIZE(rtl_regs))
536        return -EINVAL;
537
538    if ((attr->max > 0) && (val->value.i > attr->max))
539        return -EINVAL;
540
541    /* access to phy register 22 on port 4/5
542     * needs phy status save/restore */
543    if ((val->port_vlan > 3) &&
544        (rtl_regs[idx].reg == 22) &&
545        (rtl_regs[idx].page == 0)) {
546
547        rtl_phy_save(dev, val->port_vlan, &port);
548        rtl_set(dev, idx, val->value.i);
549        rtl_phy_restore(dev, val->port_vlan, &port);
550    } else {
551        rtl_set(dev, idx, val->value.i);
552    }
553
554    return 0;
555}
556
557static int
558rtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
559{
560    int idx = attr->id + (val->port_vlan * attr->ofs);
561
562    if (idx >= ARRAY_SIZE(rtl_regs))
563        return -EINVAL;
564
565    val->value.i = rtl_get(dev, idx);
566    return 0;
567}
568
569static int
570rtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
571{
572    if (val->port_vlan >= RTL8306_NUM_PORTS)
573        return -EINVAL;
574
575    return rtl_attr_set_int(dev, attr, val);
576}
577
578static int
579rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
580{
581    if (val->port_vlan >= RTL8306_NUM_PORTS)
582        return -EINVAL;
583    return rtl_attr_get_int(dev, attr, val);
584}
585
586static int
587rtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
588{
589    if (val->port_vlan >= dev->vlans)
590        return -EINVAL;
591
592    return rtl_attr_set_int(dev, attr, val);
593}
594
595static int
596rtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
597{
598    if (val->port_vlan >= dev->vlans)
599        return -EINVAL;
600
601    return rtl_attr_get_int(dev, attr, val);
602}
603
604static int
605rtl_get_ports(struct switch_dev *dev, struct switch_val *val)
606{
607    unsigned int i, mask;
608
609    mask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
610    for (i = 0; i < RTL8306_NUM_PORTS; i++) {
611        struct switch_port *port;
612
613        if (!(mask & (1 << i)))
614            continue;
615
616        port = &val->value.ports[val->len];
617        port->id = i;
618        port->flags = 0;
619        val->len++;
620    }
621
622    return 0;
623}
624
625static int
626rtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
627{
628    struct rtl_priv *priv = to_rtl(dev);
629    struct rtl_phyregs port;
630    int en = val->value.i;
631    int i;
632
633    rtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu);
634    rtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu);
635    rtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu);
636    rtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en);
637    if (en)
638        rtl_set(dev, RTL_REG_VLAN_FILTER, en);
639
640    for (i = 0; i < RTL8306_NUM_PORTS; i++) {
641        if (i > 3)
642            rtl_phy_save(dev, val->port_vlan, &port);
643        rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
644        rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), (en ? (i == dev->cpu_port ? 0 : 1) : 1));
645        rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? (i == dev->cpu_port ? 2 : 1) : 3));
646        if (i > 3)
647            rtl_phy_restore(dev, val->port_vlan, &port);
648    }
649    rtl_set(dev, RTL_REG_VLAN_ENABLE, en);
650
651    return 0;
652}
653
654static int
655rtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
656{
657    return rtl_get(dev, RTL_REG_VLAN_ENABLE);
658}
659
660static int
661rtl_set_ports(struct switch_dev *dev, struct switch_val *val)
662{
663    unsigned int mask = 0;
664    unsigned int oldmask;
665    int i;
666
667    for(i = 0; i < val->len; i++)
668    {
669        struct switch_port *port = &val->value.ports[i];
670        bool tagged = false;
671
672        mask |= (1 << port->id);
673
674        if (port->id == dev->cpu_port)
675            continue;
676
677        if ((i == dev->cpu_port) ||
678            (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)))
679            tagged = true;
680
681        /* fix up PVIDs for added ports */
682        if (!tagged)
683            rtl_set(dev, RTL_PORT_REG(port->id, PVID), val->port_vlan);
684
685        rtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1));
686        rtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1));
687        rtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1));
688    }
689
690    oldmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
691    rtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask);
692
693    /* fix up PVIDs for removed ports, default to last vlan */
694    oldmask &= ~mask;
695    for (i = 0; i < RTL8306_NUM_PORTS; i++) {
696        if (!(oldmask & (1 << i)))
697            continue;
698
699        if (i == dev->cpu_port)
700            continue;
701
702        if (rtl_get(dev, RTL_PORT_REG(i, PVID)) == val->port_vlan)
703            rtl_set(dev, RTL_PORT_REG(i, PVID), dev->vlans - 1);
704    }
705
706    return 0;
707}
708
709static int
710rtl8306_config_init(struct phy_device *pdev)
711{
712    struct net_device *netdev = pdev->attached_dev;
713    struct rtl_priv *priv = pdev->priv;
714    struct switch_dev *dev = &priv->dev;
715    struct switch_val val;
716    unsigned int chipid, chipver, chiptype;
717    int err;
718
719    /* Only init the switch for the primary PHY */
720    if (pdev->addr != 0)
721        return 0;
722
723    val.value.i = 1;
724    memcpy(&priv->dev, &rtldev, sizeof(struct switch_dev));
725    priv->do_cpu = 0;
726    priv->page = -1;
727    priv->bus = pdev->bus;
728
729    dev->priv = priv;
730
731    chipid = rtl_get(dev, RTL_REG_CHIPID);
732    chipver = rtl_get(dev, RTL_REG_CHIPVER);
733    chiptype = rtl_get(dev, RTL_REG_CHIPTYPE);
734    switch(chiptype) {
735    case 0:
736    case 2:
737        strncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname));
738        priv->type = RTL_TYPE_S;
739        break;
740    case 1:
741        strncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname));
742        priv->type = RTL_TYPE_SD;
743        break;
744    case 3:
745        strncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname));
746        priv->type = RTL_TYPE_SDM;
747        break;
748    default:
749        strncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname));
750        break;
751    }
752
753    dev->name = priv->hwname;
754    rtl_hw_init(dev);
755
756    printk(KERN_INFO "Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv->hwname, chipid, chipver);
757
758    err = register_switch(dev, netdev);
759    if (err < 0) {
760        kfree(priv);
761        return err;
762    }
763
764    return 0;
765}
766
767static struct switch_attr rtl_globals[] = {
768    {
769        .type = SWITCH_TYPE_INT,
770        .name = "reset",
771        .description = "Reset the switch",
772        .set = rtl_reset,
773    },
774    {
775        .type = SWITCH_TYPE_INT,
776        .name = "enable_vlan",
777        .description = "Enable VLAN mode",
778        .max = 1,
779        .set = rtl_set_vlan,
780        .get = rtl_get_vlan,
781    },
782    {
783        RTL_GLOBAL_REGATTR(EN_TRUNK),
784        .name = "trunk",
785        .description = "Enable port trunking",
786        .max = 1,
787    },
788    {
789        RTL_GLOBAL_REGATTR(TRUNK_PORTSEL),
790        .name = "trunk_sel",
791        .description = "Select ports for trunking (0: 0,1 - 1: 3,4)",
792        .max = 1,
793    },
794#ifdef DEBUG
795    {
796        RTL_GLOBAL_REGATTR(VLAN_FILTER),
797        .name = "vlan_filter",
798        .description = "Filter incoming packets for allowed VLANS",
799        .max = 1,
800    },
801    {
802        .type = SWITCH_TYPE_INT,
803        .name = "cpuport",
804        .description = "CPU Port",
805        .set = rtl_set_cpuport,
806        .get = rtl_get_cpuport,
807        .max = RTL8306_NUM_PORTS,
808    },
809    {
810        .type = SWITCH_TYPE_INT,
811        .name = "use_cpuport",
812        .description = "CPU Port handling flag",
813        .set = rtl_set_use_cpuport,
814        .get = rtl_get_use_cpuport,
815        .max = RTL8306_NUM_PORTS,
816    },
817    {
818        RTL_GLOBAL_REGATTR(TRAP_CPU),
819        .name = "trap_cpu",
820        .description = "VLAN trap to CPU",
821        .max = 1,
822    },
823    {
824        RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE),
825        .name = "vlan_tag_aware",
826        .description = "Enable VLAN tag awareness",
827        .max = 1,
828    },
829    {
830        RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY),
831        .name = "tag_only",
832        .description = "Only accept tagged packets",
833        .max = 1,
834    },
835#endif
836};
837static struct switch_attr rtl_port[] = {
838    {
839        RTL_PORT_REGATTR(PVID),
840        .name = "pvid",
841        .description = "Port VLAN ID",
842        .max = RTL8306_NUM_VLANS - 1,
843    },
844    {
845        RTL_PORT_REGATTR(LINK),
846        .name = "link",
847        .description = "get the current link state",
848        .max = 1,
849        .set = NULL,
850    },
851#ifdef DEBUG
852    {
853        RTL_PORT_REGATTR(NULL_VID_REPLACE),
854        .name = "null_vid",
855        .description = "NULL VID gets replaced by port default vid",
856        .max = 1,
857    },
858    {
859        RTL_PORT_REGATTR(NON_PVID_DISCARD),
860        .name = "non_pvid_discard",
861        .description = "discard packets with VID != PVID",
862        .max = 1,
863    },
864    {
865        RTL_PORT_REGATTR(VID_INSERT),
866        .name = "vid_insert_remove",
867        .description = "how should the switch insert and remove vids ?",
868        .max = 3,
869    },
870    {
871        RTL_PORT_REGATTR(TAG_INSERT),
872        .name = "tag_insert",
873        .description = "tag insertion handling",
874        .max = 3,
875    },
876#endif
877    {
878        RTL_PORT_REGATTR(SPEED),
879        .name = "speed",
880        .description = "current link speed",
881        .max = 1,
882    },
883    {
884        RTL_PORT_REGATTR(NWAY),
885        .name = "nway",
886        .description = "enable autonegotiation",
887        .max = 1,
888    },
889};
890
891static struct switch_attr rtl_vlan[] = {
892    {
893        RTL_VLAN_REGATTR(VID),
894        .name = "vid",
895        .description = "VLAN ID",
896        .max = 4095,
897    },
898};
899
900/* template */
901static struct switch_dev rtldev = {
902    .cpu_port = RTL8306_PORT_CPU,
903    .ports = RTL8306_NUM_PORTS,
904    .vlans = RTL8306_NUM_VLANS,
905    .attr_global = {
906        .attr = rtl_globals,
907        .n_attr = ARRAY_SIZE(rtl_globals),
908    },
909    .attr_port = {
910        .attr = rtl_port,
911        .n_attr = ARRAY_SIZE(rtl_port),
912    },
913    .attr_vlan = {
914        .attr = rtl_vlan,
915        .n_attr = ARRAY_SIZE(rtl_vlan),
916    },
917
918    .get_vlan_ports = rtl_get_ports,
919    .set_vlan_ports = rtl_set_ports,
920    .apply_config = rtl_hw_apply,
921};
922
923
924static int
925rtl8306_fixup(struct phy_device *pdev)
926{
927    struct rtl_priv priv;
928    u16 chipid;
929
930    /* Attach to primary LAN port and WAN port */
931    if (pdev->addr != 0 && pdev->addr != 4)
932        return 0;
933
934    priv.page = -1;
935    priv.bus = pdev->bus;
936    chipid = rtl_get(&priv.dev, RTL_REG_CHIPID);
937    if (chipid == 0x5988)
938        pdev->phy_id = RTL8306_MAGIC;
939
940    return 0;
941}
942
943static int
944rtl8306_probe(struct phy_device *pdev)
945{
946    struct rtl_priv *priv;
947
948    list_for_each_entry(priv, &phydevs, list) {
949        /*
950         * share one rtl_priv instance between virtual phy
951         * devices on the same bus
952         */
953        if (priv->bus == pdev->bus)
954            goto found;
955    }
956    priv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL);
957    if (!priv)
958        return -ENOMEM;
959
960    priv->bus = pdev->bus;
961
962found:
963    pdev->priv = priv;
964    return 0;
965}
966
967static void
968rtl8306_remove(struct phy_device *pdev)
969{
970    struct rtl_priv *priv = pdev->priv;
971    unregister_switch(&priv->dev);
972    kfree(priv);
973}
974
975static int
976rtl8306_config_aneg(struct phy_device *pdev)
977{
978    struct rtl_priv *priv = pdev->priv;
979
980    /* Only for WAN */
981    if (pdev->addr == 0)
982        return 0;
983
984    /* Restart autonegotiation */
985    rtl_set(&priv->dev, RTL_PORT_REG(4, NWAY), 1);
986    rtl_set(&priv->dev, RTL_PORT_REG(4, NRESTART), 1);
987
988    return 0;
989}
990
991static int
992rtl8306_read_status(struct phy_device *pdev)
993{
994    struct rtl_priv *priv = pdev->priv;
995    struct switch_dev *dev = &priv->dev;
996
997    if (pdev->addr == 4) {
998        /* WAN */
999        pdev->speed = rtl_get(dev, RTL_PORT_REG(4, SPEED)) ? SPEED_100 : SPEED_10;
1000        pdev->duplex = rtl_get(dev, RTL_PORT_REG(4, DUPLEX)) ? DUPLEX_FULL : DUPLEX_HALF;
1001        pdev->link = !!rtl_get(dev, RTL_PORT_REG(4, LINK));
1002    } else {
1003        /* LAN */
1004        pdev->speed = SPEED_100;
1005        pdev->duplex = DUPLEX_FULL;
1006        pdev->link = 1;
1007    }
1008
1009    /*
1010     * Bypass generic PHY status read,
1011     * it doesn't work with this switch
1012     */
1013    if (pdev->link) {
1014        pdev->state = PHY_RUNNING;
1015        netif_carrier_on(pdev->attached_dev);
1016        pdev->adjust_link(pdev->attached_dev);
1017    } else {
1018        pdev->state = PHY_NOLINK;
1019        netif_carrier_off(pdev->attached_dev);
1020        pdev->adjust_link(pdev->attached_dev);
1021    }
1022
1023    return 0;
1024}
1025
1026
1027static struct phy_driver rtl8306_driver = {
1028    .name = "Realtek RTL8306S",
1029    .flags = PHY_HAS_MAGICANEG,
1030    .phy_id = RTL8306_MAGIC,
1031    .phy_id_mask = 0xffffffff,
1032    .features = PHY_BASIC_FEATURES,
1033    .probe = &rtl8306_probe,
1034    .remove = &rtl8306_remove,
1035    .config_init = &rtl8306_config_init,
1036    .config_aneg = &rtl8306_config_aneg,
1037    .read_status = &rtl8306_read_status,
1038    .driver = { .owner = THIS_MODULE,},
1039};
1040
1041
1042static int __init
1043rtl_init(void)
1044{
1045    phy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup);
1046    return phy_driver_register(&rtl8306_driver);
1047}
1048
1049static void __exit
1050rtl_exit(void)
1051{
1052    phy_driver_unregister(&rtl8306_driver);
1053}
1054
1055module_init(rtl_init);
1056module_exit(rtl_exit);
1057MODULE_LICENSE("GPL");
1058
1059

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