Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/switch.h>
19#include <linux/rtl8366s.h>
20
21#include "rtl8366_smi.h"
22
23#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
24#define RTL8366S_DRIVER_VER "0.2.2"
25
26#define RTL8366S_PHY_NO_MAX 4
27#define RTL8366S_PHY_PAGE_MAX 7
28#define RTL8366S_PHY_ADDR_MAX 31
29
30/* Switch Global Configuration register */
31#define RTL8366S_SGCR 0x0000
32#define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33#define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34#define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35#define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36#define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37#define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38#define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39#define RTL8366S_SGCR_EN_VLAN BIT(13)
40
41/* Port Enable Control register */
42#define RTL8366S_PECR 0x0001
43
44/* Switch Security Control registers */
45#define RTL8366S_SSCR0 0x0002
46#define RTL8366S_SSCR1 0x0003
47#define RTL8366S_SSCR2 0x0004
48#define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
49
50#define RTL8366S_RESET_CTRL_REG 0x0100
51#define RTL8366S_CHIP_CTRL_RESET_HW 1
52#define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
53
54#define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55#define RTL8366S_CHIP_VERSION_MASK 0xf
56#define RTL8366S_CHIP_ID_REG 0x0105
57#define RTL8366S_CHIP_ID_8366 0x8366
58
59/* PHY registers control */
60#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
62
63#define RTL8366S_PHY_CTRL_READ 1
64#define RTL8366S_PHY_CTRL_WRITE 0
65
66#define RTL8366S_PHY_REG_MASK 0x1f
67#define RTL8366S_PHY_PAGE_OFFSET 5
68#define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69#define RTL8366S_PHY_NO_OFFSET 9
70#define RTL8366S_PHY_NO_MASK (0x1f << 9)
71
72/* LED control registers */
73#define RTL8366S_LED_BLINKRATE_REG 0x0420
74#define RTL8366S_LED_BLINKRATE_BIT 0
75#define RTL8366S_LED_BLINKRATE_MASK 0x0007
76
77#define RTL8366S_LED_CTRL_REG 0x0421
78#define RTL8366S_LED_0_1_CTRL_REG 0x0422
79#define RTL8366S_LED_2_3_CTRL_REG 0x0423
80
81#define RTL8366S_MIB_COUNT 33
82#define RTL8366S_GLOBAL_MIB_COUNT 1
83#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84#define RTL8366S_MIB_COUNTER_BASE 0x1000
85#define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86#define RTL8366S_MIB_COUNTER_BASE2 0x1180
87#define RTL8366S_MIB_CTRL_REG 0x11F0
88#define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90#define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
91
92#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
95
96
97#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99        (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
102
103
104#define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
106
107#define RTL8366S_VLAN_TB_CTRL_REG 0x010F
108
109#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
112
113#define RTL8366S_VLAN_MEMCONF_BASE 0x0016
114
115#define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
116
117#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
118#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
119#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
120#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
121#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
122#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
123#define RTL8366S_PORT_STATUS_AN_MASK 0x0080
124
125
126#define RTL8366S_PORT_NUM_CPU 5
127#define RTL8366S_NUM_PORTS 6
128#define RTL8366S_NUM_VLANS 16
129#define RTL8366S_NUM_LEDGROUPS 4
130#define RTL8366S_NUM_VIDS 4096
131#define RTL8366S_PRIORITYMAX 7
132#define RTL8366S_FIDMAX 7
133
134
135#define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
136#define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
137#define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
138#define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
139
140#define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
141#define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
142
143#define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
144                     RTL8366S_PORT_2 | \
145                     RTL8366S_PORT_3 | \
146                     RTL8366S_PORT_4 | \
147                     RTL8366S_PORT_UNKNOWN | \
148                     RTL8366S_PORT_CPU)
149
150#define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
151                     RTL8366S_PORT_2 | \
152                     RTL8366S_PORT_3 | \
153                     RTL8366S_PORT_4 | \
154                     RTL8366S_PORT_UNKNOWN)
155
156#define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
157                     RTL8366S_PORT_2 | \
158                     RTL8366S_PORT_3 | \
159                     RTL8366S_PORT_4)
160
161#define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
162                     RTL8366S_PORT_CPU)
163
164struct rtl8366s {
165    struct device *parent;
166    struct rtl8366_smi smi;
167    struct switch_dev dev;
168};
169
170struct rtl8366s_vlan_mc {
171    u16 reserved2:1;
172    u16 priority:3;
173    u16 vid:12;
174
175    u16 reserved1:1;
176    u16 fid:3;
177    u16 untag:6;
178    u16 member:6;
179};
180
181struct rtl8366s_vlan_4k {
182    u16 reserved1:4;
183    u16 vid:12;
184
185    u16 reserved2:1;
186    u16 fid:3;
187    u16 untag:6;
188    u16 member:6;
189};
190
191static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
192    { 0, 0, 4, "IfInOctets" },
193    { 0, 4, 4, "EtherStatsOctets" },
194    { 0, 8, 2, "EtherStatsUnderSizePkts" },
195    { 0, 10, 2, "EtherFragments" },
196    { 0, 12, 2, "EtherStatsPkts64Octets" },
197    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
198    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
199    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
200    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
201    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
202    { 0, 24, 2, "EtherOversizeStats" },
203    { 0, 26, 2, "EtherStatsJabbers" },
204    { 0, 28, 2, "IfInUcastPkts" },
205    { 0, 30, 2, "EtherStatsMulticastPkts" },
206    { 0, 32, 2, "EtherStatsBroadcastPkts" },
207    { 0, 34, 2, "EtherStatsDropEvents" },
208    { 0, 36, 2, "Dot3StatsFCSErrors" },
209    { 0, 38, 2, "Dot3StatsSymbolErrors" },
210    { 0, 40, 2, "Dot3InPauseFrames" },
211    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
212    { 0, 44, 4, "IfOutOctets" },
213    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
214    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
215    { 0, 52, 2, "Dot3sDeferredTransmissions" },
216    { 0, 54, 2, "Dot3StatsLateCollisions" },
217    { 0, 56, 2, "EtherStatsCollisions" },
218    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
219    { 0, 60, 2, "Dot3OutPauseFrames" },
220    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
221
222    /*
223     * The following counters are accessible at a different
224     * base address.
225     */
226    { 1, 0, 2, "Dot1dTpPortInDiscards" },
227    { 1, 2, 2, "IfOutUcastPkts" },
228    { 1, 4, 2, "IfOutMulticastPkts" },
229    { 1, 6, 2, "IfOutBroadcastPkts" },
230};
231
232#define REG_WR(_smi, _reg, _val) \
233    do { \
234        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
235        if (err) \
236            return err; \
237    } while (0)
238
239#define REG_RMW(_smi, _reg, _mask, _val) \
240    do { \
241        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
242        if (err) \
243            return err; \
244    } while (0)
245
246static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
247{
248    return container_of(smi, struct rtl8366s, smi);
249}
250
251static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
252{
253    return container_of(sw, struct rtl8366s, dev);
254}
255
256static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
257{
258    struct rtl8366s *rtl = sw_to_rtl8366s(sw);
259    return &rtl->smi;
260}
261
262static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
263{
264    int timeout = 10;
265    u32 data;
266
267    rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
268                  RTL8366S_CHIP_CTRL_RESET_HW);
269    do {
270        msleep(1);
271        if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
272            return -EIO;
273
274        if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
275            break;
276    } while (--timeout);
277
278    if (!timeout) {
279        printk("Timeout waiting for the switch to reset\n");
280        return -EIO;
281    }
282
283    return 0;
284}
285
286static int rtl8366s_hw_init(struct rtl8366_smi *smi)
287{
288    int err;
289
290    /* set maximum packet length to 1536 bytes */
291    REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
292        RTL8366S_SGCR_MAX_LENGTH_1536);
293
294    /* enable all ports */
295    REG_WR(smi, RTL8366S_PECR, 0);
296
297    /* enable learning for all ports */
298    REG_WR(smi, RTL8366S_SSCR0, 0);
299
300    /* enable auto ageing for all ports */
301    REG_WR(smi, RTL8366S_SSCR1, 0);
302
303    /*
304     * discard VLAN tagged packets if the port is not a member of
305     * the VLAN with which the packets is associated.
306     */
307    REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
308
309    /* don't drop packets whose DA has not been learned */
310    REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
311
312    return 0;
313}
314
315static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
316                 u32 phy_no, u32 page, u32 addr, u32 *data)
317{
318    u32 reg;
319    int ret;
320
321    if (phy_no > RTL8366S_PHY_NO_MAX)
322        return -EINVAL;
323
324    if (page > RTL8366S_PHY_PAGE_MAX)
325        return -EINVAL;
326
327    if (addr > RTL8366S_PHY_ADDR_MAX)
328        return -EINVAL;
329
330    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
331                    RTL8366S_PHY_CTRL_READ);
332    if (ret)
333        return ret;
334
335    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
336          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
337          (addr & RTL8366S_PHY_REG_MASK);
338
339    ret = rtl8366_smi_write_reg(smi, reg, 0);
340    if (ret)
341        return ret;
342
343    ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
344    if (ret)
345        return ret;
346
347    return 0;
348}
349
350static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
351                  u32 phy_no, u32 page, u32 addr, u32 data)
352{
353    u32 reg;
354    int ret;
355
356    if (phy_no > RTL8366S_PHY_NO_MAX)
357        return -EINVAL;
358
359    if (page > RTL8366S_PHY_PAGE_MAX)
360        return -EINVAL;
361
362    if (addr > RTL8366S_PHY_ADDR_MAX)
363        return -EINVAL;
364
365    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
366                    RTL8366S_PHY_CTRL_WRITE);
367    if (ret)
368        return ret;
369
370    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
371          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
372          (addr & RTL8366S_PHY_REG_MASK);
373
374    ret = rtl8366_smi_write_reg(smi, reg, data);
375    if (ret)
376        return ret;
377
378    return 0;
379}
380
381static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
382                   int port, unsigned long long *val)
383{
384    int i;
385    int err;
386    u32 addr, data;
387    u64 mibvalue;
388
389    if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
390        return -EINVAL;
391
392    switch (rtl8366s_mib_counters[counter].base) {
393    case 0:
394        addr = RTL8366S_MIB_COUNTER_BASE +
395               RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
396        break;
397
398    case 1:
399        addr = RTL8366S_MIB_COUNTER_BASE2 +
400            RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
401        break;
402
403    default:
404        return -EINVAL;
405    }
406
407    addr += rtl8366s_mib_counters[counter].offset;
408
409    /*
410     * Writing access counter address first
411     * then ASIC will prepare 64bits counter wait for being retrived
412     */
413    data = 0; /* writing data will be discard by ASIC */
414    err = rtl8366_smi_write_reg(smi, addr, data);
415    if (err)
416        return err;
417
418    /* read MIB control register */
419    err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
420    if (err)
421        return err;
422
423    if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
424        return -EBUSY;
425
426    if (data & RTL8366S_MIB_CTRL_RESET_MASK)
427        return -EIO;
428
429    mibvalue = 0;
430    for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
431        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
432        if (err)
433            return err;
434
435        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
436    }
437
438    *val = mibvalue;
439    return 0;
440}
441
442static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
443                struct rtl8366_vlan_4k *vlan4k)
444{
445    struct rtl8366s_vlan_4k vlan4k_priv;
446    int err;
447    u32 data;
448    u16 *tableaddr;
449
450    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
451    vlan4k_priv.vid = vid;
452
453    if (vid >= RTL8366S_NUM_VIDS)
454        return -EINVAL;
455
456    tableaddr = (u16 *)&vlan4k_priv;
457
458    /* write VID */
459    data = *tableaddr;
460    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
461    if (err)
462        return err;
463
464    /* write table access control word */
465    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
466                    RTL8366S_TABLE_VLAN_READ_CTRL);
467    if (err)
468        return err;
469
470    err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
471    if (err)
472        return err;
473
474    *tableaddr = data;
475    tableaddr++;
476
477    err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
478                   &data);
479    if (err)
480        return err;
481
482    *tableaddr = data;
483
484    vlan4k->vid = vid;
485    vlan4k->untag = vlan4k_priv.untag;
486    vlan4k->member = vlan4k_priv.member;
487    vlan4k->fid = vlan4k_priv.fid;
488
489    return 0;
490}
491
492static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
493                const struct rtl8366_vlan_4k *vlan4k)
494{
495    struct rtl8366s_vlan_4k vlan4k_priv;
496    int err;
497    u32 data;
498    u16 *tableaddr;
499
500    if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
501        vlan4k->member > RTL8366S_PORT_ALL ||
502        vlan4k->untag > RTL8366S_PORT_ALL ||
503        vlan4k->fid > RTL8366S_FIDMAX)
504        return -EINVAL;
505
506    vlan4k_priv.vid = vlan4k->vid;
507    vlan4k_priv.untag = vlan4k->untag;
508    vlan4k_priv.member = vlan4k->member;
509    vlan4k_priv.fid = vlan4k->fid;
510
511    tableaddr = (u16 *)&vlan4k_priv;
512
513    data = *tableaddr;
514
515    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
516    if (err)
517        return err;
518
519    tableaddr++;
520
521    data = *tableaddr;
522
523    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
524                    data);
525    if (err)
526        return err;
527
528    /* write table access control word */
529    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
530                    RTL8366S_TABLE_VLAN_WRITE_CTRL);
531
532    return err;
533}
534
535static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
536                struct rtl8366_vlan_mc *vlanmc)
537{
538    struct rtl8366s_vlan_mc vlanmc_priv;
539    int err;
540    u32 addr;
541    u32 data;
542    u16 *tableaddr;
543
544    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
545
546    if (index >= RTL8366S_NUM_VLANS)
547        return -EINVAL;
548
549    tableaddr = (u16 *)&vlanmc_priv;
550
551    addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
552    err = rtl8366_smi_read_reg(smi, addr, &data);
553    if (err)
554        return err;
555
556    *tableaddr = data;
557    tableaddr++;
558
559    addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
560    err = rtl8366_smi_read_reg(smi, addr, &data);
561    if (err)
562        return err;
563
564    *tableaddr = data;
565
566    vlanmc->vid = vlanmc_priv.vid;
567    vlanmc->priority = vlanmc_priv.priority;
568    vlanmc->untag = vlanmc_priv.untag;
569    vlanmc->member = vlanmc_priv.member;
570    vlanmc->fid = vlanmc_priv.fid;
571
572    return 0;
573}
574
575static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
576                const struct rtl8366_vlan_mc *vlanmc)
577{
578    struct rtl8366s_vlan_mc vlanmc_priv;
579    int err;
580    u32 addr;
581    u32 data;
582    u16 *tableaddr;
583
584    if (index >= RTL8366S_NUM_VLANS ||
585        vlanmc->vid >= RTL8366S_NUM_VIDS ||
586        vlanmc->priority > RTL8366S_PRIORITYMAX ||
587        vlanmc->member > RTL8366S_PORT_ALL ||
588        vlanmc->untag > RTL8366S_PORT_ALL ||
589        vlanmc->fid > RTL8366S_FIDMAX)
590        return -EINVAL;
591
592    vlanmc_priv.vid = vlanmc->vid;
593    vlanmc_priv.priority = vlanmc->priority;
594    vlanmc_priv.untag = vlanmc->untag;
595    vlanmc_priv.member = vlanmc->member;
596    vlanmc_priv.fid = vlanmc->fid;
597
598    addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
599
600    tableaddr = (u16 *)&vlanmc_priv;
601    data = *tableaddr;
602
603    err = rtl8366_smi_write_reg(smi, addr, data);
604    if (err)
605        return err;
606
607    addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
608
609    tableaddr++;
610    data = *tableaddr;
611
612    err = rtl8366_smi_write_reg(smi, addr, data);
613    if (err)
614        return err;
615
616    return 0;
617}
618
619static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
620{
621    u32 data;
622    int err;
623
624    if (port >= RTL8366S_NUM_PORTS)
625        return -EINVAL;
626
627    err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
628                   &data);
629    if (err)
630        return err;
631
632    *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
633           RTL8366S_PORT_VLAN_CTRL_MASK;
634
635    return 0;
636}
637
638static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
639{
640    if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
641        return -EINVAL;
642
643    return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
644                RTL8366S_PORT_VLAN_CTRL_MASK <<
645                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
646                (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
647                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
648}
649
650static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
651{
652    return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
653                (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
654}
655
656static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
657{
658    return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
659                1, (enable) ? 1 : 0);
660}
661
662static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
663                  const struct switch_attr *attr,
664                  struct switch_val *val)
665{
666    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
667    int err = 0;
668
669    if (val->value.i == 1)
670        err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
671
672    return err;
673}
674
675static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
676                       const struct switch_attr *attr,
677                       struct switch_val *val)
678{
679    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
680    u32 data;
681
682    if (attr->ofs == 1) {
683        rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
684
685        if (data & RTL8366S_SGCR_EN_VLAN)
686            val->value.i = 1;
687        else
688            val->value.i = 0;
689    } else if (attr->ofs == 2) {
690        rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
691
692        if (data & 0x0001)
693            val->value.i = 1;
694        else
695            val->value.i = 0;
696    }
697
698    return 0;
699}
700
701static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
702                     const struct switch_attr *attr,
703                     struct switch_val *val)
704{
705    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
706    u32 data;
707
708    rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
709
710    val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
711
712    return 0;
713}
714
715static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
716                    const struct switch_attr *attr,
717                    struct switch_val *val)
718{
719    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
720
721    if (val->value.i >= 6)
722        return -EINVAL;
723
724    return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
725                RTL8366S_LED_BLINKRATE_MASK,
726                val->value.i);
727}
728
729static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
730                       const struct switch_attr *attr,
731                       struct switch_val *val)
732{
733    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
734
735    if (attr->ofs == 1)
736        return rtl8366s_vlan_set_vlan(smi, val->value.i);
737    else
738        return rtl8366s_vlan_set_4ktable(smi, val->value.i);
739}
740
741static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
742                       const struct switch_attr *attr,
743                       struct switch_val *val)
744{
745    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
746    u32 data;
747
748    rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
749    val->value.i = !data;
750
751    return 0;
752}
753
754
755static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
756                       const struct switch_attr *attr,
757                       struct switch_val *val)
758{
759    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
760    u32 portmask = 0;
761    int err = 0;
762
763    if (!val->value.i)
764        portmask = RTL8366S_PORT_ALL;
765
766    /* set learning for all ports */
767    REG_WR(smi, RTL8366S_SSCR0, portmask);
768
769    /* set auto ageing for all ports */
770    REG_WR(smi, RTL8366S_SSCR1, portmask);
771
772    return 0;
773}
774
775
776static const char *rtl8366s_speed_str(unsigned speed)
777{
778    switch (speed) {
779    case 0:
780        return "10baseT";
781    case 1:
782        return "100baseT";
783    case 2:
784        return "1000baseT";
785    }
786
787    return "unknown";
788}
789
790static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
791                     const struct switch_attr *attr,
792                     struct switch_val *val)
793{
794    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
795    u32 len = 0, data = 0;
796
797    if (val->port_vlan >= RTL8366S_NUM_PORTS)
798        return -EINVAL;
799
800    memset(smi->buf, '\0', sizeof(smi->buf));
801    rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
802                 (val->port_vlan / 2), &data);
803
804    if (val->port_vlan % 2)
805        data = data >> 8;
806
807    if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
808        len = snprintf(smi->buf, sizeof(smi->buf),
809                "port:%d link:up speed:%s %s-duplex %s%s%s",
810                val->port_vlan,
811                rtl8366s_speed_str(data &
812                      RTL8366S_PORT_STATUS_SPEED_MASK),
813                (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
814                    "full" : "half",
815                (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
816                    "tx-pause ": "",
817                (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
818                    "rx-pause " : "",
819                (data & RTL8366S_PORT_STATUS_AN_MASK) ?
820                    "nway ": "");
821    } else {
822        len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
823                val->port_vlan);
824    }
825
826    val->value.s = smi->buf;
827    val->len = len;
828
829    return 0;
830}
831
832static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
833                     const struct switch_attr *attr,
834                     struct switch_val *val)
835{
836    int i;
837    u32 len = 0;
838    struct rtl8366_vlan_4k vlan4k;
839    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
840    char *buf = smi->buf;
841    int err;
842
843    if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
844        return -EINVAL;
845
846    memset(buf, '\0', sizeof(smi->buf));
847
848    err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
849    if (err)
850        return err;
851
852    len += snprintf(buf + len, sizeof(smi->buf) - len,
853            "VLAN %d: Ports: '", vlan4k.vid);
854
855    for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
856        if (!(vlan4k.member & (1 << i)))
857            continue;
858
859        len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
860                (vlan4k.untag & (1 << i)) ? "" : "t");
861    }
862
863    len += snprintf(buf + len, sizeof(smi->buf) - len,
864            "', members=%04x, untag=%04x, fid=%u",
865            vlan4k.member, vlan4k.untag, vlan4k.fid);
866
867    val->value.s = buf;
868    val->len = len;
869
870    return 0;
871}
872
873static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
874                    const struct switch_attr *attr,
875                    struct switch_val *val)
876{
877    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
878    u32 data;
879    u32 mask;
880    u32 reg;
881
882    if (val->port_vlan >= RTL8366S_NUM_PORTS ||
883        (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
884        return -EINVAL;
885
886    if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
887        reg = RTL8366S_LED_BLINKRATE_REG;
888        mask = 0xF << 4;
889        data = val->value.i << 4;
890    } else {
891        reg = RTL8366S_LED_CTRL_REG;
892        mask = 0xF << (val->port_vlan * 4),
893        data = val->value.i << (val->port_vlan * 4);
894    }
895
896    return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
897}
898
899static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
900                    const struct switch_attr *attr,
901                    struct switch_val *val)
902{
903    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
904    u32 data = 0;
905
906    if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
907        return -EINVAL;
908
909    rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
910    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
911
912    return 0;
913}
914
915static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
916                       const struct switch_attr *attr,
917                       struct switch_val *val)
918{
919    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
920
921    if (val->port_vlan >= RTL8366S_NUM_PORTS)
922        return -EINVAL;
923
924
925    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
926                0, (1 << (val->port_vlan + 3)));
927}
928
929static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
930                    const struct switch_attr *attr,
931                    struct switch_val *val)
932{
933    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
934    int i, len = 0;
935    unsigned long long counter = 0;
936    char *buf = smi->buf;
937
938    if (val->port_vlan >= RTL8366S_NUM_PORTS)
939        return -EINVAL;
940
941    len += snprintf(buf + len, sizeof(smi->buf) - len,
942            "Port %d MIB counters\n",
943            val->port_vlan);
944
945    for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
946        len += snprintf(buf + len, sizeof(smi->buf) - len,
947                "%-36s: ", rtl8366s_mib_counters[i].name);
948        if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
949            len += snprintf(buf + len, sizeof(smi->buf) - len,
950                    "%llu\n", counter);
951        else
952            len += snprintf(buf + len, sizeof(smi->buf) - len,
953                    "%s\n", "error");
954    }
955
956    val->value.s = buf;
957    val->len = len;
958    return 0;
959}
960
961static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
962                      struct switch_val *val)
963{
964    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
965    struct switch_port *port;
966    struct rtl8366_vlan_4k vlan4k;
967    int i;
968
969    if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
970        return -EINVAL;
971
972    rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
973
974    port = &val->value.ports[0];
975    val->len = 0;
976    for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
977        if (!(vlan4k.member & BIT(i)))
978            continue;
979
980        port->id = i;
981        port->flags = (vlan4k.untag & BIT(i)) ?
982                    0 : BIT(SWITCH_PORT_FLAG_TAGGED);
983        val->len++;
984        port++;
985    }
986    return 0;
987}
988
989static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
990                      struct switch_val *val)
991{
992    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
993    struct switch_port *port;
994    u32 member = 0;
995    u32 untag = 0;
996    int i;
997
998    if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
999        return -EINVAL;
1000
1001    port = &val->value.ports[0];
1002    for (i = 0; i < val->len; i++, port++) {
1003        member |= BIT(port->id);
1004
1005        if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1006            untag |= BIT(port->id);
1007    }
1008
1009    return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1010}
1011
1012static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1013{
1014    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1015    return rtl8366_get_pvid(smi, port, val);
1016}
1017
1018static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1019{
1020    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1021    return rtl8366_set_pvid(smi, port, val);
1022}
1023
1024static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1025{
1026    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1027    int err;
1028
1029    err = rtl8366s_reset_chip(smi);
1030    if (err)
1031        return err;
1032
1033    err = rtl8366s_hw_init(smi);
1034    if (err)
1035        return err;
1036
1037    return rtl8366_reset_vlan(smi);
1038}
1039
1040static struct switch_attr rtl8366s_globals[] = {
1041    {
1042        .type = SWITCH_TYPE_INT,
1043        .name = "enable_learning",
1044        .description = "Enable learning, enable aging",
1045        .set = rtl8366s_sw_set_learning_enable,
1046        .get = rtl8366s_sw_get_learning_enable,
1047        .max = 1,
1048    }, {
1049        .type = SWITCH_TYPE_INT,
1050        .name = "enable_vlan",
1051        .description = "Enable VLAN mode",
1052        .set = rtl8366s_sw_set_vlan_enable,
1053        .get = rtl8366s_sw_get_vlan_enable,
1054        .max = 1,
1055        .ofs = 1
1056    }, {
1057        .type = SWITCH_TYPE_INT,
1058        .name = "enable_vlan4k",
1059        .description = "Enable VLAN 4K mode",
1060        .set = rtl8366s_sw_set_vlan_enable,
1061        .get = rtl8366s_sw_get_vlan_enable,
1062        .max = 1,
1063        .ofs = 2
1064    }, {
1065        .type = SWITCH_TYPE_INT,
1066        .name = "reset_mibs",
1067        .description = "Reset all MIB counters",
1068        .set = rtl8366s_sw_reset_mibs,
1069        .get = NULL,
1070        .max = 1
1071    }, {
1072        .type = SWITCH_TYPE_INT,
1073        .name = "blinkrate",
1074        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1075        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1076        .set = rtl8366s_sw_set_blinkrate,
1077        .get = rtl8366s_sw_get_blinkrate,
1078        .max = 5
1079    },
1080};
1081
1082static struct switch_attr rtl8366s_port[] = {
1083    {
1084        .type = SWITCH_TYPE_STRING,
1085        .name = "link",
1086        .description = "Get port link information",
1087        .max = 1,
1088        .set = NULL,
1089        .get = rtl8366s_sw_get_port_link,
1090    }, {
1091        .type = SWITCH_TYPE_INT,
1092        .name = "reset_mib",
1093        .description = "Reset single port MIB counters",
1094        .max = 1,
1095        .set = rtl8366s_sw_reset_port_mibs,
1096        .get = NULL,
1097    }, {
1098        .type = SWITCH_TYPE_STRING,
1099        .name = "mib",
1100        .description = "Get MIB counters for port",
1101        .max = 33,
1102        .set = NULL,
1103        .get = rtl8366s_sw_get_port_mib,
1104    }, {
1105        .type = SWITCH_TYPE_INT,
1106        .name = "led",
1107        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1108        .max = 15,
1109        .set = rtl8366s_sw_set_port_led,
1110        .get = rtl8366s_sw_get_port_led,
1111    },
1112};
1113
1114static struct switch_attr rtl8366s_vlan[] = {
1115    {
1116        .type = SWITCH_TYPE_STRING,
1117        .name = "info",
1118        .description = "Get vlan information",
1119        .max = 1,
1120        .set = NULL,
1121        .get = rtl8366s_sw_get_vlan_info,
1122    },
1123};
1124
1125/* template */
1126static struct switch_dev rtl8366_switch_dev = {
1127    .name = "RTL8366S",
1128    .cpu_port = RTL8366S_PORT_NUM_CPU,
1129    .ports = RTL8366S_NUM_PORTS,
1130    .vlans = RTL8366S_NUM_VLANS,
1131    .attr_global = {
1132        .attr = rtl8366s_globals,
1133        .n_attr = ARRAY_SIZE(rtl8366s_globals),
1134    },
1135    .attr_port = {
1136        .attr = rtl8366s_port,
1137        .n_attr = ARRAY_SIZE(rtl8366s_port),
1138    },
1139    .attr_vlan = {
1140        .attr = rtl8366s_vlan,
1141        .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1142    },
1143
1144    .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1145    .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1146    .get_port_pvid = rtl8366s_sw_get_port_pvid,
1147    .set_port_pvid = rtl8366s_sw_set_port_pvid,
1148    .reset_switch = rtl8366s_sw_reset_switch,
1149};
1150
1151static int rtl8366s_switch_init(struct rtl8366s *rtl)
1152{
1153    struct switch_dev *dev = &rtl->dev;
1154    int err;
1155
1156    memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1157    dev->priv = rtl;
1158    dev->devname = dev_name(rtl->parent);
1159
1160    err = register_switch(dev, NULL);
1161    if (err)
1162        dev_err(rtl->parent, "switch registration failed\n");
1163
1164    return err;
1165}
1166
1167static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1168{
1169    unregister_switch(&rtl->dev);
1170}
1171
1172static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1173{
1174    struct rtl8366_smi *smi = bus->priv;
1175    u32 val = 0;
1176    int err;
1177
1178    err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1179    if (err)
1180        return 0xffff;
1181
1182    return val;
1183}
1184
1185static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1186{
1187    struct rtl8366_smi *smi = bus->priv;
1188    u32 t;
1189    int err;
1190
1191    err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1192    /* flush write */
1193    (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1194
1195    return err;
1196}
1197
1198static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1199{
1200    return (bus->read == rtl8366s_mii_read &&
1201        bus->write == rtl8366s_mii_write);
1202}
1203
1204static int rtl8366s_setup(struct rtl8366s *rtl)
1205{
1206    struct rtl8366_smi *smi = &rtl->smi;
1207    int ret;
1208
1209    ret = rtl8366s_reset_chip(smi);
1210    if (ret)
1211        return ret;
1212
1213    ret = rtl8366s_hw_init(smi);
1214    return ret;
1215}
1216
1217static int rtl8366s_detect(struct rtl8366_smi *smi)
1218{
1219    u32 chip_id = 0;
1220    u32 chip_ver = 0;
1221    int ret;
1222
1223    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1224    if (ret) {
1225        dev_err(smi->parent, "unable to read chip id\n");
1226        return ret;
1227    }
1228
1229    switch (chip_id) {
1230    case RTL8366S_CHIP_ID_8366:
1231        break;
1232    default:
1233        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1234        return -ENODEV;
1235    }
1236
1237    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1238                   &chip_ver);
1239    if (ret) {
1240        dev_err(smi->parent, "unable to read chip version\n");
1241        return ret;
1242    }
1243
1244    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1245         chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1246
1247    return 0;
1248}
1249
1250static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1251    .detect = rtl8366s_detect,
1252    .mii_read = rtl8366s_mii_read,
1253    .mii_write = rtl8366s_mii_write,
1254
1255    .get_vlan_mc = rtl8366s_get_vlan_mc,
1256    .set_vlan_mc = rtl8366s_set_vlan_mc,
1257    .get_vlan_4k = rtl8366s_get_vlan_4k,
1258    .set_vlan_4k = rtl8366s_set_vlan_4k,
1259    .get_mc_index = rtl8366s_get_mc_index,
1260    .set_mc_index = rtl8366s_set_mc_index,
1261    .get_mib_counter = rtl8366_get_mib_counter,
1262};
1263
1264static int __init rtl8366s_probe(struct platform_device *pdev)
1265{
1266    static int rtl8366_smi_version_printed;
1267    struct rtl8366s_platform_data *pdata;
1268    struct rtl8366s *rtl;
1269    struct rtl8366_smi *smi;
1270    int err;
1271
1272    if (!rtl8366_smi_version_printed++)
1273        printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1274               " version " RTL8366S_DRIVER_VER"\n");
1275
1276    pdata = pdev->dev.platform_data;
1277    if (!pdata) {
1278        dev_err(&pdev->dev, "no platform data specified\n");
1279        err = -EINVAL;
1280        goto err_out;
1281    }
1282
1283    rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1284    if (!rtl) {
1285        dev_err(&pdev->dev, "no memory for private data\n");
1286        err = -ENOMEM;
1287        goto err_out;
1288    }
1289
1290    rtl->parent = &pdev->dev;
1291
1292    smi = &rtl->smi;
1293    smi->parent = &pdev->dev;
1294    smi->gpio_sda = pdata->gpio_sda;
1295    smi->gpio_sck = pdata->gpio_sck;
1296    smi->ops = &rtl8366s_smi_ops;
1297    smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1298    smi->num_ports = RTL8366S_NUM_PORTS;
1299    smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1300    smi->mib_counters = rtl8366s_mib_counters;
1301    smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1302
1303    err = rtl8366_smi_init(smi);
1304    if (err)
1305        goto err_free_rtl;
1306
1307    platform_set_drvdata(pdev, rtl);
1308
1309    err = rtl8366s_setup(rtl);
1310    if (err)
1311        goto err_clear_drvdata;
1312
1313    err = rtl8366s_switch_init(rtl);
1314    if (err)
1315        goto err_clear_drvdata;
1316
1317    return 0;
1318
1319 err_clear_drvdata:
1320    platform_set_drvdata(pdev, NULL);
1321    rtl8366_smi_cleanup(smi);
1322 err_free_rtl:
1323    kfree(rtl);
1324 err_out:
1325    return err;
1326}
1327
1328static int rtl8366s_phy_config_init(struct phy_device *phydev)
1329{
1330    if (!rtl8366s_mii_bus_match(phydev->bus))
1331        return -EINVAL;
1332
1333    return 0;
1334}
1335
1336static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1337{
1338    return 0;
1339}
1340
1341static struct phy_driver rtl8366s_phy_driver = {
1342    .phy_id = 0x001cc960,
1343    .name = "Realtek RTL8366S",
1344    .phy_id_mask = 0x1ffffff0,
1345    .features = PHY_GBIT_FEATURES,
1346    .config_aneg = rtl8366s_phy_config_aneg,
1347    .config_init = rtl8366s_phy_config_init,
1348    .read_status = genphy_read_status,
1349    .driver = {
1350        .owner = THIS_MODULE,
1351    },
1352};
1353
1354static int __devexit rtl8366s_remove(struct platform_device *pdev)
1355{
1356    struct rtl8366s *rtl = platform_get_drvdata(pdev);
1357
1358    if (rtl) {
1359        rtl8366s_switch_cleanup(rtl);
1360        platform_set_drvdata(pdev, NULL);
1361        rtl8366_smi_cleanup(&rtl->smi);
1362        kfree(rtl);
1363    }
1364
1365    return 0;
1366}
1367
1368static struct platform_driver rtl8366s_driver = {
1369    .driver = {
1370        .name = RTL8366S_DRIVER_NAME,
1371        .owner = THIS_MODULE,
1372    },
1373    .probe = rtl8366s_probe,
1374    .remove = __devexit_p(rtl8366s_remove),
1375};
1376
1377static int __init rtl8366s_module_init(void)
1378{
1379    int ret;
1380    ret = platform_driver_register(&rtl8366s_driver);
1381    if (ret)
1382        return ret;
1383
1384    ret = phy_driver_register(&rtl8366s_phy_driver);
1385    if (ret)
1386        goto err_platform_unregister;
1387
1388    return 0;
1389
1390 err_platform_unregister:
1391    platform_driver_unregister(&rtl8366s_driver);
1392    return ret;
1393}
1394module_init(rtl8366s_module_init);
1395
1396static void __exit rtl8366s_module_exit(void)
1397{
1398    phy_driver_unregister(&rtl8366s_phy_driver);
1399    platform_driver_unregister(&rtl8366s_driver);
1400}
1401module_exit(rtl8366s_module_exit);
1402
1403MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1404MODULE_VERSION(RTL8366S_DRIVER_VER);
1405MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1406MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1407MODULE_LICENSE("GPL v2");
1408MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
1409

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