Root/target/linux/ifxmips/files-2.6.33/arch/mips/ifxmips/compat/timer.c

1#include <linux/kernel.h>
2#include <linux/module.h>
3#include <linux/version.h>
4#include <linux/types.h>
5#include <linux/fs.h>
6#include <linux/miscdevice.h>
7#include <linux/init.h>
8#include <linux/uaccess.h>
9#include <linux/unistd.h>
10#include <linux/errno.h>
11#include <linux/interrupt.h>
12#include <linux/sched.h>
13
14#include <asm/irq.h>
15#include <asm/div64.h>
16
17#include <ifxmips.h>
18#include <ifxmips_irq.h>
19#include <ifxmips_cgu.h>
20#include <ifxmips_gptu.h>
21#include <ifxmips_pmu.h>
22
23#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
24
25#ifdef TIMER1A
26#define FIRST_TIMER TIMER1A
27#else
28#define FIRST_TIMER 2
29#endif
30
31/*
32 * GPTC divider is set or not.
33 */
34#define GPTU_CLC_RMC_IS_SET 0
35
36/*
37 * Timer Interrupt (IRQ)
38 */
39/* Must be adjusted when ICU driver is available */
40#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
41
42/*
43 * Bits Operation
44 */
45#define GET_BITS(x, msb, lsb) \
46    (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
47#define SET_BITS(x, msb, lsb, value) \
48    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
49    (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
50
51/*
52 * GPTU Register Mapping
53 */
54#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
55#define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
56#define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
57#define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
58#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
59#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
60#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
61#define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
62#define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
63#define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
64
65/*
66 * Clock Control Register
67 */
68#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
69#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
70#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
71#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
72#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
73#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
74#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
75
76#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
77#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
78#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
79#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
80#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
81#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
82#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
83
84/*
85 * ID Register
86 */
87#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
88#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
89#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
90
91/*
92 * Control Register of Timer/Counter nX
93 * n is the index of block (1 based index)
94 * X is either A or B
95 */
96#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
97#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
98#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
99#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
100#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
101#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
102#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
103#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
104#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
105#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
106
107#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
108#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
109#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
110#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
111#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
112#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
113#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
114#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
115#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
116
117#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
118#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
119#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
120
121#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
122#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
123
124#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
125#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
126#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
127#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
128#define TIMER_FLAG_NONE_EDGE 0x0000
129#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
130#define TIMER_FLAG_REAL 0x0000
131#define TIMER_FLAG_INVERT 0x0040
132#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
133#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
134#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
135#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
136#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
137#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
138
139struct timer_dev_timer {
140    unsigned int f_irq_on;
141    unsigned int irq;
142    unsigned int flag;
143    unsigned long arg1;
144    unsigned long arg2;
145};
146
147struct timer_dev {
148    struct mutex gptu_mutex;
149    unsigned int number_of_timers;
150    unsigned int occupation;
151    unsigned int f_gptu_on;
152    struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
153};
154
155static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
156static int gptu_open(struct inode *, struct file *);
157static int gptu_release(struct inode *, struct file *);
158
159static struct file_operations gptu_fops = {
160    .owner = THIS_MODULE,
161    .ioctl = gptu_ioctl,
162    .open = gptu_open,
163    .release = gptu_release
164};
165
166static struct miscdevice gptu_miscdev = {
167    .minor = MISC_DYNAMIC_MINOR,
168    .name = "gptu",
169    .fops = &gptu_fops,
170};
171
172static struct timer_dev timer_dev;
173
174static irqreturn_t timer_irq_handler(int irq, void *p)
175{
176    unsigned int timer;
177    unsigned int flag;
178    struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
179
180    timer = irq - TIMER_INTERRUPT;
181    if (timer < timer_dev.number_of_timers
182        && dev_timer == &timer_dev.timer[timer]) {
183        /* Clear interrupt. */
184        ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
185
186        /* Call user hanler or signal. */
187        flag = dev_timer->flag;
188        if (!(timer & 0x01)
189            || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
190            /* 16-bit timer or timer A of 32-bit timer */
191            switch (TIMER_FLAG_MASK_HANDLE(flag)) {
192            case TIMER_FLAG_CALLBACK_IN_IRQ:
193            case TIMER_FLAG_CALLBACK_IN_HB:
194                if (dev_timer->arg1)
195                    (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
196                break;
197            case TIMER_FLAG_SIGNAL:
198                send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
199                break;
200            }
201        }
202    }
203    return IRQ_HANDLED;
204}
205
206static inline void ifxmips_enable_gptu(void)
207{
208    ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
209
210    /* Set divider as 1, disable write protection for SPEN, enable module. */
211    *IFXMIPS_GPTU_CLC =
212        GPTU_CLC_SMC_SET(0x00) |
213        GPTU_CLC_RMC_SET(0x01) |
214        GPTU_CLC_FSOE_SET(0) |
215        GPTU_CLC_SBWE_SET(1) |
216        GPTU_CLC_EDIS_SET(0) |
217        GPTU_CLC_SPEN_SET(0) |
218        GPTU_CLC_DISR_SET(0);
219}
220
221static inline void ifxmips_disable_gptu(void)
222{
223    ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
224    ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
225
226    /* Set divider as 0, enable write protection for SPEN, disable module. */
227    *IFXMIPS_GPTU_CLC =
228        GPTU_CLC_SMC_SET(0x00) |
229        GPTU_CLC_RMC_SET(0x00) |
230        GPTU_CLC_FSOE_SET(0) |
231        GPTU_CLC_SBWE_SET(0) |
232        GPTU_CLC_EDIS_SET(0) |
233        GPTU_CLC_SPEN_SET(0) |
234        GPTU_CLC_DISR_SET(1);
235
236    ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
237}
238
239int ifxmips_request_timer(unsigned int timer, unsigned int flag,
240    unsigned long value, unsigned long arg1, unsigned long arg2)
241{
242    int ret = 0;
243    unsigned int con_reg, irnen_reg;
244    int n, X;
245
246    if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
247        return -EINVAL;
248
249    printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
250        timer, flag, value);
251
252    if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
253        value &= 0xFFFF;
254    else
255        timer &= ~0x01;
256
257    mutex_lock(&timer_dev.gptu_mutex);
258
259    /*
260     * Allocate timer.
261     */
262    if (timer < FIRST_TIMER) {
263        unsigned int mask;
264        unsigned int shift;
265        /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
266        unsigned int offset = TIMER2A;
267
268        /*
269         * Pick up a free timer.
270         */
271        if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
272            mask = 1 << offset;
273            shift = 1;
274        } else {
275            mask = 3 << offset;
276            shift = 2;
277        }
278        for (timer = offset;
279             timer < offset + timer_dev.number_of_timers;
280             timer += shift, mask <<= shift)
281            if (!(timer_dev.occupation & mask)) {
282                timer_dev.occupation |= mask;
283                break;
284            }
285        if (timer >= offset + timer_dev.number_of_timers) {
286            printk("failed![%d]\n", __LINE__);
287            mutex_unlock(&timer_dev.gptu_mutex);
288            return -EINVAL;
289        } else
290            ret = timer;
291    } else {
292        register unsigned int mask;
293
294        /*
295         * Check if the requested timer is free.
296         */
297        mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
298        if ((timer_dev.occupation & mask)) {
299            printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
300                __LINE__, mask, timer_dev.occupation);
301            mutex_unlock(&timer_dev.gptu_mutex);
302            return -EBUSY;
303        } else {
304            timer_dev.occupation |= mask;
305            ret = 0;
306        }
307    }
308
309    /*
310     * Prepare control register value.
311     */
312    switch (TIMER_FLAG_MASK_EDGE(flag)) {
313    default:
314    case TIMER_FLAG_NONE_EDGE:
315        con_reg = GPTU_CON_EDGE_SET(0x00);
316        break;
317    case TIMER_FLAG_RISE_EDGE:
318        con_reg = GPTU_CON_EDGE_SET(0x01);
319        break;
320    case TIMER_FLAG_FALL_EDGE:
321        con_reg = GPTU_CON_EDGE_SET(0x02);
322        break;
323    case TIMER_FLAG_ANY_EDGE:
324        con_reg = GPTU_CON_EDGE_SET(0x03);
325        break;
326    }
327    if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
328        con_reg |=
329            TIMER_FLAG_MASK_SRC(flag) ==
330            TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
331            GPTU_CON_SRC_EXT_SET(0);
332    else
333        con_reg |=
334            TIMER_FLAG_MASK_SRC(flag) ==
335            TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
336            GPTU_CON_SRC_EG_SET(0);
337    con_reg |=
338        TIMER_FLAG_MASK_SYNC(flag) ==
339        TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
340        GPTU_CON_SYNC_SET(1);
341    con_reg |=
342        TIMER_FLAG_MASK_INVERT(flag) ==
343        TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
344    con_reg |=
345        TIMER_FLAG_MASK_SIZE(flag) ==
346        TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
347        GPTU_CON_EXT_SET(1);
348    con_reg |=
349        TIMER_FLAG_MASK_STOP(flag) ==
350        TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
351    con_reg |=
352        TIMER_FLAG_MASK_TYPE(flag) ==
353        TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
354        GPTU_CON_CNT_SET(1);
355    con_reg |=
356        TIMER_FLAG_MASK_DIR(flag) ==
357        TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
358
359    /*
360     * Fill up running data.
361     */
362    timer_dev.timer[timer - FIRST_TIMER].flag = flag;
363    timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
364    timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
365    if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
366        timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
367
368    /*
369     * Enable GPTU module.
370     */
371    if (!timer_dev.f_gptu_on) {
372        ifxmips_enable_gptu();
373        timer_dev.f_gptu_on = 1;
374    }
375
376    /*
377     * Enable IRQ.
378     */
379    if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
380        if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
381            timer_dev.timer[timer - FIRST_TIMER].arg1 =
382                (unsigned long) find_task_by_vpid((int) arg1);
383
384        irnen_reg = 1 << (timer - FIRST_TIMER);
385
386        if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
387            || (TIMER_FLAG_MASK_HANDLE(flag) ==
388            TIMER_FLAG_CALLBACK_IN_IRQ
389            && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
390            enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
391            timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
392        }
393    } else
394        irnen_reg = 0;
395
396    /*
397     * Write config register, reload value and enable interrupt.
398     */
399    n = timer >> 1;
400    X = timer & 0x01;
401    *IFXMIPS_GPTU_CON(n, X) = con_reg;
402    *IFXMIPS_GPTU_RELOAD(n, X) = value;
403    /* printk("reload value = %d\n", (u32)value); */
404    *IFXMIPS_GPTU_IRNEN |= irnen_reg;
405
406    mutex_unlock(&timer_dev.gptu_mutex);
407    printk("successful!\n");
408    return ret;
409}
410EXPORT_SYMBOL(ifxmips_request_timer);
411
412int ifxmips_free_timer(unsigned int timer)
413{
414    unsigned int flag;
415    unsigned int mask;
416    int n, X;
417
418    if (!timer_dev.f_gptu_on)
419        return -EINVAL;
420
421    if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
422        return -EINVAL;
423
424    mutex_lock(&timer_dev.gptu_mutex);
425
426    flag = timer_dev.timer[timer - FIRST_TIMER].flag;
427    if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
428        timer &= ~0x01;
429
430    mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
431    if (((timer_dev.occupation & mask) ^ mask)) {
432        mutex_unlock(&timer_dev.gptu_mutex);
433        return -EINVAL;
434    }
435
436    n = timer >> 1;
437    X = timer & 0x01;
438
439    if (GPTU_CON_EN(n, X))
440        *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
441
442    *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
443    *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
444
445    if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
446        disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
447        timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
448    }
449
450    timer_dev.occupation &= ~mask;
451    if (!timer_dev.occupation && timer_dev.f_gptu_on) {
452        ifxmips_disable_gptu();
453        timer_dev.f_gptu_on = 0;
454    }
455
456    mutex_unlock(&timer_dev.gptu_mutex);
457
458    return 0;
459}
460EXPORT_SYMBOL(ifxmips_free_timer);
461
462int ifxmips_start_timer(unsigned int timer, int is_resume)
463{
464    unsigned int flag;
465    unsigned int mask;
466    int n, X;
467
468    if (!timer_dev.f_gptu_on)
469        return -EINVAL;
470
471    if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
472        return -EINVAL;
473
474    mutex_lock(&timer_dev.gptu_mutex);
475
476    flag = timer_dev.timer[timer - FIRST_TIMER].flag;
477    if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
478        timer &= ~0x01;
479
480    mask = (TIMER_FLAG_MASK_SIZE(flag) ==
481    TIMER_FLAG_16BIT ? 1 : 3) << timer;
482    if (((timer_dev.occupation & mask) ^ mask)) {
483        mutex_unlock(&timer_dev.gptu_mutex);
484        return -EINVAL;
485    }
486
487    n = timer >> 1;
488    X = timer & 0x01;
489
490    *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
491
492    mutex_unlock(&timer_dev.gptu_mutex);
493
494    return 0;
495}
496EXPORT_SYMBOL(ifxmips_start_timer);
497
498int ifxmips_stop_timer(unsigned int timer)
499{
500    unsigned int flag;
501    unsigned int mask;
502    int n, X;
503
504    if (!timer_dev.f_gptu_on)
505        return -EINVAL;
506
507    if (timer < FIRST_TIMER
508        || timer >= FIRST_TIMER + timer_dev.number_of_timers)
509        return -EINVAL;
510
511    mutex_lock(&timer_dev.gptu_mutex);
512
513    flag = timer_dev.timer[timer - FIRST_TIMER].flag;
514    if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
515        timer &= ~0x01;
516
517    mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
518    if (((timer_dev.occupation & mask) ^ mask)) {
519        mutex_unlock(&timer_dev.gptu_mutex);
520        return -EINVAL;
521    }
522
523    n = timer >> 1;
524    X = timer & 0x01;
525
526    *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
527
528    mutex_unlock(&timer_dev.gptu_mutex);
529
530    return 0;
531}
532EXPORT_SYMBOL(ifxmips_stop_timer);
533
534int ifxmips_reset_counter_flags(u32 timer, u32 flags)
535{
536    unsigned int oflag;
537    unsigned int mask, con_reg;
538    int n, X;
539
540    if (!timer_dev.f_gptu_on)
541        return -EINVAL;
542
543    if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
544        return -EINVAL;
545
546    mutex_lock(&timer_dev.gptu_mutex);
547
548    oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
549    if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
550        timer &= ~0x01;
551
552    mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
553    if (((timer_dev.occupation & mask) ^ mask)) {
554        mutex_unlock(&timer_dev.gptu_mutex);
555        return -EINVAL;
556    }
557
558    switch (TIMER_FLAG_MASK_EDGE(flags)) {
559    default:
560    case TIMER_FLAG_NONE_EDGE:
561        con_reg = GPTU_CON_EDGE_SET(0x00);
562        break;
563    case TIMER_FLAG_RISE_EDGE:
564        con_reg = GPTU_CON_EDGE_SET(0x01);
565        break;
566    case TIMER_FLAG_FALL_EDGE:
567        con_reg = GPTU_CON_EDGE_SET(0x02);
568        break;
569    case TIMER_FLAG_ANY_EDGE:
570        con_reg = GPTU_CON_EDGE_SET(0x03);
571        break;
572    }
573    if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
574        con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
575    else
576        con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
577    con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
578    con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
579    con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
580    con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
581    con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
582    con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
583
584    timer_dev.timer[timer - FIRST_TIMER].flag = flags;
585    if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
586        timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
587
588    n = timer >> 1;
589    X = timer & 0x01;
590
591    *IFXMIPS_GPTU_CON(n, X) = con_reg;
592    smp_wmb();
593    printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X));
594    mutex_unlock(&timer_dev.gptu_mutex);
595    return 0;
596}
597EXPORT_SYMBOL(ifxmips_reset_counter_flags);
598
599int ifxmips_get_count_value(unsigned int timer, unsigned long *value)
600{
601    unsigned int flag;
602    unsigned int mask;
603    int n, X;
604
605    if (!timer_dev.f_gptu_on)
606        return -EINVAL;
607
608    if (timer < FIRST_TIMER
609        || timer >= FIRST_TIMER + timer_dev.number_of_timers)
610        return -EINVAL;
611
612    mutex_lock(&timer_dev.gptu_mutex);
613
614    flag = timer_dev.timer[timer - FIRST_TIMER].flag;
615    if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
616        timer &= ~0x01;
617
618    mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
619    if (((timer_dev.occupation & mask) ^ mask)) {
620        mutex_unlock(&timer_dev.gptu_mutex);
621        return -EINVAL;
622    }
623
624    n = timer >> 1;
625    X = timer & 0x01;
626
627    *value = *IFXMIPS_GPTU_COUNT(n, X);
628
629    mutex_unlock(&timer_dev.gptu_mutex);
630
631    return 0;
632}
633EXPORT_SYMBOL(ifxmips_get_count_value);
634
635u32 ifxmips_cal_divider(unsigned long freq)
636{
637    u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
638    u32 clock_divider = 1;
639    module_freq = fpi * 1000;
640    do_div(module_freq, clock_divider * freq);
641    return module_freq;
642}
643EXPORT_SYMBOL(ifxmips_cal_divider);
644
645int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
646    int is_ext_src, unsigned int handle_flag, unsigned long arg1,
647    unsigned long arg2)
648{
649    unsigned long divider;
650    unsigned int flag;
651
652    divider = ifxmips_cal_divider(freq);
653    if (divider == 0)
654        return -EINVAL;
655    flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
656        | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
657        | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
658        | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
659        | TIMER_FLAG_MASK_HANDLE(handle_flag);
660
661    printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n",
662        timer, freq, divider);
663    return ifxmips_request_timer(timer, flag, divider, arg1, arg2);
664}
665EXPORT_SYMBOL(ifxmips_set_timer);
666
667int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload,
668    unsigned long arg1, unsigned long arg2)
669{
670    printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload);
671    return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
672}
673EXPORT_SYMBOL(ifxmips_set_counter);
674
675static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
676    unsigned long arg)
677{
678    int ret;
679    struct gptu_ioctl_param param;
680
681    if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
682        return -EFAULT;
683    copy_from_user(&param, (void *) arg, sizeof(param));
684
685    if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
686           || GPTU_SET_COUNTER) && param.timer < 2)
687         || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
688        && !access_ok(VERIFY_WRITE, arg,
689               sizeof(struct gptu_ioctl_param)))
690        return -EFAULT;
691
692    switch (cmd) {
693    case GPTU_REQUEST_TIMER:
694        ret = ifxmips_request_timer(param.timer, param.flag, param.value,
695                     (unsigned long) param.pid,
696                     (unsigned long) param.sig);
697        if (ret > 0) {
698            copy_to_user(&((struct gptu_ioctl_param *) arg)->
699                      timer, &ret, sizeof(&ret));
700            ret = 0;
701        }
702        break;
703    case GPTU_FREE_TIMER:
704        ret = ifxmips_free_timer(param.timer);
705        break;
706    case GPTU_START_TIMER:
707        ret = ifxmips_start_timer(param.timer, param.flag);
708        break;
709    case GPTU_STOP_TIMER:
710        ret = ifxmips_stop_timer(param.timer);
711        break;
712    case GPTU_GET_COUNT_VALUE:
713        ret = ifxmips_get_count_value(param.timer, &param.value);
714        if (!ret)
715            copy_to_user(&((struct gptu_ioctl_param *) arg)->
716                      value, &param.value,
717                      sizeof(param.value));
718        break;
719    case GPTU_CALCULATE_DIVIDER:
720        param.value = ifxmips_cal_divider(param.value);
721        if (param.value == 0)
722            ret = -EINVAL;
723        else {
724            copy_to_user(&((struct gptu_ioctl_param *) arg)->
725                      value, &param.value,
726                      sizeof(param.value));
727            ret = 0;
728        }
729        break;
730    case GPTU_SET_TIMER:
731        ret = ifxmips_set_timer(param.timer, param.value,
732                 TIMER_FLAG_MASK_STOP(param.flag) !=
733                 TIMER_FLAG_ONCE ? 1 : 0,
734                 TIMER_FLAG_MASK_SRC(param.flag) ==
735                 TIMER_FLAG_EXT_SRC ? 1 : 0,
736                 TIMER_FLAG_MASK_HANDLE(param.flag) ==
737                 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
738                 TIMER_FLAG_NO_HANDLE,
739                 (unsigned long) param.pid,
740                 (unsigned long) param.sig);
741        if (ret > 0) {
742            copy_to_user(&((struct gptu_ioctl_param *) arg)->
743                      timer, &ret, sizeof(&ret));
744            ret = 0;
745        }
746        break;
747    case GPTU_SET_COUNTER:
748        ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0);
749        if (ret > 0) {
750            copy_to_user(&((struct gptu_ioctl_param *) arg)->
751                      timer, &ret, sizeof(&ret));
752            ret = 0;
753        }
754        break;
755    default:
756        ret = -ENOTTY;
757    }
758
759    return ret;
760}
761
762static int gptu_open(struct inode *inode, struct file *file)
763{
764    return 0;
765}
766
767static int gptu_release(struct inode *inode, struct file *file)
768{
769    return 0;
770}
771
772int __init ifxmips_gptu_init(void)
773{
774    int ret;
775    unsigned int i;
776
777    ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
778    ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
779
780    memset(&timer_dev, 0, sizeof(timer_dev));
781    mutex_init(&timer_dev.gptu_mutex);
782
783    ifxmips_enable_gptu();
784    timer_dev.number_of_timers = GPTU_ID_CFG * 2;
785    ifxmips_disable_gptu();
786    if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
787        timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
788    printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
789
790    ret = misc_register(&gptu_miscdev);
791    if (ret) {
792        printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
793        return ret;
794    } else {
795        printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
796    }
797
798    for (i = 0; i < timer_dev.number_of_timers; i++) {
799        ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
800        if (ret) {
801            for (; i >= 0; i--)
802                free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
803            misc_deregister(&gptu_miscdev);
804            printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
805            return ret;
806        } else {
807            timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
808            disable_irq(timer_dev.timer[i].irq);
809            printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
810        }
811    }
812
813    return 0;
814}
815
816void __exit ifxmips_gptu_exit(void)
817{
818    unsigned int i;
819
820    for (i = 0; i < timer_dev.number_of_timers; i++) {
821        if (timer_dev.timer[i].f_irq_on)
822            disable_irq(timer_dev.timer[i].irq);
823        free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
824    }
825    ifxmips_disable_gptu();
826    misc_deregister(&gptu_miscdev);
827}
828
829module_init(ifxmips_gptu_init);
830module_exit(ifxmips_gptu_exit);
831

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