target/linux/ifxmips/files-2.6.33/arch/mips/include/asm/mach-ifxmips/ifxmips.h - OpenWrt XBurst Git Source Tree - development environment for Qi Hardware device.

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/*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.

*

*/

#ifndef _IFXMIPS_H__

#define _IFXMIPS_H__

#define ifxmips_r32(reg) __raw_readl(reg)

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#define ifxmips_w32(val, reg) __raw_writel(val, reg)

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#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)

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/*------------ GENERAL */

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#define BOARD_SYSTEM_TYPE "IFXMIPS"

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#define IFXMIPS_SYS_TYPE_LEN 0x100

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#define IOPORT_RESOURCE_START 0x10000000

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#define IOPORT_RESOURCE_END 0xffffffff

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#define IOMEM_RESOURCE_START 0x10000000

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#define IOMEM_RESOURCE_END 0xffffffff

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#define IFXMIPS_FLASH_START 0x10000000

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#define IFXMIPS_FLASH_MAX 0x02000000

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/*------------ ASC0/1 */

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#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)

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#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)

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#define IFXMIPS_ASC_FSTAT 0x0048

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#define IFXMIPS_ASC_TBUF 0x0020

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#define IFXMIPS_ASC_WHBSTATE 0x0018

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#define IFXMIPS_ASC_RBUF 0x0024

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#define IFXMIPS_ASC_STATE 0x0014

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#define IFXMIPS_ASC_IRNCR 0x00F8

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#define IFXMIPS_ASC_CLC 0x0000

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#define IFXMIPS_ASC_PISEL 0x0004

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#define IFXMIPS_ASC_TXFCON 0x0044

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#define IFXMIPS_ASC_RXFCON 0x0040

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#define IFXMIPS_ASC_CON 0x0010

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#define IFXMIPS_ASC_BG 0x0050

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#define IFXMIPS_ASC_IRNREN 0x00F4

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#define IFXMIPS_ASC_CLC_DISS 0x2

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#define ASC_IRNREN_RX_BUF 0x8

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#define ASC_IRNREN_TX_BUF 0x4

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#define ASC_IRNREN_ERR 0x2

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#define ASC_IRNREN_TX 0x1

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#define ASC_IRNCR_TIR 0x4

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#define ASC_IRNCR_RIR 0x2

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#define ASC_IRNCR_EIR 0x4

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#define ASCOPT_CSIZE 0x3

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#define ASCOPT_CS7 0x1

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#define ASCOPT_CS8 0x2

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#define ASCOPT_PARENB 0x4

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#define ASCOPT_STOPB 0x8

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#define ASCOPT_PARODD 0x0

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#define ASCOPT_CREAD 0x20

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#define TXFIFO_FL 1

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#define RXFIFO_FL 1

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#define TXFIFO_FULL 16

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#define ASCCLC_RMCMASK 0x0000FF00

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#define ASCCLC_RMCOFFSET 8

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#define ASCCON_M_8ASYNC 0x0

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#define ASCCON_M_7ASYNC 0x2

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#define ASCCON_ODD 0x00000020

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#define ASCCON_STP 0x00000080

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#define ASCCON_BRS 0x00000100

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#define ASCCON_FDE 0x00000200

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#define ASCCON_R 0x00008000

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#define ASCCON_FEN 0x00020000

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#define ASCCON_ROEN 0x00080000

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#define ASCCON_TOEN 0x00100000

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#define ASCSTATE_PE 0x00010000

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#define ASCSTATE_FE 0x00020000

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#define ASCSTATE_ROE 0x00080000

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#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)

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#define ASCWHBSTATE_CLRREN 0x00000001

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#define ASCWHBSTATE_SETREN 0x00000002

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#define ASCWHBSTATE_CLRPE 0x00000004

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#define ASCWHBSTATE_CLRFE 0x00000008

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#define ASCWHBSTATE_CLRROE 0x00000020

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#define ASCTXFCON_TXFEN 0x0001

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#define ASCTXFCON_TXFFLU 0x0002

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#define ASCTXFCON_TXFITLMASK 0x3F00

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#define ASCTXFCON_TXFITLOFF 8

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#define ASCRXFCON_RXFEN 0x0001

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#define ASCRXFCON_RXFFLU 0x0002

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#define ASCRXFCON_RXFITLMASK 0x3F00

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#define ASCRXFCON_RXFITLOFF 8

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#define ASCFSTAT_RXFFLMASK 0x003F

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#define ASCFSTAT_TXFFLMASK 0x3F00

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#define ASCFSTAT_TXFFLOFF 8

/*------------ RCU */

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#define IFXMIPS_RCU_BASE_ADDR 0xBF203000

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/* reset request */

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#define IFXMIPS_RCU_RST ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010))

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#define IFXMIPS_RCU_RST_CPU1 (1 << 3)

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#define IFXMIPS_RCU_RST_ALL 0x40000000

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#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)

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#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)

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#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)

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/*------------ GPTU */

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#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300

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/* clock control register */

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#define IFXMIPS_GPTU_GPT_CLC ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))

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/* captur reload register */

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#define IFXMIPS_GPTU_GPT_CAPREL ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))

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/* timer 6 control register */

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#define IFXMIPS_GPTU_GPT_T6CON ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))

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/*------------ EBU */

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#define IFXMIPS_EBU_BASE_ADDR 0xBE105300

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/* bus configuration register */

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#define IFXMIPS_EBU_BUSCON0 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060))

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#define IFXMIPS_EBU_PCC_CON ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090))

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#define IFXMIPS_EBU_PCC_IEN ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))

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#define IFXMIPS_EBU_PCC_ISTAT ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))

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#define IFXMIPS_EBU_BUSCON1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0064))

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#define IFXMIPS_EBU_ADDRSEL1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0024))

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/*------------ CGU */

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#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000)

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#define IFXMIPS_CGU_PLL0_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004))

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#define IFXMIPS_CGU_PLL1_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008))

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#define IFXMIPS_CGU_PLL2_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C))

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#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))

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#define IFXMIPS_CGU_UPDATE ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014))

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#define IFXMIPS_CGU_IF_CLK ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))

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#define IFXMIPS_CGU_OSC_CON ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C))

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#define IFXMIPS_CGU_SMD ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020))

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#define IFXMIPS_CGU_CT1SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028))

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#define IFXMIPS_CGU_CT2SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C))

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#define IFXMIPS_CGU_PCMCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030))

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#define IFXMIPS_CGU_PCI_CR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))

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#define IFXMIPS_CGU_PD_PC ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038))

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#define IFXMIPS_CGU_FMR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C))

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/* clock mux */

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#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))

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#define IFXMIPS_CGU_IFCCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))

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#define IFXMIPS_CGU_PCICR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))

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#define CLOCK_60M 60000000

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#define CLOCK_83M 83333333

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#define CLOCK_111M 111111111

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#define CLOCK_133M 133333333

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#define CLOCK_167M 166666667

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#define CLOCK_333M 333333333

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/*------------ CGU */

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#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)

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#define IFXMIPS_PMU_PWDCR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C))

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#define IFXMIPS_PMU_PWDSR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020))

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/*------------ ICU */

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#define IFXMIPS_ICU_BASE_ADDR 0xBF880200

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#define IFXMIPS_ICU_IM0_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000))

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#define IFXMIPS_ICU_IM0_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008))

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#define IFXMIPS_ICU_IM0_IOSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010))

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#define IFXMIPS_ICU_IM0_IRSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018))

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#define IFXMIPS_ICU_IM0_IMR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020))

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#define IFXMIPS_ICU_IM1_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028))

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#define IFXMIPS_ICU_IM2_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058))

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#define IFXMIPS_ICU_IM3_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080))

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#define IFXMIPS_ICU_IM4_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))

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#define IFXMIPS_ICU_IM5_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))

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#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)

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/*------------ ETOP */

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#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000

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#define IFXMIPS_PPE32_SIZE 0x40000

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#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600

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#define IFXMIPS_PPE32_MEM_MAP ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))

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#define IFXMIPS_PPE32_SRST ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))

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#define MII_MODE 1

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#define REV_MII_MODE 2

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/* mdio access */

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#define IFXMIPS_PPE32_MDIO_CFG ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))

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#define IFXMIPS_PPE32_MDIO_ACC ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))

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#define MDIO_ACC_REQUEST 0x80000000

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#define MDIO_ACC_READ 0x40000000

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#define MDIO_ACC_ADDR_MASK 0x1f

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#define MDIO_ACC_ADDR_OFFSET 0x15

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#define MDIO_ACC_REG_MASK 0x1f

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#define MDIO_ACC_REG_OFFSET 0x10

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#define MDIO_ACC_VAL_MASK 0xffff

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/* configuration */

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#define IFXMIPS_PPE32_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808))

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#define PPE32_MII_MASK 0xfffffffc

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#define PPE32_MII_NORMAL 0x8

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#define PPE32_MII_REVERSE 0xe

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/* packet length */

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#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820))

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#define PPE32_PLEN_OVER 0x5ee

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#define PPE32_PLEN_UNDER 0x400000

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/* enet */

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#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840))

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#define PPE32_CGEN 0x800

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/*------------ DMA */

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#define IFXMIPS_DMA_BASE_ADDR 0xBE104100

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#define IFXMIPS_DMA_CS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18))

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#define IFXMIPS_DMA_CIE ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C))

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#define IFXMIPS_DMA_IRNEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4))

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#define IFXMIPS_DMA_CCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C))

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#define IFXMIPS_DMA_CIS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28))

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#define IFXMIPS_DMA_CDLEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24))

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#define IFXMIPS_DMA_PS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40))

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#define IFXMIPS_DMA_PCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44))

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#define IFXMIPS_DMA_CTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10))

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#define IFXMIPS_DMA_CPOLL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14))

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#define IFXMIPS_DMA_CDBA ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20))

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/*------------ PCI */

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#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)

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#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))

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#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))

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#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))

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#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))

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#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))

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#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))

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#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))

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#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))

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#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))

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#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))

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#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))

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#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))

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#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))

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#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))

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#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))

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#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))

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#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))

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#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))

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#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))

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#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)

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#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))

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#define PCI_MASTER0_REQ_MASK_2BITS 8

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#define PCI_MASTER1_REQ_MASK_2BITS 10

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#define PCI_MASTER2_REQ_MASK_2BITS 12

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#define INTERNAL_ARB_ENABLE_BIT 0

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/*------------ WDT */

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#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)

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#define IFXMIPS_WDT_SIZE 0x400

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#define IFXMIPS_BIU_WDT_CR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))

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#define IFXMIPS_BIU_WDT_SR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))

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/*------------ LED */

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#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)

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#define IFXMIPS_LED_CON0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000))

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#define IFXMIPS_LED_CON1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004))

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#define IFXMIPS_LED_CPU0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008))

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#define IFXMIPS_LED_CPU1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C))

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#define IFXMIPS_LED_AR ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010))

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#define LED_CON0_SWU (1 << 31)

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#define LED_CON0_AD1 (1 << 25)

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#define LED_CON0_AD0 (1 << 24)

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#define IFXMIPS_LED_2HZ (0)

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#define IFXMIPS_LED_4HZ (1 << 23)

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#define IFXMIPS_LED_8HZ (2 << 23)

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#define IFXMIPS_LED_10HZ (3 << 23)

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#define IFXMIPS_LED_MASK (0xf << 23)

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#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)

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#define IFXMIPS_LED_UPD_MASK (3 << 30)

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#define IFXMIPS_LED_ADSL_SRC (3 << 24)

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#define IFXMIPS_LED_GROUP0 (1 << 0)

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#define IFXMIPS_LED_GROUP1 (1 << 1)

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#define IFXMIPS_LED_GROUP2 (1 << 2)

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#define IFXMIPS_LED_RISING 0

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#define IFXMIPS_LED_FALLING (1 << 26)

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#define IFXMIPS_LED_EDGE_MASK (1 << 26)

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/*------------ GPIO */

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#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)

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#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))

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#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))

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#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))

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#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))

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#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))

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#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))

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#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))

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#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))

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#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))

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#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))

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#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))

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#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))

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#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))

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#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))

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#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))

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#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))

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#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))

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#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))

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/*------------ SSC */

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#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)

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#define IFXMIPS_SSC_CLC ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000))

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#define IFXMIPS_SSC_IRN ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))

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#define IFXMIPS_SSC_SFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060))

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#define IFXMIPS_SSC_WHBGPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078))

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#define IFXMIPS_SSC_STATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014))

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#define IFXMIPS_SSC_WHBSTATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018))

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#define IFXMIPS_SSC_FSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038))

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#define IFXMIPS_SSC_ID ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008))

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#define IFXMIPS_SSC_TB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020))

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#define IFXMIPS_SSC_RXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030))

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#define IFXMIPS_SSC_TXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034))

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#define IFXMIPS_SSC_CON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010))

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#define IFXMIPS_SSC_GPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074))

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#define IFXMIPS_SSC_RB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024))

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#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))

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#define IFXMIPS_SSC_GPOCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070))

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#define IFXMIPS_SSC_BR ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040))

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#define IFXMIPS_SSC_RXREQ ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080))

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#define IFXMIPS_SSC_SFSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064))

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#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))

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/*------------ MEI */

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#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000)

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#define MEI_DATA_XFR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000))

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#define MEI_VERSION ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004))

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#define MEI_ARC_GP_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008))

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#define MEI_DATA_XFR_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C))

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#define MEI_XFR_ADDR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010))

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#define MEI_MAX_WAIT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014))

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#define MEI_TO_ARC_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018))

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#define ARC_TO_MEI_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C))

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#define ARC_TO_MEI_INT_MASK ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020))

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#define MEI_DEBUG_WAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024))

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#define MEI_DEBUG_RAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028))

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#define MEI_DEBUG_DATA ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C))

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#define MEI_DEBUG_DEC ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030))

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#define MEI_CONFIG ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034))

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#define MEI_RST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038))

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#define MEI_DBG_MASTER ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C))

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#define MEI_CLK_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040))

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#define MEI_BIST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044))

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#define MEI_BIST_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048))

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#define MEI_XDATA_BASE_SH ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c))

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#define MEI_XDATA_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050))

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#define MEI_XMEM_BAR_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))

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#define MEI_XMEM_BAR0 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))

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#define MEI_XMEM_BAR1 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058))

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#define MEI_XMEM_BAR2 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C))

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#define MEI_XMEM_BAR3 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060))

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#define MEI_XMEM_BAR4 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064))

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#define MEI_XMEM_BAR5 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068))

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#define MEI_XMEM_BAR6 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C))

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#define MEI_XMEM_BAR7 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070))

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#define MEI_XMEM_BAR8 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074))

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#define MEI_XMEM_BAR9 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078))

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#define MEI_XMEM_BAR10 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C))

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#define MEI_XMEM_BAR11 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080))

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#define MEI_XMEM_BAR12 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084))

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#define MEI_XMEM_BAR13 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088))

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#define MEI_XMEM_BAR14 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C))

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#define MEI_XMEM_BAR15 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090))

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#define MEI_XMEM_BAR16 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094))

436

437

438

/*------------ DEU */

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#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)

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#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))

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#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))

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#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))

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#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))

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#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))

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#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))

448

#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))

449

#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))

450

#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))

451

#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))

452

#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))

453

#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))

454

#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))

455

#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))

456

#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))

457

#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))

458

#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))

459

#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))

460

#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))

461

#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))

462

#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))

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#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))

464

#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))

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#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))

466

#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))

467

#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))

468

#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))

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#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))

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#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))

471

#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))

472

#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))

473

#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))

474

#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))

475

#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))

476

477

/*------------ FUSE */

478

479

#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)

480

481

482

/*------------ MPS */

483

484

#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)

485

#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))

486

487

#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))

488

#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))

489

#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))

490

#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))

491

#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))

492

#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))

493

#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))

494

#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))

495

#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))

496

#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))

497

#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))

498

#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))

499

#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))

500

#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))

501

#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))

502

#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))

503

#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))

504

#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))

505

#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))

506

#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))

507

#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))

508

#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))

509

#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))

510

#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))

511

#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))

512

513

#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))

514

#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)

515

#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))

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#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)

517

#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))

518

#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)

519

520

#endif

521

OpenWrt XBurst

OpenWrt XBurst Git Source Tree

Root/target/linux/ifxmips/files-2.6.33/arch/mips/include/asm/mach-ifxmips/ifxmips.h

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