Root/target/linux/ifxmips/patches-2.6.30/120-serial.patch

1Index: linux-2.6.30.10/drivers/serial/Kconfig
2===================================================================
3--- linux-2.6.30.10.orig/drivers/serial/Kconfig 2009-12-04 07:00:07.000000000 +0100
4+++ linux-2.6.30.10/drivers/serial/Kconfig 2010-03-18 12:24:20.000000000 +0100
5@@ -1365,6 +1365,14 @@
6     help
7       Support for Console on the NWP serial ports.
8 
9+config SERIAL_IFXMIPS
10+ bool "IFXMips serial driver"
11+ depends on IFXMIPS
12+ select SERIAL_CORE
13+ select SERIAL_CORE_CONSOLE
14+ help
15+ Driver for the ifxmipss built in ASC hardware
16+
17 config SERIAL_QE
18     tristate "Freescale QUICC Engine serial port support"
19     depends on QUICC_ENGINE
20Index: linux-2.6.30.10/drivers/serial/Makefile
21===================================================================
22--- linux-2.6.30.10.orig/drivers/serial/Makefile 2009-12-04 07:00:07.000000000 +0100
23+++ linux-2.6.30.10/drivers/serial/Makefile 2010-03-18 12:24:20.000000000 +0100
24@@ -77,3 +77,4 @@
25 obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
26 obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
27 obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
28+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o
29Index: linux-2.6.30.10/drivers/serial/ifxmips_asc.c
30===================================================================
31--- /dev/null 1970-01-01 00:00:00.000000000 +0000
32+++ linux-2.6.30.10/drivers/serial/ifxmips_asc.c 2010-03-18 14:04:58.000000000 +0100
33@@ -0,0 +1,555 @@
34+/*
35+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
36+ *
37+ * This program is free software; you can redistribute it and/or modify
38+ * it under the terms of the GNU General Public License as published by
39+ * the Free Software Foundation; either version 2 of the License, or
40+ * (at your option) any later version.
41+ *
42+ * This program is distributed in the hope that it will be useful,
43+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
44+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45+ * GNU General Public License for more details.
46+ *
47+ * You should have received a copy of the GNU General Public License
48+ * along with this program; if not, write to the Free Software
49+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50+ *
51+ * Copyright (C) 2004 Infineon IFAP DC COM CPE
52+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
53+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
54+ */
55+
56+#include <linux/module.h>
57+#include <linux/errno.h>
58+#include <linux/signal.h>
59+#include <linux/sched.h>
60+#include <linux/interrupt.h>
61+#include <linux/tty.h>
62+#include <linux/tty_flip.h>
63+#include <linux/major.h>
64+#include <linux/string.h>
65+#include <linux/fcntl.h>
66+#include <linux/ptrace.h>
67+#include <linux/ioport.h>
68+#include <linux/mm.h>
69+#include <linux/slab.h>
70+#include <linux/init.h>
71+#include <linux/circ_buf.h>
72+#include <linux/serial.h>
73+#include <linux/serial_core.h>
74+#include <linux/console.h>
75+#include <linux/sysrq.h>
76+#include <linux/irq.h>
77+#include <linux/platform_device.h>
78+#include <linux/io.h>
79+#include <linux/uaccess.h>
80+#include <linux/bitops.h>
81+
82+#include <asm/system.h>
83+
84+#include <ifxmips.h>
85+#include <ifxmips_irq.h>
86+
87+#define PORT_IFXMIPSASC 111
88+
89+#include <linux/serial_core.h>
90+
91+#define UART_DUMMY_UER_RX 1
92+
93+static void ifxmipsasc_tx_chars(struct uart_port *port);
94+extern void prom_printf(const char *fmt, ...);
95+static struct uart_port ifxmipsasc_port[2];
96+static struct uart_driver ifxmipsasc_reg;
97+extern unsigned int ifxmips_get_fpi_hz(void);
98+
99+static void ifxmipsasc_stop_tx(struct uart_port *port)
100+{
101+ return;
102+}
103+
104+static void ifxmipsasc_start_tx(struct uart_port *port)
105+{
106+ unsigned long flags;
107+ local_irq_save(flags);
108+ ifxmipsasc_tx_chars(port);
109+ local_irq_restore(flags);
110+ return;
111+}
112+
113+static void ifxmipsasc_stop_rx(struct uart_port *port)
114+{
115+ ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
116+}
117+
118+static void ifxmipsasc_enable_ms(struct uart_port *port)
119+{
120+}
121+
122+#include <linux/version.h>
123+
124+static void ifxmipsasc_rx_chars(struct uart_port *port)
125+{
126+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26))
127+ struct tty_struct *tty = port->info->port.tty;
128+#else
129+ struct tty_struct *tty = port->info->tty;
130+#endif
131+ unsigned int ch = 0, rsr = 0, fifocnt;
132+
133+ fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
134+ while (fifocnt--) {
135+ u8 flag = TTY_NORMAL;
136+ ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
137+ rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
138+ tty_flip_buffer_push(tty);
139+ port->icount.rx++;
140+
141+ /*
142+ * Note that the error handling code is
143+ * out of the main execution path
144+ */
145+ if (rsr & ASCSTATE_ANY) {
146+ if (rsr & ASCSTATE_PE) {
147+ port->icount.parity++;
148+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
149+ } else if (rsr & ASCSTATE_FE) {
150+ port->icount.frame++;
151+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
152+ }
153+ if (rsr & ASCSTATE_ROE) {
154+ port->icount.overrun++;
155+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
156+ }
157+
158+ rsr &= port->read_status_mask;
159+
160+ if (rsr & ASCSTATE_PE)
161+ flag = TTY_PARITY;
162+ else if (rsr & ASCSTATE_FE)
163+ flag = TTY_FRAME;
164+ }
165+
166+ if ((rsr & port->ignore_status_mask) == 0)
167+ tty_insert_flip_char(tty, ch, flag);
168+
169+ if (rsr & ASCSTATE_ROE)
170+ /*
171+ * Overrun is special, since it's reported
172+ * immediately, and doesn't affect the current
173+ * character
174+ */
175+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
176+ }
177+ if (ch != 0)
178+ tty_flip_buffer_push(tty);
179+ return;
180+}
181+
182+
183+static void ifxmipsasc_tx_chars(struct uart_port *port)
184+{
185+ struct circ_buf *xmit = &port->info->xmit;
186+ if (uart_tx_stopped(port)) {
187+ ifxmipsasc_stop_tx(port);
188+ return;
189+ }
190+
191+ while (((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
192+ >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) {
193+ if (port->x_char) {
194+ ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
195+ port->icount.tx++;
196+ port->x_char = 0;
197+ continue;
198+ }
199+
200+ if (uart_circ_empty(xmit))
201+ break;
202+
203+ ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
204+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
205+ port->icount.tx++;
206+ }
207+
208+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
209+ uart_write_wakeup(port);
210+}
211+
212+static irqreturn_t ifxmipsasc_tx_int(int irq, void *_port)
213+{
214+ struct uart_port *port = (struct uart_port *)_port;
215+ ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
216+ ifxmipsasc_start_tx(port);
217+ ifxmips_mask_and_ack_irq(irq);
218+ return IRQ_HANDLED;
219+}
220+
221+static irqreturn_t ifxmipsasc_er_int(int irq, void *_port)
222+{
223+ struct uart_port *port = (struct uart_port *)_port;
224+ /* clear any pending interrupts */
225+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
226+ ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
227+ return IRQ_HANDLED;
228+}
229+
230+static irqreturn_t ifxmipsasc_rx_int(int irq, void *_port)
231+{
232+ struct uart_port *port = (struct uart_port *)_port;
233+ ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
234+ ifxmipsasc_rx_chars((struct uart_port *)port);
235+ ifxmips_mask_and_ack_irq(irq);
236+ return IRQ_HANDLED;
237+}
238+
239+static unsigned int ifxmipsasc_tx_empty(struct uart_port *port)
240+{
241+ int status;
242+ status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
243+ return status ? 0 : TIOCSER_TEMT;
244+}
245+
246+static unsigned int ifxmipsasc_get_mctrl(struct uart_port *port)
247+{
248+ return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
249+}
250+
251+static void ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
252+{
253+}
254+
255+static void ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
256+{
257+}
258+
259+static int ifxmipsasc_startup(struct uart_port *port)
260+{
261+ int retval;
262+
263+ port->uartclk = ifxmips_get_fpi_hz();
264+
265+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
266+ ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
267+ ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
268+ ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
269+ ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
270+ wmb();
271+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
272+
273+ retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
274+ if (retval) {
275+ printk(KERN_ERR "failed to request ifxmipsasc_tx_int\n");
276+ return retval;
277+ }
278+
279+ retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
280+ if (retval) {
281+ printk(KERN_ERR "failed to request ifxmipsasc_rx_int\n");
282+ goto err1;
283+ }
284+
285+ retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
286+ if (retval) {
287+ printk(KERN_ERR "failed to request ifxmipsasc_er_int\n");
288+ goto err2;
289+ }
290+
291+ ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
292+ return 0;
293+
294+err2:
295+ free_irq(port->irq + 2, port);
296+err1:
297+ free_irq(port->irq, port);
298+ return retval;
299+}
300+
301+static void ifxmipsasc_shutdown(struct uart_port *port)
302+{
303+ free_irq(port->irq, port);
304+ free_irq(port->irq + 2, port);
305+ free_irq(port->irq + 3, port);
306+
307+ ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
308+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
309+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
310+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
311+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
312+}
313+
314+static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
315+{
316+ unsigned int cflag;
317+ unsigned int iflag;
318+ unsigned int quot;
319+ unsigned int baud;
320+ unsigned int con = 0;
321+ unsigned long flags;
322+
323+ cflag = new->c_cflag;
324+ iflag = new->c_iflag;
325+
326+ switch (cflag & CSIZE) {
327+ case CS7:
328+ con = ASCCON_M_7ASYNC;
329+ break;
330+
331+ case CS5:
332+ case CS6:
333+ default:
334+ con = ASCCON_M_8ASYNC;
335+ break;
336+ }
337+
338+ if (cflag & CSTOPB)
339+ con |= ASCCON_STP;
340+
341+ if (cflag & PARENB) {
342+ if (!(cflag & PARODD))
343+ con &= ~ASCCON_ODD;
344+ else
345+ con |= ASCCON_ODD;
346+ }
347+
348+ port->read_status_mask = ASCSTATE_ROE;
349+ if (iflag & INPCK)
350+ port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
351+
352+ port->ignore_status_mask = 0;
353+ if (iflag & IGNPAR)
354+ port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
355+
356+ if (iflag & IGNBRK) {
357+ /*
358+ * If we're ignoring parity and break indicators,
359+ * ignore overruns too (for real raw support).
360+ */
361+ if (iflag & IGNPAR)
362+ port->ignore_status_mask |= ASCSTATE_ROE;
363+ }
364+
365+ if ((cflag & CREAD) == 0)
366+ port->ignore_status_mask |= UART_DUMMY_UER_RX;
367+
368+ /* set error signals - framing, parity and overrun, enable receiver */
369+ con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
370+
371+ local_irq_save(flags);
372+
373+ /* set up CON */
374+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
375+
376+ /* Set baud rate - take a divider of 2 into account */
377+ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
378+ quot = uart_get_divisor(port, baud);
379+ quot = quot / 2 - 1;
380+
381+ /* disable the baudrate generator */
382+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
383+
384+ /* make sure the fractional divider is off */
385+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
386+
387+ /* set up to use divisor of 2 */
388+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
389+
390+ /* now we can write the new baudrate into the register */
391+ ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
392+
393+ /* turn the baudrate generator back on */
394+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
395+
396+ /* enable rx */
397+ ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
398+
399+ local_irq_restore(flags);
400+}
401+
402+static const char *ifxmipsasc_type(struct uart_port *port)
403+{
404+ if (port->type == PORT_IFXMIPSASC) {
405+ if (port->membase == (void *)IFXMIPS_ASC_BASE_ADDR)
406+ return "asc0";
407+ else
408+ return "asc1";
409+ } else {
410+ return NULL;
411+ }
412+}
413+
414+static void ifxmipsasc_release_port(struct uart_port *port)
415+{
416+}
417+
418+static int ifxmipsasc_request_port(struct uart_port *port)
419+{
420+ return 0;
421+}
422+
423+static void ifxmipsasc_config_port(struct uart_port *port, int flags)
424+{
425+ if (flags & UART_CONFIG_TYPE) {
426+ port->type = PORT_IFXMIPSASC;
427+ ifxmipsasc_request_port(port);
428+ }
429+}
430+
431+static int ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
432+{
433+ int ret = 0;
434+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
435+ ret = -EINVAL;
436+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
437+ ret = -EINVAL;
438+ if (ser->baud_base < 9600)
439+ ret = -EINVAL;
440+ return ret;
441+}
442+
443+static struct uart_ops ifxmipsasc_pops = {
444+ .tx_empty = ifxmipsasc_tx_empty,
445+ .set_mctrl = ifxmipsasc_set_mctrl,
446+ .get_mctrl = ifxmipsasc_get_mctrl,
447+ .stop_tx = ifxmipsasc_stop_tx,
448+ .start_tx = ifxmipsasc_start_tx,
449+ .stop_rx = ifxmipsasc_stop_rx,
450+ .enable_ms = ifxmipsasc_enable_ms,
451+ .break_ctl = ifxmipsasc_break_ctl,
452+ .startup = ifxmipsasc_startup,
453+ .shutdown = ifxmipsasc_shutdown,
454+ .set_termios = ifxmipsasc_set_termios,
455+ .type = ifxmipsasc_type,
456+ .release_port = ifxmipsasc_release_port,
457+ .request_port = ifxmipsasc_request_port,
458+ .config_port = ifxmipsasc_config_port,
459+ .verify_port = ifxmipsasc_verify_port,
460+};
461+
462+static struct uart_port ifxmipsasc_port[2] = {
463+ {
464+ .membase = (void *)IFXMIPS_ASC_BASE_ADDR,
465+ .mapbase = IFXMIPS_ASC_BASE_ADDR,
466+ .iotype = SERIAL_IO_MEM,
467+ .irq = IFXMIPSASC_TIR(0),
468+ .uartclk = 0,
469+ .fifosize = 16,
470+ .type = PORT_IFXMIPSASC,
471+ .ops = &ifxmipsasc_pops,
472+ .flags = ASYNC_BOOT_AUTOCONF,
473+ .line = 0
474+ }, {
475+ .membase = (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
476+ .mapbase = IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
477+ .iotype = SERIAL_IO_MEM,
478+ .irq = IFXMIPSASC_TIR(1),
479+ .uartclk = 0,
480+ .fifosize = 16,
481+ .type = PORT_IFXMIPSASC,
482+ .ops = &ifxmipsasc_pops,
483+ .flags = ASYNC_BOOT_AUTOCONF,
484+ .line = 1
485+ }
486+};
487+
488+static void ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
489+{
490+ int port = co->index;
491+ int i, fifocnt;
492+ unsigned long flags;
493+ local_irq_save(flags);
494+ for (i = 0; i < count; i++) {
495+ do {
496+ fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
497+ >> ASCFSTAT_TXFFLOFF;
498+ } while (fifocnt == TXFIFO_FULL);
499+
500+ if (s[i] == '\0')
501+ break;
502+
503+ if (s[i] == '\n') {
504+ ifxmips_w32('\r', (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
505+ do {
506+ fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
507+ >> ASCFSTAT_TXFFLOFF;
508+ } while (fifocnt == TXFIFO_FULL);
509+ }
510+ ifxmips_w32(s[i], (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
511+ }
512+
513+ local_irq_restore(flags);
514+}
515+
516+static int __init ifxmipsasc_console_setup(struct console *co, char *options)
517+{
518+ int port = co->index;
519+ int baud = 115200;
520+ int bits = 8;
521+ int parity = 'n';
522+ int flow = 'n';
523+ ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
524+ ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
525+ if (options)
526+ uart_parse_options(options, &baud, &parity, &bits, &flow);
527+ return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
528+}
529+
530+static struct console ifxmipsasc_console[2] =
531+{
532+ {
533+ .name = "ttyS",
534+ .write = ifxmipsasc_console_write,
535+ .device = uart_console_device,
536+ .setup = ifxmipsasc_console_setup,
537+ .flags = CON_PRINTBUFFER,
538+ .index = 0,
539+ .data = &ifxmipsasc_reg,
540+ }, {
541+ .name = "ttyS",
542+ .write = ifxmipsasc_console_write,
543+ .device = uart_console_device,
544+ .setup = ifxmipsasc_console_setup,
545+ .flags = CON_PRINTBUFFER,
546+ .index = 1,
547+ .data = &ifxmipsasc_reg,
548+ }
549+};
550+
551+static int __init ifxmipsasc_console_init(void)
552+{
553+ register_console(&ifxmipsasc_console[0]);
554+ register_console(&ifxmipsasc_console[1]);
555+ return 0;
556+}
557+console_initcall(ifxmipsasc_console_init);
558+
559+static struct uart_driver ifxmipsasc_reg = {
560+ .owner = THIS_MODULE,
561+ .driver_name = "serial",
562+ .dev_name = "ttyS",
563+ .major = TTY_MAJOR,
564+ .minor = 64,
565+ .nr = 2,
566+ .cons = &ifxmipsasc_console[1],
567+};
568+
569+int __init ifxmipsasc_init(void)
570+{
571+ int ret;
572+ uart_register_driver(&ifxmipsasc_reg);
573+ ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
574+ ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
575+ return 0;
576+}
577+
578+void __exit ifxmipsasc_exit(void)
579+{
580+ uart_unregister_driver(&ifxmipsasc_reg);
581+}
582+
583+module_init(ifxmipsasc_init);
584+module_exit(ifxmipsasc_exit);
585+
586+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
587+MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
588+MODULE_LICENSE("GPL");
589

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