| 1 | Index: linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c |
| 2 | =================================================================== |
| 3 | --- linux-2.6.32.10.orig/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:39.000000000 +0200 |
| 4 | +++ linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:52.000000000 +0200 |
| 5 | @@ -22,6 +22,22 @@ |
| 6 | |
| 7 | #ifndef CONFIG_MIPS_MT_SMTC |
| 8 | |
| 9 | +/* |
| 10 | + * Compare interrupt can be routed and latched outside the core, |
| 11 | + * so a single execution hazard barrier may not be enough to give |
| 12 | + * it time to clear as seen in the Cause register. 4 time the |
| 13 | + * pipeline depth seems reasonably conservative, and empirically |
| 14 | + * works better in configurations with high CPU/bus clock ratios. |
| 15 | + */ |
| 16 | + |
| 17 | +#define compare_change_hazard() \ |
| 18 | + do { \ |
| 19 | + irq_disable_hazard(); \ |
| 20 | + irq_disable_hazard(); \ |
| 21 | + irq_disable_hazard(); \ |
| 22 | + irq_disable_hazard(); \ |
| 23 | + } while (0) |
| 24 | + |
| 25 | static int mips_next_event(unsigned long delta, |
| 26 | struct clock_event_device *evt) |
| 27 | { |
| 28 | @@ -31,6 +47,7 @@ |
| 29 | cnt = read_c0_count(); |
| 30 | cnt += delta; |
| 31 | write_c0_compare(cnt); |
| 32 | + compare_change_hazard(); |
| 33 | res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; |
| 34 | return res; |
| 35 | } |
| 36 | |
