| 1 | --- a/arch/powerpc/boot/dts/rb600.dts |
| 2 | +++ b/arch/powerpc/boot/dts/rb600.dts |
| 3 | @@ -0,0 +1,242 @@ |
| 4 | +/* |
| 5 | + * RouterBOARD 600 series Device Tree Source |
| 6 | + * |
| 7 | + * Copyright 2009 Michael Guntsche <mike@it-loops.com> |
| 8 | + * |
| 9 | + * This program is free software; you can redistribute it and/or modify it |
| 10 | + * under the terms of the GNU General Public License as published by the |
| 11 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | + * option) any later version. |
| 13 | + */ |
| 14 | + |
| 15 | +/dts-v1/; |
| 16 | + |
| 17 | +/ { |
| 18 | + model = "RB600"; |
| 19 | + compatible = "MPC83xx"; |
| 20 | + #address-cells = <1>; |
| 21 | + #size-cells = <1>; |
| 22 | + |
| 23 | + aliases { |
| 24 | + ethernet0 = &enet0; |
| 25 | + ethernet1 = &enet1; |
| 26 | + }; |
| 27 | + |
| 28 | + chosen { |
| 29 | + linux,stdout-path = "/soc8343@e0000000/serial@4500"; |
| 30 | + }; |
| 31 | + |
| 32 | + cpus { |
| 33 | + #address-cells = <1>; |
| 34 | + #size-cells = <0>; |
| 35 | + |
| 36 | + PowerPC,8343E@0 { |
| 37 | + device_type = "cpu"; |
| 38 | + reg = <0x0>; |
| 39 | + d-cache-line-size = <0x20>; |
| 40 | + i-cache-line-size = <0x20>; |
| 41 | + d-cache-size = <0x8000>; |
| 42 | + i-cache-size = <0x8000>; |
| 43 | + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob |
| 44 | + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob |
| 45 | + }; |
| 46 | + }; |
| 47 | + |
| 48 | + memory { |
| 49 | + device_type = "memory"; |
| 50 | + reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob |
| 51 | + }; |
| 52 | + |
| 53 | + cf@f9200000 { |
| 54 | + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>; |
| 55 | + interrupt-at-level = <0x0>; |
| 56 | + interrupt-parent = <&ipic>; |
| 57 | + interrupts = <0x16 0x8>; |
| 58 | + lbc_extra_divider = <0x1>; |
| 59 | + reg = <0xf9200000 0x200000>; |
| 60 | + device_type = "rb,cf"; |
| 61 | + }; |
| 62 | + |
| 63 | + cf@f9000000 { |
| 64 | + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>; |
| 65 | + interrupt-at-level = <0x0>; |
| 66 | + interrupt-parent = <&ipic>; |
| 67 | + interrupts = <0x14 0x8>; |
| 68 | + lbc_extra_divider = <0x1>; |
| 69 | + reg = <0xf9000000 0x200000>; |
| 70 | + device_type = "rb,cf"; |
| 71 | + }; |
| 72 | + |
| 73 | + flash { |
| 74 | + reg = <0xff800000 0x20000>; |
| 75 | + }; |
| 76 | + |
| 77 | + nnand { |
| 78 | + reg = <0xf0000000 0x1000>; |
| 79 | + }; |
| 80 | + |
| 81 | + nand { |
| 82 | + ale = <&gpio 0x6>; |
| 83 | + cle = <&gpio 0x5>; |
| 84 | + nce = <&gpio 0x4>; |
| 85 | + rdy = <&gpio 0x3>; |
| 86 | + reg = <0xf8000000 0x1000>; |
| 87 | + device_type = "rb,nand"; |
| 88 | + }; |
| 89 | + |
| 90 | + fancon { |
| 91 | + interrupt-parent = <&ipic>; |
| 92 | + interrupts = <0x17 0x8>; |
| 93 | + sense = <&gpio 0x7>; |
| 94 | + fan_on = <&gpio 0x9>; |
| 95 | + }; |
| 96 | + |
| 97 | + pci0: pci@e0008500 { |
| 98 | + device_type = "pci"; |
| 99 | + compatible = "fsl,mpc8349-pci"; |
| 100 | + reg = <0xe0008500 0x100 0xe0008300 0x8>; |
| 101 | + #address-cells = <3>; |
| 102 | + #size-cells = <2>; |
| 103 | + #interrupt-cells = <1>; |
| 104 | + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>; |
| 105 | + bus-range = <0x0 0x0>; |
| 106 | + interrupt-map = < |
| 107 | + 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8 |
| 108 | + 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 109 | + 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8 |
| 110 | + 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 111 | + 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 112 | + 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8 |
| 113 | + 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8 |
| 114 | + 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8 |
| 115 | + 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8 |
| 116 | + 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 117 | + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 118 | + 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8 |
| 119 | + 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8 |
| 120 | + 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 121 | + 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8 |
| 122 | + 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8 |
| 123 | + 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8 |
| 124 | + 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 125 | + 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 126 | + 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8 |
| 127 | + 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>; |
| 128 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 129 | + interrupt-parent = <&ipic>; |
| 130 | + }; |
| 131 | + |
| 132 | + soc8343@e0000000 { |
| 133 | + #address-cells = <1>; |
| 134 | + #size-cells = <1>; |
| 135 | + device_type = "soc"; |
| 136 | + compatible = "simple-bus"; |
| 137 | + ranges = <0x0 0xe0000000 0x100000>; |
| 138 | + reg = <0xe0000000 0x200>; |
| 139 | + bus-frequency = <0x1>; |
| 140 | + |
| 141 | + led { |
| 142 | + user_led = <0x400 0x8>; |
| 143 | + }; |
| 144 | + |
| 145 | + beeper { |
| 146 | + reg = <0x500 0x100>; |
| 147 | + }; |
| 148 | + |
| 149 | + gpio: gpio@0 { |
| 150 | + reg = <0xc08 0x4>; |
| 151 | + device-id = <0x0>; |
| 152 | + compatible = "gpio"; |
| 153 | + device_type = "gpio"; |
| 154 | + }; |
| 155 | + |
| 156 | + enet0: ethernet@25000 { |
| 157 | + #address-cells = <1>; |
| 158 | + #size-cells = <1>; |
| 159 | + cell-index = <0>; |
| 160 | + phy-handle = <&phy0>; |
| 161 | + tbi-handle = <&tbi0>; |
| 162 | + interrupt-parent = <&ipic>; |
| 163 | + interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; |
| 164 | + local-mac-address = [00 00 00 00 00 00]; |
| 165 | + reg = <0x25000 0x1000>; |
| 166 | + ranges = <0x0 0x25000 0x1000>; |
| 167 | + compatible = "gianfar"; |
| 168 | + model = "TSEC"; |
| 169 | + device_type = "network"; |
| 170 | + |
| 171 | + mdio@520 { |
| 172 | + #address-cells = <1>; |
| 173 | + #size-cells = <0>; |
| 174 | + compatible = "fsl,gianfar-tbi"; |
| 175 | + reg = <0x520 0x20>; |
| 176 | + |
| 177 | + tbi0: tbi-phy@11 { |
| 178 | + reg = <0x11>; |
| 179 | + device_type = "tbi-phy"; |
| 180 | + }; |
| 181 | + }; |
| 182 | + }; |
| 183 | + |
| 184 | + enet1: ethernet@24000 { |
| 185 | + #address-cells = <1>; |
| 186 | + #size-cells = <1>; |
| 187 | + cell-index = <1>; |
| 188 | + phy-handle = <&phy1>; |
| 189 | + tbi-handle = <&tbi1>; |
| 190 | + interrupt-parent = <&ipic>; |
| 191 | + interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; |
| 192 | + local-mac-address = [00 00 00 00 00 00]; |
| 193 | + reg = <0x24000 0x1000>; |
| 194 | + ranges = <0x0 0x24000 0x1000>; |
| 195 | + compatible = "gianfar"; |
| 196 | + model = "TSEC"; |
| 197 | + device_type = "network"; |
| 198 | + |
| 199 | + mdio@520 { |
| 200 | + #size-cells = <0x0>; |
| 201 | + #address-cells = <0x1>; |
| 202 | + reg = <0x520 0x20>; |
| 203 | + compatible = "fsl,gianfar-mdio"; |
| 204 | + |
| 205 | + phy0: ethernet-phy@0 { |
| 206 | + device_type = "ethernet-phy"; |
| 207 | + reg = <0x0>; |
| 208 | + }; |
| 209 | + |
| 210 | + phy1: ethernet-phy@1 { |
| 211 | + device_type = "ethernet-phy"; |
| 212 | + reg = <0x1>; |
| 213 | + }; |
| 214 | + |
| 215 | + tbi1: tbi-phy@11 { |
| 216 | + reg = <0x11>; |
| 217 | + device_type = "tbi-phy"; |
| 218 | + }; |
| 219 | + }; |
| 220 | + }; |
| 221 | + |
| 222 | + ipic: pic@700 { |
| 223 | + interrupt-controller; |
| 224 | + #address-cells = <0>; |
| 225 | + #interrupt-cells = <2>; |
| 226 | + reg = <0x700 0x100>; |
| 227 | + device_type = "ipic"; |
| 228 | + }; |
| 229 | + |
| 230 | + serial@4500 { |
| 231 | + interrupt-parent = <&ipic>; |
| 232 | + interrupts = <0x9 0x8>; |
| 233 | + clock-frequency = <0xfe4f840>; |
| 234 | + reg = <0x4500 0x100>; |
| 235 | + compatible = "ns16550"; |
| 236 | + device_type = "serial"; |
| 237 | + }; |
| 238 | + |
| 239 | + wdt@200 { |
| 240 | + reg = <0x200 0x100>; |
| 241 | + compatible = "mpc83xx_wdt"; |
| 242 | + device_type = "watchdog"; |
| 243 | + }; |
| 244 | + }; |
| 245 | +}; |
| 246 | |
