Root/target/linux/octeon/patches-2.6.30/005-register_defs_octeon_mgmt.patch

1The MGMT ethernet driver uses the AGL, MIXX and SMIX blocks, so we add
2definitions for them.
3
4Signed-off-by: David Daney <ddaney@caviumnetworks.com>
5---
6 arch/mips/include/asm/octeon/cvmx-agl-defs.h | 1194 +++++++++++++++++++++++++
7 arch/mips/include/asm/octeon/cvmx-mixx-defs.h | 248 +++++
8 arch/mips/include/asm/octeon/cvmx-smix-defs.h | 178 ++++
9 3 files changed, 1620 insertions(+), 0 deletions(-)
10 create mode 100644 arch/mips/include/asm/octeon/cvmx-agl-defs.h
11 create mode 100644 arch/mips/include/asm/octeon/cvmx-mixx-defs.h
12 create mode 100644 arch/mips/include/asm/octeon/cvmx-smix-defs.h
13
14--- /dev/null
15+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
16@@ -0,0 +1,1194 @@
17+/***********************license start***************
18+ * Author: Cavium Networks
19+ *
20+ * Contact: support@caviumnetworks.com
21+ * This file is part of the OCTEON SDK
22+ *
23+ * Copyright (c) 2003-2008 Cavium Networks
24+ *
25+ * This file is free software; you can redistribute it and/or modify
26+ * it under the terms of the GNU General Public License, Version 2, as
27+ * published by the Free Software Foundation.
28+ *
29+ * This file is distributed in the hope that it will be useful, but
30+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
31+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
32+ * NONINFRINGEMENT. See the GNU General Public License for more
33+ * details.
34+ *
35+ * You should have received a copy of the GNU General Public License
36+ * along with this file; if not, write to the Free Software
37+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
38+ * or visit http://www.gnu.org/licenses/.
39+ *
40+ * This file may also be available under a different license from Cavium.
41+ * Contact Cavium Networks for more information
42+ ***********************license end**************************************/
43+
44+#ifndef __CVMX_AGL_DEFS_H__
45+#define __CVMX_AGL_DEFS_H__
46+
47+#define CVMX_AGL_GMX_BAD_REG \
48+ CVMX_ADD_IO_SEG(0x00011800E0000518ull)
49+#define CVMX_AGL_GMX_BIST \
50+ CVMX_ADD_IO_SEG(0x00011800E0000400ull)
51+#define CVMX_AGL_GMX_DRV_CTL \
52+ CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
53+#define CVMX_AGL_GMX_INF_MODE \
54+ CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
55+#define CVMX_AGL_GMX_PRTX_CFG(offset) \
56+ CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
57+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
58+ CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
59+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
60+ CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
61+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
62+ CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
63+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
64+ CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
65+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
66+ CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
67+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
68+ CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
69+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
70+ CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
71+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
72+ CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
73+#define CVMX_AGL_GMX_RXX_DECISION(offset) \
74+ CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
75+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
76+ CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
77+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
78+ CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
79+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
80+ CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
81+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
82+ CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
83+#define CVMX_AGL_GMX_RXX_IFG(offset) \
84+ CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
85+#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
86+ CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
87+#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
88+ CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
89+#define CVMX_AGL_GMX_RXX_JABBER(offset) \
90+ CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
91+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
92+ CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
93+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
94+ CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
95+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
96+ CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
97+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
98+ CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
99+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
100+ CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
101+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
102+ CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
103+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
104+ CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
105+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
106+ CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
107+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
108+ CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
109+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
110+ CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
111+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
112+ CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
113+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
114+ CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
115+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
116+ CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
117+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
118+ CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
119+#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
120+ CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
121+#define CVMX_AGL_GMX_RX_PRT_INFO \
122+ CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
123+#define CVMX_AGL_GMX_RX_TX_STATUS \
124+ CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
125+#define CVMX_AGL_GMX_SMACX(offset) \
126+ CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
127+#define CVMX_AGL_GMX_STAT_BP \
128+ CVMX_ADD_IO_SEG(0x00011800E0000520ull)
129+#define CVMX_AGL_GMX_TXX_APPEND(offset) \
130+ CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
131+#define CVMX_AGL_GMX_TXX_CTL(offset) \
132+ CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
133+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
134+ CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
135+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
136+ CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
137+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
138+ CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
139+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
140+ CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
141+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
142+ CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
143+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
144+ CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
145+#define CVMX_AGL_GMX_TXX_STAT0(offset) \
146+ CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
147+#define CVMX_AGL_GMX_TXX_STAT1(offset) \
148+ CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
149+#define CVMX_AGL_GMX_TXX_STAT2(offset) \
150+ CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
151+#define CVMX_AGL_GMX_TXX_STAT3(offset) \
152+ CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
153+#define CVMX_AGL_GMX_TXX_STAT4(offset) \
154+ CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
155+#define CVMX_AGL_GMX_TXX_STAT5(offset) \
156+ CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
157+#define CVMX_AGL_GMX_TXX_STAT6(offset) \
158+ CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
159+#define CVMX_AGL_GMX_TXX_STAT7(offset) \
160+ CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
161+#define CVMX_AGL_GMX_TXX_STAT8(offset) \
162+ CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
163+#define CVMX_AGL_GMX_TXX_STAT9(offset) \
164+ CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
165+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
166+ CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
167+#define CVMX_AGL_GMX_TXX_THRESH(offset) \
168+ CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
169+#define CVMX_AGL_GMX_TX_BP \
170+ CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
171+#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
172+ CVMX_ADD_IO_SEG(0x00011800E0000498ull)
173+#define CVMX_AGL_GMX_TX_IFG \
174+ CVMX_ADD_IO_SEG(0x00011800E0000488ull)
175+#define CVMX_AGL_GMX_TX_INT_EN \
176+ CVMX_ADD_IO_SEG(0x00011800E0000508ull)
177+#define CVMX_AGL_GMX_TX_INT_REG \
178+ CVMX_ADD_IO_SEG(0x00011800E0000500ull)
179+#define CVMX_AGL_GMX_TX_JAM \
180+ CVMX_ADD_IO_SEG(0x00011800E0000490ull)
181+#define CVMX_AGL_GMX_TX_LFSR \
182+ CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
183+#define CVMX_AGL_GMX_TX_OVR_BP \
184+ CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
185+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
186+ CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
187+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
188+ CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
189+
190+union cvmx_agl_gmx_bad_reg {
191+ uint64_t u64;
192+ struct cvmx_agl_gmx_bad_reg_s {
193+ uint64_t reserved_38_63:26;
194+ uint64_t txpsh1:1;
195+ uint64_t txpop1:1;
196+ uint64_t ovrflw1:1;
197+ uint64_t txpsh:1;
198+ uint64_t txpop:1;
199+ uint64_t ovrflw:1;
200+ uint64_t reserved_27_31:5;
201+ uint64_t statovr:1;
202+ uint64_t reserved_23_25:3;
203+ uint64_t loststat:1;
204+ uint64_t reserved_4_21:18;
205+ uint64_t out_ovr:2;
206+ uint64_t reserved_0_1:2;
207+ } s;
208+ struct cvmx_agl_gmx_bad_reg_s cn52xx;
209+ struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
210+ struct cvmx_agl_gmx_bad_reg_cn56xx {
211+ uint64_t reserved_35_63:29;
212+ uint64_t txpsh:1;
213+ uint64_t txpop:1;
214+ uint64_t ovrflw:1;
215+ uint64_t reserved_27_31:5;
216+ uint64_t statovr:1;
217+ uint64_t reserved_23_25:3;
218+ uint64_t loststat:1;
219+ uint64_t reserved_3_21:19;
220+ uint64_t out_ovr:1;
221+ uint64_t reserved_0_1:2;
222+ } cn56xx;
223+ struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
224+};
225+
226+union cvmx_agl_gmx_bist {
227+ uint64_t u64;
228+ struct cvmx_agl_gmx_bist_s {
229+ uint64_t reserved_10_63:54;
230+ uint64_t status:10;
231+ } s;
232+ struct cvmx_agl_gmx_bist_s cn52xx;
233+ struct cvmx_agl_gmx_bist_s cn52xxp1;
234+ struct cvmx_agl_gmx_bist_s cn56xx;
235+ struct cvmx_agl_gmx_bist_s cn56xxp1;
236+};
237+
238+union cvmx_agl_gmx_drv_ctl {
239+ uint64_t u64;
240+ struct cvmx_agl_gmx_drv_ctl_s {
241+ uint64_t reserved_49_63:15;
242+ uint64_t byp_en1:1;
243+ uint64_t reserved_45_47:3;
244+ uint64_t pctl1:5;
245+ uint64_t reserved_37_39:3;
246+ uint64_t nctl1:5;
247+ uint64_t reserved_17_31:15;
248+ uint64_t byp_en:1;
249+ uint64_t reserved_13_15:3;
250+ uint64_t pctl:5;
251+ uint64_t reserved_5_7:3;
252+ uint64_t nctl:5;
253+ } s;
254+ struct cvmx_agl_gmx_drv_ctl_s cn52xx;
255+ struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
256+ struct cvmx_agl_gmx_drv_ctl_cn56xx {
257+ uint64_t reserved_17_63:47;
258+ uint64_t byp_en:1;
259+ uint64_t reserved_13_15:3;
260+ uint64_t pctl:5;
261+ uint64_t reserved_5_7:3;
262+ uint64_t nctl:5;
263+ } cn56xx;
264+ struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
265+};
266+
267+union cvmx_agl_gmx_inf_mode {
268+ uint64_t u64;
269+ struct cvmx_agl_gmx_inf_mode_s {
270+ uint64_t reserved_2_63:62;
271+ uint64_t en:1;
272+ uint64_t reserved_0_0:1;
273+ } s;
274+ struct cvmx_agl_gmx_inf_mode_s cn52xx;
275+ struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
276+ struct cvmx_agl_gmx_inf_mode_s cn56xx;
277+ struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
278+};
279+
280+union cvmx_agl_gmx_prtx_cfg {
281+ uint64_t u64;
282+ struct cvmx_agl_gmx_prtx_cfg_s {
283+ uint64_t reserved_6_63:58;
284+ uint64_t tx_en:1;
285+ uint64_t rx_en:1;
286+ uint64_t slottime:1;
287+ uint64_t duplex:1;
288+ uint64_t speed:1;
289+ uint64_t en:1;
290+ } s;
291+ struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
292+ struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
293+ struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
294+ struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
295+};
296+
297+union cvmx_agl_gmx_rxx_adr_cam0 {
298+ uint64_t u64;
299+ struct cvmx_agl_gmx_rxx_adr_cam0_s {
300+ uint64_t adr:64;
301+ } s;
302+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
303+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
304+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
305+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
306+};
307+
308+union cvmx_agl_gmx_rxx_adr_cam1 {
309+ uint64_t u64;
310+ struct cvmx_agl_gmx_rxx_adr_cam1_s {
311+ uint64_t adr:64;
312+ } s;
313+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
314+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
315+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
316+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
317+};
318+
319+union cvmx_agl_gmx_rxx_adr_cam2 {
320+ uint64_t u64;
321+ struct cvmx_agl_gmx_rxx_adr_cam2_s {
322+ uint64_t adr:64;
323+ } s;
324+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
325+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
326+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
327+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
328+};
329+
330+union cvmx_agl_gmx_rxx_adr_cam3 {
331+ uint64_t u64;
332+ struct cvmx_agl_gmx_rxx_adr_cam3_s {
333+ uint64_t adr:64;
334+ } s;
335+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
336+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
337+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
338+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
339+};
340+
341+union cvmx_agl_gmx_rxx_adr_cam4 {
342+ uint64_t u64;
343+ struct cvmx_agl_gmx_rxx_adr_cam4_s {
344+ uint64_t adr:64;
345+ } s;
346+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
347+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
348+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
349+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
350+};
351+
352+union cvmx_agl_gmx_rxx_adr_cam5 {
353+ uint64_t u64;
354+ struct cvmx_agl_gmx_rxx_adr_cam5_s {
355+ uint64_t adr:64;
356+ } s;
357+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
358+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
359+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
360+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
361+};
362+
363+union cvmx_agl_gmx_rxx_adr_cam_en {
364+ uint64_t u64;
365+ struct cvmx_agl_gmx_rxx_adr_cam_en_s {
366+ uint64_t reserved_8_63:56;
367+ uint64_t en:8;
368+ } s;
369+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
370+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
371+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
372+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
373+};
374+
375+union cvmx_agl_gmx_rxx_adr_ctl {
376+ uint64_t u64;
377+ struct cvmx_agl_gmx_rxx_adr_ctl_s {
378+ uint64_t reserved_4_63:60;
379+ uint64_t cam_mode:1;
380+ uint64_t mcst:2;
381+ uint64_t bcst:1;
382+ } s;
383+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
384+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
385+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
386+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
387+};
388+
389+union cvmx_agl_gmx_rxx_decision {
390+ uint64_t u64;
391+ struct cvmx_agl_gmx_rxx_decision_s {
392+ uint64_t reserved_5_63:59;
393+ uint64_t cnt:5;
394+ } s;
395+ struct cvmx_agl_gmx_rxx_decision_s cn52xx;
396+ struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
397+ struct cvmx_agl_gmx_rxx_decision_s cn56xx;
398+ struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
399+};
400+
401+union cvmx_agl_gmx_rxx_frm_chk {
402+ uint64_t u64;
403+ struct cvmx_agl_gmx_rxx_frm_chk_s {
404+ uint64_t reserved_9_63:55;
405+ uint64_t skperr:1;
406+ uint64_t rcverr:1;
407+ uint64_t lenerr:1;
408+ uint64_t alnerr:1;
409+ uint64_t fcserr:1;
410+ uint64_t jabber:1;
411+ uint64_t maxerr:1;
412+ uint64_t reserved_1_1:1;
413+ uint64_t minerr:1;
414+ } s;
415+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
416+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
417+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
418+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
419+};
420+
421+union cvmx_agl_gmx_rxx_frm_ctl {
422+ uint64_t u64;
423+ struct cvmx_agl_gmx_rxx_frm_ctl_s {
424+ uint64_t reserved_10_63:54;
425+ uint64_t pre_align:1;
426+ uint64_t pad_len:1;
427+ uint64_t vlan_len:1;
428+ uint64_t pre_free:1;
429+ uint64_t ctl_smac:1;
430+ uint64_t ctl_mcst:1;
431+ uint64_t ctl_bck:1;
432+ uint64_t ctl_drp:1;
433+ uint64_t pre_strp:1;
434+ uint64_t pre_chk:1;
435+ } s;
436+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
437+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
438+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
439+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
440+};
441+
442+union cvmx_agl_gmx_rxx_frm_max {
443+ uint64_t u64;
444+ struct cvmx_agl_gmx_rxx_frm_max_s {
445+ uint64_t reserved_16_63:48;
446+ uint64_t len:16;
447+ } s;
448+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
449+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
450+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
451+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
452+};
453+
454+union cvmx_agl_gmx_rxx_frm_min {
455+ uint64_t u64;
456+ struct cvmx_agl_gmx_rxx_frm_min_s {
457+ uint64_t reserved_16_63:48;
458+ uint64_t len:16;
459+ } s;
460+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
461+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
462+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
463+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
464+};
465+
466+union cvmx_agl_gmx_rxx_ifg {
467+ uint64_t u64;
468+ struct cvmx_agl_gmx_rxx_ifg_s {
469+ uint64_t reserved_4_63:60;
470+ uint64_t ifg:4;
471+ } s;
472+ struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
473+ struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
474+ struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
475+ struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
476+};
477+
478+union cvmx_agl_gmx_rxx_int_en {
479+ uint64_t u64;
480+ struct cvmx_agl_gmx_rxx_int_en_s {
481+ uint64_t reserved_20_63:44;
482+ uint64_t pause_drp:1;
483+ uint64_t reserved_16_18:3;
484+ uint64_t ifgerr:1;
485+ uint64_t coldet:1;
486+ uint64_t falerr:1;
487+ uint64_t rsverr:1;
488+ uint64_t pcterr:1;
489+ uint64_t ovrerr:1;
490+ uint64_t reserved_9_9:1;
491+ uint64_t skperr:1;
492+ uint64_t rcverr:1;
493+ uint64_t lenerr:1;
494+ uint64_t alnerr:1;
495+ uint64_t fcserr:1;
496+ uint64_t jabber:1;
497+ uint64_t maxerr:1;
498+ uint64_t reserved_1_1:1;
499+ uint64_t minerr:1;
500+ } s;
501+ struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
502+ struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
503+ struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
504+ struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
505+};
506+
507+union cvmx_agl_gmx_rxx_int_reg {
508+ uint64_t u64;
509+ struct cvmx_agl_gmx_rxx_int_reg_s {
510+ uint64_t reserved_20_63:44;
511+ uint64_t pause_drp:1;
512+ uint64_t reserved_16_18:3;
513+ uint64_t ifgerr:1;
514+ uint64_t coldet:1;
515+ uint64_t falerr:1;
516+ uint64_t rsverr:1;
517+ uint64_t pcterr:1;
518+ uint64_t ovrerr:1;
519+ uint64_t reserved_9_9:1;
520+ uint64_t skperr:1;
521+ uint64_t rcverr:1;
522+ uint64_t lenerr:1;
523+ uint64_t alnerr:1;
524+ uint64_t fcserr:1;
525+ uint64_t jabber:1;
526+ uint64_t maxerr:1;
527+ uint64_t reserved_1_1:1;
528+ uint64_t minerr:1;
529+ } s;
530+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
531+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
532+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
533+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
534+};
535+
536+union cvmx_agl_gmx_rxx_jabber {
537+ uint64_t u64;
538+ struct cvmx_agl_gmx_rxx_jabber_s {
539+ uint64_t reserved_16_63:48;
540+ uint64_t cnt:16;
541+ } s;
542+ struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
543+ struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
544+ struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
545+ struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
546+};
547+
548+union cvmx_agl_gmx_rxx_pause_drop_time {
549+ uint64_t u64;
550+ struct cvmx_agl_gmx_rxx_pause_drop_time_s {
551+ uint64_t reserved_16_63:48;
552+ uint64_t status:16;
553+ } s;
554+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
555+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
556+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
557+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
558+};
559+
560+union cvmx_agl_gmx_rxx_stats_ctl {
561+ uint64_t u64;
562+ struct cvmx_agl_gmx_rxx_stats_ctl_s {
563+ uint64_t reserved_1_63:63;
564+ uint64_t rd_clr:1;
565+ } s;
566+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
567+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
568+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
569+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
570+};
571+
572+union cvmx_agl_gmx_rxx_stats_octs {
573+ uint64_t u64;
574+ struct cvmx_agl_gmx_rxx_stats_octs_s {
575+ uint64_t reserved_48_63:16;
576+ uint64_t cnt:48;
577+ } s;
578+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
579+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
580+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
581+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
582+};
583+
584+union cvmx_agl_gmx_rxx_stats_octs_ctl {
585+ uint64_t u64;
586+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
587+ uint64_t reserved_48_63:16;
588+ uint64_t cnt:48;
589+ } s;
590+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
591+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
592+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
593+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
594+};
595+
596+union cvmx_agl_gmx_rxx_stats_octs_dmac {
597+ uint64_t u64;
598+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
599+ uint64_t reserved_48_63:16;
600+ uint64_t cnt:48;
601+ } s;
602+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
603+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
604+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
605+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
606+};
607+
608+union cvmx_agl_gmx_rxx_stats_octs_drp {
609+ uint64_t u64;
610+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
611+ uint64_t reserved_48_63:16;
612+ uint64_t cnt:48;
613+ } s;
614+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
615+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
616+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
617+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
618+};
619+
620+union cvmx_agl_gmx_rxx_stats_pkts {
621+ uint64_t u64;
622+ struct cvmx_agl_gmx_rxx_stats_pkts_s {
623+ uint64_t reserved_32_63:32;
624+ uint64_t cnt:32;
625+ } s;
626+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
627+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
628+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
629+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
630+};
631+
632+union cvmx_agl_gmx_rxx_stats_pkts_bad {
633+ uint64_t u64;
634+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
635+ uint64_t reserved_32_63:32;
636+ uint64_t cnt:32;
637+ } s;
638+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
639+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
640+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
641+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
642+};
643+
644+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
645+ uint64_t u64;
646+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
647+ uint64_t reserved_32_63:32;
648+ uint64_t cnt:32;
649+ } s;
650+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
651+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
652+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
653+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
654+};
655+
656+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
657+ uint64_t u64;
658+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
659+ uint64_t reserved_32_63:32;
660+ uint64_t cnt:32;
661+ } s;
662+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
663+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
664+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
665+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
666+};
667+
668+union cvmx_agl_gmx_rxx_stats_pkts_drp {
669+ uint64_t u64;
670+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
671+ uint64_t reserved_32_63:32;
672+ uint64_t cnt:32;
673+ } s;
674+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
675+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
676+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
677+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
678+};
679+
680+union cvmx_agl_gmx_rxx_udd_skp {
681+ uint64_t u64;
682+ struct cvmx_agl_gmx_rxx_udd_skp_s {
683+ uint64_t reserved_9_63:55;
684+ uint64_t fcssel:1;
685+ uint64_t reserved_7_7:1;
686+ uint64_t len:7;
687+ } s;
688+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
689+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
690+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
691+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
692+};
693+
694+union cvmx_agl_gmx_rx_bp_dropx {
695+ uint64_t u64;
696+ struct cvmx_agl_gmx_rx_bp_dropx_s {
697+ uint64_t reserved_6_63:58;
698+ uint64_t mark:6;
699+ } s;
700+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
701+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
702+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
703+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
704+};
705+
706+union cvmx_agl_gmx_rx_bp_offx {
707+ uint64_t u64;
708+ struct cvmx_agl_gmx_rx_bp_offx_s {
709+ uint64_t reserved_6_63:58;
710+ uint64_t mark:6;
711+ } s;
712+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
713+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
714+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
715+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
716+};
717+
718+union cvmx_agl_gmx_rx_bp_onx {
719+ uint64_t u64;
720+ struct cvmx_agl_gmx_rx_bp_onx_s {
721+ uint64_t reserved_9_63:55;
722+ uint64_t mark:9;
723+ } s;
724+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
725+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
726+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
727+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
728+};
729+
730+union cvmx_agl_gmx_rx_prt_info {
731+ uint64_t u64;
732+ struct cvmx_agl_gmx_rx_prt_info_s {
733+ uint64_t reserved_18_63:46;
734+ uint64_t drop:2;
735+ uint64_t reserved_2_15:14;
736+ uint64_t commit:2;
737+ } s;
738+ struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
739+ struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
740+ struct cvmx_agl_gmx_rx_prt_info_cn56xx {
741+ uint64_t reserved_17_63:47;
742+ uint64_t drop:1;
743+ uint64_t reserved_1_15:15;
744+ uint64_t commit:1;
745+ } cn56xx;
746+ struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
747+};
748+
749+union cvmx_agl_gmx_rx_tx_status {
750+ uint64_t u64;
751+ struct cvmx_agl_gmx_rx_tx_status_s {
752+ uint64_t reserved_6_63:58;
753+ uint64_t tx:2;
754+ uint64_t reserved_2_3:2;
755+ uint64_t rx:2;
756+ } s;
757+ struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
758+ struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
759+ struct cvmx_agl_gmx_rx_tx_status_cn56xx {
760+ uint64_t reserved_5_63:59;
761+ uint64_t tx:1;
762+ uint64_t reserved_1_3:3;
763+ uint64_t rx:1;
764+ } cn56xx;
765+ struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
766+};
767+
768+union cvmx_agl_gmx_smacx {
769+ uint64_t u64;
770+ struct cvmx_agl_gmx_smacx_s {
771+ uint64_t reserved_48_63:16;
772+ uint64_t smac:48;
773+ } s;
774+ struct cvmx_agl_gmx_smacx_s cn52xx;
775+ struct cvmx_agl_gmx_smacx_s cn52xxp1;
776+ struct cvmx_agl_gmx_smacx_s cn56xx;
777+ struct cvmx_agl_gmx_smacx_s cn56xxp1;
778+};
779+
780+union cvmx_agl_gmx_stat_bp {
781+ uint64_t u64;
782+ struct cvmx_agl_gmx_stat_bp_s {
783+ uint64_t reserved_17_63:47;
784+ uint64_t bp:1;
785+ uint64_t cnt:16;
786+ } s;
787+ struct cvmx_agl_gmx_stat_bp_s cn52xx;
788+ struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
789+ struct cvmx_agl_gmx_stat_bp_s cn56xx;
790+ struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
791+};
792+
793+union cvmx_agl_gmx_txx_append {
794+ uint64_t u64;
795+ struct cvmx_agl_gmx_txx_append_s {
796+ uint64_t reserved_4_63:60;
797+ uint64_t force_fcs:1;
798+ uint64_t fcs:1;
799+ uint64_t pad:1;
800+ uint64_t preamble:1;
801+ } s;
802+ struct cvmx_agl_gmx_txx_append_s cn52xx;
803+ struct cvmx_agl_gmx_txx_append_s cn52xxp1;
804+ struct cvmx_agl_gmx_txx_append_s cn56xx;
805+ struct cvmx_agl_gmx_txx_append_s cn56xxp1;
806+};
807+
808+union cvmx_agl_gmx_txx_ctl {
809+ uint64_t u64;
810+ struct cvmx_agl_gmx_txx_ctl_s {
811+ uint64_t reserved_2_63:62;
812+ uint64_t xsdef_en:1;
813+ uint64_t xscol_en:1;
814+ } s;
815+ struct cvmx_agl_gmx_txx_ctl_s cn52xx;
816+ struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
817+ struct cvmx_agl_gmx_txx_ctl_s cn56xx;
818+ struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
819+};
820+
821+union cvmx_agl_gmx_txx_min_pkt {
822+ uint64_t u64;
823+ struct cvmx_agl_gmx_txx_min_pkt_s {
824+ uint64_t reserved_8_63:56;
825+ uint64_t min_size:8;
826+ } s;
827+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
828+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
829+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
830+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
831+};
832+
833+union cvmx_agl_gmx_txx_pause_pkt_interval {
834+ uint64_t u64;
835+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
836+ uint64_t reserved_16_63:48;
837+ uint64_t interval:16;
838+ } s;
839+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
840+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
841+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
842+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
843+};
844+
845+union cvmx_agl_gmx_txx_pause_pkt_time {
846+ uint64_t u64;
847+ struct cvmx_agl_gmx_txx_pause_pkt_time_s {
848+ uint64_t reserved_16_63:48;
849+ uint64_t time:16;
850+ } s;
851+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
852+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
853+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
854+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
855+};
856+
857+union cvmx_agl_gmx_txx_pause_togo {
858+ uint64_t u64;
859+ struct cvmx_agl_gmx_txx_pause_togo_s {
860+ uint64_t reserved_16_63:48;
861+ uint64_t time:16;
862+ } s;
863+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
864+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
865+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
866+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
867+};
868+
869+union cvmx_agl_gmx_txx_pause_zero {
870+ uint64_t u64;
871+ struct cvmx_agl_gmx_txx_pause_zero_s {
872+ uint64_t reserved_1_63:63;
873+ uint64_t send:1;
874+ } s;
875+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
876+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
877+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
878+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
879+};
880+
881+union cvmx_agl_gmx_txx_soft_pause {
882+ uint64_t u64;
883+ struct cvmx_agl_gmx_txx_soft_pause_s {
884+ uint64_t reserved_16_63:48;
885+ uint64_t time:16;
886+ } s;
887+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
888+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
889+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
890+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
891+};
892+
893+union cvmx_agl_gmx_txx_stat0 {
894+ uint64_t u64;
895+ struct cvmx_agl_gmx_txx_stat0_s {
896+ uint64_t xsdef:32;
897+ uint64_t xscol:32;
898+ } s;
899+ struct cvmx_agl_gmx_txx_stat0_s cn52xx;
900+ struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
901+ struct cvmx_agl_gmx_txx_stat0_s cn56xx;
902+ struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
903+};
904+
905+union cvmx_agl_gmx_txx_stat1 {
906+ uint64_t u64;
907+ struct cvmx_agl_gmx_txx_stat1_s {
908+ uint64_t scol:32;
909+ uint64_t mcol:32;
910+ } s;
911+ struct cvmx_agl_gmx_txx_stat1_s cn52xx;
912+ struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
913+ struct cvmx_agl_gmx_txx_stat1_s cn56xx;
914+ struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
915+};
916+
917+union cvmx_agl_gmx_txx_stat2 {
918+ uint64_t u64;
919+ struct cvmx_agl_gmx_txx_stat2_s {
920+ uint64_t reserved_48_63:16;
921+ uint64_t octs:48;
922+ } s;
923+ struct cvmx_agl_gmx_txx_stat2_s cn52xx;
924+ struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
925+ struct cvmx_agl_gmx_txx_stat2_s cn56xx;
926+ struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
927+};
928+
929+union cvmx_agl_gmx_txx_stat3 {
930+ uint64_t u64;
931+ struct cvmx_agl_gmx_txx_stat3_s {
932+ uint64_t reserved_32_63:32;
933+ uint64_t pkts:32;
934+ } s;
935+ struct cvmx_agl_gmx_txx_stat3_s cn52xx;
936+ struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
937+ struct cvmx_agl_gmx_txx_stat3_s cn56xx;
938+ struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
939+};
940+
941+union cvmx_agl_gmx_txx_stat4 {
942+ uint64_t u64;
943+ struct cvmx_agl_gmx_txx_stat4_s {
944+ uint64_t hist1:32;
945+ uint64_t hist0:32;
946+ } s;
947+ struct cvmx_agl_gmx_txx_stat4_s cn52xx;
948+ struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
949+ struct cvmx_agl_gmx_txx_stat4_s cn56xx;
950+ struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
951+};
952+
953+union cvmx_agl_gmx_txx_stat5 {
954+ uint64_t u64;
955+ struct cvmx_agl_gmx_txx_stat5_s {
956+ uint64_t hist3:32;
957+ uint64_t hist2:32;
958+ } s;
959+ struct cvmx_agl_gmx_txx_stat5_s cn52xx;
960+ struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
961+ struct cvmx_agl_gmx_txx_stat5_s cn56xx;
962+ struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
963+};
964+
965+union cvmx_agl_gmx_txx_stat6 {
966+ uint64_t u64;
967+ struct cvmx_agl_gmx_txx_stat6_s {
968+ uint64_t hist5:32;
969+ uint64_t hist4:32;
970+ } s;
971+ struct cvmx_agl_gmx_txx_stat6_s cn52xx;
972+ struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
973+ struct cvmx_agl_gmx_txx_stat6_s cn56xx;
974+ struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
975+};
976+
977+union cvmx_agl_gmx_txx_stat7 {
978+ uint64_t u64;
979+ struct cvmx_agl_gmx_txx_stat7_s {
980+ uint64_t hist7:32;
981+ uint64_t hist6:32;
982+ } s;
983+ struct cvmx_agl_gmx_txx_stat7_s cn52xx;
984+ struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
985+ struct cvmx_agl_gmx_txx_stat7_s cn56xx;
986+ struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
987+};
988+
989+union cvmx_agl_gmx_txx_stat8 {
990+ uint64_t u64;
991+ struct cvmx_agl_gmx_txx_stat8_s {
992+ uint64_t mcst:32;
993+ uint64_t bcst:32;
994+ } s;
995+ struct cvmx_agl_gmx_txx_stat8_s cn52xx;
996+ struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
997+ struct cvmx_agl_gmx_txx_stat8_s cn56xx;
998+ struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
999+};
1000+
1001+union cvmx_agl_gmx_txx_stat9 {
1002+ uint64_t u64;
1003+ struct cvmx_agl_gmx_txx_stat9_s {
1004+ uint64_t undflw:32;
1005+ uint64_t ctl:32;
1006+ } s;
1007+ struct cvmx_agl_gmx_txx_stat9_s cn52xx;
1008+ struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
1009+ struct cvmx_agl_gmx_txx_stat9_s cn56xx;
1010+ struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
1011+};
1012+
1013+union cvmx_agl_gmx_txx_stats_ctl {
1014+ uint64_t u64;
1015+ struct cvmx_agl_gmx_txx_stats_ctl_s {
1016+ uint64_t reserved_1_63:63;
1017+ uint64_t rd_clr:1;
1018+ } s;
1019+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1020+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1021+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1022+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1023+};
1024+
1025+union cvmx_agl_gmx_txx_thresh {
1026+ uint64_t u64;
1027+ struct cvmx_agl_gmx_txx_thresh_s {
1028+ uint64_t reserved_6_63:58;
1029+ uint64_t cnt:6;
1030+ } s;
1031+ struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1032+ struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1033+ struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1034+ struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1035+};
1036+
1037+union cvmx_agl_gmx_tx_bp {
1038+ uint64_t u64;
1039+ struct cvmx_agl_gmx_tx_bp_s {
1040+ uint64_t reserved_2_63:62;
1041+ uint64_t bp:2;
1042+ } s;
1043+ struct cvmx_agl_gmx_tx_bp_s cn52xx;
1044+ struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1045+ struct cvmx_agl_gmx_tx_bp_cn56xx {
1046+ uint64_t reserved_1_63:63;
1047+ uint64_t bp:1;
1048+ } cn56xx;
1049+ struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1050+};
1051+
1052+union cvmx_agl_gmx_tx_col_attempt {
1053+ uint64_t u64;
1054+ struct cvmx_agl_gmx_tx_col_attempt_s {
1055+ uint64_t reserved_5_63:59;
1056+ uint64_t limit:5;
1057+ } s;
1058+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1059+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1060+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1061+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1062+};
1063+
1064+union cvmx_agl_gmx_tx_ifg {
1065+ uint64_t u64;
1066+ struct cvmx_agl_gmx_tx_ifg_s {
1067+ uint64_t reserved_8_63:56;
1068+ uint64_t ifg2:4;
1069+ uint64_t ifg1:4;
1070+ } s;
1071+ struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1072+ struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1073+ struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1074+ struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1075+};
1076+
1077+union cvmx_agl_gmx_tx_int_en {
1078+ uint64_t u64;
1079+ struct cvmx_agl_gmx_tx_int_en_s {
1080+ uint64_t reserved_18_63:46;
1081+ uint64_t late_col:2;
1082+ uint64_t reserved_14_15:2;
1083+ uint64_t xsdef:2;
1084+ uint64_t reserved_10_11:2;
1085+ uint64_t xscol:2;
1086+ uint64_t reserved_4_7:4;
1087+ uint64_t undflw:2;
1088+ uint64_t reserved_1_1:1;
1089+ uint64_t pko_nxa:1;
1090+ } s;
1091+ struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1092+ struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1093+ struct cvmx_agl_gmx_tx_int_en_cn56xx {
1094+ uint64_t reserved_17_63:47;
1095+ uint64_t late_col:1;
1096+ uint64_t reserved_13_15:3;
1097+ uint64_t xsdef:1;
1098+ uint64_t reserved_9_11:3;
1099+ uint64_t xscol:1;
1100+ uint64_t reserved_3_7:5;
1101+ uint64_t undflw:1;
1102+ uint64_t reserved_1_1:1;
1103+ uint64_t pko_nxa:1;
1104+ } cn56xx;
1105+ struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1106+};
1107+
1108+union cvmx_agl_gmx_tx_int_reg {
1109+ uint64_t u64;
1110+ struct cvmx_agl_gmx_tx_int_reg_s {
1111+ uint64_t reserved_18_63:46;
1112+ uint64_t late_col:2;
1113+ uint64_t reserved_14_15:2;
1114+ uint64_t xsdef:2;
1115+ uint64_t reserved_10_11:2;
1116+ uint64_t xscol:2;
1117+ uint64_t reserved_4_7:4;
1118+ uint64_t undflw:2;
1119+ uint64_t reserved_1_1:1;
1120+ uint64_t pko_nxa:1;
1121+ } s;
1122+ struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1123+ struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1124+ struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1125+ uint64_t reserved_17_63:47;
1126+ uint64_t late_col:1;
1127+ uint64_t reserved_13_15:3;
1128+ uint64_t xsdef:1;
1129+ uint64_t reserved_9_11:3;
1130+ uint64_t xscol:1;
1131+ uint64_t reserved_3_7:5;
1132+ uint64_t undflw:1;
1133+ uint64_t reserved_1_1:1;
1134+ uint64_t pko_nxa:1;
1135+ } cn56xx;
1136+ struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1137+};
1138+
1139+union cvmx_agl_gmx_tx_jam {
1140+ uint64_t u64;
1141+ struct cvmx_agl_gmx_tx_jam_s {
1142+ uint64_t reserved_8_63:56;
1143+ uint64_t jam:8;
1144+ } s;
1145+ struct cvmx_agl_gmx_tx_jam_s cn52xx;
1146+ struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1147+ struct cvmx_agl_gmx_tx_jam_s cn56xx;
1148+ struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1149+};
1150+
1151+union cvmx_agl_gmx_tx_lfsr {
1152+ uint64_t u64;
1153+ struct cvmx_agl_gmx_tx_lfsr_s {
1154+ uint64_t reserved_16_63:48;
1155+ uint64_t lfsr:16;
1156+ } s;
1157+ struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1158+ struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1159+ struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1160+ struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1161+};
1162+
1163+union cvmx_agl_gmx_tx_ovr_bp {
1164+ uint64_t u64;
1165+ struct cvmx_agl_gmx_tx_ovr_bp_s {
1166+ uint64_t reserved_10_63:54;
1167+ uint64_t en:2;
1168+ uint64_t reserved_6_7:2;
1169+ uint64_t bp:2;
1170+ uint64_t reserved_2_3:2;
1171+ uint64_t ign_full:2;
1172+ } s;
1173+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1174+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1175+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1176+ uint64_t reserved_9_63:55;
1177+ uint64_t en:1;
1178+ uint64_t reserved_5_7:3;
1179+ uint64_t bp:1;
1180+ uint64_t reserved_1_3:3;
1181+ uint64_t ign_full:1;
1182+ } cn56xx;
1183+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1184+};
1185+
1186+union cvmx_agl_gmx_tx_pause_pkt_dmac {
1187+ uint64_t u64;
1188+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1189+ uint64_t reserved_48_63:16;
1190+ uint64_t dmac:48;
1191+ } s;
1192+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1193+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1194+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1195+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1196+};
1197+
1198+union cvmx_agl_gmx_tx_pause_pkt_type {
1199+ uint64_t u64;
1200+ struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1201+ uint64_t reserved_16_63:48;
1202+ uint64_t type:16;
1203+ } s;
1204+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1205+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1206+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1207+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1208+};
1209+
1210+#endif
1211--- /dev/null
1212+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
1213@@ -0,0 +1,248 @@
1214+/***********************license start***************
1215+ * Author: Cavium Networks
1216+ *
1217+ * Contact: support@caviumnetworks.com
1218+ * This file is part of the OCTEON SDK
1219+ *
1220+ * Copyright (c) 2003-2008 Cavium Networks
1221+ *
1222+ * This file is free software; you can redistribute it and/or modify
1223+ * it under the terms of the GNU General Public License, Version 2, as
1224+ * published by the Free Software Foundation.
1225+ *
1226+ * This file is distributed in the hope that it will be useful, but
1227+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1228+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1229+ * NONINFRINGEMENT. See the GNU General Public License for more
1230+ * details.
1231+ *
1232+ * You should have received a copy of the GNU General Public License
1233+ * along with this file; if not, write to the Free Software
1234+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1235+ * or visit http://www.gnu.org/licenses/.
1236+ *
1237+ * This file may also be available under a different license from Cavium.
1238+ * Contact Cavium Networks for more information
1239+ ***********************license end**************************************/
1240+
1241+#ifndef __CVMX_MIXX_DEFS_H__
1242+#define __CVMX_MIXX_DEFS_H__
1243+
1244+#define CVMX_MIXX_BIST(offset) \
1245+ CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
1246+#define CVMX_MIXX_CTL(offset) \
1247+ CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
1248+#define CVMX_MIXX_INTENA(offset) \
1249+ CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
1250+#define CVMX_MIXX_IRCNT(offset) \
1251+ CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
1252+#define CVMX_MIXX_IRHWM(offset) \
1253+ CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
1254+#define CVMX_MIXX_IRING1(offset) \
1255+ CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
1256+#define CVMX_MIXX_IRING2(offset) \
1257+ CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
1258+#define CVMX_MIXX_ISR(offset) \
1259+ CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
1260+#define CVMX_MIXX_ORCNT(offset) \
1261+ CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
1262+#define CVMX_MIXX_ORHWM(offset) \
1263+ CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
1264+#define CVMX_MIXX_ORING1(offset) \
1265+ CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
1266+#define CVMX_MIXX_ORING2(offset) \
1267+ CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
1268+#define CVMX_MIXX_REMCNT(offset) \
1269+ CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
1270+
1271+union cvmx_mixx_bist {
1272+ uint64_t u64;
1273+ struct cvmx_mixx_bist_s {
1274+ uint64_t reserved_4_63:60;
1275+ uint64_t mrqdat:1;
1276+ uint64_t ipfdat:1;
1277+ uint64_t irfdat:1;
1278+ uint64_t orfdat:1;
1279+ } s;
1280+ struct cvmx_mixx_bist_s cn52xx;
1281+ struct cvmx_mixx_bist_s cn52xxp1;
1282+ struct cvmx_mixx_bist_s cn56xx;
1283+ struct cvmx_mixx_bist_s cn56xxp1;
1284+};
1285+
1286+union cvmx_mixx_ctl {
1287+ uint64_t u64;
1288+ struct cvmx_mixx_ctl_s {
1289+ uint64_t reserved_8_63:56;
1290+ uint64_t crc_strip:1;
1291+ uint64_t busy:1;
1292+ uint64_t en:1;
1293+ uint64_t reset:1;
1294+ uint64_t lendian:1;
1295+ uint64_t nbtarb:1;
1296+ uint64_t mrq_hwm:2;
1297+ } s;
1298+ struct cvmx_mixx_ctl_s cn52xx;
1299+ struct cvmx_mixx_ctl_s cn52xxp1;
1300+ struct cvmx_mixx_ctl_s cn56xx;
1301+ struct cvmx_mixx_ctl_s cn56xxp1;
1302+};
1303+
1304+union cvmx_mixx_intena {
1305+ uint64_t u64;
1306+ struct cvmx_mixx_intena_s {
1307+ uint64_t reserved_7_63:57;
1308+ uint64_t orunena:1;
1309+ uint64_t irunena:1;
1310+ uint64_t data_drpena:1;
1311+ uint64_t ithena:1;
1312+ uint64_t othena:1;
1313+ uint64_t ivfena:1;
1314+ uint64_t ovfena:1;
1315+ } s;
1316+ struct cvmx_mixx_intena_s cn52xx;
1317+ struct cvmx_mixx_intena_s cn52xxp1;
1318+ struct cvmx_mixx_intena_s cn56xx;
1319+ struct cvmx_mixx_intena_s cn56xxp1;
1320+};
1321+
1322+union cvmx_mixx_ircnt {
1323+ uint64_t u64;
1324+ struct cvmx_mixx_ircnt_s {
1325+ uint64_t reserved_20_63:44;
1326+ uint64_t ircnt:20;
1327+ } s;
1328+ struct cvmx_mixx_ircnt_s cn52xx;
1329+ struct cvmx_mixx_ircnt_s cn52xxp1;
1330+ struct cvmx_mixx_ircnt_s cn56xx;
1331+ struct cvmx_mixx_ircnt_s cn56xxp1;
1332+};
1333+
1334+union cvmx_mixx_irhwm {
1335+ uint64_t u64;
1336+ struct cvmx_mixx_irhwm_s {
1337+ uint64_t reserved_40_63:24;
1338+ uint64_t ibplwm:20;
1339+ uint64_t irhwm:20;
1340+ } s;
1341+ struct cvmx_mixx_irhwm_s cn52xx;
1342+ struct cvmx_mixx_irhwm_s cn52xxp1;
1343+ struct cvmx_mixx_irhwm_s cn56xx;
1344+ struct cvmx_mixx_irhwm_s cn56xxp1;
1345+};
1346+
1347+union cvmx_mixx_iring1 {
1348+ uint64_t u64;
1349+ struct cvmx_mixx_iring1_s {
1350+ uint64_t reserved_60_63:4;
1351+ uint64_t isize:20;
1352+ uint64_t reserved_36_39:4;
1353+ uint64_t ibase:33;
1354+ uint64_t reserved_0_2:3;
1355+ } s;
1356+ struct cvmx_mixx_iring1_s cn52xx;
1357+ struct cvmx_mixx_iring1_s cn52xxp1;
1358+ struct cvmx_mixx_iring1_s cn56xx;
1359+ struct cvmx_mixx_iring1_s cn56xxp1;
1360+};
1361+
1362+union cvmx_mixx_iring2 {
1363+ uint64_t u64;
1364+ struct cvmx_mixx_iring2_s {
1365+ uint64_t reserved_52_63:12;
1366+ uint64_t itlptr:20;
1367+ uint64_t reserved_20_31:12;
1368+ uint64_t idbell:20;
1369+ } s;
1370+ struct cvmx_mixx_iring2_s cn52xx;
1371+ struct cvmx_mixx_iring2_s cn52xxp1;
1372+ struct cvmx_mixx_iring2_s cn56xx;
1373+ struct cvmx_mixx_iring2_s cn56xxp1;
1374+};
1375+
1376+union cvmx_mixx_isr {
1377+ uint64_t u64;
1378+ struct cvmx_mixx_isr_s {
1379+ uint64_t reserved_7_63:57;
1380+ uint64_t orun:1;
1381+ uint64_t irun:1;
1382+ uint64_t data_drp:1;
1383+ uint64_t irthresh:1;
1384+ uint64_t orthresh:1;
1385+ uint64_t idblovf:1;
1386+ uint64_t odblovf:1;
1387+ } s;
1388+ struct cvmx_mixx_isr_s cn52xx;
1389+ struct cvmx_mixx_isr_s cn52xxp1;
1390+ struct cvmx_mixx_isr_s cn56xx;
1391+ struct cvmx_mixx_isr_s cn56xxp1;
1392+};
1393+
1394+union cvmx_mixx_orcnt {
1395+ uint64_t u64;
1396+ struct cvmx_mixx_orcnt_s {
1397+ uint64_t reserved_20_63:44;
1398+ uint64_t orcnt:20;
1399+ } s;
1400+ struct cvmx_mixx_orcnt_s cn52xx;
1401+ struct cvmx_mixx_orcnt_s cn52xxp1;
1402+ struct cvmx_mixx_orcnt_s cn56xx;
1403+ struct cvmx_mixx_orcnt_s cn56xxp1;
1404+};
1405+
1406+union cvmx_mixx_orhwm {
1407+ uint64_t u64;
1408+ struct cvmx_mixx_orhwm_s {
1409+ uint64_t reserved_20_63:44;
1410+ uint64_t orhwm:20;
1411+ } s;
1412+ struct cvmx_mixx_orhwm_s cn52xx;
1413+ struct cvmx_mixx_orhwm_s cn52xxp1;
1414+ struct cvmx_mixx_orhwm_s cn56xx;
1415+ struct cvmx_mixx_orhwm_s cn56xxp1;
1416+};
1417+
1418+union cvmx_mixx_oring1 {
1419+ uint64_t u64;
1420+ struct cvmx_mixx_oring1_s {
1421+ uint64_t reserved_60_63:4;
1422+ uint64_t osize:20;
1423+ uint64_t reserved_36_39:4;
1424+ uint64_t obase:33;
1425+ uint64_t reserved_0_2:3;
1426+ } s;
1427+ struct cvmx_mixx_oring1_s cn52xx;
1428+ struct cvmx_mixx_oring1_s cn52xxp1;
1429+ struct cvmx_mixx_oring1_s cn56xx;
1430+ struct cvmx_mixx_oring1_s cn56xxp1;
1431+};
1432+
1433+union cvmx_mixx_oring2 {
1434+ uint64_t u64;
1435+ struct cvmx_mixx_oring2_s {
1436+ uint64_t reserved_52_63:12;
1437+ uint64_t otlptr:20;
1438+ uint64_t reserved_20_31:12;
1439+ uint64_t odbell:20;
1440+ } s;
1441+ struct cvmx_mixx_oring2_s cn52xx;
1442+ struct cvmx_mixx_oring2_s cn52xxp1;
1443+ struct cvmx_mixx_oring2_s cn56xx;
1444+ struct cvmx_mixx_oring2_s cn56xxp1;
1445+};
1446+
1447+union cvmx_mixx_remcnt {
1448+ uint64_t u64;
1449+ struct cvmx_mixx_remcnt_s {
1450+ uint64_t reserved_52_63:12;
1451+ uint64_t iremcnt:20;
1452+ uint64_t reserved_20_31:12;
1453+ uint64_t oremcnt:20;
1454+ } s;
1455+ struct cvmx_mixx_remcnt_s cn52xx;
1456+ struct cvmx_mixx_remcnt_s cn52xxp1;
1457+ struct cvmx_mixx_remcnt_s cn56xx;
1458+ struct cvmx_mixx_remcnt_s cn56xxp1;
1459+};
1460+
1461+#endif
1462--- /dev/null
1463+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
1464@@ -0,0 +1,178 @@
1465+/***********************license start***************
1466+ * Author: Cavium Networks
1467+ *
1468+ * Contact: support@caviumnetworks.com
1469+ * This file is part of the OCTEON SDK
1470+ *
1471+ * Copyright (c) 2003-2008 Cavium Networks
1472+ *
1473+ * This file is free software; you can redistribute it and/or modify
1474+ * it under the terms of the GNU General Public License, Version 2, as
1475+ * published by the Free Software Foundation.
1476+ *
1477+ * This file is distributed in the hope that it will be useful, but
1478+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1479+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1480+ * NONINFRINGEMENT. See the GNU General Public License for more
1481+ * details.
1482+ *
1483+ * You should have received a copy of the GNU General Public License
1484+ * along with this file; if not, write to the Free Software
1485+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1486+ * or visit http://www.gnu.org/licenses/.
1487+ *
1488+ * This file may also be available under a different license from Cavium.
1489+ * Contact Cavium Networks for more information
1490+ ***********************license end**************************************/
1491+
1492+#ifndef __CVMX_SMIX_DEFS_H__
1493+#define __CVMX_SMIX_DEFS_H__
1494+
1495+#define CVMX_SMIX_CLK(offset) \
1496+ CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
1497+#define CVMX_SMIX_CMD(offset) \
1498+ CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
1499+#define CVMX_SMIX_EN(offset) \
1500+ CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
1501+#define CVMX_SMIX_RD_DAT(offset) \
1502+ CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
1503+#define CVMX_SMIX_WR_DAT(offset) \
1504+ CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
1505+
1506+union cvmx_smix_clk {
1507+ uint64_t u64;
1508+ struct cvmx_smix_clk_s {
1509+ uint64_t reserved_25_63:39;
1510+ uint64_t mode:1;
1511+ uint64_t reserved_21_23:3;
1512+ uint64_t sample_hi:5;
1513+ uint64_t sample_mode:1;
1514+ uint64_t reserved_14_14:1;
1515+ uint64_t clk_idle:1;
1516+ uint64_t preamble:1;
1517+ uint64_t sample:4;
1518+ uint64_t phase:8;
1519+ } s;
1520+ struct cvmx_smix_clk_cn30xx {
1521+ uint64_t reserved_21_63:43;
1522+ uint64_t sample_hi:5;
1523+ uint64_t reserved_14_15:2;
1524+ uint64_t clk_idle:1;
1525+ uint64_t preamble:1;
1526+ uint64_t sample:4;
1527+ uint64_t phase:8;
1528+ } cn30xx;
1529+ struct cvmx_smix_clk_cn30xx cn31xx;
1530+ struct cvmx_smix_clk_cn30xx cn38xx;
1531+ struct cvmx_smix_clk_cn30xx cn38xxp2;
1532+ struct cvmx_smix_clk_cn50xx {
1533+ uint64_t reserved_25_63:39;
1534+ uint64_t mode:1;
1535+ uint64_t reserved_21_23:3;
1536+ uint64_t sample_hi:5;
1537+ uint64_t reserved_14_15:2;
1538+ uint64_t clk_idle:1;
1539+ uint64_t preamble:1;
1540+ uint64_t sample:4;
1541+ uint64_t phase:8;
1542+ } cn50xx;
1543+ struct cvmx_smix_clk_s cn52xx;
1544+ struct cvmx_smix_clk_cn50xx cn52xxp1;
1545+ struct cvmx_smix_clk_s cn56xx;
1546+ struct cvmx_smix_clk_cn50xx cn56xxp1;
1547+ struct cvmx_smix_clk_cn30xx cn58xx;
1548+ struct cvmx_smix_clk_cn30xx cn58xxp1;
1549+};
1550+
1551+union cvmx_smix_cmd {
1552+ uint64_t u64;
1553+ struct cvmx_smix_cmd_s {
1554+ uint64_t reserved_18_63:46;
1555+ uint64_t phy_op:2;
1556+ uint64_t reserved_13_15:3;
1557+ uint64_t phy_adr:5;
1558+ uint64_t reserved_5_7:3;
1559+ uint64_t reg_adr:5;
1560+ } s;
1561+ struct cvmx_smix_cmd_cn30xx {
1562+ uint64_t reserved_17_63:47;
1563+ uint64_t phy_op:1;
1564+ uint64_t reserved_13_15:3;
1565+ uint64_t phy_adr:5;
1566+ uint64_t reserved_5_7:3;
1567+ uint64_t reg_adr:5;
1568+ } cn30xx;
1569+ struct cvmx_smix_cmd_cn30xx cn31xx;
1570+ struct cvmx_smix_cmd_cn30xx cn38xx;
1571+ struct cvmx_smix_cmd_cn30xx cn38xxp2;
1572+ struct cvmx_smix_cmd_s cn50xx;
1573+ struct cvmx_smix_cmd_s cn52xx;
1574+ struct cvmx_smix_cmd_s cn52xxp1;
1575+ struct cvmx_smix_cmd_s cn56xx;
1576+ struct cvmx_smix_cmd_s cn56xxp1;
1577+ struct cvmx_smix_cmd_cn30xx cn58xx;
1578+ struct cvmx_smix_cmd_cn30xx cn58xxp1;
1579+};
1580+
1581+union cvmx_smix_en {
1582+ uint64_t u64;
1583+ struct cvmx_smix_en_s {
1584+ uint64_t reserved_1_63:63;
1585+ uint64_t en:1;
1586+ } s;
1587+ struct cvmx_smix_en_s cn30xx;
1588+ struct cvmx_smix_en_s cn31xx;
1589+ struct cvmx_smix_en_s cn38xx;
1590+ struct cvmx_smix_en_s cn38xxp2;
1591+ struct cvmx_smix_en_s cn50xx;
1592+ struct cvmx_smix_en_s cn52xx;
1593+ struct cvmx_smix_en_s cn52xxp1;
1594+ struct cvmx_smix_en_s cn56xx;
1595+ struct cvmx_smix_en_s cn56xxp1;
1596+ struct cvmx_smix_en_s cn58xx;
1597+ struct cvmx_smix_en_s cn58xxp1;
1598+};
1599+
1600+union cvmx_smix_rd_dat {
1601+ uint64_t u64;
1602+ struct cvmx_smix_rd_dat_s {
1603+ uint64_t reserved_18_63:46;
1604+ uint64_t pending:1;
1605+ uint64_t val:1;
1606+ uint64_t dat:16;
1607+ } s;
1608+ struct cvmx_smix_rd_dat_s cn30xx;
1609+ struct cvmx_smix_rd_dat_s cn31xx;
1610+ struct cvmx_smix_rd_dat_s cn38xx;
1611+ struct cvmx_smix_rd_dat_s cn38xxp2;
1612+ struct cvmx_smix_rd_dat_s cn50xx;
1613+ struct cvmx_smix_rd_dat_s cn52xx;
1614+ struct cvmx_smix_rd_dat_s cn52xxp1;
1615+ struct cvmx_smix_rd_dat_s cn56xx;
1616+ struct cvmx_smix_rd_dat_s cn56xxp1;
1617+ struct cvmx_smix_rd_dat_s cn58xx;
1618+ struct cvmx_smix_rd_dat_s cn58xxp1;
1619+};
1620+
1621+union cvmx_smix_wr_dat {
1622+ uint64_t u64;
1623+ struct cvmx_smix_wr_dat_s {
1624+ uint64_t reserved_18_63:46;
1625+ uint64_t pending:1;
1626+ uint64_t val:1;
1627+ uint64_t dat:16;
1628+ } s;
1629+ struct cvmx_smix_wr_dat_s cn30xx;
1630+ struct cvmx_smix_wr_dat_s cn31xx;
1631+ struct cvmx_smix_wr_dat_s cn38xx;
1632+ struct cvmx_smix_wr_dat_s cn38xxp2;
1633+ struct cvmx_smix_wr_dat_s cn50xx;
1634+ struct cvmx_smix_wr_dat_s cn52xx;
1635+ struct cvmx_smix_wr_dat_s cn52xxp1;
1636+ struct cvmx_smix_wr_dat_s cn56xx;
1637+ struct cvmx_smix_wr_dat_s cn56xxp1;
1638+ struct cvmx_smix_wr_dat_s cn58xx;
1639+ struct cvmx_smix_wr_dat_s cn58xxp1;
1640+};
1641+
1642+#endif
1643

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