Root/target/linux/octeon/patches-2.6.30/017-platform_devices.patch

1From: David Daney <ddaney@caviumnetworks.com>
2Date: Wed, 16 Sep 2009 21:54:18 +0000 (-0700)
3Subject: MIPS: Octeon: Move some platform device registration to its own file.
4X-Git-Tag: linux-2.6.32-rc1~29
5X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=936c111e;hp=e1302af3482d3955f5a6100160e595e792d5f1e4
6
7MIPS: Octeon: Move some platform device registration to its own file.
8
9There is a bunch of platform device registration in
10arch/mips/cavium-octeon/setup.c. We move it to its own file in
11preparation for adding more platform devices.
12
13Signed-off-by: David Daney <ddaney@caviumnetworks.com>
14Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
15---
16
17diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
18index d6903c3..1394362 100644
19--- a/arch/mips/cavium-octeon/Makefile
20+++ b/arch/mips/cavium-octeon/Makefile
21@@ -6,10 +6,10 @@
22 # License. See the file "COPYING" in the main directory of this archive
23 # for more details.
24 #
25-# Copyright (C) 2005-2008 Cavium Networks
26+# Copyright (C) 2005-2009 Cavium Networks
27 #
28 
29-obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
30+obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
31 obj-y += dma-octeon.o flash_setup.o
32 obj-y += octeon-memcpy.o
33 
34diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
35new file mode 100644
36index 0000000..be711dd
37--- /dev/null
38+++ b/arch/mips/cavium-octeon/octeon-platform.c
39@@ -0,0 +1,164 @@
40+/*
41+ * This file is subject to the terms and conditions of the GNU General Public
42+ * License. See the file "COPYING" in the main directory of this archive
43+ * for more details.
44+ *
45+ * Copyright (C) 2004-2009 Cavium Networks
46+ * Copyright (C) 2008 Wind River Systems
47+ */
48+
49+#include <linux/init.h>
50+#include <linux/irq.h>
51+#include <linux/module.h>
52+#include <linux/platform_device.h>
53+
54+#include <asm/octeon/octeon.h>
55+#include <asm/octeon/cvmx-rnm-defs.h>
56+
57+static struct octeon_cf_data octeon_cf_data;
58+
59+static int __init octeon_cf_device_init(void)
60+{
61+ union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
62+ unsigned long base_ptr, region_base, region_size;
63+ struct platform_device *pd;
64+ struct resource cf_resources[3];
65+ unsigned int num_resources;
66+ int i;
67+ int ret = 0;
68+
69+ /* Setup octeon-cf platform device if present. */
70+ base_ptr = 0;
71+ if (octeon_bootinfo->major_version == 1
72+ && octeon_bootinfo->minor_version >= 1) {
73+ if (octeon_bootinfo->compact_flash_common_base_addr)
74+ base_ptr =
75+ octeon_bootinfo->compact_flash_common_base_addr;
76+ } else {
77+ base_ptr = 0x1d000800;
78+ }
79+
80+ if (!base_ptr)
81+ return ret;
82+
83+ /* Find CS0 region. */
84+ for (i = 0; i < 8; i++) {
85+ mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
86+ region_base = mio_boot_reg_cfg.s.base << 16;
87+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
88+ if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
89+ && base_ptr < region_base + region_size)
90+ break;
91+ }
92+ if (i >= 7) {
93+ /* i and i + 1 are CS0 and CS1, both must be less than 8. */
94+ goto out;
95+ }
96+ octeon_cf_data.base_region = i;
97+ octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
98+ octeon_cf_data.base_region_bias = base_ptr - region_base;
99+ memset(cf_resources, 0, sizeof(cf_resources));
100+ num_resources = 0;
101+ cf_resources[num_resources].flags = IORESOURCE_MEM;
102+ cf_resources[num_resources].start = region_base;
103+ cf_resources[num_resources].end = region_base + region_size - 1;
104+ num_resources++;
105+
106+
107+ if (!(base_ptr & 0xfffful)) {
108+ /*
109+ * Boot loader signals availability of DMA (true_ide
110+ * mode) by setting low order bits of base_ptr to
111+ * zero.
112+ */
113+
114+ /* Asume that CS1 immediately follows. */
115+ mio_boot_reg_cfg.u64 =
116+ cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
117+ region_base = mio_boot_reg_cfg.s.base << 16;
118+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
119+ if (!mio_boot_reg_cfg.s.en)
120+ goto out;
121+
122+ cf_resources[num_resources].flags = IORESOURCE_MEM;
123+ cf_resources[num_resources].start = region_base;
124+ cf_resources[num_resources].end = region_base + region_size - 1;
125+ num_resources++;
126+
127+ octeon_cf_data.dma_engine = 0;
128+ cf_resources[num_resources].flags = IORESOURCE_IRQ;
129+ cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
130+ cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
131+ num_resources++;
132+ } else {
133+ octeon_cf_data.dma_engine = -1;
134+ }
135+
136+ pd = platform_device_alloc("pata_octeon_cf", -1);
137+ if (!pd) {
138+ ret = -ENOMEM;
139+ goto out;
140+ }
141+ pd->dev.platform_data = &octeon_cf_data;
142+
143+ ret = platform_device_add_resources(pd, cf_resources, num_resources);
144+ if (ret)
145+ goto fail;
146+
147+ ret = platform_device_add(pd);
148+ if (ret)
149+ goto fail;
150+
151+ return ret;
152+fail:
153+ platform_device_put(pd);
154+out:
155+ return ret;
156+}
157+device_initcall(octeon_cf_device_init);
158+
159+/* Octeon Random Number Generator. */
160+static int __init octeon_rng_device_init(void)
161+{
162+ struct platform_device *pd;
163+ int ret = 0;
164+
165+ struct resource rng_resources[] = {
166+ {
167+ .flags = IORESOURCE_MEM,
168+ .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
169+ .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
170+ }, {
171+ .flags = IORESOURCE_MEM,
172+ .start = cvmx_build_io_address(8, 0),
173+ .end = cvmx_build_io_address(8, 0) + 0x7
174+ }
175+ };
176+
177+ pd = platform_device_alloc("octeon_rng", -1);
178+ if (!pd) {
179+ ret = -ENOMEM;
180+ goto out;
181+ }
182+
183+ ret = platform_device_add_resources(pd, rng_resources,
184+ ARRAY_SIZE(rng_resources));
185+ if (ret)
186+ goto fail;
187+
188+ ret = platform_device_add(pd);
189+ if (ret)
190+ goto fail;
191+
192+ return ret;
193+fail:
194+ platform_device_put(pd);
195+
196+out:
197+ return ret;
198+}
199+device_initcall(octeon_rng_device_init);
200+
201+MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
202+MODULE_LICENSE("GPL");
203+MODULE_DESCRIPTION("Platform driver for Octeon SOC");
204diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
205index 468a120..b321d3b 100644
206--- a/arch/mips/cavium-octeon/setup.c
207+++ b/arch/mips/cavium-octeon/setup.c
208@@ -11,7 +11,6 @@
209 #include <linux/delay.h>
210 #include <linux/interrupt.h>
211 #include <linux/io.h>
212-#include <linux/irq.h>
213 #include <linux/serial.h>
214 #include <linux/smp.h>
215 #include <linux/types.h>
216@@ -33,7 +32,6 @@
217 #include <asm/time.h>
218 
219 #include <asm/octeon/octeon.h>
220-#include <asm/octeon/cvmx-rnm-defs.h>
221 
222 #ifdef CONFIG_CAVIUM_DECODE_RSL
223 extern void cvmx_interrupt_rsl_decode(void);
224@@ -825,147 +823,3 @@ void prom_free_prom_memory(void)
225        CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
226     octeon_hal_setup_reserved32();
227 }
228-
229-static struct octeon_cf_data octeon_cf_data;
230-
231-static int __init octeon_cf_device_init(void)
232-{
233- union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
234- unsigned long base_ptr, region_base, region_size;
235- struct platform_device *pd;
236- struct resource cf_resources[3];
237- unsigned int num_resources;
238- int i;
239- int ret = 0;
240-
241- /* Setup octeon-cf platform device if present. */
242- base_ptr = 0;
243- if (octeon_bootinfo->major_version == 1
244- && octeon_bootinfo->minor_version >= 1) {
245- if (octeon_bootinfo->compact_flash_common_base_addr)
246- base_ptr =
247- octeon_bootinfo->compact_flash_common_base_addr;
248- } else {
249- base_ptr = 0x1d000800;
250- }
251-
252- if (!base_ptr)
253- return ret;
254-
255- /* Find CS0 region. */
256- for (i = 0; i < 8; i++) {
257- mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
258- region_base = mio_boot_reg_cfg.s.base << 16;
259- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
260- if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
261- && base_ptr < region_base + region_size)
262- break;
263- }
264- if (i >= 7) {
265- /* i and i + 1 are CS0 and CS1, both must be less than 8. */
266- goto out;
267- }
268- octeon_cf_data.base_region = i;
269- octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
270- octeon_cf_data.base_region_bias = base_ptr - region_base;
271- memset(cf_resources, 0, sizeof(cf_resources));
272- num_resources = 0;
273- cf_resources[num_resources].flags = IORESOURCE_MEM;
274- cf_resources[num_resources].start = region_base;
275- cf_resources[num_resources].end = region_base + region_size - 1;
276- num_resources++;
277-
278-
279- if (!(base_ptr & 0xfffful)) {
280- /*
281- * Boot loader signals availability of DMA (true_ide
282- * mode) by setting low order bits of base_ptr to
283- * zero.
284- */
285-
286- /* Asume that CS1 immediately follows. */
287- mio_boot_reg_cfg.u64 =
288- cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
289- region_base = mio_boot_reg_cfg.s.base << 16;
290- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
291- if (!mio_boot_reg_cfg.s.en)
292- goto out;
293-
294- cf_resources[num_resources].flags = IORESOURCE_MEM;
295- cf_resources[num_resources].start = region_base;
296- cf_resources[num_resources].end = region_base + region_size - 1;
297- num_resources++;
298-
299- octeon_cf_data.dma_engine = 0;
300- cf_resources[num_resources].flags = IORESOURCE_IRQ;
301- cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
302- cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
303- num_resources++;
304- } else {
305- octeon_cf_data.dma_engine = -1;
306- }
307-
308- pd = platform_device_alloc("pata_octeon_cf", -1);
309- if (!pd) {
310- ret = -ENOMEM;
311- goto out;
312- }
313- pd->dev.platform_data = &octeon_cf_data;
314-
315- ret = platform_device_add_resources(pd, cf_resources, num_resources);
316- if (ret)
317- goto fail;
318-
319- ret = platform_device_add(pd);
320- if (ret)
321- goto fail;
322-
323- return ret;
324-fail:
325- platform_device_put(pd);
326-out:
327- return ret;
328-}
329-device_initcall(octeon_cf_device_init);
330-
331-/* Octeon Random Number Generator. */
332-static int __init octeon_rng_device_init(void)
333-{
334- struct platform_device *pd;
335- int ret = 0;
336-
337- struct resource rng_resources[] = {
338- {
339- .flags = IORESOURCE_MEM,
340- .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
341- .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
342- }, {
343- .flags = IORESOURCE_MEM,
344- .start = cvmx_build_io_address(8, 0),
345- .end = cvmx_build_io_address(8, 0) + 0x7
346- }
347- };
348-
349- pd = platform_device_alloc("octeon_rng", -1);
350- if (!pd) {
351- ret = -ENOMEM;
352- goto out;
353- }
354-
355- ret = platform_device_add_resources(pd, rng_resources,
356- ARRAY_SIZE(rng_resources));
357- if (ret)
358- goto fail;
359-
360- ret = platform_device_add(pd);
361- if (ret)
362- goto fail;
363-
364- return ret;
365-fail:
366- platform_device_put(pd);
367-
368-out:
369- return ret;
370-}
371-device_initcall(octeon_rng_device_init);
372

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