| 1 | --- /dev/null |
| 2 | +++ b/kexec/arch/mips/regdef.h |
| 3 | @@ -0,0 +1,100 @@ |
| 4 | +/* |
| 5 | + * This file is subject to the terms and conditions of the GNU General Public |
| 6 | + * License. See the file "COPYING" in the main directory of this archive |
| 7 | + * for more details. |
| 8 | + * |
| 9 | + * Copyright (C) 1985 MIPS Computer Systems, Inc. |
| 10 | + * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle |
| 11 | + * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. |
| 12 | + */ |
| 13 | +#ifndef _ASM_REGDEF_H |
| 14 | +#define _ASM_REGDEF_H |
| 15 | + |
| 16 | +#include <asm/sgidefs.h> |
| 17 | + |
| 18 | +#if _MIPS_SIM == _MIPS_SIM_ABI32 |
| 19 | + |
| 20 | +/* |
| 21 | + * Symbolic register names for 32 bit ABI |
| 22 | + */ |
| 23 | +#define zero $0 /* wired zero */ |
| 24 | +#define AT $1 /* assembler temp - uppercase because of ".set at" */ |
| 25 | +#define v0 $2 /* return value */ |
| 26 | +#define v1 $3 |
| 27 | +#define a0 $4 /* argument registers */ |
| 28 | +#define a1 $5 |
| 29 | +#define a2 $6 |
| 30 | +#define a3 $7 |
| 31 | +#define t0 $8 /* caller saved */ |
| 32 | +#define t1 $9 |
| 33 | +#define t2 $10 |
| 34 | +#define t3 $11 |
| 35 | +#define t4 $12 |
| 36 | +#define t5 $13 |
| 37 | +#define t6 $14 |
| 38 | +#define t7 $15 |
| 39 | +#define s0 $16 /* callee saved */ |
| 40 | +#define s1 $17 |
| 41 | +#define s2 $18 |
| 42 | +#define s3 $19 |
| 43 | +#define s4 $20 |
| 44 | +#define s5 $21 |
| 45 | +#define s6 $22 |
| 46 | +#define s7 $23 |
| 47 | +#define t8 $24 /* caller saved */ |
| 48 | +#define t9 $25 |
| 49 | +#define jp $25 /* PIC jump register */ |
| 50 | +#define k0 $26 /* kernel scratch */ |
| 51 | +#define k1 $27 |
| 52 | +#define gp $28 /* global pointer */ |
| 53 | +#define sp $29 /* stack pointer */ |
| 54 | +#define fp $30 /* frame pointer */ |
| 55 | +#define s8 $30 /* same like fp! */ |
| 56 | +#define ra $31 /* return address */ |
| 57 | + |
| 58 | +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
| 59 | + |
| 60 | +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 |
| 61 | + |
| 62 | +#define zero $0 /* wired zero */ |
| 63 | +#define AT $at /* assembler temp - uppercase because of ".set at" */ |
| 64 | +#define v0 $2 /* return value - caller saved */ |
| 65 | +#define v1 $3 |
| 66 | +#define a0 $4 /* argument registers */ |
| 67 | +#define a1 $5 |
| 68 | +#define a2 $6 |
| 69 | +#define a3 $7 |
| 70 | +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ |
| 71 | +#define ta0 $8 |
| 72 | +#define a5 $9 |
| 73 | +#define ta1 $9 |
| 74 | +#define a6 $10 |
| 75 | +#define ta2 $10 |
| 76 | +#define a7 $11 |
| 77 | +#define ta3 $11 |
| 78 | +#define t0 $12 /* caller saved */ |
| 79 | +#define t1 $13 |
| 80 | +#define t2 $14 |
| 81 | +#define t3 $15 |
| 82 | +#define s0 $16 /* callee saved */ |
| 83 | +#define s1 $17 |
| 84 | +#define s2 $18 |
| 85 | +#define s3 $19 |
| 86 | +#define s4 $20 |
| 87 | +#define s5 $21 |
| 88 | +#define s6 $22 |
| 89 | +#define s7 $23 |
| 90 | +#define t8 $24 /* caller saved */ |
| 91 | +#define t9 $25 /* callee address for PIC/temp */ |
| 92 | +#define jp $25 /* PIC jump register */ |
| 93 | +#define k0 $26 /* kernel temporary */ |
| 94 | +#define k1 $27 |
| 95 | +#define gp $28 /* global pointer - caller saved for PIC */ |
| 96 | +#define sp $29 /* stack pointer */ |
| 97 | +#define fp $30 /* frame pointer */ |
| 98 | +#define s8 $30 /* callee saved */ |
| 99 | +#define ra $31 /* return address */ |
| 100 | + |
| 101 | +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ |
| 102 | + |
| 103 | +#endif /* _ASM_REGDEF_H */ |
| 104 | |
