| 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Michael Kurz <michi.kurz@googlemail.com>. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef RTL8366_MII_H |
| 25 | #define RTL8366_MII_H |
| 26 | |
| 27 | #define MII_CONTROL_REG 0 |
| 28 | #define MII_STATUS_REG 1 |
| 29 | #define MII_PHY_ID0 2 |
| 30 | #define MII_PHY_ID1 3 |
| 31 | #define MII_LOCAL_CAP 4 |
| 32 | #define MII_REMOTE_CAP 5 |
| 33 | #define MII_EXT_AUTONEG 6 |
| 34 | #define MII_LOCAL_NEXT_PAGE 7 |
| 35 | #define MII_REMOTE_NEXT_PAGE 8 |
| 36 | #define MII_GIGA_CONTROL 9 |
| 37 | #define MII_GIGA_STATUS 10 |
| 38 | #define MII_EXT_STATUS_REG 15 |
| 39 | |
| 40 | /* Control register */ |
| 41 | #define MII_CONTROL_1000MBPS 6 |
| 42 | #define MII_CONTROL_COLL_TEST 7 |
| 43 | #define MII_CONTROL_FULLDUPLEX 8 |
| 44 | #define MII_CONTROL_RENEG 9 |
| 45 | #define MII_CONTROL_ISOLATE 10 |
| 46 | #define MII_CONTROL_POWERDOWN 11 |
| 47 | #define MII_CONTROL_AUTONEG 12 |
| 48 | #define MII_CONTROL_100MBPS 13 |
| 49 | #define MII_CONTROL_LOOPBACK 14 |
| 50 | #define MII_CONTROL_RESET 15 |
| 51 | |
| 52 | /* Status/Extended status register */ |
| 53 | /* Basic status */ |
| 54 | #define MII_STATUS_CAPABILITY 0 |
| 55 | #define MII_STATUS_JABBER 1 |
| 56 | #define MII_STATUS_LINK_UP 2 |
| 57 | #define MII_STATUS_AUTONEG_ABLE 3 |
| 58 | #define MII_STATUS_REMOTE_FAULT 4 |
| 59 | #define MII_STATUS_AUTONEG_DONE 5 |
| 60 | #define MII_STATUS_NO_PREAMBLE 6 |
| 61 | #define MII_STATUS_RESERVED 7 |
| 62 | #define MII_STATUS_EXTENDED 8 |
| 63 | #define MII_STATUS_100_T2_HALF 9 |
| 64 | #define MII_STATUS_100_T2_FULL 10 |
| 65 | #define MII_STATUS_10_TX_HALF 11 |
| 66 | #define MII_STATUS_10_TX_FULL 12 |
| 67 | #define MII_STATUS_100_TX_HALF 13 |
| 68 | #define MII_STATUS_100_TX_FULL 14 |
| 69 | #define MII_STATUS_100_T4 15 |
| 70 | |
| 71 | #define MII_GIGA_CONTROL_HALF 8 |
| 72 | #define MII_GIGA_CONTROL_FULL 9 |
| 73 | #define MII_GIGA_STATUS_HALF 10 |
| 74 | #define MII_GIGA_STATUS_FULL 11 |
| 75 | |
| 76 | /* Extended status */ |
| 77 | #define MII_STATUS_1000_T_HALF 12 |
| 78 | #define MII_STATUS_1000_T_FULL 13 |
| 79 | #define MII_STATUS_1000_X_HALF 14 |
| 80 | #define MII_STATUS_1000_X_FULL 15 |
| 81 | |
| 82 | /* Local/Remmote capability register */ |
| 83 | #define MII_CAP_10BASE_TX 5 |
| 84 | #define MII_CAP_10BASE_TX_FULL 6 |
| 85 | #define MII_CAP_100BASE_TX 7 |
| 86 | #define MII_CAP_100BASE_TX_FULL 8 |
| 87 | #define MII_CAP_100BASE_T4 9 |
| 88 | #define MII_CAP_SYMM_PAUSE 10 |
| 89 | #define MII_CAP_ASYMM_PAUSE 11 |
| 90 | #define MII_CAP_RESERVED 12 |
| 91 | #define MII_CAP_REMOTE_FAULT 13 |
| 92 | #define MII_CAP_ACKNOWLEDGE 14 |
| 93 | #define MII_CAP_NEXT_PAGE 15 |
| 94 | #define MII_CAP_IEEE_802_3 0x0001 |
| 95 | |
| 96 | #define MII_LINK_MODE_MASK 0x1f |
| 97 | |
| 98 | #define REALTEK_RTL8366_CHIP_ID0 0x001C |
| 99 | #define REALTEK_RTL8366_CHIP_ID1 0xC940 |
| 100 | #define REALTEK_RTL8366_CHIP_ID1_MP 0xC960 |
| 101 | |
| 102 | #define REALTEK_MIN_PORT_ID 0 |
| 103 | #define REALTEK_MAX_PORT_ID 5 |
| 104 | #define REALTEK_MIN_PHY_ID REALTEK_MIN_PORT_ID |
| 105 | #define REALTEK_MAX_PHY_ID 4 |
| 106 | #define REALTEK_CPU_PORT_ID REALTEK_MAX_PORT_ID |
| 107 | #define REALTEK_PHY_PORT_MASK ((1<<(REALTEK_MAX_PHY_ID+1)) - (1<<REALTEK_MIN_PHY_ID)) |
| 108 | #define REALTEK_CPU_PORT_MASK (1<<REALTEK_CPU_PORT_ID) |
| 109 | #define REALTEK_ALL_PORT_MASK (REALTEK_PHY_PORT_MASK | REALTEK_CPU_PORT_MASK) |
| 110 | |
| 111 | /* port ability */ |
| 112 | #define RTL8366S_PORT_ABILITY_BASE 0x0011 |
| 113 | |
| 114 | /* port vlan control register */ |
| 115 | #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058 |
| 116 | |
| 117 | /* port linking status */ |
| 118 | #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060 |
| 119 | #define RTL8366S_PORT_STATUS_SPEED_BIT 0 |
| 120 | #define RTL8366S_PORT_STATUS_SPEED_MSK 0x0003 |
| 121 | #define RTL8366S_PORT_STATUS_DUPLEX_BIT 2 |
| 122 | #define RTL8366S_PORT_STATUS_DUPLEX_MSK 0x0004 |
| 123 | #define RTL8366S_PORT_STATUS_LINK_BIT 4 |
| 124 | #define RTL8366S_PORT_STATUS_LINK_MSK 0x0010 |
| 125 | #define RTL8366S_PORT_STATUS_TXPAUSE_BIT 5 |
| 126 | #define RTL8366S_PORT_STATUS_TXPAUSE_MSK 0x0020 |
| 127 | #define RTL8366S_PORT_STATUS_RXPAUSE_BIT 6 |
| 128 | #define RTL8366S_PORT_STATUS_RXPAUSE_MSK 0x0040 |
| 129 | #define RTL8366S_PORT_STATUS_AN_BIT 7 |
| 130 | #define RTL8366S_PORT_STATUS_AN_MSK 0x0080 |
| 131 | |
| 132 | /* internal control */ |
| 133 | #define RTL8366S_RESET_CONTROL_REG 0x0100 |
| 134 | #define RTL8366S_RESET_QUEUE_BIT 2 |
| 135 | |
| 136 | #define RTL8366S_CHIP_ID_REG 0x0105 |
| 137 | |
| 138 | /* MAC control */ |
| 139 | #define RTL8366S_MAC_FORCE_CTRL0_REG 0x0F04 |
| 140 | #define RTL8366S_MAC_FORCE_CTRL1_REG 0x0F05 |
| 141 | |
| 142 | |
| 143 | /* PHY registers control */ |
| 144 | #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028 |
| 145 | #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029 |
| 146 | |
| 147 | #define RTL8366S_PHY_CTRL_READ 1 |
| 148 | #define RTL8366S_PHY_CTRL_WRITE 0 |
| 149 | |
| 150 | #define RTL8366S_PHY_REG_MASK 0x1F |
| 151 | #define RTL8366S_PHY_PAGE_OFFSET 5 |
| 152 | #define RTL8366S_PHY_PAGE_MASK (0x7<<5) |
| 153 | #define RTL8366S_PHY_NO_OFFSET 9 |
| 154 | #define RTL8366S_PHY_NO_MASK (0x1F<<9) |
| 155 | |
| 156 | #define RTL8366S_PHY_NO_MAX 4 |
| 157 | #define RTL8366S_PHY_PAGE_MAX 7 |
| 158 | #define RTL8366S_PHY_ADDR_MAX 31 |
| 159 | |
| 160 | /* cpu port control reg */ |
| 161 | #define RTL8366S_CPU_CTRL_REG 0x004F |
| 162 | #define RTL8366S_CPU_DRP_BIT 14 |
| 163 | #define RTL8366S_CPU_DRP_MSK 0x4000 |
| 164 | #define RTL8366S_CPU_INSTAG_BIT 15 |
| 165 | #define RTL8366S_CPU_INSTAG_MSK 0x8000 |
| 166 | |
| 167 | /* LED registers*/ |
| 168 | #define RTL8366S_LED_BLINK_REG 0x420 |
| 169 | #define RTL8366S_LED_BLINKRATE_BIT 0 |
| 170 | #define RTL8366S_LED_BLINKRATE_MSK 0x0007 |
| 171 | #define RTL8366S_LED_INDICATED_CONF_REG 0x421 |
| 172 | #define RTL8366S_LED_0_1_FORCE_REG 0x422 |
| 173 | #define RTL8366S_LED_2_3_FORCE_REG 0x423 |
| 174 | #define RTL8366S_LEDCONF_LEDFORCE 0x1F |
| 175 | #define RTL8366S_LED_GROUP_MAX 4 |
| 176 | |
| 177 | #define RTL8366S_GREEN_FEATURE_REG 0x000A |
| 178 | #define RTL8366S_GREEN_FEATURE_TX_BIT 3 |
| 179 | #define RTL8366S_GREEN_FEATURE_TX_MSK 0x0008 |
| 180 | #define RTL8366S_GREEN_FEATURE_RX_BIT 4 |
| 181 | #define RTL8366S_GREEN_FEATURE_RX_MSK 0x0010 |
| 182 | |
| 183 | #define RTL8366S_MODEL_ID_REG 0x5C |
| 184 | #define RTL8366S_REV_ID_REG 0x5D |
| 185 | #define RTL8366S_MODEL_8366SR 0x6027 |
| 186 | #define RTL8366S_MODEL_8366RB 0x5937 |
| 187 | |
| 188 | #endif |
| 189 | |
