Root/package/platform/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_amazon_se.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <asm/delay.h>
44
45/*
46 * Chip Specific Head File
47 */
48#include "ifxmips_atm_core.h"
49#include "ifxmips_atm_fw_amazon_se.h"
50
51#include <lantiq_soc.h>
52
53#define EMA_CMD_BUF_LEN 0x0040
54#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
55#define EMA_DATA_BUF_LEN 0x0100
56#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
57#define EMA_WRITE_BURST 0x2
58#define EMA_READ_BURST 0x2
59
60
61
62/*
63 * ####################################
64 * Definition
65 * ####################################
66 */
67
68/*
69 * EMA Settings
70 */
71#define EMA_CMD_BUF_LEN 0x0040
72#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
73#define EMA_DATA_BUF_LEN 0x0100
74#define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
75#define EMA_WRITE_BURST 0x2
76#define EMA_READ_BURST 0x2
77
78
79
80/*
81 * ####################################
82 * Declaration
83 * ####################################
84 */
85
86/*
87 * Hardware Init/Uninit Functions
88 */
89static inline void init_pmu(void);
90static inline void uninit_pmu(void);
91static inline void reset_ppe(void);
92static inline void init_ema(void);
93static inline void init_mailbox(void);
94static inline void init_atm_tc(void);
95static inline void clear_share_buffer(void);
96
97
98
99/*
100 * ####################################
101 * Local Variable
102 * ####################################
103 */
104
105
106
107/*
108 * ####################################
109 * Local Function
110 * ####################################
111 */
112#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
113#define IFX_PMU_MODULE_PPE_TC BIT(21)
114#define IFX_PMU_MODULE_PPE_EMA BIT(22)
115#define IFX_PMU_MODULE_PPE_QSB BIT(18)
116#define IFX_PMU_MODULE_TPE BIT(13)
117#define IFX_PMU_MODULE_DSL_DFE BIT(9)
118
119static inline void init_pmu(void)
120{
121    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
122    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
123/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
124    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
125    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
126    //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
127    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
128    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
129    ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
130        IFX_PMU_MODULE_PPE_TC |
131        IFX_PMU_MODULE_PPE_EMA |
132        IFX_PMU_MODULE_TPE |
133        IFX_PMU_MODULE_DSL_DFE);
134}
135
136static inline void uninit_pmu(void)
137{
138    /*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
139    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
140    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
141    //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
142    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
143    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
144    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
145}
146
147static inline void reset_ppe(void)
148{
149#if 0 //MODULE
150    unsigned int etop_cfg;
151    unsigned int etop_mdio_cfg;
152    unsigned int etop_ig_plen_ctrl;
153    unsigned int enet_mac_cfg;
154
155    etop_cfg = *IFX_PP32_ETOP_CFG;
156    etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
157    etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
158    enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
159
160    *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
161
162    // reset PPE
163    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
164
165    *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
166    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
167    *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
168    *IFX_PP32_ETOP_CFG = etop_cfg;
169#endif
170}
171
172static inline void init_ema(void)
173{
174    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
175    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
176    IFX_REG_W32(0x000000FF, EMA_IER);
177    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
178}
179
180static inline void init_mailbox(void)
181{
182    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
183    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
184    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
185    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
186}
187
188static inline void init_atm_tc(void)
189{
190    IFX_REG_W32(0x0000, DREG_AT_CTRL);
191    IFX_REG_W32(0x0000, DREG_AR_CTRL);
192    IFX_REG_W32(0x0, DREG_AT_IDLE0);
193    IFX_REG_W32(0x0, DREG_AT_IDLE1);
194    IFX_REG_W32(0x0, DREG_AR_IDLE0);
195    IFX_REG_W32(0x0, DREG_AR_IDLE1);
196    IFX_REG_W32(0x40, RFBI_CFG);
197    IFX_REG_W32(0x0700, SFSM_DBA0);
198    IFX_REG_W32(0x0818, SFSM_DBA1);
199    IFX_REG_W32(0x0930, SFSM_CBA0);
200    IFX_REG_W32(0x0944, SFSM_CBA1);
201    IFX_REG_W32(0x14014, SFSM_CFG0);
202    IFX_REG_W32(0x14014, SFSM_CFG1);
203    IFX_REG_W32(0x0958, FFSM_DBA0);
204    IFX_REG_W32(0x09AC, FFSM_DBA1);
205    IFX_REG_W32(0x10006, FFSM_CFG0);
206    IFX_REG_W32(0x10006, FFSM_CFG1);
207    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
208    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
209}
210
211static inline void clear_share_buffer(void)
212{
213    volatile u32 *p = SB_RAM0_ADDR(0);
214    unsigned int i;
215
216    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
217        IFX_REG_W32(0, p++);
218}
219
220/*
221 * Description:
222 * Download PPE firmware binary code.
223 * Input:
224 * src --- u32 *, binary code buffer
225 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
226 * Output:
227 * int --- 0: Success
228 * else: Error Code
229 */
230static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
231{
232    volatile u32 *dest;
233
234    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
235        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
236        return -1;
237
238    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
239        IFX_REG_W32(0x00, CDM_CFG);
240    else
241        IFX_REG_W32(0x04, CDM_CFG);
242
243    /* copy code */
244    dest = CDM_CODE_MEMORY(0, 0);
245    while ( code_dword_len-- > 0 )
246        IFX_REG_W32(*code_src++, dest++);
247
248    /* copy data */
249    dest = CDM_DATA_MEMORY(0, 0);
250    while ( data_dword_len-- > 0 )
251        IFX_REG_W32(*data_src++, dest++);
252
253    return 0;
254}
255
256
257
258/*
259 * ####################################
260 * Global Function
261 * ####################################
262 */
263
264extern void ase_fw_ver(unsigned int *major, unsigned int *minor)
265{
266    ASSERT(major != NULL, "pointer is NULL");
267    ASSERT(minor != NULL, "pointer is NULL");
268
269    *major = FW_VER_ID->major;
270    *minor = FW_VER_ID->minor;
271}
272
273void ase_init(void)
274{
275    init_pmu();
276
277    reset_ppe();
278
279    init_ema();
280
281    init_mailbox();
282
283    init_atm_tc();
284
285    clear_share_buffer();
286}
287
288void ase_shutdown(void)
289{
290    uninit_pmu();
291}
292
293/*
294 * Description:
295 * Initialize and start up PP32.
296 * Input:
297 * none
298 * Output:
299 * int --- 0: Success
300 * else: Error Code
301 */
302int ase_start(int pp32)
303{
304    int ret;
305
306    /* download firmware */
307    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
308    if ( ret != 0 )
309        return ret;
310
311    /* run PP32 */
312    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
313
314    /* idle for a while to let PP32 init itself */
315    udelay(10);
316
317    return 0;
318}
319
320/*
321 * Description:
322 * Halt PP32.
323 * Input:
324 * none
325 * Output:
326 * none
327 */
328void ase_stop(int pp32)
329{
330    /* halt PP32 */
331    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
332}
333
334struct ltq_atm_ops ase_ops = {
335    .init = ase_init,
336    .shutdown = ase_shutdown,
337    .start = ase_start,
338    .stop = ase_stop,
339    .fw_ver = ase_fw_ver,
340};
341
342

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive