| 1 | /****************************************************************************** |
| 2 | ** |
| 3 | ** FILE NAME : ifxmips_atm_ppe_danube.h |
| 4 | ** PROJECT : UEIP |
| 5 | ** MODULES : ATM (ADSL) |
| 6 | ** |
| 7 | ** DATE : 1 AUG 2005 |
| 8 | ** AUTHOR : Xu Liang |
| 9 | ** DESCRIPTION : ATM Driver (PPE Registers) |
| 10 | ** COPYRIGHT : Copyright (c) 2006 |
| 11 | ** Infineon Technologies AG |
| 12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
| 13 | ** |
| 14 | ** This program is free software; you can redistribute it and/or modify |
| 15 | ** it under the terms of the GNU General Public License as published by |
| 16 | ** the Free Software Foundation; either version 2 of the License, or |
| 17 | ** (at your option) any later version. |
| 18 | ** |
| 19 | ** HISTORY |
| 20 | ** $Date $Author $Comment |
| 21 | ** 4 AUG 2005 Xu Liang Initiate Version |
| 22 | ** 23 OCT 2006 Xu Liang Add GPL header. |
| 23 | ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) |
| 24 | *******************************************************************************/ |
| 25 | |
| 26 | |
| 27 | |
| 28 | #ifndef IFXMIPS_ATM_PPE_DANUBE_H |
| 29 | #define IFXMIPS_ATM_PPE_DANUBE_H |
| 30 | |
| 31 | |
| 32 | |
| 33 | /* |
| 34 | * FPI Configuration Bus Register and Memory Address Mapping |
| 35 | */ |
| 36 | #define IFX_PPE (KSEG1 | 0x1E180000) |
| 37 | #define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) |
| 38 | #define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) |
| 39 | #define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) |
| 40 | #define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) |
| 41 | #define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) |
| 42 | #define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) |
| 43 | #define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) |
| 44 | #define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) |
| 45 | #define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) |
| 46 | #define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) |
| 47 | #define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) |
| 48 | #define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2))) |
| 49 | #define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2))) |
| 50 | #define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2))) |
| 51 | #define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2))) |
| 52 | #define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) |
| 53 | |
| 54 | /* |
| 55 | * DWORD-Length of Memory Blocks |
| 56 | */ |
| 57 | #define PP32_DEBUG_REG_DWLEN 0x0030 |
| 58 | #define PPM_INT_REG_DWLEN 0x0010 |
| 59 | #define PP32_INTERNAL_RES_DWLEN 0x00C0 |
| 60 | #define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) |
| 61 | #define PPE_REG_DWLEN 0x1000 |
| 62 | #define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) |
| 63 | #define PPM_INT_UNIT_DWLEN 0x0100 |
| 64 | #define PPM_TIMER0_DWLEN 0x0100 |
| 65 | #define PPM_TASK_IND_REG_DWLEN 0x0100 |
| 66 | #define PPS_BRK_DWLEN 0x0100 |
| 67 | #define PPM_TIMER1_DWLEN 0x0100 |
| 68 | #define SB_RAM0_DWLEN 0x0400 |
| 69 | #define SB_RAM1_DWLEN 0x0800 |
| 70 | #define SB_RAM2_DWLEN 0x0A00 |
| 71 | #define SB_RAM3_DWLEN 0x0400 |
| 72 | #define QSB_CONF_REG_DWLEN 0x0100 |
| 73 | |
| 74 | /* |
| 75 | * PP32 to FPI Address Mapping |
| 76 | */ |
| 77 | #define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \ |
| 78 | (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \ |
| 79 | (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \ |
| 80 | (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \ |
| 81 | 0)) |
| 82 | |
| 83 | /* |
| 84 | * PP32 Debug Control Register |
| 85 | */ |
| 86 | #define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) |
| 87 | |
| 88 | #define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0) |
| 89 | #define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0) |
| 90 | #define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0) |
| 91 | |
| 92 | #define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001) |
| 93 | |
| 94 | #define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002) |
| 95 | |
| 96 | #define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i)) |
| 97 | #define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i)) |
| 98 | #define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i)) |
| 99 | #define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i)) |
| 100 | #define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i)) |
| 101 | |
| 102 | #define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080) |
| 103 | |
| 104 | #define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081) |
| 105 | |
| 106 | #define PP32_DBG_REG_BASE(tsk, i) PP32_DEBUG_REG_ADDR(0, 0x0100 + (tsk) * 16 + (i)) |
| 107 | |
| 108 | /* |
| 109 | * EMA Registers |
| 110 | */ |
| 111 | #define EMA_CMDCFG PPE_REG_ADDR(0x0A00) |
| 112 | #define EMA_DATACFG PPE_REG_ADDR(0x0A01) |
| 113 | #define EMA_CMDCNT PPE_REG_ADDR(0x0A02) |
| 114 | #define EMA_DATACNT PPE_REG_ADDR(0x0A03) |
| 115 | #define EMA_ISR PPE_REG_ADDR(0x0A04) |
| 116 | #define EMA_IER PPE_REG_ADDR(0x0A05) |
| 117 | #define EMA_CFG PPE_REG_ADDR(0x0A06) |
| 118 | #define EMA_SUBID PPE_REG_ADDR(0x0A07) |
| 119 | |
| 120 | #define EMA_ALIGNMENT 4 |
| 121 | |
| 122 | /* |
| 123 | * Mailbox IGU1 Interrupt |
| 124 | */ |
| 125 | #define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 |
| 126 | |
| 127 | |
| 128 | |
| 129 | #endif // IFXMIPS_ATM_PPE_DANUBE_H |
| 130 | |
