Root/package/platform/lantiq/ltq-atm/src/ifxmips_atm_vr9.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_vr9.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <asm/delay.h>
44
45#include "ifxmips_atm_core.h"
46#include "ifxmips_atm_fw_vr9.h"
47
48#ifdef CONFIG_VR9
49
50#include <lantiq_soc.h>
51
52#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
53#define IFX_PMU_MODULE_PPE_TC BIT(21)
54#define IFX_PMU_MODULE_PPE_EMA BIT(22)
55#define IFX_PMU_MODULE_PPE_QSB BIT(18)
56#define IFX_PMU_MODULE_AHBS BIT(13)
57#define IFX_PMU_MODULE_DSL_DFE BIT(9)
58
59static inline void vr9_reset_ppe(void)
60{
61/*#ifdef MODULE
62    // reset PPE
63    ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
64    udelay(1000);
65    ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
66    udelay(1000);
67    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
68    udelay(1000);
69    *PP32_SRST &= ~0x000303CF;
70    udelay(1000);
71    *PP32_SRST |= 0x000303CF;
72    udelay(1000);
73#endif*/
74}
75
76static inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
77{
78    unsigned int clr, set;
79    volatile u32 *dest;
80
81    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
82            || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
83        return -1;
84
85    clr = pp32 ? 0xF0 : 0x0F;
86    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
87        set = pp32 ? (3 << 6): (2 << 2);
88    else
89        set = 0x00;
90    IFX_REG_W32_MASK(clr, set, CDM_CFG);
91
92    dest = CDM_CODE_MEMORY(pp32, 0);
93    while ( code_dword_len-- > 0 )
94        IFX_REG_W32(*code_src++, dest++);
95
96    dest = CDM_DATA_MEMORY(pp32, 0);
97    while ( data_dword_len-- > 0 )
98        IFX_REG_W32(*data_src++, dest++);
99
100    return 0;
101}
102
103static void vr9_fw_ver(unsigned int *major, unsigned int *minor)
104{
105
106    *major = FW_VER_ID->major;
107    *minor = FW_VER_ID->minor;
108}
109
110static void vr9_init(void)
111{
112    volatile u32 *p;
113    unsigned int i;
114
115    /* setup pmu */
116    ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
117        IFX_PMU_MODULE_PPE_TC |
118        IFX_PMU_MODULE_PPE_EMA |
119        IFX_PMU_MODULE_PPE_QSB |
120        IFX_PMU_MODULE_AHBS |
121        IFX_PMU_MODULE_DSL_DFE);
122
123    vr9_reset_ppe();
124
125    /* pdma init */
126    IFX_REG_W32(0x08, PDMA_CFG);
127    IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
128    IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
129
130    /* mailbox init */
131    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
132    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
133    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
134    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
135
136    /* tc init - clear sync state */
137    *SFSM_STATE0 = 0;
138    *SFSM_STATE1 = 0;
139
140    /* init shared buffer */
141    p = SB_RAM0_ADDR(0);
142    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
143        IFX_REG_W32(0, p++);
144
145    p = SB_RAM6_ADDR(0);
146    for ( i = 0; i < SB_RAM6_DWLEN; i++ )
147        IFX_REG_W32(0, p++);
148}
149
150static void vr9_shutdown(void)
151{
152}
153
154static int vr9_start(int pp32)
155{
156    unsigned int mask = 1 << (pp32 << 4);
157    int ret;
158
159    /* download firmware */
160    ret = vr9_pp32_download_code(pp32,
161        vr9_fw_bin, sizeof(vr9_fw_bin) / sizeof(*vr9_fw_bin),
162        vr9_fw_data, sizeof(vr9_fw_data) / sizeof(*vr9_fw_data));
163    if ( ret != 0 )
164        return ret;
165
166    /* run PP32 */
167    IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
168
169    /* idle for a while to let PP32 init itself */
170    udelay(10);
171
172    return 0;
173}
174
175static void vr9_stop(int pp32)
176{
177    unsigned int mask = 1 << (pp32 << 4);
178
179    IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
180}
181
182struct ltq_atm_ops vr9_ops = {
183    .init = vr9_init,
184    .shutdown = vr9_shutdown,
185    .start = vr9_start,
186    .stop = vr9_stop,
187    .fw_ver = vr9_fw_ver,
188};
189
190#endif
191

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