Root/package/platform/lantiq/ltq-deu/src/ifxmips_deu_ar9.h

1/******************************************************************************
2**
3** FILE NAME : ifxmips_deu_ar9.h
4** PROJECT : IFX UEIP
5** MODULES : DEU Module for AR9
6**
7** DATE : September 8, 2009
8** AUTHOR : Mohammad Firdaus
9** DESCRIPTION : Data Encryption Unit Driver
10** COPYRIGHT : Copyright (c) 2009
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
22*******************************************************************************/
23/*!
24  \defgroup IFX_DEU IFX_DEU_DRIVERS
25  \ingroup API
26  \brief deu driver module
27*/
28
29/*!
30  \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
31  \ingroup IFX_DEU
32  \brief ifx deu definitions
33*/
34
35/*!
36  \file ifxmips_deu_ar9.h
37  \brief deu driver header file
38*/
39
40
41#ifndef IFXMIPS_DEU_AR9_H
42#define IFXMIPS_DEU_AR9_H
43
44/* Project Header Files */
45#include <linux/version.h>
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/types.h>
49#include <linux/errno.h>
50#include <linux/crypto.h>
51#include <linux/interrupt.h>
52#include <linux/delay.h>
53#include <asm/byteorder.h>
54#include <crypto/algapi.h>
55#include <linux/module.h>
56#include <linux/mm.h>
57#include <asm/scatterlist.h>
58#include <linux/skbuff.h>
59#include <linux/netdevice.h>
60#include "ifxmips_deu.h"
61
62
63/* SHA CONSTANTS */
64#define HASH_CON_VALUE 0x0700002C
65
66#define INPUT_ENDIAN_SWAP(input) input_swap(input)
67#define DEU_ENDIAN_SWAP(input) endian_swap(input)
68#define DELAY_PERIOD 10
69#define FIND_DEU_CHIP_VERSION chip_version()
70#define CLC_START IFX_DEU_CLK
71
72#define AES_INIT 0
73#define DES_INIT 1
74#define ARC4_INIT 2
75#define SHA1_INIT 3
76#define MD5_INIT 4
77#define SHA1_HMAC_INIT 5
78#define MD5_HMAC_INIT 6
79
80#define AES_START IFX_AES_CON
81#define DES_3DES_START IFX_DES_CON
82                      
83#define WAIT_AES_DMA_READY() \
84    do { \
85        int i; \
86        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
87        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
88        for (i = 0; i < 10; i++) \
89        udelay(DELAY_PERIOD); \
90        while (dma->controlr.BSY) {}; \
91        while (aes->controlr.BUS) {}; \
92    } while (0)
93
94#define WAIT_DES_DMA_READY() \
95    do { \
96        int i; \
97        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
98        volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
99        for (i = 0; i < 10; i++) \
100            udelay(DELAY_PERIOD); \
101        while (dma->controlr.BSY) {}; \
102        while (des->controlr.BUS) {}; \
103    } while (0)
104
105#define AES_DMA_MISC_CONFIG() \
106    do { \
107        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
108        aes->controlr.KRE = 1; \
109        aes->controlr.GO = 1; \
110    } while(0)
111
112#define SHA_HASH_INIT \
113    do { \
114        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
115        hash->controlr.SM = 1; \
116        hash->controlr.ALGO = 0; \
117        hash->controlr.INIT = 1; \
118    } while(0)
119
120/* DEU Common Structures for AR9*/
121 
122struct clc_controlr_t {
123    u32 Res:26;
124    u32 FSOE:1;
125    u32 SBWE:1;
126    u32 EDIS:1;
127    u32 SPEN:1;
128    u32 DISS:1;
129    u32 DISR:1;
130
131};
132
133struct des_t {
134    struct des_controlr { //10h
135        u32 KRE:1;
136        u32 reserved1:5;
137        u32 GO:1;
138        u32 STP:1;
139        u32 Res2:6;
140                u32 NDC:1;
141                u32 ENDI:1;
142                u32 Res3:2;
143        u32 F:3;
144        u32 O:3;
145        u32 BUS:1;
146        u32 DAU:1;
147        u32 ARS:1;
148        u32 SM:1;
149        u32 E_D:1;
150        u32 M:3;
151
152    } controlr;
153    u32 IHR; //14h
154    u32 ILR; //18h
155    u32 K1HR; //1c
156    u32 K1LR; //
157    u32 K2HR;
158    u32 K2LR;
159    u32 K3HR;
160    u32 K3LR; //30h
161    u32 IVHR; //34h
162    u32 IVLR; //38
163    u32 OHR; //3c
164    u32 OLR; //40
165};
166
167struct aes_t {
168    struct aes_controlr {
169
170        u32 KRE:1;
171        u32 reserved1:4;
172        u32 PNK:1;
173        u32 GO:1;
174        u32 STP:1;
175        u32 reserved2:6;
176        u32 NDC:1;
177        u32 ENDI:1;
178                u32 reserved3:2;
179        u32 F:3; //fbs
180        u32 O:3; //om
181        u32 BUS:1; //bsy
182        u32 DAU:1;
183        u32 ARS:1;
184        u32 SM:1;
185        u32 E_D:1;
186        u32 KV:1;
187        u32 K:2; //KL
188
189    } controlr;
190    u32 ID3R; //80h
191    u32 ID2R; //84h
192    u32 ID1R; //88h
193    u32 ID0R; //8Ch
194    u32 K7R; //90h
195    u32 K6R; //94h
196    u32 K5R; //98h
197    u32 K4R; //9Ch
198    u32 K3R; //A0h
199    u32 K2R; //A4h
200    u32 K1R; //A8h
201    u32 K0R; //ACh
202    u32 IV3R; //B0h
203    u32 IV2R; //B4h
204    u32 IV1R; //B8h
205    u32 IV0R; //BCh
206    u32 OD3R; //D4h
207    u32 OD2R; //D8h
208    u32 OD1R; //DCh
209    u32 OD0R; //E0h
210};
211
212struct arc4_t {
213    struct arc4_controlr {
214
215        u32 KRE:1;
216        u32 KLEN:4;
217        u32 KSAE:1;
218        u32 GO:1;
219        u32 STP:1;
220        u32 reserved1:6;
221        u32 NDC:1;
222        u32 ENDI:1;
223        u32 reserved2:8;
224        u32 BUS:1; //bsy
225        u32 reserved3:1;
226        u32 ARS:1;
227        u32 SM:1;
228        u32 reserved4:4;
229
230    } controlr;
231    u32 K3R; //104h
232    u32 K2R; //108h
233    u32 K1R; //10Ch
234    u32 K0R; //110h
235
236        u32 IDLEN; //114h
237
238    u32 ID3R; //118h
239    u32 ID2R; //11Ch
240    u32 ID1R; //120h
241    u32 ID0R; //124h
242    
243    u32 OD3R; //128h
244    u32 OD2R; //12Ch
245    u32 OD1R; //130h
246    u32 OD0R; //134h
247};
248
249struct deu_hash_t {
250    struct hash_controlr {
251        u32 reserved1:5;
252        u32 KHS:1;
253        u32 GO:1;
254        u32 INIT:1;
255        u32 reserved2:6;
256        u32 NDC:1;
257        u32 ENDI:1;
258        u32 reserved3:7;
259        u32 DGRY:1;
260        u32 BSY:1;
261        u32 reserved4:1;
262        u32 IRCL:1;
263        u32 SM:1;
264        u32 KYUE:1;
265                u32 HMEN:1;
266        u32 SSEN:1;
267        u32 ALGO:1;
268
269    } controlr;
270    u32 MR; //B4h
271    u32 D1R; //B8h
272    u32 D2R; //BCh
273    u32 D3R; //C0h
274    u32 D4R; //C4h
275    u32 D5R; //C8h
276
277    u32 dummy; //CCh
278
279    u32 KIDX; //D0h
280    u32 KEY; //D4h
281    u32 DBN; //D8h
282};
283
284
285struct deu_dma_t {
286    struct dma_controlr {
287        u32 reserved1:22;
288        u32 BS:2;
289        u32 BSY:1;
290        u32 reserved2:1;
291        u32 ALGO:2;
292        u32 RXCLS:2;
293        u32 reserved3:1;
294        u32 EN:1;
295
296    } controlr;
297};
298
299#endif /* IFXMIPS_DEU_AR9_H */
300

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