Root/package/platform/lantiq/ltq-deu/src/ifxmips_deu_danube.h

1/******************************************************************************
2**
3** FILE NAME : ifxmips_deu_danube.h
4** PROJECT : IFX UEIP
5** MODULES : DEU Module for Danube
6**
7** DATE : September 8, 2009
8** AUTHOR : Mohammad Firdaus
9** DESCRIPTION : Data Encryption Unit Driver
10** COPYRIGHT : Copyright (c) 2009
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
22*******************************************************************************/
23/*!
24  \defgroup IFX_DEU IFX_DEU_DRIVERS
25  \ingroup API
26  \brief deu driver module
27*/
28
29/*!
30  \file ifxmips_deu_danube.h
31  \brief board specific driver header file for danube
32*/
33
34/*!
35  \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS
36  \ingroup IFX_DEU
37  \brief board specific deu header files
38*/
39
40#ifndef IFXMIPS_DEU_DANUBE_H
41#define IFXMIPS_DEU_DANUBE_H
42
43/* Project Header Files */
44#include <linux/version.h>
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/types.h>
48#include <linux/errno.h>
49#include <linux/crypto.h>
50#include <linux/interrupt.h>
51#include <linux/delay.h>
52#include <asm/byteorder.h>
53#include <crypto/algapi.h>
54#include <linux/module.h>
55#include <linux/mm.h>
56#include <asm/scatterlist.h>
57#include <linux/skbuff.h>
58#include <linux/netdevice.h>
59#include "ifxmips_deu.h"
60
61
62
63#define INPUT_ENDIAN_SWAP(input) input_swap(input)
64#define DEU_ENDIAN_SWAP(input) endian_swap(input)
65#define FIND_DEU_CHIP_VERSION chip_version()
66#define AES_DMA_MISC_CONFIG()
67#define CLC_START IFX_DEU_CLK
68
69#define AES_START IFX_AES_CON
70#define DES_3DES_START IFX_DES_CON
71
72#define AES_INIT 0
73#define DES_INIT 1
74#define SHA1_INIT 2
75#define MD5_INIT 3
76
77#define WAIT_AES_DMA_READY() \
78    do { \
79        int i; \
80        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
81        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
82        for (i = 0; i < 10; i++) \
83            udelay(DELAY_PERIOD); \
84        while (dma->controlr.BSY) {}; \
85        while (aes->controlr.BUS) {}; \
86    } while (0)
87
88#define WAIT_DES_DMA_READY() \
89    do { \
90        int i; \
91        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
92        volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
93        for (i = 0; i < 10; i++) \
94            udelay(DELAY_PERIOD); \
95        while (dma->controlr.BSY) {}; \
96        while (des->controlr.BUS) {}; \
97    } while (0)
98
99#define SHA_HASH_INIT \
100    do { \
101        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
102        hash->controlr.SM = 1; \
103        hash->controlr.ALGO = 0; \
104        hash->controlr.INIT = 1; \
105    } while(0)
106
107/* DEU STRUCTURES */
108
109struct clc_controlr_t {
110    u32 Res:26;
111    u32 FSOE:1;
112    u32 SBWE:1;
113    u32 EDIS:1;
114    u32 SPEN:1;
115    u32 DISS:1;
116    u32 DISR:1;
117
118};
119
120struct des_t {
121    struct des_controlr { //10h
122        u32 KRE:1;
123        u32 reserved1:5;
124        u32 GO:1;
125        u32 STP:1;
126        u32 Res2:6;
127        u32 NDC:1;
128        u32 ENDI:1;
129        u32 Res3:2;
130        u32 F:3;
131        u32 O:3;
132        u32 BUS:1;
133        u32 DAU:1;
134        u32 ARS:1;
135        u32 SM:1;
136        u32 E_D:1;
137        u32 M:3;
138
139    } controlr;
140    u32 IHR; //14h
141    u32 ILR; //18h
142    u32 K1HR; //1c
143    u32 K1LR; //
144    u32 K2HR;
145    u32 K2LR;
146    u32 K3HR;
147    u32 K3LR; //30h
148    u32 IVHR; //34h
149    u32 IVLR; //38
150    u32 OHR; //3c
151    u32 OLR; //40
152};
153
154struct aes_t {
155    struct aes_controlr {
156
157        u32 KRE:1;
158        u32 reserved1:4;
159        u32 PNK:1;
160        u32 GO:1;
161        u32 STP:1;
162        
163        u32 reserved2:6;
164        u32 NDC:1;
165        u32 ENDI:1;
166        u32 reserved3:2;
167        
168        u32 F:3; //fbs
169        u32 O:3; //om
170        u32 BUS:1; //bsy
171        u32 DAU:1;
172        u32 ARS:1;
173        u32 SM:1;
174        u32 E_D:1;
175        u32 KV:1;
176        u32 K:2; //KL
177
178    } controlr;
179    u32 ID3R; //80h
180    u32 ID2R; //84h
181    u32 ID1R; //88h
182    u32 ID0R; //8Ch
183    u32 K7R; //90h
184    u32 K6R; //94h
185    u32 K5R; //98h
186    u32 K4R; //9Ch
187    u32 K3R; //A0h
188    u32 K2R; //A4h
189    u32 K1R; //A8h
190    u32 K0R; //ACh
191    u32 IV3R; //B0h
192    u32 IV2R; //B4h
193    u32 IV1R; //B8h
194    u32 IV0R; //BCh
195    u32 OD3R; //D4h
196    u32 OD2R; //D8h
197    u32 OD1R; //DCh
198    u32 OD0R; //E0h
199};
200
201struct deu_hash_t {
202    struct hash_controlr {
203        u32 reserved1:5;
204        u32 KHS:1;
205        u32 GO:1;
206        u32 INIT:1;
207        u32 reserved2:6;
208        u32 NDC:1;
209        u32 ENDI:1;
210        u32 reserved3:7;
211        u32 DGRY:1;
212        u32 BSY:1;
213        u32 reserved4:1;
214        u32 IRCL:1;
215        u32 SM:1;
216        u32 KYUE:1;
217                u32 HMEN:1;
218        u32 SSEN:1;
219        u32 ALGO:1;
220
221    } controlr;
222    u32 MR; //B4h
223    u32 D1R; //B8h
224    u32 D2R; //BCh
225    u32 D3R; //C0h
226    u32 D4R; //C4h
227    u32 D5R; //C8h
228
229    u32 dummy; //CCh
230
231    u32 KIDX; //D0h
232    u32 KEY; //D4h
233    u32 DBN; //D8h
234};
235
236struct deu_dma_t {
237    struct dma_controlr {
238        u32 reserved1:22;
239        u32 BS:2;
240        u32 BSY:1;
241        u32 reserved2:1;
242        u32 ALGO:2;
243        u32 RXCLS:2;
244        u32 reserved3:1;
245        u32 EN:1;
246
247    } controlr;
248};
249
250#endif /* IFXMIPS_DEU_DANUBE_H */
251

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