| 1 | /***************************************************************************** |
| 2 | ** FILE NAME : ifxusb_cif_h.c |
| 3 | ** PROJECT : IFX USB sub-system V3 |
| 4 | ** MODULES : IFX USB sub-system Host and Device driver |
| 5 | ** SRC VERSION : 3.2 |
| 6 | ** DATE : 1/Jan/2011 |
| 7 | ** AUTHOR : Chen, Howard |
| 8 | ** DESCRIPTION : The Core Interface provides basic services for accessing and |
| 9 | ** managing the IFX USB hardware. These services are used by the |
| 10 | ** Host Controller Driver only. |
| 11 | ** FUNCTIONS : |
| 12 | ** COMPILER : gcc |
| 13 | ** REFERENCE : Synopsys DWC-OTG Driver 2.7 |
| 14 | ** COPYRIGHT : Copyright (c) 2010 |
| 15 | ** LANTIQ DEUTSCHLAND GMBH, |
| 16 | ** Am Campeon 3, 85579 Neubiberg, Germany |
| 17 | ** |
| 18 | ** This program is free software; you can redistribute it and/or modify |
| 19 | ** it under the terms of the GNU General Public License as published by |
| 20 | ** the Free Software Foundation; either version 2 of the License, or |
| 21 | ** (at your option) any later version. |
| 22 | ** |
| 23 | ** Version Control Section ** |
| 24 | ** $Author$ |
| 25 | ** $Date$ |
| 26 | ** $Revisions$ |
| 27 | ** $Log$ Revision history |
| 28 | *****************************************************************************/ |
| 29 | |
| 30 | /* |
| 31 | * This file contains code fragments from Synopsys HS OTG Linux Software Driver. |
| 32 | * For this code the following notice is applicable: |
| 33 | * |
| 34 | * ========================================================================== |
| 35 | * |
| 36 | * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
| 37 | * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
| 38 | * otherwise expressly agreed to in writing between Synopsys and you. |
| 39 | * |
| 40 | * The Software IS NOT an item of Licensed Software or Licensed Product under |
| 41 | * any End User Software License Agreement or Agreement for Licensed Product |
| 42 | * with Synopsys or any supplement thereto. You are permitted to use and |
| 43 | * redistribute this Software in source and binary forms, with or without |
| 44 | * modification, provided that redistributions of source code must retain this |
| 45 | * notice. You may not view, use, disclose, copy or distribute this file or |
| 46 | * any information contained herein except pursuant to this license grant from |
| 47 | * Synopsys. If you do not agree with this notice, including the disclaimer |
| 48 | * below, then you are not authorized to use the Software. |
| 49 | * |
| 50 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
| 51 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 52 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 53 | * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
| 54 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 55 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 56 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 57 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 58 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 59 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 60 | * DAMAGE. |
| 61 | * ========================================================================== */ |
| 62 | |
| 63 | /*! |
| 64 | \file ifxusb_cif_h.c |
| 65 | \ingroup IFXUSB_DRIVER_V3 |
| 66 | \brief This file contains the interface to the IFX USB Core. |
| 67 | */ |
| 68 | #include <linux/version.h> |
| 69 | #include "ifxusb_version.h" |
| 70 | |
| 71 | #include <asm/byteorder.h> |
| 72 | #include <asm/unaligned.h> |
| 73 | |
| 74 | #ifdef __DEBUG__ |
| 75 | #include <linux/jiffies.h> |
| 76 | #endif |
| 77 | #include <linux/platform_device.h> |
| 78 | #include <linux/kernel.h> |
| 79 | #include <linux/ioport.h> |
| 80 | |
| 81 | #include "ifxusb_plat.h" |
| 82 | #include "ifxusb_regs.h" |
| 83 | #include "ifxusb_cif.h" |
| 84 | |
| 85 | #include "ifxhcd.h" |
| 86 | |
| 87 | #if !defined(__UEIP__) |
| 88 | #undef __USING_LED_AS_GPIO__ |
| 89 | #endif |
| 90 | |
| 91 | |
| 92 | /*! |
| 93 | \brief This function enables the Host mode interrupts. |
| 94 | \param _core_if Pointer of core_if structure |
| 95 | */ |
| 96 | void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if) |
| 97 | { |
| 98 | gint_data_t intr_mask ={ .d32 = 0}; |
| 99 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 100 | |
| 101 | IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__); |
| 102 | |
| 103 | /* Clear any pending OTG Interrupts */ |
| 104 | ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF); |
| 105 | |
| 106 | /* Clear any pending interrupts */ |
| 107 | ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF); |
| 108 | |
| 109 | /* Enable the interrupts in the GINTMSK.*/ |
| 110 | |
| 111 | /* Common interrupts */ |
| 112 | intr_mask.b.modemismatch = 1; |
| 113 | intr_mask.b.conidstschng = 1; |
| 114 | intr_mask.b.wkupintr = 1; |
| 115 | intr_mask.b.disconnect = 1; |
| 116 | intr_mask.b.usbsuspend = 1; |
| 117 | |
| 118 | /* Host interrupts */ |
| 119 | intr_mask.b.sofintr = 1; |
| 120 | intr_mask.b.portintr = 1; |
| 121 | intr_mask.b.hcintr = 1; |
| 122 | |
| 123 | ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); |
| 124 | IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk)); |
| 125 | } |
| 126 | |
| 127 | /*! |
| 128 | \brief This function disables the Host mode interrupts. |
| 129 | \param _core_if Pointer of core_if structure |
| 130 | */ |
| 131 | void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if) |
| 132 | { |
| 133 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 134 | |
| 135 | IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__); |
| 136 | |
| 137 | #if 1 |
| 138 | ifxusb_wreg( &global_regs->gintmsk, 0); |
| 139 | #else |
| 140 | /* Common interrupts */ |
| 141 | { |
| 142 | gint_data_t intr_mask ={.d32 = 0}; |
| 143 | intr_mask.b.modemismatch = 1; |
| 144 | intr_mask.b.rxstsqlvl = 1; |
| 145 | intr_mask.b.conidstschng = 1; |
| 146 | intr_mask.b.wkupintr = 1; |
| 147 | intr_mask.b.disconnect = 1; |
| 148 | intr_mask.b.usbsuspend = 1; |
| 149 | |
| 150 | /* Host interrupts */ |
| 151 | intr_mask.b.sofintr = 1; |
| 152 | intr_mask.b.portintr = 1; |
| 153 | intr_mask.b.hcintr = 1; |
| 154 | intr_mask.b.ptxfempty = 1; |
| 155 | intr_mask.b.nptxfempty = 1; |
| 156 | ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0); |
| 157 | } |
| 158 | #endif |
| 159 | } |
| 160 | |
| 161 | /*! |
| 162 | \brief This function initializes the IFXUSB controller registers for Host mode. |
| 163 | This function flushes the Tx and Rx FIFOs and it flushes any entries in the |
| 164 | request queues. |
| 165 | \param _core_if Pointer of core_if structure |
| 166 | \param _params parameters to be set |
| 167 | */ |
| 168 | void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) |
| 169 | { |
| 170 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 171 | |
| 172 | gusbcfg_data_t usbcfg ={.d32 = 0}; |
| 173 | gahbcfg_data_t ahbcfg ={.d32 = 0}; |
| 174 | gotgctl_data_t gotgctl ={.d32 = 0}; |
| 175 | |
| 176 | int i; |
| 177 | |
| 178 | IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if); |
| 179 | |
| 180 | /* Copy Params */ |
| 181 | |
| 182 | _core_if->params.dma_burst_size = _params->dma_burst_size; |
| 183 | _core_if->params.speed = _params->speed; |
| 184 | if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) ) |
| 185 | _core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1); |
| 186 | else |
| 187 | _core_if->params.max_transfer_size = _params->max_transfer_size; |
| 188 | |
| 189 | if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) ) |
| 190 | _core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); |
| 191 | else |
| 192 | _core_if->params.max_packet_count= _params->max_packet_count; |
| 193 | _core_if->params.phy_utmi_width = _params->phy_utmi_width; |
| 194 | _core_if->params.turn_around_time_hs = _params->turn_around_time_hs; |
| 195 | _core_if->params.turn_around_time_fs = _params->turn_around_time_fs; |
| 196 | _core_if->params.timeout_cal_hs = _params->timeout_cal_hs; |
| 197 | _core_if->params.timeout_cal_fs = _params->timeout_cal_fs; |
| 198 | usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); |
| 199 | // usbcfg.b.ulpi_ext_vbus_drv = 1; |
| 200 | usbcfg.b.term_sel_dl_pulse = 0; |
| 201 | usbcfg.b.ForceDevMode = 0; |
| 202 | usbcfg.b.ForceHstMode = 1; |
| 203 | ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); |
| 204 | /* Reset the Controller */ |
| 205 | do |
| 206 | { |
| 207 | while(ifxusb_core_soft_reset_h( _core_if )) |
| 208 | ifxusb_hard_reset_h(_core_if); |
| 209 | } while (ifxusb_is_device_mode(_core_if)); |
| 210 | |
| 211 | usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); |
| 212 | // usbcfg.b.ulpi_ext_vbus_drv = 1; |
| 213 | usbcfg.b.term_sel_dl_pulse = 0; |
| 214 | ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); |
| 215 | |
| 216 | /* This programming sequence needs to happen in FS mode before any other |
| 217 | * programming occurs */ |
| 218 | /* High speed PHY. */ |
| 219 | if (!_core_if->phy_init_done) |
| 220 | { |
| 221 | _core_if->phy_init_done = 1; |
| 222 | /* HS PHY parameters. These parameters are preserved |
| 223 | * during soft reset so only program the first time. Do |
| 224 | * a soft reset immediately after setting phyif. */ |
| 225 | usbcfg.b.ulpi_utmi_sel = 0; //UTMI+ |
| 226 | usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0; |
| 227 | ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); |
| 228 | /* Reset after setting the PHY parameters */ |
| 229 | ifxusb_core_soft_reset_h( _core_if ); |
| 230 | } |
| 231 | |
| 232 | usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); |
| 233 | // usbcfg.b.ulpi_fsls = 0; |
| 234 | // usbcfg.b.ulpi_clk_sus_m = 0; |
| 235 | usbcfg.b.term_sel_dl_pulse = 0; |
| 236 | usbcfg.b.ForceDevMode = 0; |
| 237 | usbcfg.b.ForceHstMode = 1; |
| 238 | ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32); |
| 239 | |
| 240 | /* Program the GAHBCFG Register.*/ |
| 241 | switch (_core_if->params.dma_burst_size) |
| 242 | { |
| 243 | case 0 : |
| 244 | ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE; |
| 245 | break; |
| 246 | case 1 : |
| 247 | ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR; |
| 248 | break; |
| 249 | case 4 : |
| 250 | ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4; |
| 251 | break; |
| 252 | case 8 : |
| 253 | ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8; |
| 254 | break; |
| 255 | case 16: |
| 256 | ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16; |
| 257 | break; |
| 258 | } |
| 259 | #if defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__) |
| 260 | _core_if->unaligned_mask=3; |
| 261 | #if defined(__UNALIGNED_BUF_BURST__) |
| 262 | switch(_core_if->params.dma_burst_size) |
| 263 | { |
| 264 | case 4 : |
| 265 | _core_if->unaligned_mask=15; |
| 266 | break; |
| 267 | case 8 : |
| 268 | _core_if->unaligned_mask=31; |
| 269 | break; |
| 270 | case 16: |
| 271 | _core_if->unaligned_mask=63; |
| 272 | break; |
| 273 | case 0 : |
| 274 | case 1 : |
| 275 | break; |
| 276 | default: |
| 277 | break; |
| 278 | } |
| 279 | #endif //defined(__UNALIGNED_BUF_BURST__) |
| 280 | #endif //defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__) |
| 281 | ahbcfg.b.dmaenable = 1; |
| 282 | ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32); |
| 283 | |
| 284 | /* Program the GUSBCFG register. */ |
| 285 | usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg ); |
| 286 | usbcfg.b.hnpcap = 0; |
| 287 | usbcfg.b.srpcap = 0; |
| 288 | ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); |
| 289 | |
| 290 | /* Restart the Phy Clock */ |
| 291 | ifxusb_wreg(_core_if->pcgcctl, 0); |
| 292 | |
| 293 | /* Initialize Host Configuration Register */ |
| 294 | { |
| 295 | hcfg_data_t hcfg; |
| 296 | hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg); |
| 297 | hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ; |
| 298 | if (_params->speed == IFXUSB_PARAM_SPEED_FULL) |
| 299 | hcfg.b.fslssupp = 1; |
| 300 | ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32); |
| 301 | } |
| 302 | |
| 303 | _core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1); |
| 304 | |
| 305 | if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels) |
| 306 | _core_if->params.host_channels = _params->host_channels; |
| 307 | |
| 308 | /* Configure data FIFO sizes */ |
| 309 | _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth; |
| 310 | _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz); |
| 311 | _core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16; |
| 312 | _core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16; |
| 313 | IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); |
| 314 | IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size); |
| 315 | IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size); |
| 316 | IFX_DEBUGPL(DBG_CIL, " PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size); |
| 317 | |
| 318 | { |
| 319 | fifosize_data_t txfifosize; |
| 320 | if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size) |
| 321 | _core_if->params.data_fifo_size = _params->data_fifo_size; |
| 322 | |
| 323 | if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size) |
| 324 | _core_if->params.rx_fifo_size = _params->rx_fifo_size; |
| 325 | if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size) |
| 326 | _core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size; |
| 327 | if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size) |
| 328 | _core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size; |
| 329 | |
| 330 | if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size) |
| 331 | _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size; |
| 332 | ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size); |
| 333 | txfifosize.b.startaddr = _core_if->params.rx_fifo_size; |
| 334 | |
| 335 | if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size) |
| 336 | _core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; |
| 337 | txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size; |
| 338 | ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); |
| 339 | txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size; |
| 340 | |
| 341 | if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size) |
| 342 | _core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; |
| 343 | txfifosize.b.depth=_core_if->params.perio_tx_fifo_size; |
| 344 | ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32); |
| 345 | txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size; |
| 346 | } |
| 347 | |
| 348 | #ifdef __DEBUG__ |
| 349 | { |
| 350 | fifosize_data_t fifosize; |
| 351 | IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); |
| 352 | |
| 353 | fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz); |
| 354 | IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); |
| 355 | fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); |
| 356 | IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); |
| 357 | fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz); |
| 358 | IFX_DEBUGPL(DBG_CIL, " PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); |
| 359 | } |
| 360 | #endif |
| 361 | |
| 362 | /* Clear Host Set HNP Enable in the OTG Control Register */ |
| 363 | gotgctl.b.hstsethnpen = 1; |
| 364 | ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0); |
| 365 | |
| 366 | /* Flush the FIFOs */ |
| 367 | ifxusb_flush_tx_fifo_h(_core_if, 0x10); /* all Tx FIFOs */ |
| 368 | ifxusb_flush_rx_fifo_h(_core_if); |
| 369 | |
| 370 | for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) |
| 371 | { |
| 372 | hcchar_data_t hcchar; |
| 373 | hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); |
| 374 | hcchar.b.chen = 0; |
| 375 | hcchar.b.chdis = 1; |
| 376 | hcchar.b.epdir = 0; |
| 377 | ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); |
| 378 | } |
| 379 | /* Halt all channels to put them into a known state. */ |
| 380 | for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) |
| 381 | { |
| 382 | hcchar_data_t hcchar; |
| 383 | int count = 0; |
| 384 | |
| 385 | hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); |
| 386 | hcchar.b.chen = 1; |
| 387 | hcchar.b.chdis = 1; |
| 388 | hcchar.b.epdir = 0; |
| 389 | ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); |
| 390 | |
| 391 | IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); |
| 392 | do{ |
| 393 | hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); |
| 394 | if (++count > 1000) |
| 395 | { |
| 396 | IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i); |
| 397 | break; |
| 398 | } |
| 399 | } while (hcchar.b.chen); |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| 404 | |
| 405 | #if defined(__UEIP__) |
| 406 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 407 | int ifxusb_vbus_status =-1; |
| 408 | #endif |
| 409 | |
| 410 | #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 411 | int ifxusb_vbus1_status =-1; |
| 412 | #endif |
| 413 | |
| 414 | #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 415 | int ifxusb_vbus2_status =-1; |
| 416 | #endif |
| 417 | |
| 418 | #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 419 | static void *g_usb_vbus_trigger = NULL; |
| 420 | #endif |
| 421 | #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 422 | static void *g_usb_vbus1_trigger = NULL; |
| 423 | #endif |
| 424 | #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 425 | static void *g_usb_vbus2_trigger = NULL; |
| 426 | #endif |
| 427 | |
| 428 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 429 | int ifxusb_vbus_gpio_inited=0; |
| 430 | #endif |
| 431 | |
| 432 | #else //defined(__UEIP__) |
| 433 | int ifxusb_vbus_status =-1; |
| 434 | int ifxusb_vbus1_status =-1; |
| 435 | int ifxusb_vbus2_status =-1; |
| 436 | int ifxusb_vbus_gpio_inited=0; |
| 437 | #endif |
| 438 | |
| 439 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| 440 | |
| 441 | /*! |
| 442 | \fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) |
| 443 | \brief This function init the VBUS control. |
| 444 | \param _core_if Pointer of core_if structure |
| 445 | \ingroup IFXUSB_CIF |
| 446 | */ |
| 447 | void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) |
| 448 | { |
| 449 | #if defined(__UEIP__) |
| 450 | #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 451 | if ( !g_usb_vbus_trigger ) |
| 452 | { |
| 453 | ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger); |
| 454 | if ( g_usb_vbus_trigger != NULL ) |
| 455 | { |
| 456 | struct ifx_led_trigger_attrib attrib = {0}; |
| 457 | attrib.delay_on = 0; |
| 458 | attrib.delay_off = 0; |
| 459 | attrib.timeout = 0; |
| 460 | attrib.def_value = 0; |
| 461 | attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; |
| 462 | IFX_DEBUGP("Reg USB power!!\n"); |
| 463 | ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib); |
| 464 | ifxusb_vbus_status =0; |
| 465 | } |
| 466 | } |
| 467 | #endif |
| 468 | #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 469 | if(_core_if->core_no==0 && !g_usb_vbus1_trigger ) |
| 470 | { |
| 471 | ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger); |
| 472 | if ( g_usb_vbus1_trigger != NULL ) |
| 473 | { |
| 474 | struct ifx_led_trigger_attrib attrib = {0}; |
| 475 | attrib.delay_on = 0; |
| 476 | attrib.delay_off = 0; |
| 477 | attrib.timeout = 0; |
| 478 | attrib.def_value = 0; |
| 479 | attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; |
| 480 | IFX_DEBUGP("Reg USB1 power!!\n"); |
| 481 | ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib); |
| 482 | ifxusb_vbus1_status =0; |
| 483 | } |
| 484 | } |
| 485 | #endif |
| 486 | #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 487 | if(_core_if->core_no==1 && !g_usb_vbus2_trigger ) |
| 488 | { |
| 489 | ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger); |
| 490 | if ( g_usb_vbus2_trigger != NULL ) |
| 491 | { |
| 492 | struct ifx_led_trigger_attrib attrib = {0}; |
| 493 | attrib.delay_on = 0; |
| 494 | attrib.delay_off = 0; |
| 495 | attrib.timeout = 0; |
| 496 | attrib.def_value = 0; |
| 497 | attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; |
| 498 | IFX_DEBUGP("Reg USB2 power!!\n"); |
| 499 | ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib); |
| 500 | ifxusb_vbus2_status =0; |
| 501 | } |
| 502 | } |
| 503 | #endif |
| 504 | |
| 505 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 506 | if(!ifxusb_vbus_gpio_inited) |
| 507 | { |
| 508 | if(!ifx_gpio_register(IFX_GPIO_MODULE_USB)) |
| 509 | { |
| 510 | IFX_DEBUGP("Register USB VBus through GPIO OK!!\n"); |
| 511 | #ifdef IFX_GPIO_USB_VBUS |
| 512 | ifxusb_vbus_status =0; |
| 513 | #endif //IFX_GPIO_USB_VBUS |
| 514 | #ifdef IFX_GPIO_USB_VBUS1 |
| 515 | ifxusb_vbus1_status=0; |
| 516 | #endif //IFX_GPIO_USB_VBUS1 |
| 517 | #ifdef IFX_GPIO_USB_VBUS2 |
| 518 | ifxusb_vbus2_status=0; |
| 519 | #endif //IFX_GPIO_USB_VBUS2 |
| 520 | } |
| 521 | else |
| 522 | IFX_PRINT("Register USB VBus Failed!!\n"); |
| 523 | ifxusb_vbus_gpio_inited=1; |
| 524 | } |
| 525 | #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 526 | #endif //defined(__UEIP__) |
| 527 | } |
| 528 | |
| 529 | /*! |
| 530 | \fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) |
| 531 | \brief This function free the VBUS control. |
| 532 | \param _core_if Pointer of core_if structure |
| 533 | \ingroup IFXUSB_CIF |
| 534 | */ |
| 535 | void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) |
| 536 | { |
| 537 | #if defined(__UEIP__) |
| 538 | #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 539 | if ( g_usb_vbus_trigger ) |
| 540 | { |
| 541 | ifx_led_trigger_deregister(g_usb_vbus_trigger); |
| 542 | g_usb_vbus_trigger = NULL; |
| 543 | ifxusb_vbus_status =-1; |
| 544 | } |
| 545 | #endif |
| 546 | #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 547 | if(_core_if->core_no==0 && g_usb_vbus1_trigger ) |
| 548 | { |
| 549 | ifx_led_trigger_deregister(g_usb_vbus1_trigger); |
| 550 | g_usb_vbus1_trigger = NULL; |
| 551 | ifxusb_vbus1_status =-1; |
| 552 | } |
| 553 | #endif |
| 554 | #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 555 | if(_core_if->core_no==1 && g_usb_vbus2_trigger ) |
| 556 | { |
| 557 | ifx_led_trigger_deregister(g_usb_vbus2_trigger); |
| 558 | g_usb_vbus2_trigger = NULL; |
| 559 | ifxusb_vbus2_status =-1; |
| 560 | } |
| 561 | #endif |
| 562 | |
| 563 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 564 | if(ifxusb_vbus_gpio_inited) |
| 565 | { |
| 566 | ifx_gpio_deregister(IFX_GPIO_MODULE_USB); |
| 567 | #ifdef IFX_GPIO_USB_VBUS |
| 568 | ifxusb_vbus_status =-1; |
| 569 | #endif //IFX_GPIO_USB_VBUS |
| 570 | #ifdef IFX_GPIO_USB_VBUS1 |
| 571 | ifxusb_vbus1_status=-1; |
| 572 | #endif //IFX_GPIO_USB_VBUS1 |
| 573 | #ifdef IFX_GPIO_USB_VBUS2 |
| 574 | ifxusb_vbus2_status=-1; |
| 575 | #endif //IFX_GPIO_USB_VBUS2 |
| 576 | ifxusb_vbus_gpio_inited=0; |
| 577 | } |
| 578 | #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 579 | #endif //defined(__UEIP__) |
| 580 | } |
| 581 | |
| 582 | |
| 583 | #if defined(__DO_OC_INT__) |
| 584 | |
| 585 | #define OC_Timer_Stable 3 |
| 586 | #define OC_Timer_Sleep 200 |
| 587 | #define OC_Timer_Max 3 |
| 588 | |
| 589 | |
| 590 | #if defined(__IS_AR10__) |
| 591 | #if defined(__IS_DUAL__) |
| 592 | unsigned int oc1_int_installed=0; |
| 593 | unsigned int oc2_int_installed=0; |
| 594 | unsigned int oc1_int_count=0; |
| 595 | unsigned int oc2_int_count=0; |
| 596 | extern ifxhcd_hcd_t *oc1_int_id; |
| 597 | extern ifxhcd_hcd_t *oc2_int_id; |
| 598 | |
| 599 | /*! |
| 600 | \brief Handles host mode Over Current Interrupt |
| 601 | */ |
| 602 | struct timer_list oc1_retry_timer; |
| 603 | struct timer_list oc2_retry_timer; |
| 604 | |
| 605 | void oc_retry_timer_func(unsigned long arg) |
| 606 | { |
| 607 | if(arg==1) |
| 608 | { |
| 609 | if(oc1_int_installed==0) //not installed |
| 610 | { |
| 611 | } |
| 612 | else if(oc1_int_installed==1) //disabled |
| 613 | { |
| 614 | } |
| 615 | else if(oc1_int_installed==2) //stablizing |
| 616 | { |
| 617 | oc1_int_installed=4; |
| 618 | oc1_int_count=0; |
| 619 | } |
| 620 | else if(oc1_int_installed==3) // sleeping |
| 621 | { |
| 622 | mod_timer(&oc1_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 623 | oc1_int_installed=2; |
| 624 | enable_irq(IFXUSB1_OC_IRQ); |
| 625 | } |
| 626 | else if(oc1_int_installed==4) // |
| 627 | { |
| 628 | oc1_int_count=0; |
| 629 | } |
| 630 | else if(oc1_int_installed==5) // Stable sleeping |
| 631 | { |
| 632 | mod_timer(&oc1_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 633 | oc1_int_installed=4; |
| 634 | enable_irq(IFXUSB1_OC_IRQ); |
| 635 | } |
| 636 | else |
| 637 | { |
| 638 | } |
| 639 | } |
| 640 | else |
| 641 | { |
| 642 | if(oc2_int_installed==0) //not installed |
| 643 | { |
| 644 | } |
| 645 | else if(oc2_int_installed==1) //disabled |
| 646 | { |
| 647 | } |
| 648 | else if(oc2_int_installed==2) //stablizing |
| 649 | { |
| 650 | oc2_int_installed=4; |
| 651 | oc2_int_count=0; |
| 652 | } |
| 653 | else if(oc2_int_installed==3) // sleeping |
| 654 | { |
| 655 | mod_timer(&oc2_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 656 | oc2_int_installed=2; |
| 657 | enable_irq(IFXUSB2_OC_IRQ); |
| 658 | } |
| 659 | else if(oc2_int_installed==4) // |
| 660 | { |
| 661 | oc2_int_count=0; |
| 662 | } |
| 663 | else if(oc2_int_installed==5) // Stable sleeping |
| 664 | { |
| 665 | mod_timer(&oc2_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 666 | oc2_int_installed=4; |
| 667 | enable_irq(IFXUSB2_OC_IRQ); |
| 668 | } |
| 669 | else |
| 670 | { |
| 671 | } |
| 672 | } |
| 673 | } |
| 674 | |
| 675 | irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev) |
| 676 | { |
| 677 | //ifxhcd_hcd_t *ifxhcd= _dev; |
| 678 | int32_t retval=1; |
| 679 | if(_irq==IFXUSB1_OC_IRQ) |
| 680 | { |
| 681 | if(oc1_int_installed==0) //not installed |
| 682 | { |
| 683 | } |
| 684 | else if(oc1_int_installed==1) //disabled |
| 685 | { |
| 686 | } |
| 687 | else if(oc1_int_installed==2) //stablizing |
| 688 | { |
| 689 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 690 | mod_timer(&oc1_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 691 | oc1_int_installed=3; |
| 692 | } |
| 693 | else if(oc1_int_installed==3) // sleeping |
| 694 | { |
| 695 | } |
| 696 | else if(oc1_int_installed==4) // |
| 697 | { |
| 698 | oc1_int_count++; |
| 699 | if(oc1_int_count>=OC_Timer_Max) |
| 700 | { |
| 701 | IFX_DEBUGP("OC INTERRUPT port #1\n"); |
| 702 | oc1_int_id->flags.b.port_over_current_change = 1; |
| 703 | ifxusb_vbus_off(&oc1_int_id->core_if); |
| 704 | IFX_DEBUGP("Turning off port #1\n"); |
| 705 | } |
| 706 | else |
| 707 | { |
| 708 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 709 | mod_timer(&oc1_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 710 | oc1_int_installed=5; |
| 711 | } |
| 712 | } |
| 713 | else if(oc1_int_installed==5) // Stable sleeping |
| 714 | { |
| 715 | } |
| 716 | } |
| 717 | else |
| 718 | { |
| 719 | if(oc2_int_installed==0) //not installed |
| 720 | { |
| 721 | } |
| 722 | else if(oc2_int_installed==1) //disabled |
| 723 | { |
| 724 | } |
| 725 | else if(oc2_int_installed==2) //stablizing |
| 726 | { |
| 727 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 728 | mod_timer(&oc2_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 729 | oc2_int_installed=3; |
| 730 | } |
| 731 | else if(oc2_int_installed==3) // sleeping |
| 732 | { |
| 733 | } |
| 734 | else if(oc2_int_installed==4) // |
| 735 | { |
| 736 | oc2_int_count++; |
| 737 | if(oc2_int_count>=OC_Timer_Max) |
| 738 | { |
| 739 | IFX_DEBUGP("OC INTERRUPT port #2\n"); |
| 740 | oc2_int_id->flags.b.port_over_current_change = 1; |
| 741 | ifxusb_vbus_off(&oc2_int_id->core_if); |
| 742 | IFX_DEBUGP("Turning off port #2\n"); |
| 743 | } |
| 744 | else |
| 745 | { |
| 746 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 747 | mod_timer(&oc2_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 748 | oc2_int_installed=5; |
| 749 | } |
| 750 | } |
| 751 | else if(oc2_int_installed==5) // Stable sleeping |
| 752 | { |
| 753 | } |
| 754 | } |
| 755 | return IRQ_RETVAL(retval); |
| 756 | } |
| 757 | |
| 758 | void ifxusb_oc_int_on(int port) |
| 759 | { |
| 760 | if(port==1) |
| 761 | IFX_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for port #1 irq%d\n", IFXUSB1_OC_IRQ); |
| 762 | else |
| 763 | IFX_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for port #2 irq%d\n", IFXUSB2_OC_IRQ); |
| 764 | if((port==1&&oc1_int_id) || (port==2&&oc2_int_id) |
| 765 | { |
| 766 | if((port==1&&oc1_int_installed==0)||(port==2&&oc2_int_installed==0)) |
| 767 | { |
| 768 | if(port==1) |
| 769 | { |
| 770 | oc1_int_installed=2; |
| 771 | init_timer(&oc1_retry_timer); |
| 772 | oc1_retry_timer.function = oc_retry_timer_func; |
| 773 | oc1_retry_timer.data=1; |
| 774 | if(request_irq((unsigned int)IFXUSB1_OC_IRQ, &ifxhcd_oc_irq, |
| 775 | IRQF_TRIGGER_NONE |
| 776 | // | IRQF_TRIGGER_RISING |
| 777 | // | IRQF_TRIGGER_FALLING |
| 778 | // | IRQF_TRIGGER_HIGH |
| 779 | // | IRQF_TRIGGER_LOW |
| 780 | // | IRQF_TRIGGER_PROBE |
| 781 | | IRQF_DISABLED |
| 782 | // | IRQF_SAMPLE_RANDOM |
| 783 | // | IRQF_SHARED |
| 784 | | IRQF_PROBE_SHARED |
| 785 | // | IRQF_TIMER |
| 786 | // | IRQF_PERCPU |
| 787 | // | IRQF_NOBALANCING |
| 788 | // | IRQF_IRQPOLL |
| 789 | // | IRQF_ONESHOT |
| 790 | , |
| 791 | "ifxusb1_oc", (void *)oc1_int_id)) |
| 792 | oc1_int_installed=0; |
| 793 | else |
| 794 | mod_timer(&oc1_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 795 | } |
| 796 | else |
| 797 | { |
| 798 | oc2_int_installed=2; |
| 799 | init_timer(&oc2_retry_timer); |
| 800 | oc2_retry_timer.function = oc_retry_timer_func; |
| 801 | oc2_retry_timer.data=2; |
| 802 | if(request_irq((unsigned int)IFXUSB2_OC_IRQ, &ifxhcd_oc_irq, |
| 803 | IRQF_TRIGGER_NONE |
| 804 | // | IRQF_TRIGGER_RISING |
| 805 | // | IRQF_TRIGGER_FALLING |
| 806 | // | IRQF_TRIGGER_HIGH |
| 807 | // | IRQF_TRIGGER_LOW |
| 808 | // | IRQF_TRIGGER_PROBE |
| 809 | | IRQF_DISABLED |
| 810 | // | IRQF_SAMPLE_RANDOM |
| 811 | // | IRQF_SHARED |
| 812 | | IRQF_PROBE_SHARED |
| 813 | // | IRQF_TIMER |
| 814 | // | IRQF_PERCPU |
| 815 | // | IRQF_NOBALANCING |
| 816 | // | IRQF_IRQPOLL |
| 817 | // | IRQF_ONESHOT |
| 818 | , |
| 819 | "ifxusb2_oc", (void *)oc2_int_id)) |
| 820 | oc2_int_installed=0; |
| 821 | else |
| 822 | mod_timer(&oc2_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 823 | } |
| 824 | /* Poll the event ring */ |
| 825 | } |
| 826 | else if(port==1 && oc1_int_installed!=2 && oc1_int_installed!=4 ) |
| 827 | { |
| 828 | oc1_int_installed=2; |
| 829 | enable_irq(IFXUSB1_OC_IRQ); |
| 830 | mod_timer(&oc1_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 831 | } |
| 832 | else if(port==2 && oc2_int_installed!=2 && oc2_int_installed!=4 ) |
| 833 | { |
| 834 | oc2_int_installed=2; |
| 835 | enable_irq(IFXUSB2_OC_IRQ); |
| 836 | mod_timer(&oc2_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 837 | } |
| 838 | } |
| 839 | } |
| 840 | |
| 841 | void ifxusb_oc_int_off(int port) |
| 842 | { |
| 843 | if(port==1) |
| 844 | { |
| 845 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 846 | if(oc1_int_installed) |
| 847 | oc1_int_installed=1; |
| 848 | } |
| 849 | else |
| 850 | { |
| 851 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 852 | if(oc2_int_installed) |
| 853 | oc2_int_installed=1; |
| 854 | } |
| 855 | } |
| 856 | |
| 857 | |
| 858 | void ifxusb_oc_int_free(int port) |
| 859 | { |
| 860 | if(port==1) |
| 861 | { |
| 862 | del_timer(&oc1_retry_timer); |
| 863 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 864 | free_irq(IFXUSB1_OC_IRQ, (void *)oc1_int_id); |
| 865 | oc1_int_installed=0; |
| 866 | } |
| 867 | else |
| 868 | { |
| 869 | del_timer(&oc1_retry_timer); |
| 870 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 871 | free_irq(IFXUSB2_OC_IRQ, (void *)oc2_int_id); |
| 872 | oc2_int_installed=0; |
| 873 | } |
| 874 | } |
| 875 | |
| 876 | #elif defined(__IS_FIRST__) || defined(__IS_SECOND__) |
| 877 | unsigned int oc_int_installed=0; |
| 878 | unsigned int oc_int_count=0; |
| 879 | extern ifxhcd_hcd_t *oc_int_id; |
| 880 | |
| 881 | /*! |
| 882 | \brief Handles host mode Over Current Interrupt |
| 883 | */ |
| 884 | struct timer_list oc_retry_timer; |
| 885 | |
| 886 | void oc_retry_timer_func(void) |
| 887 | { |
| 888 | if(oc_int_installed==0) //not installed |
| 889 | { |
| 890 | } |
| 891 | else if(oc_int_installed==1) //disabled |
| 892 | { |
| 893 | } |
| 894 | else if(oc_int_installed==2) //stablizing |
| 895 | { |
| 896 | oc_int_installed=4; |
| 897 | oc_int_count=0; |
| 898 | } |
| 899 | else if(oc_int_installed==3) // sleeping |
| 900 | { |
| 901 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 902 | oc_int_installed=2; |
| 903 | #if defined(__IS_FIRST__) |
| 904 | enable_irq(IFXUSB1_OC_IRQ); |
| 905 | #else |
| 906 | enable_irq(IFXUSB2_OC_IRQ); |
| 907 | #endif |
| 908 | } |
| 909 | else if(oc_int_installed==4) // |
| 910 | { |
| 911 | oc_int_count=0; |
| 912 | } |
| 913 | else if(oc_int_installed==5) // Stable sleeping |
| 914 | { |
| 915 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 916 | oc_int_installed=4; |
| 917 | #if defined(__IS_FIRST__) |
| 918 | enable_irq(IFXUSB1_OC_IRQ); |
| 919 | #else |
| 920 | enable_irq(IFXUSB2_OC_IRQ); |
| 921 | #endif |
| 922 | } |
| 923 | else |
| 924 | { |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev) |
| 929 | { |
| 930 | //ifxhcd_hcd_t *ifxhcd= _dev; |
| 931 | int32_t retval=1; |
| 932 | if(oc_int_installed==0) //not installed |
| 933 | { |
| 934 | } |
| 935 | else if(oc_int_installed==1) //disabled |
| 936 | { |
| 937 | } |
| 938 | else if(oc_int_installed==2) //stablizing |
| 939 | { |
| 940 | #if defined(__IS_FIRST__) |
| 941 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 942 | #else |
| 943 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 944 | #endif |
| 945 | mod_timer(&oc_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 946 | oc_int_installed=3; |
| 947 | } |
| 948 | else if(oc_int_installed==3) // sleeping |
| 949 | { |
| 950 | } |
| 951 | else if(oc_int_installed==4) // |
| 952 | { |
| 953 | oc_int_count++; |
| 954 | if(oc_int_count>=OC_Timer_Max) |
| 955 | { |
| 956 | #if defined(__IS_FIRST__) |
| 957 | IFX_DEBUGP("OC INTERRUPT port #1\n"); |
| 958 | #else |
| 959 | IFX_DEBUGP("OC INTERRUPT port #2\n"); |
| 960 | #endif |
| 961 | oc_int_id->flags.b.port_over_current_change = 1; |
| 962 | ifxusb_vbus_off(&oc_int_id->core_if); |
| 963 | #if defined(__IS_FIRST__) |
| 964 | IFX_DEBUGP("Turning off port #1\n"); |
| 965 | #else |
| 966 | IFX_DEBUGP("Turning off port #2\n"); |
| 967 | #endif |
| 968 | } |
| 969 | else |
| 970 | { |
| 971 | #if defined(__IS_FIRST__) |
| 972 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 973 | #else |
| 974 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 975 | #endif |
| 976 | mod_timer(&oc_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 977 | oc_int_installed=5; |
| 978 | } |
| 979 | } |
| 980 | else if(oc_int_installed==5) // Stable sleeping |
| 981 | { |
| 982 | } |
| 983 | return IRQ_RETVAL(retval); |
| 984 | } |
| 985 | |
| 986 | void ifxusb_oc_int_on(void) |
| 987 | { |
| 988 | #if defined(__IS_FIRST__) |
| 989 | IFX_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for port #1 irq%d\n", IFXUSB1_OC_IRQ); |
| 990 | #else |
| 991 | IFX_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for port #2 irq%d\n", IFXUSB2_OC_IRQ); |
| 992 | #endif |
| 993 | if(oc_int_id) |
| 994 | { |
| 995 | if(oc_int_installed==0) |
| 996 | { |
| 997 | oc_int_installed=2; |
| 998 | init_timer(&oc_retry_timer); |
| 999 | oc_retry_timer.function = oc_retry_timer_func; |
| 1000 | oc_retry_timer.data=1; |
| 1001 | #if defined(__IS_FIRST__) |
| 1002 | if(request_irq((unsigned int)IFXUSB1_OC_IRQ, &ifxhcd_oc_irq, |
| 1003 | #else |
| 1004 | if(request_irq((unsigned int)IFXUSB2_OC_IRQ, &ifxhcd_oc_irq, |
| 1005 | #endif |
| 1006 | IRQF_TRIGGER_NONE |
| 1007 | // | IRQF_TRIGGER_RISING |
| 1008 | // | IRQF_TRIGGER_FALLING |
| 1009 | // | IRQF_TRIGGER_HIGH |
| 1010 | // | IRQF_TRIGGER_LOW |
| 1011 | // | IRQF_TRIGGER_PROBE |
| 1012 | | IRQF_DISABLED |
| 1013 | // | IRQF_SAMPLE_RANDOM |
| 1014 | // | IRQF_SHARED |
| 1015 | | IRQF_PROBE_SHARED |
| 1016 | // | IRQF_TIMER |
| 1017 | // | IRQF_PERCPU |
| 1018 | // | IRQF_NOBALANCING |
| 1019 | // | IRQF_IRQPOLL |
| 1020 | // | IRQF_ONESHOT |
| 1021 | , |
| 1022 | "ifxusb_oc", (void *)oc_int_id)) |
| 1023 | oc_int_installed=0; |
| 1024 | else |
| 1025 | mod_timer(&oc1_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1026 | } |
| 1027 | else if(oc_int_installed!=2 && oc_int_installed!=4 ) |
| 1028 | { |
| 1029 | oc_int_installed=2; |
| 1030 | #if defined(__IS_FIRST__) |
| 1031 | enable_irq(IFXUSB1_OC_IRQ); |
| 1032 | #else |
| 1033 | enable_irq(IFXUSB2_OC_IRQ); |
| 1034 | #endif |
| 1035 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1036 | } |
| 1037 | } |
| 1038 | } |
| 1039 | |
| 1040 | void ifxusb_oc_int_off(int port) |
| 1041 | { |
| 1042 | #if defined(__IS_FIRST__) |
| 1043 | disable_irq_nosync(IFXUSB1_OC_IRQ); |
| 1044 | #else |
| 1045 | disable_irq_nosync(IFXUSB2_OC_IRQ); |
| 1046 | #endif |
| 1047 | } |
| 1048 | void ifxusb_oc_int_free(int port) |
| 1049 | { |
| 1050 | #if defined(__IS_FIRST__) |
| 1051 | free_irq(IFXUSB1_OC_IRQ, (void *)oc_int_id); |
| 1052 | #else |
| 1053 | free_irq(IFXUSB2_OC_IRQ, (void *)oc_int_id); |
| 1054 | #endif |
| 1055 | } |
| 1056 | #endif |
| 1057 | #else //!defined(__IS_AR10__) |
| 1058 | unsigned int oc_int_installed=0; |
| 1059 | unsigned int oc_int_count=0; |
| 1060 | extern ifxhcd_hcd_t *oc_int_id; |
| 1061 | #ifdef __IS_DUAL__ |
| 1062 | extern ifxhcd_hcd_t *oc_int_id_1; |
| 1063 | extern ifxhcd_hcd_t *oc_int_id_2; |
| 1064 | #endif |
| 1065 | |
| 1066 | /*! |
| 1067 | \brief Handles host mode Over Current Interrupt |
| 1068 | */ |
| 1069 | struct timer_list oc_retry_timer; |
| 1070 | |
| 1071 | void oc_retry_timer_func(unsigned long arg) |
| 1072 | { |
| 1073 | if(oc_int_installed==0) //not installed |
| 1074 | { |
| 1075 | } |
| 1076 | else if(oc_int_installed==1) //disabled |
| 1077 | { |
| 1078 | } |
| 1079 | else if(oc_int_installed==2) //stablizing |
| 1080 | { |
| 1081 | oc_int_installed=4; |
| 1082 | oc_int_count=0; |
| 1083 | } |
| 1084 | else if(oc_int_installed==3) // sleeping |
| 1085 | { |
| 1086 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1087 | oc_int_installed=2; |
| 1088 | enable_irq(IFXUSB_OC_IRQ); |
| 1089 | } |
| 1090 | else if(oc_int_installed==4) // |
| 1091 | { |
| 1092 | oc_int_count=0; |
| 1093 | } |
| 1094 | else if(oc_int_installed==5) // Stable sleeping |
| 1095 | { |
| 1096 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1097 | oc_int_installed=4; |
| 1098 | enable_irq(IFXUSB_OC_IRQ); |
| 1099 | } |
| 1100 | else |
| 1101 | { |
| 1102 | } |
| 1103 | } |
| 1104 | |
| 1105 | irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev) |
| 1106 | { |
| 1107 | //ifxhcd_hcd_t *ifxhcd= _dev; |
| 1108 | int32_t retval=1; |
| 1109 | |
| 1110 | if(oc_int_installed==0) //not installed |
| 1111 | { |
| 1112 | } |
| 1113 | else if(oc_int_installed==1) //disabled |
| 1114 | { |
| 1115 | } |
| 1116 | else if(oc_int_installed==2) //stablizing |
| 1117 | { |
| 1118 | disable_irq_nosync(IFXUSB_OC_IRQ); |
| 1119 | mod_timer(&oc_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 1120 | oc_int_installed=3; |
| 1121 | } |
| 1122 | else if(oc_int_installed==3) // sleeping |
| 1123 | { |
| 1124 | } |
| 1125 | else if(oc_int_installed==4) // |
| 1126 | { |
| 1127 | oc_int_count++; |
| 1128 | if(oc_int_count>=OC_Timer_Max) |
| 1129 | { |
| 1130 | IFX_DEBUGP("OC INTERRUPT port #%d\n",oc_int_id->core_if.core_no); |
| 1131 | #ifdef __IS_DUAL__ |
| 1132 | oc_int_id_1->flags.b.port_over_current_change = 1; |
| 1133 | oc_int_id_2->flags.b.port_over_current_change = 1; |
| 1134 | ifxusb_vbus_off(&oc_int_id_1->core_if); |
| 1135 | IFX_DEBUGP("Turning off port #%d\n",oc_int_id_1->core_if.core_no); |
| 1136 | ifxusb_vbus_off(&oc_int_id_2->core_if); |
| 1137 | IFX_DEBUGP("Turning off port #%d\n",oc_int_id_2->core_if.core_no); |
| 1138 | #else |
| 1139 | oc_int_id->flags.b.port_over_current_change = 1; |
| 1140 | ifxusb_vbus_off(&oc_int_id->core_if); |
| 1141 | IFX_DEBUGP("Turning off port #%d\n",oc_int_id->core_if.core_no); |
| 1142 | #endif |
| 1143 | } |
| 1144 | else |
| 1145 | { |
| 1146 | disable_irq_nosync(IFXUSB_OC_IRQ); |
| 1147 | mod_timer(&oc_retry_timer,jiffies + HZ/OC_Timer_Sleep); |
| 1148 | oc_int_installed=5; |
| 1149 | } |
| 1150 | } |
| 1151 | else if(oc_int_installed==5) // Stable sleeping |
| 1152 | { |
| 1153 | } |
| 1154 | |
| 1155 | return IRQ_RETVAL(retval); |
| 1156 | } |
| 1157 | |
| 1158 | void ifxusb_oc_int_on(void) |
| 1159 | { |
| 1160 | IFX_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ); |
| 1161 | if(oc_int_id) |
| 1162 | { |
| 1163 | if(oc_int_installed==0) |
| 1164 | { |
| 1165 | oc_int_installed=2; |
| 1166 | init_timer(&oc_retry_timer); |
| 1167 | oc_retry_timer.function = oc_retry_timer_func; |
| 1168 | /* Poll the event ring */ |
| 1169 | |
| 1170 | if(request_irq((unsigned int)IFXUSB_OC_IRQ, &ifxhcd_oc_irq, |
| 1171 | IRQF_TRIGGER_NONE |
| 1172 | // | IRQF_TRIGGER_RISING |
| 1173 | // | IRQF_TRIGGER_FALLING |
| 1174 | // | IRQF_TRIGGER_HIGH |
| 1175 | // | IRQF_TRIGGER_LOW |
| 1176 | // | IRQF_TRIGGER_PROBE |
| 1177 | | IRQF_DISABLED |
| 1178 | // | IRQF_SAMPLE_RANDOM |
| 1179 | // | IRQF_SHARED |
| 1180 | // | IRQF_PROBE_SHARED |
| 1181 | // | IRQF_TIMER |
| 1182 | // | IRQF_PERCPU |
| 1183 | // | IRQF_NOBALANCING |
| 1184 | // | IRQF_IRQPOLL |
| 1185 | // | IRQF_ONESHOT |
| 1186 | , |
| 1187 | "ifxusb_oc", (void *)oc_int_id)) |
| 1188 | oc_int_installed=0; |
| 1189 | else |
| 1190 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1191 | } |
| 1192 | else if(oc_int_installed!=2 && oc_int_installed!=4 ) |
| 1193 | { |
| 1194 | oc_int_installed=2; |
| 1195 | enable_irq(IFXUSB_OC_IRQ); |
| 1196 | mod_timer(&oc_retry_timer,jiffies + HZ*OC_Timer_Stable); |
| 1197 | } |
| 1198 | } |
| 1199 | } |
| 1200 | |
| 1201 | void ifxusb_oc_int_off(void) |
| 1202 | { |
| 1203 | disable_irq_nosync(IFXUSB_OC_IRQ); |
| 1204 | if(oc_int_installed) |
| 1205 | oc_int_installed=1; |
| 1206 | } |
| 1207 | |
| 1208 | void ifxusb_oc_int_free(void) |
| 1209 | { |
| 1210 | del_timer(&oc_retry_timer); |
| 1211 | disable_irq_nosync(IFXUSB_OC_IRQ); |
| 1212 | if(oc_int_installed) |
| 1213 | free_irq(IFXUSB_OC_IRQ, (void *)oc_int_id); |
| 1214 | oc_int_installed=0; |
| 1215 | } |
| 1216 | #endif |
| 1217 | #endif |
| 1218 | |
| 1219 | |
| 1220 | /*! |
| 1221 | \fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) |
| 1222 | \brief Turn on the USB 5V VBus Power |
| 1223 | \param _core_if Pointer of core_if structure |
| 1224 | \ingroup IFXUSB_CIF |
| 1225 | */ |
| 1226 | void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) |
| 1227 | { |
| 1228 | IFX_DEBUGP("SENDING VBus POWER UP\n"); |
| 1229 | #if defined(__UEIP__) |
| 1230 | #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 1231 | if ( g_usb_vbus_trigger && ifxusb_vbus_status==0) |
| 1232 | { |
| 1233 | ifx_led_trigger_activate(g_usb_vbus_trigger); |
| 1234 | IFX_DEBUGP("Enable USB power!!\n"); |
| 1235 | ifxusb_vbus_status=1; |
| 1236 | } |
| 1237 | #endif |
| 1238 | #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 1239 | if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0) |
| 1240 | { |
| 1241 | ifx_led_trigger_activate(g_usb_vbus1_trigger); |
| 1242 | IFX_DEBUGP("Enable USB1 power!!\n"); |
| 1243 | ifxusb_vbus1_status=1; |
| 1244 | } |
| 1245 | #endif |
| 1246 | #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 1247 | if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0) |
| 1248 | { |
| 1249 | ifx_led_trigger_activate(g_usb_vbus2_trigger); |
| 1250 | IFX_DEBUGP("Enable USB2 power!!\n"); |
| 1251 | ifxusb_vbus2_status=1; |
| 1252 | } |
| 1253 | #endif |
| 1254 | |
| 1255 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 1256 | if(ifxusb_vbus_gpio_inited) |
| 1257 | { |
| 1258 | #if defined(IFX_GPIO_USB_VBUS) |
| 1259 | if(ifxusb_vbus_status==0) |
| 1260 | { |
| 1261 | ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); |
| 1262 | ifxusb_vbus_status=1; |
| 1263 | } |
| 1264 | #endif |
| 1265 | #if defined(IFX_GPIO_USB_VBUS1) |
| 1266 | if(_core_if->core_no==0 && ifxusb_vbus1_status==0) |
| 1267 | { |
| 1268 | ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); |
| 1269 | ifxusb_vbus1_status=1; |
| 1270 | } |
| 1271 | #endif |
| 1272 | #if defined(IFX_GPIO_USB_VBUS2) |
| 1273 | if(_core_if->core_no==1 && ifxusb_vbus2_status==0) |
| 1274 | { |
| 1275 | ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); |
| 1276 | ifxusb_vbus2_status=1; |
| 1277 | } |
| 1278 | #endif |
| 1279 | } |
| 1280 | #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 1281 | #else |
| 1282 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1283 | ifxusb_vbus_status=1; |
| 1284 | //usb_set_vbus_on(); |
| 1285 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1286 | #if defined(__IS_AMAZON_SE__) |
| 1287 | set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); |
| 1288 | ifxusb_vbus_status=1; |
| 1289 | #endif //defined(__IS_AMAZON_SE__) |
| 1290 | #if defined(__IS_AR9__) |
| 1291 | if(_core_if->core_no==0) |
| 1292 | { |
| 1293 | if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) |
| 1294 | { |
| 1295 | IFX_PRINT("Can't enable USB1 5.5V power!!\n"); |
| 1296 | return; |
| 1297 | } |
| 1298 | bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); |
| 1299 | bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); |
| 1300 | bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); |
| 1301 | bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); |
| 1302 | bsp_port_set_puden(1, 13, PORT_MODULE_USB); |
| 1303 | bsp_port_set_output(1, 13, PORT_MODULE_USB); |
| 1304 | IFX_DEBUGP("Enable USB1 power!!\n"); |
| 1305 | ifxusb_vbus1_status=1; |
| 1306 | } |
| 1307 | else |
| 1308 | { |
| 1309 | if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) |
| 1310 | { |
| 1311 | IFX_PRINT("Can't enable USB2 5.5V power!!\n"); |
| 1312 | return; |
| 1313 | } |
| 1314 | bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); |
| 1315 | bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); |
| 1316 | bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); |
| 1317 | bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); |
| 1318 | bsp_port_set_puden(3, 4, PORT_MODULE_USB); |
| 1319 | bsp_port_set_output(3, 4, PORT_MODULE_USB); |
| 1320 | IFX_DEBUGP("Enable USB2 power!!\n"); |
| 1321 | ifxusb_vbus2_status=1; |
| 1322 | } |
| 1323 | #endif //defined(__IS_AR9__) |
| 1324 | #if defined(__IS_VR9__) |
| 1325 | if(_core_if->core_no==0) |
| 1326 | { |
| 1327 | ifxusb_vbus1_status=1; |
| 1328 | } |
| 1329 | else |
| 1330 | { |
| 1331 | ifxusb_vbus2_status=1; |
| 1332 | } |
| 1333 | #endif //defined(__IS_VR9__) |
| 1334 | #endif //defined(__UEIP__) |
| 1335 | |
| 1336 | #if defined(__DO_OC_INT__) |
| 1337 | #if defined(__IS_AR10__) && defined(__IS_DUAL__) |
| 1338 | if(_core_if->core_no==0) |
| 1339 | ifxusb_oc_int_on(1); |
| 1340 | else |
| 1341 | ifxusb_oc_int_on(2); |
| 1342 | #else |
| 1343 | ifxusb_oc_int_on(); |
| 1344 | #endif |
| 1345 | #endif |
| 1346 | |
| 1347 | } |
| 1348 | |
| 1349 | |
| 1350 | /*! |
| 1351 | \fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) |
| 1352 | \brief Turn off the USB 5V VBus Power |
| 1353 | \param _core_if Pointer of core_if structure |
| 1354 | \ingroup IFXUSB_CIF |
| 1355 | */ |
| 1356 | void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) |
| 1357 | { |
| 1358 | IFX_DEBUGP("SENDING VBus POWER OFF\n"); |
| 1359 | |
| 1360 | #if defined(__UEIP__) |
| 1361 | #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 1362 | if ( g_usb_vbus_trigger && ifxusb_vbus_status==1) |
| 1363 | { |
| 1364 | ifx_led_trigger_deactivate(g_usb_vbus_trigger); |
| 1365 | IFX_DEBUGP("Disable USB power!!\n"); |
| 1366 | ifxusb_vbus_status=0; |
| 1367 | } |
| 1368 | #endif |
| 1369 | #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 1370 | if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1) |
| 1371 | { |
| 1372 | ifx_led_trigger_deactivate(g_usb_vbus1_trigger); |
| 1373 | IFX_DEBUGP("Disable USB1 power!!\n"); |
| 1374 | ifxusb_vbus1_status=0; |
| 1375 | } |
| 1376 | #endif |
| 1377 | #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 1378 | if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1) |
| 1379 | { |
| 1380 | ifx_led_trigger_deactivate(g_usb_vbus2_trigger); |
| 1381 | IFX_DEBUGP("Disable USB2 power!!\n"); |
| 1382 | ifxusb_vbus2_status=0; |
| 1383 | } |
| 1384 | #endif |
| 1385 | |
| 1386 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 1387 | if(ifxusb_vbus_gpio_inited) |
| 1388 | { |
| 1389 | #if defined(IFX_GPIO_USB_VBUS) |
| 1390 | if(ifxusb_vbus_status==1) |
| 1391 | { |
| 1392 | ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); |
| 1393 | ifxusb_vbus_status=0; |
| 1394 | } |
| 1395 | #endif |
| 1396 | #if defined(IFX_GPIO_USB_VBUS1) |
| 1397 | if(_core_if->core_no==0 && ifxusb_vbus1_status==1) |
| 1398 | { |
| 1399 | ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); |
| 1400 | ifxusb_vbus1_status=0; |
| 1401 | } |
| 1402 | #endif |
| 1403 | #if defined(IFX_GPIO_USB_VBUS2) |
| 1404 | if(_core_if->core_no==1 && ifxusb_vbus2_status==1) |
| 1405 | { |
| 1406 | ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); |
| 1407 | ifxusb_vbus2_status=0; |
| 1408 | } |
| 1409 | #endif |
| 1410 | } |
| 1411 | #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) |
| 1412 | #else |
| 1413 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1414 | ifxusb_vbus_status=0; |
| 1415 | //usb_set_vbus_on(); |
| 1416 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1417 | #if defined(__IS_AMAZON_SE__) |
| 1418 | clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); |
| 1419 | ifxusb_vbus_status=0; |
| 1420 | #endif //defined(__IS_AMAZON_SE__) |
| 1421 | #if defined(__IS_AR9__) |
| 1422 | if(_core_if->core_no==0) |
| 1423 | { |
| 1424 | if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) { |
| 1425 | IFX_PRINT("Can't Disable USB1 5.5V power!!\n"); |
| 1426 | return; |
| 1427 | } |
| 1428 | bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); |
| 1429 | bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); |
| 1430 | bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); |
| 1431 | bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); |
| 1432 | bsp_port_set_puden(1, 13, PORT_MODULE_USB); |
| 1433 | bsp_port_clear_output(1, 13, PORT_MODULE_USB); |
| 1434 | IFX_DEBUGP("Disable USB1 power!!\n"); |
| 1435 | ifxusb_vbus1_status=0; |
| 1436 | } |
| 1437 | else |
| 1438 | { |
| 1439 | if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) { |
| 1440 | IFX_PRINT("Can't Disable USB2 5.5V power!!\n"); |
| 1441 | return; |
| 1442 | } |
| 1443 | bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); |
| 1444 | bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); |
| 1445 | bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); |
| 1446 | bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); |
| 1447 | bsp_port_set_puden(3, 4, PORT_MODULE_USB); |
| 1448 | bsp_port_clear_output(3, 4, PORT_MODULE_USB); |
| 1449 | IFX_DEBUGP("Disable USB2 power!!\n"); |
| 1450 | |
| 1451 | ifxusb_vbus2_status=0; |
| 1452 | } |
| 1453 | #endif //defined(__IS_AR9__) |
| 1454 | #if defined(__IS_VR9__) |
| 1455 | if(_core_if->core_no==0) |
| 1456 | { |
| 1457 | ifxusb_vbus1_status=0; |
| 1458 | } |
| 1459 | else |
| 1460 | { |
| 1461 | ifxusb_vbus2_status=0; |
| 1462 | } |
| 1463 | #endif //defined(__IS_VR9__) |
| 1464 | #endif //defined(__UEIP__) |
| 1465 | #if defined(__DO_OC_INT__) |
| 1466 | #if defined(__IS_AR10__) && defined(__IS_DUAL__) |
| 1467 | if(_core_if->core_no==0) |
| 1468 | ifxusb_oc_int_off(1); |
| 1469 | else |
| 1470 | ifxusb_oc_int_off(2); |
| 1471 | #else |
| 1472 | ifxusb_oc_int_off(); |
| 1473 | #endif |
| 1474 | #endif |
| 1475 | } |
| 1476 | |
| 1477 | |
| 1478 | /*! |
| 1479 | \fn int ifxusb_vbus(ifxusb_core_if_t *_core_if) |
| 1480 | \brief Read Current VBus status |
| 1481 | \param _core_if Pointer of core_if structure |
| 1482 | \ingroup IFXUSB_CIF |
| 1483 | */ |
| 1484 | int ifxusb_vbus(ifxusb_core_if_t *_core_if) |
| 1485 | { |
| 1486 | #if defined(__UEIP__) |
| 1487 | #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) |
| 1488 | return (ifxusb_vbus_status); |
| 1489 | #endif |
| 1490 | |
| 1491 | #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) |
| 1492 | if(_core_if->core_no==0) |
| 1493 | return (ifxusb_vbus1_status); |
| 1494 | #endif |
| 1495 | |
| 1496 | #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) |
| 1497 | if(_core_if->core_no==1) |
| 1498 | return (ifxusb_vbus2_status); |
| 1499 | #endif |
| 1500 | #else //defined(__UEIP__) |
| 1501 | #endif |
| 1502 | return -1; |
| 1503 | } |
| 1504 | |
| 1505 | #if defined(__UEIP__) |
| 1506 | #else |
| 1507 | #if defined(__IS_TWINPASS__) |
| 1508 | #define ADSL_BASE 0x20000 |
| 1509 | #define CRI_BASE 0x31F00 |
| 1510 | #define CRI_CCR0 CRI_BASE + 0x00 |
| 1511 | #define CRI_CCR1 CRI_BASE + 0x01*4 |
| 1512 | #define CRI_CDC0 CRI_BASE + 0x02*4 |
| 1513 | #define CRI_CDC1 CRI_BASE + 0x03*4 |
| 1514 | #define CRI_RST CRI_BASE + 0x04*4 |
| 1515 | #define CRI_MASK0 CRI_BASE + 0x05*4 |
| 1516 | #define CRI_MASK1 CRI_BASE + 0x06*4 |
| 1517 | #define CRI_MASK2 CRI_BASE + 0x07*4 |
| 1518 | #define CRI_STATUS0 CRI_BASE + 0x08*4 |
| 1519 | #define CRI_STATUS1 CRI_BASE + 0x09*4 |
| 1520 | #define CRI_STATUS2 CRI_BASE + 0x0A*4 |
| 1521 | #define CRI_AMASK0 CRI_BASE + 0x0B*4 |
| 1522 | #define CRI_AMASK1 CRI_BASE + 0x0C*4 |
| 1523 | #define CRI_UPDCTL CRI_BASE + 0x0D*4 |
| 1524 | #define CRI_MADST CRI_BASE + 0x0E*4 |
| 1525 | // 0x0f is missing |
| 1526 | #define CRI_EVENT0 CRI_BASE + 0x10*4 |
| 1527 | #define CRI_EVENT1 CRI_BASE + 0x11*4 |
| 1528 | #define CRI_EVENT2 CRI_BASE + 0x12*4 |
| 1529 | |
| 1530 | #define IRI_I_ENABLE 0x32000 |
| 1531 | #define STY_SMODE 0x3c004 |
| 1532 | #define AFE_TCR_0 0x3c0dc |
| 1533 | #define AFE_ADDR_ADDR 0x3c0e8 |
| 1534 | #define AFE_RDATA_ADDR 0x3c0ec |
| 1535 | #define AFE_WDATA_ADDR 0x3c0f0 |
| 1536 | #define AFE_CONFIG 0x3c0f4 |
| 1537 | #define AFE_SERIAL_CFG 0x3c0fc |
| 1538 | |
| 1539 | #define DFE_BASE_ADDR 0xBE116000 |
| 1540 | //#define DFE_BASE_ADDR 0x9E116000 |
| 1541 | |
| 1542 | #define MEI_FR_ARCINT_C (DFE_BASE_ADDR + 0x0000001C) |
| 1543 | #define MEI_DBG_WADDR_C (DFE_BASE_ADDR + 0x00000024) |
| 1544 | #define MEI_DBG_RADDR_C (DFE_BASE_ADDR + 0x00000028) |
| 1545 | #define MEI_DBG_DATA_C (DFE_BASE_ADDR + 0x0000002C) |
| 1546 | #define MEI_DBG_DECO_C (DFE_BASE_ADDR + 0x00000030) |
| 1547 | #define MEI_DBG_MASTER_C (DFE_BASE_ADDR + 0x0000003C) |
| 1548 | |
| 1549 | static void WriteARCmem(uint32_t addr, uint32_t data) |
| 1550 | { |
| 1551 | writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); |
| 1552 | writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); |
| 1553 | writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C ); |
| 1554 | writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C ); |
| 1555 | while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; |
| 1556 | writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); |
| 1557 | IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data); |
| 1558 | }; |
| 1559 | |
| 1560 | static uint32_t ReadARCmem(uint32_t addr) |
| 1561 | { |
| 1562 | u32 data; |
| 1563 | writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); |
| 1564 | writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); |
| 1565 | writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C ); |
| 1566 | while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; |
| 1567 | data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C ); |
| 1568 | writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); |
| 1569 | IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data); |
| 1570 | return data; |
| 1571 | }; |
| 1572 | |
| 1573 | void ifxusb_enable_afe_oc(void) |
| 1574 | { |
| 1575 | /* Start the clock */ |
| 1576 | WriteARCmem(CRI_UPDCTL ,0x00000008); |
| 1577 | WriteARCmem(CRI_CCR0 ,0x00000014); |
| 1578 | WriteARCmem(CRI_CCR1 ,0x00000500); |
| 1579 | WriteARCmem(AFE_CONFIG ,0x000001c8); |
| 1580 | WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge |
| 1581 | WriteARCmem(AFE_TCR_0 ,0x00000002); |
| 1582 | //Take afe out of reset |
| 1583 | WriteARCmem(AFE_CONFIG ,0x000000c0); |
| 1584 | WriteARCmem(IRI_I_ENABLE ,0x00000101); |
| 1585 | WriteARCmem(STY_SMODE ,0x00001980); |
| 1586 | |
| 1587 | ReadARCmem(CRI_UPDCTL ); |
| 1588 | ReadARCmem(CRI_CCR0 ); |
| 1589 | ReadARCmem(CRI_CCR1 ); |
| 1590 | ReadARCmem(AFE_CONFIG ); |
| 1591 | ReadARCmem(AFE_SERIAL_CFG); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge |
| 1592 | ReadARCmem(AFE_TCR_0 ); |
| 1593 | ReadARCmem(AFE_CONFIG ); |
| 1594 | ReadARCmem(IRI_I_ENABLE ); |
| 1595 | ReadARCmem(STY_SMODE ); |
| 1596 | } |
| 1597 | #endif //defined(__IS_TWINPASS__) |
| 1598 | #endif //defined(__UEIP__) |
| 1599 | |
| 1600 | |
