Root/package/platform/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_adsl.h

1/******************************************************************************
2**
3** FILE NAME : ifxmips_ptm_fw_regs_adsl.h
4** PROJECT : UEIP
5** MODULES : PTM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : PTM driver header file (firmware register for ADSL)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26#ifndef IFXMIPS_PTM_FW_REGS_ADSL_H
27#define IFXMIPS_PTM_FW_REGS_ADSL_H
28
29
30
31#if defined(CONFIG_DANUBE)
32  #include "ifxmips_ptm_fw_regs_danube.h"
33#elif defined(CONFIG_AMAZON_SE)
34  #include "ifxmips_ptm_fw_regs_amazon_se.h"
35#elif defined(CONFIG_AR9)
36  #include "ifxmips_ptm_fw_regs_ar9.h"
37#elif defined(CONFIG_VR9)
38  #error VR9 is not ADSL PTM mode!
39#else
40  #error Platform is not specified!
41#endif
42
43
44
45/*
46 * MIB Table Maintained by Firmware
47 */
48
49struct wan_mib_table {
50    unsigned int wrx_correct_pdu; /* 0 */
51    unsigned int wrx_correct_pdu_bytes; /* 1 */
52    unsigned int wrx_tccrc_err_pdu; /* 2 */
53    unsigned int wrx_tccrc_err_pdu_bytes; /* 3 */
54    unsigned int wrx_ethcrc_err_pdu; /* 4 */
55    unsigned int wrx_ethcrc_err_pdu_bytes; /* 5 */
56    unsigned int wrx_nodesc_drop_pdu; /* 6 */
57    unsigned int wrx_len_violation_drop_pdu; /* 7 */
58    unsigned int wrx_idle_bytes; /* 8 */
59    unsigned int wrx_nonidle_cw; /* 9 */
60    unsigned int wrx_idle_cw; /* A */
61    unsigned int wrx_err_cw; /* B */
62    unsigned int wtx_total_pdu; /* C */
63    unsigned int wtx_total_bytes; /* D */
64    unsigned int res0; /* E */
65    unsigned int res1; /* F */
66};
67
68
69/*
70 * Host-PPE Communication Data Structure
71 */
72
73#if defined(__BIG_ENDIAN)
74
75  struct fw_ver_id {
76    unsigned int family :4;
77    unsigned int fwtype :4;
78    unsigned int interface :4;
79    unsigned int fwmode :4;
80    unsigned int major :8;
81    unsigned int minor :8;
82  };
83
84  struct wrx_port_cfg_status {
85    /* 0h */
86    unsigned int mfs :16;
87    unsigned int res0 :12;
88    unsigned int dmach :3;
89    unsigned int res1 :1;
90
91    /* 1h */
92    unsigned int res2 :14;
93    unsigned int local_state :2; // init with 0, written by firmware only
94    unsigned int res3 :15;
95    unsigned int partner_state :1; // init with 0, written by firmware only
96
97  };
98
99  struct wrx_dma_channel_config {
100    /* 0h */
101    unsigned int res3 :1;
102    unsigned int res4 :2;
103    unsigned int res5 :1;
104    unsigned int desba :28;
105    /* 1h */
106    unsigned int res1 :16;
107    unsigned int res2 :16;
108    /* 2h */
109    unsigned int deslen :16;
110    unsigned int vlddes :16;
111  };
112
113  struct wtx_port_cfg {
114    /* 0h */
115    unsigned int tx_cwth2 :8;
116    unsigned int tx_cwth1 :8;
117    unsigned int res0 :16;
118  };
119
120  struct wtx_dma_channel_config {
121    /* 0h */
122    unsigned int res3 :1;
123    unsigned int res4 :2;
124    unsigned int res5 :1;
125    unsigned int desba :28;
126
127    /* 1h */
128    unsigned int res1 :16;
129    unsigned int res2 :16;
130
131    /* 2h */
132    unsigned int deslen :16;
133    unsigned int vlddes :16;
134  };
135
136  struct eth_efmtc_crc_cfg {
137    /* 0h */
138    unsigned int res0 :6;
139    unsigned int tx_eth_crc_gen :1;
140    unsigned int tx_tc_crc_gen :1;
141    unsigned int tx_tc_crc_len :8;
142    unsigned int res1 :5;
143    unsigned int rx_eth_crc_present :1;
144    unsigned int rx_eth_crc_check :1;
145    unsigned int rx_tc_crc_check :1;
146    unsigned int rx_tc_crc_len :8;
147  };
148
149  /* DMA descriptor */
150  struct rx_descriptor {
151    /* 0 - 3h */
152    unsigned int own :1;
153    unsigned int c :1;
154    unsigned int sop :1;
155    unsigned int eop :1;
156    unsigned int res1 :3;
157    unsigned int byteoff :2;
158    unsigned int res2 :2;
159    unsigned int id :4;
160    unsigned int err :1;
161    unsigned int datalen :16;
162    /* 4 - 7h */
163    unsigned int res3 :4;
164    unsigned int dataptr :28;
165  };
166
167  struct tx_descriptor {
168    /* 0 - 3h */
169    unsigned int own :1;
170    unsigned int c :1;
171    unsigned int sop :1;
172    unsigned int eop :1;
173    unsigned int byteoff :5;
174    unsigned int res1 :5;
175    unsigned int iscell :1;
176    unsigned int clp :1;
177    unsigned int datalen :16;
178    /* 4 - 7h */
179    unsigned int res2 :4;
180    unsigned int dataptr :28;
181  };
182
183#else /* defined(__BIG_ENDIAN) */
184
185  struct wrx_port_cfg_status {
186    /* 0h */
187    unsigned int res1 :1;
188    unsigned int dmach :3;
189    unsigned int res0 :12;
190    unsigned int mfs :16;
191
192    /* 1h */
193    unsigned int partner_state :1;
194    unsigned int res3 :15;
195    unsigned int local_state :2;
196    unsigned int res2 :14;
197  };
198
199  struct wrx_dma_channel_config {
200    /* 0h */
201    unsigned int desba :28;
202    unsigned int res5 :1;
203    unsigned int res4 :2;
204    unsigned int res3 :1;
205    /* 1h */
206    unsigned int res2 :16;
207    unsigned int res1 :16;
208    /* 2h */
209    unsigned int vlddes :16;
210    unsigned int deslen :16;
211  };
212
213  struct wtx_port_cfg {
214    /* 0h */
215    unsigned int res0 :16;
216    unsigned int tx_cwth1 :8;
217    unsigned int tx_cwth2 :8;
218  };
219
220  struct wtx_dma_channel_config {
221    /* 0h */
222    unsigned int desba :28;
223    unsigned int res5 :1;
224    unsigned int res4 :2;
225    unsigned int res3 :1;
226    /* 1h */
227    unsigned int res2 :16;
228    unsigned int res1 :16;
229    /* 2h */
230    unsigned int vlddes :16;
231    unsigned int deslen :16;
232  };
233
234  struct eth_efmtc_crc_cfg {
235    /* 0h */
236    unsigned int rx_tc_crc_len :8;
237    unsigned int rx_tc_crc_check :1;
238    unsigned int rx_eth_crc_check :1;
239    unsigned int rx_eth_crc_present :1;
240    unsigned int res1 :5;
241    unsigned int tx_tc_crc_len :8;
242    unsigned int tx_tc_crc_gen :1;
243    unsigned int tx_eth_crc_gen :1;
244    unsigned int res0 :6;
245  };
246
247  /* DMA descriptor */
248  struct rx_descriptor {
249    /* 4 - 7h */
250    unsigned int dataptr :28;
251    unsigned int res3 :4;
252    /* 0 - 3h */
253    unsigned int datalen :16;
254    unsigned int err :1;
255    unsigned int id :4;
256    unsigned int res2 :2;
257    unsigned int byteoff :2;
258    unsigned int res1 :3;
259    unsigned int eop :1;
260    unsigned int sop :1;
261    unsigned int c :1;
262    unsigned int own :1;
263  };
264
265  struct tx_descriptor {
266    /* 4 - 7h */
267    unsigned int dataptr :28;
268    unsigned int res2 :4;
269    /* 0 - 3h */
270    unsigned int datalen :16;
271    unsigned int clp :1;
272    unsigned int iscell :1;
273    unsigned int res1 :5;
274    unsigned int byteoff :5;
275    unsigned int eop :1;
276    unsigned int sop :1;
277    unsigned int c :1;
278    unsigned int own :1;
279  };
280#endif /* defined(__BIG_ENDIAN) */
281
282
283
284#endif // IFXMIPS_PTM_FW_REGS_ADSL_H
285

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