| 1 | /****************************************************************************** |
| 2 | ** |
| 3 | ** FILE NAME : ifxmips_ptm_fw_regs_vdsl.h |
| 4 | ** PROJECT : UEIP |
| 5 | ** MODULES : PTM |
| 6 | ** |
| 7 | ** DATE : 7 Jul 2009 |
| 8 | ** AUTHOR : Xu Liang |
| 9 | ** DESCRIPTION : PTM driver header file (firmware register for VDSL) |
| 10 | ** COPYRIGHT : Copyright (c) 2006 |
| 11 | ** Infineon Technologies AG |
| 12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
| 13 | ** |
| 14 | ** This program is free software; you can redistribute it and/or modify |
| 15 | ** it under the terms of the GNU General Public License as published by |
| 16 | ** the Free Software Foundation; either version 2 of the License, or |
| 17 | ** (at your option) any later version. |
| 18 | ** |
| 19 | ** HISTORY |
| 20 | ** $Date $Author $Comment |
| 21 | ** 07 JUL 2009 Xu Liang Init Version |
| 22 | *******************************************************************************/ |
| 23 | |
| 24 | |
| 25 | |
| 26 | #ifndef IFXMIPS_PTM_FW_REGS_VDSL_H |
| 27 | #define IFXMIPS_PTM_FW_REGS_VDSL_H |
| 28 | |
| 29 | |
| 30 | |
| 31 | #if defined(CONFIG_DANUBE) |
| 32 | #error Danube is not VDSL PTM mode! |
| 33 | #elif defined(CONFIG_AMAZON_SE) |
| 34 | #error Amazon-SE is not VDSL PTM mode! |
| 35 | #elif defined(CONFIG_AR9) |
| 36 | #error AR9 is not VDSL PTM mode! |
| 37 | #elif defined(CONFIG_VR9) |
| 38 | #include "ifxmips_ptm_fw_regs_vr9.h" |
| 39 | #else |
| 40 | #error Platform is not specified! |
| 41 | #endif |
| 42 | |
| 43 | |
| 44 | |
| 45 | /* |
| 46 | * MIB Table Maintained by Firmware |
| 47 | */ |
| 48 | |
| 49 | struct wan_rx_mib_table { |
| 50 | unsigned int res1[2]; |
| 51 | unsigned int wrx_dropdes_pdu; |
| 52 | unsigned int wrx_total_bytes; |
| 53 | unsigned int res2[4]; |
| 54 | // wrx_total_pdu is implemented with hardware counter (not used by PTM TC) |
| 55 | // check register "TC_RX_MIB_CMD" |
| 56 | // "HEC_INC" used to increase preemption Gamma interface (wrx_total_pdu) |
| 57 | // "AIIDLE_INC" used to increase normal Gamma interface (wrx_total_pdu) |
| 58 | }; |
| 59 | |
| 60 | struct wan_tx_mib_table { |
| 61 | //unsigned int wtx_total_pdu; // version before 0.26 |
| 62 | //unsigned int small_pkt_drop_cnt; |
| 63 | //unsigned int total_pkt_drop_cnt; |
| 64 | unsigned int wrx_total_pdu; // version 0.26 and onwards |
| 65 | unsigned int wrx_total_bytes; |
| 66 | unsigned int wtx_total_pdu; |
| 67 | unsigned int wtx_total_bytes; |
| 68 | |
| 69 | unsigned int wtx_cpu_dropsmall_pdu; |
| 70 | unsigned int wtx_cpu_dropdes_pdu; |
| 71 | unsigned int wtx_fast_dropsmall_pdu; |
| 72 | unsigned int wtx_fast_dropdes_pdu; |
| 73 | }; |
| 74 | |
| 75 | |
| 76 | /* |
| 77 | * Host-PPE Communication Data Structure |
| 78 | */ |
| 79 | |
| 80 | #if defined(__BIG_ENDIAN) |
| 81 | |
| 82 | struct fw_ver_id { |
| 83 | unsigned int family :4; |
| 84 | unsigned int fwtype :4; |
| 85 | unsigned int interface :4; |
| 86 | unsigned int fwmode :4; |
| 87 | unsigned int major :8; |
| 88 | unsigned int minor :8; |
| 89 | }; |
| 90 | |
| 91 | struct cfg_std_data_len { |
| 92 | unsigned int res1 :14; |
| 93 | unsigned int byte_off :2; // byte offset in RX DMA channel |
| 94 | unsigned int data_len :16; // data length for standard size packet buffer |
| 95 | }; |
| 96 | |
| 97 | struct tx_qos_cfg { |
| 98 | unsigned int time_tick :16; // number of PP32 cycles per basic time tick |
| 99 | unsigned int overhd_bytes :8; // number of overhead bytes per packet in rate shaping |
| 100 | unsigned int eth1_eg_qnum :4; // number of egress QoS queues (< 8); |
| 101 | unsigned int eth1_burst_chk :1; // always 1, more accurate WFQ |
| 102 | unsigned int eth1_qss :1; // 1: FW QoS, 0: HW QoS |
| 103 | unsigned int shape_en :1; // 1: enable rate shaping, 0: disable |
| 104 | unsigned int wfq_en :1; // 1: WFQ enabled, 0: strict priority enabled |
| 105 | }; |
| 106 | |
| 107 | struct psave_cfg { |
| 108 | unsigned int res1 :15; |
| 109 | unsigned int start_state :1; // 1: start from partial PPE reset, 0: start from full PPE reset |
| 110 | unsigned int res2 :15; |
| 111 | unsigned int sleep_en :1; // 1: enable sleep mode, 0: disable sleep mode |
| 112 | }; |
| 113 | |
| 114 | struct eg_bwctrl_cfg { |
| 115 | unsigned int fdesc_wm :16; // if free descriptors in QoS/Swap channel is less than this watermark, large size packets are discarded |
| 116 | unsigned int class_len :16; // if packet length is not less than this value, the packet is recognized as large packet |
| 117 | }; |
| 118 | |
| 119 | struct test_mode { |
| 120 | unsigned int res1 :30; |
| 121 | unsigned int mib_clear_mode :1; // 1: MIB counter is cleared with TPS-TC software reset, 0: MIB counter not cleared |
| 122 | unsigned int test_mode :1; // 1: test mode, 0: normal mode |
| 123 | }; |
| 124 | |
| 125 | struct gpio_mode { |
| 126 | unsigned int res1 :3; |
| 127 | unsigned int gpio_bit_bc1 :5; |
| 128 | unsigned int res2 :3; |
| 129 | unsigned int gpio_bit_bc0 :5; |
| 130 | |
| 131 | unsigned int res3 :7; |
| 132 | unsigned int gpio_bc1_en :1; |
| 133 | |
| 134 | unsigned int res4 :7; |
| 135 | unsigned int gpio_bc0_en :1; |
| 136 | }; |
| 137 | |
| 138 | struct gpio_wm_cfg { |
| 139 | unsigned int stop_wm_bc1 :8; |
| 140 | unsigned int start_wm_bc1 :8; |
| 141 | unsigned int stop_wm_bc0 :8; |
| 142 | unsigned int start_wm_bc0 :8; |
| 143 | }; |
| 144 | |
| 145 | struct rx_bc_cfg { |
| 146 | unsigned int res1 :14; |
| 147 | unsigned int local_state :2; // 0: local receiver is "Looking", 1: local receiver is "Freewheel Sync False", 2: local receiver is "Synced", 3: local receiver is "Freewheel Sync Truee" |
| 148 | unsigned int res2 :15; |
| 149 | unsigned int remote_state :1; // 0: remote receiver is "Out-of-Sync", 1: remote receiver is "Synced" |
| 150 | unsigned int to_false_th :16; // the number of consecutive "Miss Sync" for leaving "Freewheel Sync False" to "Looking" (default 3) |
| 151 | unsigned int to_looking_th :16; // the number of consecutive "Miss Sync" for leaving "Freewheel Sync True" to "Freewheel Sync False" (default 7) |
| 152 | unsigned int res_word[30]; |
| 153 | }; |
| 154 | |
| 155 | struct rx_gamma_itf_cfg { |
| 156 | unsigned int res1 :31; |
| 157 | unsigned int receive_state :1; // 0: "Out-of-Fragment", 1: "In-Fragment" |
| 158 | unsigned int res2 :16; |
| 159 | unsigned int rx_min_len :8; // min length of packet, padding if packet length is smaller than this value |
| 160 | unsigned int rx_pad_en :1; // 0: padding disabled, 1: padding enabled |
| 161 | unsigned int res3 :2; |
| 162 | unsigned int rx_eth_fcs_ver_dis :1; // 0: ETH FCS verification is enabled, 1: disabled |
| 163 | unsigned int rx_rm_eth_fcs :1; // 0: ETH FCS field is not removed, 1: ETH FCS field is removed |
| 164 | unsigned int rx_tc_crc_ver_dis :1; // 0: TC CRC verification enabled, 1: disabled |
| 165 | unsigned int rx_tc_crc_size :2; // 0: 0-bit, 1: 16-bit, 2: 32-bit |
| 166 | unsigned int rx_eth_fcs_result; // if the ETH FCS result matches this magic number, then the packet is valid packet |
| 167 | unsigned int rx_tc_crc_result; // if the TC CRC result matches this magic number, then the packet is valid packet |
| 168 | unsigned int rx_crc_cfg :16; // TC CRC config, please check the description of SAR context data structure in the hardware spec |
| 169 | unsigned int res4 :16; |
| 170 | unsigned int rx_eth_fcs_init_value; // ETH FCS initialization value |
| 171 | unsigned int rx_tc_crc_init_value; // TC CRC initialization value |
| 172 | unsigned int res_word1; |
| 173 | unsigned int rx_max_len_sel :1; // 0: normal, the max length is given by MAX_LEN_NORMAL, 1: fragment, the max length is given by MAX_LEN_FRAG |
| 174 | unsigned int res5 :2; |
| 175 | unsigned int rx_edit_num2 :4; // number of bytes to be inserted/removed |
| 176 | unsigned int rx_edit_pos2 :7; // first byte position to be edited |
| 177 | unsigned int rx_edit_type2 :1; // 0: remove, 1: insert |
| 178 | unsigned int rx_edit_en2 :1; // 0: disable insertion or removal of data, 1: enable |
| 179 | unsigned int res6 :3; |
| 180 | unsigned int rx_edit_num1 :4; // number of bytes to be inserted/removed |
| 181 | unsigned int rx_edit_pos1 :7; // first byte position to be edited |
| 182 | unsigned int rx_edit_type1 :1; // 0: remove, 1: insert |
| 183 | unsigned int rx_edit_en1 :1; // 0: disable insertion or removal of data, 1: enable |
| 184 | unsigned int res_word2[2]; |
| 185 | unsigned int rx_inserted_bytes_1l; |
| 186 | unsigned int rx_inserted_bytes_1h; |
| 187 | unsigned int rx_inserted_bytes_2l; |
| 188 | unsigned int rx_inserted_bytes_2h; |
| 189 | int rx_len_adj; // the packet length adjustment, it is sign integer |
| 190 | unsigned int res_word3[16]; |
| 191 | }; |
| 192 | |
| 193 | struct tx_bc_cfg { |
| 194 | unsigned int fill_wm :16; // default 2 |
| 195 | unsigned int uflw_wm :16; // default 2 |
| 196 | unsigned int res_word[31]; |
| 197 | }; |
| 198 | |
| 199 | struct tx_gamma_itf_cfg { |
| 200 | unsigned int res_word1; |
| 201 | unsigned int res1 :8; |
| 202 | unsigned int tx_len_adj :4; // 4 * (not TX_ETH_FCS_GEN_DIS) + TX_TC_CRC_SIZE |
| 203 | unsigned int tx_crc_off_adj :4; // 4 + TX_TC_CRC_SIZE |
| 204 | unsigned int tx_min_len :8; // min length of packet, if length is less than this value, packet is padded |
| 205 | unsigned int res2 :3; |
| 206 | unsigned int tx_eth_fcs_gen_dis :1; // 0: ETH FCS generation enabled, 1: disabled |
| 207 | unsigned int res3 :2; |
| 208 | unsigned int tx_tc_crc_size :2; // 0: 0-bit, 1: 16-bit, 2: 32-bit |
| 209 | unsigned int res4 :24; |
| 210 | unsigned int queue_mapping :8; // TX queue attached to this Gamma interface |
| 211 | unsigned int res_word2; |
| 212 | unsigned int tx_crc_cfg :16; // TC CRC config, please check the description of SAR context data structure in the hardware spec |
| 213 | unsigned int res5 :16; |
| 214 | unsigned int tx_eth_fcs_init_value; // ETH FCS initialization value |
| 215 | unsigned int tx_tc_crc_init_value; // TC CRC initialization value |
| 216 | unsigned int res_word3[25]; |
| 217 | }; |
| 218 | |
| 219 | struct wtx_qos_q_desc_cfg { |
| 220 | unsigned int threshold :8; |
| 221 | unsigned int length :8; |
| 222 | unsigned int addr :16; |
| 223 | unsigned int rd_ptr :16; |
| 224 | unsigned int wr_ptr :16; |
| 225 | }; |
| 226 | |
| 227 | struct wtx_eg_q_shaping_cfg { |
| 228 | unsigned int t :8; |
| 229 | unsigned int w :24; |
| 230 | unsigned int s :16; |
| 231 | unsigned int r :16; |
| 232 | unsigned int res1 :8; |
| 233 | unsigned int d :24; // ppe internal variable |
| 234 | unsigned int res2 :8; |
| 235 | unsigned int tick_cnt :8; // ppe internal variable |
| 236 | unsigned int b :16; // ppe internal variable |
| 237 | }; |
| 238 | |
| 239 | /* DMA descriptor */ |
| 240 | struct rx_descriptor { |
| 241 | /* 0 - 3h */ |
| 242 | unsigned int own :1; // 0: Central DMA TX or MIPS, 1: PPE |
| 243 | unsigned int c :1; // PPE tells current descriptor is complete |
| 244 | unsigned int sop :1; |
| 245 | unsigned int eop :1; |
| 246 | unsigned int res1 :3; |
| 247 | unsigned int byteoff :2; |
| 248 | unsigned int res2 :7; |
| 249 | unsigned int datalen :16; |
| 250 | /* 4 - 7h */ |
| 251 | unsigned int res3 :4; |
| 252 | unsigned int dataptr :28; // byte address |
| 253 | }; |
| 254 | |
| 255 | struct tx_descriptor { |
| 256 | /* 0 - 3h */ |
| 257 | unsigned int own :1; // CPU path - 0: MIPS, 1: PPE Dispatcher, Fastpath - 0: PPE Dispatcher, 1: Central DMA, QoS Queue - 0: PPE Dispatcher, 1: PPE DMA, SWAP Channel - 0: MIPS, 1: PPE Dispatcher |
| 258 | unsigned int c :1; // MIPS or central DMA tells PPE the current descriptor is complete |
| 259 | unsigned int sop :1; |
| 260 | unsigned int eop :1; |
| 261 | unsigned int byteoff :5; |
| 262 | unsigned int qid :4; // TX Queue ID, bit 3 is reserved |
| 263 | unsigned int res1 :3; |
| 264 | unsigned int datalen :16; |
| 265 | /* 4 - 7h */ |
| 266 | unsigned int small :1; // 0: standard size, 1: less than standard size |
| 267 | unsigned int res2 :3; |
| 268 | unsigned int dataptr :28; // byte address |
| 269 | }; |
| 270 | |
| 271 | #else /* defined(__BIG_ENDIAN) */ |
| 272 | #error structures are defined in big endian |
| 273 | #endif /* defined(__BIG_ENDIAN) */ |
| 274 | |
| 275 | |
| 276 | |
| 277 | #endif // IFXMIPS_PTM_FW_REGS_VDSL_H |
| 278 | |
| 279 | |
