package/platform/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h - OpenWrt XBurst Git Source Tree - development environment for Qi Hardware device.

1

/******************************************************************************

2

**

3

** FILE NAME : ifxmips_ptm_ppe_danube.h

** PROJECT : UEIP

** MODULES : PTM

**

** DATE : 7 Jul 2009

** AUTHOR : Xu Liang

** DESCRIPTION : PTM driver header file (PPE register for Danube)

10

11

** Infineon Technologies AG

12

** Am Campeon 1-12, 85579 Neubiberg, Germany

13

**

14

** This program is free software; you can redistribute it and/or modify

15

** it under the terms of the GNU General Public License as published by

16

** the Free Software Foundation; either version 2 of the License, or

17

** (at your option) any later version.

18

**

19

** HISTORY

20

** $Date $Author $Comment

21

** 07 JUL 2009 Xu Liang Init Version

22

*******************************************************************************/

#ifndef IFXMIPS_PTM_PPE_DANUBE_H

27

#define IFXMIPS_PTM_PPE_DANUBE_H

/*

* FPI Configuration Bus Register and Memory Address Mapping

33

*/

34

#define IFX_PPE (KSEG1 | 0x1E180000)

35

#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))

36

#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))

37

#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))

38

#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))

39

#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))

40

#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))

41

#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))

42

#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))

43

#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))

44

#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))

45

#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))

46

#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))

47

#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))

48

#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))

49

#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))

50

#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))

51

52

/*

53

* DWORD-Length of Memory Blocks

54

*/

55

#define PP32_DEBUG_REG_DWLEN 0x0030

56

#define PPM_INT_REG_DWLEN 0x0010

57

#define PP32_INTERNAL_RES_DWLEN 0x00C0

58

#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)

59

#define PPE_REG_DWLEN 0x1000

60

#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)

61

#define PPM_INT_UNIT_DWLEN 0x0100

62

#define PPM_TIMER0_DWLEN 0x0100

63

#define PPM_TASK_IND_REG_DWLEN 0x0100

64

#define PPS_BRK_DWLEN 0x0100

65

#define PPM_TIMER1_DWLEN 0x0100

66

#define SB_RAM0_DWLEN 0x0400

67

#define SB_RAM1_DWLEN 0x0800

68

#define SB_RAM2_DWLEN 0x0A00

69

#define SB_RAM3_DWLEN 0x0400

70

#define QSB_CONF_REG_DWLEN 0x0100

71

72

/*

73

* PP32 to FPI Address Mapping

74

*/

75

#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \

76

(((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \

77

(((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \

78

(((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \

0))

/*

* PP32 Debug Control Register

83

*/

84

#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000)

85

86

#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0)

87

#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0)

88

#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0)

89

90

#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001)

91

92

#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002)

93

#define PP32_BRK_SRC_PC(i) (1 << (i))

94

#define PP32_BRK_SRC_DATA(i, cmd) ((cmd) << ((i) * 3 + 8))

95

96

#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))

97

#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))

98

#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))

99

#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i))

100

#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i))

101

102

#define PP32_DBG_TASK_GPR(task, i) PP32_DEBUG_REG_ADDR(0, 0x0040 + (task) * 0x0010 + (i))

103

104

#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080)

105

#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081)

106

#define PP32_DBG_TASK_PRIO PP32_DEBUG_REG_ADDR(0, 0x0086)

107

#define PP32_DBG_PC_OF_TASK(i) PP32_DEBUG_REG_ADDR(0, 0x0087 + (i))

108

109

/*

110

* Share Buffer Registers

111

*/

112

#define SB_MST_SEL PPE_REG_ADDR(0x0304)

/*

* EMA Registers

*/

#define EMA_CMDCFG PPE_REG_ADDR(0x0A00)

118

#define EMA_DATACFG PPE_REG_ADDR(0x0A01)

119

#define EMA_CMDCNT PPE_REG_ADDR(0x0A02)

120

#define EMA_DATACNT PPE_REG_ADDR(0x0A03)

121

#define EMA_ISR PPE_REG_ADDR(0x0A04)

122

#define EMA_IER PPE_REG_ADDR(0x0A05)

123

#define EMA_CFG PPE_REG_ADDR(0x0A06)

124

#define EMA_SUBID PPE_REG_ADDR(0x0A07)

125

126

#define EMA_ALIGNMENT 4

127

128

/*

129

* Mailbox IGU1 Interrupt

130

*/

131

#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24

#endif // IFXMIPS_PTM_PPE_DANUBE_H

136

OpenWrt XBurst

OpenWrt XBurst Git Source Tree

Root/package/platform/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h

interactive